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Merge pull request #17 from timmy61109/feature/timmy61109/CH5-1
如果採用，此拉請求將完成5-1實習課程
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‎CH5/CH5-1/4bit_adder.bdf‎

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‎CH5/CH5-1/4bit_adder.bsf‎

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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus II License Agreement,
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the Altera MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Altera and sold by Altera or its
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authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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(header "symbol" (version "1.2"))
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(symbol
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(rect 16 16 112 208)
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(text "4bit_adder" (rect 5 0 67 12)(font "Arial" (font_size 8)))
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(text "inst" (rect 8 178 25 188)(font "Arial" ))
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‎CH5/CH5-1/4bit_adder.qpf‎

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, the Altera Quartus II License Agreement,
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# the Altera MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Altera and sold by Altera or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 15.0.2 Build 153 07/15/2015 SJ Web Edition
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# Date created = 20:46:18 August 15, 2019
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "15.0"
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DATE = "20:46:18 August 15, 2019"
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# Revisions
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PROJECT_REVISION = "4bit_adder"

‎CH5/CH5-1/4bit_adder.qsf‎

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
9+
# to the terms and conditions of the Altera Program License
10+
# Subscription Agreement, the Altera Quartus II License Agreement,
11+
# the Altera MegaCore Function License Agreement, or other
12+
# applicable license agreement, including, without limitation,
13+
# that your use is for the sole purpose of programming logic
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# devices manufactured by Altera and sold by Altera or its
15+
# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 15.0.2 Build 153 07/15/2015 SJ Web Edition
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# Date created = 20:46:18 August 15, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# 4bit_adder_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CSXFC6D6F31C8
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set_global_assignment -name TOP_LEVEL_ENTITY 4bit_adder
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.2
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:46:18 AUGUST 15, 2019"
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set_global_assignment -name LAST_QUARTUS_VERSION 15.0.2
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name BDF_FILE 4bit_adder.bdf
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VECTOR_WAVEFORM_FILE 4bit_adder.vwf
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_location_assignment PIN_W25 -to A1
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set_location_assignment PIN_V25 -to A2
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set_location_assignment PIN_AC28 -to A3
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set_location_assignment PIN_AC29 -to A4
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

‎CH5/CH5-1/4bit_adder.qws‎

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