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如果採用，此提交將新增JK正反器的組合邏輯電路與模擬測試檔
修改項目: 模組: 議題57
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‎Digital_Logic_Practice/CH7/CH7-2/JK_FF.bdf‎

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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus II License Agreement,
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the Altera MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Altera and sold by Altera or its
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authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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