1+ # -------------------------------------------------------------------------- #
2+ #
3+ # Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
4+ # Your use of Altera Corporation's design tools, logic functions
5+ # and other software and tools, and its AMPP partner logic
6+ # functions, and any output files from any of the foregoing
7+ # (including device programming or simulation files), and any
8+ # associated documentation or information are expressly subject
9+ # to the terms and conditions of the Altera Program License
10+ # Subscription Agreement, the Altera Quartus II License Agreement,
11+ # the Altera MegaCore Function License Agreement, or other
12+ # applicable license agreement, including, without limitation,
13+ # that your use is for the sole purpose of programming logic
14+ # devices manufactured by Altera and sold by Altera or its
15+ # authorized distributors. Please refer to the applicable
16+ # agreement for further details.
17+ #
18+ # -------------------------------------------------------------------------- #
19+ #
20+ # Quartus II 64-Bit
21+ # Version 15.0.2 Build 153 07/15/2015 SJ Web Edition
22+ # Date created = 14:48:53 十二月 17, 2020
23+ #
24+ # -------------------------------------------------------------------------- #
25+ #
26+ # Notes:
27+ #
28+ # 1) The default values for assignments are stored in the file:
29+ # JK_FF_D_FF_T_FF_assignment_defaults.qdf
30+ # If this file doesn't exist, see file:
31+ # assignment_defaults.qdf
32+ #
33+ # 2) Altera recommends that you do not modify this file. This
34+ # file is updated automatically by the Quartus II software
35+ # and any changes you make may be lost or overwritten.
36+ #
37+ # -------------------------------------------------------------------------- #
38+
39+
40+ set_global_assignment -name FAMILY "Cyclone V"
41+ set_global_assignment -name DEVICE 5CGXFC7C7F23C8
42+ set_global_assignment -name TOP_LEVEL_ENTITY JK_FF
43+ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.2
44+ set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:48:53 十二月 17, 2020"
45+ set_global_assignment -name LAST_QUARTUS_VERSION 15.0.2
46+ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
47+ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
48+ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
49+ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
50+ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
51+ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
52+ set_global_assignment -name BDF_FILE JK_FF.bdf
53+ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
54+ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
55+ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
56+ set_global_assignment -name BDF_FILE D_FF.bdf
57+ set_global_assignment -name VECTOR_WAVEFORM_FILE JK_FF.vwf
58+ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
59+ set_global_assignment -name BDF_FILE T_FF.bdf
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