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如果採用，此提交將更新目錄名稱
修改項目: 模組: 議題
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Verilog_Digital_Logic_Design_Practice/CH2/and_gate.qpf renamed to VerilogHDL_Practice/CH2/and_gate.qpf

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Verilog_Digital_Logic_Design_Practice/CH2/and_gate.qsf renamed to VerilogHDL_Practice/CH2/and_gate.qsf

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Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/gui_handlers.wdf renamed to VerilogHDL_Practice/CH2/and_gate/and_gate.cache/wt/gui_handlers.wdf

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Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/java_command_handlers.wdf renamed to VerilogHDL_Practice/CH2/and_gate/and_gate.cache/wt/java_command_handlers.wdf

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Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/project.wpc renamed to VerilogHDL_Practice/CH2/and_gate/and_gate.cache/wt/project.wpc

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Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/synthesis.wdf renamed to VerilogHDL_Practice/CH2/and_gate/and_gate.cache/wt/synthesis.wdf

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Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/synthesis_details.wdf renamed to VerilogHDL_Practice/CH2/and_gate/and_gate.cache/wt/synthesis_details.wdf

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Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/webtalk_pa.xml renamed to VerilogHDL_Practice/CH2/and_gate/and_gate.cache/wt/webtalk_pa.xml

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Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/xsim.wdf renamed to VerilogHDL_Practice/CH2/and_gate/and_gate.cache/wt/xsim.wdf

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Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.hw/and_gate.lpr renamed to VerilogHDL_Practice/CH2/and_gate/and_gate.hw/and_gate.lpr

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