如果採用，此提交將新增一位元全加法器

修改項目:

模組:

議題

Author: timmy61109

Verilog_Digital_Logic_Design_Practice/CH3/full_add_one.v

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+module full_add_one (A, B, Ci, Co, S);
+
+input A, B, Ci;
+output Co, S;
+wire AB, ACi, BCi;
+
+and (AB, A, B);
+and (ACi, A, Ci);
+and (BCi, B, Ci);
+or (Co, AB, ACi, BCi);
+xor (S, A, B, Ci);
+
+endmodule // full_add_one

Verilog_Digital_Logic_Design_Practice/CH3/full_add_one_test.v

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+module full_add_one_test ();
+`timescale 1ns / 1ps
+
+reg A = 0'b0;
+reg B = 0'b0;
+reg Ci = 0'b0;
+
+wire Co, S;
+
+full_add_one UUT (.A(A), .B(B), .Ci(Ci), .Co(Co), .S(S));
+
+initial begin
+  #100; A = 0'b0; B = 0'b0; Ci = 0'b1;
+  #100; A = 0'b0; B = 0'b1; Ci = 0'b0;
+  #100; A = 0'b0; B = 0'b1; Ci = 0'b1;
+  #100; A = 0'b1; B = 0'b0; Ci = 0'b0;
+  #100; A = 0'b1; B = 0'b0; Ci = 0'b1;
+  #100; A = 0'b1; B = 0'b1; Ci = 0'b0;
+  #100; A = 0'b1; B = 0'b1; Ci = 0'b1;
+
+end
+
+initial begin
+  #900;
+  $stop;
+
+end
+
+endmodule // full_add_one_test