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如果採用，此提交將新增第三章wire_and_or.v實作
修改項目: 模組: 議題
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‎Verilog_Digital_Logic_Design_Practice/CH3/wire_and_or.v‎

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module wire_and_or (A, B, C, D, E);
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input A, B;
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output C, D, E;
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wire A_NOT;
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wand D;
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wor E;
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//wire
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assign A_NOT = ~A;
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assign C = A_NOT & B; // C = ~AB
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// wire-and
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assign D = A;
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assign D = B;
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// wire-or
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assign E = A;
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assign E = B;
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endmodule // wire_and_or

‎Verilog_Digital_Logic_Design_Practice/CH3/wire_and_or/wire_and_or.cache/wt/gui_handlers.wdf‎

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‎Verilog_Digital_Logic_Design_Practice/CH3/wire_and_or/wire_and_or.cache/wt/java_command_handlers.wdf‎

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‎Verilog_Digital_Logic_Design_Practice/CH3/wire_and_or/wire_and_or.cache/wt/project.wpc‎

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‎Verilog_Digital_Logic_Design_Practice/CH3/wire_and_or/wire_and_or.cache/wt/synthesis.wdf‎

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‎Verilog_Digital_Logic_Design_Practice/CH3/wire_and_or/wire_and_or.cache/wt/synthesis_details.wdf‎

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version:1
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‎Verilog_Digital_Logic_Design_Practice/CH3/wire_and_or/wire_and_or.cache/wt/webtalk_pa.xml‎

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<?xml version="1.0" encoding="UTF-8" ?>
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<document>
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pa" timeStamp="Fri Oct 16 15:51:50 2020">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="fe4b558e683c401486a18ae878521f00" type="ProjectID"/>
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<property name="ProjectIteration" value="5" type="ProjectIteration"/>
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</section>
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<section name="PlanAhead Usage" visible="true">
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<item name="Project Data">
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<property name="SrcSetCount" value="1" type="SrcSetCount"/>
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<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
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<property name="DesignMode" value="RTL" type="DesignMode"/>
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<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
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<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
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</item>
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<item name="Java Command Handlers">
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<property name="AddSources" value="1" type="JavaHandler"/>
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<property name="NewProject" value="1" type="JavaHandler"/>
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<property name="OpenCheckpoint" value="1" type="JavaHandler"/>
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<property name="RunImplementation" value="4" type="JavaHandler"/>
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<property name="RunSchematic" value="2" type="JavaHandler"/>
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<property name="RunSynthesis" value="4" type="JavaHandler"/>
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<property name="SimulationRun" value="6" type="JavaHandler"/>
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<property name="SimulationRunAll" value="2" type="JavaHandler"/>
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<property name="ToggleViewNavigator" value="4" type="JavaHandler"/>
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<property name="ToolsSettings" value="1" type="JavaHandler"/>
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<property name="ViewTaskImplementation" value="3" type="JavaHandler"/>
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</item>
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<item name="Gui Handlers">
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<property name="AbstractFileView_RELOAD" value="4" type="GuiHandlerData"/>
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<property name="BaseDialog_CANCEL" value="5" type="GuiHandlerData"/>
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<property name="BaseDialog_OK" value="19" type="GuiHandlerData"/>
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<property name="BaseDialog_YES" value="1" type="GuiHandlerData"/>
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<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="16" type="GuiHandlerData"/>
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<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="10" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_FIT" value="6" type="GuiHandlerData"/>
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<property name="MainMenuMgr_CHECKPOINT" value="3" type="GuiHandlerData"/>
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<property name="MainMenuMgr_FILE" value="6" type="GuiHandlerData"/>
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<property name="MainMenuMgr_FLOW" value="10" type="GuiHandlerData"/>
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<property name="MainMenuMgr_HELP" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="1" type="GuiHandlerData"/>
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<property name="MainMenuMgr_PROJECT" value="4" type="GuiHandlerData"/>
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<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_TOOLS" value="6" type="GuiHandlerData"/>
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<property name="MainMenuMgr_WINDOW" value="4" type="GuiHandlerData"/>
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<property name="MainToolbarMgr_RUN" value="5" type="GuiHandlerData"/>
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<property name="NumJobsChooser_NUMBER_OF_JOBS" value="2" type="GuiHandlerData"/>
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<property name="PACommandNames_ADD_SOURCES" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_NEW_PROJECT" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_OPEN_CHECKPOINT" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_RUN_SYNTHESIS" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_LIVE_RUN_ALL" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_RUN" value="3" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="6" type="GuiHandlerData"/>
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<property name="PACommandNames_TOGGLE_VIEW_NAV" value="4" type="GuiHandlerData"/>
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<property name="PAViews_CODE" value="1" type="GuiHandlerData"/>
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<property name="PAViews_PROJECT_SUMMARY" value="6" type="GuiHandlerData"/>
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<property name="PAViews_SCHEMATIC" value="1" type="GuiHandlerData"/>
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<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="3" type="GuiHandlerData"/>
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<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
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<property name="RDICommands_CUSTOM_COMMANDS" value="2" type="GuiHandlerData"/>
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<property name="RDICommands_SETTINGS" value="1" type="GuiHandlerData"/>
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<property name="RDIViews_WAVEFORM_VIEWER" value="10" type="GuiHandlerData"/>
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<property name="SettingsDialog_OPTIONS_TREE" value="1" type="GuiHandlerData"/>
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<property name="SettingsDialog_PROJECT_TREE" value="6" type="GuiHandlerData"/>
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<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="2" type="GuiHandlerData"/>
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<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="1" type="GuiHandlerData"/>
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<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="2" type="GuiHandlerData"/>
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<property name="SrcFilePropPanels_LIBRARY" value="2" type="GuiHandlerData"/>
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<property name="SrcFilePropPanels_TYPE" value="2" type="GuiHandlerData"/>
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</item>
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</section>
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</application>
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</document>

‎Verilog_Digital_Logic_Design_Practice/CH3/wire_and_or/wire_and_or.cache/wt/xsim.wdf‎

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version:1
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eof:2427094519

‎Verilog_Digital_Logic_Design_Practice/CH3/wire_and_or/wire_and_or.hw/wire_and_or.lpr‎

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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2020.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>

‎Verilog_Digital_Logic_Design_Practice/CH3/wire_and_or/wire_and_or.ip_user_files/README.txt‎

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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

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