Multimedia-Processing
diff --git a/‎Verilog/CH2/and_gate.qpf‎ ‎…l_Logic_Design_Practice/CH2/and_gate.qpf‎Verilog/CH2/and_gate.qpf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate.qpf b/‎Verilog/CH2/and_gate.qpf‎ ‎…l_Logic_Design_Practice/CH2/and_gate.qpf‎Verilog/CH2/and_gate.qpf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate.qpf
diff --git a/‎Verilog/CH2/and_gate.qsf‎ ‎…l_Logic_Design_Practice/CH2/and_gate.qsf‎Verilog/CH2/and_gate.qsf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate.qsf b/‎Verilog/CH2/and_gate.qsf‎ ‎…l_Logic_Design_Practice/CH2/and_gate.qsf‎Verilog/CH2/and_gate.qsf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate.qsf
diff --git a/‎…_gate/and_gate.cache/wt/gui_handlers.wdf‎ ‎…_gate/and_gate.cache/wt/gui_handlers.wdf‎Verilog/CH2/and_gate/and_gate.cache/wt/gui_handlers.wdf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/gui_handlers.wdf b/‎…_gate/and_gate.cache/wt/gui_handlers.wdf‎ ‎…_gate/and_gate.cache/wt/gui_handlers.wdf‎Verilog/CH2/and_gate/and_gate.cache/wt/gui_handlers.wdf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/gui_handlers.wdf
diff --git a/‎…_gate.cache/wt/java_command_handlers.wdf‎ ‎…_gate.cache/wt/java_command_handlers.wdf‎Verilog/CH2/and_gate/and_gate.cache/wt/java_command_handlers.wdf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/java_command_handlers.wdf b/‎…_gate.cache/wt/java_command_handlers.wdf‎ ‎…_gate.cache/wt/java_command_handlers.wdf‎Verilog/CH2/and_gate/and_gate.cache/wt/java_command_handlers.wdf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/java_command_handlers.wdf
diff --git a/‎…2/and_gate/and_gate.cache/wt/project.wpc‎ ‎…2/and_gate/and_gate.cache/wt/project.wpc‎Verilog/CH2/and_gate/and_gate.cache/wt/project.wpc renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/project.wpc b/‎…2/and_gate/and_gate.cache/wt/project.wpc‎ ‎…2/and_gate/and_gate.cache/wt/project.wpc‎Verilog/CH2/and_gate/and_gate.cache/wt/project.wpc renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/project.wpc
diff --git a/‎…and_gate/and_gate.cache/wt/synthesis.wdf‎ ‎…and_gate/and_gate.cache/wt/synthesis.wdf‎Verilog/CH2/and_gate/and_gate.cache/wt/synthesis.wdf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/synthesis.wdf b/‎…and_gate/and_gate.cache/wt/synthesis.wdf‎ ‎…and_gate/and_gate.cache/wt/synthesis.wdf‎Verilog/CH2/and_gate/and_gate.cache/wt/synthesis.wdf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/synthesis.wdf
diff --git a/‎…/and_gate.cache/wt/synthesis_details.wdf‎ ‎…/and_gate.cache/wt/synthesis_details.wdf‎Verilog/CH2/and_gate/and_gate.cache/wt/synthesis_details.wdf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/synthesis_details.wdf b/‎…/and_gate.cache/wt/synthesis_details.wdf‎ ‎…/and_gate.cache/wt/synthesis_details.wdf‎Verilog/CH2/and_gate/and_gate.cache/wt/synthesis_details.wdf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/synthesis_details.wdf
diff --git a/‎…nd_gate/and_gate.cache/wt/webtalk_pa.xml‎ ‎…nd_gate/and_gate.cache/wt/webtalk_pa.xml‎Verilog/CH2/and_gate/and_gate.cache/wt/webtalk_pa.xml renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/webtalk_pa.xml b/‎…nd_gate/and_gate.cache/wt/webtalk_pa.xml‎ ‎…nd_gate/and_gate.cache/wt/webtalk_pa.xml‎Verilog/CH2/and_gate/and_gate.cache/wt/webtalk_pa.xml renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/webtalk_pa.xml
diff --git a/‎…/CH2/and_gate/and_gate.cache/wt/xsim.wdf‎ ‎…/CH2/and_gate/and_gate.cache/wt/xsim.wdf‎Verilog/CH2/and_gate/and_gate.cache/wt/xsim.wdf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/xsim.wdf b/‎…/CH2/and_gate/and_gate.cache/wt/xsim.wdf‎ ‎…/CH2/and_gate/and_gate.cache/wt/xsim.wdf‎Verilog/CH2/and_gate/and_gate.cache/wt/xsim.wdf renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.cache/wt/xsim.wdf
diff --git a/‎…og/CH2/and_gate/and_gate.hw/and_gate.lpr‎ ‎…ce/CH2/and_gate/and_gate.hw/and_gate.lpr‎Verilog/CH2/and_gate/and_gate.hw/and_gate.lpr renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.hw/and_gate.lpr b/‎…og/CH2/and_gate/and_gate.hw/and_gate.lpr‎ ‎…ce/CH2/and_gate/and_gate.hw/and_gate.lpr‎Verilog/CH2/and_gate/and_gate.hw/and_gate.lpr renamed to Verilog_Digital_Logic_Design_Practice/CH2/and_gate/and_gate.hw/and_gate.lpr