Commit 7f879ba
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如果採用，此提交將移動路徑，將《數位邏輯實習》的成果放入到新的資料夾
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議題1 parent 6d087ed commit 7f879ba
2,268 files changed
Lines changed: 0 additions & 73850 deletions
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- CH3/CH3-2
- db
- incremental_db
- compiled_partitions
- output_files
- CH4
- CH4-2
- db
- incremental_db
- compiled_partitions
- output_files
- CH4-3
- db
- incremental_db
- compiled_partitions
- output_files
- CH5
- CH5-2
- db
- incremental_db
- compiled_partitions
- output_files
- CH5-3
- db
- incremental_db
- compiled_partitions
- output_files
- CH6
- CH6-1
- db
- incremental_db
- compiled_partitions
- output_files
- CH6-2
- db
- incremental_db
- compiled_partitions
- output_files
- Digital_Logic_Practice
- CH3/CH3-2
- simulation/modelsim
- CH4
- CH4-2
- output_files
- simulation
- modelsim
- qsim
- work
- CH4-3
- output_files
- simulation
- modelsim
- qsim
- work
- CH5
- CH5-2
- output_files
- simulation
- modelsim
- qsim
- work
- CH5-3
- hc_output
- output_files
- simulation
- modelsim
- qsim
- work
- @b@c@d_adder_1@d_@g_vlg_check_tst
- @b@c@d_adder_1@d_@g_vlg_sample_tst
- @b@c@d_adder_1@d_@g_vlg_vec_tst
- @b@c@d_adder_1@d_@g
- CH6
- CH6-1
- output_files
- simulation
- modelsim
- qsim
- work
- @b@c@d_to_decimal_decoder_vlg_check_tst
- @b@c@d_to_decimal_decoder_vlg_sample_tst
- @b@c@d_to_decimal_decoder_vlg_vec_tst
- @b@c@d_to_decimal_decoder
- @ten_line_to_four_line_@b@c@d_encoder_vlg_check_tst
- @ten_line_to_four_line_@b@c@d_encoder_vlg_sample_tst
- @ten_line_to_four_line_@b@c@d_encoder_vlg_vec_tst
- @ten_line_to_four_line_@b@c@d_encoder
- enight_to_three_priority_encoder_vlg_check_tst
- enight_to_three_priority_encoder_vlg_sample_tst
- enight_to_three_priority_encoder_vlg_vec_tst
- enight_to_three_priority_encoder
- four_line_to_sixteen_line_decimal_decoder_vlg_check_tst
- four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst
- four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst
- four_line_to_sixteen_line_decimal_decoder
- ten_line_to_four_line_@b@c@d_priority_encoder_vlg_check_tst
- ten_line_to_four_line_@b@c@d_priority_encoder_vlg_sample_tst
- ten_line_to_four_line_@b@c@d_priority_encoder_vlg_vec_tst
- ten_line_to_four_line_@b@c@d_priority_encoder
- three_line_to_eight_decimal_decoder_vlg_check_tst
- three_line_to_eight_decimal_decoder_vlg_sample_tst
- three_line_to_eight_decimal_decoder_vlg_vec_tst
- three_line_to_eight_decimal_decoder
- CH6-2
- hc_output
- output_files
- simulation
- modelsim
- qsim
- work
- @b@c@d_seven_seg_@a_vlg_check_tst
- @b@c@d_seven_seg_@a_vlg_sample_tst
- @b@c@d_seven_seg_@a_vlg_vec_tst
- @b@c@d_seven_seg_@a
- @b@c@d_seven_seg_seven_four_four_seven_vlg_check_tst
- @b@c@d_seven_seg_seven_four_four_seven_vlg_sample_tst
- @b@c@d_seven_seg_seven_four_four_seven_vlg_vec_tst
- @b@c@d_seven_seg_seven_four_four_seven
- @b@c@d_seven_seg_seven_four_two_four_eight_vlg_check_tst
- @b@c@d_seven_seg_seven_four_two_four_eight_vlg_sample_tst
- @b@c@d_seven_seg_seven_four_two_four_eight_vlg_vec_tst
- @b@c@d_seven_seg_seven_four_two_four_eight
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