Popular repositories Loading

1. Yield-Aware-CMOS-Inverter-KLayout Yield-Aware-CMOS-Inverter-KLayout Public

   Designed a CMOS inverter layout in KLayout and performed yield-oriented defect analysis, including missing contact, metal open, metal short, spacing violation, and poly gate break defects to study …

2. 6T-SRAM-LTspice 6T-SRAM-LTspice Public

   Design, simulation and verification of a CMOS 6T SRAM cell in LTspice including Hold, Write, Read and Bit-line Capacitance analysis.

   AGS Script