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feat(frontend): introduce transistor-first standard cells and switch-level CMOS simulation - #20
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Intent
I have realized what cadence has gotten right, right? So basically the gates that we were making, there are smaller, there are units that make the gate as well.
So we need gate, we need to be able to, we need to get rid of the gates, the north gate, the and gate and the south and the and gate, north gate, nor gate. And we need to work on smaller components than them.
And then when we put them together, like CMOS and a lot of NAND gates together, components that make the NAND gate together, we can make it a component, name it NAND gate and use it in our personal library. Save it in our personal library and use it anywhere. I want you to understand cadence thoroughly. Dig very deep into it, understand what it does and all those things.
Figure out how we can train and model on it. I want to train a model for my agent.
So if we could do that, that will be great, a model that works for pure electronics. That will be great. We could fine tune a model like a one to billion parameter model. We could make do something with it.
I want to write a research paper on it. An RL environment also we discussed. Something should be a very, very good and well documented project is what I feel.
So if you could start working on it, that will be great.
Context: "north gate" and "south" are speech-to-text for NOT/NAND/NOR gates. DigiSim already has NMOS/PMOS nodes, a subcircuit hierarchy (logic/hierarchy/CellRegistry.ts), a personal component library panel, and a Gymnasium RL environment (ml/rl/digisim_env.py) from PR #14; plans/ holds earlier vision docs (virtuoso_ai_master_plan.md, digicopilot_silicon_architect.md).
What Changed
switchLevel.ts) integrated intorunSimulationthat resolves NMOS and PMOS transistor networks with supplies and inputs to digital logic levels (0, 1, X, Z).standardCells.ts, and updatedCustomComponentNodeto distribute same-side pin handles evenly.Risk Assessment
✅ Low: Transistor-first transition cleanly removes ready-made gate chips from the UI, adds switch-level CMOS logic simulation for NMOS/PMOS networks, seeds inspectable standard cells into the personal library, and preserves backward compatibility for legacy saved circuits.
Testing
Built and stood up the product stack (Flask backend on port 5001, production React build on port 3000) and drove 5 end-to-end scenarios live using Google Chrome via Chrome DevTools Protocol. Exercised the transistor-first toolbox, verified standard cell library seeding, placed MOSFET and subcircuit nodes on the interactive canvas, validated multi-pin handle geometry, and verified digital switch-level CMOS simulation. Captured 6 reviewer-visible visual artifacts in the evidence directory.
Pipeline
Updates from git push no-mistakes
✅ **intent** - passed
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✅ **Rebase** - passed
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✅ **Review** - passed
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✅ **Test** - passed
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cd frontend && npm test -- --watchAll=false(32 test suites, 201 unit tests passing)Live headless Chrome CDP session against running Flask backend (port 5001) and static frontend build (port 3000)Sidebar inspection: verified 'Silicon Primitives' menu, 'Digital I/O' tab with Input/Output chips, absence of raw gate primitives, and 'Gates live in My Library' guidanceCommand Palette (⌘K) inspection: verified 'Gates live in My Library (transistor cells)' entry and absence of raw gate primitivesPersonal Library inspection: verified 6 seeded standard cells (NOT, NAND, NOR, AND, OR, XOR) with inspectable CMOS transistor subcircuitsCanvas component placement: placed NMOS, PMOS, and standard cells on the canvas, toggled Input switch states, and observed real-time simulation updatesPin spreading verification: verified CustomComponentNode handles on NAND cell are spread at distinct top offsets (33.33% and 66.67% on LEFT edge) rather than overlapping✅ **Document** - passed
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✅ **Lint** - passed
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✅ **Push** - passed
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