Manchester Decoder

A discrete-logic Manchester decoder built from standard 74HC logic ICs.

This project turns a digital-logic state-machine problem into a real hardware circuit. Instead of decoding Manchester data in firmware or an FPGA, the design uses ordinary NAND gates, NOR gates, and D flip-flops so the whole decoding process can be inspected directly on the bench.

The decoder follows the common IEEE 802.3 Manchester convention:

• high-to-low transition: 0
• low-to-high transition: 1

The circuit provides a decoded data output (D) and a valid output (V). Downstream logic should sample D only when V is asserted.

Features

• Discrete 74HC-series logic implementation.
• Clocked finite-state-machine decoder.
• Decoded data output plus valid flag output.
• Logic implementation based on NAND, NOR, and D flip-flop devices.
• JLC EDA Pro project export and Altium schematic/PCB export included.
• Suitable for learning, probing, and verifying Manchester decoding at the gate level.

Hardware Overview

The main logic devices used in this design include:

Device	Role
SN74HC00N	Quad 2-input NAND gate
SN74HC02N	Quad 2-input NOR gate
SN74HC74N	Dual D-type flip-flop

The design is a clocked Moore-style decoder. The internal state is stored in D flip-flops, and the combinational transition/output logic is implemented with NAND and NOR gates.

Key Considerations

1. Encoding Convention

   The project assumes the IEEE 802.3-style convention where high-to-low means 0 and low-to-high means 1. If the signal source uses the opposite convention, the decoded data output will be inverted.

2. Valid Output

   Treat D as meaningful only when V is asserted. This is important at the beginning of a stream, after invalid transitions, and around any discontinuity in the encoded signal.

3. Clocking

   The decoder is synchronous. The usable data rate depends on the clock source, the encoded input quality, the supply voltage, and the propagation delay of the selected 74HC devices.

4. Logic Family Consistency

   Use compatible logic-family parts and a clean supply rail. Mixing logic families or driving the board from weak signal sources can reduce timing margin.

5. Bench Verification

   A microcontroller or signal generator can be used as a Manchester encoder source. During verification, observe the raw encoded input, clock, D, and V signals together.

6. Debug Access

   Keep the clock, encoded input, decoded data, and valid output easy to probe. These are the most useful nodes when checking state-machine behavior.

Repository Contents

File	Description
Altium_Manchester_Decoder_2026-05-06.zip	Altium export containing the schematic and PCB files.
ProPrj_Manchester_Decoder_2026-05-06.epro	JLC EDA Pro project export.
LICENSE	MIT license.
README.md	Project introduction and design notes.

Opening the Project

Use ProPrj_Manchester_Decoder_2026-05-06.epro to import the project back into JLC EDA Pro.

Use Altium_Manchester_Decoder_2026-05-06.zip if you want to inspect or modify the exported Altium schematic and PCB files.

Project Status

This repository contains the editable project exports. Manufacturing outputs such as Gerbers, BOM files, placement files, and assembly drawings are not included unless exported separately.

Background

• Background article: https://mp.weixin.qq.com/s/hv9AFArUfTvjjuDU3YBIcw

License

This project is released under the MIT License.