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🔐 Digital Safe‑Lock System

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🧩 Overview

This project implements a Digital Safe‑Lock System using SystemVerilog, designed to authenticate a 4‑bit security code using a combination of:

• AXI‑style Parallel‑to‑Serial (P2S) data conversion
• Finite State Machines (FSMs) — both Mealy and Moore versions
• Bit‑by‑bit verification logic
• Unlock/Incorrect signaling

The system ensures secure access by serializing the 4‑bit passcode and validating each bit through a state machine.
Only when the full sequence matches the predefined code (1011) does the safe unlock.

This project demonstrates strong digital design skills, including RTL design, FSM modeling, modular architecture, and simulation‑based verification.

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🧱 System Architecture

The safe‑lock system consists of three main components:

1. Parallel‑to‑Serial Converter (P2S)

• Accepts a 4‑bit parallel input
• Converts it into a serial bitstream using a shift‑register mechanism
• Follows an AXI‑style handshake (par_valid, par_ready, ser_valid, ser_ready)
• Outputs one bit per clock cycle

2. Finite State Machine (FSM)

Two versions are implemented:

Moore Machine

• Output depends only on the current state

• Moves through states as each serial bit arrives

• Generates:

  • output_valid
  • output (correct/incorrect)

• State Diagram of Moore Machine

Mealy Machine

• Output depends on state + input

• Responds faster to incorrect bits

• Immediately flags incorrect sequences

• State Diagram of Mealy Machine

Both FSMs:

• Validate the 4‑bit sequence 1011
• Stop checking further bits once an incorrect bit is detected
• Produce:
  • Unlock signal (correct code)
  • Incorrect signal (wrong code)

3. Top‑Level Integration

The top module connects:

• P2S converter
• FSM (Mealy or Moore)

It performs:

1. Parallel input → serialized bitstream
2. Bit‑by‑bit verification
3. Unlock decision

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🧪 Testbenches & Verification

Each module includes a dedicated testbench:

✔ Parallel‑to‑Serial Converter

• Tested with 10 different 4‑bit inputs
• Verified correct serialization order

✔ FSM (Mealy & Moore)

• Tested with valid and invalid sequences
• Verified state transitions and output behavior

✔ Integrated System

• Full system simulation
• Validates correct unlock behavior
• Ensures incorrect sequences are rejected immediately

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📸 Simulation Screenshots

• Parallel‑to‑Serial (P2S) testbench result
  

• Moore Machine testbench result

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📂 Suggested Project Structure

/Digital-Safe-Lock
│
├── p2s_converter.sv
├── p2s_converter_tb.sv
│
├── mealy_fsm.sv
├── moore_fsm.sv
├── fsm_tb.sv
│
├── top_module.sv
├── top_module_tb.sv
      

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🛠 Tools Used

• SystemVerilog
• EDA Playground (simulation)
• Visual Studio Code (development)

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