Add fossee HDL project folders

fossee/asynchronous_fifo/asynchronous_fifo/analysis

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+.tran 1e-09 450e-09 0e-09

fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo-cache.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_5
+#
+DEF adc_bridge_5 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_5" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -400 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X OUT1 6 550 50 200 L 50 50 1 1 O
+X OUT2 7 550 -50 200 L 50 50 1 1 O
+X OUT3 8 550 -150 200 L 50 50 1 1 O
+X OUT4 9 550 -250 200 L 50 50 1 1 O
+X OUT5 10 550 -350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# asynchronous_fifo
+#
+DEF asynchronous_fifo U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "asynchronous_fifo" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 500 0 1 0 N
+X wclk0 1 2150 1900 200 R 50 50 1 1 I
+X rclk0 2 2150 1800 200 R 50 50 1 1 I
+X rst0 3 2150 1700 200 R 50 50 1 1 I
+X wr_en0 4 2150 1600 200 R 50 50 1 1 I
+X rd_en0 5 2150 1500 200 R 50 50 1 1 I
+X din7 6 2150 1400 200 R 50 50 1 1 I
+X din6 7 2150 1300 200 R 50 50 1 1 I
+X din5 8 2150 1200 200 R 50 50 1 1 I
+X din4 9 2150 1100 200 R 50 50 1 1 I
+X din3 10 2150 1000 200 R 50 50 1 1 I
+X dout1 20 3550 1300 200 L 50 50 1 1 O
+X din2 11 2150 900 200 R 50 50 1 1 I
+X dout0 21 3550 1200 200 L 50 50 1 1 O
+X din1 12 2150 800 200 R 50 50 1 1 I
+X full0 22 3550 1100 200 L 50 50 1 1 O
+X din0 13 2150 700 200 R 50 50 1 1 I
+X empty0 23 3550 1000 200 L 50 50 1 1 O
+X dout7 14 3550 1900 200 L 50 50 1 1 O
+X dout6 15 3550 1800 200 L 50 50 1 1 O
+X dout5 16 3550 1700 200 L 50 50 1 1 O
+X dout4 17 3550 1600 200 L 50 50 1 1 O
+X dout3 18 3550 1500 200 L 50 50 1 1 O
+X dout2 19 3550 1400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library

fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.cir

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+* C:\Users\VLSI\eSim-Workspace\asynchronous_fifo\asynchronous_fifo.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/03/2026 19:49:05
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ Net-_U11-Pad9_ Net-_U11-Pad10_ Net-_U11-Pad11_ Net-_U11-Pad12_ Net-_U11-Pad13_ Net-_U11-Pad14_ Net-_U11-Pad15_ Net-_U11-Pad16_ Net-_U11-Pad17_ Net-_U11-Pad18_ Net-_U11-Pad19_ Net-_U11-Pad20_ Net-_U11-Pad21_ Net-_U11-Pad22_ Net-_U11-Pad23_ asynchronous_fifo		
+U17  d7 d6 d5 d4 d3 d2 d1 d0 Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ Net-_U11-Pad9_ Net-_U11-Pad10_ Net-_U11-Pad11_ Net-_U11-Pad12_ Net-_U11-Pad13_ adc_bridge_8		
+U16  wclk0 rclk0 rst0 wr_en0 rd_en0 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ adc_bridge_5		
+U18  Net-_U11-Pad14_ Net-_U11-Pad15_ Net-_U11-Pad16_ Net-_U11-Pad17_ Net-_U11-Pad18_ Net-_U11-Pad19_ Net-_U11-Pad20_ Net-_U11-Pad21_ q7 q6 q5 q4 q3 q2 q1 q0 dac_bridge_8		
+U19  Net-_U11-Pad22_ Net-_U11-Pad23_ full0 empty0 dac_bridge_2		
+v11  wclk0 GND pulse		
+v12  rclk0 GND pulse		
+v13  rst0 GND pulse		
+v5  wr_en0 GND pulse		
+v6  rd_en0 GND pulse		
+v7  d7 GND pulse		
+v8  d6 GND pulse		
+v1  d5 GND pulse		
+v2  d4 GND pulse		
+v9  d3 GND pulse		
+v10  d2 GND pulse		
+v3  d1 GND pulse		
+v4  ? GND pulse		
+U2  wclk0 plot_v1		
+U1  rclk0 plot_v1		
+U3  rst0 plot_v1		
+U4  wr_en0 plot_v1		
+U6  rd_en0 plot_v1		
+U10  d7 plot_v1		
+U7  d6 plot_v1		
+U13  d5 plot_v1		
+U9  d4 plot_v1		
+U5  d3 plot_v1		
+U15  d3 plot_v1		
+U12  d2 plot_v1		
+U14  d1 plot_v1		
+U8  d0 plot_v1		
+U20  q7 plot_v1		
+U21  q6 plot_v1		
+U22  q5 plot_v1		
+U23  q4 plot_v1		
+U24  q3 plot_v1		
+U25  q2 plot_v1		
+U26  q1 plot_v1		
+U27  q0 plot_v1		
+U28  full0 plot_v1		
+U29  empty0 plot_v1		
+
+.end

fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.cir.out

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+* c:\users\vlsi\esim-workspace\asynchronous_fifo\asynchronous_fifo.cir
+
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ net-_u11-pad11_ net-_u11-pad12_ net-_u11-pad13_ net-_u11-pad14_ net-_u11-pad15_ net-_u11-pad16_ net-_u11-pad17_ net-_u11-pad18_ net-_u11-pad19_ net-_u11-pad20_ net-_u11-pad21_ net-_u11-pad22_ net-_u11-pad23_ asynchronous_fifo
+* u17  d7 d6 d5 d4 d3 d2 d1 d0 net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ net-_u11-pad11_ net-_u11-pad12_ net-_u11-pad13_ adc_bridge_8
+* u16  wclk0 rclk0 rst0 wr_en0 rd_en0 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ adc_bridge_5
+* u18  net-_u11-pad14_ net-_u11-pad15_ net-_u11-pad16_ net-_u11-pad17_ net-_u11-pad18_ net-_u11-pad19_ net-_u11-pad20_ net-_u11-pad21_ q7 q6 q5 q4 q3 q2 q1 q0 dac_bridge_8
+* u19  net-_u11-pad22_ net-_u11-pad23_ full0 empty0 dac_bridge_2
+v11  wclk0 gnd pulse(0 1 0n 1n 1n 10n 20n)
+v12  rclk0 gnd pulse(0 1 0n 1n 1n 15n 30n)
+v13  rst0 gnd pulse(0 1 40n 1n 1n 1000n 2000n)
+v5  wr_en0 gnd pulse(0 1 60n 1n 1n 120n 240n)
+v6  rd_en0 gnd pulse(0 1 200n 1n 1n 120n 240n)
+v4  d0 gnd pulse(0 1 60n 1n 1n 20n 40n)
+v3  d1 gnd pulse(0 1 80n 1n 1n 40n 80n)
+v10 d2 gnd pulse(0 1 120n 1n 1n 80n 160n)
+v9  d3 gnd pulse(0 0 0 0 0 0 0)
+v2  d4 gnd pulse(0 0 0 0 0 0 0)
+v1  d5 gnd pulse(0 0 0 0 0 0 0)
+v8  d6 gnd pulse(0 0 0 0 0 0 0)
+v7  d7 gnd pulse(0 0 0 0 0 0 0)
+* u2  wclk0 plot_v1
+* u1  rclk0 plot_v1
+* u3  rst0 plot_v1
+* u4  wr_en0 plot_v1
+* u6  rd_en0 plot_v1
+* u10  d7 plot_v1
+* u7  d6 plot_v1
+* u13  d5 plot_v1
+* u9  d4 plot_v1
+* u5  d3 plot_v1
+* u15  d3 plot_v1
+* u12  d2 plot_v1
+* u14  d1 plot_v1
+* u8  d0 plot_v1
+* u20  q7 plot_v1
+* u21  q6 plot_v1
+* u22  q5 plot_v1
+* u23  q4 plot_v1
+* u24  q3 plot_v1
+* u25  q2 plot_v1
+* u26  q1 plot_v1
+* u27  q0 plot_v1
+* u28  full0 plot_v1
+* u29  empty0 plot_v1
+a1 [net-_u11-pad1_ ] [net-_u11-pad2_ ] [net-_u11-pad3_ ] [net-_u11-pad4_ ] [net-_u11-pad5_ ] [net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ net-_u11-pad11_ net-_u11-pad12_ net-_u11-pad13_ ] [net-_u11-pad14_ net-_u11-pad15_ net-_u11-pad16_ net-_u11-pad17_ net-_u11-pad18_ net-_u11-pad19_ net-_u11-pad20_ net-_u11-pad21_ ] [net-_u11-pad22_ ] [net-_u11-pad23_ ] u11
+a2 [d7 d6 d5 d4 d3 d2 d1 d0 ] [net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ net-_u11-pad11_ net-_u11-pad12_ net-_u11-pad13_ ] u17
+a3 [wclk0 rclk0 rst0 wr_en0 rd_en0 ] [net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ ] u16
+a4 [net-_u11-pad14_ net-_u11-pad15_ net-_u11-pad16_ net-_u11-pad17_ net-_u11-pad18_ net-_u11-pad19_ net-_u11-pad20_ net-_u11-pad21_ ] [q7 q6 q5 q4 q3 q2 q1 q0 ] u18
+a5 [net-_u11-pad22_ net-_u11-pad23_ ] [full0 empty0 ] u19
+* Schematic Name:                             asynchronous_fifo, NgSpice Name: asynchronous_fifo
+.model u11 asynchronous_fifo(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             adc_bridge_8, NgSpice Name: adc_bridge
+.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_5, NgSpice Name: adc_bridge
+.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_8, NgSpice Name: dac_bridge
+.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_2, NgSpice Name: dac_bridge
+.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 1e-09 450e-09 0e-09
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(q0)+6  v(q1)+12  v(q2)+18  v(q3)+24  v(q4)+30  v(q5)+36  v(q6)+42  v(q7)+48 v(full0)+54  v(empty0)+60 v(d0)+66  v(d1)+72  v(d2)+78  v(d3)+84  v(d4)+90  v(d5)+96  v(d6)+102  v(d7)+108 v(wr_en0)+114  v(rd_en0)+120  v(rst0)+126  v(wclk0)+132  v(rclk0)+138
+.endc
+.end

fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.pro

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+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts

fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.proj

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+schematicFile asynchronous_fifo.sch