🪙 Vending Machine Controller using Digital Logic Gates & FSM

A sequential digital logic implementation of a coin-operated vending machine modeled using a Moore Finite State Machine (FSM) and simulated in Proteus 8 Professional[cite: 2].

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📌 Overview

This circuit simulates an automated vending machine that accepts 5¢ (D) and 10¢ (N) coin inputs, tracks accumulated deposits, dispenses a product upon reaching 15¢, and returns 5¢ change (C) if 20¢ is deposited[cite: 2].

• Design Methodology: Moore Finite State Machine (FSM), K-Map minimization[cite: 2]
• State Register: 2 $\times$ D Flip-Flops (DTFF)[cite: 2]
• Simulation Tool: Proteus 8 Professional[cite: 2]

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🖼️ Circuit Schematic

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⚙️ FSM Specification & State Encoding

The system tracks accumulated values using 2 state variables ($x, y$) across 3 active states[cite: 2]:

State	Accumulated	$x$ (FF1)	$y$ (FF2)
S0	0¢	0	0
S1	10¢	0	1
S2	20¢	1	0

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📐 Boolean Equations (Next-State & Output Logic)

Derived using Karnaugh Maps from the encoded state transition table[cite: 2]:

• Next State for FF1 ($x^+$): $$x^+ = \bar{x} \cdot y \cdot N + \bar{x} \cdot y \cdot D$$[cite: 2]
• Next State for FF2 ($y^+$): $$y^+ = \bar{x} \cdot \bar{y} \cdot N + \bar{x} \cdot \bar{y} \cdot D + \bar{x} \cdot y \cdot \bar{N} \cdot \bar{D}$$[cite: 2]
• Product Release Output ($R$): $$R = x \cdot \bar{y} \cdot N + x \cdot \bar{y} \cdot D$$[cite: 2]
• Change Return Output ($C$): $$C = x \cdot \bar{y} \cdot N$$[cite: 2]

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🔄 Operation Flow

1. Coin Input: Toggle D (5¢) or N (10¢) logic states (one active coin per clock cycle)[cite: 2].
2. State Transition: On the clock trigger, the D flip-flops transition based on combinational logic gates[cite: 2].
3. Dispense & Change:
   • Reaching 15¢ sets Release ($R = 1$)[cite: 2].
   • Reaching 20¢ sets Release ($R = 1$) and Change ($C = 1$) simultaneously, then resets the machine to S0[cite: 2].

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🚀 How to Run the Simulation

1. Open simulation/vending_machine.pdsprj in Proteus 8.x+[cite: 2].
2. Run the simulation.
3. Toggle the D and N logic state inputs to verify state progression on the logic probes connected to the $R$ and $C$ outputs[cite: 2].

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👥 Contributors

• Ayushman Sethy (Reg: B324011)[cite: 2]
• Dibya Ranjan Pany (Reg: B324014)[cite: 2]

Department of Electrical and Electronics Engineering (EEE), IIIT Bhubaneswar[cite: 1, 2]