This repository releases the logic-locked gate-level designs used in our paper:
Protected but Not Anonymous: Semantic Exposure in Hardware IP Protection
The purpose of this repository is to support reproducible research on semantic exposure in hardware IP protection. In particular, we study whether logic-locked designs still preserve structural and functional cues that can be exploited by learning-based hardware analysis models, such as GNN-based reverse engineering.
Logic locking protects hardware intellectual property (IP) by inserting key-controlled logic into a design. Existing evaluations often focus on key recovery, output corruption, or functional correctness. In our work, we ask a complementary question:
Even when a design is protected by logic locking, does the protected netlist still reveal semantic information about the original hardware IP?
To enable further study of this question, we release the locked design variants evaluated in the paper. The released designs are generated from the RTL designs used in the GNN-RE framework and are organized by locking scheme and locking configuration.
The repository is organized as follows:
ProtectedNotAnonymous/
├── 45_lib_syn_verilog/
├── antisat_lock_10/
├── antisat_lock_20/
├── antisat_lock_30/
├── aor_lock_10/
├── aor_lock_20/
├── aor_lock_30/
├── cyc_lock_10_lp2/
├── cyc_lock_10_lp3/
├── cyc_lock_10_lp4/
├── cyc_lock_20_lp2/
├── cyc_lock_20_lp3/
├── cyc_lock_20_lp4/
└── ...