GitHub - Desir-16/VLSI-4Bit-Comparator: This project details a 4-bit Magnitude Comparator design using Cadence Virtuoso (90nm). It compares inputs (>, <, =) via schematic and layout. Verification (DRC/LVS) and transient simulations confirmed logical correctness and physical compliance.

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
mylibrary		mylibrary
.gitattributes		.gitattributes

About

This project details a 4-bit Magnitude Comparator design using Cadence Virtuoso (90nm). It compares inputs (>, <, =) via schematic and layout. Verification (DRC/LVS) and transient simulations confirmed logical correctness and physical compliance.

Activity

0 stars

0 watching

0 forks

Report repository

Navigation Menu

About

Releases

Packages

Contributors

Folders and files

Latest commit

History

About

Stars

Watchers

Forks

Releases

Packages

Contributors