HELLO! 你好!
This project is the open-source version of the various assignments for the graduate courses (Advanced Digital Integrated Circuits) at the UCAS. All current and future students are welcome to access and use it in accordance with the regulations.
本项目是UCAS研究生课程(高等数字集成电路)的各项作业的开源,欢迎各位学弟学妹符合规定地查询、使用。
NOW There are below projects:
该仓库目前包括以下项目:
(按时间顺序排序)
| 文件夹名称 | 描述 | |
|---|---|---|
| 1. | First1Detector | 向量前导1检测器 |
| 2. | SpecificStreamDetector | 序列检测器 |
| 3. | toBCD | 二进制转BCD码 |
| 4. | Timer | 跑表 |
| 5. | FastAdder | 快速加法器 |
| 6. | FastMul | 快速乘法器 |
| 7. | BarrelShifter | 桶形移位器 |
| 8. | Sort | 数据排序 |
| 9. | Sqrt | 开方 |
| 10. | AHB_SRAM | AHB总线读写SRAM |
| 11. | MatScan | 矩阵扫描 |
| 12. | FFT | 256点fft/ifft |
Tips:
- You can get the details in each project folder. 你可以在每一个工程的文件夹中找到详细描述。
- Welcome you find and post issues in this repository.
- Because my ability is limited, these codes are inevitable to have mistakes. 个人能力有限,代码难免有误。(可以拿AI跑一跑,改一改发现的错误)
- Some of the content references other people's projects. 一些内容参考了前人的工程项目。
在此感谢在Verilog学习过程中起到帮助的个人/网站:
- Wu Bin, Lu Zexiao(UCAS)
- RUNOOB.COM (https://www.runoob.com/)
- Sasasatori (https://www.cnblogs.com/sasasatori)