[HIC]Add support for the NXP LPC845 Breakout board

[HuanQian571]

Adds DAPLink interface firmware support for the NXP LPC845 Breakout board (HIC: LPC11U35, target: LPC845), plus two fixes found while bringing it up.

Commits

1. lpc11u35: Fill the interface image out to the end of the app region.

The LPC11U35 has no DAPLink bootloader, so the only way to program the HIC is the on-chip ROM ISP MSC drive (CRP DISABLD). That drive maps a fixed-size firmware.bin 1:1 onto the whole 0xF000 app region, and deleting firmware.bin only clears the directory entry — the flash sectors keep their previous contents. A short image therefore left stale bytes from the old firmware in the tail, producing an image that would not boot, with no USB enumeration and no indication why.

Adds a .fill section padding .text out to the end of the app region, the same way kinetis.ld and lpc4322.ld already do.

This also fixes the interface CRC reported in DETAILS.TXT. info_crc_compute() checksums DAPLINK_ROM_IF_SIZE - 4 unconditionally, so with a short image the value depended on whatever stale bytes followed the image and never matched the CRC recorded at build time. The build-time CRC now lands at 0xEFFC, exactly where info_crc_compute() expects it.

Affects all 30 lpc11u35_*_if projects, so it is kept as a separate commit.

2. Add support for the NXP LPC845 Breakout board.

Board and target-family layers only; the firmware reuses the existing lpc11u35 HIC anchor. No custom reset or unlock behaviour is needed, so the generic kStub_HWReset_FamilyID stub family is used rather than a new target_reset.c.

3. lpc845: Regenerate the flash algorithm from the official LPC84x FLM.

The flash algorithm was initially copied from the LPC824 family on the assumption that LPC84x shares the LPC82x IAP ROM interface. It does not. Keil's own algorithm source, shipped in Keil.LPC800_DFP as Flash/LPC8xx_IAP/FlashPrg.c, distinguishes the two:

#if   defined LPC8XX || defined LPC8N04
  #define IAP_Call ((IAP_Entry) 0x1FFF1FF1)
#elif defined LPC84X || defined LPC80X
  #define IAP_Call ((IAP_Entry) 0x0F001FF1)

Byte-comparing LPC8xx_32.FLM against LPC84x_64.FLM shows exactly three functional differences, all of which the copied blob got wrong:

	LPC82x (was used)	LPC84x (correct)	effect
IAP entry	0x1FFF1FF1	0x0F001FF1	LPC84x boot ROM is at 0x0F000000; every IAP call branched to a non-existent address
END_SECTOR	31	63	chip erase covered only the lower 32 kB, leaving the upper 32 kB unerased
MAINCLKSEL/MAINCLKUEN/SYSAHBCLKDIV	SYSCON +0x70/74/78	+0x50/54/58	Init wrote to the wrong registers

The END_SECTOR bug is on the default drag-n-drop path: flash_manager calls erase_chip() whenever kEnablePageErase is not set, and this board does not set it.

Regenerated from the authoritative algorithm rather than patching bytes:

python tools/generate_flash_algo.py LPC84x_64.FLM \
    --blob-start 0x10000000 --pack-path Keil.LPC800_DFP.1.10.2.pack

The flash geometry the previous blob declared was already correct and is unchanged (one 1 kB sector descriptor at 0, 64 kB region), matching the FLM. target.c needs no change; its flash and RAM regions also match the pack's IROM1/IRAM1 for LPC845M301JBD48.

Testing

• All 30 lpc11u35_*_if projects build with GCC 10.3-2021.10; each produces a 0xF000 image and none overflow m_text.
• Flashed lpc11u35_lpc845breakout_if to an LPC845 Breakout board. It enumerates as a full DAPLink MSD drive, and DETAILS.TXT reports an interface CRC matching the build's _crc.txt.
• Drag-n-drop to the LPC845 target succeeds. Reading the target flash back over SWD shows a ~34 kB image programmed correctly past 0x8000 — sectors that the previous END_SECTOR of 31 would have left unerased.
• CMSIS-DAP/SWD verified via pyOCD against lpc845m301jbd48: halt/resume, core register reads, CPUID (0x410CC601, Cortex-M0+), 4 kB RAM write/read round trip, and reset_and_halt.

test/run_test.py endpoint tests were not run: they require a daplink-validation image built for the LPC845, which does not exist, and --testdl self-skips because this board has no bootloader.

Notes for reviewers

• A test/info.py entry is added for board ID 0xD002 (LPC845BREAKOUT).
• records/board/lpc845breakout.yaml and source/board/lpc845breakout.c follow docs/PORT_BOARD.md; no common code is touched, so the no-#ifdef rule is preserved.