scom_init

.gitmodules

@@ -1,60 +1,64 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
+	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://github.com/coreboot/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
+[submodule "3rdparty/sb-signing-utils"]
+	path = 3rdparty/sb-signing-utils
+	url = https://github.com/open-power/sb-signing-utils.git

Makefile.inc

@@ -500,9 +500,9 @@ ifeq ($(CONFIG_DEBUG_ADA_CODE),y)
 ADAFLAGS_common += -gnata
 endif
 
-additional-dirs := $(objutil)/cbfstool $(objutil)/ifdtool \
+additional-dirs += $(objutil)/cbfstool $(objutil)/ifdtool \
 		   $(objutil)/options $(objutil)/amdfwtool \
-		   $(objutil)/cbootimage
+		   $(objutil)/cbootimage $(objutil)/ffs
 
 export $(COREBOOT_EXPORTS)
 
@@ -538,6 +538,8 @@ RMODTOOL:=$(objutil)/cbfstool/rmodtool
 IFWITOOL:=$(objutil)/cbfstool/ifwitool
 IFITTOOL:=$(objutil)/cbfstool/ifittool
 AMDCOMPRESS:=$(objutil)/cbfstool/amdcompress
+ECCTOOL:=$(objutil)/ffs/ecc/ecc
+SBSINGTOOLS:=$(objutil)/sb-signing-utils
 
 $(obj)/cbfstool: $(CBFSTOOL)
 	cp $< $@
@@ -576,6 +578,18 @@ $(IFDTOOL):
 
 AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
 
+$(ECCTOOL):
+	@printf "    Compile ECCTOOL\n"
+	cp -r $(top)/3rdparty/ffs $(objutil)
+	cd $(objutil)/ffs && autoreconf -i && ./configure
+	+$(MAKE) -C $(objutil)/ffs
+
+$(SBSINGTOOLS):
+	@printf "    Compile SB SIGNING UTILS\n"
+	cp -r $(top)/3rdparty/sb-signing-utils $(objutil)
+	cd $(objutil)/sb-signing-utils && autoreconf -i -Wno-unsupported && ./configure
+	+$(MAKE) -C $(objutil)/sb-signing-utils
+
 APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
 
 CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage
@@ -687,7 +701,7 @@ install-git-commit-clangfmt:
 include util/crossgcc/Makefile.inc
 
 .PHONY: tools
-tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo
+tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(ECCTOOL) $(SBSINGTOOL)
 
 ###########################################################################
 # Common recipes for all stages
@@ -1124,7 +1138,7 @@ else
 RAMSTAGE=
 endif
 
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE)
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $(ECCTOOL) $(SBSINGTOOLS) $$(INTERMEDIATE)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 # The full ROM may be larger than the CBFS part, so create an empty
 # file (filled with \377 = 0xff) and copy the CBFS image over it.
@@ -1144,6 +1158,20 @@ endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	$(CBFSTOOL) $@ layout
 	@printf "    CBFSPRINT  $(subst $(obj)/,,$(@))\n\n"
 	$(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions))
+ifeq ($(CONFIG_ARCH_PPC64),y)
+	cp -r $(top)/3rdparty/sb-signing-utils/test/keys /tmp
+	@printf "    SBSIGN  $(subst $(obj)/,,$(@))\n"
+	cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$(objcbfs)/bootblock.bin $(top)/$(obj)/bootblock.signed 2> /dev/null
+	cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$@ $(top)/$@.signed 2> /dev/null
+	@printf "    ECC     $(subst $(obj)/,,$(@))\n"
+	$(ECCTOOL) --inject $(top)/$@.signed --output $(top)/$@.signed.ecc --p8
+	$(ECCTOOL) --inject $(top)/$@ --output $(top)/$@.ecc --p8
+	@printf "    ECC     bootblock\n"
+	dd  if=$(obj)/bootblock.signed  of=$(obj)/bootblock.signed.pad  ibs=25486 conv=sync 2> /dev/null
+	$(ECCTOOL) --inject $(obj)/bootblock.signed.pad --output $(obj)/bootblock.signed.ecc --p8
+	rm $(obj)/bootblock.signed $(obj)/bootblock.signed.pad
+endif
+
 
 cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage
 $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf

README.md

@@ -1,3 +1,8 @@
+## Contributing
+
+All relevant chnages to OpenPOWER Talos II should go here:
+https://github.com/InsurgoTech/coreboot
+
 coreboot README
 ===============
 

configs/config.raptor-cs-talos-2

@@ -0,0 +1 @@
+CONFIG_VENDOR_RAPTOR_CS=y

src/arch/ppc64/Makefile.inc

@@ -9,7 +9,8 @@ ppc64_asm_flags =
 ################################################################################
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64),y)
 
-bootblock-y = bootblock.S stages.c
+bootblock-y = bootblock_crt0.S
+bootblock-y += arch_timer.c
 bootblock-y += boot.c
 bootblock-y += rom_media.c
 bootblock-y += \
@@ -34,6 +35,7 @@ endif
 ################################################################################
 ifeq ($(CONFIG_ARCH_ROMSTAGE_PPC64),y)
 
+romstage-y += arch_timer.c
 romstage-y += boot.c
 romstage-y += stages.c
 romstage-y += rom_media.c
@@ -62,6 +64,7 @@ endif
 ################################################################################
 ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y)
 
+ramstage-y += arch_timer.c
 ramstage-y += rom_media.c
 ramstage-y += stages.c
 ramstage-y += boot.c

src/arch/ppc64/arch_timer.c

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <timer.h>
+
+/* Refer to hostboot/src/kernel/timemgr.C */
+
+/* Time base frequency is 512 MHz so 512 ticks per usec */
+#define TB_TICKS_PER_USEC 512
+
+static inline uint64_t get_time_base(void)
+{
+	uint64_t tb = 0;
+	asm volatile("mfspr %0, 268" : "=r" (tb));
+	return tb;
+}
+
+static struct monotonic_counter {
+	int initialized;
+	struct mono_time time;
+	uint64_t last_value;
+} mono_counter;
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+	uint64_t current_tick;
+	uint64_t usecs_elapsed;
+
+	if (!mono_counter.initialized) {
+		mono_counter.last_value = get_time_base();
+		mono_counter.initialized = 1;
+	}
+
+	current_tick = get_time_base();
+	usecs_elapsed = (current_tick - mono_counter.last_value) / TB_TICKS_PER_USEC;
+
+	/* Update current time and tick values only if a full tick occurred. */
+	if (usecs_elapsed) {
+		mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
+		mono_counter.last_value = current_tick;
+	}
+
+	/* Save result. */
+	*mt = mono_counter.time;
+}

src/arch/ppc64/bootblock_crt0.S

@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Early initialization code for POWER8.
+ */
+
+#define FIXUP_ENDIAN						   \
+	tdi   0,0,0x48;	  /* Reverse endian of b . + 8		*/ \
+	b     $+44;	  /* Skip trampoline if endian is good	*/ \
+	.long 0xa600607d; /* mfmsr r11				*/ \
+	.long 0x01006b69; /* xori r11,r11,1			*/ \
+	.long 0x00004039; /* li r10,0				*/ \
+	.long 0x6401417d; /* mtmsrd r10,1			*/ \
+	.long 0x05009f42; /* bcl 20,31,$+4			*/ \
+	.long 0xa602487d; /* mflr r10				*/ \
+	.long 0x14004a39; /* addi r10,r10,20			*/ \
+	.long 0xa6035a7d; /* mtsrr0 r10				*/ \
+	.long 0xa6037b7d; /* mtsrr1 r11				*/ \
+	.long 0x2400004c  /* rfid				*/
+
+/* SBE sets HRMOR to 130MB, ie 2MB into 10MB cache. Our bootblock is loaded
+ * 12 KB above that address - it is used as a place for interrupt vectors in
+ * Hostboot, but it isn't actually a part of the HBBL partition to save space
+ * in PNOR image. */
+
+.section ".text._start", "ax", %progbits
+.globl _start
+_start:
+	/* QEMU with hb-mode=on starts at address 0x10, while hardware at 0x0. */
+	nop
+	nop
+	nop
+	nop
+	FIXUP_ENDIAN
+
+	/* Set program priority to medium */
+	or		%r2, %r2, %r2
+
+	/* Stack */
+	lis		%r1, _estack@ha
+	addi	%r1, %r1, _estack@l
+
+	/* Clear .bss section */
+	/* Curently not needed, .bss is zeroed in the file. If it were to be used,
+	 * make sure that .bss is 128B aligned (size of cache line), otherwise dcbz
+	 * will clear (part of) .opd section! */
+/*
+	lis		%r5, _bss@ha
+	addi	%r5, %r5, _bss@l
+	lis		%r6, _ebss@ha
+	addi	%r6, %r6, _ebss@l
+	addi	%r6, %r6, -1
+1:
+	dcbz	0, %r5
+	addi	%r5, %r5, 128
+	cmpld	cr7, %r5, %r6
+	blt		cr7, 1b
+*/
+
+	/* Enable floating point and vector operations */
+	/* Vector operations are sometimes generated for code like 
+	 * 'uint8_t x[32] = {0}', this results in an exception when vector registers
+	 * (VEC) are not enabled. VSX (vector-scalar extension) is also enabled,
+	 * there is no reason not to. Floating point must also be enabled for VSX.
+	 */
+	mfmsr	%r3
+	ori		%r3, %r3, 0x2000	/* FP = 1 */
+	oris	%r3, %r3, 0x0280	/* VEC = 1, VSX = 1 */
+	mtmsr	%r3
+
+	/* Load official procedure descriptor address for main() */
+	lis		%r12, main@ha
+	addi	%r12, %r12, main@l
+
+	/* Load TOC pointer and jump to main() */
+	ld		%r2, 8(%r12)
+	b main

src/arch/ppc64/include/arch/byteorder.h

@@ -3,6 +3,9 @@
 #ifndef _BYTEORDER_H
 #define _BYTEORDER_H
 
-#define __LITTLE_ENDIAN 1234
+#define __BIG_ENDIAN 4321
+
+#define PPC_BIT(bit)		(0x8000000000000000UL >> (bit))
+#define PPC_BITMASK(bs,be)	((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
 
 #endif /* _BYTEORDER_H */