diff --git a/spec/cpu32.typ b/spec/cpu32.typ
index e5e8963bc..a3c639cc7 100644
--- a/spec/cpu32.typ
+++ b/spec/cpu32.typ
@@ -45,6 +45,7 @@ provide these below.
 
 Most constraints correspond to those already present in the CPU, and we present them here first,
 including some updates to the range checking corresponding to the differing types.
+We also need to make sure that for padding rows ($mu = 0$), no side effects can occur.
 
 #render_constraint_table(chip, config, groups: ("decode", "range", "alu", "mem", "logup"))
 
diff --git a/spec/src/cpu32.toml b/spec/src/cpu32.toml
index f26ce0e8c..72386685e 100644
--- a/spec/src/cpu32.toml
+++ b/spec/src/cpu32.toml
@@ -350,6 +350,21 @@ multiplicity = "write_register"
 [[constraint_groups]]
 name = "logup"
 
+[[constraints.logup]]
+kind = "arith"
+constraint = "$#`!μ` => #`read_register1 = 0`$"
+poly = ["*", ["not", "μ"], "read_register1"]
+
+[[constraints.logup]]
+kind = "arith"
+constraint = "$#`!μ` => #`read_register2 = 0`$"
+poly = ["*", ["not", "μ"], "read_register2"]
+
+[[constraints.logup]]
+kind = "arith"
+constraint = "$#`!μ` => #`write_register = 0`$"
+poly = ["*", ["not", "μ"], "write_register"]
+
 [[constraints.logup]]
 kind = "interaction"
 tag = "CPU32"