From a2983ff3d54b94bac7a7e415cf5824ed0d39bfd5 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Tue, 18 Aug 2026 15:51:15 -0700
Subject: [PATCH] Explicitly truncate wide-RHS assignments

Addresses #92 without backwards incompatibility.

Signed-off-by: Andrew Waterman <andrew@sifive.com>
---
 hardfloat/src/main/scala/DivSqrtRecFN_small.scala | 2 +-
 hardfloat/src/main/scala/MulAddRecFN.scala        | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hardfloat/src/main/scala/DivSqrtRecFN_small.scala b/hardfloat/src/main/scala/DivSqrtRecFN_small.scala
index 2d79a18..7f65d66 100644
--- a/hardfloat/src/main/scala/DivSqrtRecFN_small.scala
+++ b/hardfloat/src/main/scala/DivSqrtRecFN_small.scala
@@ -357,7 +357,7 @@ class
             0.U
         ) |
         Mux(! inReady, rem_Z<<1, 0.U)
-    val bitMask = (1.U<<cycleNum)>>2
+    val bitMask = (1.U<<cycleNum)(sigWidth + 2, 0)>>2
     val trialTerm =
         Mux(inReady && ! io.sqrtOp,  rawB_S.sig<<1,                 0.U) |
         Mux(inReady && evenSqrt_S,   (BigInt(1)<<sigWidth).U,       0.U) |
diff --git a/hardfloat/src/main/scala/MulAddRecFN.scala b/hardfloat/src/main/scala/MulAddRecFN.scala
index bd49cc3..27996b8 100644
--- a/hardfloat/src/main/scala/MulAddRecFN.scala
+++ b/hardfloat/src/main/scala/MulAddRecFN.scala
@@ -138,8 +138,8 @@ class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
 
     //------------------------------------------------------------------------
     //------------------------------------------------------------------------
-    io.mulAddA := rawA.sig
-    io.mulAddB := rawB.sig
+    io.mulAddA := rawA.sig(sigWidth - 1, 0)
+    io.mulAddB := rawB.sig(sigWidth - 1, 0)
     io.mulAddC := alignedSigC(sigWidth * 2, 1)
 
     io.toPostMul.isSigNaNAny :=
@@ -155,7 +155,7 @@ class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
     io.toPostMul.isInfC    := rawC.isInf
     io.toPostMul.isZeroC   := rawC.isZero
     io.toPostMul.sExpSum   :=
-        Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
+        Mux(CIsDominant, rawC.sExp, (sExpAlignedProd - sigWidth.S)(expWidth + 1, 0).asSInt)
     io.toPostMul.doSubMags := doSubMags
     io.toPostMul.CIsDominant := CIsDominant
     io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)