acp_7_x: clk: power PLL and set max clock at platform init

Power the Audio PLL and request CLK_MAX_CPU_HZ in platform_init so
the DSP is at full clock before DMA/IPC init. Do not send the same
PMFW mailbox from the D0/D3 clock sequences.

Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>

Author: DINESHKUMARK1

src/platform/amd/acp_7_x/lib/clk.c

@@ -222,8 +222,7 @@ void acp_clk_d0_sequence(uint32_t clock_freq)
 {
 	clk_tick_cnt_config_reg_t clk_tick_config;
 
-	/* Send message to PMFW to power on Audio PLL */
-	mp1_mailbox_send(ACPSMC_MSG_PllPowerState, ACP_AUDIOPLL_POWER_ON_REQ);
+	/* Audio PLL is powered on in platform_init(). */
 
 	/* Enable clk tick count */
 	clk_tick_config.u32All = acp_reg_read_via_smn(CLK_TICK_CNT_CONFIG_REG, sizeof(uint32_t));
@@ -257,8 +256,7 @@ void acp_clk_d3_sequence(void)
 	acp_reg_write_via_smn(mmCLK6_CLK1_BYPASS_CNTL, bypass_cntl.u32All, sizeof(uint32_t));
 	/* mp1_mailbox_send(ACPSMC_MSG_PllPowerState, ACP_AUDIOPLL_POWER_OFF_REQ); */
 
-	/* Send message to PMFW to power off Audio PLL */
-	mp1_mailbox_send(ACPSMC_MSG_PllPowerState, ACP_AUDIOPLL_POWER_OFF_REQ_WITH_WOV_EN);
+	/* Leave Audio PLL powered; D3 does not request PMFW power-off. */
 }
 
 void change_clock_notify(uint32_t clock_freq)

src/platform/amd/acp_7_x/platform.c

@@ -42,6 +42,7 @@ LOG_MODULE_REGISTER(platform_file, CONFIG_SOF_LOG_LEVEL);
 
 #define INTERRUPT_DISABLE 0
 extern void acp_dsp_to_host_intr_trig(void);
+extern uint32_t mp1_mailbox_send(uint32_t reg_id, uint32_t value);
 struct sof;
 static const struct sof_ipc_fw_ready ready
 	__attribute__((section(".fw_ready"))) = {
@@ -149,6 +150,8 @@ int platform_init(struct sof *sof)
 
 	/*CONFIG_SYSTICK_PERIOD hardcoded as 200000*/
 	sa_init(sof, 200000);
+	mp1_mailbox_send(ACPSMC_MSG_PllPowerState, ACP_AUDIOPLL_POWER_ON_REQ);
+	acp_change_clock_notify(CLK_MAX_CPU_HZ);
 	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
 	/* init DMA */
 	ret = dmac_init(sof);