diff --git a/compiler/rustc_codegen_cranelift/src/intrinsics/llvm.rs b/compiler/rustc_codegen_cranelift/src/intrinsics/llvm.rs
index 2dee9176936fd..9ec84d135dc8f 100644
--- a/compiler/rustc_codegen_cranelift/src/intrinsics/llvm.rs
+++ b/compiler/rustc_codegen_cranelift/src/intrinsics/llvm.rs
@@ -19,7 +19,7 @@ pub(crate) fn codegen_llvm_intrinsic_call<'tcx>(
     }
 
     match intrinsic {
-        "llvm.prefetch" => {
+        "llvm.prefetch.p0" => {
             // Nothing to do. This is merely a perf hint.
         }
 
diff --git a/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs b/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs
index d58697f1bf270..41efe3e8209bf 100644
--- a/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs
+++ b/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs
@@ -1044,7 +1044,7 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
 #[cfg(feature = "master")]
 pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> {
     let gcc_name = match name {
-        "llvm.prefetch" => {
+        "llvm.prefetch.p0" => {
             let gcc_name = "__builtin_prefetch";
             let func = cx.context.get_builtin_function(gcc_name);
             cx.functions.borrow_mut().insert(gcc_name.to_string(), func);
diff --git a/compiler/rustc_codegen_llvm/src/intrinsic.rs b/compiler/rustc_codegen_llvm/src/intrinsic.rs
index 0b03d6862ca84..4ec398a6ec27d 100644
--- a/compiler/rustc_codegen_llvm/src/intrinsic.rs
+++ b/compiler/rustc_codegen_llvm/src/intrinsic.rs
@@ -402,7 +402,7 @@ impl<'ll, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
                 let ptr = args[0].immediate();
                 let locality = fn_args.const_at(1).to_leaf().to_i32();
                 self.call_intrinsic(
-                    "llvm.prefetch",
+                    "llvm.prefetch.p0",
                     &[self.val_ty(ptr)],
                     &[
                         ptr,
diff --git a/library/stdarch/.github/workflows/main.yml b/library/stdarch/.github/workflows/main.yml
index 98f6b842d135f..6333b32ab8ad4 100644
--- a/library/stdarch/.github/workflows/main.yml
+++ b/library/stdarch/.github/workflows/main.yml
@@ -337,6 +337,8 @@ jobs:
         cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lasx.spec
         git diff --exit-code
     - name: Check hexagon
+      env:
+        STDARCH_GEN_MODE: check
       run: |
         cargo run -p stdarch-gen-hexagon --release
         git diff --exit-code
diff --git a/library/stdarch/Cargo.lock b/library/stdarch/Cargo.lock
index a1c31fa9f0cea..c8cfc21a5a1a1 100644
--- a/library/stdarch/Cargo.lock
+++ b/library/stdarch/Cargo.lock
@@ -268,6 +268,22 @@ version = "1.0.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f"
 
+[[package]]
+name = "errno"
+version = "0.3.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "39cab71617ae0d63f51a36d69f866391735b51691dbda63cf6f96d042b63efeb"
+dependencies = [
+ "libc",
+ "windows-sys",
+]
+
+[[package]]
+name = "fastrand"
+version = "2.4.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9f1f227452a390804cdb637b74a86990f2a7d7ba4b7d5693aac9b4dd6defd8d6"
+
 [[package]]
 name = "find-msvc-tools"
 version = "0.1.9"
@@ -282,13 +298,14 @@ checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2"
 
 [[package]]
 name = "getrandom"
-version = "0.2.17"
+version = "0.3.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ff2abc00be7fca6ebc474524697ae276ad847ad0a6b3faa4bcb027e9a4614ad0"
+checksum = "899def5c37c4fd7b2664648c28120ecec138e4d395b459e5ca34f9cce2dd77fd"
 dependencies = [
  "cfg-if",
  "libc",
- "wasi",
+ "r-efi 5.3.0",
+ "wasip2",
 ]
 
 [[package]]
@@ -299,7 +316,7 @@ checksum = "0de51e6874e94e7bf76d726fc5d13ba782deca734ff60d5bb2fb2607c7406555"
 dependencies = [
  "cfg-if",
  "libc",
- "r-efi",
+ "r-efi 6.0.0",
  "rand_core 0.10.0",
  "wasip2",
  "wasip3",
@@ -445,6 +462,12 @@ version = "0.5.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0717cef1bc8b636c6e1c1bbdefc09e6322da8a9321966e8928ef80d20f7f770f"
 
+[[package]]
+name = "linux-raw-sys"
+version = "0.12.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "32a66949e030da00e8c7d4434b251670a91556f4144941d37452769c25d58a53"
+
 [[package]]
 name = "log"
 version = "0.4.29"
@@ -457,6 +480,12 @@ version = "2.8.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79"
 
+[[package]]
+name = "once_cell"
+version = "1.21.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9f7c3e4beb33f85d45ae3e3a1792185706c8e16d043238c593331cc7cd313b50"
+
 [[package]]
 name = "once_cell_polyfill"
 version = "1.70.2"
@@ -529,7 +558,7 @@ checksum = "95c589f335db0f6aaa168a7cd27b1fc6920f5e1470c804f814d9cd6e62a0f70b"
 dependencies = [
  "env_logger 0.11.10",
  "log",
- "rand 0.10.0",
+ "rand 0.10.1",
 ]
 
 [[package]]
@@ -541,6 +570,12 @@ dependencies = [
  "proc-macro2",
 ]
 
+[[package]]
+name = "r-efi"
+version = "5.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f"
+
 [[package]]
 name = "r-efi"
 version = "6.0.0"
@@ -549,20 +584,19 @@ checksum = "f8dcc9c7d52a811697d2151c701e0d08956f92b0e24136cf4cf27b57a6a0d9bf"
 
 [[package]]
 name = "rand"
-version = "0.8.5"
+version = "0.9.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "34af8d1a0e25924bc5b7c43c079c942339d8f0a8b57c39049bef581b46327404"
+checksum = "44c5af06bb1b7d3216d91932aed5265164bf384dc89cd6ba05cf59a35f5f76ea"
 dependencies = [
- "libc",
  "rand_chacha",
- "rand_core 0.6.4",
+ "rand_core 0.9.5",
 ]
 
 [[package]]
 name = "rand"
-version = "0.10.0"
+version = "0.10.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bc266eb313df6c5c09c1c7b1fbe2510961e5bcd3add930c1e31f7ed9da0feff8"
+checksum = "d2e8e8bcc7961af1fdac401278c6a831614941f6164ee3bf4ce61b7edb162207"
 dependencies = [
  "getrandom 0.4.2",
  "rand_core 0.10.0",
@@ -570,21 +604,21 @@ dependencies = [
 
 [[package]]
 name = "rand_chacha"
-version = "0.3.1"
+version = "0.9.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e6c10a63a0fa32252be49d21e7709d4d4baf8d231c2dbce1eaa8141b9b127d88"
+checksum = "d3022b5f1df60f26e1ffddd6c66e8aa15de382ae63b3a0c1bfc0e4d3e3f325cb"
 dependencies = [
  "ppv-lite86",
- "rand_core 0.6.4",
+ "rand_core 0.9.5",
 ]
 
 [[package]]
 name = "rand_core"
-version = "0.6.4"
+version = "0.9.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c"
+checksum = "76afc826de14238e6e8c374ddcc1fa19e374fd8dd986b0d2af0d02377261d83c"
 dependencies = [
- "getrandom 0.2.17",
+ "getrandom 0.3.4",
 ]
 
 [[package]]
@@ -648,6 +682,19 @@ version = "0.1.27"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d"
 
+[[package]]
+name = "rustix"
+version = "1.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b6fe4565b9518b83ef4f91bb47ce29620ca828bd32cb7e408f0062e9930ba190"
+dependencies = [
+ "bitflags",
+ "errno",
+ "libc",
+ "linux-raw-sys",
+ "windows-sys",
+]
+
 [[package]]
 name = "ryu"
 version = "1.0.23"
@@ -787,11 +834,19 @@ dependencies = [
  "walkdir",
 ]
 
+[[package]]
+name = "stdarch-gen-common"
+version = "0.1.0"
+dependencies = [
+ "tempfile",
+]
+
 [[package]]
 name = "stdarch-gen-hexagon"
 version = "0.1.0"
 dependencies = [
  "regex",
+ "stdarch-gen-common",
 ]
 
 [[package]]
@@ -805,7 +860,7 @@ dependencies = [
 name = "stdarch-gen-loongarch"
 version = "0.1.0"
 dependencies = [
- "rand 0.8.5",
+ "rand 0.9.4",
 ]
 
 [[package]]
@@ -838,7 +893,7 @@ version = "0.0.0"
 dependencies = [
  "core_arch",
  "quickcheck",
- "rand 0.8.5",
+ "rand 0.9.4",
 ]
 
 [[package]]
@@ -864,6 +919,19 @@ version = "0.6.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "43d0e35dc7d73976a53c7e6d7d177ef804a0c0ee774ec77bcc520c2216fd7cbe"
 
+[[package]]
+name = "tempfile"
+version = "3.27.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "32497e9a4c7b38532efcdebeef879707aa9f794296a4f0244f6f69e9bc8574bd"
+dependencies = [
+ "fastrand",
+ "getrandom 0.4.2",
+ "once_cell",
+ "rustix",
+ "windows-sys",
+]
+
 [[package]]
 name = "termcolor"
 version = "1.4.1"
@@ -921,12 +989,6 @@ dependencies = [
  "winapi-util",
 ]
 
-[[package]]
-name = "wasi"
-version = "0.11.1+wasi-snapshot-preview1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b"
-
 [[package]]
 name = "wasip2"
 version = "1.0.2+wasi-0.2.9"
diff --git a/library/stdarch/ci/intrinsic-test.sh b/library/stdarch/ci/intrinsic-test.sh
index 0441611f38fd2..8de7a4cfa5221 100755
--- a/library/stdarch/ci/intrinsic-test.sh
+++ b/library/stdarch/ci/intrinsic-test.sh
@@ -1,13 +1,19 @@
 #!/usr/bin/env sh
 
-set -ex
-
 if [ $# -lt 2 ]; then
-    >&2 echo "Usage: $0 <TARGET> <CC>"
+    >&2 echo "Usage: $0 <TARGET> <CC> <..args for \`cargo test\`..>"
     exit 1
 fi
 
-case ${2} in
+set -ex
+
+# Pop both arguments and leave "$@" as containing args to be forwarded to `cargo test`
+TARGET="$1"
+shift
+CC_KIND="$1"
+shift
+
+case ${CC_KIND} in
     clang)
         export CC="${CLANG_PATH}"
         CC_ARG_STYLE=clang
@@ -22,7 +28,7 @@ case ${2} in
         CC_ARG_STYLE=clang
         ;;
     *)
-        >&2 echo "Unknown compiler: ${2}"
+        >&2 echo "Unknown compiler: ${CC_KIND}"
         exit 1
         ;;
 esac
@@ -35,7 +41,7 @@ echo "PROFILE=${PROFILE}"
 
 INTRINSIC_TEST="--manifest-path=crates/intrinsic-test/Cargo.toml"
 
-case ${1} in
+case ${TARGET} in
     aarch64_be*)
         export CFLAGS="-I${AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc/usr/include --sysroot={AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc -Wno-nonportable-vector-initialization"
         ARCH=aarch64_be
@@ -60,24 +66,25 @@ case ${1} in
 
 esac
 
-case "${1}" in
+case "${TARGET}" in
     x86_64-unknown-linux-gnu*)
         env -u CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER \
             cargo run "${INTRINSIC_TEST}" --release \
             --bin intrinsic-test -- intrinsics_data/x86-intel.xml \
             --skip "crates/intrinsic-test/missing_${ARCH}_common.txt" \
-            --skip "crates/intrinsic-test/missing_${ARCH}_${2}.txt" \
-            --target "${1}" \
+            --skip "crates/intrinsic-test/missing_${ARCH}_${CC_KIND}.txt" \
+            --target "${TARGET}" \
             --cc-arg-style "${CC_ARG_STYLE}"
         ;;
     *)
         cargo run "${INTRINSIC_TEST}" --release \
             --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \
             --skip "crates/intrinsic-test/missing_${ARCH}_common.txt" \
-            --skip "crates/intrinsic-test/missing_${ARCH}_${2}.txt" \
-            --target "${1}" \
+            --skip "crates/intrinsic-test/missing_${ARCH}_${CC_KIND}.txt" \
+            --target "${TARGET}" \
             --cc-arg-style "${CC_ARG_STYLE}"
         ;;
 esac
 
-cargo test --manifest-path=rust_programs/Cargo.toml --target "${1}" --profile "${PROFILE}" --tests
+cargo test --manifest-path=rust_programs/Cargo.toml --target "${TARGET}" --profile "${PROFILE}" \
+    --tests "$@"
diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
index 8d701d9b88056..1b5b17e538bde 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
@@ -11903,7 +11903,7 @@ pub unsafe fn vluti4q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
     unsafe extern "unadjusted" {
         #[cfg_attr(
             any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.vluti4q.lane.v8i8"
+            link_name = "llvm.aarch64.neon.vluti4q.lane.v16i8"
         )]
         fn _vluti4q_lane_s8(a: int8x16_t, b: uint8x8_t, n: i32) -> int8x16_t;
     }
diff --git a/library/stdarch/crates/core_arch/src/aarch64/prefetch.rs b/library/stdarch/crates/core_arch/src/aarch64/prefetch.rs
index 4dcbc9549f115..88e5c0987f34d 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/prefetch.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/prefetch.rs
@@ -2,7 +2,7 @@
 use stdarch_test::assert_instr;
 
 unsafe extern "unadjusted" {
-    #[link_name = "llvm.prefetch"]
+    #[link_name = "llvm.prefetch.p0"]
     fn prefetch(p: *const i8, rw: i32, loc: i32, ty: i32);
 }
 
diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs
index e1157f3440cfb..ac3070918a025 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs
@@ -1844,7 +1844,7 @@ pub fn svadrd_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint
 #[cfg_attr(test, assert_instr(and))]
 pub fn svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.z.nvx16i1")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.z.nxv16i1")]
         fn _svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
     unsafe { _svand_b_z(pg, op1, op2) }
@@ -2936,7 +2936,7 @@ pub fn svasrd_n_s64_z<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_
 #[cfg_attr(test, assert_instr(bic))]
 pub fn svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.z.nvx16i1")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.z.nxv16i1")]
         fn _svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
     unsafe { _svbic_b_z(pg, op1, op2) }
@@ -4560,7 +4560,7 @@ pub fn svcmla_lane_f32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
     unsafe extern "unadjusted" {
         #[cfg_attr(
             target_arch = "aarch64",
-            link_name = "llvm.aarch64.sve.fcmla.lane.x.nxv4f32"
+            link_name = "llvm.aarch64.sve.fcmla.lane.nxv4f32"
         )]
         fn _svcmla_lane_f32(
             op1: svfloat32_t,
@@ -7658,7 +7658,10 @@ pub fn svcvt_f64_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat64_t {
 #[cfg_attr(test, assert_instr(scvtf))]
 pub fn svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool_t, op: svint32_t) -> svfloat32_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f32i32")]
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.scvtf.nxv4f32.nxv4i32"
+        )]
         fn _svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t;
     }
     unsafe { _svcvt_f32_s32_m(inactive, pg.sve_into(), op) }
@@ -7682,66 +7685,137 @@ pub fn svcvt_f32_s32_z(pg: svbool_t, op: svint32_t) -> svfloat32_t {
     svcvt_f32_s32_m(svdup_n_f32(0.0), pg, op)
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_m)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_m)"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool_t, op: svuint32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ucvtf.nxv4f32.nxv4i32"
+        )]
+        fn _svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t;
+    }
+    unsafe { _svcvt_f32_u32_m(inactive, pg.sve_into(), op.as_signed()) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_x)"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f32_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat32_t {
+    unsafe { svcvt_f32_u32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_z)"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f32_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat32_t {
+    svcvt_f32_u32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_m)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
-pub fn svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool_t, op: svint64_t) -> svfloat32_t {
+pub fn svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool_t, op: svint64_t) -> svfloat64_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f32i64")]
-        fn _svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool2_t, op: svint64_t) -> svfloat32_t;
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.scvtf.nxv2f64.nxv2i64"
+        )]
+        fn _svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t;
     }
-    unsafe { _svcvt_f32_s64_m(inactive, pg.sve_into(), op) }
+    unsafe { _svcvt_f64_s64_m(inactive, pg.sve_into(), op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_x)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_x)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
-pub fn svcvt_f32_s64_x(pg: svbool_t, op: svint64_t) -> svfloat32_t {
-    unsafe { svcvt_f32_s64_m(transmute_unchecked(op), pg, op) }
+pub fn svcvt_f64_s64_x(pg: svbool_t, op: svint64_t) -> svfloat64_t {
+    unsafe { svcvt_f64_s64_m(transmute_unchecked(op), pg, op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_z)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_z)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
-pub fn svcvt_f32_s64_z(pg: svbool_t, op: svint64_t) -> svfloat32_t {
-    svcvt_f32_s64_m(svdup_n_f32(0.0), pg, op)
+pub fn svcvt_f64_s64_z(pg: svbool_t, op: svint64_t) -> svfloat64_t {
+    svcvt_f64_s64_m(svdup_n_f64(0.0), pg, op)
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_m)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_m)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
-pub fn svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool_t, op: svuint32_t) -> svfloat32_t {
+pub fn svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool_t, op: svuint64_t) -> svfloat64_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f32i32")]
-        fn _svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t;
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ucvtf.nxv2f64.nxv2i64"
+        )]
+        fn _svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t;
     }
-    unsafe { _svcvt_f32_u32_m(inactive, pg.sve_into(), op.as_signed()) }
+    unsafe { _svcvt_f64_u64_m(inactive, pg.sve_into(), op.as_signed()) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_x)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_x)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
-pub fn svcvt_f32_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat32_t {
-    unsafe { svcvt_f32_u32_m(transmute_unchecked(op), pg, op) }
+pub fn svcvt_f64_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat64_t {
+    unsafe { svcvt_f64_u64_m(transmute_unchecked(op), pg, op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_z)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_z)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
-pub fn svcvt_f32_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat32_t {
-    svcvt_f32_u32_m(svdup_n_f32(0.0), pg, op)
+pub fn svcvt_f64_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat64_t {
+    svcvt_f64_u64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_m)"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool_t, op: svint64_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f32i64")]
+        fn _svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool2_t, op: svint64_t) -> svfloat32_t;
+    }
+    unsafe { _svcvt_f32_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_x)"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f32_s64_x(pg: svbool_t, op: svint64_t) -> svfloat32_t {
+    unsafe { svcvt_f32_s64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_z)"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f32_s64_z(pg: svbool_t, op: svint64_t) -> svfloat32_t {
+    svcvt_f32_s64_m(svdup_n_f32(0.0), pg, op)
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_m)"]
@@ -7806,37 +7880,6 @@ pub fn svcvt_f64_s32_z(pg: svbool_t, op: svint32_t) -> svfloat64_t {
     svcvt_f64_s32_m(svdup_n_f64(0.0), pg, op)
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_m)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(scvtf))]
-pub fn svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool_t, op: svint64_t) -> svfloat64_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f64i64")]
-        fn _svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t;
-    }
-    unsafe { _svcvt_f64_s64_m(inactive, pg.sve_into(), op) }
-}
-#[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_x)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(scvtf))]
-pub fn svcvt_f64_s64_x(pg: svbool_t, op: svint64_t) -> svfloat64_t {
-    unsafe { svcvt_f64_s64_m(transmute_unchecked(op), pg, op) }
-}
-#[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_z)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(scvtf))]
-pub fn svcvt_f64_s64_z(pg: svbool_t, op: svint64_t) -> svfloat64_t {
-    svcvt_f64_s64_m(svdup_n_f64(0.0), pg, op)
-}
-#[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_m)"]
 #[inline]
 #[target_feature(enable = "sve")]
@@ -7868,190 +7911,202 @@ pub fn svcvt_f64_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat64_t {
     svcvt_f64_u32_m(svdup_n_f64(0.0), pg, op)
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_m)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_m)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(ucvtf))]
-pub fn svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool_t, op: svuint64_t) -> svfloat64_t {
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s32_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint32_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f64i64")]
-        fn _svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t;
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32"
+        )]
+        fn _svcvt_s32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t;
     }
-    unsafe { _svcvt_f64_u64_m(inactive, pg.sve_into(), op.as_signed()) }
+    unsafe { _svcvt_s32_f32_m(inactive, pg.sve_into(), op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_x)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_x)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(ucvtf))]
-pub fn svcvt_f64_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat64_t {
-    unsafe { svcvt_f64_u64_m(transmute_unchecked(op), pg, op) }
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s32_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t {
+    unsafe { svcvt_s32_f32_m(transmute_unchecked(op), pg, op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_z)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_z)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(ucvtf))]
-pub fn svcvt_f64_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat64_t {
-    svcvt_f64_u64_m(svdup_n_f64(0.0), pg, op)
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s32_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t {
+    svcvt_s32_f32_m(svdup_n_s32(0), pg, op)
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_m)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_m)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s32_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint32_t {
+pub fn svcvt_s64_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint64_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i32f32")]
-        fn _svcvt_s32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t;
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fcvtzs.nxv2i64.nxv2f64"
+        )]
+        fn _svcvt_s64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t;
     }
-    unsafe { _svcvt_s32_f32_m(inactive, pg.sve_into(), op) }
+    unsafe { _svcvt_s64_f64_m(inactive, pg.sve_into(), op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_x)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_x)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s32_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t {
-    unsafe { svcvt_s32_f32_m(transmute_unchecked(op), pg, op) }
+pub fn svcvt_s64_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t {
+    unsafe { svcvt_s64_f64_m(transmute_unchecked(op), pg, op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_z)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_z)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s32_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t {
-    svcvt_s32_f32_m(svdup_n_s32(0), pg, op)
+pub fn svcvt_s64_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t {
+    svcvt_s64_f64_m(svdup_n_s64(0), pg, op)
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_m)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_m)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s32_f64_m(inactive: svint32_t, pg: svbool_t, op: svfloat64_t) -> svint32_t {
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u32_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuint32_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i32f64")]
-        fn _svcvt_s32_f64_m(inactive: svint32_t, pg: svbool2_t, op: svfloat64_t) -> svint32_t;
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fcvtzu.nxv4i32.nxv4f32"
+        )]
+        fn _svcvt_u32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t;
     }
-    unsafe { _svcvt_s32_f64_m(inactive, pg.sve_into(), op) }
+    unsafe { _svcvt_u32_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_x)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_x)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s32_f64_x(pg: svbool_t, op: svfloat64_t) -> svint32_t {
-    unsafe { svcvt_s32_f64_m(transmute_unchecked(op), pg, op) }
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u32_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
+    unsafe { svcvt_u32_f32_m(transmute_unchecked(op), pg, op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_z)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_z)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s32_f64_z(pg: svbool_t, op: svfloat64_t) -> svint32_t {
-    svcvt_s32_f64_m(svdup_n_s32(0), pg, op)
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u32_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
+    svcvt_u32_f32_m(svdup_n_u32(0), pg, op)
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_m)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_m)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s64_f32_m(inactive: svint64_t, pg: svbool_t, op: svfloat32_t) -> svint64_t {
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u64_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuint64_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i64f32")]
-        fn _svcvt_s64_f32_m(inactive: svint64_t, pg: svbool2_t, op: svfloat32_t) -> svint64_t;
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fcvtzu.nxv2i64.nxv2f64"
+        )]
+        fn _svcvt_u64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t;
     }
-    unsafe { _svcvt_s64_f32_m(inactive, pg.sve_into(), op) }
+    unsafe { _svcvt_u64_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_x)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_x)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s64_f32_x(pg: svbool_t, op: svfloat32_t) -> svint64_t {
-    unsafe { svcvt_s64_f32_m(transmute_unchecked(op), pg, op) }
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u64_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
+    unsafe { svcvt_u64_f64_m(transmute_unchecked(op), pg, op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_z)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_z)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s64_f32_z(pg: svbool_t, op: svfloat32_t) -> svint64_t {
-    svcvt_s64_f32_m(svdup_n_s64(0), pg, op)
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u64_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
+    svcvt_u64_f64_m(svdup_n_u64(0), pg, op)
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_m)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_m)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s64_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint64_t {
+pub fn svcvt_s32_f64_m(inactive: svint32_t, pg: svbool_t, op: svfloat64_t) -> svint32_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i64f64")]
-        fn _svcvt_s64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i32f64")]
+        fn _svcvt_s32_f64_m(inactive: svint32_t, pg: svbool2_t, op: svfloat64_t) -> svint32_t;
     }
-    unsafe { _svcvt_s64_f64_m(inactive, pg.sve_into(), op) }
+    unsafe { _svcvt_s32_f64_m(inactive, pg.sve_into(), op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_x)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_x)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s64_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t {
-    unsafe { svcvt_s64_f64_m(transmute_unchecked(op), pg, op) }
+pub fn svcvt_s32_f64_x(pg: svbool_t, op: svfloat64_t) -> svint32_t {
+    unsafe { svcvt_s32_f64_m(transmute_unchecked(op), pg, op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_z)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_z)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
-pub fn svcvt_s64_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t {
-    svcvt_s64_f64_m(svdup_n_s64(0), pg, op)
+pub fn svcvt_s32_f64_z(pg: svbool_t, op: svfloat64_t) -> svint32_t {
+    svcvt_s32_f64_m(svdup_n_s32(0), pg, op)
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_m)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_m)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzu))]
-pub fn svcvt_u32_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuint32_t {
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s64_f32_m(inactive: svint64_t, pg: svbool_t, op: svfloat32_t) -> svint64_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i32f32")]
-        fn _svcvt_u32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i64f32")]
+        fn _svcvt_s64_f32_m(inactive: svint64_t, pg: svbool2_t, op: svfloat32_t) -> svint64_t;
     }
-    unsafe { _svcvt_u32_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+    unsafe { _svcvt_s64_f32_m(inactive, pg.sve_into(), op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_x)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_x)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzu))]
-pub fn svcvt_u32_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
-    unsafe { svcvt_u32_f32_m(transmute_unchecked(op), pg, op) }
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s64_f32_x(pg: svbool_t, op: svfloat32_t) -> svint64_t {
+    unsafe { svcvt_s64_f32_m(transmute_unchecked(op), pg, op) }
 }
 #[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_z)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_z)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzu))]
-pub fn svcvt_u32_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
-    svcvt_u32_f32_m(svdup_n_u32(0), pg, op)
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s64_f32_z(pg: svbool_t, op: svfloat32_t) -> svint64_t {
+    svcvt_s64_f32_m(svdup_n_s64(0), pg, op)
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_m)"]
@@ -8115,37 +8170,6 @@ pub fn svcvt_u64_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint64_t {
 pub fn svcvt_u64_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint64_t {
     svcvt_u64_f32_m(svdup_n_u64(0), pg, op)
 }
-#[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_m)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzu))]
-pub fn svcvt_u64_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuint64_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i64f64")]
-        fn _svcvt_u64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t;
-    }
-    unsafe { _svcvt_u64_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
-}
-#[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_x)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzu))]
-pub fn svcvt_u64_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
-    unsafe { svcvt_u64_f64_m(transmute_unchecked(op), pg, op) }
-}
-#[doc = "Floating-point convert"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_z)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(fcvtzu))]
-pub fn svcvt_u64_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
-    svcvt_u64_f64_m(svdup_n_u64(0), pg, op)
-}
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_m)"]
 #[inline]
@@ -10041,7 +10065,7 @@ pub fn svdupq_n_u8(
 #[cfg_attr(test, assert_instr(eor))]
 pub fn sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.z.nvx16i1")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.z.nxv16i1")]
         fn _sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
     unsafe { _sveor_b_z(pg, op1, op2) }
@@ -10592,7 +10616,7 @@ pub fn svexpa_f32(op: svuint32_t) -> svfloat32_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
             target_arch = "aarch64",
-            link_name = "llvm.aarch64.sve.fexpa.x.nxv4f32 "
+            link_name = "llvm.aarch64.sve.fexpa.x.nxv4f32"
         )]
         fn _svexpa_f32(op: svint32_t) -> svfloat32_t;
     }
@@ -10608,7 +10632,7 @@ pub fn svexpa_f64(op: svuint64_t) -> svfloat64_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
             target_arch = "aarch64",
-            link_name = "llvm.aarch64.sve.fexpa.x.nxv2f64 "
+            link_name = "llvm.aarch64.sve.fexpa.x.nxv2f64"
         )]
         fn _svexpa_f64(op: svint64_t) -> svfloat64_t;
     }
@@ -27372,7 +27396,10 @@ pub fn svmls_lane_f64<const IMM_INDEX: i32>(
 #[cfg_attr(test, assert_instr(fmmla))]
 pub fn svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svfloat32_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmmla.nxv4f32")]
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32"
+        )]
         fn _svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svfloat32_t;
     }
     unsafe { _svmmla_f32(op1, op2, op3) }
@@ -27385,7 +27412,10 @@ pub fn svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svflo
 #[cfg_attr(test, assert_instr(fmmla))]
 pub fn svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svfloat64_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmmla.nxv2f64")]
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64"
+        )]
         fn _svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svfloat64_t;
     }
     unsafe { _svmmla_f64(op1, op2, op3) }
@@ -30261,7 +30291,7 @@ pub fn svnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 #[cfg_attr(test, assert_instr(orn))]
 pub fn svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orn.z.nvx16i1")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orn.z.nxv16i1")]
         fn _svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
     unsafe { _svorn_b_z(pg, op1, op2) }
@@ -30274,7 +30304,7 @@ pub fn svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(orr))]
 pub fn svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.z.nvx16i1")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.z.nxv16i1")]
         fn _svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
     unsafe { _svorr_b_z(pg, op1, op2) }
@@ -34341,10 +34371,7 @@ pub fn svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 #[cfg_attr(test, assert_instr(frecpx))]
 pub fn svrecpx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(
-            target_arch = "aarch64",
-            link_name = "llvm.aarch64.sve.frecpx.x.nxv4f32"
-        )]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frecpx.nxv4f32")]
         fn _svrecpx_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
     }
     unsafe { _svrecpx_f32_m(inactive, pg.sve_into(), op) }
@@ -34375,10 +34402,7 @@ pub fn svrecpx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 #[cfg_attr(test, assert_instr(frecpx))]
 pub fn svrecpx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(
-            target_arch = "aarch64",
-            link_name = "llvm.aarch64.sve.frecpx.x.nxv2f64"
-        )]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frecpx.nxv2f64")]
         fn _svrecpx_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
     }
     unsafe { _svrecpx_f64_m(inactive, pg.sve_into(), op) }
@@ -35202,19 +35226,6 @@ pub fn svreinterpret_u64_u64(op: svuint64_t) -> svuint64_t {
     unsafe { crate::intrinsics::transmute_unchecked(op) }
 }
 #[doc = "Reverse all elements"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b8)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(rev))]
-pub fn svrev_b8(op: svbool_t) -> svbool_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv16i1")]
-        fn _svrev_b8(op: svbool_t) -> svbool_t;
-    }
-    unsafe { _svrev_b8(op) }
-}
-#[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b16)"]
 #[inline]
 #[target_feature(enable = "sve")]
@@ -35222,10 +35233,10 @@ pub fn svrev_b8(op: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_b16(op: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv8i1")]
-        fn _svrev_b16(op: svbool8_t) -> svbool8_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.b16")]
+        fn _svrev_b16(op: svbool_t) -> svbool_t;
     }
-    unsafe { _svrev_b16(op.sve_into()).sve_into() }
+    unsafe { _svrev_b16(op.sve_into()) }
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b32)"]
@@ -35235,10 +35246,10 @@ pub fn svrev_b16(op: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_b32(op: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv4i1")]
-        fn _svrev_b32(op: svbool4_t) -> svbool4_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.b32")]
+        fn _svrev_b32(op: svbool_t) -> svbool_t;
     }
-    unsafe { _svrev_b32(op.sve_into()).sve_into() }
+    unsafe { _svrev_b32(op.sve_into()) }
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b64)"]
@@ -35248,10 +35259,10 @@ pub fn svrev_b32(op: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_b64(op: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv2i1")]
-        fn _svrev_b64(op: svbool2_t) -> svbool2_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.b64")]
+        fn _svrev_b64(op: svbool_t) -> svbool_t;
     }
-    unsafe { _svrev_b64(op.sve_into()).sve_into() }
+    unsafe { _svrev_b64(op.sve_into()) }
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f32])"]
@@ -35367,6 +35378,19 @@ pub fn svrev_u32(op: svuint32_t) -> svuint32_t {
 pub fn svrev_u64(op: svuint64_t) -> svuint64_t {
     unsafe { svrev_s64(op.as_signed()).as_unsigned() }
 }
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_b8])"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_b8(op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv16i1")]
+        fn _svrev_b8(op: svbool_t) -> svbool_t;
+    }
+    unsafe { _svrev_b8(op) }
+}
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_m)"]
 #[inline]
@@ -43312,19 +43336,6 @@ pub fn svusmmla_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t
     unsafe { _svusmmla_s32(op1, op2.as_signed(), op3) }
 }
 #[doc = "Concatenate even elements from two inputs"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b8)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(uzp1))]
-pub fn svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv16i1")]
-        fn _svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
-    }
-    unsafe { _svuzp1_b8(op1, op2) }
-}
-#[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b16)"]
 #[inline]
 #[target_feature(enable = "sve")]
@@ -43332,10 +43343,10 @@ pub fn svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(uzp1))]
 pub fn svuzp1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv8i1")]
-        fn _svuzp1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.b16")]
+        fn _svuzp1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svuzp1_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svuzp1_b16(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b32)"]
@@ -43345,10 +43356,10 @@ pub fn svuzp1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(uzp1))]
 pub fn svuzp1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4i1")]
-        fn _svuzp1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.b32")]
+        fn _svuzp1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svuzp1_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svuzp1_b32(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b64)"]
@@ -43358,10 +43369,10 @@ pub fn svuzp1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(uzp1))]
 pub fn svuzp1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2i1")]
-        fn _svuzp1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.b64")]
+        fn _svuzp1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svuzp1_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svuzp1_b64(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f32])"]
@@ -43477,6 +43488,19 @@ pub fn svuzp1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 pub fn svuzp1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svuzp1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_b8])"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv16i1")]
+        fn _svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svuzp1_b8(op1, op2) }
+}
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f32])"]
 #[inline]
@@ -43592,19 +43616,6 @@ pub fn svuzp1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svuzp1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
 #[doc = "Concatenate odd elements from two inputs"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b8)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(uzp2))]
-pub fn svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv16i1")]
-        fn _svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
-    }
-    unsafe { _svuzp2_b8(op1, op2) }
-}
-#[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b16)"]
 #[inline]
 #[target_feature(enable = "sve")]
@@ -43612,10 +43623,10 @@ pub fn svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(uzp2))]
 pub fn svuzp2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv8i1")]
-        fn _svuzp2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.b16")]
+        fn _svuzp2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svuzp2_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svuzp2_b16(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b32)"]
@@ -43625,10 +43636,10 @@ pub fn svuzp2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(uzp2))]
 pub fn svuzp2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4i1")]
-        fn _svuzp2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.b32")]
+        fn _svuzp2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svuzp2_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svuzp2_b32(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b64)"]
@@ -43638,10 +43649,10 @@ pub fn svuzp2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(uzp2))]
 pub fn svuzp2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2i1")]
-        fn _svuzp2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.b64")]
+        fn _svuzp2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svuzp2_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svuzp2_b64(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f32])"]
@@ -43757,6 +43768,19 @@ pub fn svuzp2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 pub fn svuzp2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svuzp2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_b8])"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv16i1")]
+        fn _svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svuzp2_b8(op1, op2) }
+}
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f32])"]
 #[inline]
@@ -44397,19 +44421,6 @@ pub fn svwrffr(op: svbool_t) {
     unsafe { _svwrffr(op) }
 }
 #[doc = "Interleave elements from low halves of two inputs"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b8)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(zip1))]
-pub fn svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv16i1")]
-        fn _svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
-    }
-    unsafe { _svzip1_b8(op1, op2) }
-}
-#[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b16)"]
 #[inline]
 #[target_feature(enable = "sve")]
@@ -44417,10 +44428,10 @@ pub fn svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(zip1))]
 pub fn svzip1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv8i1")]
-        fn _svzip1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.b16")]
+        fn _svzip1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svzip1_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svzip1_b16(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b32)"]
@@ -44430,10 +44441,10 @@ pub fn svzip1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(zip1))]
 pub fn svzip1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4i1")]
-        fn _svzip1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.b32")]
+        fn _svzip1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svzip1_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svzip1_b32(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b64)"]
@@ -44443,10 +44454,10 @@ pub fn svzip1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(zip1))]
 pub fn svzip1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2i1")]
-        fn _svzip1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.b64")]
+        fn _svzip1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svzip1_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svzip1_b64(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f32])"]
@@ -44562,6 +44573,19 @@ pub fn svzip1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 pub fn svzip1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svzip1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_b8])"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv16i1")]
+        fn _svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svzip1_b8(op1, op2) }
+}
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f32])"]
 #[inline]
@@ -44677,19 +44701,6 @@ pub fn svzip1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svzip1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
 #[doc = "Interleave elements from high halves of two inputs"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b8)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(zip2))]
-pub fn svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv16i1")]
-        fn _svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
-    }
-    unsafe { _svzip2_b8(op1, op2) }
-}
-#[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b16)"]
 #[inline]
 #[target_feature(enable = "sve")]
@@ -44697,10 +44708,10 @@ pub fn svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(zip2))]
 pub fn svzip2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv8i1")]
-        fn _svzip2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.b16")]
+        fn _svzip2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svzip2_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svzip2_b16(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b32)"]
@@ -44710,10 +44721,10 @@ pub fn svzip2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(zip2))]
 pub fn svzip2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4i1")]
-        fn _svzip2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.b32")]
+        fn _svzip2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svzip2_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svzip2_b32(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b64)"]
@@ -44723,10 +44734,10 @@ pub fn svzip2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(zip2))]
 pub fn svzip2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2i1")]
-        fn _svzip2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.b64")]
+        fn _svzip2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svzip2_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svzip2_b64(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f32])"]
@@ -44842,6 +44853,19 @@ pub fn svzip2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 pub fn svzip2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svzip2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_b8])"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv16i1")]
+        fn _svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svzip2_b8(op1, op2) }
+}
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f32])"]
 #[inline]
diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve/mod.rs b/library/stdarch/crates/core_arch/src/aarch64/sve/mod.rs
index a3f70ab61c40f..f11ca660b15e2 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/sve/mod.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/sve/mod.rs
@@ -28,6 +28,14 @@ pub(super) trait SveInto<T>: Sized {
     unsafe fn sve_into(self) -> T;
 }
 
+impl<T> SveInto<T> for T {
+    #[inline]
+    #[target_feature(enable = "sve")]
+    unsafe fn sve_into(self) -> T {
+        self
+    }
+}
+
 macro_rules! impl_sve_type {
     ($(($v:vis, $elem_type:ty, $name:ident, $elt:literal))*) => ($(
         #[doc = concat!("Scalable vector of type ", stringify!($elem_type))]
@@ -130,7 +138,7 @@ macro_rules! impl_internal_sve_predicate {
             #[target_feature(enable = "sve")]
             unsafe fn sve_into(self) -> svbool_t {
                 #[allow(improper_ctypes)]
-                unsafe extern "C" {
+                unsafe extern "unadjusted" {
                     #[cfg_attr(
                         target_arch = "aarch64",
                         link_name = concat!("llvm.aarch64.sve.convert.to.svbool.nxv", $elt, "i1")
@@ -147,7 +155,7 @@ macro_rules! impl_internal_sve_predicate {
             #[target_feature(enable = "sve")]
             unsafe fn sve_into(self) -> $name {
                 #[allow(improper_ctypes)]
-                unsafe extern "C" {
+                unsafe extern "unadjusted" {
                     #[cfg_attr(
                         target_arch = "aarch64",
                         link_name = concat!("llvm.aarch64.sve.convert.from.svbool.nxv", $elt, "i1")
diff --git a/library/stdarch/crates/core_arch/src/hexagon/v128.rs b/library/stdarch/crates/core_arch/src/hexagon/v128.rs
index 1f0566af78ef3..1a1826ddda316 100644
--- a/library/stdarch/crates/core_arch/src/hexagon/v128.rs
+++ b/library/stdarch/crates/core_arch/src/hexagon/v128.rs
@@ -1,3 +1,4 @@
+// This code is automatically generated. DO NOT MODIFY.
 //! Hexagon HVX 128-byte vector mode intrinsics
 //!
 //! This module provides intrinsics for the Hexagon Vector Extensions (HVX)
diff --git a/library/stdarch/crates/core_arch/src/hexagon/v64.rs b/library/stdarch/crates/core_arch/src/hexagon/v64.rs
index e9b18b2fd8efe..3ac8b47079333 100644
--- a/library/stdarch/crates/core_arch/src/hexagon/v64.rs
+++ b/library/stdarch/crates/core_arch/src/hexagon/v64.rs
@@ -1,3 +1,4 @@
+// This code is automatically generated. DO NOT MODIFY.
 //! Hexagon HVX 64-byte vector mode intrinsics
 //!
 //! This module provides intrinsics for the Hexagon Vector Extensions (HVX)
diff --git a/library/stdarch/crates/core_arch/src/loongarch64/mod.rs b/library/stdarch/crates/core_arch/src/loongarch64/mod.rs
index 7e9f45f5e7b04..ffaa4225ba99d 100644
--- a/library/stdarch/crates/core_arch/src/loongarch64/mod.rs
+++ b/library/stdarch/crates/core_arch/src/loongarch64/mod.rs
@@ -62,56 +62,56 @@ unsafe extern "unadjusted" {
 
 /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
 #[inline(always)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+#[stable(feature = "stdarch_loongarch_crc", since = "CURRENT_RUSTC_VERSION")]
 pub fn crc_w_b_w(a: i8, b: i32) -> i32 {
-    unsafe { __crc_w_b_w(a.cast_unsigned() as i32, b) }
+    unsafe { __crc_w_b_w(a as i32, b) }
 }
 
 /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
 #[inline(always)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+#[stable(feature = "stdarch_loongarch_crc", since = "CURRENT_RUSTC_VERSION")]
 pub fn crc_w_h_w(a: i16, b: i32) -> i32 {
-    unsafe { __crc_w_h_w(a.cast_unsigned() as i32, b) }
+    unsafe { __crc_w_h_w(a as i32, b) }
 }
 
 /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
 #[inline(always)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+#[stable(feature = "stdarch_loongarch_crc", since = "CURRENT_RUSTC_VERSION")]
 pub fn crc_w_w_w(a: i32, b: i32) -> i32 {
     unsafe { __crc_w_w_w(a, b) }
 }
 
 /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
 #[inline(always)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+#[stable(feature = "stdarch_loongarch_crc", since = "CURRENT_RUSTC_VERSION")]
 pub fn crc_w_d_w(a: i64, b: i32) -> i32 {
     unsafe { __crc_w_d_w(a, b) }
 }
 
 /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
 #[inline(always)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+#[stable(feature = "stdarch_loongarch_crc", since = "CURRENT_RUSTC_VERSION")]
 pub fn crcc_w_b_w(a: i8, b: i32) -> i32 {
-    unsafe { __crcc_w_b_w(a.cast_unsigned() as i32, b) }
+    unsafe { __crcc_w_b_w(a as i32, b) }
 }
 
 /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
 #[inline(always)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+#[stable(feature = "stdarch_loongarch_crc", since = "CURRENT_RUSTC_VERSION")]
 pub fn crcc_w_h_w(a: i16, b: i32) -> i32 {
-    unsafe { __crcc_w_h_w(a.cast_unsigned() as i32, b) }
+    unsafe { __crcc_w_h_w(a as i32, b) }
 }
 
 /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
 #[inline(always)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+#[stable(feature = "stdarch_loongarch_crc", since = "CURRENT_RUSTC_VERSION")]
 pub fn crcc_w_w_w(a: i32, b: i32) -> i32 {
     unsafe { __crcc_w_w_w(a, b) }
 }
 
 /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
 #[inline(always)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+#[stable(feature = "stdarch_loongarch_crc", since = "CURRENT_RUSTC_VERSION")]
 pub fn crcc_w_d_w(a: i64, b: i32) -> i32 {
     unsafe { __crcc_w_d_w(a, b) }
 }
diff --git a/library/stdarch/crates/core_arch/src/mips/msa.rs b/library/stdarch/crates/core_arch/src/mips/msa.rs
index bc601baef9e2a..dab64319ccc3b 100644
--- a/library/stdarch/crates/core_arch/src/mips/msa.rs
+++ b/library/stdarch/crates/core_arch/src/mips/msa.rs
@@ -45,7 +45,7 @@ types! {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.mips.add.a.b"]
     fn msa_add_a_b(a: v16i8, b: v16i8) -> v16i8;
     #[link_name = "llvm.mips.add.a.h"]
diff --git a/library/stdarch/crates/core_arch/src/nvptx/mod.rs b/library/stdarch/crates/core_arch/src/nvptx/mod.rs
index b63a5d01a7a22..d22f3a25bf70e 100644
--- a/library/stdarch/crates/core_arch/src/nvptx/mod.rs
+++ b/library/stdarch/crates/core_arch/src/nvptx/mod.rs
@@ -19,9 +19,9 @@ mod packed;
 pub use packed::*;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
-    #[link_name = "llvm.nvvm.barrier0"]
-    fn syncthreads() -> ();
+unsafe extern "unadjusted" {
+    #[link_name = "llvm.nvvm.barrier.cta.sync.aligned.all"]
+    fn syncthreads(a: u32) -> ();
     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.x"]
     fn block_dim_x() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.y"]
@@ -54,7 +54,7 @@ unsafe extern "C" {
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
 pub unsafe fn _syncthreads() -> () {
-    syncthreads()
+    syncthreads(0)
 }
 
 /// x-th thread-block dimension.
diff --git a/library/stdarch/crates/core_arch/src/nvptx/packed.rs b/library/stdarch/crates/core_arch/src/nvptx/packed.rs
index 1c7e81268fc99..7e6c14bc993d9 100644
--- a/library/stdarch/crates/core_arch/src/nvptx/packed.rs
+++ b/library/stdarch/crates/core_arch/src/nvptx/packed.rs
@@ -7,7 +7,7 @@
 use crate::intrinsics::simd::*;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.minimum.v2f16"]
     fn llvm_f16x2_minimum(a: f16x2, b: f16x2) -> f16x2;
     #[link_name = "llvm.maximum.v2f16"]
diff --git a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
index 78ec39f91ff33..ccfed88a93c2a 100644
--- a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
+++ b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
@@ -96,7 +96,7 @@ impl From<vector_bool_int> for m32x4 {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.ppc.altivec.lvx"]
     fn lvx(p: *const i8) -> vector_unsigned_int;
 
diff --git a/library/stdarch/crates/core_arch/src/powerpc/vsx.rs b/library/stdarch/crates/core_arch/src/powerpc/vsx.rs
index 4a7b561a20c55..60cb2ad44cd4e 100644
--- a/library/stdarch/crates/core_arch/src/powerpc/vsx.rs
+++ b/library/stdarch/crates/core_arch/src/powerpc/vsx.rs
@@ -52,7 +52,7 @@ impl From<vector_bool_long> for m64x2 {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.ppc.altivec.vperm"]
     fn vperm(
         a: vector_signed_int,
diff --git a/library/stdarch/crates/core_arch/src/powerpc64/vsx.rs b/library/stdarch/crates/core_arch/src/powerpc64/vsx.rs
index 7b42be8653c55..9032e7795980f 100644
--- a/library/stdarch/crates/core_arch/src/powerpc64/vsx.rs
+++ b/library/stdarch/crates/core_arch/src/powerpc64/vsx.rs
@@ -17,7 +17,7 @@ use stdarch_test::assert_instr;
 use crate::mem::transmute;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.ppc.vsx.lxvl"]
     fn lxvl(a: *const u8, l: usize) -> vector_signed_int;
 
diff --git a/library/stdarch/crates/core_arch/src/wasm32/memory.rs b/library/stdarch/crates/core_arch/src/wasm32/memory.rs
index 90e9075e5136b..9d7b7287ede1b 100644
--- a/library/stdarch/crates/core_arch/src/wasm32/memory.rs
+++ b/library/stdarch/crates/core_arch/src/wasm32/memory.rs
@@ -2,9 +2,11 @@
 use stdarch_test::assert_instr;
 
 unsafe extern "unadjusted" {
-    #[link_name = "llvm.wasm.memory.grow"]
+    #[cfg_attr(target_pointer_width = "32", link_name = "llvm.wasm.memory.grow.i32")]
+    #[cfg_attr(target_pointer_width = "64", link_name = "llvm.wasm.memory.grow.i64")]
     fn llvm_memory_grow(mem: u32, pages: usize) -> usize;
-    #[link_name = "llvm.wasm.memory.size"]
+    #[cfg_attr(target_pointer_width = "32", link_name = "llvm.wasm.memory.size.i32")]
+    #[cfg_attr(target_pointer_width = "64", link_name = "llvm.wasm.memory.size.i64")]
     fn llvm_memory_size(mem: u32) -> usize;
 }
 
diff --git a/library/stdarch/crates/core_arch/src/x86/aes.rs b/library/stdarch/crates/core_arch/src/x86/aes.rs
index d07ab4dc2a01e..ecb09a6a9099f 100644
--- a/library/stdarch/crates/core_arch/src/x86/aes.rs
+++ b/library/stdarch/crates/core_arch/src/x86/aes.rs
@@ -13,7 +13,7 @@ use crate::core_arch::x86::__m128i;
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.aesni.aesdec"]
     fn aesdec(a: __m128i, round_key: __m128i) -> __m128i;
     #[link_name = "llvm.x86.aesni.aesdeclast"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx.rs b/library/stdarch/crates/core_arch/src/x86/avx.rs
index ef434205b52a0..f5ddff6457aea 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx.rs
@@ -3292,7 +3292,7 @@ pub const fn _mm256_cvtss_f32(a: __m256) -> f32 {
 
 // LLVM intrinsics used in the above functions
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx.round.pd.256"]
     fn roundpd256(a: __m256d, b: i32) -> __m256d;
     #[link_name = "llvm.x86.avx.round.ps.256"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx2.rs b/library/stdarch/crates/core_arch/src/x86/avx2.rs
index b49ad9522a412..6925ba8e27028 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx2.rs
@@ -3906,7 +3906,7 @@ pub const fn _mm256_extract_epi16<const INDEX: i32>(a: __m256i) -> i32 {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx2.pmadd.wd"]
     fn pmaddwd(a: i16x16, b: i16x16) -> i32x8;
     #[link_name = "llvm.x86.avx2.pmadd.ub.sw"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs b/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs
index 8d944f5ba817b..230a4f3754cad 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs
@@ -9,7 +9,7 @@ use crate::intrinsics::simd::*;
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512bf16.cvtne2ps2bf16.128"]
     fn cvtne2ps2bf16(a: f32x4, b: f32x4) -> i16x8;
     #[link_name = "llvm.x86.avx512bf16.cvtne2ps2bf16.256"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bitalg.rs b/library/stdarch/crates/core_arch/src/x86/avx512bitalg.rs
index dd211854afbb4..344130fb6e720 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512bitalg.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512bitalg.rs
@@ -27,7 +27,7 @@ use crate::mem::transmute;
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.vpshufbitqmb.512"]
     fn bitshuffle_512(data: i8x64, indices: i8x64) -> __mmask64;
     #[link_name = "llvm.x86.avx512.vpshufbitqmb.256"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs
index 659d6c3be88e7..50d57b4964489 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs
@@ -12764,7 +12764,7 @@ pub unsafe fn _mm_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a:
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.pmul.hr.sw.512"]
     fn vpmulhrsw(a: i16x32, b: i16x32) -> i16x32;
 
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512cd.rs b/library/stdarch/crates/core_arch/src/x86/avx512cd.rs
index 4082433e70759..378bc3617ed63 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512cd.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512cd.rs
@@ -563,7 +563,7 @@ pub const fn _mm_maskz_lzcnt_epi64(k: __mmask8, a: __m128i) -> __m128i {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.conflict.d.512"]
     fn vpconflictd(a: i32x16) -> i32x16;
     #[link_name = "llvm.x86.avx512.conflict.d.256"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs
index 0b322c8b83c7b..5fe40b7541549 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs
@@ -7235,7 +7235,7 @@ pub fn _mm_mask_fpclass_ss_mask<const IMM8: i32>(k1: __mmask8, a: __m128) -> __m
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.sitofp.round.v2f64.v2i64"]
     fn vcvtqq2pd_128(a: i64x2, rounding: i32) -> f64x2;
     #[link_name = "llvm.x86.avx512.sitofp.round.v4f64.v4i64"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512f.rs b/library/stdarch/crates/core_arch/src/x86/avx512f.rs
index 9b90ad60a39fb..76e7297bcda40 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512f.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512f.rs
@@ -44215,7 +44215,7 @@ pub const _MM_PERM_DDDC: _MM_PERM_ENUM = 0xFE;
 pub const _MM_PERM_DDDD: _MM_PERM_ENUM = 0xFF;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.sqrt.ps.512"]
     fn vsqrtps(a: f32x16, rounding: i32) -> f32x16;
     #[link_name = "llvm.x86.avx512.sqrt.pd.512"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512ifma.rs b/library/stdarch/crates/core_arch/src/x86/avx512ifma.rs
index 5ce28565d1085..262215e62c43d 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512ifma.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512ifma.rs
@@ -347,7 +347,7 @@ pub fn _mm_maskz_madd52lo_epu64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i)
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.vpmadd52l.uq.128"]
     fn vpmadd52luq_128(z: __m128i, x: __m128i, y: __m128i) -> __m128i;
     #[link_name = "llvm.x86.avx512.vpmadd52h.uq.128"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vbmi.rs b/library/stdarch/crates/core_arch/src/x86/avx512vbmi.rs
index d9ad14ef00ddb..141a8c8aec2bc 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512vbmi.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512vbmi.rs
@@ -453,7 +453,7 @@ pub fn _mm_maskz_multishift_epi64_epi8(k: __mmask16, a: __m128i, b: __m128i) ->
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.vpermi2var.qi.512"]
     fn vpermi2b(a: i8x64, idx: i8x64, b: i8x64) -> i8x64;
     #[link_name = "llvm.x86.avx512.vpermi2var.qi.256"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs b/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs
index 78a50b90c8614..0a4accc2f70fb 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs
@@ -2383,7 +2383,7 @@ pub const fn _mm_maskz_shrdi_epi16<const IMM8: i32>(
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.mask.compress.store.w.512"]
     fn vcompressstorew(mem: *mut i8, data: i16x32, mask: u32);
     #[link_name = "llvm.x86.avx512.mask.compress.store.w.256"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vnni.rs b/library/stdarch/crates/core_arch/src/x86/avx512vnni.rs
index 8cd8764f24868..b9084aec59344 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512vnni.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512vnni.rs
@@ -873,7 +873,7 @@ pub fn _mm256_dpwuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.vpdpwssd.512"]
     fn vpdpwssd(src: i32x16, a: i16x32, b: i16x32) -> i32x16;
     #[link_name = "llvm.x86.avx512.vpdpwssd.256"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vp2intersect.rs b/library/stdarch/crates/core_arch/src/x86/avx512vp2intersect.rs
index 4dd7412e9e330..30fcfce63ccf4 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512vp2intersect.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512vp2intersect.rs
@@ -110,7 +110,7 @@ pub unsafe fn _mm512_2intersect_epi64(
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.vp2intersect.d.128"]
     fn vp2intersectd_128(a: i32x4, b: i32x4) -> (u8, u8);
     #[link_name = "llvm.x86.avx512.vp2intersect.q.128"]
diff --git a/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs b/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs
index 861213eb4257f..b17d3de48b595 100644
--- a/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs
@@ -176,7 +176,7 @@ pub fn _mm256_cvtneps_avx_pbh(a: __m256) -> __m128bh {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.vbcstnebf162ps128"]
     fn bcstnebf162ps_128(a: *const bf16) -> __m128;
     #[link_name = "llvm.x86.vbcstnebf162ps256"]
diff --git a/library/stdarch/crates/core_arch/src/x86/bmi1.rs b/library/stdarch/crates/core_arch/src/x86/bmi1.rs
index 432051abd1cfa..21da03667f849 100644
--- a/library/stdarch/crates/core_arch/src/x86/bmi1.rs
+++ b/library/stdarch/crates/core_arch/src/x86/bmi1.rs
@@ -131,7 +131,7 @@ pub const fn _mm_tzcnt_32(x: u32) -> i32 {
     x.trailing_zeros() as i32
 }
 
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.bmi.bextr.32"]
     fn x86_bmi_bextr_32(x: u32, y: u32) -> u32;
 }
diff --git a/library/stdarch/crates/core_arch/src/x86/bmi2.rs b/library/stdarch/crates/core_arch/src/x86/bmi2.rs
index 5320640d96873..dae4133d63bec 100644
--- a/library/stdarch/crates/core_arch/src/x86/bmi2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/bmi2.rs
@@ -67,7 +67,7 @@ pub fn _pext_u32(a: u32, mask: u32) -> u32 {
     unsafe { x86_bmi2_pext_32(a, mask) }
 }
 
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.bmi.bzhi.32"]
     fn x86_bmi2_bzhi_32(x: u32, y: u32) -> u32;
     #[link_name = "llvm.x86.bmi.pdep.32"]
diff --git a/library/stdarch/crates/core_arch/src/x86/fxsr.rs b/library/stdarch/crates/core_arch/src/x86/fxsr.rs
index 08619efe7c9ef..74a95e192a3af 100644
--- a/library/stdarch/crates/core_arch/src/x86/fxsr.rs
+++ b/library/stdarch/crates/core_arch/src/x86/fxsr.rs
@@ -4,7 +4,7 @@
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.fxsave"]
     fn fxsave(p: *mut u8);
     #[link_name = "llvm.x86.fxrstor"]
diff --git a/library/stdarch/crates/core_arch/src/x86/gfni.rs b/library/stdarch/crates/core_arch/src/x86/gfni.rs
index e9ee27a7b823b..8cebd04a4b836 100644
--- a/library/stdarch/crates/core_arch/src/x86/gfni.rs
+++ b/library/stdarch/crates/core_arch/src/x86/gfni.rs
@@ -23,7 +23,7 @@ use crate::mem::transmute;
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.vgf2p8affineinvqb.512"]
     fn vgf2p8affineinvqb_512(x: i8x64, a: i8x64, imm8: u8) -> i8x64;
     #[link_name = "llvm.x86.vgf2p8affineinvqb.256"]
diff --git a/library/stdarch/crates/core_arch/src/x86/pclmulqdq.rs b/library/stdarch/crates/core_arch/src/x86/pclmulqdq.rs
index 0f2769257f958..454785c5e0c89 100644
--- a/library/stdarch/crates/core_arch/src/x86/pclmulqdq.rs
+++ b/library/stdarch/crates/core_arch/src/x86/pclmulqdq.rs
@@ -11,7 +11,7 @@ use crate::core_arch::x86::__m128i;
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.pclmulqdq"]
     fn pclmulqdq(a: __m128i, round_key: __m128i, imm8: u8) -> __m128i;
 }
diff --git a/library/stdarch/crates/core_arch/src/x86/rtm.rs b/library/stdarch/crates/core_arch/src/x86/rtm.rs
index c88bd6592d784..f09b95d76bdb3 100644
--- a/library/stdarch/crates/core_arch/src/x86/rtm.rs
+++ b/library/stdarch/crates/core_arch/src/x86/rtm.rs
@@ -16,7 +16,7 @@
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.xbegin"]
     fn x86_xbegin() -> i32;
     #[link_name = "llvm.x86.xend"]
diff --git a/library/stdarch/crates/core_arch/src/x86/sha.rs b/library/stdarch/crates/core_arch/src/x86/sha.rs
index f8a3295d19589..f7d8c3c0b2408 100644
--- a/library/stdarch/crates/core_arch/src/x86/sha.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sha.rs
@@ -1,7 +1,7 @@
 use crate::core_arch::{simd::*, x86::*};
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.sha1msg1"]
     fn sha1msg1(a: i32x4, b: i32x4) -> i32x4;
     #[link_name = "llvm.x86.sha1msg2"]
diff --git a/library/stdarch/crates/core_arch/src/x86/sse.rs b/library/stdarch/crates/core_arch/src/x86/sse.rs
index 867387290119b..e31175d48cf94 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse.rs
@@ -1987,7 +1987,7 @@ pub const fn _MM_TRANSPOSE4_PS(
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.sse.rcp.ss"]
     fn rcpss(a: __m128) -> __m128;
     #[link_name = "llvm.x86.sse.rcp.ps"]
@@ -2040,7 +2040,7 @@ unsafe extern "C" {
     fn stmxcsr(p: *mut i8);
     #[link_name = "llvm.x86.sse.ldmxcsr"]
     fn ldmxcsr(p: *const i8);
-    #[link_name = "llvm.prefetch"]
+    #[link_name = "llvm.prefetch.p0"]
     fn prefetch(p: *const i8, rw: i32, loc: i32, ty: i32);
     #[link_name = "llvm.x86.sse.cmp.ss"]
     fn cmpss(a: __m128, b: __m128, imm8: i8) -> __m128;
diff --git a/library/stdarch/crates/core_arch/src/x86/sse2.rs b/library/stdarch/crates/core_arch/src/x86/sse2.rs
index 62719700ad905..bd7e4df2138d5 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse2.rs
@@ -3242,7 +3242,7 @@ pub const fn _mm_unpacklo_pd(a: __m128d, b: __m128d) -> __m128d {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.sse2.pause"]
     fn pause();
     #[link_name = "llvm.x86.sse2.clflush"]
diff --git a/library/stdarch/crates/core_arch/src/x86/sse3.rs b/library/stdarch/crates/core_arch/src/x86/sse3.rs
index e4c75702544d9..2f6fa35cb616a 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse3.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse3.rs
@@ -178,7 +178,7 @@ pub const fn _mm_moveldup_ps(a: __m128) -> __m128 {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.sse3.ldu.dq"]
     fn lddqu(mem_addr: *const i8) -> i8x16;
 }
diff --git a/library/stdarch/crates/core_arch/src/x86/sse41.rs b/library/stdarch/crates/core_arch/src/x86/sse41.rs
index 4ebf7d3bd39a8..d981166ff08c9 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse41.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse41.rs
@@ -1181,7 +1181,7 @@ pub unsafe fn _mm_stream_load_si128(mem_addr: *const __m128i) -> __m128i {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.sse41.insertps"]
     fn insertps(a: __m128, b: __m128, imm8: u8) -> __m128;
     #[link_name = "llvm.x86.sse41.dppd"]
diff --git a/library/stdarch/crates/core_arch/src/x86/sse42.rs b/library/stdarch/crates/core_arch/src/x86/sse42.rs
index 55e22592637f1..0534fe9379a18 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse42.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse42.rs
@@ -569,7 +569,7 @@ pub const fn _mm_cmpgt_epi64(a: __m128i, b: __m128i) -> __m128i {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     // SSE 4.2 string and text comparison ops
     #[link_name = "llvm.x86.sse42.pcmpestrm128"]
     fn pcmpestrm128(a: i8x16, la: i32, b: i8x16, lb: i32, imm8: i8) -> u8x16;
diff --git a/library/stdarch/crates/core_arch/src/x86/sse4a.rs b/library/stdarch/crates/core_arch/src/x86/sse4a.rs
index f36b879a030e3..14e9b56dcb2ed 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse4a.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse4a.rs
@@ -6,7 +6,7 @@ use crate::core_arch::{simd::*, x86::*};
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.sse4a.extrq"]
     fn extrq(x: i64x2, y: i8x16) -> i64x2;
     #[link_name = "llvm.x86.sse4a.extrqi"]
diff --git a/library/stdarch/crates/core_arch/src/x86/ssse3.rs b/library/stdarch/crates/core_arch/src/x86/ssse3.rs
index 1d7a97944a37b..b0152c81596bd 100644
--- a/library/stdarch/crates/core_arch/src/x86/ssse3.rs
+++ b/library/stdarch/crates/core_arch/src/x86/ssse3.rs
@@ -345,7 +345,7 @@ pub fn _mm_sign_epi32(a: __m128i, b: __m128i) -> __m128i {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.ssse3.pshuf.b.128"]
     fn pshufb128(a: u8x16, b: u8x16) -> u8x16;
 
diff --git a/library/stdarch/crates/core_arch/src/x86/tbm.rs b/library/stdarch/crates/core_arch/src/x86/tbm.rs
index 0ba4572dcd029..2a44579408364 100644
--- a/library/stdarch/crates/core_arch/src/x86/tbm.rs
+++ b/library/stdarch/crates/core_arch/src/x86/tbm.rs
@@ -13,7 +13,7 @@
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.tbm.bextri.u32"]
     fn bextri_u32(a: u32, control: u32) -> u32;
 }
diff --git a/library/stdarch/crates/core_arch/src/x86/vaes.rs b/library/stdarch/crates/core_arch/src/x86/vaes.rs
index 864b1d56d1057..72dd387f900d5 100644
--- a/library/stdarch/crates/core_arch/src/x86/vaes.rs
+++ b/library/stdarch/crates/core_arch/src/x86/vaes.rs
@@ -14,7 +14,7 @@ use crate::core_arch::x86::__m512i;
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.aesni.aesenc.256"]
     fn aesenc_256(a: __m256i, round_key: __m256i) -> __m256i;
     #[link_name = "llvm.x86.aesni.aesenclast.256"]
diff --git a/library/stdarch/crates/core_arch/src/x86/vpclmulqdq.rs b/library/stdarch/crates/core_arch/src/x86/vpclmulqdq.rs
index ad44e59f3ada1..4c39ae6ee7aa3 100644
--- a/library/stdarch/crates/core_arch/src/x86/vpclmulqdq.rs
+++ b/library/stdarch/crates/core_arch/src/x86/vpclmulqdq.rs
@@ -12,7 +12,7 @@ use crate::core_arch::x86::__m512i;
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.pclmulqdq.256"]
     fn pclmulqdq_256(a: __m256i, round_key: __m256i, imm8: u8) -> __m256i;
     #[link_name = "llvm.x86.pclmulqdq.512"]
diff --git a/library/stdarch/crates/core_arch/src/x86/xsave.rs b/library/stdarch/crates/core_arch/src/x86/xsave.rs
index e22d3580ff463..395e2c64be3a0 100644
--- a/library/stdarch/crates/core_arch/src/x86/xsave.rs
+++ b/library/stdarch/crates/core_arch/src/x86/xsave.rs
@@ -5,7 +5,7 @@
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.xsave"]
     fn xsave(p: *mut u8, hi: u32, lo: u32);
     #[link_name = "llvm.x86.xrstor"]
diff --git a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
index 0fd9b09363d4b..e26bfc5c1ca4f 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
@@ -527,7 +527,7 @@ pub fn _mm_cvtt_roundss_u64<const SAE: i32>(a: __m128) -> u64 {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512.vcvtss2si64"]
     fn vcvtss2si64(a: f32x4, rounding: i32) -> i64;
     #[link_name = "llvm.x86.avx512.vcvtss2usi64"]
diff --git a/library/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs b/library/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs
index 2a511328bb382..5baf1c9036e19 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs
@@ -211,7 +211,7 @@ pub fn _mm_cvtt_roundsh_u64<const SAE: i32>(a: __m128h) -> u64 {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.avx512fp16.vcvtsi642sh"]
     fn vcvtsi642sh(a: __m128h, b: i64, rounding: i32) -> __m128h;
     #[link_name = "llvm.x86.avx512fp16.vcvtusi642sh"]
diff --git a/library/stdarch/crates/core_arch/src/x86_64/bmi.rs b/library/stdarch/crates/core_arch/src/x86_64/bmi.rs
index 8d2b22089ac10..f082953f9df90 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/bmi.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/bmi.rs
@@ -122,7 +122,7 @@ pub const fn _mm_tzcnt_64(x: u64) -> i64 {
     x.trailing_zeros() as i64
 }
 
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.bmi.bextr.64"]
     fn x86_bmi_bextr_64(x: u64, y: u64) -> u64;
 }
diff --git a/library/stdarch/crates/core_arch/src/x86_64/bmi2.rs b/library/stdarch/crates/core_arch/src/x86_64/bmi2.rs
index 6151eee8bdbb5..81ab9e05add96 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/bmi2.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/bmi2.rs
@@ -69,7 +69,7 @@ pub fn _pext_u64(a: u64, mask: u64) -> u64 {
     unsafe { x86_bmi2_pext_64(a, mask) }
 }
 
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.bmi.bzhi.64"]
     fn x86_bmi2_bzhi_64(x: u64, y: u64) -> u64;
     #[link_name = "llvm.x86.bmi.pdep.64"]
diff --git a/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs b/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs
index 28bf1951167a5..f50dacb4bee4f 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs
@@ -4,7 +4,7 @@
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.fxsave64"]
     fn fxsave64(p: *mut u8);
     #[link_name = "llvm.x86.fxrstor64"]
diff --git a/library/stdarch/crates/core_arch/src/x86_64/sse.rs b/library/stdarch/crates/core_arch/src/x86_64/sse.rs
index 81e1070b55691..521652c126914 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/sse.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/sse.rs
@@ -6,7 +6,7 @@ use crate::core_arch::x86::*;
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.sse.cvtss2si64"]
     fn cvtss2si64(a: __m128) -> i64;
     #[link_name = "llvm.x86.sse.cvttss2si64"]
diff --git a/library/stdarch/crates/core_arch/src/x86_64/sse2.rs b/library/stdarch/crates/core_arch/src/x86_64/sse2.rs
index 08dabf053d428..c4768cedbfa6b 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/sse2.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/sse2.rs
@@ -6,7 +6,7 @@ use crate::core_arch::x86::*;
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.sse2.cvtsd2si64"]
     fn cvtsd2si64(a: __m128d) -> i64;
     #[link_name = "llvm.x86.sse2.cvttsd2si64"]
diff --git a/library/stdarch/crates/core_arch/src/x86_64/sse42.rs b/library/stdarch/crates/core_arch/src/x86_64/sse42.rs
index cd32c149aff5b..307e6167aabae 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/sse42.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/sse42.rs
@@ -4,7 +4,7 @@
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.sse42.crc32.64.64"]
     fn crc32_64_64(crc: u64, v: u64) -> u64;
 }
diff --git a/library/stdarch/crates/core_arch/src/x86_64/tbm.rs b/library/stdarch/crates/core_arch/src/x86_64/tbm.rs
index fe12538b07a06..b4ec50a66fa0b 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/tbm.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/tbm.rs
@@ -13,7 +13,7 @@
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.tbm.bextri.u64"]
     fn bextri_u64(a: u64, control: u64) -> u64;
 }
diff --git a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs
index 30a7123315e5f..c307d40073433 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs
@@ -6,7 +6,7 @@
 use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
     #[link_name = "llvm.x86.xsave64"]
     fn xsave64(p: *mut u8, hi: u32, lo: u32);
     #[link_name = "llvm.x86.xrstor64"]
diff --git a/library/stdarch/crates/intrinsic-test/src/arm/config.rs b/library/stdarch/crates/intrinsic-test/src/arm/config.rs
deleted file mode 100644
index 87b8ebfa183e7..0000000000000
--- a/library/stdarch/crates/intrinsic-test/src/arm/config.rs
+++ /dev/null
@@ -1,26 +0,0 @@
-pub const NOTICE: &str = "\
-// This is a transient test file, not intended for distribution. Some aspects of the
-// test are derived from a JSON specification, published under the same license as the
-// `intrinsic-test` crate.\n";
-
-pub const PLATFORM_RUST_DEFINITIONS: &str = "";
-
-pub const PLATFORM_RUST_CFGS: &str = r#"
-#![cfg_attr(target_arch = "arm", feature(stdarch_arm_neon_intrinsics))]
-#![cfg_attr(target_arch = "arm", feature(stdarch_aarch32_crc32))]
-#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fcma))]
-#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_dotprod))]
-#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_i8mm))]
-#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sm4))]
-#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_ftts))]
-#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_feat_lut))]
-#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fp8))]
-#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(faminmax))]
-#![feature(stdarch_neon_f16)]
-
-#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
-use core_arch::arch::aarch64::*;
-
-#[cfg(target_arch = "arm")]
-use core_arch::arch::arm::*;
-"#;
diff --git a/library/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs b/library/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs
index a54e5857192e0..bcbee3503b9ad 100644
--- a/library/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs
+++ b/library/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs
@@ -2,9 +2,9 @@ use crate::common::intrinsic_helpers::IntrinsicType;
 use std::ops::{Deref, DerefMut};
 
 #[derive(Debug, Clone, PartialEq)]
-pub struct ArmIntrinsicType(pub IntrinsicType);
+pub struct ArmType(pub IntrinsicType);
 
-impl Deref for ArmIntrinsicType {
+impl Deref for ArmType {
     type Target = IntrinsicType;
 
     fn deref(&self) -> &Self::Target {
@@ -12,7 +12,7 @@ impl Deref for ArmIntrinsicType {
     }
 }
 
-impl DerefMut for ArmIntrinsicType {
+impl DerefMut for ArmType {
     fn deref_mut(&mut self) -> &mut Self::Target {
         &mut self.0
     }
diff --git a/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs b/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs
index 06cf78a422285..26f861ca64b62 100644
--- a/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs
+++ b/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs
@@ -1,4 +1,5 @@
-use super::intrinsic::ArmIntrinsicType;
+use super::intrinsic::ArmType;
+use crate::arm::Arm;
 use crate::arm::types::parse_intrinsic_type;
 use crate::common::argument::{Argument, ArgumentList};
 use crate::common::constraint::Constraint;
@@ -59,7 +60,7 @@ struct JsonIntrinsic {
 
 pub fn get_neon_intrinsics(
     filename: &Path,
-) -> Result<Vec<Intrinsic<ArmIntrinsicType>>, Box<dyn std::error::Error>> {
+) -> Result<Vec<Intrinsic<Arm>>, Box<dyn std::error::Error>> {
     let file = std::fs::File::open(filename)?;
     let reader = std::io::BufReader::new(file);
     let json: Vec<JsonIntrinsic> = serde_json::from_reader(reader).expect("Couldn't parse JSON");
@@ -79,10 +80,10 @@ pub fn get_neon_intrinsics(
 
 fn json_to_intrinsic(
     mut intr: JsonIntrinsic,
-) -> Result<Intrinsic<ArmIntrinsicType>, Box<dyn std::error::Error>> {
+) -> Result<Intrinsic<Arm>, Box<dyn std::error::Error>> {
     let name = intr.name.replace(['[', ']'], "");
 
-    let result_ty = ArmIntrinsicType(parse_intrinsic_type(&intr.return_type.value)?);
+    let result_ty = ArmType(parse_intrinsic_type(&intr.return_type.value)?);
 
     let args = intr
         .arguments
@@ -120,12 +121,8 @@ fn json_to_intrinsic(
                     }
                 });
 
-            let mut arg = Argument::<ArmIntrinsicType>::new(
-                i,
-                String::from(arg_name),
-                ArmIntrinsicType(arg_ty),
-                constraint,
-            );
+            let mut arg =
+                Argument::<Arm>::new(i, String::from(arg_name), ArmType(arg_ty), constraint);
 
             // The JSON doesn't list immediates as const
             let IntrinsicType {
@@ -138,13 +135,14 @@ fn json_to_intrinsic(
         })
         .collect();
 
-    let arguments = ArgumentList::<ArmIntrinsicType> { args };
+    let arguments = ArgumentList::<Arm> { args };
 
     Ok(Intrinsic {
         name,
         arguments,
         results: result_ty,
         arch_tags: intr.architectures,
+        extension: intr.simd_isa,
     })
 }
 
diff --git a/library/stdarch/crates/intrinsic-test/src/arm/mod.rs b/library/stdarch/crates/intrinsic-test/src/arm/mod.rs
index 378f23ba7c361..a60e0ff1551a3 100644
--- a/library/stdarch/crates/intrinsic-test/src/arm/mod.rs
+++ b/library/stdarch/crates/intrinsic-test/src/arm/mod.rs
@@ -1,42 +1,48 @@
-mod config;
 mod intrinsic;
 mod json_parser;
 mod types;
 
-use crate::common::SupportedArchitectureTest;
+use crate::common::SupportedArchitecture;
 use crate::common::cli::{CcArgStyle, ProcessedCli};
 use crate::common::intrinsic::Intrinsic;
-use crate::common::intrinsic_helpers::TypeKind;
-use intrinsic::ArmIntrinsicType;
+use crate::common::intrinsic_helpers::{SimdLen, TypeKind};
+use intrinsic::ArmType;
 use json_parser::get_neon_intrinsics;
 
-pub struct ArmArchitectureTest {
-    intrinsics: Vec<Intrinsic<ArmIntrinsicType>>,
-}
+#[derive(PartialEq)]
+pub struct Arm(Vec<Intrinsic<Arm>>);
 
-impl SupportedArchitectureTest for ArmArchitectureTest {
-    type IntrinsicImpl = ArmIntrinsicType;
+impl SupportedArchitecture for Arm {
+    type Type = ArmType;
 
-    fn intrinsics(&self) -> &[Intrinsic<ArmIntrinsicType>] {
-        &self.intrinsics
+    fn intrinsics(&self) -> &[Intrinsic<Self>] {
+        &self.0
     }
 
-    const NOTICE: &str = config::NOTICE;
-
-    const PLATFORM_C_HEADERS: &[&str] = &["arm_neon.h", "arm_acle.h", "arm_fp16.h"];
+    const NOTICE: &str = r#"
+// This is a transient test file, not intended for distribution. Some aspects of the
+// test are derived from a JSON specification, published under the same license as the
+// `intrinsic-test` crate.
+"#;
 
-    const PLATFORM_RUST_DEFINITIONS: &str = config::PLATFORM_RUST_DEFINITIONS;
-    const PLATFORM_RUST_CFGS: &str = config::PLATFORM_RUST_CFGS;
+    const C_PRELUDE: &str = r#"
+#include <arm_acle.h>
+#include <arm_fp16.h>
+#include <arm_neon.h>
+"#;
+    const RUST_PRELUDE: &str = RUST_PRELUDE;
 
-    fn arch_flags(&self, cli_options: &ProcessedCli) -> Vec<&str> {
+    fn c_compiler_flags(&self, cli_options: &ProcessedCli) -> Vec<&str> {
         // GCC uses an extra `-` in the arch name
         match cli_options.cc_arg_style {
             CcArgStyle::Clang => vec!["-march=armv8.6a+crypto+crc+dotprod+fp16"],
+            // SVE tests aren't run under GCC so there are no target features added for SVE
             CcArgStyle::Gcc => vec!["-march=armv8.6-a+crypto+crc+dotprod+fp16+sha3+sm4"],
         }
     }
 
     fn create(cli_options: &ProcessedCli) -> Self {
+        let big_endian = cli_options.target.starts_with("aarch64_be");
         let a32 = cli_options.target.starts_with("armv7");
         let mut intrinsics =
             get_neon_intrinsics(&cli_options.filename).expect("Error parsing input file");
@@ -54,6 +60,53 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
             // Skip bfloat intrinsics - not currently supported
             .filter(|i| i.results.kind() != TypeKind::BFloat)
             .filter(|i| !i.arguments.iter().any(|a| a.ty.kind() == TypeKind::BFloat))
+            // Skip SVE intrinsics that have `f16` - not yet implemented!
+            .filter(|i| {
+                let has_f16_arg = i
+                    .arguments
+                    .iter()
+                    .any(|a| a.ty.kind() == TypeKind::Float && a.ty.bit_len == Some(16));
+                let has_sve_arg = i
+                    .arguments
+                    .iter()
+                    .any(|a| a.ty.simd_len == Some(SimdLen::Scalable));
+                !(has_f16_arg && has_sve_arg)
+            })
+            .filter(|i| {
+                let has_f16_ret =
+                    i.results.kind() == TypeKind::Float && i.results.bit_len == Some(16);
+                let has_sve_ret = i.results.simd_len == Some(SimdLen::Scalable);
+                !(has_f16_ret && has_sve_ret)
+            })
+            // Skip `svqcvtn{u,}n*_x2` intrinsics - not yet implemented!
+            .filter(|i| !(i.name.starts_with("svqcvtn") && i.name.ends_with("_x2")))
+            // Skip `svqrshr{u,}n*_x2` intrinsics - not yet implemented!
+            .filter(|i| !(i.name.starts_with("svqrshrn") && i.name.ends_with("_x2")))
+            .filter(|i| !(i.name.starts_with("svqrshrun") && i.name.ends_with("_x2")))
+            // Skip `svclamp*` intrinsics - not yet implemented!
+            .filter(|i| !i.name.starts_with("svclamp"))
+            // Skip `svdot{_lane,}_{s,u}32_{s,u}16` intrinsics - not yet implemented!
+            .filter(|i| {
+                i.name != "svdot_lane_u32_u16"
+                    && i.name != "svdot_lane_s32_s16"
+                    && i.name != "svdot_u32_u16"
+                    && i.name != "svdot_s32_s16"
+            })
+            // Skip `svrevd*` intrinsics - not yet implemented!
+            .filter(|i| !i.name.starts_with("svrevd"))
+            // Skip `svpsel_lane_b*` intrinsics - not yet implemented!
+            .filter(|i| !i.name.starts_with("svpsel_lane_b"))
+            // Skip `svundef*` intrinsics - to avoid undefined behaviour in Rust, these return
+            // zeroed vectors in Rust, which are inherently going to be different than the
+            // undefined vectors returned by the C intrinsics.
+            .filter(|i| !i.name.starts_with("svundef"))
+            // Skip `sveorv` intrinsics - the code produced by `intrinsic-test` for these
+            // miscompiles and the Rust intrinsic call gets replaced by a constant zero (see
+            // llvm/llvm-project#203921).
+            .filter(|i| !i.name.starts_with("sveorv"))
+            // These load intrinsics expect each element in the scalable vector `bases` argument to
+            // be able to be cast to a pointer, which we don't support generating tests for yet.
+            .filter(|i| !(i.name.starts_with("svld") && i.name.contains("_gather_")))
             // Skip pointers for now, we would probably need to look at the return
             // type to work out how many elements we need to point to.
             .filter(|i| !i.arguments.iter().any(|a| a.is_ptr()))
@@ -63,9 +116,36 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
             .filter(|i| !cli_options.skip.contains(&i.name))
             // Skip A64-specific intrinsics on A32
             .filter(|i| !(a32 && i.arch_tags == vec!["A64".to_string()]))
+            // Skip SVE intrinsics on big endian
+            .filter(|i| !(big_endian && (i.extension == "SVE" || i.extension == "SVE2")))
+            // Skip SVE intrinsics when testing against GCC as our wrappers run into ICEs
+            // See <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125818>
+            .filter(|i| {
+                !(matches!(cli_options.cc_arg_style, CcArgStyle::Gcc)
+                    && (i.extension == "SVE" || i.extension == "SVE2"))
+            })
             .take(sample_size)
             .collect::<Vec<_>>();
 
-        Self { intrinsics }
+        Self(intrinsics)
     }
 }
+
+const RUST_PRELUDE: &str = r#"
+#![cfg_attr(target_arch = "arm", feature(stdarch_arm_neon_intrinsics))]
+#![cfg_attr(target_arch = "arm", feature(stdarch_aarch32_crc32))]
+#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fcma))]
+#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_i8mm))]
+#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sm4))]
+#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_ftts))]
+#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_feat_lut))]
+#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fp8))]
+#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(faminmax))]
+#![feature(stdarch_neon_f16)]
+
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
+use core_arch::arch::aarch64::*;
+
+#[cfg(target_arch = "arm")]
+use core_arch::arch::arm::*;
+"#;
diff --git a/library/stdarch/crates/intrinsic-test/src/arm/types.rs b/library/stdarch/crates/intrinsic-test/src/arm/types.rs
index cd420f10678fc..7754e9ec2d0dd 100644
--- a/library/stdarch/crates/intrinsic-test/src/arm/types.rs
+++ b/library/stdarch/crates/intrinsic-test/src/arm/types.rs
@@ -1,28 +1,37 @@
-use super::intrinsic::ArmIntrinsicType;
-use crate::common::intrinsic_helpers::{
-    IntrinsicType, IntrinsicTypeDefinition, Sign, SimdLen, TypeKind,
-};
+use super::intrinsic::ArmType;
+use crate::common::intrinsic_helpers::{IntrinsicType, Sign, SimdLen, TypeDefinition, TypeKind};
 
-impl IntrinsicTypeDefinition for ArmIntrinsicType {
+impl TypeDefinition for ArmType {
     /// Gets a string containing the typename for this type in C format.
     fn c_type(&self) -> String {
         let prefix = self.kind.c_prefix();
 
-        if let Some(bit_len) = self.bit_len {
-            match (self.simd_len, self.vec_len) {
-                (None, None) => format!("{prefix}{bit_len}_t"),
-                (Some(SimdLen::Fixed(simd)), None) => format!("{prefix}{bit_len}x{simd}_t"),
-                (Some(SimdLen::Fixed(simd)), Some(vec)) => {
-                    format!("{prefix}{bit_len}x{simd}x{vec}_t")
-                }
-                (Some(SimdLen::Scalable), None) => format!("sv{prefix}{bit_len}_t"),
-                (Some(SimdLen::Scalable), Some(vec)) => {
-                    format!("sv{prefix}{bit_len}x{vec}_t")
-                }
-                (None, Some(_)) => todo!("{self:#?}"), // Likely an invalid case
+        match (self.bit_len, self.simd_len, self.vec_len) {
+            // e.g. `bool`
+            (Some(_), None, None) if matches!(self.kind, TypeKind::Bool) => {
+                format!("{prefix}")
             }
-        } else {
-            todo!("{self:#?}")
+            // e.g. `float32_t`, `int64_t`
+            (Some(bit_len), None, None) => format!("{prefix}{bit_len}_t"),
+            // e.g. `float32x2_t`, `int64x2_t`
+            (Some(bit_len), Some(SimdLen::Fixed(simd)), None) => {
+                format!("{prefix}{bit_len}x{simd}_t")
+            }
+            // e.g. `float32x2x3_t`, `int64x2x3_t`
+            (Some(bit_len), Some(SimdLen::Fixed(simd)), Some(vec)) => {
+                format!("{prefix}{bit_len}x{simd}x{vec}_t")
+            }
+            // e.g. `svbool_t`
+            (Some(_), Some(SimdLen::Scalable), None) if matches!(self.kind, TypeKind::Bool) => {
+                format!("sv{prefix}_t")
+            }
+            // e.g. `svfloat32_t`, `svint64_t`
+            (Some(bit_len), Some(SimdLen::Scalable), None) => format!("sv{prefix}{bit_len}_t"),
+            // e.g. `svfloat32x3_t`, `svint64x3_t`
+            (Some(bit_len), Some(SimdLen::Scalable), Some(vec)) => {
+                format!("sv{prefix}{bit_len}x{vec}_t")
+            }
+            _ => todo!("{self:#?}"),
         }
     }
 
@@ -30,26 +39,39 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
         let rust_prefix = self.kind.rust_prefix();
         let c_prefix = self.kind.c_prefix();
 
-        if let Some(bit_len) = self.bit_len {
-            match (self.simd_len, self.vec_len) {
-                (None, None) => format!("{rust_prefix}{bit_len}"),
-                (Some(SimdLen::Fixed(simd)), None) => format!("{c_prefix}{bit_len}x{simd}_t"),
-                (Some(SimdLen::Fixed(simd)), Some(vec)) => {
-                    format!("{c_prefix}{bit_len}x{simd}x{vec}_t")
-                }
-                (Some(SimdLen::Scalable), None) => format!("sv{c_prefix}{bit_len}_t"),
-                (Some(SimdLen::Scalable), Some(vec)) => {
-                    format!("sv{c_prefix}{bit_len}x{vec}_t")
-                }
-                (None, Some(_)) => todo!("{self:#?}"), // Likely an invalid case
+        match (self.bit_len, self.simd_len, self.vec_len) {
+            // e.g. `svpattern`
+            (None, _, _) => format!("{rust_prefix}"),
+            // e.g. `bool`
+            (Some(_), None, None) if matches!(self.kind, TypeKind::Bool) => {
+                format!("{rust_prefix}")
             }
-        } else {
-            todo!("{self:#?}")
+            // e.g. `i32`
+            (Some(bit_len), None, None) => format!("{rust_prefix}{bit_len}"),
+            // e.g. `int32x2_t`
+            (Some(bit_len), Some(SimdLen::Fixed(simd)), None) => {
+                format!("{c_prefix}{bit_len}x{simd}_t")
+            }
+            // e.g. `int32x2x3_t`
+            (Some(bit_len), Some(SimdLen::Fixed(simd)), Some(vec)) => {
+                format!("{c_prefix}{bit_len}x{simd}x{vec}_t")
+            }
+            // e.g. `svbool_t`
+            (Some(_), Some(SimdLen::Scalable), None) if matches!(self.kind, TypeKind::Bool) => {
+                format!("sv{c_prefix}_t")
+            }
+            // e.g. `svint32_t`
+            (Some(bit_len), Some(SimdLen::Scalable), None) => format!("sv{c_prefix}{bit_len}_t"),
+            // e.g. `svint32x3_t`
+            (Some(bit_len), Some(SimdLen::Scalable), Some(vec)) => {
+                format!("sv{c_prefix}{bit_len}x{vec}_t")
+            }
+            (Some(_), None, Some(_)) => todo!("{self:#?}"),
         }
     }
 
     /// Determines the load function for this type.
-    fn get_load_function(&self) -> String {
+    fn load_function(&self) -> String {
         if let IntrinsicType {
             kind: k,
             bit_len: Some(bl),
@@ -73,7 +95,7 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
                 len = vec_len.unwrap_or(1),
             )
         } else {
-            todo!("get_load_function IntrinsicType: {self:#?}")
+            todo!("load_function IntrinsicType: {self:#?}")
         }
     }
 }
diff --git a/library/stdarch/crates/intrinsic-test/src/common/argument.rs b/library/stdarch/crates/intrinsic-test/src/common/argument.rs
index eaec5b71c47e3..4d38bce327930 100644
--- a/library/stdarch/crates/intrinsic-test/src/common/argument.rs
+++ b/library/stdarch/crates/intrinsic-test/src/common/argument.rs
@@ -1,30 +1,31 @@
 use itertools::Itertools;
 
+use crate::common::SupportedArchitecture;
 use crate::common::intrinsic_helpers::TypeKind;
 use crate::common::values::test_values_array_name;
 
 use super::PASSES;
 use super::constraint::Constraint;
-use super::intrinsic_helpers::IntrinsicTypeDefinition;
+use super::intrinsic_helpers::TypeDefinition;
 
 /// An argument for the intrinsic.
 #[derive(Debug, PartialEq, Clone)]
-pub struct Argument<T: IntrinsicTypeDefinition> {
+pub struct Argument<A: SupportedArchitecture> {
     /// The argument's index in the intrinsic function call.
     pub pos: usize,
     /// The argument name.
     pub name: String,
     /// The type of the argument.
-    pub ty: T,
+    pub ty: A::Type,
     /// Any constraints that are on this argument
     pub constraint: Option<Constraint>,
 }
 
-impl<T> Argument<T>
+impl<A> Argument<A>
 where
-    T: IntrinsicTypeDefinition,
+    A: SupportedArchitecture,
 {
-    pub fn new(pos: usize, name: String, ty: T, constraint: Option<Constraint>) -> Self {
+    pub fn new(pos: usize, name: String, ty: A::Type, constraint: Option<Constraint>) -> Self {
         Argument {
             pos,
             name,
@@ -63,13 +64,13 @@ where
 
 /// Arguments of an intrinsic - including parameters that end up being const generics.
 #[derive(Debug, PartialEq, Clone)]
-pub struct ArgumentList<T: IntrinsicTypeDefinition> {
-    pub args: Vec<Argument<T>>,
+pub struct ArgumentList<A: SupportedArchitecture> {
+    pub args: Vec<Argument<A>>,
 }
 
-impl<T> ArgumentList<T>
+impl<A> ArgumentList<A>
 where
-    T: IntrinsicTypeDefinition,
+    A: SupportedArchitecture,
 {
     /// Returns a string with the arguments in `self` as a parameter list for a wrapper fn
     /// definition in C (e.g. `$ty1 $arg1, $ty2 $arg2`).
@@ -179,14 +180,14 @@ where
             .map(|(idx, arg)| {
                 if arg.is_simd() {
                     format!(
-                        "let {name} = {load}({vals_name}.as_ptr().add((i+{idx}) % {PASSES}) as _);\n",
+                        "let {name} = {load}({vals_name}.as_ptr().add((i+{idx}) % {PASSES}) as _);",
                         name = arg.generate_name(),
                         vals_name = test_values_array_name(&arg.ty),
-                        load = arg.ty.get_load_function(),
+                        load = arg.ty.load_function(),
                     )
                 } else {
                     format!(
-                        "let {name} = {vals_name}[(i+{idx}) % {PASSES}];\n",
+                        "let {name} = {vals_name}[(i+{idx}) % {PASSES}];",
                         name = arg.generate_name(),
                         vals_name = test_values_array_name(&arg.ty),
                     )
@@ -196,7 +197,7 @@ where
     }
 
     /// Returns an iterator over the contained arguments
-    pub fn iter(&self) -> std::slice::Iter<'_, Argument<T>> {
+    pub fn iter(&self) -> std::slice::Iter<'_, Argument<A>> {
         self.args.iter()
     }
 }
diff --git a/library/stdarch/crates/intrinsic-test/src/common/gen_c.rs b/library/stdarch/crates/intrinsic-test/src/common/gen_c.rs
index 24756324c48e4..21cc5cfa2e597 100644
--- a/library/stdarch/crates/intrinsic-test/src/common/gen_c.rs
+++ b/library/stdarch/crates/intrinsic-test/src/common/gen_c.rs
@@ -1,8 +1,8 @@
 use itertools::Itertools;
 
-use crate::common::intrinsic::Intrinsic;
+use crate::common::{SupportedArchitecture, intrinsic::Intrinsic};
 
-use super::intrinsic_helpers::IntrinsicTypeDefinition;
+use super::intrinsic_helpers::TypeDefinition;
 
 /// Generates a C source file containing wrapper functions around each specialisation of each
 /// intrinsic (that is, intrinsics with specific values for the the immediate arguments). Each
@@ -14,20 +14,15 @@ use super::intrinsic_helpers::IntrinsicTypeDefinition;
 ///    *__dst = __crc32cd(a, b);
 /// }
 /// ```
-pub fn write_wrapper_c<T: IntrinsicTypeDefinition>(
+pub fn write_wrapper_c<A: SupportedArchitecture>(
     w: &mut impl std::io::Write,
-    notice: &str,
-    platform_headers: &[&str],
-    intrinsics: &[Intrinsic<T>],
+    intrinsics: &[Intrinsic<A>],
 ) -> std::io::Result<()> {
-    write!(w, "{notice}")?;
+    write!(w, "{}", A::NOTICE)?;
 
     writeln!(w, "#include <stdint.h>")?;
     writeln!(w, "#include <stddef.h>")?;
-
-    for header in platform_headers {
-        writeln!(w, "#include <{header}>")?;
-    }
+    writeln!(w, "{}", A::C_PRELUDE)?;
 
     for intrinsic in intrinsics {
         intrinsic.iter_specializations(|imm_values| {
diff --git a/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs b/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs
index 02f6e40dc06a6..baa11511ec219 100644
--- a/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs
@@ -2,12 +2,11 @@ use std::process::Command;
 
 use itertools::Itertools;
 
-use super::intrinsic_helpers::IntrinsicTypeDefinition;
-use crate::common::PASSES;
+use super::intrinsic_helpers::TypeDefinition;
 use crate::common::cli::{CcArgStyle, ProcessedCli};
 use crate::common::intrinsic::Intrinsic;
-use crate::common::intrinsic_helpers::TypeKind;
 use crate::common::values::{test_values_array_name, test_values_array_static};
+use crate::common::{PASSES, SupportedArchitecture};
 
 /// Rust definitions that are included verbatim in the generated source. In particular, defines
 /// a wrapper around float types that defines `NaN`s to be equal reflexively to enable
@@ -32,12 +31,6 @@ macro_rules! wrap_partialeq {
 wrap_partialeq!(NanEqF16(f16), NanEqF32(f32), NanEqF64(f64));
 "#;
 
-macro_rules! concatln {
-    ($($lines:expr),* $(,)?) => {
-        concat!($( $lines, "\n" ),*)
-    };
-}
-
 /// Run rustfmt on the generated source code
 pub fn run_rustfmt(source_path: &str) {
     let output = Command::new("rustfmt")
@@ -65,11 +58,14 @@ pub fn write_bin_cargo_toml(
     w: &mut impl std::io::Write,
     module_count: usize,
 ) -> std::io::Result<()> {
-    write!(w, concatln!("[workspace]", "members = ["))?;
-    for i in 0..module_count {
-        writeln!(w, "    \"mod_{i}\",")?;
-    }
-    writeln!(w, "]")
+    write!(
+        w,
+        r#"
+[workspace]
+members = [{members}]
+"#,
+        members = (0..module_count).format_with(",", |i, fmt| fmt(&format_args!("\"mod_{i}\"")))
+    )
 }
 
 /// Writes a `Cargo.toml` for a crate with name `name` to `w` that will contain a single Rust source
@@ -77,21 +73,20 @@ pub fn write_bin_cargo_toml(
 pub fn write_lib_cargo_toml(w: &mut impl std::io::Write, name: &str) -> std::io::Result<()> {
     write!(
         w,
-        concatln!(
-            "[package]",
-            "name = \"{name}\"",
-            "version = \"{version}\"",
-            "authors = [{authors}]",
-            "license = \"{license}\"",
-            "edition = \"2018\"",
-            "",
-            "[dependencies]",
-            "core_arch = {{ path = \"../../crates/core_arch\" }}",
-            "",
-            "[build-dependencies]",
-            "cc = \"1\""
-        ),
-        name = name,
+        r#"
+[package]
+name = "{name}"
+version = "{version}"
+authors = [{authors}]
+license = "{license}"
+edition = "2018"
+
+[dependencies]
+core_arch = {{ path = "../../crates/core_arch" }}
+
+[build-dependencies]
+cc = "1"
+"#,
         version = env!("CARGO_PKG_VERSION"),
         authors = env!("CARGO_PKG_AUTHORS")
             .split(":")
@@ -102,30 +97,30 @@ pub fn write_lib_cargo_toml(w: &mut impl std::io::Write, name: &str) -> std::io:
 
 /// Writes a Rust source file into `w` with common definitions, static arrays with test values,
 /// declarations of C wrapper functions for FFI and Rust test functions.
-pub fn write_lib_rs<T: IntrinsicTypeDefinition>(
+pub fn write_lib_rs<A: SupportedArchitecture>(
     w: &mut impl std::io::Write,
-    notice: &str,
-    cfg: &str,
-    definitions: &str,
     i: usize,
-    intrinsics: &[Intrinsic<T>],
+    intrinsics: &[Intrinsic<A>],
 ) -> std::io::Result<()> {
-    write!(w, "{notice}")?;
-
-    writeln!(w, "#![feature(simd_ffi)]")?;
-    writeln!(w, "#![feature(f16)]")?;
-    writeln!(w, "#![allow(unused)]")?;
-
-    // Cargo will spam the logs if these warnings are not silenced.
-    writeln!(w, "#![allow(non_upper_case_globals)]")?;
-    writeln!(w, "#![allow(non_camel_case_types)]")?;
-    writeln!(w, "#![allow(non_snake_case)]")?;
-
-    writeln!(w, "{cfg}")?;
-
-    writeln!(w, "{}", COMMON_RUST_DEFINITIONS)?;
-
-    writeln!(w, "{definitions}")?;
+    writeln!(
+        w,
+        r#"
+{notice}
+#![feature(simd_ffi)]
+#![feature(f16)]
+#![allow(unused)]
+
+// Cargo will spam the logs if these warnings are not silenced.
+#![allow(non_upper_case_globals)]
+#![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
+
+{prelude}
+{COMMON_RUST_DEFINITIONS}
+"#,
+        notice = A::NOTICE,
+        prelude = A::RUST_PRELUDE,
+    )?;
 
     let mut seen = std::collections::HashSet::new();
 
@@ -157,9 +152,9 @@ pub fn write_lib_rs<T: IntrinsicTypeDefinition>(
 /// (first loop) `PASSES` number of times (second loop). For a given iteration of a given
 /// specialisation, test values are loaded for each argument and passed to the Rust intrinsic
 /// and the C wrapper function, and the results are compared.
-fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
+fn generate_rust_test_loop<A: SupportedArchitecture>(
     w: &mut impl std::io::Write,
-    intrinsic: &Intrinsic<T>,
+    intrinsic: &Intrinsic<A>,
 ) -> std::io::Result<()> {
     let intrinsic_name = &intrinsic.name;
 
@@ -199,67 +194,45 @@ fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
         writeln!(w, "    ];")?;
     }
 
-    let (cast_prefix, cast_suffix) = if intrinsic.results.is_simd() {
-        (
-            format!(
-                "std::mem::transmute::<_, [{}; {}]>(",
-                intrinsic.results.rust_scalar_type().replace("f", "NanEqF"),
-                intrinsic.results.num_lanes() * intrinsic.results.num_vectors()
-            ),
-            ")",
-        )
-    } else if intrinsic.results.kind == TypeKind::Float {
-        (
-            match intrinsic.results.inner_size() {
-                16 => format!("NanEqF16("),
-                32 => format!("NanEqF32("),
-                64 => format!("NanEqF64("),
-                _ => unimplemented!(),
-            },
-            ")",
-        )
-    } else {
-        ("".to_string(), "")
-    };
-
     write!(
         w,
-        concatln!(
-            "    for (id, rust, c) in specializations {{",
-            "        for i in 0..{passes} {{",
-            "            unsafe {{",
-            "{loaded_args}",
-            "                let __rust_return_value = rust({rust_args});",
-            "",
-            "                let mut __c_return_value = std::mem::MaybeUninit::uninit();",
-            "                c(__c_return_value.as_mut_ptr(){c_args});",
-            "                let __c_return_value = __c_return_value.assume_init();",
-            "",
-            "                assert_eq!({cast_prefix}__rust_return_value{cast_suffix}, {cast_prefix}__c_return_value{cast_suffix}, \"{{id}}\");",
-            "            }}",
-            "        }}",
-            "    }}",
-        ),
+        r#"
+for (id, rust, c) in specializations {{
+    for i in 0..{PASSES} {{
+        unsafe {{
+            {loaded_args}
+            let __rust_return_value = rust({rust_args});
+
+            let mut __c_return_value = std::mem::MaybeUninit::uninit();
+            c(__c_return_value.as_mut_ptr(){c_args});
+            let __c_return_value = __c_return_value.assume_init();
+
+            {comparison}
+        }}
+    }}
+}}
+"#,
         loaded_args = intrinsic.arguments.load_values_rust(),
         rust_args = intrinsic.arguments.as_call_param_rust(),
         c_args = intrinsic.arguments.as_c_call_param_rust(),
-        passes = PASSES,
-        cast_prefix = cast_prefix,
-        cast_suffix = cast_suffix,
+        comparison = intrinsic.results.comparison_function(),
     )
 }
 
 /// Writes a test function for an given intrinsic to `w`, with a body generated by
 /// `generate_rust_test_loop`.
-fn create_rust_test<T: IntrinsicTypeDefinition>(
+fn create_rust_test<A: SupportedArchitecture>(
     w: &mut impl std::io::Write,
-    intrinsic: &Intrinsic<T>,
+    intrinsic: &Intrinsic<A>,
 ) -> std::io::Result<()> {
     trace!("generating `{}`", intrinsic.name);
 
     write!(
         w,
-        concatln!("#[test]", "fn test_{intrinsic_name}() {{"),
+        r#"
+#[test]
+fn test_{intrinsic_name}() {{
+"#,
         intrinsic_name = intrinsic.name,
     )?;
 
@@ -272,26 +245,25 @@ fn create_rust_test<T: IntrinsicTypeDefinition>(
 
 /// Writes an `extern "C"` block with function declarations for each of the C wrapper functions into
 /// `w`.
-pub fn write_bindings_rust<T: IntrinsicTypeDefinition>(
+pub fn write_bindings_rust<A: SupportedArchitecture>(
     w: &mut impl std::io::Write,
     i: usize,
-    intrinsics: &[Intrinsic<T>],
+    intrinsics: &[Intrinsic<A>],
 ) -> std::io::Result<()> {
     write!(
         w,
-        concatln!(
-            "#[allow(improper_ctypes)]",
-            "#[link(name = \"wrapper_{i}\")]",
-            "unsafe extern \"C\" {{"
-        ),
-        i = i
+        r#"
+#[allow(improper_ctypes)]
+#[link(name = "wrapper_{i}")]
+unsafe extern "C" {{
+"#,
     )?;
 
     for intrinsic in intrinsics {
         intrinsic.iter_specializations(|imm_values| {
             writeln!(
                 w,
-                "    fn {name}_wrapper{imm_arglist}(__dst: *mut {return_ty}{arglist});",
+                "fn {name}_wrapper{imm_arglist}(__dst: *mut {return_ty}{arglist});",
                 return_ty = intrinsic.results.rust_type(),
                 name = intrinsic.name,
                 imm_arglist = imm_values
@@ -326,32 +298,22 @@ pub fn write_build_rs(
 
     write!(
         w,
-        concatln!(
-            "fn main() {{",
-            "    cc::Build::new()",
-            "    .file(\"../../c_programs/wrapper_{i}.c\")",
-            "    .opt_level(2)",
-            "    .flags(&[",
-        ),
-        i = i
-    )?;
-
-    let compiler_specific_flags = match cli_options.cc_arg_style {
-        CcArgStyle::Gcc => GCC_FLAGS,
-        CcArgStyle::Clang => CLANG_FLAGS,
-    };
-
-    for flag in COMMON_FLAGS
-        .iter()
-        .chain(compiler_specific_flags)
-        .chain(arch_flags)
-    {
-        writeln!(w, "\"{flag}\",")?;
-    }
-
-    write!(
-        w,
-        concatln!("    ])", "    .compile(\"wrapper_{i}\");", "}}"),
-        i = i
+        r#"
+fn main() {{
+    cc::Build::new()
+        .file("../../c_programs/wrapper_{i}.c")
+        .opt_level(2)
+        .flags(&[{flags}])
+        .compile("wrapper_{i}");
+}}
+"#,
+        flags = COMMON_FLAGS
+            .iter()
+            .chain(match cli_options.cc_arg_style {
+                CcArgStyle::Gcc => GCC_FLAGS,
+                CcArgStyle::Clang => CLANG_FLAGS,
+            })
+            .chain(arch_flags)
+            .format_with(",", |flag, fmt| fmt(&format_args!("\"{flag}\""))),
     )
 }
diff --git a/library/stdarch/crates/intrinsic-test/src/common/intrinsic.rs b/library/stdarch/crates/intrinsic-test/src/common/intrinsic.rs
index d69644388a830..0c5bf43069d00 100644
--- a/library/stdarch/crates/intrinsic-test/src/common/intrinsic.rs
+++ b/library/stdarch/crates/intrinsic-test/src/common/intrinsic.rs
@@ -1,22 +1,23 @@
-use crate::common::constraint::Constraint;
-
 use super::argument::ArgumentList;
-use super::intrinsic_helpers::IntrinsicTypeDefinition;
+use crate::common::{SupportedArchitecture, constraint::Constraint};
 
 /// An intrinsic
 #[derive(Debug, PartialEq, Clone)]
-pub struct Intrinsic<T: IntrinsicTypeDefinition> {
+pub struct Intrinsic<A: SupportedArchitecture> {
     /// The function name of this intrinsic.
     pub name: String,
 
     /// Any arguments for this intrinsic.
-    pub arguments: ArgumentList<T>,
+    pub arguments: ArgumentList<A>,
 
     /// The return type of this intrinsic.
-    pub results: T,
+    pub results: A::Type,
 
     /// Any architecture-specific tags.
     pub arch_tags: Vec<String>,
+
+    /// Specific extension that the intrinsic is from
+    pub extension: String,
 }
 
 /// Invokes `f` for each combination of the values in the constraint ranges.
@@ -40,7 +41,7 @@ fn recurse_specializations<'a, E>(
     }
 }
 
-impl<T: IntrinsicTypeDefinition> Intrinsic<T> {
+impl<A: SupportedArchitecture> Intrinsic<A> {
     /// Invokes `f` for "specialisation" of the intrinsic - a specific instantiation of the
     /// constant generics of the intrinsic. `f` takes a slice where the `i`th element corresponds
     /// to the value of the `i`th const generic argument of the intrinsic.
diff --git a/library/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/library/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index ca5aeba86dab9..b9f30af7dfd51 100644
--- a/library/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/library/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -1,6 +1,6 @@
 use std::cmp;
 use std::fmt;
-use std::ops::Deref;
+use std::ops::DerefMut;
 use std::str::FromStr;
 
 #[derive(Debug, PartialEq, Copy, Clone)]
@@ -90,9 +90,13 @@ impl TypeKind {
         }
     }
 
-    /// Returns the Rust prefix for this type kind i.e. `i`, `u`, or `f`.
+    /// Returns the Rust prefix for this type kind (i.e. `i` for `i16`, or `u` for `u16`). For type
+    /// kinds without any bit length at the end (e.g. `bool`), returns the whole type name.
     pub fn rust_prefix(&self) -> &str {
         match self {
+            Self::Bool => "bool",
+            Self::SvPattern => "svpattern",
+            Self::SvPrefetchOp => "svprfop",
             Self::BFloat => "bf",
             Self::Float => "f",
             Self::Int(Sign::Signed) => "i",
@@ -101,7 +105,7 @@ impl TypeKind {
             Self::Char(Sign::Unsigned) => "u",
             Self::Char(Sign::Signed) => "i",
             Self::Mask => "u",
-            _ => unreachable!("Unused type kind: {self:#?}"),
+            _ => unreachable!("type kind without Rust prefix: {self:#?}"),
         }
     }
 }
@@ -195,9 +199,19 @@ impl IntrinsicType {
     }
 }
 
-pub trait IntrinsicTypeDefinition: Deref<Target = IntrinsicType> {
+pub trait TypeDefinition: Clone + DerefMut<Target = IntrinsicType> {
     /// Determines the load function for this type.
-    fn get_load_function(&self) -> String;
+    fn load_function(&self) -> String;
+
+    /// Determines the comparison function for this type.
+    fn comparison_function(&self) -> String {
+        match self.simd_len {
+            Some(SimdLen::Scalable) => unimplemented!("architecture-specific"),
+            Some(SimdLen::Fixed(_)) | None => {
+                default_fixed_vector_comparison(self, self.num_lanes())
+            }
+        }
+    }
 
     /// Gets a string containing the typename for this type in C.
     fn c_type(&self) -> String;
@@ -208,14 +222,49 @@ pub trait IntrinsicTypeDefinition: Deref<Target = IntrinsicType> {
     /// Gets a string containing the name of the scalar type corresponding to this type if it is a
     /// vector.
     fn rust_scalar_type(&self) -> String {
-        if self.is_simd() {
-            format!(
-                "{prefix}{bits}",
-                prefix = self.kind().rust_prefix(),
-                bits = self.inner_size()
-            )
-        } else {
-            self.rust_type()
-        }
+        let mut ty = self.clone();
+        ty.simd_len = None;
+        ty.vec_len = None;
+        ty.rust_type()
     }
 }
+
+/// Returns the default comparison between results of an intrinsic - casting the vectors to arrays
+/// and using `assert_eq` - using `NanEqF*` where required for floats.
+pub(crate) fn default_fixed_vector_comparison<Ty: TypeDefinition>(
+    ty: &Ty,
+    num_lanes: u32,
+) -> String {
+    let (cast_prefix, cast_suffix) = if ty.is_simd() {
+        (
+            format!(
+                "std::mem::transmute::<_, [{}; {}]>(",
+                ty.rust_scalar_type().replace("f", "NanEqF"),
+                num_lanes * ty.num_vectors()
+            ),
+            ")",
+        )
+    } else if ty.kind == TypeKind::Float {
+        (
+            match ty.inner_size() {
+                16 => format!("NanEqF16("),
+                32 => format!("NanEqF32("),
+                64 => format!("NanEqF64("),
+                _ => unimplemented!(),
+            },
+            ")",
+        )
+    } else {
+        ("".to_string(), "")
+    };
+
+    format!(
+        r#"
+assert_eq!(
+    {cast_prefix}__rust_return_value{cast_suffix},
+    {cast_prefix}__c_return_value{cast_suffix},
+    "{{id}}"
+);
+"#,
+    )
+}
diff --git a/library/stdarch/crates/intrinsic-test/src/common/mod.rs b/library/stdarch/crates/intrinsic-test/src/common/mod.rs
index b577491454e44..73daabbd6661a 100644
--- a/library/stdarch/crates/intrinsic-test/src/common/mod.rs
+++ b/library/stdarch/crates/intrinsic-test/src/common/mod.rs
@@ -10,7 +10,7 @@ use crate::common::{
         run_rustfmt, write_bin_cargo_toml, write_build_rs, write_lib_cargo_toml, write_lib_rs,
     },
     intrinsic::Intrinsic,
-    intrinsic_helpers::IntrinsicTypeDefinition,
+    intrinsic_helpers::TypeDefinition,
 };
 
 pub mod argument;
@@ -29,21 +29,19 @@ pub(crate) const PASSES: u32 = 20;
 
 /// Architectures must support this trait
 /// to be successfully tested.
-pub trait SupportedArchitectureTest {
-    type IntrinsicImpl: IntrinsicTypeDefinition + Sync;
+pub trait SupportedArchitecture: Sized {
+    type Type: TypeDefinition + std::fmt::Debug + PartialEq + Sync;
 
-    fn intrinsics(&self) -> &[Intrinsic<Self::IntrinsicImpl>];
+    fn intrinsics(&self) -> &[Intrinsic<Self>];
 
     fn create(cli_options: &ProcessedCli) -> Self;
 
     const NOTICE: &str;
 
-    const PLATFORM_C_HEADERS: &[&str];
+    const C_PRELUDE: &str;
+    const RUST_PRELUDE: &str;
 
-    const PLATFORM_RUST_CFGS: &str;
-    const PLATFORM_RUST_DEFINITIONS: &str;
-
-    fn arch_flags(&self, cli_options: &ProcessedCli) -> Vec<&str>;
+    fn c_compiler_flags(&self, cli_options: &ProcessedCli) -> Vec<&str>;
 
     fn generate_c_file(&self) {
         let (max_chunk_size, _chunk_count) = manual_chunk(self.intrinsics().len());
@@ -55,14 +53,14 @@ pub trait SupportedArchitectureTest {
             .map(|(i, chunk)| {
                 let c_filename = format!("c_programs/wrapper_{i}.c");
                 let mut file = File::create(&c_filename).unwrap();
-                write_wrapper_c(&mut file, Self::NOTICE, Self::PLATFORM_C_HEADERS, chunk)
+                write_wrapper_c(&mut file, chunk)
             })
             .collect::<io::Result<()>>()
             .unwrap();
     }
 
     fn generate_rust_file(&self, cli_options: &ProcessedCli) {
-        let arch_flags = self.arch_flags(cli_options);
+        let arch_flags = self.c_compiler_flags(cli_options);
 
         std::fs::create_dir_all("rust_programs").unwrap();
 
@@ -81,14 +79,7 @@ pub trait SupportedArchitectureTest {
                 trace!("generating `{rust_filename}`");
                 let mut file = File::create(&rust_filename)?;
 
-                write_lib_rs(
-                    &mut file,
-                    Self::NOTICE,
-                    Self::PLATFORM_RUST_CFGS,
-                    Self::PLATFORM_RUST_DEFINITIONS,
-                    i,
-                    chunk,
-                )?;
+                write_lib_rs(&mut file, i, chunk)?;
                 run_rustfmt(&rust_filename);
 
                 let toml_filename = format!("rust_programs/mod_{i}/Cargo.toml");
diff --git a/library/stdarch/crates/intrinsic-test/src/common/values.rs b/library/stdarch/crates/intrinsic-test/src/common/values.rs
index 4c3dd078e034f..8c549346ce6ed 100644
--- a/library/stdarch/crates/intrinsic-test/src/common/values.rs
+++ b/library/stdarch/crates/intrinsic-test/src/common/values.rs
@@ -2,7 +2,7 @@ use itertools::Itertools as _;
 
 use crate::common::{
     PASSES,
-    intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, SimdLen, TypeKind},
+    intrinsic_helpers::{IntrinsicType, Sign, SimdLen, TypeDefinition, TypeKind},
 };
 
 /// Maximum size of a SVE vector
@@ -18,13 +18,13 @@ pub const MAX_SVE_BITS: u32 = 2048;
 ///     0x80, 0x3b, 0xff,
 /// ];
 /// ```
-pub fn test_values_array_static<T: IntrinsicTypeDefinition>(
+pub fn test_values_array_static<T: TypeDefinition>(
     w: &mut impl std::io::Write,
     ty: &T,
 ) -> std::io::Result<()> {
     writeln!(
         w,
-        "static {name}: [{ty}; {load_size}] = {values};\n",
+        "static {name}: [{ty}; {load_size}] = {values};",
         name = test_values_array_name(ty),
         ty = ty.rust_scalar_type(),
         load_size = test_values_array_length(&ty),
@@ -34,7 +34,7 @@ pub fn test_values_array_static<T: IntrinsicTypeDefinition>(
 
 /// Returns a string with the name of the static variable containing test values for intrinsic
 /// arguments of this type.
-pub fn test_values_array_name<T: IntrinsicTypeDefinition>(ty: &T) -> String {
+pub fn test_values_array_name<T: TypeDefinition>(ty: &T) -> String {
     format!(
         "{ty}_{load_size}",
         ty = ty.rust_scalar_type().to_uppercase(),
diff --git a/library/stdarch/crates/intrinsic-test/src/main.rs b/library/stdarch/crates/intrinsic-test/src/main.rs
index 4c0136041fc35..e25eb48a456d1 100644
--- a/library/stdarch/crates/intrinsic-test/src/main.rs
+++ b/library/stdarch/crates/intrinsic-test/src/main.rs
@@ -5,10 +5,10 @@ mod arm;
 mod common;
 mod x86;
 
-use arm::ArmArchitectureTest;
-use common::SupportedArchitectureTest;
+use arm::Arm;
+use common::SupportedArchitecture;
 use common::cli::{Cli, ProcessedCli};
-use x86::X86ArchitectureTest;
+use x86::X86;
 
 fn main() {
     pretty_env_logger::init();
@@ -18,21 +18,15 @@ fn main() {
     if processed_cli_options.target.starts_with("arm")
         | processed_cli_options.target.starts_with("aarch64")
     {
-        run(
-            ArmArchitectureTest::create(&processed_cli_options),
-            processed_cli_options,
-        )
+        run(Arm::create(&processed_cli_options), processed_cli_options)
     } else if processed_cli_options.target.starts_with("x86") {
-        run(
-            X86ArchitectureTest::create(&processed_cli_options),
-            processed_cli_options,
-        )
+        run(X86::create(&processed_cli_options), processed_cli_options)
     } else {
         unimplemented!("Unsupported target {}", processed_cli_options.target)
     }
 }
 
-fn run(test_environment: impl SupportedArchitectureTest, processed_cli_options: ProcessedCli) {
+fn run(test_environment: impl SupportedArchitecture, processed_cli_options: ProcessedCli) {
     info!("building C binaries");
     test_environment.generate_c_file();
 
diff --git a/library/stdarch/crates/intrinsic-test/src/x86/config.rs b/library/stdarch/crates/intrinsic-test/src/x86/config.rs
deleted file mode 100644
index 68737ab5ac4c8..0000000000000
--- a/library/stdarch/crates/intrinsic-test/src/x86/config.rs
+++ /dev/null
@@ -1,138 +0,0 @@
-pub const NOTICE: &str = "\
-// This is a transient test file, not intended for distribution. Some aspects of the
-// test are derived from an XML specification, published under the same license as the
-// `intrinsic-test` crate.\n";
-
-pub const PLATFORM_RUST_DEFINITIONS: &str = r#"
-use core_arch::arch::x86_64::*;
-
-#[inline]
-unsafe fn _mm_loadu_ph_to___m128i(mem_addr: *const f16) -> __m128i {
-    _mm_castph_si128(_mm_loadu_ph(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm256_loadu_ph_to___m256i(mem_addr: *const f16) -> __m256i {
-    _mm256_castph_si256(_mm256_loadu_ph(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm512_loadu_ph_to___mm512i(mem_addr: *const f16) -> __m512i {
-    _mm512_castph_si512(_mm512_loadu_ph(mem_addr))
-}
-
-
-#[inline]
-unsafe fn _mm_loadu_ps_to___m128h(mem_addr: *const f32) -> __m128h {
-    _mm_castps_ph(_mm_loadu_ps(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm256_loadu_ps_to___m256h(mem_addr: *const f32) -> __m256h {
-    _mm256_castps_ph(_mm256_loadu_ps(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm512_loadu_ps_to___m512h(mem_addr: *const f32) -> __m512h {
-    _mm512_castps_ph(_mm512_loadu_ps(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm_loadu_epi16_to___m128d(mem_addr: *const i16) -> __m128d {
-    _mm_castsi128_pd(_mm_loadu_epi16(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm256_loadu_epi16_to___m256d(mem_addr: *const i16) -> __m256d {
-    _mm256_castsi256_pd(_mm256_loadu_epi16(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm512_loadu_epi16_to___m512d(mem_addr: *const i16) -> __m512d {
-    _mm512_castsi512_pd(_mm512_loadu_epi16(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm_loadu_epi32_to___m128d(mem_addr: *const i32) -> __m128d {
-    _mm_castsi128_pd(_mm_loadu_epi32(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm256_loadu_epi32_to___m256d(mem_addr: *const i32) -> __m256d {
-    _mm256_castsi256_pd(_mm256_loadu_epi32(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm512_loadu_epi32_to___m512d(mem_addr: *const i32) -> __m512d {
-    _mm512_castsi512_pd(_mm512_loadu_epi32(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm_loadu_epi64_to___m128d(mem_addr: *const i64) -> __m128d {
-    _mm_castsi128_pd(_mm_loadu_epi64(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm256_loadu_epi64_to___m256d(mem_addr: *const i64) -> __m256d {
-    _mm256_castsi256_pd(_mm256_loadu_epi64(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm512_loadu_epi64_to___m512d(mem_addr: *const i64) -> __m512d {
-    _mm512_castsi512_pd(_mm512_loadu_epi64(mem_addr))
-}
-
-// === 
-#[inline]
-unsafe fn _mm_loadu_epi16_to___m128(mem_addr: *const i16) -> __m128 {
-    _mm_castsi128_ps(_mm_loadu_epi16(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm256_loadu_epi16_to___m256(mem_addr: *const i16) -> __m256 {
-    _mm256_castsi256_ps(_mm256_loadu_epi16(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm512_loadu_epi16_to___m512(mem_addr: *const i16) -> __m512 {
-    _mm512_castsi512_ps(_mm512_loadu_epi16(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm_loadu_epi32_to___m128(mem_addr: *const i32) -> __m128 {
-    _mm_castsi128_ps(_mm_loadu_epi32(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm256_loadu_epi32_to___m256(mem_addr: *const i32) -> __m256 {
-    _mm256_castsi256_ps(_mm256_loadu_epi32(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm512_loadu_epi32_to___m512(mem_addr: *const i32) -> __m512 {
-    _mm512_castsi512_ps(_mm512_loadu_epi32(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm_loadu_epi64_to___m128(mem_addr: *const i64) -> __m128 {
-    _mm_castsi128_ps(_mm_loadu_epi64(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm256_loadu_epi64_to___m256(mem_addr: *const i64) -> __m256 {
-    _mm256_castsi256_ps(_mm256_loadu_epi64(mem_addr))
-}
-
-#[inline]
-unsafe fn _mm512_loadu_epi64_to___m512(mem_addr: *const i64) -> __m512 {
-    _mm512_castsi512_ps(_mm512_loadu_epi64(mem_addr))
-}
-
-"#;
-
-pub const PLATFORM_RUST_CFGS: &str = r#"
-#![feature(stdarch_x86_avx512_bf16)]
-#![feature(stdarch_x86_avx512_f16)]
-#![feature(stdarch_x86_rtm)]
-#![feature(x86_amx_intrinsics)]
-"#;
diff --git a/library/stdarch/crates/intrinsic-test/src/x86/mod.rs b/library/stdarch/crates/intrinsic-test/src/x86/mod.rs
index 288bd8bdf8961..ce4955032916d 100644
--- a/library/stdarch/crates/intrinsic-test/src/x86/mod.rs
+++ b/library/stdarch/crates/intrinsic-test/src/x86/mod.rs
@@ -1,35 +1,38 @@
-mod config;
 mod constraint;
 mod intrinsic;
 mod types;
 mod xml_parser;
 
-use crate::common::SupportedArchitectureTest;
+use crate::common::SupportedArchitecture;
 use crate::common::cli::ProcessedCli;
 use crate::common::intrinsic::Intrinsic;
 use crate::common::intrinsic_helpers::TypeKind;
 use intrinsic::X86IntrinsicType;
 use xml_parser::get_xml_intrinsics;
 
-pub struct X86ArchitectureTest {
-    intrinsics: Vec<Intrinsic<X86IntrinsicType>>,
+pub struct X86 {
+    intrinsics: Vec<Intrinsic<X86>>,
 }
 
-impl SupportedArchitectureTest for X86ArchitectureTest {
-    type IntrinsicImpl = X86IntrinsicType;
+impl SupportedArchitecture for X86 {
+    type Type = X86IntrinsicType;
 
-    fn intrinsics(&self) -> &[Intrinsic<X86IntrinsicType>] {
+    fn intrinsics(&self) -> &[Intrinsic<Self>] {
         &self.intrinsics
     }
 
-    const NOTICE: &str = config::NOTICE;
+    const NOTICE: &str = r#"
+// This is a transient test file, not intended for distribution. Some aspects of the
+// test are derived from an XML specification, published under the same license as the
+// `intrinsic-test` crate.
+"#;
 
-    const PLATFORM_C_HEADERS: &[&str] = &["immintrin.h"];
+    const C_PRELUDE: &str = r#"
+#include <immintrin.h>
+"#;
+    const RUST_PRELUDE: &str = RUST_PRELUDE;
 
-    const PLATFORM_RUST_DEFINITIONS: &str = config::PLATFORM_RUST_DEFINITIONS;
-    const PLATFORM_RUST_CFGS: &str = config::PLATFORM_RUST_CFGS;
-
-    fn arch_flags(&self, _cli_options: &ProcessedCli) -> Vec<&str> {
+    fn c_compiler_flags(&self, _cli_options: &ProcessedCli) -> Vec<&str> {
         vec![
             "-maes",
             "-mf16c",
@@ -97,3 +100,134 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
         Self { intrinsics }
     }
 }
+
+const RUST_PRELUDE: &str = r#"
+#![feature(stdarch_x86_avx512_bf16)]
+#![feature(stdarch_x86_avx512_f16)]
+#![feature(stdarch_x86_rtm)]
+#![feature(x86_amx_intrinsics)]
+
+use core_arch::arch::x86_64::*;
+
+#[inline]
+unsafe fn _mm_loadu_ph_to___m128i(mem_addr: *const f16) -> __m128i {
+    _mm_castph_si128(_mm_loadu_ph(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_ph_to___m256i(mem_addr: *const f16) -> __m256i {
+    _mm256_castph_si256(_mm256_loadu_ph(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_ph_to___mm512i(mem_addr: *const f16) -> __m512i {
+    _mm512_castph_si512(_mm512_loadu_ph(mem_addr))
+}
+
+
+#[inline]
+unsafe fn _mm_loadu_ps_to___m128h(mem_addr: *const f32) -> __m128h {
+    _mm_castps_ph(_mm_loadu_ps(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_ps_to___m256h(mem_addr: *const f32) -> __m256h {
+    _mm256_castps_ph(_mm256_loadu_ps(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_ps_to___m512h(mem_addr: *const f32) -> __m512h {
+    _mm512_castps_ph(_mm512_loadu_ps(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm_loadu_epi16_to___m128d(mem_addr: *const i16) -> __m128d {
+    _mm_castsi128_pd(_mm_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi16_to___m256d(mem_addr: *const i16) -> __m256d {
+    _mm256_castsi256_pd(_mm256_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi16_to___m512d(mem_addr: *const i16) -> __m512d {
+    _mm512_castsi512_pd(_mm512_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm_loadu_epi32_to___m128d(mem_addr: *const i32) -> __m128d {
+    _mm_castsi128_pd(_mm_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi32_to___m256d(mem_addr: *const i32) -> __m256d {
+    _mm256_castsi256_pd(_mm256_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi32_to___m512d(mem_addr: *const i32) -> __m512d {
+    _mm512_castsi512_pd(_mm512_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm_loadu_epi64_to___m128d(mem_addr: *const i64) -> __m128d {
+    _mm_castsi128_pd(_mm_loadu_epi64(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi64_to___m256d(mem_addr: *const i64) -> __m256d {
+    _mm256_castsi256_pd(_mm256_loadu_epi64(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi64_to___m512d(mem_addr: *const i64) -> __m512d {
+    _mm512_castsi512_pd(_mm512_loadu_epi64(mem_addr))
+}
+
+// === 
+#[inline]
+unsafe fn _mm_loadu_epi16_to___m128(mem_addr: *const i16) -> __m128 {
+    _mm_castsi128_ps(_mm_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi16_to___m256(mem_addr: *const i16) -> __m256 {
+    _mm256_castsi256_ps(_mm256_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi16_to___m512(mem_addr: *const i16) -> __m512 {
+    _mm512_castsi512_ps(_mm512_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm_loadu_epi32_to___m128(mem_addr: *const i32) -> __m128 {
+    _mm_castsi128_ps(_mm_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi32_to___m256(mem_addr: *const i32) -> __m256 {
+    _mm256_castsi256_ps(_mm256_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi32_to___m512(mem_addr: *const i32) -> __m512 {
+    _mm512_castsi512_ps(_mm512_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm_loadu_epi64_to___m128(mem_addr: *const i64) -> __m128 {
+    _mm_castsi128_ps(_mm_loadu_epi64(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi64_to___m256(mem_addr: *const i64) -> __m256 {
+    _mm256_castsi256_ps(_mm256_loadu_epi64(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi64_to___m512(mem_addr: *const i64) -> __m512 {
+    _mm512_castsi512_ps(_mm512_loadu_epi64(mem_addr))
+}
+"#;
diff --git a/library/stdarch/crates/intrinsic-test/src/x86/types.rs b/library/stdarch/crates/intrinsic-test/src/x86/types.rs
index a0e14c77d6b5e..2cba54a73f767 100644
--- a/library/stdarch/crates/intrinsic-test/src/x86/types.rs
+++ b/library/stdarch/crates/intrinsic-test/src/x86/types.rs
@@ -3,12 +3,10 @@ use std::str::FromStr;
 use itertools::Itertools;
 
 use super::intrinsic::X86IntrinsicType;
-use crate::common::intrinsic_helpers::{
-    IntrinsicType, IntrinsicTypeDefinition, Sign, SimdLen, TypeKind,
-};
+use crate::common::intrinsic_helpers::{IntrinsicType, Sign, SimdLen, TypeDefinition, TypeKind};
 use crate::x86::xml_parser::Parameter;
 
-impl IntrinsicTypeDefinition for X86IntrinsicType {
+impl TypeDefinition for X86IntrinsicType {
     /// Gets a string containing the type in C format.
     /// This function assumes that this value is present in the metadata hashmap.
     fn c_type(&self) -> String {
@@ -50,7 +48,7 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
     }
 
     /// Determines the load function for this type.
-    fn get_load_function(&self) -> String {
+    fn load_function(&self) -> String {
         let type_value = self.param.type_data.clone();
         if type_value.len() == 0 {
             unimplemented!("the value for key 'type' is not present!");
diff --git a/library/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs b/library/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs
index 6006d7919f875..52f6da786e3d7 100644
--- a/library/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/library/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -1,6 +1,7 @@
 use crate::common::argument::{Argument, ArgumentList};
 use crate::common::intrinsic::Intrinsic;
 use crate::common::intrinsic_helpers::TypeKind;
+use crate::x86::X86;
 use crate::x86::constraint::map_constraints;
 
 use regex::Regex;
@@ -56,13 +57,13 @@ pub struct Parameter {
 
 pub fn get_xml_intrinsics(
     filename: &Path,
-) -> Result<Vec<Intrinsic<X86IntrinsicType>>, Box<dyn std::error::Error>> {
+) -> Result<Vec<Intrinsic<X86>>, Box<dyn std::error::Error>> {
     let file = std::fs::File::open(filename)?;
     let reader = std::io::BufReader::new(file);
     let data: Data =
         quick_xml::de::from_reader(reader).expect("failed to deserialize the source XML file");
 
-    let parsed_intrinsics: Vec<Intrinsic<X86IntrinsicType>> = data
+    let parsed_intrinsics: Vec<Intrinsic<X86>> = data
         .intrinsics
         .into_iter()
         .filter(|intrinsic| {
@@ -84,9 +85,7 @@ pub fn get_xml_intrinsics(
     Ok(parsed_intrinsics)
 }
 
-fn xml_to_intrinsic(
-    intr: XMLIntrinsic,
-) -> Result<Intrinsic<X86IntrinsicType>, Box<dyn std::error::Error>> {
+fn xml_to_intrinsic(intr: XMLIntrinsic) -> Result<Intrinsic<X86>, Box<dyn std::error::Error>> {
     let name = intr.name;
     let result = X86IntrinsicType::from_param(&intr.return_data);
     let args_check = intr.parameters.into_iter().enumerate().map(|(i, param)| {
@@ -100,12 +99,7 @@ fn xml_to_intrinsic(
                 param.imm_width
             };
             let constraint = map_constraints(&name, &param.imm_type, effective_imm_width);
-            let arg = Argument::<X86IntrinsicType>::new(
-                i,
-                param.var_name.clone(),
-                ty.unwrap(),
-                constraint,
-            );
+            let arg = Argument::<X86>::new(i, param.var_name.clone(), ty.unwrap(), constraint);
             Some(arg)
         }
     });
@@ -125,8 +119,8 @@ fn xml_to_intrinsic(
     // if one of the args has etype="MASK" and type="__m<int>d",
     // then set the bit_len and simd_len accordingly
     let re = Regex::new(r"__m\d+").unwrap();
-    let is_mask = |arg: &Argument<X86IntrinsicType>| arg.ty.param.etype.as_str() == "MASK";
-    let is_vector = |arg: &Argument<X86IntrinsicType>| re.is_match(arg.ty.param.type_data.as_str());
+    let is_mask = |arg: &Argument<X86>| arg.ty.param.etype.as_str() == "MASK";
+    let is_vector = |arg: &Argument<X86>| re.is_match(arg.ty.param.type_data.as_str());
     let pos = args_test.position(|arg| is_mask(arg) && is_vector(arg));
     if let Some(index) = pos {
         args[index].ty.bit_len = args[0].ty.bit_len;
@@ -134,7 +128,7 @@ fn xml_to_intrinsic(
 
     args.iter_mut().for_each(|arg| arg.ty.update_simd_len());
 
-    let arguments = ArgumentList::<X86IntrinsicType> { args };
+    let arguments = ArgumentList::<X86> { args };
 
     if let Err(message) = result {
         return Err(Box::from(message));
@@ -145,5 +139,6 @@ fn xml_to_intrinsic(
         arguments,
         results: result.unwrap(),
         arch_tags: intr.cpuid,
+        extension: intr.tech,
     })
 }
diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 03fea5e0a4af3..e5ce77ed8b33f 100644
--- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -13951,7 +13951,7 @@ intrinsics:
             - 'b: {neon_type[1]}'
             - 'n: i32'
           links:
-            - link: "llvm.aarch64.neon.vluti4q.lane.{neon_type[1]}"
+            - link: "llvm.aarch64.neon.vluti4q.lane.{neon_type[0]}"
               arch: aarch64,arm64ec
       - FnCall: ['_vluti4{neon_type[0].lane_nox}', [a, b, LANE]]
 
@@ -14002,7 +14002,7 @@ intrinsics:
             - 'b: {neon_type[1]}'
             - 'n: i32'
           links:
-            - link: "llvm.aarch64.neon.vluti4q.laneq.{neon_type[1]}"
+            - link: "llvm.aarch64.neon.vluti4q.laneq.{neon_type[0]}"
               arch: aarch64,arm64ec
       - FnCall: ['_vluti4{neon_type[0].laneq_nox}', [a, b, LANE]]
 
diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
index 29dd3a095d7e6..138d5ba31175b 100644
--- a/library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
@@ -115,7 +115,7 @@ intrinsics:
     assert_instr: [[fcmla, "IMM_INDEX = 0, IMM_ROTATION = 90"]]
     compose:
       - LLVMLink:
-          name: fcmla.lane.x.{sve_type}
+          name: fcmla.lane.{sve_type}
           arguments:
             - "op1: {sve_type}"
             - "op2: {sve_type}"
@@ -1021,7 +1021,7 @@ intrinsics:
     doc: Interleave elements from low halves of two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
     assert_instr: [zip1]
     compose:
       - LLVMLink: { name: "zip1.{sve_type}" }
@@ -1031,10 +1031,13 @@ intrinsics:
     doc: Interleave elements from low halves of two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [b8, b16, b32, b64]
+    types: [b16, b32, b64]
     assert_instr: [zip1]
     compose:
-      - LLVMLink: { name: "zip1.{sve_type}" }
+      - LLVMLink:
+          name: "llvm.aarch64.sve.zip1.b{size}"
+          arguments: ["op1: svbool_t", "op2: svbool_t"]
+          return_type: "svbool_t"
 
   - name: svzip1q[_{type}]
     attr: [*sve-unstable]
@@ -1052,7 +1055,7 @@ intrinsics:
     doc: Interleave elements from high halves of two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
     assert_instr: [zip2]
     compose:
       - LLVMLink: { name: "zip2.{sve_type}" }
@@ -1062,10 +1065,13 @@ intrinsics:
     doc: Interleave elements from high halves of two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [b8, b16, b32, b64]
+    types: [b16, b32, b64]
     assert_instr: [zip2]
     compose:
-      - LLVMLink: { name: "zip2.{sve_type}" }
+      - LLVMLink:
+          name: "llvm.aarch64.sve.zip2.b{size}"
+          arguments: ["op1: svbool_t", "op2: svbool_t"]
+          return_type: "svbool_t"
 
   - name: svzip2q[_{type}]
     attr: [*sve-unstable]
@@ -1083,7 +1089,7 @@ intrinsics:
     doc: Concatenate even elements from two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
     assert_instr: [uzp1]
     compose:
       - LLVMLink: { name: "uzp1.{sve_type}" }
@@ -1093,10 +1099,13 @@ intrinsics:
     doc: Concatenate even elements from two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [b8, b16, b32, b64]
+    types: [b16, b32, b64]
     assert_instr: [uzp1]
     compose:
-      - LLVMLink: { name: "uzp1.{sve_type}" }
+      - LLVMLink:
+          name: "llvm.aarch64.sve.uzp1.b{size}"
+          arguments: ["op1: svbool_t", "op2: svbool_t"]
+          return_type: "svbool_t"
 
   - name: svuzp1q[_{type}]
     attr: [*sve-unstable]
@@ -1114,7 +1123,7 @@ intrinsics:
     doc: Concatenate odd elements from two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
     assert_instr: [uzp2]
     compose:
       - LLVMLink: { name: "uzp2.{sve_type}" }
@@ -1124,10 +1133,13 @@ intrinsics:
     doc: Concatenate odd elements from two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [b8, b16, b32, b64]
+    types: [b16, b32, b64]
     assert_instr: [uzp2]
     compose:
-      - LLVMLink: { name: "uzp2.{sve_type}" }
+      - LLVMLink:
+          name: "llvm.aarch64.sve.uzp2.b{size}"
+          arguments: ["op1: svbool_t", "op2: svbool_t"]
+          return_type: "svbool_t"
 
   - name: svuzp2q[_{type}]
     attr: [*sve-unstable]
@@ -1207,7 +1219,7 @@ intrinsics:
     doc: Reverse all elements
     arguments: ["op: {sve_type}"]
     return_type: "{sve_type}"
-    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
     assert_instr: [rev]
     compose:
       - LLVMLink: { name: "llvm.vector.reverse.{sve_type}" }
@@ -1217,10 +1229,13 @@ intrinsics:
     doc: Reverse all elements
     arguments: ["op: {sve_type}"]
     return_type: "{sve_type}"
-    types: [b8, b16, b32, b64]
+    types: [b16, b32, b64]
     assert_instr: [rev]
     compose:
-      - LLVMLink: { name: "llvm.vector.reverse.{sve_type}" }
+      - LLVMLink:
+          name: "llvm.aarch64.sve.rev.b{size}"
+          arguments: ["op: svbool_t"]
+          return_type: "svbool_t"
 
   - name: svrevb[_{type}]{_mxz}
     attr: [*sve-unstable]
@@ -4179,7 +4194,8 @@ intrinsics:
       ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
     return_type: "{sve_type[0]}"
     types:
-      - [[f32, f64], [i32, u32, i64, u64]]
+      - [f32, [i64, u64]]
+      - [f64, [i32, u32]]
     zeroing_method: { drop: inactive }
     substitutions:
       convert_from: { match_kind: "{type[1]}", default: s, unsigned: u }
@@ -4187,6 +4203,23 @@ intrinsics:
     compose:
       - LLVMLink:
           name: "{convert_from}cvtf.{type[0]}{type[1]}"
+  
+  - name: svcvt_{type[0]}[_{type[1]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Floating-point convert
+    arguments:
+      ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [f32, [i32, u32]]
+      - [f64, [i64, u64]]
+    zeroing_method: { drop: inactive }
+    substitutions:
+      convert_from: { match_kind: "{type[1]}", default: s, unsigned: u }
+    assert_instr: ["{convert_from}cvtf"]
+    compose:
+      - LLVMLink:
+          name: "{convert_from}cvtf.{sve_type[0]}.{sve_type[1]}"
 
   - name: svcvt_{type[0]}[_{type[1]}]{_mxz}
     attr: [*sve-unstable]
@@ -4195,13 +4228,30 @@ intrinsics:
       ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
     return_type: "{sve_type[0]}"
     types:
-      - [[i32, u32, i64, u64], [f32, f64]]
+      - [[i32, u32], f64]
+      - [[i64, u64], f32]
     zeroing_method: { drop: inactive }
     substitutions:
       convert_to: { match_kind: "{type[0]}", default: s, unsigned: u }
     assert_instr: ["fcvtz{convert_to}"]
     compose:
       - LLVMLink: { name: "fcvtz{convert_to}.{type[0]}{type[1]}" }
+  
+  - name: svcvt_{type[0]}[_{type[1]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Floating-point convert
+    arguments:
+      ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i32, u32], f32]
+      - [[i64, u64], f64]
+    zeroing_method: { drop: inactive }
+    substitutions:
+      convert_to: { match_kind: "{type[0]}", default: s, unsigned: u }
+    assert_instr: ["fcvtz{convert_to}"]
+    compose:
+      - LLVMLink: { name: "fcvtz{convert_to}.{sve_type[0]}.{sve_type[1]}" }
 
   - name: svcvt_{type[0]}[_{type[1]}]{_mxz}
     attr: [*sve-unstable]
@@ -4356,7 +4406,7 @@ intrinsics:
     return_type: svbool_t
     assert_instr: [and]
     compose:
-      - LLVMLink: { name: "and.z.nvx16i1" }
+      - LLVMLink: { name: "and.z.nxv16i1" }
 
   - name: svmov[_b]_z
     attr: [*sve-unstable]
@@ -4386,7 +4436,7 @@ intrinsics:
     return_type: svbool_t
     assert_instr: [bic]
     compose:
-      - LLVMLink: { name: "bic.z.nvx16i1" }
+      - LLVMLink: { name: "bic.z.nxv16i1" }
 
   - name: sveor[{_n}_{type}]{_mxz}
     attr: [*sve-unstable]
@@ -4417,7 +4467,7 @@ intrinsics:
     return_type: svbool_t
     assert_instr: [eor]
     compose:
-      - LLVMLink: { name: "eor.z.nvx16i1" }
+      - LLVMLink: { name: "eor.z.nxv16i1" }
 
   - name: svnot[_{type}]{_mxz}
     attr: [*sve-unstable]
@@ -4497,7 +4547,7 @@ intrinsics:
     return_type: svbool_t
     assert_instr: [orr]
     compose:
-      - LLVMLink: { name: "orr.z.nvx16i1" }
+      - LLVMLink: { name: "orr.z.nxv16i1" }
 
   - name: svorn[_b]_z
     attr: [*sve-unstable]
@@ -4506,7 +4556,7 @@ intrinsics:
     return_type: svbool_t
     assert_instr: [orn]
     compose:
-      - LLVMLink: { name: "orn.z.nvx16i1" }
+      - LLVMLink: { name: "orn.z.nxv16i1" }
 
   - name: svlsl[{_n}_{type[0]}]{_mxz}
     attr: [*sve-unstable]
@@ -4749,7 +4799,7 @@ intrinsics:
     assert_instr: [frecpx]
     zeroing_method: { drop: inactive }
     compose:
-      - LLVMLink: { name: "frecpx.x.{sve_type}" }
+      - LLVMLink: { name: "frecpx.{sve_type}" }
 
   - name: svrsqrte[_{type}]
     attr: [*sve-unstable]
@@ -5115,7 +5165,7 @@ intrinsics:
     types: [[f32, u32], [f64, u64]]
     assert_instr: [fexpa]
     compose:
-      - LLVMLink: { name: "fexpa.x.{sve_type[0]} " }
+      - LLVMLink: { name: "fexpa.x.{sve_type[0]}" }
 
   - name: svscale[{_n}_{type[0]}]{_mxz}
     attr: [*sve-unstable]
@@ -5139,7 +5189,7 @@ intrinsics:
     types: [f32]
     assert_instr: [fmmla]
     compose:
-      - LLVMLink: { name: "fmmla.{sve_type}" }
+      - LLVMLink: { name: "fmmla.{sve_type}.{sve_type}" }
 
   - name: svmmla[_{type}]
     attr: [*sve-unstable]
@@ -5150,7 +5200,7 @@ intrinsics:
     types: [f64]
     assert_instr: [fmmla]
     compose:
-      - LLVMLink: { name: "fmmla.{sve_type}" }
+      - LLVMLink: { name: "fmmla.{sve_type}.{sve_type}" }
 
   - name: svmmla[_{type[0]}]
     attr: [*sve-unstable]
diff --git a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
index 72fb97fee1f08..f96f05dfec680 100644
--- a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -1604,6 +1604,7 @@ impl Intrinsic {
                             (Some(BaseTypeKind::Float), Some(BaseTypeKind::Float)) => ex,
                             (Some(BaseTypeKind::UInt), Some(BaseTypeKind::UInt)) => ex,
                             (Some(BaseTypeKind::Poly), Some(BaseTypeKind::Poly)) => ex,
+                            (Some(BaseTypeKind::Bool), Some(BaseTypeKind::Bool)) => ex,
 
                             (None, None) => ex,
                             _ => unreachable!(
diff --git a/library/stdarch/crates/stdarch-gen-common/Cargo.toml b/library/stdarch/crates/stdarch-gen-common/Cargo.toml
new file mode 100644
index 0000000000000..691be14971a0d
--- /dev/null
+++ b/library/stdarch/crates/stdarch-gen-common/Cargo.toml
@@ -0,0 +1,7 @@
+[package]
+name = "stdarch-gen-common"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+tempfile = "3"
\ No newline at end of file
diff --git a/library/stdarch/crates/stdarch-gen-common/src/lib.rs b/library/stdarch/crates/stdarch-gen-common/src/lib.rs
new file mode 100644
index 0000000000000..13d788594ca55
--- /dev/null
+++ b/library/stdarch/crates/stdarch-gen-common/src/lib.rs
@@ -0,0 +1,352 @@
+//! Shared check/bless harness for stdarch generators.
+
+use std::error::Error as StdError;
+use std::fmt;
+use std::fs;
+use std::io;
+use std::io::Read;
+use std::path::{Path, PathBuf};
+
+/// First-line marker identifying an auto-generated file. Generators emit this
+/// as the first line of every file they produce; the harness uses it to
+/// discover which files in `committed` are owned by the generator.
+pub const GENERATED_MARKER: &str = "// This code is automatically generated. DO NOT MODIFY.";
+
+/// Controls what `run_generator` does with the generator's output.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum Mode {
+    /// Verify that the `committed` matches the generator's output for owned files.
+    ///
+    /// Runs the generator into a temp directory, then compares each produced
+    /// file against the committed copy. Returns an error on the first mismatch.
+    Check,
+    /// Update the `committed` to match the generator's output for owned files.
+    ///
+    /// Runs the generator into a temp directory and copies each produced file
+    /// into `committed`. If the generator no longer produces an owned file, the
+    /// committed copy is deleted. Files in `committed` that are not owned
+    /// are left untouched.
+    Bless,
+}
+
+impl Mode {
+    /// Read the mode from the `STDARCH_GEN_MODE` environment variable.
+    ///
+    /// Recognized values:
+    /// - `"check"` → [`Mode::Check`]
+    /// - `"bless"` → [`Mode::Bless`]
+    /// - unset → [`Mode::Bless`]
+    /// - any other value → panic
+    pub fn from_env() -> Self {
+        match std::env::var("STDARCH_GEN_MODE").as_deref() {
+            Ok("check") => Mode::Check,
+            Ok("bless") => Mode::Bless,
+            Ok(other) => panic!("unknown STDARCH_GEN_MODE value: {other:?}"),
+            Err(_) => Mode::Bless,
+        }
+    }
+}
+
+#[derive(Debug)]
+pub enum Error {
+    Io(io::Error),
+    Mismatch { path: PathBuf, kind: MismatchKind },
+    Generator(Box<dyn StdError + Send + Sync>),
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum MismatchKind {
+    /// Owned file produced by the generator but absent from the `committed`.
+    /// Means the `committed` needs to be regenerated.
+    MissingInCommitted,
+    /// Owned file present in the `committed` but the generator no longer
+    /// produces it. The file must be removed from the `committed` .
+    ExtraInCommitted,
+    /// Owned file exists on both sides but contents differ.
+    ContentsDiffer,
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            Error::Io(e) => write!(f, "I/O error: {e}"),
+            Error::Mismatch { path, kind } => match kind {
+                MismatchKind::MissingInCommitted => {
+                    write!(f, "{}: generated but not committed", path.display())
+                }
+                MismatchKind::ExtraInCommitted => {
+                    write!(f, "{}: committed but no longer generated", path.display())
+                }
+                MismatchKind::ContentsDiffer => write!(f, "{}: contents differ", path.display()),
+            },
+            Error::Generator(e) => write!(f, "generator failed: {e}"),
+        }
+    }
+}
+
+impl StdError for Error {
+    fn source(&self) -> Option<&(dyn StdError + 'static)> {
+        match self {
+            Error::Io(e) => Some(e),
+            Error::Generator(e) => Some(&**e),
+            _ => None,
+        }
+    }
+}
+
+impl From<io::Error> for Error {
+    fn from(e: io::Error) -> Self {
+        Error::Io(e)
+    }
+}
+
+pub type Result<T> = std::result::Result<T, Error>;
+
+/// Run a generator under the chosen `mode`, reconciling its output with `committed`.
+///
+/// Arguments:
+/// - `committed` — the directory holding the in-tree (committed) source files.
+///   Files inside `committed` whose first line begins with [`GENERATED_MARKER`]
+///   are treated as owned by the generator. Anything else is treated as
+///   hand-written and is left untouched by `Bless` and ignored by `Check`.
+///   So generated files coexist with hand-written files in the same  directory.
+/// - `mode` — what to do with the generator's output.
+/// - `generate` — closure that writes the generator's output into the
+///   directory it is given. Its error is wrapped in [`Error::Generator`].
+///
+/// Behavior per mode:
+/// - [`Mode::Check`]: runs the generator into a temp dir and compares owned
+///   files against the committed copies. Mismatch returns [`Error::Mismatch`].
+/// - [`Mode::Bless`]: runs the generator into a temp dir and copies owned
+///   files into `committed`, or removes `committed`'s copy if the generator no
+///   longer produces them.
+pub fn run_generator<F, E>(committed: &Path, mode: Mode, generate: F) -> Result<()>
+where
+    F: FnOnce(&Path) -> std::result::Result<(), E>,
+    E: Into<Box<dyn StdError + Send + Sync>>,
+{
+    let scratch = tempfile::tempdir()?;
+    generate(scratch.path()).map_err(|e| Error::Generator(e.into()))?;
+
+    let owned = discover_owned(committed)?;
+    let produced = discover_all(scratch.path())?;
+
+    let mut names: Vec<&String> = owned.iter().chain(produced.iter()).collect();
+    names.sort();
+    names.dedup();
+
+    for name in names {
+        match mode {
+            Mode::Check => compare(scratch.path(), committed, name)?,
+            Mode::Bless => apply_bless(scratch.path(), committed, name)?,
+        }
+    }
+    Ok(())
+}
+
+/// Returns the names of files in `dir` whose first line begins with
+/// [`GENERATED_MARKER`]. Files without the marker are skipped.
+fn discover_owned(dir: &Path) -> Result<Vec<String>> {
+    let mut out = Vec::new();
+    for entry in fs::read_dir(dir)? {
+        let entry = entry?;
+        if !entry.file_type()?.is_file() {
+            continue;
+        }
+        let Ok(mut file) = fs::File::open(entry.path()) else {
+            continue;
+        };
+        let mut buf = [0u8; GENERATED_MARKER.len()];
+        if file.read_exact(&mut buf).is_err() {
+            continue;
+        }
+        if buf == *GENERATED_MARKER.as_bytes()
+            && let Some(name) = entry.file_name().to_str()
+        {
+            out.push(name.to_owned());
+        }
+    }
+    out.sort();
+    Ok(out)
+}
+
+/// Returns every file name in `dir` (scratch dir — all files are generator output).
+fn discover_all(dir: &Path) -> Result<Vec<String>> {
+    let mut out = Vec::new();
+    for entry in fs::read_dir(dir)? {
+        let entry = entry?;
+        if entry.file_type()?.is_file()
+            && let Some(name) = entry.file_name().to_str()
+        {
+            out.push(name.to_string());
+        }
+    }
+    Ok(out)
+}
+
+fn compare(generated_dir: &Path, committed_dir: &Path, filename: &str) -> Result<()> {
+    let rel_path = PathBuf::from(filename);
+    let gen_path = generated_dir.join(&rel_path);
+    let comm_path = committed_dir.join(&rel_path);
+    match (gen_path.exists(), comm_path.exists()) {
+        (true, false) => Err(Error::Mismatch {
+            path: rel_path,
+            kind: MismatchKind::MissingInCommitted,
+        }),
+        (false, true) => Err(Error::Mismatch {
+            path: rel_path,
+            kind: MismatchKind::ExtraInCommitted,
+        }),
+        (false, false) => Ok(()),
+        (true, true) => {
+            if fs::read(&gen_path)? != fs::read(&comm_path)? {
+                Err(Error::Mismatch {
+                    path: rel_path,
+                    kind: MismatchKind::ContentsDiffer,
+                })
+            } else {
+                Ok(())
+            }
+        }
+    }
+}
+
+fn apply_bless(generated_dir: &Path, committed_dir: &Path, filename: &str) -> Result<()> {
+    fs::create_dir_all(committed_dir)?;
+    let rel_path = PathBuf::from(filename);
+    let from = generated_dir.join(&rel_path);
+    let to = committed_dir.join(&rel_path);
+    if from.exists() {
+        if let Some(parent) = to.parent() {
+            fs::create_dir_all(parent)?;
+        }
+        fs::copy(&from, &to)?;
+    } else if to.exists() {
+        fs::remove_file(&to)?;
+    }
+    Ok(())
+}
+
+// Skipped on iOS because these tests fail on the `x86_64-apple-ios-macabi` CI runner
+// with `Os { code: 17, kind: AlreadyExists, message: "File exists" }`.
+#[cfg(all(test, not(target_os = "ios")))]
+mod tests {
+    use super::*;
+
+    fn write_marker(p: &Path, body: &[u8]) {
+        if let Some(d) = p.parent() {
+            fs::create_dir_all(d).unwrap();
+        }
+        let mut bytes = Vec::new();
+        bytes.extend_from_slice(GENERATED_MARKER.as_bytes());
+        bytes.push(b'\n');
+        bytes.extend_from_slice(body);
+        fs::write(p, bytes).unwrap();
+    }
+
+    #[test]
+    fn check_fails_on_byte_diff() {
+        let tmp = tempfile::tempdir().unwrap();
+        let committed = tmp.path().join("c");
+        write_marker(&committed.join("a.txt"), b"hi");
+        let e = run_generator(
+            &committed,
+            Mode::Check,
+            |out| -> std::result::Result<(), io::Error> {
+                write_marker(&out.join("a.txt"), b"HI");
+                Ok(())
+            },
+        )
+        .unwrap_err();
+        assert!(matches!(
+            e,
+            Error::Mismatch {
+                kind: MismatchKind::ContentsDiffer,
+                ..
+            }
+        ));
+    }
+
+    #[test]
+    fn check_fails_when_owned_file_missing_from_generated() {
+        let tmp = tempfile::tempdir().unwrap();
+        let committed = tmp.path().join("c");
+        write_marker(&committed.join("a.txt"), b"hi");
+        let e = run_generator(
+            &committed,
+            Mode::Check,
+            |_| -> std::result::Result<(), io::Error> { Ok(()) },
+        )
+        .unwrap_err();
+        assert!(matches!(
+            e,
+            Error::Mismatch {
+                kind: MismatchKind::ExtraInCommitted,
+                ..
+            }
+        ));
+    }
+
+    #[test]
+    fn check_fails_when_owned_file_missing_from_committed() {
+        let tmp = tempfile::tempdir().unwrap();
+        let committed = tmp.path().join("c");
+        fs::create_dir_all(&committed).unwrap();
+        let e = run_generator(
+            &committed,
+            Mode::Check,
+            |out| -> std::result::Result<(), io::Error> {
+                write_marker(&out.join("a.txt"), b"hi");
+                Ok(())
+            },
+        )
+        .unwrap_err();
+        assert!(matches!(
+            e,
+            Error::Mismatch {
+                kind: MismatchKind::MissingInCommitted,
+                ..
+            }
+        ));
+    }
+
+    #[test]
+    fn bless_deletes_files_no_longer_produced() {
+        let tmp = tempfile::tempdir().unwrap();
+        let committed = tmp.path().join("c");
+        write_marker(&committed.join("keep.txt"), b"");
+        write_marker(&committed.join("stale.txt"), b"");
+        run_generator(
+            &committed,
+            Mode::Bless,
+            |out| -> std::result::Result<(), io::Error> {
+                write_marker(&out.join("keep.txt"), b"");
+                Ok(())
+            },
+        )
+        .unwrap();
+        assert!(committed.join("keep.txt").exists());
+        assert!(!committed.join("stale.txt").exists());
+    }
+
+    #[test]
+    fn bless_preserves_unowned_files() {
+        let tmp = tempfile::tempdir().unwrap();
+        let committed = tmp.path().join("c");
+        fs::create_dir_all(&committed).unwrap();
+        fs::write(committed.join("mod.rs"), b"hand-written").unwrap();
+        fs::write(committed.join("old.txt"), b"old").unwrap();
+        run_generator(
+            &committed,
+            Mode::Bless,
+            |out| -> std::result::Result<(), io::Error> {
+                write_marker(&out.join("new.txt"), b"new");
+                Ok(())
+            },
+        )
+        .unwrap();
+        assert_eq!(fs::read(committed.join("mod.rs")).unwrap(), b"hand-written");
+        assert_eq!(fs::read(committed.join("old.txt")).unwrap(), b"old");
+        assert!(committed.join("new.txt").exists());
+    }
+}
diff --git a/library/stdarch/crates/stdarch-gen-hexagon/Cargo.toml b/library/stdarch/crates/stdarch-gen-hexagon/Cargo.toml
index 397c7816f8d1e..c7dfce2c0fd7b 100644
--- a/library/stdarch/crates/stdarch-gen-hexagon/Cargo.toml
+++ b/library/stdarch/crates/stdarch-gen-hexagon/Cargo.toml
@@ -7,3 +7,4 @@ edition = "2021"
 
 [dependencies]
 regex = "1.10"
+stdarch-gen-common = { path = "../stdarch-gen-common" }
diff --git a/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs b/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs
index 7a1c3030c0042..c3ad153ab0a7a 100644
--- a/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs
+++ b/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs
@@ -21,6 +21,7 @@ use std::collections::{HashMap, HashSet};
 use std::fs::File;
 use std::io::Write;
 use std::path::Path;
+use stdarch_gen_common::{run_generator, Mode, GENERATED_MARKER};
 
 /// Mappings from HVX intrinsics to architecture-independent SIMD intrinsics.
 /// These intrinsics have equivalent semantics and can be lowered to the generic form.
@@ -1609,6 +1610,7 @@ fn generate_module_file(
     let mut output =
         File::create(output_path).map_err(|e| format!("Failed to create output: {}", e))?;
 
+    writeln!(output, "{}", GENERATED_MARKER).map_err(|e| e.to_string())?;
     writeln!(output, "{}", generate_module_doc(mode)).map_err(|e| e.to_string())?;
     writeln!(output, "{}", generate_types(mode)).map_err(|e| e.to_string())?;
     writeln!(output, "{}", generate_extern_block(intrinsics, mode)).map_err(|e| e.to_string())?;
@@ -1691,23 +1693,21 @@ fn main() -> Result<(), String> {
     }
 
     // Generate output files
-    let hexagon_dir = std::env::args()
-        .nth(1)
-        .map(std::path::PathBuf::from)
-        .unwrap_or_else(|| crate_dir.join("../core_arch/src/hexagon"));
-    std::fs::create_dir_all(&hexagon_dir).map_err(|e| e.to_string())?;
-
-    // Generate v64.rs (64-byte vector mode)
-    let v64_path = hexagon_dir.join("v64.rs");
-    println!("\nStep 3: Generating v64.rs (64-byte mode)...");
-    generate_module_file(&intrinsics, &v64_path, VectorMode::V64)?;
-    println!("  Output: {}", v64_path.display());
-
-    // Generate v128.rs (128-byte vector mode)
-    let v128_path = hexagon_dir.join("v128.rs");
-    println!("\nStep 4: Generating v128.rs (128-byte mode)...");
-    generate_module_file(&intrinsics, &v128_path, VectorMode::V128)?;
-    println!("  Output: {}", v128_path.display());
+    let hexagon_dir = crate_dir.join("../core_arch/src/hexagon");
+
+    // Either "check" to check the output versus the committed output, or "bless"
+    // to update the output.
+    let mode = Mode::from_env();
+    println!("\nStep 3: Generating v64.rs and v128.rs (mode: {mode:?})...");
+    run_generator(&hexagon_dir, mode, |out_dir| -> Result<(), String> {
+        for (filename, vmode) in [("v64.rs", VectorMode::V64), ("v128.rs", VectorMode::V128)] {
+            let path = out_dir.join(filename);
+            generate_module_file(&intrinsics, &path, vmode)?;
+            println!("  Output: {}", hexagon_dir.join(filename).display());
+        }
+        Ok(())
+    })
+    .map_err(|e| e.to_string())?;
 
     println!("\n=== Results ===");
     println!(
diff --git a/library/stdarch/crates/stdarch-gen-loongarch/Cargo.toml b/library/stdarch/crates/stdarch-gen-loongarch/Cargo.toml
index d3ac607c5576c..1a8c052ebe318 100644
--- a/library/stdarch/crates/stdarch-gen-loongarch/Cargo.toml
+++ b/library/stdarch/crates/stdarch-gen-loongarch/Cargo.toml
@@ -7,4 +7,4 @@ edition = "2024"
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [dependencies]
-rand = "0.8.5"
+rand = "0.9.3"
diff --git a/library/stdarch/examples/Cargo.toml b/library/stdarch/examples/Cargo.toml
index c4fc4c7e374c8..8752f206526c7 100644
--- a/library/stdarch/examples/Cargo.toml
+++ b/library/stdarch/examples/Cargo.toml
@@ -13,7 +13,7 @@ default-run = "hex"
 [dependencies]
 core_arch = { path = "../crates/core_arch" }
 quickcheck = "1.0"
-rand = "0.8"
+rand = "0.9.3"
 
 [[bin]]
 name = "hex"
diff --git a/library/stdarch/examples/connect5.rs b/library/stdarch/examples/connect5.rs
index f24657b148394..2df294b16b71e 100644
--- a/library/stdarch/examples/connect5.rs
+++ b/library/stdarch/examples/connect5.rs
@@ -33,8 +33,8 @@
 #![cfg_attr(target_arch = "x86_64", feature(stdarch_internal))]
 #![feature(stmt_expr_attributes)]
 
+use rand::rng;
 use rand::seq::SliceRandom;
-use rand::thread_rng;
 
 use std::cmp;
 use std::time::Instant;
@@ -374,7 +374,7 @@ impl List {
     }
 
     pub fn shuffle(&mut self) {
-        let mut rng = thread_rng();
+        let mut rng = rng();
         let num = self.p_size as usize;
 
         self.p_move[..num].shuffle(&mut rng);
diff --git a/library/stdarch/examples/hex.rs b/library/stdarch/examples/hex.rs
index 21827b375adaf..6417562074d9c 100644
--- a/library/stdarch/examples/hex.rs
+++ b/library/stdarch/examples/hex.rs
@@ -354,9 +354,9 @@ mod benches {
         len: usize,
         f: for<'a> unsafe fn(&[u8], &'a mut [u8]) -> Result<&'a str, usize>,
     ) {
-        let mut rng = rand::thread_rng();
+        let mut rng = rand::rng();
         let input = std::iter::repeat(())
-            .map(|()| rng.r#gen::<u8>())
+            .map(|()| rng.r#random::<u8>())
             .take(len)
             .collect::<Vec<_>>();
         let mut dst = vec![0; input.len() * 2];
diff --git a/library/stdarch/intrinsics_data/arm_intrinsics.json b/library/stdarch/intrinsics_data/arm_intrinsics.json
index fab6da7f2c16c..7f749fe4d8842 100644
--- a/library/stdarch/intrinsics_data/arm_intrinsics.json
+++ b/library/stdarch/intrinsics_data/arm_intrinsics.json
@@ -51174,6 +51174,12 @@
       "svfloat16x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svfloat16_t"
     },
@@ -51188,6 +51194,12 @@
       "svfloat32x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svfloat32_t"
     },
@@ -51202,6 +51214,12 @@
       "svfloat64x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svfloat64_t"
     },
@@ -51216,6 +51234,12 @@
       "svint16x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svint16_t"
     },
@@ -51230,6 +51254,12 @@
       "svint32x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svint32_t"
     },
@@ -51244,6 +51274,12 @@
       "svint64x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svint64_t"
     },
@@ -51258,6 +51294,12 @@
       "svint8x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svint8_t"
     },
@@ -51272,6 +51314,12 @@
       "svuint16x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svuint16_t"
     },
@@ -51286,6 +51334,12 @@
       "svuint32x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svuint32_t"
     },
@@ -51300,6 +51354,12 @@
       "svuint64x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svuint64_t"
     },
@@ -51314,6 +51374,12 @@
       "svuint8x2_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svuint8_t"
     },
@@ -51328,6 +51394,12 @@
       "svfloat16x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svfloat16_t"
     },
@@ -51342,6 +51414,12 @@
       "svfloat32x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svfloat32_t"
     },
@@ -51356,6 +51434,12 @@
       "svfloat64x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svfloat64_t"
     },
@@ -51370,6 +51454,12 @@
       "svint16x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svint16_t"
     },
@@ -51384,6 +51474,12 @@
       "svint32x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svint32_t"
     },
@@ -51398,6 +51494,12 @@
       "svint64x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svint64_t"
     },
@@ -51412,6 +51514,12 @@
       "svint8x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svint8_t"
     },
@@ -51426,6 +51534,12 @@
       "svuint16x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svuint16_t"
     },
@@ -51440,6 +51554,12 @@
       "svuint32x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svuint32_t"
     },
@@ -51454,6 +51574,12 @@
       "svuint64x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svuint64_t"
     },
@@ -51468,6 +51594,12 @@
       "svuint8x3_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svuint8_t"
     },
@@ -51482,6 +51614,12 @@
       "svfloat16x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svfloat16_t"
     },
@@ -51496,6 +51634,12 @@
       "svfloat32x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svfloat32_t"
     },
@@ -51510,6 +51654,12 @@
       "svfloat64x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svfloat64_t"
     },
@@ -51524,6 +51674,12 @@
       "svint16x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svint16_t"
     },
@@ -51538,6 +51694,12 @@
       "svint32x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svint32_t"
     },
@@ -51552,6 +51714,12 @@
       "svint64x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svint64_t"
     },
@@ -51566,6 +51734,12 @@
       "svint8x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svint8_t"
     },
@@ -51580,6 +51754,12 @@
       "svuint16x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svuint16_t"
     },
@@ -51594,6 +51774,12 @@
       "svuint32x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svuint32_t"
     },
@@ -51608,6 +51794,12 @@
       "svuint64x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svuint64_t"
     },
@@ -51622,6 +51814,12 @@
       "svuint8x4_t tuple",
       "uint64_t imm_index"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svuint8_t"
     },
@@ -162999,6 +163197,12 @@
       "uint64_t imm_index",
       "svfloat16_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svfloat16x2_t"
     },
@@ -163014,6 +163218,12 @@
       "uint64_t imm_index",
       "svfloat32_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svfloat32x2_t"
     },
@@ -163029,6 +163239,12 @@
       "uint64_t imm_index",
       "svfloat64_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svfloat64x2_t"
     },
@@ -163044,6 +163260,12 @@
       "uint64_t imm_index",
       "svint16_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svint16x2_t"
     },
@@ -163059,6 +163281,12 @@
       "uint64_t imm_index",
       "svint32_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svint32x2_t"
     },
@@ -163074,6 +163302,12 @@
       "uint64_t imm_index",
       "svint64_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svint64x2_t"
     },
@@ -163089,6 +163323,12 @@
       "uint64_t imm_index",
       "svint8_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svint8x2_t"
     },
@@ -163104,6 +163344,12 @@
       "uint64_t imm_index",
       "svuint16_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svuint16x2_t"
     },
@@ -163119,6 +163365,12 @@
       "uint64_t imm_index",
       "svuint32_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svuint32x2_t"
     },
@@ -163134,6 +163386,12 @@
       "uint64_t imm_index",
       "svuint64_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svuint64x2_t"
     },
@@ -163149,6 +163407,12 @@
       "uint64_t imm_index",
       "svuint8_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
     "return_type": {
       "value": "svuint8x2_t"
     },
@@ -163164,6 +163428,12 @@
       "uint64_t imm_index",
       "svfloat16_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svfloat16x3_t"
     },
@@ -163179,6 +163449,12 @@
       "uint64_t imm_index",
       "svfloat32_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svfloat32x3_t"
     },
@@ -163194,6 +163470,12 @@
       "uint64_t imm_index",
       "svfloat64_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svfloat64x3_t"
     },
@@ -163209,6 +163491,12 @@
       "uint64_t imm_index",
       "svint16_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svint16x3_t"
     },
@@ -163224,6 +163512,12 @@
       "uint64_t imm_index",
       "svint32_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svint32x3_t"
     },
@@ -163239,6 +163533,12 @@
       "uint64_t imm_index",
       "svint64_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svint64x3_t"
     },
@@ -163254,6 +163554,12 @@
       "uint64_t imm_index",
       "svint8_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svint8x3_t"
     },
@@ -163269,6 +163575,12 @@
       "uint64_t imm_index",
       "svuint16_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svuint16x3_t"
     },
@@ -163284,6 +163596,12 @@
       "uint64_t imm_index",
       "svuint32_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svuint32x3_t"
     },
@@ -163299,6 +163617,12 @@
       "uint64_t imm_index",
       "svuint64_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svuint64x3_t"
     },
@@ -163314,6 +163638,12 @@
       "uint64_t imm_index",
       "svuint8_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 2
+      }
+    },
     "return_type": {
       "value": "svuint8x3_t"
     },
@@ -163329,6 +163659,12 @@
       "uint64_t imm_index",
       "svfloat16_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svfloat16x4_t"
     },
@@ -163344,6 +163680,12 @@
       "uint64_t imm_index",
       "svfloat32_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svfloat32x4_t"
     },
@@ -163359,6 +163701,12 @@
       "uint64_t imm_index",
       "svfloat64_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svfloat64x4_t"
     },
@@ -163374,6 +163722,12 @@
       "uint64_t imm_index",
       "svint16_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svint16x4_t"
     },
@@ -163389,6 +163743,12 @@
       "uint64_t imm_index",
       "svint32_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svint32x4_t"
     },
@@ -163404,6 +163764,12 @@
       "uint64_t imm_index",
       "svint64_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svint64x4_t"
     },
@@ -163419,6 +163785,12 @@
       "uint64_t imm_index",
       "svint8_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svint8x4_t"
     },
@@ -163434,6 +163806,12 @@
       "uint64_t imm_index",
       "svuint16_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svuint16x4_t"
     },
@@ -163449,6 +163827,12 @@
       "uint64_t imm_index",
       "svuint32_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svuint32x4_t"
     },
@@ -163464,6 +163848,12 @@
       "uint64_t imm_index",
       "svuint64_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svuint64x4_t"
     },
@@ -163479,6 +163869,12 @@
       "uint64_t imm_index",
       "svuint8_t x"
     ],
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
     "return_type": {
       "value": "svuint8x4_t"
     },
diff --git a/library/stdarch/rust-version b/library/stdarch/rust-version
index 59e9e5a0e6ee9..e8cec4e0ee9c9 100644
--- a/library/stdarch/rust-version
+++ b/library/stdarch/rust-version
@@ -1 +1 @@
-045b17737dab5fcc28e4cbee0cfe2ce4ed363b32
+8e150217bafcaaaa0c45bf685c55fd56cec48598
diff --git a/src/tools/miri/src/shims/foreign_items.rs b/src/tools/miri/src/shims/foreign_items.rs
index e4daab7a2005d..5fd86769e96b5 100644
--- a/src/tools/miri/src/shims/foreign_items.rs
+++ b/src/tools/miri/src/shims/foreign_items.rs
@@ -789,7 +789,7 @@ trait EvalContextExtPriv<'tcx>: crate::MiriInterpCxExt<'tcx> {
             }
 
             // LLVM intrinsics
-            "llvm.prefetch" => {
+            "llvm.prefetch.p0" => {
                 let [p, rw, loc, ty] =
                     this.check_shim_sig_lenient(abi, CanonAbi::C, link_name, args)?;