From 4e1cf205fdaf597d04614de42417d50cf5cb7504 Mon Sep 17 00:00:00 2001 From: Wenjia Zhang Date: Wed, 22 Jul 2026 20:46:04 +0530 Subject: [PATCH 1/2] FROMLIST: qcom,inline-crypto-engine: Add x1e80100 support Document the compatible string for inline crypto engine found on the Qualcomm X1E80100 SoC, used by the Hamoa IoT EVK board. Link: https://lore.kernel.org/all/20260722-devtool-v2-1-03f6c82d84fe@oss.qualcomm.com/ Signed-off-by: Wenjia Zhang Signed-off-by: Abhinaba Rakshit --- .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index 7bfe8cfc346f6..6cf931d364ad3 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -23,6 +23,7 @@ properties: - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engine - qcom,sm8750-inline-crypto-engine + - qcom,x1e80100-inline-crypto-engine - const: qcom,inline-crypto-engine reg: From f6f19f25fd4f77d1e736bad37bf8845338f2c3f9 Mon Sep 17 00:00:00 2001 From: Wenjia Zhang Date: Wed, 22 Jul 2026 20:51:17 +0530 Subject: [PATCH 2/2] FROMLIST: hamoa: Add ICE node for UFS inline encryption Add the Inline Crypto Engine (ICE) device node to describe the hardware-accelerated inline encryption for UFS storage on the Hamoa IoT EVK board (Qualcomm X1E80100 SoC). Link: https://lore.kernel.org/all/20260722-devtool-v2-2-03f6c82d84fe@oss.qualcomm.com/ Signed-off-by: Wenjia Zhang Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 540e3f69d3093..0ba4a27506281 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3089,6 +3089,7 @@ }; }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; @@ -3932,6 +3933,8 @@ phys = <&ufs_mem_phy>; phy-names = "ufsphy"; + qcom,ice = <&ice>; + #reset-cells = <1>; status = "disabled"; @@ -3977,6 +3980,17 @@ }; }; + ice: crypto@1d88000 { + compatible = "qcom,x1e80100-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>;