Inquiry regarding iDMA 32b 3D Reference Design: Integration, Source Accessibility, and Testbench Availability

[SMVSKN]

Hi iDMA Team,
I am evaluating the iDMA IP for a project requiring a 4D DMA implementation with a reg_inst interface. Before proceeding with architectural changes, I am attempting to run basic simulations using the existing 32b 3D reference design located in target/rtl.
However, I have encountered the following blockers that are hindering my verification progress:
Source Code Accessibility: The design files are located in target/rtl, but are absent from src/rtl. Could you clarify how this reference design was generated and if the source RTL is intended to be available?
Missing Type Definitions: In idma_reg32_3d_reg_top.sv, I am unable to locate definitions for key structs such as reg_req_t and reg_rsp_t. Could you point me to the package or header file containing these definitions?
Testbench Availability: I have not been able to locate a top-level testbench for the 32b 3D design. Currently, I only see a backend-focused testbench. To validate the existing functionality before I begin implementing the 4D extensions, I require a comprehensive testbench that covers the frontend (reg interface), midend, and backend integration.
Could you please verify if the repository is fully up-to-date or if there is additional documentation/setup I might be missing? I want to ensure my verification environment is correctly aligned with the reference design before moving forward with the 4D integration.
Any guidance or pointers to the relevant testbench/source files would be greatly appreciated.
Best regards,
SMV

[DanielKellerM]

Hi @SMVSKN,

A few quick notes that should unblock you:

The generated RTL isn't committed on master. The .sv files under target/rtl/ are gitignored, and you produce them locally by running make idma_hw_all (needs bender, morty, and the Python deps from requirements.txt).

If you'd rather skip the generation flow entirely, CI pushes a snapshot branch for every commit on master with all the artifacts already built in. The latest one is __deploy__e618e4d__master, and it contains the full idma_reg32_3d_* set you're looking for.

On the missing types: reg_req_t and reg_rsp_t are not iDMA types. They come from the register_interface dependency and are meant to be typedef'd at the integration site using the macros from that package. So you won't find them inside iDMA itself, they're defined by whoever instantiates the IP.

On the testbench: there isn't a full frontend-to-backend integration TB inside this repo. We run per-layer tests (the backend ones cover the bulk of the regression surface), but full verification is done at the SoC level. A good reference for how the reg interface is wired up and exercised in a real system is the pulp_cluster repo, which integrates iDMA with the reg frontend you're targeting.

Hope this helps, happy to clarify anything.

[SMVSKN]

Thanks very much for your response!! It helps a lot.
The reg interface pointer you provided to the pulp cluster repository helps to a great extent. Will go over this and get back if there are further queries.
Thanks again.