diff --git a/docs/regs/hyperbus_cfg_regs.md b/docs/regs/hyperbus_cfg_regs.md
index 326f98d..9458acf 100644
--- a/docs/regs/hyperbus_cfg_regs.md
+++ b/docs/regs/hyperbus_cfg_regs.md
@@ -2,398 +2,1134 @@
Markdown description for SystemRDL register map.
Don't override. Generated from: hyperbus_cfg_regs
- - /home/phsauter/repos/hyperbus/src/regs/hyperbus_cfg_regs.rdl
+ - /home/phsauter/repos/hyperbus-peakrdl/src/regs/hyperbus_cfg_regs.rdl
-->
## hyperbus_cfg_regs address map
- Absolute Address: 0x0
- Base Offset: 0x0
-- Size: 0x78
-
-HyperBus controller configuration. Chip address ranges must be 4 MiB aligned, ordered by chip-select index, and non-overlapping.
-
-|Offset| Identifier |Name|
-|------|---------------------|----|
-| 0x00 | t_latency_access | — |
-| 0x04 |en_latency_additional| — |
-| 0x08 | t_burst_max | — |
-| 0x0C |t_read_write_recovery| — |
-| 0x10 | t_rx_clk_delay | — |
-| 0x14 | t_tx_clk_delay | — |
-| 0x18 | address_mask_msb | — |
-| 0x1C | address_space | — |
-| 0x20 | phys_in_use | — |
-| 0x24 | which_phy | — |
-| 0x28 | t_csh_cycles | — |
-| 0x2C | csn_to_ck_cycles | — |
-| 0x30 | chip0_base | — |
-| 0x34 | chip0_bound | — |
-| 0x38 | chip1_base | — |
-| 0x3C | chip1_bound | — |
-| 0x40 | chip2_base | — |
-| 0x44 | chip2_bound | — |
-| 0x48 | chip3_base | — |
-| 0x4C | chip3_bound | — |
-| 0x58 | chip4_base | — |
-| 0x5C | chip4_bound | — |
-| 0x60 | chip5_base | — |
-| 0x64 | chip5_bound | — |
-| 0x68 | chip6_base | — |
-| 0x6C | chip6_bound | — |
-| 0x70 | chip7_base | — |
-| 0x74 | chip7_bound | — |
-
-### t_latency_access register
+- Size: 0x1000
+
+HyperBus controller configuration register map. Enabled chip ranges must be 4 MiB aligned, ordered by chip-select index, and non-overlapping.
+
+|Offset| Identifier |Name|
+|------|------------|----|
+| 0x000| global_cfg | — |
+| 0x100| frontend | — |
+| 0x200| backend | — |
+| 0x300| phy_0 | — |
+| 0x340| phy_1 | — |
+| 0x400| chip_0 | — |
+| 0x440| chip_1 | — |
+| 0x480| chip_2 | — |
+| 0x4C0| chip_3 | — |
+| 0x500| chip_4 | — |
+| 0x540| chip_5 | — |
+| 0x580| chip_6 | — |
+| 0x5C0| chip_7 | — |
+| 0xFFC|reserved_top| — |
+
+## global_cfg register file
+
+- Absolute Address: 0x0
+- Base Offset: 0x0
+- Size: 0x14
+
+|Offset| Identifier |Name|
+|------|--------------|----|
+| 0x00 | ip_version | — |
+| 0x04 |reg_if_version| — |
+| 0x08 | capability | — |
+| 0x0C | command | — |
+| 0x10 | status | — |
+
+### ip_version register
- Absolute Address: 0x0
- Base Offset: 0x0
- Size: 0x4
-Initial latency cycles before read or write data.
+IP version (major.minor.patch.revision).
-|Bits|Identifier|Access|Reset|Name|
-|----|----------|------|-----|----|
-| 3:0| value | rw | 0x6 | — |
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+| 7:0 | revision | r | 0x0 | — |
+| 15:8| patch | r | 0x9 | — |
+|23:16| minor | r | 0x0 | — |
+|31:24| major | r | 0x0 | — |
-### en_latency_additional register
+### reg_if_version register
- Absolute Address: 0x4
- Base Offset: 0x4
- Size: 0x4
-Enable additional latency cycles when requested by RWDS.
+Register interface version.
-|Bits|Identifier|Access|Reset|Name|
-|----|----------|------|-----|----|
-| 0 | value | rw | 0x0 | — |
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+| 15:0| minor | r | 0x0 | — |
+|31:16| major | r | 0x1 | — |
-### t_burst_max register
+### capability register
- Absolute Address: 0x8
- Base Offset: 0x8
- Size: 0x4
-Maximum continuous burst length before the PHY restarts a transfer.
+Hardware-provided implementation capabilities.
-|Bits|Identifier|Access|Reset|Name|
-|----|----------|------|-----|----|
-|15:0| value | rw |0x15E| — |
+|Bits| Identifier |Access|Reset|Name|
+|----|------------------|------|-----|----|
+| 7:0| num_chips | r | 0x0 | — |
+|15:8| num_phys | r | 0x0 | — |
+| 16 | per_chip_cfg | r | 0x0 | — |
+| 17 | per_phy_cfg | r | 0x0 | — |
+| 18 | chip_enable | r | 0x0 | — |
+| 19 | clock_divider | r | 0x0 | — |
+| 20 | staged_apply | r | 0x0 | — |
+| 21 | error_status | r | 0x0 | — |
+| 22 |rwds_sample_timing| r | 0x0 | — |
+| 23 | rwds_oe_timing | r | 0x0 | — |
+
+#### num_chips field
+
+Number of implemented chip selects.
+
+#### num_phys field
+
+Number of implemented PHY lanes.
+
+#### per_chip_cfg field
+
+Each chip record controls its corresponding chip rather than chip 0 being shared.
+
+#### per_phy_cfg field
+
+Each PHY record controls its corresponding lane rather than PHY 0 being shared.
-### t_read_write_recovery register
+#### chip_enable field
+
+Per-chip enable bits participate in address decoding.
+
+#### clock_divider field
+
+CLOCK_CFG controls an implemented backend clock divider.
+
+#### staged_apply field
+
+FLUSH and APPLY commands implement a staged configuration barrier.
+
+#### error_status field
+
+STATUS reports sticky controller errors.
+
+#### rwds_sample_timing field
+
+Per-chip RWDS sample timing is implemented.
+
+#### rwds_oe_timing field
+
+Per-PHY RWDS output-enable timing is implemented.
+
+### command register
- Absolute Address: 0xC
- Base Offset: 0xC
- Size: 0x4
-Recovery cycles inserted between read and write phases.
+Single-cycle write-one command strobes, active when capability.staged_apply is set; otherwise writes are retained only as inert pulses.
|Bits|Identifier|Access|Reset|Name|
|----|----------|------|-----|----|
-| 3:0| value | rw | 0x6 | — |
+| 0 | flush | rw | 0x0 | — |
+| 1 | apply | rw | 0x0 | — |
-### t_rx_clk_delay register
+### status register
- Absolute Address: 0x10
- Base Offset: 0x10
- Size: 0x4
-RX sampling delay with fine taps in bits 4:0 and coarse taps in bits 7:5.
+Controller status.
-|Bits|Identifier|Access|Reset|Name|
-|----|----------|------|-----|----|
-| 4:0| fine | rw | 0x10| — |
-| 7:5| coarse | rw | 0x0 | — |
-
-#### fine field
+|Bits| Identifier | Access |Reset|Name|
+|----|------------|---------|-----|----|
+| 0 |decode_error|rw, woclr| 0x0 | — |
+| 1 | busy | r | 0x0 | — |
+| 2 | dirty | r | 0x0 | — |
-Fine delay-line tap setting, nominally about 78 ps per tap.
+## frontend register file
-#### coarse field
+- Absolute Address: 0x100
+- Base Offset: 0x100
+- Size: 0x4
-Coarse delay-line tap setting with an implementation-defined step size.
+|Offset| Identifier |Name|
+|------|------------|----|
+| 0x0 |frontend_cfg| — |
-### t_tx_clk_delay register
+### frontend_cfg register
-- Absolute Address: 0x14
-- Base Offset: 0x14
+- Absolute Address: 0x100
+- Base Offset: 0x0
- Size: 0x4
-TX clock delay with fine taps in bits 4:0 and coarse taps in bits 7:5.
+Frontend configuration. dual_phy must be 0 or 1.
|Bits|Identifier|Access|Reset|Name|
|----|----------|------|-----|----|
-| 4:0| fine | rw | 0x10| — |
-| 7:5| coarse | rw | 0x0 | — |
+| 0 | dual_phy | rw | 0x1 | — |
-#### fine field
+## backend register file
-Fine delay-line tap setting, nominally about 78 ps per tap.
-
-#### coarse field
+- Absolute Address: 0x200
+- Base Offset: 0x200
+- Size: 0x4
-Coarse delay-line tap setting with an implementation-defined step size.
+|Offset|Identifier|Name|
+|------|----------|----|
+| 0x0 | clock_cfg| — |
-### address_mask_msb register
+### clock_cfg register
-- Absolute Address: 0x18
-- Base Offset: 0x18
+- Absolute Address: 0x200
+- Base Offset: 0x0
- Size: 0x4
-Most-significant address bit used by frontend address packing.
+Backend clock-divider configuration, active when capability.clock_divider is set; divider values must be at least 2.
|Bits|Identifier|Access|Reset|Name|
|----|----------|------|-----|----|
-| 4:0| value | rw | 0x19| — |
+| 7:0| divider | rw | 0x8 | — |
-### address_space register
+## phy_0 register file
-- Absolute Address: 0x1C
-- Base Offset: 0x1C
-- Size: 0x4
+- Absolute Address: 0x300
+- Base Offset: 0x300
+- Size: 0x8
-Select HyperRAM or HyperFlash address-space interpretation.
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x0 | tx_delay | — |
+| 0x4 |rwds_timing| — |
-|Bits|Identifier|Access|Reset|Name|
-|----|----------|------|-----|----|
-| 0 | value | rw | 0x0 | — |
-
-### phys_in_use register
+### tx_delay register
-- Absolute Address: 0x20
-- Base Offset: 0x20
+- Absolute Address: 0x300
+- Base Offset: 0x0
- Size: 0x4
-Select whether one or both PHY lanes are active.
+PHY transmit delay. PHY 0 is shared when capability.per_phy_cfg is clear.
|Bits|Identifier|Access|Reset|Name|
|----|----------|------|-----|----|
-| 0 | value | rw | 0x1 | — |
+| 7:0| value | rw | 0x10| — |
-### which_phy register
+### rwds_timing register
-- Absolute Address: 0x24
-- Base Offset: 0x24
+- Absolute Address: 0x304
+- Base Offset: 0x4
- Size: 0x4
-Select the PHY lane used when only one PHY is active.
+PHY RWDS output-enable timing. rwds_oe_setup_cycles must be at most 15 and is active when capability.rwds_oe_timing is set.
-|Bits|Identifier|Access|Reset|Name|
-|----|----------|------|-----|----|
-| 0 | value | rw | 0x1 | — |
+|Bits| Identifier |Access|Reset|Name|
+|----|--------------------|------|-----|----|
+| 7:0|rwds_oe_setup_cycles| rw | 0x1 | — |
+
+## phy_1 register file
+
+- Absolute Address: 0x340
+- Base Offset: 0x340
+- Size: 0x8
-### t_csh_cycles register
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x0 | tx_delay | — |
+| 0x4 |rwds_timing| — |
-- Absolute Address: 0x28
-- Base Offset: 0x28
+### tx_delay register
+
+- Absolute Address: 0x340
+- Base Offset: 0x0
- Size: 0x4
-Chip-select high time between transfers.
+PHY transmit delay. PHY 0 is shared when capability.per_phy_cfg is clear.
|Bits|Identifier|Access|Reset|Name|
|----|----------|------|-----|----|
-| 3:0| value | rw | 0x1 | — |
+| 7:0| value | rw | 0x10| — |
-### csn_to_ck_cycles register
+### rwds_timing register
-- Absolute Address: 0x2C
-- Base Offset: 0x2C
+- Absolute Address: 0x344
+- Base Offset: 0x4
- Size: 0x4
-Delay cycles from chip-select assertion to clock start.
+PHY RWDS output-enable timing. rwds_oe_setup_cycles must be at most 15 and is active when capability.rwds_oe_timing is set.
-|Bits|Identifier|Access|Reset|Name|
-|----|----------|------|-----|----|
-| 3:0| value | rw | 0x0 | — |
+|Bits| Identifier |Access|Reset|Name|
+|----|--------------------|------|-----|----|
+| 7:0|rwds_oe_setup_cycles| rw | 0x1 | — |
+
+## chip_0 register file
-### chip0_base register
+- Absolute Address: 0x400
+- Base Offset: 0x400
+- Size: 0x1C
-- Absolute Address: 0x30
-- Base Offset: 0x30
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x400
+- Base Offset: 0x0
- Size: 0x4
-Inclusive 4 MiB-aligned address for chip-select 0 decoding.
+Inclusive 4 MiB-aligned chip address range base.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x0 | — |
-### chip0_bound register
+### range_bound register
-- Absolute Address: 0x34
-- Base Offset: 0x34
+- Absolute Address: 0x404
+- Base Offset: 0x4
- Size: 0x4
-Exclusive 4 MiB-aligned address for chip-select 0 decoding.
+Exclusive 4 MiB-aligned chip address range bound.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x1 | — |
-### chip1_base register
+### address_cfg register
+
+- Absolute Address: 0x408
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x40C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x410
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x414
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x418
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_1 register file
-- Absolute Address: 0x38
-- Base Offset: 0x38
+- Absolute Address: 0x440
+- Base Offset: 0x440
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x440
+- Base Offset: 0x0
- Size: 0x4
-Inclusive 4 MiB-aligned address for chip-select 1 decoding.
+Inclusive 4 MiB-aligned chip address range base.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x1 | — |
-### chip1_bound register
+### range_bound register
-- Absolute Address: 0x3C
-- Base Offset: 0x3C
+- Absolute Address: 0x444
+- Base Offset: 0x4
- Size: 0x4
-Exclusive 4 MiB-aligned address for chip-select 1 decoding.
+Exclusive 4 MiB-aligned chip address range bound.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x2 | — |
-### chip2_base register
+### address_cfg register
+
+- Absolute Address: 0x448
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x44C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
-- Absolute Address: 0x40
-- Base Offset: 0x40
+- Absolute Address: 0x450
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x454
+- Base Offset: 0x14
- Size: 0x4
-Inclusive 4 MiB-aligned address for chip-select 2 decoding.
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x458
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_2 register file
+
+- Absolute Address: 0x480
+- Base Offset: 0x480
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x480
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x2 | — |
-### chip2_bound register
+### range_bound register
-- Absolute Address: 0x44
-- Base Offset: 0x44
+- Absolute Address: 0x484
+- Base Offset: 0x4
- Size: 0x4
-Exclusive 4 MiB-aligned address for chip-select 2 decoding.
+Exclusive 4 MiB-aligned chip address range bound.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x3 | — |
-### chip3_base register
+### address_cfg register
+
+- Absolute Address: 0x488
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
-- Absolute Address: 0x48
-- Base Offset: 0x48
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x48C
+- Base Offset: 0xC
- Size: 0x4
-Inclusive 4 MiB-aligned address for chip-select 3 decoding.
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x490
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x494
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x498
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_3 register file
+
+- Absolute Address: 0x4C0
+- Base Offset: 0x4C0
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x4C0
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x3 | — |
-### chip3_bound register
+### range_bound register
-- Absolute Address: 0x4C
-- Base Offset: 0x4C
+- Absolute Address: 0x4C4
+- Base Offset: 0x4
- Size: 0x4
-Exclusive 4 MiB-aligned address for chip-select 3 decoding.
+Exclusive 4 MiB-aligned chip address range bound.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x4 | — |
-### chip4_base register
+### address_cfg register
-- Absolute Address: 0x58
-- Base Offset: 0x58
+- Absolute Address: 0x4C8
+- Base Offset: 0x8
- Size: 0x4
-Inclusive 4 MiB-aligned address for chip-select 4 decoding.
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x4CC
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x4D0
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x4D4
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x4D8
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_4 register file
+
+- Absolute Address: 0x500
+- Base Offset: 0x500
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x500
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x4 | — |
-### chip4_bound register
+### range_bound register
-- Absolute Address: 0x5C
-- Base Offset: 0x5C
+- Absolute Address: 0x504
+- Base Offset: 0x4
- Size: 0x4
-Exclusive 4 MiB-aligned address for chip-select 4 decoding.
+Exclusive 4 MiB-aligned chip address range bound.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x5 | — |
-### chip5_base register
+### address_cfg register
-- Absolute Address: 0x60
-- Base Offset: 0x60
+- Absolute Address: 0x508
+- Base Offset: 0x8
- Size: 0x4
-Inclusive 4 MiB-aligned address for chip-select 5 decoding.
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x50C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x510
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x514
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x518
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_5 register file
+
+- Absolute Address: 0x540
+- Base Offset: 0x540
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x540
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x5 | — |
-### chip5_bound register
+### range_bound register
-- Absolute Address: 0x64
-- Base Offset: 0x64
+- Absolute Address: 0x544
+- Base Offset: 0x4
- Size: 0x4
-Exclusive 4 MiB-aligned address for chip-select 5 decoding.
+Exclusive 4 MiB-aligned chip address range bound.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x6 | — |
-### chip6_base register
+### address_cfg register
-- Absolute Address: 0x68
-- Base Offset: 0x68
+- Absolute Address: 0x548
+- Base Offset: 0x8
- Size: 0x4
-Inclusive 4 MiB-aligned address for chip-select 6 decoding.
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x54C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x550
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x554
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x558
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_6 register file
+
+- Absolute Address: 0x580
+- Base Offset: 0x580
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x580
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x6 | — |
-### chip6_bound register
+### range_bound register
-- Absolute Address: 0x6C
-- Base Offset: 0x6C
+- Absolute Address: 0x584
+- Base Offset: 0x4
- Size: 0x4
-Exclusive 4 MiB-aligned address for chip-select 6 decoding.
+Exclusive 4 MiB-aligned chip address range bound.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x7 | — |
-### chip7_base register
+### address_cfg register
+
+- Absolute Address: 0x588
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x58C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x590
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x594
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x598
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_7 register file
+
+- Absolute Address: 0x5C0
+- Base Offset: 0x5C0
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
-- Absolute Address: 0x70
-- Base Offset: 0x70
+### range_base register
+
+- Absolute Address: 0x5C0
+- Base Offset: 0x0
- Size: 0x4
-Inclusive 4 MiB-aligned address for chip-select 7 decoding.
+Inclusive 4 MiB-aligned chip address range base.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x7 | — |
-### chip7_bound register
+### range_bound register
-- Absolute Address: 0x74
-- Base Offset: 0x74
+- Absolute Address: 0x5C4
+- Base Offset: 0x4
- Size: 0x4
-Exclusive 4 MiB-aligned address for chip-select 7 decoding.
+Exclusive 4 MiB-aligned chip address range bound.
| Bits|Identifier|Access|Reset|Name|
|-----|----------|------|-----|----|
|31:22| value | rw | 0x8 | — |
+
+### address_cfg register
+
+- Absolute Address: 0x5C8
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x5CC
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x5D0
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x5D4
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x5D8
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+### reserved_top register
+
+- Absolute Address: 0xFFC
+- Base Offset: 0xFFC
+- Size: 0x4
+
+Reserved endpoint that fixes the register window size to 4 KiB.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0| value | r | 0x0 | — |
diff --git a/include/hyperbus_cfg_regs.h b/include/hyperbus_cfg_regs.h
index a5a09ba..25b7b58 100644
--- a/include/hyperbus_cfg_regs.h
+++ b/include/hyperbus_cfg_regs.h
@@ -10,217 +10,426 @@ extern "C" {
#include
#include
-// reg - hyperbus_cfg_regs::t_latency_access
-#define HYPERBUS_CFG_REGS__T_LATENCY_ACCESS__VALUE_bm 0xf
-#define HYPERBUS_CFG_REGS__T_LATENCY_ACCESS__VALUE_bp 0
-#define HYPERBUS_CFG_REGS__T_LATENCY_ACCESS__VALUE_bw 4
-#define HYPERBUS_CFG_REGS__T_LATENCY_ACCESS__VALUE_reset 0x6
-
-// reg - hyperbus_cfg_regs::en_latency_additional
-#define HYPERBUS_CFG_REGS__EN_LATENCY_ADDITIONAL__VALUE_bm 0x1
-#define HYPERBUS_CFG_REGS__EN_LATENCY_ADDITIONAL__VALUE_bp 0
-#define HYPERBUS_CFG_REGS__EN_LATENCY_ADDITIONAL__VALUE_bw 1
-#define HYPERBUS_CFG_REGS__EN_LATENCY_ADDITIONAL__VALUE_reset 0x0
-
-// reg - hyperbus_cfg_regs::t_burst_max
-#define HYPERBUS_CFG_REGS__T_BURST_MAX__VALUE_bm 0xffff
-#define HYPERBUS_CFG_REGS__T_BURST_MAX__VALUE_bp 0
-#define HYPERBUS_CFG_REGS__T_BURST_MAX__VALUE_bw 16
-#define HYPERBUS_CFG_REGS__T_BURST_MAX__VALUE_reset 0x15e
-
-// reg - hyperbus_cfg_regs::t_read_write_recovery
-#define HYPERBUS_CFG_REGS__T_READ_WRITE_RECOVERY__VALUE_bm 0xf
-#define HYPERBUS_CFG_REGS__T_READ_WRITE_RECOVERY__VALUE_bp 0
-#define HYPERBUS_CFG_REGS__T_READ_WRITE_RECOVERY__VALUE_bw 4
-#define HYPERBUS_CFG_REGS__T_READ_WRITE_RECOVERY__VALUE_reset 0x6
-
-// reg - hyperbus_cfg_regs::t_rx_clk_delay
-#define HYPERBUS_CFG_REGS__T_RX_CLK_DELAY__FINE_bm 0x1f
-#define HYPERBUS_CFG_REGS__T_RX_CLK_DELAY__FINE_bp 0
-#define HYPERBUS_CFG_REGS__T_RX_CLK_DELAY__FINE_bw 5
-#define HYPERBUS_CFG_REGS__T_RX_CLK_DELAY__FINE_reset 0x10
-#define HYPERBUS_CFG_REGS__T_RX_CLK_DELAY__COARSE_bm 0xe0
-#define HYPERBUS_CFG_REGS__T_RX_CLK_DELAY__COARSE_bp 5
-#define HYPERBUS_CFG_REGS__T_RX_CLK_DELAY__COARSE_bw 3
-#define HYPERBUS_CFG_REGS__T_RX_CLK_DELAY__COARSE_reset 0x0
-
-// reg - hyperbus_cfg_regs::t_tx_clk_delay
-#define HYPERBUS_CFG_REGS__T_TX_CLK_DELAY__FINE_bm 0x1f
-#define HYPERBUS_CFG_REGS__T_TX_CLK_DELAY__FINE_bp 0
-#define HYPERBUS_CFG_REGS__T_TX_CLK_DELAY__FINE_bw 5
-#define HYPERBUS_CFG_REGS__T_TX_CLK_DELAY__FINE_reset 0x10
-#define HYPERBUS_CFG_REGS__T_TX_CLK_DELAY__COARSE_bm 0xe0
-#define HYPERBUS_CFG_REGS__T_TX_CLK_DELAY__COARSE_bp 5
-#define HYPERBUS_CFG_REGS__T_TX_CLK_DELAY__COARSE_bw 3
-#define HYPERBUS_CFG_REGS__T_TX_CLK_DELAY__COARSE_reset 0x0
-
-// reg - hyperbus_cfg_regs::address_mask_msb
-#define HYPERBUS_CFG_REGS__ADDRESS_MASK_MSB__VALUE_bm 0x1f
-#define HYPERBUS_CFG_REGS__ADDRESS_MASK_MSB__VALUE_bp 0
-#define HYPERBUS_CFG_REGS__ADDRESS_MASK_MSB__VALUE_bw 5
-#define HYPERBUS_CFG_REGS__ADDRESS_MASK_MSB__VALUE_reset 0x19
-
-// reg - hyperbus_cfg_regs::address_space
-#define HYPERBUS_CFG_REGS__ADDRESS_SPACE__VALUE_bm 0x1
-#define HYPERBUS_CFG_REGS__ADDRESS_SPACE__VALUE_bp 0
-#define HYPERBUS_CFG_REGS__ADDRESS_SPACE__VALUE_bw 1
-#define HYPERBUS_CFG_REGS__ADDRESS_SPACE__VALUE_reset 0x0
-
-// reg - hyperbus_cfg_regs::phys_in_use
-#define HYPERBUS_CFG_REGS__PHYS_IN_USE__VALUE_bm 0x1
-#define HYPERBUS_CFG_REGS__PHYS_IN_USE__VALUE_bp 0
-#define HYPERBUS_CFG_REGS__PHYS_IN_USE__VALUE_bw 1
-#define HYPERBUS_CFG_REGS__PHYS_IN_USE__VALUE_reset 0x1
-
-// reg - hyperbus_cfg_regs::which_phy
-#define HYPERBUS_CFG_REGS__WHICH_PHY__VALUE_bm 0x1
-#define HYPERBUS_CFG_REGS__WHICH_PHY__VALUE_bp 0
-#define HYPERBUS_CFG_REGS__WHICH_PHY__VALUE_bw 1
-#define HYPERBUS_CFG_REGS__WHICH_PHY__VALUE_reset 0x1
-
-// reg - hyperbus_cfg_regs::t_csh_cycles
-#define HYPERBUS_CFG_REGS__T_CSH_CYCLES__VALUE_bm 0xf
-#define HYPERBUS_CFG_REGS__T_CSH_CYCLES__VALUE_bp 0
-#define HYPERBUS_CFG_REGS__T_CSH_CYCLES__VALUE_bw 4
-#define HYPERBUS_CFG_REGS__T_CSH_CYCLES__VALUE_reset 0x1
-
-// reg - hyperbus_cfg_regs::csn_to_ck_cycles
-#define HYPERBUS_CFG_REGS__CSN_TO_CK_CYCLES__VALUE_bm 0xf
-#define HYPERBUS_CFG_REGS__CSN_TO_CK_CYCLES__VALUE_bp 0
-#define HYPERBUS_CFG_REGS__CSN_TO_CK_CYCLES__VALUE_bw 4
-#define HYPERBUS_CFG_REGS__CSN_TO_CK_CYCLES__VALUE_reset 0x0
-
-// reg - hyperbus_cfg_regs::chip0_base
-#define HYPERBUS_CFG_REGS__CHIP0_BASE__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP0_BASE__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP0_BASE__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP0_BASE__VALUE_reset 0x0
-
-// reg - hyperbus_cfg_regs::chip0_bound
-#define HYPERBUS_CFG_REGS__CHIP0_BOUND__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP0_BOUND__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP0_BOUND__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP0_BOUND__VALUE_reset 0x1
-
-// reg - hyperbus_cfg_regs::chip1_base
-#define HYPERBUS_CFG_REGS__CHIP1_BASE__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP1_BASE__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP1_BASE__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP1_BASE__VALUE_reset 0x1
-
-// reg - hyperbus_cfg_regs::chip1_bound
-#define HYPERBUS_CFG_REGS__CHIP1_BOUND__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP1_BOUND__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP1_BOUND__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP1_BOUND__VALUE_reset 0x2
-
-// reg - hyperbus_cfg_regs::chip2_base
-#define HYPERBUS_CFG_REGS__CHIP2_BASE__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP2_BASE__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP2_BASE__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP2_BASE__VALUE_reset 0x2
-
-// reg - hyperbus_cfg_regs::chip2_bound
-#define HYPERBUS_CFG_REGS__CHIP2_BOUND__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP2_BOUND__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP2_BOUND__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP2_BOUND__VALUE_reset 0x3
-
-// reg - hyperbus_cfg_regs::chip3_base
-#define HYPERBUS_CFG_REGS__CHIP3_BASE__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP3_BASE__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP3_BASE__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP3_BASE__VALUE_reset 0x3
-
-// reg - hyperbus_cfg_regs::chip3_bound
-#define HYPERBUS_CFG_REGS__CHIP3_BOUND__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP3_BOUND__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP3_BOUND__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP3_BOUND__VALUE_reset 0x4
-
-// reg - hyperbus_cfg_regs::chip4_base
-#define HYPERBUS_CFG_REGS__CHIP4_BASE__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP4_BASE__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP4_BASE__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP4_BASE__VALUE_reset 0x4
-
-// reg - hyperbus_cfg_regs::chip4_bound
-#define HYPERBUS_CFG_REGS__CHIP4_BOUND__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP4_BOUND__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP4_BOUND__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP4_BOUND__VALUE_reset 0x5
-
-// reg - hyperbus_cfg_regs::chip5_base
-#define HYPERBUS_CFG_REGS__CHIP5_BASE__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP5_BASE__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP5_BASE__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP5_BASE__VALUE_reset 0x5
-
-// reg - hyperbus_cfg_regs::chip5_bound
-#define HYPERBUS_CFG_REGS__CHIP5_BOUND__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP5_BOUND__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP5_BOUND__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP5_BOUND__VALUE_reset 0x6
-
-// reg - hyperbus_cfg_regs::chip6_base
-#define HYPERBUS_CFG_REGS__CHIP6_BASE__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP6_BASE__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP6_BASE__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP6_BASE__VALUE_reset 0x6
-
-// reg - hyperbus_cfg_regs::chip6_bound
-#define HYPERBUS_CFG_REGS__CHIP6_BOUND__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP6_BOUND__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP6_BOUND__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP6_BOUND__VALUE_reset 0x7
-
-// reg - hyperbus_cfg_regs::chip7_base
-#define HYPERBUS_CFG_REGS__CHIP7_BASE__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP7_BASE__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP7_BASE__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP7_BASE__VALUE_reset 0x7
-
-// reg - hyperbus_cfg_regs::chip7_bound
-#define HYPERBUS_CFG_REGS__CHIP7_BOUND__VALUE_bm 0xffc00000
-#define HYPERBUS_CFG_REGS__CHIP7_BOUND__VALUE_bp 22
-#define HYPERBUS_CFG_REGS__CHIP7_BOUND__VALUE_bw 10
-#define HYPERBUS_CFG_REGS__CHIP7_BOUND__VALUE_reset 0x8
+// reg - hyperbus_cfg_regs::ip_version
+#define HYPERBUS_CFG_REGS__IP_VERSION__REVISION_bm 0xff
+#define HYPERBUS_CFG_REGS__IP_VERSION__REVISION_bp 0
+#define HYPERBUS_CFG_REGS__IP_VERSION__REVISION_bw 8
+#define HYPERBUS_CFG_REGS__IP_VERSION__REVISION_reset 0x0
+#define HYPERBUS_CFG_REGS__IP_VERSION__PATCH_bm 0xff00
+#define HYPERBUS_CFG_REGS__IP_VERSION__PATCH_bp 8
+#define HYPERBUS_CFG_REGS__IP_VERSION__PATCH_bw 8
+#define HYPERBUS_CFG_REGS__IP_VERSION__PATCH_reset 0x9
+#define HYPERBUS_CFG_REGS__IP_VERSION__MINOR_bm 0xff0000
+#define HYPERBUS_CFG_REGS__IP_VERSION__MINOR_bp 16
+#define HYPERBUS_CFG_REGS__IP_VERSION__MINOR_bw 8
+#define HYPERBUS_CFG_REGS__IP_VERSION__MINOR_reset 0x0
+#define HYPERBUS_CFG_REGS__IP_VERSION__MAJOR_bm 0xff000000
+#define HYPERBUS_CFG_REGS__IP_VERSION__MAJOR_bp 24
+#define HYPERBUS_CFG_REGS__IP_VERSION__MAJOR_bw 8
+#define HYPERBUS_CFG_REGS__IP_VERSION__MAJOR_reset 0x0
+
+// reg - hyperbus_cfg_regs::reg_if_version
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MINOR_bm 0xffff
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MINOR_bp 0
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MINOR_bw 16
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MINOR_reset 0x0
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MAJOR_bm 0xffff0000
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MAJOR_bp 16
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MAJOR_bw 16
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MAJOR_reset 0x1
+
+// reg - hyperbus_cfg_regs::capability
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_CHIPS_bm 0xff
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_CHIPS_bp 0
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_CHIPS_bw 8
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_CHIPS_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_PHYS_bm 0xff00
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_PHYS_bp 8
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_PHYS_bw 8
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_PHYS_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_CHIP_CFG_bm 0x10000
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_CHIP_CFG_bp 16
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_CHIP_CFG_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_CHIP_CFG_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_PHY_CFG_bm 0x20000
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_PHY_CFG_bp 17
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_PHY_CFG_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_PHY_CFG_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__CHIP_ENABLE_bm 0x40000
+#define HYPERBUS_CFG_REGS__CAPABILITY__CHIP_ENABLE_bp 18
+#define HYPERBUS_CFG_REGS__CAPABILITY__CHIP_ENABLE_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__CHIP_ENABLE_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__CLOCK_DIVIDER_bm 0x80000
+#define HYPERBUS_CFG_REGS__CAPABILITY__CLOCK_DIVIDER_bp 19
+#define HYPERBUS_CFG_REGS__CAPABILITY__CLOCK_DIVIDER_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__CLOCK_DIVIDER_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__STAGED_APPLY_bm 0x100000
+#define HYPERBUS_CFG_REGS__CAPABILITY__STAGED_APPLY_bp 20
+#define HYPERBUS_CFG_REGS__CAPABILITY__STAGED_APPLY_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__STAGED_APPLY_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__ERROR_STATUS_bm 0x200000
+#define HYPERBUS_CFG_REGS__CAPABILITY__ERROR_STATUS_bp 21
+#define HYPERBUS_CFG_REGS__CAPABILITY__ERROR_STATUS_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__ERROR_STATUS_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_SAMPLE_TIMING_bm 0x400000
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_SAMPLE_TIMING_bp 22
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_SAMPLE_TIMING_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_SAMPLE_TIMING_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_OE_TIMING_bm 0x800000
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_OE_TIMING_bp 23
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_OE_TIMING_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_OE_TIMING_reset 0x0
+
+// reg - hyperbus_cfg_regs::command
+#define HYPERBUS_CFG_REGS__COMMAND__FLUSH_bm 0x1
+#define HYPERBUS_CFG_REGS__COMMAND__FLUSH_bp 0
+#define HYPERBUS_CFG_REGS__COMMAND__FLUSH_bw 1
+#define HYPERBUS_CFG_REGS__COMMAND__FLUSH_reset 0x0
+#define HYPERBUS_CFG_REGS__COMMAND__APPLY_bm 0x2
+#define HYPERBUS_CFG_REGS__COMMAND__APPLY_bp 1
+#define HYPERBUS_CFG_REGS__COMMAND__APPLY_bw 1
+#define HYPERBUS_CFG_REGS__COMMAND__APPLY_reset 0x0
+
+// reg - hyperbus_cfg_regs::status
+#define HYPERBUS_CFG_REGS__STATUS__DECODE_ERROR_bm 0x1
+#define HYPERBUS_CFG_REGS__STATUS__DECODE_ERROR_bp 0
+#define HYPERBUS_CFG_REGS__STATUS__DECODE_ERROR_bw 1
+#define HYPERBUS_CFG_REGS__STATUS__DECODE_ERROR_reset 0x0
+#define HYPERBUS_CFG_REGS__STATUS__BUSY_bm 0x2
+#define HYPERBUS_CFG_REGS__STATUS__BUSY_bp 1
+#define HYPERBUS_CFG_REGS__STATUS__BUSY_bw 1
+#define HYPERBUS_CFG_REGS__STATUS__BUSY_reset 0x0
+#define HYPERBUS_CFG_REGS__STATUS__DIRTY_bm 0x4
+#define HYPERBUS_CFG_REGS__STATUS__DIRTY_bp 2
+#define HYPERBUS_CFG_REGS__STATUS__DIRTY_bw 1
+#define HYPERBUS_CFG_REGS__STATUS__DIRTY_reset 0x0
+
+// regfile - hyperbus_cfg_regs::global_regs
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t ip_version;
+ uint32_t reg_if_version;
+ uint32_t capability;
+ uint32_t command;
+ uint32_t status;
+} hyperbus_cfg_regs__global_regs_t;
+
+// reg - hyperbus_cfg_regs::frontend_cfg
+#define HYPERBUS_CFG_REGS__FRONTEND_CFG__DUAL_PHY_bm 0x1
+#define HYPERBUS_CFG_REGS__FRONTEND_CFG__DUAL_PHY_bp 0
+#define HYPERBUS_CFG_REGS__FRONTEND_CFG__DUAL_PHY_bw 1
+#define HYPERBUS_CFG_REGS__FRONTEND_CFG__DUAL_PHY_reset 0x1
+
+// regfile - hyperbus_cfg_regs::frontend_regs
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t frontend_cfg;
+} hyperbus_cfg_regs__frontend_regs_t;
+
+// reg - hyperbus_cfg_regs::clock_cfg
+#define HYPERBUS_CFG_REGS__CLOCK_CFG__DIVIDER_bm 0xff
+#define HYPERBUS_CFG_REGS__CLOCK_CFG__DIVIDER_bp 0
+#define HYPERBUS_CFG_REGS__CLOCK_CFG__DIVIDER_bw 8
+#define HYPERBUS_CFG_REGS__CLOCK_CFG__DIVIDER_reset 0x8
+
+// regfile - hyperbus_cfg_regs::backend_regs
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t clock_cfg;
+} hyperbus_cfg_regs__backend_regs_t;
+
+// reg - hyperbus_cfg_regs::tx_delay
+#define HYPERBUS_CFG_REGS__TX_DELAY__VALUE_bm 0xff
+#define HYPERBUS_CFG_REGS__TX_DELAY__VALUE_bp 0
+#define HYPERBUS_CFG_REGS__TX_DELAY__VALUE_bw 8
+#define HYPERBUS_CFG_REGS__TX_DELAY__VALUE_reset 0x10
+
+// reg - hyperbus_cfg_regs::rwds_timing
+#define HYPERBUS_CFG_REGS__RWDS_TIMING__RWDS_OE_SETUP_CYCLES_bm 0xff
+#define HYPERBUS_CFG_REGS__RWDS_TIMING__RWDS_OE_SETUP_CYCLES_bp 0
+#define HYPERBUS_CFG_REGS__RWDS_TIMING__RWDS_OE_SETUP_CYCLES_bw 8
+#define HYPERBUS_CFG_REGS__RWDS_TIMING__RWDS_OE_SETUP_CYCLES_reset 0x1
+
+// regfile - hyperbus_cfg_regs::phy_regs
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t tx_delay;
+ uint32_t rwds_timing;
+} hyperbus_cfg_regs__phy_regs_t;
+
+// reg - hyperbus_cfg_regs::range_base
+#define HYPERBUS_CFG_REGS__RANGE_BASE__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE__VALUE_reset 0x0
+
+// reg - hyperbus_cfg_regs::range_bound
+#define HYPERBUS_CFG_REGS__RANGE_BOUND__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND__VALUE_reset 0x1
+
+// reg - hyperbus_cfg_regs::address_cfg
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_SPACE_bm 0xff
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_SPACE_bp 0
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_SPACE_bw 8
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_SPACE_reset 0x0
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_MASK_MSB_bm 0xff00
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_MASK_MSB_bp 8
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_MASK_MSB_bw 8
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_MASK_MSB_reset 0x19
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ENABLE_bm 0x10000
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ENABLE_bp 16
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ENABLE_bw 1
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ENABLE_reset 0x1
+
+// reg - hyperbus_cfg_regs::latency_cfg
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__T_LATENCY_ACCESS_bm 0xff
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__T_LATENCY_ACCESS_bp 0
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__T_LATENCY_ACCESS_bw 8
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__T_LATENCY_ACCESS_reset 0x6
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__RWDS_SAMPLE_DELAY_bm 0xff00
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__RWDS_SAMPLE_DELAY_bp 8
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__RWDS_SAMPLE_DELAY_bw 8
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__RWDS_SAMPLE_DELAY_reset 0x0
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__EN_LATENCY_ADDITIONAL_bm 0x10000
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__EN_LATENCY_ADDITIONAL_bp 16
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__EN_LATENCY_ADDITIONAL_bw 1
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__EN_LATENCY_ADDITIONAL_reset 0x0
+
+// reg - hyperbus_cfg_regs::burst_cfg
+#define HYPERBUS_CFG_REGS__BURST_CFG__T_BURST_MAX_bm 0xffff
+#define HYPERBUS_CFG_REGS__BURST_CFG__T_BURST_MAX_bp 0
+#define HYPERBUS_CFG_REGS__BURST_CFG__T_BURST_MAX_bw 16
+#define HYPERBUS_CFG_REGS__BURST_CFG__T_BURST_MAX_reset 0x15e
+
+// reg - hyperbus_cfg_regs::chip_timing
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_READ_WRITE_RECOVERY_bm 0xff
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_READ_WRITE_RECOVERY_bp 0
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_READ_WRITE_RECOVERY_bw 8
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_READ_WRITE_RECOVERY_reset 0x6
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_CSH_CYCLES_bm 0xff00
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_CSH_CYCLES_bp 8
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_CSH_CYCLES_bw 8
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_CSH_CYCLES_reset 0x1
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__CSN_TO_CK_CYCLES_bm 0xff0000
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__CSN_TO_CK_CYCLES_bp 16
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__CSN_TO_CK_CYCLES_bw 8
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__CSN_TO_CK_CYCLES_reset 0x0
+
+// reg - hyperbus_cfg_regs::rx_delay
+#define HYPERBUS_CFG_REGS__RX_DELAY__VALUE_bm 0xff
+#define HYPERBUS_CFG_REGS__RX_DELAY__VALUE_bp 0
+#define HYPERBUS_CFG_REGS__RX_DELAY__VALUE_bw 8
+#define HYPERBUS_CFG_REGS__RX_DELAY__VALUE_reset 0x10
+
+// regfile - hyperbus_cfg_regs::chip_regs
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_aea1d0e1
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_AEA1D0E1__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_AEA1D0E1__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_AEA1D0E1__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_AEA1D0E1__VALUE_reset 0x1
+
+// reg - hyperbus_cfg_regs::range_bound_value_e30f0c3f
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_E30F0C3F__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_E30F0C3F__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_E30F0C3F__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_E30F0C3F__VALUE_reset 0x2
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_de2a4636_range_bound_d40fd139
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_de2a4636_range_bound_d40fd139_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_e30f0c3f
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_E30F0C3F__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_E30F0C3F__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_E30F0C3F__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_E30F0C3F__VALUE_reset 0x2
+
+// reg - hyperbus_cfg_regs::range_bound_value_2f629ec9
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_2F629EC9__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_2F629EC9__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_2F629EC9__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_2F629EC9__VALUE_reset 0x3
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_b054dd4c_range_bound_a4d5f83b
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_b054dd4c_range_bound_a4d5f83b_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_2f629ec9
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_2F629EC9__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_2F629EC9__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_2F629EC9__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_2F629EC9__VALUE_reset 0x3
+
+// reg - hyperbus_cfg_regs::range_bound_value_a1e733c2
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_A1E733C2__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_A1E733C2__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_A1E733C2__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_A1E733C2__VALUE_reset 0x4
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_f7266ded_range_bound_5bf260e9
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_f7266ded_range_bound_5bf260e9_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_a1e733c2
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_A1E733C2__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_A1E733C2__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_A1E733C2__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_A1E733C2__VALUE_reset 0x4
+
+// reg - hyperbus_cfg_regs::range_bound_value_342915db
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_342915DB__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_342915DB__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_342915DB__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_342915DB__VALUE_reset 0x5
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_0d543b99_range_bound_1fffc3a2
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_0d543b99_range_bound_1fffc3a2_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_342915db
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_342915DB__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_342915DB__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_342915DB__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_342915DB__VALUE_reset 0x5
+
+// reg - hyperbus_cfg_regs::range_bound_value_883c384f
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_883C384F__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_883C384F__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_883C384F__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_883C384F__VALUE_reset 0x6
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_e068ab2e_range_bound_9afa5911
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_e068ab2e_range_bound_9afa5911_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_883c384f
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_883C384F__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_883C384F__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_883C384F__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_883C384F__VALUE_reset 0x6
+
+// reg - hyperbus_cfg_regs::range_bound_value_d0d03147
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_D0D03147__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_D0D03147__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_D0D03147__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_D0D03147__VALUE_reset 0x7
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_ac4fb754_range_bound_24b9644b
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_ac4fb754_range_bound_24b9644b_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_d0d03147
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_D0D03147__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_D0D03147__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_D0D03147__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_D0D03147__VALUE_reset 0x7
+
+// reg - hyperbus_cfg_regs::range_bound_value_971bab53
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_971BAB53__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_971BAB53__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_971BAB53__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_971BAB53__VALUE_reset 0x8
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_63c2ba90_range_bound_602aea67
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_63c2ba90_range_bound_602aea67_t;
+
+// reg - hyperbus_cfg_regs::reserved_top
+#define HYPERBUS_CFG_REGS__RESERVED_TOP__VALUE_bm 0xffffffff
+#define HYPERBUS_CFG_REGS__RESERVED_TOP__VALUE_bp 0
+#define HYPERBUS_CFG_REGS__RESERVED_TOP__VALUE_bw 32
+#define HYPERBUS_CFG_REGS__RESERVED_TOP__VALUE_reset 0x0
// addrmap - hyperbus_cfg_regs
typedef struct __attribute__ ((__packed__)) {
- uint32_t t_latency_access;
- uint32_t en_latency_additional;
- uint32_t t_burst_max;
- uint32_t t_read_write_recovery;
- uint32_t t_rx_clk_delay;
- uint32_t t_tx_clk_delay;
- uint32_t address_mask_msb;
- uint32_t address_space;
- uint32_t phys_in_use;
- uint32_t which_phy;
- uint32_t t_csh_cycles;
- uint32_t csn_to_ck_cycles;
- uint32_t chip0_base;
- uint32_t chip0_bound;
- uint32_t chip1_base;
- uint32_t chip1_bound;
- uint32_t chip2_base;
- uint32_t chip2_bound;
- uint32_t chip3_base;
- uint32_t chip3_bound;
- uint8_t RESERVED_50_57[0x8];
- uint32_t chip4_base;
- uint32_t chip4_bound;
- uint32_t chip5_base;
- uint32_t chip5_bound;
- uint32_t chip6_base;
- uint32_t chip6_bound;
- uint32_t chip7_base;
- uint32_t chip7_bound;
+ hyperbus_cfg_regs__global_regs_t global_cfg;
+ uint8_t RESERVED_14_ff[0xec];
+ hyperbus_cfg_regs__frontend_regs_t frontend;
+ uint8_t RESERVED_104_1ff[0xfc];
+ hyperbus_cfg_regs__backend_regs_t backend;
+ uint8_t RESERVED_204_2ff[0xfc];
+ hyperbus_cfg_regs__phy_regs_t phy_0;
+ uint8_t RESERVED_308_33f[0x38];
+ hyperbus_cfg_regs__phy_regs_t phy_1;
+ uint8_t RESERVED_348_3ff[0xb8];
+ hyperbus_cfg_regs__chip_regs_t chip_0;
+ uint8_t RESERVED_41c_43f[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_de2a4636_range_bound_d40fd139_t chip_1;
+ uint8_t RESERVED_45c_47f[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_b054dd4c_range_bound_a4d5f83b_t chip_2;
+ uint8_t RESERVED_49c_4bf[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_f7266ded_range_bound_5bf260e9_t chip_3;
+ uint8_t RESERVED_4dc_4ff[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_0d543b99_range_bound_1fffc3a2_t chip_4;
+ uint8_t RESERVED_51c_53f[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_e068ab2e_range_bound_9afa5911_t chip_5;
+ uint8_t RESERVED_55c_57f[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_ac4fb754_range_bound_24b9644b_t chip_6;
+ uint8_t RESERVED_59c_5bf[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_63c2ba90_range_bound_602aea67_t chip_7;
+ uint8_t RESERVED_5dc_ffb[0xa20];
+ uint32_t reserved_top;
} hyperbus_cfg_regs_t;
-static_assert(sizeof(hyperbus_cfg_regs_t) == 0x78, "Packing error");
+static_assert(sizeof(hyperbus_cfg_regs_t) == 0x1000, "Packing error");
#ifdef __cplusplus
}
diff --git a/scripts/gen_regs.sh b/scripts/gen_regs.sh
index 3d625fc..8ceb003 100755
--- a/scripts/gen_regs.sh
+++ b/scripts/gen_regs.sh
@@ -12,35 +12,37 @@ export UV_CACHE_DIR
export UV_TOOL_DIR
RDL="${ROOT}/src/regs/hyperbus_cfg_regs.rdl"
+PEAKRDL_ARGS=(
+ --from "peakrdl-cli==1.5.0"
+ --with "peakrdl-regblock==1.3.1"
+ --with "peakrdl-cheader==1.1.0"
+ --with "peakrdl-markdown==1.0.3"
+)
mkdir -p "${ROOT}/include" "${ROOT}/docs/regs"
rm -rf "${ROOT}/docs/regs/hyperbus_cfg_regs"
-uvx --from peakrdl-cli \
- --with peakrdl-regblock \
- --with peakrdl-cheader \
- --with peakrdl-markdown \
+uvx "${PEAKRDL_ARGS[@]}" \
peakrdl regblock \
--cpuif apb4-flat \
--default-reset arst_n \
--module-name hyperbus_cfg_regblock \
--package-name hyperbus_cfg_regblock_pkg \
- --addr-width 7 \
+ --addr-width 12 \
-o "${ROOT}/src/regs" \
"${RDL}"
-uvx --from peakrdl-cli \
- --with peakrdl-regblock \
- --with peakrdl-cheader \
- --with peakrdl-markdown \
+uvx "${PEAKRDL_ARGS[@]}" \
peakrdl c-header \
-o "${ROOT}/include/hyperbus_cfg_regs.h" \
"${RDL}"
-uvx --from peakrdl-cli \
- --with peakrdl-regblock \
- --with peakrdl-cheader \
- --with peakrdl-markdown \
+uvx "${PEAKRDL_ARGS[@]}" \
peakrdl markdown \
-o "${ROOT}/docs/regs/hyperbus_cfg_regs.md" \
"${RDL}"
+
+# Keep generated RTL compatible with the repository whitespace checks.
+sed -i 's/[[:space:]]\+$//' \
+ "${ROOT}/src/regs/hyperbus_cfg_regblock.sv" \
+ "${ROOT}/src/regs/hyperbus_cfg_regblock_pkg.sv"
diff --git a/src/hyperbus.sv b/src/hyperbus.sv
index ff0faa6..e0889db 100644
--- a/src/hyperbus.sv
+++ b/src/hyperbus.sv
@@ -22,6 +22,7 @@ module hyperbus #(
parameter type axi_r_chan_t = logic,
parameter type axi_aw_chan_t = logic,
parameter int unsigned RegDataWidth = -1,
+ parameter int unsigned RegAddrWidth = 32,
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic,
parameter type axi_rule_t = logic,
@@ -118,6 +119,8 @@ module hyperbus #(
.NumChips ( NumChips ),
.NumPhys ( NumPhys ),
.RegDataWidth ( RegDataWidth ),
+ .RegAddrWidth ( RegAddrWidth ),
+ .CapabilityFeatures ( '0 ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.rule_t ( axi_rule_t )
@@ -129,7 +132,12 @@ module hyperbus #(
.frontend_cfg_o ( frontend_cfg ),
.phy_cfg_o ( phy_cfg ),
.chip_rules_o ( chip_rules ),
- .trans_active_i ( trans_active )
+ .trans_active_i ( trans_active ),
+ .cfg_busy_i ( trans_active ),
+ .decode_error_i ( 1'b0 ),
+ .cfg_dirty_i ( 1'b0 ),
+ .flush_req_o ( ),
+ .apply_req_o ( )
);
// AXI slave interfacing PHY
diff --git a/src/hyperbus_cfg_regs.sv b/src/hyperbus_cfg_regs.sv
index 6c6ebd1..22162c5 100644
--- a/src/hyperbus_cfg_regs.sv
+++ b/src/hyperbus_cfg_regs.sv
@@ -10,6 +10,8 @@ module hyperbus_cfg_regs #(
parameter int unsigned NumChips = -1,
parameter int unsigned NumPhys = -1,
parameter int unsigned RegDataWidth = -1,
+ parameter int unsigned RegAddrWidth = 32,
+ parameter logic [7:0] CapabilityFeatures = '0,
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic,
parameter type rule_t = logic
@@ -23,21 +25,22 @@ module hyperbus_cfg_regs #(
output hyperbus_pkg::frontend_cfg_t frontend_cfg_o,
output hyperbus_pkg::phy_cfg_t phy_cfg_o,
output rule_t [NumChips-1:0] chip_rules_o,
- input trans_active_i
+ input logic trans_active_i,
+ input logic cfg_busy_i,
+ input logic decode_error_i,
+ input logic cfg_dirty_i,
+ output logic flush_req_o,
+ output logic apply_req_o
);
`include "common_cells/registers.svh"
localparam int unsigned NumChipsMax = 8;
- localparam int unsigned NumRegs = 30;
- localparam int unsigned RegsBits = cf_math_pkg::idx_width(NumRegs);
- localparam int unsigned RegStrbWidth = RegDataWidth/8;
-
`ASSERT_INIT(NumChipsValid, NumChips >= 1 && NumChips <= NumChipsMax)
`ASSERT_INIT(NumPhysValid, NumPhys == 1 || NumPhys == 2)
+ `ASSERT_INIT(RegAddrWidthValid, RegAddrWidth >= 12)
`ASSERT_INIT(RegDataWidthValid, RegDataWidth == 32)
- typedef logic [RegsBits-1:0] reg_idx_t;
- typedef logic [6:0] cfg_addr_t;
+ typedef logic [11:0] cfg_addr_t;
typedef logic [31:0] cfg_data_t;
typedef logic [3:0] cfg_strb_t;
@@ -72,36 +75,108 @@ module hyperbus_cfg_regs #(
} cfg_apb_rsp_t;
hyperbus_cfg_regblock_pkg::hyperbus_cfg_regs__out_t cfg_hwif_out;
+ hyperbus_cfg_regblock_pkg::hyperbus_cfg_regs__in_t cfg_hwif_in;
rule_t [NumChipsMax-1:0] chip_rules_all;
- reg_idx_t sel_reg;
+ cfg_addr_t cfg_addr;
+ logic cfg_addr_in_window;
logic sel_reg_mapped;
logic cfg_access_active_d, cfg_access_active_q;
logic cfg_access_open;
+ logic cfg_status_access;
+ logic cfg_value_valid;
+ logic unused_cfg_fields;
cfg_reg_req_t cfg_reg_req;
cfg_reg_rsp_t cfg_reg_rsp;
cfg_apb_req_t cfg_apb_req;
cfg_apb_rsp_t cfg_apb_rsp;
- assign sel_reg = reg_req_i.addr[$clog2(RegStrbWidth) +: RegsBits];
- assign sel_reg_mapped = (sel_reg < NumRegs);
- assign cfg_access_open = ~trans_active_i | cfg_access_active_q;
+ assign cfg_addr = cfg_addr_t'(reg_req_i.addr);
+ assign cfg_addr_in_window = reg_req_i.addr == RegAddrWidth'(cfg_addr);
+ assign cfg_status_access = reg_req_i.valid &&
+ cfg_addr_in_window && (cfg_addr == 12'h010);
+
+ always_comb begin : proc_cfg_addr_mapped
+ sel_reg_mapped = cfg_addr_in_window &&
+ ((cfg_addr == 12'h000) ||
+ (cfg_addr == 12'h004) ||
+ (cfg_addr == 12'h008) ||
+ (cfg_addr == 12'h00c) ||
+ (cfg_addr == 12'h010) ||
+ (cfg_addr == 12'h100) ||
+ (cfg_addr == 12'h200) ||
+ (cfg_addr == 12'hffc));
+ for (int unsigned i = 0; i < 2; i++) begin
+ sel_reg_mapped |= cfg_addr_in_window &&
+ ((cfg_addr == (12'h300 + i * 12'h40)) ||
+ (cfg_addr == (12'h304 + i * 12'h40)));
+ end
+ for (int unsigned i = 0; i < 8; i++) begin
+ sel_reg_mapped |= cfg_addr_in_window &&
+ ((cfg_addr == (12'h400 + i * 12'h40)) ||
+ (cfg_addr == (12'h404 + i * 12'h40)) ||
+ (cfg_addr == (12'h408 + i * 12'h40)) ||
+ (cfg_addr == (12'h40c + i * 12'h40)) ||
+ (cfg_addr == (12'h410 + i * 12'h40)) ||
+ (cfg_addr == (12'h414 + i * 12'h40)) ||
+ (cfg_addr == (12'h418 + i * 12'h40)));
+ end
+ end
+ assign cfg_access_open = ~trans_active_i | cfg_access_active_q | cfg_status_access;
+
+ always_comb begin : proc_cfg_value_valid
+ cfg_value_valid = 1'b1;
+ if (reg_req_i.valid && reg_req_i.write && sel_reg_mapped) begin
+ // All byte-backed legacy values are range-checked only when their
+ // corresponding byte is written, preserving partial-write behavior.
+ if ((cfg_addr == 12'h100) && reg_req_i.wstrb[0]) begin
+ cfg_value_valid &= (reg_req_i.wdata[7:0] <= 8'd1);
+ end
+ if ((cfg_addr == 12'h200) && reg_req_i.wstrb[0]) begin
+ cfg_value_valid &= (reg_req_i.wdata[7:0] >= 8'd2);
+ end
+ if (((cfg_addr == 12'h304) || (cfg_addr == 12'h344)) &&
+ reg_req_i.wstrb[0]) begin
+ cfg_value_valid &= (reg_req_i.wdata[7:0] <= 8'd15);
+ end
+ for (int unsigned i = 0; i < 8; i++) begin
+ if (cfg_addr == (12'h408 + i * 12'h40)) begin
+ if (reg_req_i.wstrb[0]) cfg_value_valid &= (reg_req_i.wdata[7:0] <= 8'd1);
+ if (reg_req_i.wstrb[1]) cfg_value_valid &= (reg_req_i.wdata[15:8] <= 8'd31);
+ if (reg_req_i.wstrb[2]) cfg_value_valid &= (reg_req_i.wdata[23:16] <= 8'd1);
+ end
+ if (cfg_addr == (12'h40c + i * 12'h40)) begin
+ if (reg_req_i.wstrb[0]) cfg_value_valid &=
+ (reg_req_i.wdata[7:0] >= 8'd3 && reg_req_i.wdata[7:0] <= 8'd15);
+ if (reg_req_i.wstrb[1]) cfg_value_valid &= (reg_req_i.wdata[15:8] <= 8'd15);
+ if (reg_req_i.wstrb[2]) cfg_value_valid &= (reg_req_i.wdata[23:16] <= 8'd1);
+ end
+ if (cfg_addr == (12'h414 + i * 12'h40)) begin
+ if (reg_req_i.wstrb[0]) cfg_value_valid &= (reg_req_i.wdata[7:0] <= 8'd15);
+ if (reg_req_i.wstrb[1]) cfg_value_valid &= (reg_req_i.wdata[15:8] <= 8'd15);
+ if (reg_req_i.wstrb[2]) cfg_value_valid &= (reg_req_i.wdata[23:16] <= 8'd15);
+ end
+ end
+ end
+ end
assign reg_rsp_o.ready = cfg_access_open &
- (~reg_req_i.valid | ~sel_reg_mapped | cfg_reg_rsp.ready);
- assign reg_rsp_o.error = ~sel_reg_mapped | cfg_reg_rsp.error;
+ (~reg_req_i.valid | ~sel_reg_mapped | ~cfg_value_valid | cfg_reg_rsp.ready);
+ assign reg_rsp_o.error = (reg_req_i.valid && ~sel_reg_mapped) |
+ (reg_req_i.valid && reg_req_i.write && sel_reg_mapped && !cfg_value_valid) |
+ cfg_reg_rsp.error;
assign reg_rsp_o.rdata = sel_reg_mapped ? RegDataWidth'(cfg_reg_rsp.rdata) : '0;
- assign cfg_reg_req.valid = reg_req_i.valid & sel_reg_mapped & cfg_access_open;
- assign cfg_reg_req.addr = {sel_reg, 2'b00};
+ assign cfg_reg_req.valid = reg_req_i.valid & sel_reg_mapped & cfg_access_open & cfg_value_valid;
+ assign cfg_reg_req.addr = cfg_addr;
assign cfg_reg_req.write = reg_req_i.write;
assign cfg_reg_req.wdata = 32'(reg_req_i.wdata);
assign cfg_reg_req.wstrb = cfg_strb_t'(reg_req_i.wstrb);
always_comb begin : proc_cfg_access
cfg_access_active_d = cfg_access_active_q;
- if (!cfg_access_active_q && cfg_reg_req.valid) begin
+ if (!cfg_access_active_q && cfg_reg_req.valid && !cfg_status_access) begin
cfg_access_active_d = 1'b1;
end
if (cfg_access_active_q && cfg_reg_rsp.ready) begin
@@ -115,60 +190,44 @@ module hyperbus_cfg_regs #(
chip_rules_all = '0;
for (int unsigned i = 0; i < NumChipsMax; i++) begin
chip_rules_all[i].idx = unsigned'(i);
- unique case (i)
- 0: begin
- chip_rules_all[i].start_addr = {
- cfg_hwif_out.chip0_base.value.value, 22'b0};
- chip_rules_all[i].end_addr = {
- cfg_hwif_out.chip0_bound.value.value, 22'b0};
- end
- 1: begin
- chip_rules_all[i].start_addr = {
- cfg_hwif_out.chip1_base.value.value, 22'b0};
- chip_rules_all[i].end_addr = {
- cfg_hwif_out.chip1_bound.value.value, 22'b0};
- end
- 2: begin
- chip_rules_all[i].start_addr = {
- cfg_hwif_out.chip2_base.value.value, 22'b0};
- chip_rules_all[i].end_addr = {
- cfg_hwif_out.chip2_bound.value.value, 22'b0};
- end
- 3: begin
- chip_rules_all[i].start_addr = {
- cfg_hwif_out.chip3_base.value.value, 22'b0};
- chip_rules_all[i].end_addr = {
- cfg_hwif_out.chip3_bound.value.value, 22'b0};
- end
- 4: begin
- chip_rules_all[i].start_addr = {
- cfg_hwif_out.chip4_base.value.value, 22'b0};
- chip_rules_all[i].end_addr = {
- cfg_hwif_out.chip4_bound.value.value, 22'b0};
- end
- 5: begin
- chip_rules_all[i].start_addr = {
- cfg_hwif_out.chip5_base.value.value, 22'b0};
- chip_rules_all[i].end_addr = {
- cfg_hwif_out.chip5_bound.value.value, 22'b0};
- end
- 6: begin
- chip_rules_all[i].start_addr = {
- cfg_hwif_out.chip6_base.value.value, 22'b0};
- chip_rules_all[i].end_addr = {
- cfg_hwif_out.chip6_bound.value.value, 22'b0};
- end
- 7: begin
- chip_rules_all[i].start_addr = {
- cfg_hwif_out.chip7_base.value.value, 22'b0};
- chip_rules_all[i].end_addr = {
- cfg_hwif_out.chip7_bound.value.value, 22'b0};
- end
- default:;
- endcase
end
+ chip_rules_all[0].start_addr = {cfg_hwif_out.chip_0.range_base.value.value, 22'b0};
+ chip_rules_all[0].end_addr = {cfg_hwif_out.chip_0.range_bound.value.value, 22'b0};
+ chip_rules_all[1].start_addr = {cfg_hwif_out.chip_1.range_base.value.value, 22'b0};
+ chip_rules_all[1].end_addr = {cfg_hwif_out.chip_1.range_bound.value.value, 22'b0};
+ chip_rules_all[2].start_addr = {cfg_hwif_out.chip_2.range_base.value.value, 22'b0};
+ chip_rules_all[2].end_addr = {cfg_hwif_out.chip_2.range_bound.value.value, 22'b0};
+ chip_rules_all[3].start_addr = {cfg_hwif_out.chip_3.range_base.value.value, 22'b0};
+ chip_rules_all[3].end_addr = {cfg_hwif_out.chip_3.range_bound.value.value, 22'b0};
+ chip_rules_all[4].start_addr = {cfg_hwif_out.chip_4.range_base.value.value, 22'b0};
+ chip_rules_all[4].end_addr = {cfg_hwif_out.chip_4.range_bound.value.value, 22'b0};
+ chip_rules_all[5].start_addr = {cfg_hwif_out.chip_5.range_base.value.value, 22'b0};
+ chip_rules_all[5].end_addr = {cfg_hwif_out.chip_5.range_bound.value.value, 22'b0};
+ chip_rules_all[6].start_addr = {cfg_hwif_out.chip_6.range_base.value.value, 22'b0};
+ chip_rules_all[6].end_addr = {cfg_hwif_out.chip_6.range_bound.value.value, 22'b0};
+ chip_rules_all[7].start_addr = {cfg_hwif_out.chip_7.range_base.value.value, 22'b0};
+ chip_rules_all[7].end_addr = {cfg_hwif_out.chip_7.range_bound.value.value, 22'b0};
end
+ assign cfg_hwif_in.global_cfg.capability.num_chips.next = 8'(NumChips);
+ assign cfg_hwif_in.global_cfg.capability.num_phys.next = 8'(NumPhys);
+ assign cfg_hwif_in.global_cfg.capability.per_chip_cfg.next = CapabilityFeatures[0];
+ assign cfg_hwif_in.global_cfg.capability.per_phy_cfg.next = CapabilityFeatures[1];
+ assign cfg_hwif_in.global_cfg.capability.chip_enable.next = CapabilityFeatures[2];
+ assign cfg_hwif_in.global_cfg.capability.clock_divider.next = CapabilityFeatures[3];
+ assign cfg_hwif_in.global_cfg.capability.staged_apply.next = CapabilityFeatures[4];
+ assign cfg_hwif_in.global_cfg.capability.error_status.next = CapabilityFeatures[5];
+ assign cfg_hwif_in.global_cfg.capability.rwds_sample_timing.next =
+ CapabilityFeatures[6];
+ assign cfg_hwif_in.global_cfg.capability.rwds_oe_timing.next = CapabilityFeatures[7];
+ assign cfg_hwif_in.global_cfg.status.decode_error.next =
+ cfg_hwif_out.global_cfg.status.decode_error.value;
+ assign cfg_hwif_in.global_cfg.status.decode_error.hwset = decode_error_i;
+ assign cfg_hwif_in.global_cfg.status.busy.next = cfg_busy_i;
+ assign cfg_hwif_in.global_cfg.status.dirty.next = cfg_dirty_i;
+ assign flush_req_o = cfg_hwif_out.global_cfg.command.flush.value;
+ assign apply_req_o = cfg_hwif_out.global_cfg.command.apply.value;
+
reg_to_apb #(
.reg_req_t ( cfg_reg_req_t ),
.reg_rsp_t ( cfg_reg_rsp_t ),
@@ -196,6 +255,7 @@ module hyperbus_cfg_regs #(
.s_apb_pready ( cfg_apb_rsp.pready ),
.s_apb_prdata ( cfg_apb_rsp.prdata ),
.s_apb_pslverr ( cfg_apb_rsp.pslverr ),
+ .hwif_in ( cfg_hwif_in ),
.hwif_out ( cfg_hwif_out )
);
@@ -203,31 +263,46 @@ module hyperbus_cfg_regs #(
frontend_cfg_o = '0;
phy_cfg_o = '0;
- frontend_cfg_o.address_mask_msb = cfg_hwif_out.address_mask_msb.value.value;
- frontend_cfg_o.address_space = cfg_hwif_out.address_space.value.value;
+ frontend_cfg_o.address_mask_msb = cfg_hwif_out.chip_0.address_cfg.address_mask_msb.value;
+ frontend_cfg_o.address_space = cfg_hwif_out.chip_0.address_cfg.address_space.value[0];
frontend_cfg_o.phys_in_use = (NumPhys == 2) &&
- cfg_hwif_out.phys_in_use.value.value;
- frontend_cfg_o.which_phy = (NumPhys == 2) &&
- cfg_hwif_out.which_phy.value.value;
-
- phy_cfg_o.chip.t_latency_access = cfg_hwif_out.t_latency_access.value.value;
- phy_cfg_o.chip.en_latency_additional = cfg_hwif_out.en_latency_additional.value.value;
- phy_cfg_o.chip.t_burst_max = cfg_hwif_out.t_burst_max.value.value;
- phy_cfg_o.chip.t_read_write_recovery = cfg_hwif_out.t_read_write_recovery.value.value;
- phy_cfg_o.chip.t_rx_clk_delay = {
- cfg_hwif_out.t_rx_clk_delay.coarse.value,
- cfg_hwif_out.t_rx_clk_delay.fine.value
- };
- phy_cfg_o.chip.t_csh_cycles = cfg_hwif_out.t_csh_cycles.value.value;
- phy_cfg_o.chip.csn_to_ck_cycles = cfg_hwif_out.csn_to_ck_cycles.value.value;
- phy_cfg_o.t_tx_clk_delay = {
- cfg_hwif_out.t_tx_clk_delay.coarse.value,
- cfg_hwif_out.t_tx_clk_delay.fine.value
- };
+ cfg_hwif_out.frontend.frontend_cfg.dual_phy.value;
+ frontend_cfg_o.which_phy = 1'b0;
+
+ phy_cfg_o.chip.t_latency_access = cfg_hwif_out.chip_0.latency_cfg.t_latency_access.value;
+ phy_cfg_o.chip.en_latency_additional = cfg_hwif_out.chip_0.latency_cfg.en_latency_additional.value;
+ phy_cfg_o.chip.t_burst_max = cfg_hwif_out.chip_0.burst_cfg.t_burst_max.value;
+ phy_cfg_o.chip.t_read_write_recovery = cfg_hwif_out.chip_0.chip_timing.t_read_write_recovery.value;
+ phy_cfg_o.chip.t_rx_clk_delay = cfg_hwif_out.chip_0.rx_delay.value.value;
+ phy_cfg_o.chip.t_csh_cycles = cfg_hwif_out.chip_0.chip_timing.t_csh_cycles.value;
+ phy_cfg_o.chip.csn_to_ck_cycles = cfg_hwif_out.chip_0.chip_timing.csn_to_ck_cycles.value;
+ phy_cfg_o.t_tx_clk_delay = cfg_hwif_out.phy_0.tx_delay.value.value;
phy_cfg_o.phys_in_use = (NumPhys == 2) &&
- cfg_hwif_out.phys_in_use.value.value;
- phy_cfg_o.which_phy = (NumPhys == 2) &&
- cfg_hwif_out.which_phy.value.value;
+ cfg_hwif_out.frontend.frontend_cfg.dual_phy.value;
+ phy_cfg_o.which_phy = 1'b0;
+ end
+
+ // The legacy PR34 interface has no destinations for these newer fields.
+ always_comb begin : proc_unused_cfg_fields
+ unused_cfg_fields = ^cfg_hwif_out.backend.clock_cfg.divider.value;
+ unused_cfg_fields |= ^cfg_hwif_out.phy_0.rwds_timing.rwds_oe_setup_cycles.value;
+ unused_cfg_fields |= ^cfg_hwif_out.phy_1.rwds_timing.rwds_oe_setup_cycles.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_0.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_0.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_1.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_1.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_2.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_2.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_3.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_3.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_4.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_4.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_5.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_5.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_6.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_6.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_7.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_7.latency_cfg.rwds_sample_delay.value;
end
for (genvar i = 0; unsigned'(i) < NumChipsMax; i++) begin : gen_chip_rules
diff --git a/src/hyperbus_synth_wrap.sv b/src/hyperbus_synth_wrap.sv
index e7fc312..ed9ccc4 100644
--- a/src/hyperbus_synth_wrap.sv
+++ b/src/hyperbus_synth_wrap.sv
@@ -146,6 +146,7 @@ module hyperbus_lint_wrap #(
.axi_r_chan_t ( r_chan_t ),
.axi_aw_chan_t ( aw_chan_t ),
.RegDataWidth ( RegDataWidth ),
+ .RegAddrWidth ( RegAddrWidth ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.axi_rule_t ( axi_rule_t )
diff --git a/src/regs/hyperbus_cfg_regblock.sv b/src/regs/hyperbus_cfg_regblock.sv
index 75b0286..ec72f2c 100644
--- a/src/regs/hyperbus_cfg_regblock.sv
+++ b/src/regs/hyperbus_cfg_regblock.sv
@@ -9,13 +9,14 @@ module hyperbus_cfg_regblock (
input wire s_apb_penable,
input wire s_apb_pwrite,
input wire [2:0] s_apb_pprot,
- input wire [6:0] s_apb_paddr,
+ input wire [11:0] s_apb_paddr,
input wire [31:0] s_apb_pwdata,
input wire [3:0] s_apb_pstrb,
output logic s_apb_pready,
output logic [31:0] s_apb_prdata,
output logic s_apb_pslverr,
+ input hyperbus_cfg_regblock_pkg::hyperbus_cfg_regs__in_t hwif_in,
output hyperbus_cfg_regblock_pkg::hyperbus_cfg_regs__out_t hwif_out
);
@@ -24,7 +25,7 @@ module hyperbus_cfg_regblock (
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_req_is_wr;
- logic [6:0] cpuif_addr;
+ logic [11:0] cpuif_addr;
logic [31:0] cpuif_wr_data;
logic [31:0] cpuif_wr_biten;
logic cpuif_req_stall_wr;
@@ -53,7 +54,7 @@ module hyperbus_cfg_regblock (
is_active <= '1;
cpuif_req <= '1;
cpuif_req_is_wr <= s_apb_pwrite;
- cpuif_addr <= {s_apb_paddr[6:2], 2'b0};
+ cpuif_addr <= {s_apb_paddr[11:2], 2'b0};
cpuif_wr_data <= s_apb_pwdata;
for(int i=0; i<4; i++) begin
cpuif_wr_biten[i*8 +: 8] <= {8{s_apb_pstrb[i]}};
@@ -86,38 +87,104 @@ module hyperbus_cfg_regblock (
// Address Decode
//--------------------------------------------------------------------------
typedef struct {
- logic t_latency_access;
- logic en_latency_additional;
- logic t_burst_max;
- logic t_read_write_recovery;
- logic t_rx_clk_delay;
- logic t_tx_clk_delay;
- logic address_mask_msb;
- logic address_space;
- logic phys_in_use;
- logic which_phy;
- logic t_csh_cycles;
- logic csn_to_ck_cycles;
- logic chip0_base;
- logic chip0_bound;
- logic chip1_base;
- logic chip1_bound;
- logic chip2_base;
- logic chip2_bound;
- logic chip3_base;
- logic chip3_bound;
- logic chip4_base;
- logic chip4_bound;
- logic chip5_base;
- logic chip5_bound;
- logic chip6_base;
- logic chip6_bound;
- logic chip7_base;
- logic chip7_bound;
+ struct {
+ logic ip_version;
+ logic reg_if_version;
+ logic capability;
+ logic command;
+ logic status;
+ } global_cfg;
+ struct {
+ logic frontend_cfg;
+ } frontend;
+ struct {
+ logic clock_cfg;
+ } backend;
+ struct {
+ logic tx_delay;
+ logic rwds_timing;
+ } phy_0;
+ struct {
+ logic tx_delay;
+ logic rwds_timing;
+ } phy_1;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_0;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_1;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_2;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_3;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_4;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_5;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_6;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_7;
+ logic reserved_top;
} decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb;
logic decoded_err;
- logic [6:0] decoded_addr;
+ logic [11:0] decoded_addr;
logic decoded_req;
logic decoded_req_is_wr;
logic [31:0] decoded_wr_data;
@@ -128,34 +195,74 @@ module hyperbus_cfg_regblock (
automatic logic is_valid_rw;
is_valid_addr = '1; // No valid address check
is_valid_rw = '1; // No valid RW check
- decoded_reg_strb.t_latency_access = cpuif_req_masked & (cpuif_addr == 7'h0);
- decoded_reg_strb.en_latency_additional = cpuif_req_masked & (cpuif_addr == 7'h4);
- decoded_reg_strb.t_burst_max = cpuif_req_masked & (cpuif_addr == 7'h8);
- decoded_reg_strb.t_read_write_recovery = cpuif_req_masked & (cpuif_addr == 7'hc);
- decoded_reg_strb.t_rx_clk_delay = cpuif_req_masked & (cpuif_addr == 7'h10);
- decoded_reg_strb.t_tx_clk_delay = cpuif_req_masked & (cpuif_addr == 7'h14);
- decoded_reg_strb.address_mask_msb = cpuif_req_masked & (cpuif_addr == 7'h18);
- decoded_reg_strb.address_space = cpuif_req_masked & (cpuif_addr == 7'h1c);
- decoded_reg_strb.phys_in_use = cpuif_req_masked & (cpuif_addr == 7'h20);
- decoded_reg_strb.which_phy = cpuif_req_masked & (cpuif_addr == 7'h24);
- decoded_reg_strb.t_csh_cycles = cpuif_req_masked & (cpuif_addr == 7'h28);
- decoded_reg_strb.csn_to_ck_cycles = cpuif_req_masked & (cpuif_addr == 7'h2c);
- decoded_reg_strb.chip0_base = cpuif_req_masked & (cpuif_addr == 7'h30);
- decoded_reg_strb.chip0_bound = cpuif_req_masked & (cpuif_addr == 7'h34);
- decoded_reg_strb.chip1_base = cpuif_req_masked & (cpuif_addr == 7'h38);
- decoded_reg_strb.chip1_bound = cpuif_req_masked & (cpuif_addr == 7'h3c);
- decoded_reg_strb.chip2_base = cpuif_req_masked & (cpuif_addr == 7'h40);
- decoded_reg_strb.chip2_bound = cpuif_req_masked & (cpuif_addr == 7'h44);
- decoded_reg_strb.chip3_base = cpuif_req_masked & (cpuif_addr == 7'h48);
- decoded_reg_strb.chip3_bound = cpuif_req_masked & (cpuif_addr == 7'h4c);
- decoded_reg_strb.chip4_base = cpuif_req_masked & (cpuif_addr == 7'h58);
- decoded_reg_strb.chip4_bound = cpuif_req_masked & (cpuif_addr == 7'h5c);
- decoded_reg_strb.chip5_base = cpuif_req_masked & (cpuif_addr == 7'h60);
- decoded_reg_strb.chip5_bound = cpuif_req_masked & (cpuif_addr == 7'h64);
- decoded_reg_strb.chip6_base = cpuif_req_masked & (cpuif_addr == 7'h68);
- decoded_reg_strb.chip6_bound = cpuif_req_masked & (cpuif_addr == 7'h6c);
- decoded_reg_strb.chip7_base = cpuif_req_masked & (cpuif_addr == 7'h70);
- decoded_reg_strb.chip7_bound = cpuif_req_masked & (cpuif_addr == 7'h74);
+ decoded_reg_strb.global_cfg.ip_version = cpuif_req_masked & (cpuif_addr == 12'h0) & !cpuif_req_is_wr;
+ decoded_reg_strb.global_cfg.reg_if_version = cpuif_req_masked & (cpuif_addr == 12'h4) & !cpuif_req_is_wr;
+ decoded_reg_strb.global_cfg.capability = cpuif_req_masked & (cpuif_addr == 12'h8) & !cpuif_req_is_wr;
+ decoded_reg_strb.global_cfg.command = cpuif_req_masked & (cpuif_addr == 12'hc);
+ decoded_reg_strb.global_cfg.status = cpuif_req_masked & (cpuif_addr == 12'h10);
+ decoded_reg_strb.frontend.frontend_cfg = cpuif_req_masked & (cpuif_addr == 12'h100);
+ decoded_reg_strb.backend.clock_cfg = cpuif_req_masked & (cpuif_addr == 12'h200);
+ decoded_reg_strb.phy_0.tx_delay = cpuif_req_masked & (cpuif_addr == 12'h300);
+ decoded_reg_strb.phy_0.rwds_timing = cpuif_req_masked & (cpuif_addr == 12'h304);
+ decoded_reg_strb.phy_1.tx_delay = cpuif_req_masked & (cpuif_addr == 12'h340);
+ decoded_reg_strb.phy_1.rwds_timing = cpuif_req_masked & (cpuif_addr == 12'h344);
+ decoded_reg_strb.chip_0.range_base = cpuif_req_masked & (cpuif_addr == 12'h400);
+ decoded_reg_strb.chip_0.range_bound = cpuif_req_masked & (cpuif_addr == 12'h404);
+ decoded_reg_strb.chip_0.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h408);
+ decoded_reg_strb.chip_0.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h40c);
+ decoded_reg_strb.chip_0.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h410);
+ decoded_reg_strb.chip_0.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h414);
+ decoded_reg_strb.chip_0.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h418);
+ decoded_reg_strb.chip_1.range_base = cpuif_req_masked & (cpuif_addr == 12'h440);
+ decoded_reg_strb.chip_1.range_bound = cpuif_req_masked & (cpuif_addr == 12'h444);
+ decoded_reg_strb.chip_1.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h448);
+ decoded_reg_strb.chip_1.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h44c);
+ decoded_reg_strb.chip_1.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h450);
+ decoded_reg_strb.chip_1.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h454);
+ decoded_reg_strb.chip_1.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h458);
+ decoded_reg_strb.chip_2.range_base = cpuif_req_masked & (cpuif_addr == 12'h480);
+ decoded_reg_strb.chip_2.range_bound = cpuif_req_masked & (cpuif_addr == 12'h484);
+ decoded_reg_strb.chip_2.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h488);
+ decoded_reg_strb.chip_2.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h48c);
+ decoded_reg_strb.chip_2.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h490);
+ decoded_reg_strb.chip_2.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h494);
+ decoded_reg_strb.chip_2.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h498);
+ decoded_reg_strb.chip_3.range_base = cpuif_req_masked & (cpuif_addr == 12'h4c0);
+ decoded_reg_strb.chip_3.range_bound = cpuif_req_masked & (cpuif_addr == 12'h4c4);
+ decoded_reg_strb.chip_3.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h4c8);
+ decoded_reg_strb.chip_3.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h4cc);
+ decoded_reg_strb.chip_3.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h4d0);
+ decoded_reg_strb.chip_3.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h4d4);
+ decoded_reg_strb.chip_3.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h4d8);
+ decoded_reg_strb.chip_4.range_base = cpuif_req_masked & (cpuif_addr == 12'h500);
+ decoded_reg_strb.chip_4.range_bound = cpuif_req_masked & (cpuif_addr == 12'h504);
+ decoded_reg_strb.chip_4.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h508);
+ decoded_reg_strb.chip_4.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h50c);
+ decoded_reg_strb.chip_4.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h510);
+ decoded_reg_strb.chip_4.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h514);
+ decoded_reg_strb.chip_4.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h518);
+ decoded_reg_strb.chip_5.range_base = cpuif_req_masked & (cpuif_addr == 12'h540);
+ decoded_reg_strb.chip_5.range_bound = cpuif_req_masked & (cpuif_addr == 12'h544);
+ decoded_reg_strb.chip_5.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h548);
+ decoded_reg_strb.chip_5.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h54c);
+ decoded_reg_strb.chip_5.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h550);
+ decoded_reg_strb.chip_5.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h554);
+ decoded_reg_strb.chip_5.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h558);
+ decoded_reg_strb.chip_6.range_base = cpuif_req_masked & (cpuif_addr == 12'h580);
+ decoded_reg_strb.chip_6.range_bound = cpuif_req_masked & (cpuif_addr == 12'h584);
+ decoded_reg_strb.chip_6.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h588);
+ decoded_reg_strb.chip_6.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h58c);
+ decoded_reg_strb.chip_6.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h590);
+ decoded_reg_strb.chip_6.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h594);
+ decoded_reg_strb.chip_6.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h598);
+ decoded_reg_strb.chip_7.range_base = cpuif_req_masked & (cpuif_addr == 12'h5c0);
+ decoded_reg_strb.chip_7.range_bound = cpuif_req_masked & (cpuif_addr == 12'h5c4);
+ decoded_reg_strb.chip_7.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h5c8);
+ decoded_reg_strb.chip_7.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h5cc);
+ decoded_reg_strb.chip_7.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h5d0);
+ decoded_reg_strb.chip_7.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h5d4);
+ decoded_reg_strb.chip_7.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h5d8);
+ decoded_reg_strb.reserved_top = cpuif_req_masked & (cpuif_addr == 12'hffc) & !cpuif_req_is_wr;
decoded_err = '0;
end
@@ -172,1129 +279,4380 @@ module hyperbus_cfg_regblock (
typedef struct {
struct {
struct {
- logic [3:0] next;
- logic load_next;
- } value;
- } t_latency_access;
- struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } num_chips;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } num_phys;
+ struct {
+ logic next;
+ logic load_next;
+ } per_chip_cfg;
+ struct {
+ logic next;
+ logic load_next;
+ } per_phy_cfg;
+ struct {
+ logic next;
+ logic load_next;
+ } chip_enable;
+ struct {
+ logic next;
+ logic load_next;
+ } clock_divider;
+ struct {
+ logic next;
+ logic load_next;
+ } staged_apply;
+ struct {
+ logic next;
+ logic load_next;
+ } error_status;
+ struct {
+ logic next;
+ logic load_next;
+ } rwds_sample_timing;
+ struct {
+ logic next;
+ logic load_next;
+ } rwds_oe_timing;
+ } capability;
struct {
- logic next;
- logic load_next;
- } value;
- } en_latency_additional;
+ struct {
+ logic next;
+ logic load_next;
+ } flush;
+ struct {
+ logic next;
+ logic load_next;
+ } apply;
+ } command;
+ struct {
+ struct {
+ logic next;
+ logic load_next;
+ } decode_error;
+ struct {
+ logic next;
+ logic load_next;
+ } busy;
+ struct {
+ logic next;
+ logic load_next;
+ } dirty;
+ } status;
+ } global_cfg;
struct {
struct {
- logic [15:0] next;
- logic load_next;
- } value;
- } t_burst_max;
+ struct {
+ logic next;
+ logic load_next;
+ } dual_phy;
+ } frontend_cfg;
+ } frontend;
struct {
struct {
- logic [3:0] next;
- logic load_next;
- } value;
- } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } divider;
+ } clock_cfg;
+ } backend;
struct {
struct {
- logic [4:0] next;
- logic load_next;
- } fine;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } tx_delay;
struct {
- logic [2:0] next;
- logic load_next;
- } coarse;
- } t_rx_clk_delay;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_oe_setup_cycles;
+ } rwds_timing;
+ } phy_0;
struct {
struct {
- logic [4:0] next;
- logic load_next;
- } fine;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } tx_delay;
struct {
- logic [2:0] next;
- logic load_next;
- } coarse;
- } t_tx_clk_delay;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_oe_setup_cycles;
+ } rwds_timing;
+ } phy_1;
struct {
struct {
- logic [4:0] next;
- logic load_next;
- } value;
- } address_mask_msb;
- struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
struct {
- logic next;
- logic load_next;
- } value;
- } address_space;
- struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
struct {
- logic next;
- logic load_next;
- } value;
- } phys_in_use;
- struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
struct {
- logic next;
- logic load_next;
- } value;
- } which_phy;
- struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
struct {
- logic [3:0] next;
- logic load_next;
- } value;
- } t_csh_cycles;
- struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
struct {
- logic [3:0] next;
- logic load_next;
- } value;
- } csn_to_ck_cycles;
- struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip0_base;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_0;
struct {
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip0_bound;
- struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip1_base;
- struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip1_bound;
- struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip2_base;
- struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip2_bound;
- struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip3_base;
- struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip3_bound;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_1;
struct {
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip4_base;
- struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip4_bound;
- struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip5_base;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_2;
struct {
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip5_bound;
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_3;
struct {
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip6_base;
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_4;
struct {
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip6_bound;
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_5;
struct {
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip7_base;
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_6;
struct {
struct {
- logic [9:0] next;
- logic load_next;
- } value;
- } chip7_bound;
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_7;
} field_combo_t;
field_combo_t field_combo;
typedef struct {
struct {
struct {
- logic [3:0] value;
- } value;
- } t_latency_access;
- struct {
+ struct {
+ logic [7:0] value;
+ } num_chips;
+ struct {
+ logic [7:0] value;
+ } num_phys;
+ struct {
+ logic value;
+ } per_chip_cfg;
+ struct {
+ logic value;
+ } per_phy_cfg;
+ struct {
+ logic value;
+ } chip_enable;
+ struct {
+ logic value;
+ } clock_divider;
+ struct {
+ logic value;
+ } staged_apply;
+ struct {
+ logic value;
+ } error_status;
+ struct {
+ logic value;
+ } rwds_sample_timing;
+ struct {
+ logic value;
+ } rwds_oe_timing;
+ } capability;
struct {
- logic value;
- } value;
- } en_latency_additional;
+ struct {
+ logic value;
+ } flush;
+ struct {
+ logic value;
+ } apply;
+ } command;
+ struct {
+ struct {
+ logic value;
+ } decode_error;
+ struct {
+ logic value;
+ } busy;
+ struct {
+ logic value;
+ } dirty;
+ } status;
+ } global_cfg;
struct {
struct {
- logic [15:0] value;
- } value;
- } t_burst_max;
+ struct {
+ logic value;
+ } dual_phy;
+ } frontend_cfg;
+ } frontend;
struct {
struct {
- logic [3:0] value;
- } value;
- } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } divider;
+ } clock_cfg;
+ } backend;
struct {
struct {
- logic [4:0] value;
- } fine;
+ struct {
+ logic [7:0] value;
+ } value;
+ } tx_delay;
struct {
- logic [2:0] value;
- } coarse;
- } t_rx_clk_delay;
+ struct {
+ logic [7:0] value;
+ } rwds_oe_setup_cycles;
+ } rwds_timing;
+ } phy_0;
struct {
struct {
- logic [4:0] value;
- } fine;
+ struct {
+ logic [7:0] value;
+ } value;
+ } tx_delay;
struct {
- logic [2:0] value;
- } coarse;
- } t_tx_clk_delay;
+ struct {
+ logic [7:0] value;
+ } rwds_oe_setup_cycles;
+ } rwds_timing;
+ } phy_1;
struct {
struct {
- logic [4:0] value;
- } value;
- } address_mask_msb;
- struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
struct {
- logic value;
- } value;
- } address_space;
- struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
struct {
- logic value;
- } value;
- } phys_in_use;
- struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
struct {
- logic value;
- } value;
- } which_phy;
- struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
struct {
- logic [3:0] value;
- } value;
- } t_csh_cycles;
- struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
struct {
- logic [3:0] value;
- } value;
- } csn_to_ck_cycles;
- struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
struct {
- logic [9:0] value;
- } value;
- } chip0_base;
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_0;
struct {
struct {
- logic [9:0] value;
- } value;
- } chip0_bound;
- struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
struct {
- logic [9:0] value;
- } value;
- } chip1_base;
- struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
struct {
- logic [9:0] value;
- } value;
- } chip1_bound;
- struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
struct {
- logic [9:0] value;
- } value;
- } chip2_base;
- struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
struct {
- logic [9:0] value;
- } value;
- } chip2_bound;
- struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
struct {
- logic [9:0] value;
- } value;
- } chip3_base;
- struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
struct {
- logic [9:0] value;
- } value;
- } chip3_bound;
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_1;
struct {
struct {
- logic [9:0] value;
- } value;
- } chip4_base;
- struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
struct {
- logic [9:0] value;
- } value;
- } chip4_bound;
- struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
struct {
- logic [9:0] value;
- } value;
- } chip5_base;
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_2;
struct {
struct {
- logic [9:0] value;
- } value;
- } chip5_bound;
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_3;
struct {
struct {
- logic [9:0] value;
- } value;
- } chip6_base;
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_4;
struct {
struct {
- logic [9:0] value;
- } value;
- } chip6_bound;
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_5;
struct {
struct {
- logic [9:0] value;
- } value;
- } chip7_base;
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_6;
struct {
struct {
- logic [9:0] value;
- } value;
- } chip7_bound;
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_7;
} field_storage_t;
field_storage_t field_storage;
- // Field: hyperbus_cfg_regs.t_latency_access.value
+ assign hwif_out.global_cfg.ip_version.revision.value = 8'h0;
+ assign hwif_out.global_cfg.ip_version.patch.value = 8'h9;
+ assign hwif_out.global_cfg.ip_version.minor.value = 8'h0;
+ assign hwif_out.global_cfg.ip_version.major.value = 8'h0;
+ assign hwif_out.global_cfg.reg_if_version.minor.value = 16'h0;
+ assign hwif_out.global_cfg.reg_if_version.major.value = 16'h1;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.num_chips
always_comb begin
- automatic logic [3:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.t_latency_access.value.value;
+ next_c = field_storage.global_cfg.capability.num_chips.value;
load_next_c = '0;
- if(decoded_reg_strb.t_latency_access && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.t_latency_access.value.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]);
- load_next_c = '1;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.num_chips.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.num_chips.next = next_c;
+ field_combo.global_cfg.capability.num_chips.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.num_chips.value <= 8'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.num_chips.load_next) begin
+ field_storage.global_cfg.capability.num_chips.value <= field_combo.global_cfg.capability.num_chips.next;
+ end
end
- field_combo.t_latency_access.value.next = next_c;
- field_combo.t_latency_access.value.load_next = load_next_c;
+ end
+ assign hwif_out.global_cfg.capability.num_chips.value = field_storage.global_cfg.capability.num_chips.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.num_phys
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.num_phys.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.num_phys.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.num_phys.next = next_c;
+ field_combo.global_cfg.capability.num_phys.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.t_latency_access.value.value <= 4'h6;
+ field_storage.global_cfg.capability.num_phys.value <= 8'h0;
end else begin
- if(field_combo.t_latency_access.value.load_next) begin
- field_storage.t_latency_access.value.value <= field_combo.t_latency_access.value.next;
+ if(field_combo.global_cfg.capability.num_phys.load_next) begin
+ field_storage.global_cfg.capability.num_phys.value <= field_combo.global_cfg.capability.num_phys.next;
end
end
end
- assign hwif_out.t_latency_access.value.value = field_storage.t_latency_access.value.value;
- // Field: hyperbus_cfg_regs.en_latency_additional.value
+ assign hwif_out.global_cfg.capability.num_phys.value = field_storage.global_cfg.capability.num_phys.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.per_chip_cfg
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.en_latency_additional.value.value;
+ next_c = field_storage.global_cfg.capability.per_chip_cfg.value;
load_next_c = '0;
- if(decoded_reg_strb.en_latency_additional && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.en_latency_additional.value.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
- load_next_c = '1;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.per_chip_cfg.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.per_chip_cfg.next = next_c;
+ field_combo.global_cfg.capability.per_chip_cfg.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.per_chip_cfg.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.per_chip_cfg.load_next) begin
+ field_storage.global_cfg.capability.per_chip_cfg.value <= field_combo.global_cfg.capability.per_chip_cfg.next;
+ end
end
- field_combo.en_latency_additional.value.next = next_c;
- field_combo.en_latency_additional.value.load_next = load_next_c;
+ end
+ assign hwif_out.global_cfg.capability.per_chip_cfg.value = field_storage.global_cfg.capability.per_chip_cfg.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.per_phy_cfg
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.per_phy_cfg.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.per_phy_cfg.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.per_phy_cfg.next = next_c;
+ field_combo.global_cfg.capability.per_phy_cfg.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.en_latency_additional.value.value <= 1'h0;
+ field_storage.global_cfg.capability.per_phy_cfg.value <= 1'h0;
end else begin
- if(field_combo.en_latency_additional.value.load_next) begin
- field_storage.en_latency_additional.value.value <= field_combo.en_latency_additional.value.next;
+ if(field_combo.global_cfg.capability.per_phy_cfg.load_next) begin
+ field_storage.global_cfg.capability.per_phy_cfg.value <= field_combo.global_cfg.capability.per_phy_cfg.next;
end
end
end
- assign hwif_out.en_latency_additional.value.value = field_storage.en_latency_additional.value.value;
- // Field: hyperbus_cfg_regs.t_burst_max.value
+ assign hwif_out.global_cfg.capability.per_phy_cfg.value = field_storage.global_cfg.capability.per_phy_cfg.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.chip_enable
always_comb begin
- automatic logic [15:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.t_burst_max.value.value;
+ next_c = field_storage.global_cfg.capability.chip_enable.value;
load_next_c = '0;
- if(decoded_reg_strb.t_burst_max && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.t_burst_max.value.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
- load_next_c = '1;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.chip_enable.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.chip_enable.next = next_c;
+ field_combo.global_cfg.capability.chip_enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.chip_enable.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.chip_enable.load_next) begin
+ field_storage.global_cfg.capability.chip_enable.value <= field_combo.global_cfg.capability.chip_enable.next;
+ end
end
- field_combo.t_burst_max.value.next = next_c;
- field_combo.t_burst_max.value.load_next = load_next_c;
+ end
+ assign hwif_out.global_cfg.capability.chip_enable.value = field_storage.global_cfg.capability.chip_enable.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.clock_divider
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.clock_divider.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.clock_divider.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.clock_divider.next = next_c;
+ field_combo.global_cfg.capability.clock_divider.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.t_burst_max.value.value <= 16'h15e;
+ field_storage.global_cfg.capability.clock_divider.value <= 1'h0;
end else begin
- if(field_combo.t_burst_max.value.load_next) begin
- field_storage.t_burst_max.value.value <= field_combo.t_burst_max.value.next;
+ if(field_combo.global_cfg.capability.clock_divider.load_next) begin
+ field_storage.global_cfg.capability.clock_divider.value <= field_combo.global_cfg.capability.clock_divider.next;
end
end
end
- assign hwif_out.t_burst_max.value.value = field_storage.t_burst_max.value.value;
- // Field: hyperbus_cfg_regs.t_read_write_recovery.value
+ assign hwif_out.global_cfg.capability.clock_divider.value = field_storage.global_cfg.capability.clock_divider.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.staged_apply
always_comb begin
- automatic logic [3:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.t_read_write_recovery.value.value;
+ next_c = field_storage.global_cfg.capability.staged_apply.value;
load_next_c = '0;
- if(decoded_reg_strb.t_read_write_recovery && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.t_read_write_recovery.value.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]);
- load_next_c = '1;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.staged_apply.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.staged_apply.next = next_c;
+ field_combo.global_cfg.capability.staged_apply.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.staged_apply.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.staged_apply.load_next) begin
+ field_storage.global_cfg.capability.staged_apply.value <= field_combo.global_cfg.capability.staged_apply.next;
+ end
end
- field_combo.t_read_write_recovery.value.next = next_c;
- field_combo.t_read_write_recovery.value.load_next = load_next_c;
+ end
+ assign hwif_out.global_cfg.capability.staged_apply.value = field_storage.global_cfg.capability.staged_apply.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.error_status
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.error_status.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.error_status.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.error_status.next = next_c;
+ field_combo.global_cfg.capability.error_status.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.t_read_write_recovery.value.value <= 4'h6;
+ field_storage.global_cfg.capability.error_status.value <= 1'h0;
end else begin
- if(field_combo.t_read_write_recovery.value.load_next) begin
- field_storage.t_read_write_recovery.value.value <= field_combo.t_read_write_recovery.value.next;
+ if(field_combo.global_cfg.capability.error_status.load_next) begin
+ field_storage.global_cfg.capability.error_status.value <= field_combo.global_cfg.capability.error_status.next;
end
end
end
- assign hwif_out.t_read_write_recovery.value.value = field_storage.t_read_write_recovery.value.value;
- // Field: hyperbus_cfg_regs.t_rx_clk_delay.fine
+ assign hwif_out.global_cfg.capability.error_status.value = field_storage.global_cfg.capability.error_status.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.rwds_sample_timing
always_comb begin
- automatic logic [4:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.t_rx_clk_delay.fine.value;
+ next_c = field_storage.global_cfg.capability.rwds_sample_timing.value;
load_next_c = '0;
- if(decoded_reg_strb.t_rx_clk_delay && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.t_rx_clk_delay.fine.value & ~decoded_wr_biten[4:0]) | (decoded_wr_data[4:0] & decoded_wr_biten[4:0]);
- load_next_c = '1;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.rwds_sample_timing.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.rwds_sample_timing.next = next_c;
+ field_combo.global_cfg.capability.rwds_sample_timing.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.rwds_sample_timing.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.rwds_sample_timing.load_next) begin
+ field_storage.global_cfg.capability.rwds_sample_timing.value <= field_combo.global_cfg.capability.rwds_sample_timing.next;
+ end
end
- field_combo.t_rx_clk_delay.fine.next = next_c;
- field_combo.t_rx_clk_delay.fine.load_next = load_next_c;
+ end
+ assign hwif_out.global_cfg.capability.rwds_sample_timing.value = field_storage.global_cfg.capability.rwds_sample_timing.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.rwds_oe_timing
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.rwds_oe_timing.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.rwds_oe_timing.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.rwds_oe_timing.next = next_c;
+ field_combo.global_cfg.capability.rwds_oe_timing.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.t_rx_clk_delay.fine.value <= 5'h10;
+ field_storage.global_cfg.capability.rwds_oe_timing.value <= 1'h0;
end else begin
- if(field_combo.t_rx_clk_delay.fine.load_next) begin
- field_storage.t_rx_clk_delay.fine.value <= field_combo.t_rx_clk_delay.fine.next;
+ if(field_combo.global_cfg.capability.rwds_oe_timing.load_next) begin
+ field_storage.global_cfg.capability.rwds_oe_timing.value <= field_combo.global_cfg.capability.rwds_oe_timing.next;
end
end
end
- assign hwif_out.t_rx_clk_delay.fine.value = field_storage.t_rx_clk_delay.fine.value;
- // Field: hyperbus_cfg_regs.t_rx_clk_delay.coarse
+ assign hwif_out.global_cfg.capability.rwds_oe_timing.value = field_storage.global_cfg.capability.rwds_oe_timing.value;
+ // Field: hyperbus_cfg_regs.global_cfg.command.flush
always_comb begin
- automatic logic [2:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.t_rx_clk_delay.coarse.value;
+ next_c = field_storage.global_cfg.command.flush.value;
load_next_c = '0;
- if(decoded_reg_strb.t_rx_clk_delay && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.t_rx_clk_delay.coarse.value & ~decoded_wr_biten[7:5]) | (decoded_wr_data[7:5] & decoded_wr_biten[7:5]);
+ if(decoded_reg_strb.global_cfg.command && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.global_cfg.command.flush.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end else begin // singlepulse clears back to 0
+ next_c = '0;
load_next_c = '1;
end
- field_combo.t_rx_clk_delay.coarse.next = next_c;
- field_combo.t_rx_clk_delay.coarse.load_next = load_next_c;
+ field_combo.global_cfg.command.flush.next = next_c;
+ field_combo.global_cfg.command.flush.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.t_rx_clk_delay.coarse.value <= 3'h0;
+ field_storage.global_cfg.command.flush.value <= 1'h0;
end else begin
- if(field_combo.t_rx_clk_delay.coarse.load_next) begin
- field_storage.t_rx_clk_delay.coarse.value <= field_combo.t_rx_clk_delay.coarse.next;
+ if(field_combo.global_cfg.command.flush.load_next) begin
+ field_storage.global_cfg.command.flush.value <= field_combo.global_cfg.command.flush.next;
end
end
end
- assign hwif_out.t_rx_clk_delay.coarse.value = field_storage.t_rx_clk_delay.coarse.value;
- // Field: hyperbus_cfg_regs.t_tx_clk_delay.fine
+ assign hwif_out.global_cfg.command.flush.value = field_storage.global_cfg.command.flush.value;
+ // Field: hyperbus_cfg_regs.global_cfg.command.apply
always_comb begin
- automatic logic [4:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.t_tx_clk_delay.fine.value;
+ next_c = field_storage.global_cfg.command.apply.value;
load_next_c = '0;
- if(decoded_reg_strb.t_tx_clk_delay && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.t_tx_clk_delay.fine.value & ~decoded_wr_biten[4:0]) | (decoded_wr_data[4:0] & decoded_wr_biten[4:0]);
+ if(decoded_reg_strb.global_cfg.command && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.global_cfg.command.apply.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
+ load_next_c = '1;
+ end else begin // singlepulse clears back to 0
+ next_c = '0;
load_next_c = '1;
end
- field_combo.t_tx_clk_delay.fine.next = next_c;
- field_combo.t_tx_clk_delay.fine.load_next = load_next_c;
+ field_combo.global_cfg.command.apply.next = next_c;
+ field_combo.global_cfg.command.apply.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.t_tx_clk_delay.fine.value <= 5'h10;
+ field_storage.global_cfg.command.apply.value <= 1'h0;
end else begin
- if(field_combo.t_tx_clk_delay.fine.load_next) begin
- field_storage.t_tx_clk_delay.fine.value <= field_combo.t_tx_clk_delay.fine.next;
+ if(field_combo.global_cfg.command.apply.load_next) begin
+ field_storage.global_cfg.command.apply.value <= field_combo.global_cfg.command.apply.next;
end
end
end
- assign hwif_out.t_tx_clk_delay.fine.value = field_storage.t_tx_clk_delay.fine.value;
- // Field: hyperbus_cfg_regs.t_tx_clk_delay.coarse
+ assign hwif_out.global_cfg.command.apply.value = field_storage.global_cfg.command.apply.value;
+ // Field: hyperbus_cfg_regs.global_cfg.status.decode_error
always_comb begin
- automatic logic [2:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.t_tx_clk_delay.coarse.value;
+ next_c = field_storage.global_cfg.status.decode_error.value;
load_next_c = '0;
- if(decoded_reg_strb.t_tx_clk_delay && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.t_tx_clk_delay.coarse.value & ~decoded_wr_biten[7:5]) | (decoded_wr_data[7:5] & decoded_wr_biten[7:5]);
+ if(hwif_in.global_cfg.status.decode_error.hwset) begin // HW Set
+ next_c = '1;
+ load_next_c = '1;
+ end else if(decoded_reg_strb.global_cfg.status && decoded_req_is_wr) begin // SW write 1 clear
+ next_c = field_storage.global_cfg.status.decode_error.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end else begin // HW Write
+ next_c = hwif_in.global_cfg.status.decode_error.next;
load_next_c = '1;
end
- field_combo.t_tx_clk_delay.coarse.next = next_c;
- field_combo.t_tx_clk_delay.coarse.load_next = load_next_c;
+ field_combo.global_cfg.status.decode_error.next = next_c;
+ field_combo.global_cfg.status.decode_error.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.t_tx_clk_delay.coarse.value <= 3'h0;
+ field_storage.global_cfg.status.decode_error.value <= 1'h0;
end else begin
- if(field_combo.t_tx_clk_delay.coarse.load_next) begin
- field_storage.t_tx_clk_delay.coarse.value <= field_combo.t_tx_clk_delay.coarse.next;
+ if(field_combo.global_cfg.status.decode_error.load_next) begin
+ field_storage.global_cfg.status.decode_error.value <= field_combo.global_cfg.status.decode_error.next;
end
end
end
- assign hwif_out.t_tx_clk_delay.coarse.value = field_storage.t_tx_clk_delay.coarse.value;
- // Field: hyperbus_cfg_regs.address_mask_msb.value
+ assign hwif_out.global_cfg.status.decode_error.value = field_storage.global_cfg.status.decode_error.value;
+ // Field: hyperbus_cfg_regs.global_cfg.status.busy
always_comb begin
- automatic logic [4:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.address_mask_msb.value.value;
+ next_c = field_storage.global_cfg.status.busy.value;
load_next_c = '0;
- if(decoded_reg_strb.address_mask_msb && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.address_mask_msb.value.value & ~decoded_wr_biten[4:0]) | (decoded_wr_data[4:0] & decoded_wr_biten[4:0]);
- load_next_c = '1;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.status.busy.next;
+ load_next_c = '1;
+ field_combo.global_cfg.status.busy.next = next_c;
+ field_combo.global_cfg.status.busy.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.status.busy.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.status.busy.load_next) begin
+ field_storage.global_cfg.status.busy.value <= field_combo.global_cfg.status.busy.next;
+ end
end
- field_combo.address_mask_msb.value.next = next_c;
- field_combo.address_mask_msb.value.load_next = load_next_c;
+ end
+ assign hwif_out.global_cfg.status.busy.value = field_storage.global_cfg.status.busy.value;
+ // Field: hyperbus_cfg_regs.global_cfg.status.dirty
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.status.dirty.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.status.dirty.next;
+ load_next_c = '1;
+ field_combo.global_cfg.status.dirty.next = next_c;
+ field_combo.global_cfg.status.dirty.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.address_mask_msb.value.value <= 5'h19;
+ field_storage.global_cfg.status.dirty.value <= 1'h0;
end else begin
- if(field_combo.address_mask_msb.value.load_next) begin
- field_storage.address_mask_msb.value.value <= field_combo.address_mask_msb.value.next;
+ if(field_combo.global_cfg.status.dirty.load_next) begin
+ field_storage.global_cfg.status.dirty.value <= field_combo.global_cfg.status.dirty.next;
end
end
end
- assign hwif_out.address_mask_msb.value.value = field_storage.address_mask_msb.value.value;
- // Field: hyperbus_cfg_regs.address_space.value
+ assign hwif_out.global_cfg.status.dirty.value = field_storage.global_cfg.status.dirty.value;
+ // Field: hyperbus_cfg_regs.frontend.frontend_cfg.dual_phy
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.address_space.value.value;
+ next_c = field_storage.frontend.frontend_cfg.dual_phy.value;
load_next_c = '0;
- if(decoded_reg_strb.address_space && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.address_space.value.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ if(decoded_reg_strb.frontend.frontend_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.frontend.frontend_cfg.dual_phy.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1;
end
- field_combo.address_space.value.next = next_c;
- field_combo.address_space.value.load_next = load_next_c;
+ field_combo.frontend.frontend_cfg.dual_phy.next = next_c;
+ field_combo.frontend.frontend_cfg.dual_phy.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.address_space.value.value <= 1'h0;
+ field_storage.frontend.frontend_cfg.dual_phy.value <= 1'h1;
end else begin
- if(field_combo.address_space.value.load_next) begin
- field_storage.address_space.value.value <= field_combo.address_space.value.next;
+ if(field_combo.frontend.frontend_cfg.dual_phy.load_next) begin
+ field_storage.frontend.frontend_cfg.dual_phy.value <= field_combo.frontend.frontend_cfg.dual_phy.next;
end
end
end
- assign hwif_out.address_space.value.value = field_storage.address_space.value.value;
- // Field: hyperbus_cfg_regs.phys_in_use.value
+ assign hwif_out.frontend.frontend_cfg.dual_phy.value = field_storage.frontend.frontend_cfg.dual_phy.value;
+ // Field: hyperbus_cfg_regs.backend.clock_cfg.divider
always_comb begin
- automatic logic [0:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.phys_in_use.value.value;
+ next_c = field_storage.backend.clock_cfg.divider.value;
load_next_c = '0;
- if(decoded_reg_strb.phys_in_use && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.phys_in_use.value.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ if(decoded_reg_strb.backend.clock_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.backend.clock_cfg.divider.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
load_next_c = '1;
end
- field_combo.phys_in_use.value.next = next_c;
- field_combo.phys_in_use.value.load_next = load_next_c;
+ field_combo.backend.clock_cfg.divider.next = next_c;
+ field_combo.backend.clock_cfg.divider.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.phys_in_use.value.value <= 1'h1;
+ field_storage.backend.clock_cfg.divider.value <= 8'h8;
end else begin
- if(field_combo.phys_in_use.value.load_next) begin
- field_storage.phys_in_use.value.value <= field_combo.phys_in_use.value.next;
+ if(field_combo.backend.clock_cfg.divider.load_next) begin
+ field_storage.backend.clock_cfg.divider.value <= field_combo.backend.clock_cfg.divider.next;
end
end
end
- assign hwif_out.phys_in_use.value.value = field_storage.phys_in_use.value.value;
- // Field: hyperbus_cfg_regs.which_phy.value
+ assign hwif_out.backend.clock_cfg.divider.value = field_storage.backend.clock_cfg.divider.value;
+ // Field: hyperbus_cfg_regs.phy_0.tx_delay.value
always_comb begin
- automatic logic [0:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.which_phy.value.value;
+ next_c = field_storage.phy_0.tx_delay.value.value;
load_next_c = '0;
- if(decoded_reg_strb.which_phy && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.which_phy.value.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ if(decoded_reg_strb.phy_0.tx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.phy_0.tx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
load_next_c = '1;
end
- field_combo.which_phy.value.next = next_c;
- field_combo.which_phy.value.load_next = load_next_c;
+ field_combo.phy_0.tx_delay.value.next = next_c;
+ field_combo.phy_0.tx_delay.value.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.which_phy.value.value <= 1'h1;
+ field_storage.phy_0.tx_delay.value.value <= 8'h10;
end else begin
- if(field_combo.which_phy.value.load_next) begin
- field_storage.which_phy.value.value <= field_combo.which_phy.value.next;
+ if(field_combo.phy_0.tx_delay.value.load_next) begin
+ field_storage.phy_0.tx_delay.value.value <= field_combo.phy_0.tx_delay.value.next;
end
end
end
- assign hwif_out.which_phy.value.value = field_storage.which_phy.value.value;
- // Field: hyperbus_cfg_regs.t_csh_cycles.value
+ assign hwif_out.phy_0.tx_delay.value.value = field_storage.phy_0.tx_delay.value.value;
+ // Field: hyperbus_cfg_regs.phy_0.rwds_timing.rwds_oe_setup_cycles
always_comb begin
- automatic logic [3:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.t_csh_cycles.value.value;
+ next_c = field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value;
load_next_c = '0;
- if(decoded_reg_strb.t_csh_cycles && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.t_csh_cycles.value.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]);
+ if(decoded_reg_strb.phy_0.rwds_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
load_next_c = '1;
end
- field_combo.t_csh_cycles.value.next = next_c;
- field_combo.t_csh_cycles.value.load_next = load_next_c;
+ field_combo.phy_0.rwds_timing.rwds_oe_setup_cycles.next = next_c;
+ field_combo.phy_0.rwds_timing.rwds_oe_setup_cycles.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.t_csh_cycles.value.value <= 4'h1;
+ field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value <= 8'h1;
end else begin
- if(field_combo.t_csh_cycles.value.load_next) begin
- field_storage.t_csh_cycles.value.value <= field_combo.t_csh_cycles.value.next;
+ if(field_combo.phy_0.rwds_timing.rwds_oe_setup_cycles.load_next) begin
+ field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value <= field_combo.phy_0.rwds_timing.rwds_oe_setup_cycles.next;
end
end
end
- assign hwif_out.t_csh_cycles.value.value = field_storage.t_csh_cycles.value.value;
- // Field: hyperbus_cfg_regs.csn_to_ck_cycles.value
+ assign hwif_out.phy_0.rwds_timing.rwds_oe_setup_cycles.value = field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value;
+ // Field: hyperbus_cfg_regs.phy_1.tx_delay.value
always_comb begin
- automatic logic [3:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.csn_to_ck_cycles.value.value;
+ next_c = field_storage.phy_1.tx_delay.value.value;
load_next_c = '0;
- if(decoded_reg_strb.csn_to_ck_cycles && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.csn_to_ck_cycles.value.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]);
+ if(decoded_reg_strb.phy_1.tx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.phy_1.tx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
load_next_c = '1;
end
- field_combo.csn_to_ck_cycles.value.next = next_c;
- field_combo.csn_to_ck_cycles.value.load_next = load_next_c;
+ field_combo.phy_1.tx_delay.value.next = next_c;
+ field_combo.phy_1.tx_delay.value.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.csn_to_ck_cycles.value.value <= 4'h0;
+ field_storage.phy_1.tx_delay.value.value <= 8'h10;
end else begin
- if(field_combo.csn_to_ck_cycles.value.load_next) begin
- field_storage.csn_to_ck_cycles.value.value <= field_combo.csn_to_ck_cycles.value.next;
+ if(field_combo.phy_1.tx_delay.value.load_next) begin
+ field_storage.phy_1.tx_delay.value.value <= field_combo.phy_1.tx_delay.value.next;
end
end
end
- assign hwif_out.csn_to_ck_cycles.value.value = field_storage.csn_to_ck_cycles.value.value;
- // Field: hyperbus_cfg_regs.chip0_base.value
+ assign hwif_out.phy_1.tx_delay.value.value = field_storage.phy_1.tx_delay.value.value;
+ // Field: hyperbus_cfg_regs.phy_1.rwds_timing.rwds_oe_setup_cycles
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip0_base.value.value;
+ next_c = field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value;
load_next_c = '0;
- if(decoded_reg_strb.chip0_base && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip0_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.phy_1.rwds_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
load_next_c = '1;
end
- field_combo.chip0_base.value.next = next_c;
- field_combo.chip0_base.value.load_next = load_next_c;
+ field_combo.phy_1.rwds_timing.rwds_oe_setup_cycles.next = next_c;
+ field_combo.phy_1.rwds_timing.rwds_oe_setup_cycles.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip0_base.value.value <= 10'h0;
+ field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value <= 8'h1;
end else begin
- if(field_combo.chip0_base.value.load_next) begin
- field_storage.chip0_base.value.value <= field_combo.chip0_base.value.next;
+ if(field_combo.phy_1.rwds_timing.rwds_oe_setup_cycles.load_next) begin
+ field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value <= field_combo.phy_1.rwds_timing.rwds_oe_setup_cycles.next;
end
end
end
- assign hwif_out.chip0_base.value.value = field_storage.chip0_base.value.value;
- // Field: hyperbus_cfg_regs.chip0_bound.value
+ assign hwif_out.phy_1.rwds_timing.rwds_oe_setup_cycles.value = field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_0.range_base.value
always_comb begin
automatic logic [9:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip0_bound.value.value;
+ next_c = field_storage.chip_0.range_base.value.value;
load_next_c = '0;
- if(decoded_reg_strb.chip0_bound && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip0_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
load_next_c = '1;
end
- field_combo.chip0_bound.value.next = next_c;
- field_combo.chip0_bound.value.load_next = load_next_c;
+ field_combo.chip_0.range_base.value.next = next_c;
+ field_combo.chip_0.range_base.value.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip0_bound.value.value <= 10'h1;
+ field_storage.chip_0.range_base.value.value <= 10'h0;
end else begin
- if(field_combo.chip0_bound.value.load_next) begin
- field_storage.chip0_bound.value.value <= field_combo.chip0_bound.value.next;
+ if(field_combo.chip_0.range_base.value.load_next) begin
+ field_storage.chip_0.range_base.value.value <= field_combo.chip_0.range_base.value.next;
end
end
end
- assign hwif_out.chip0_bound.value.value = field_storage.chip0_bound.value.value;
- // Field: hyperbus_cfg_regs.chip1_base.value
+ assign hwif_out.chip_0.range_base.value.value = field_storage.chip_0.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_0.range_bound.value
always_comb begin
automatic logic [9:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip1_base.value.value;
+ next_c = field_storage.chip_0.range_bound.value.value;
load_next_c = '0;
- if(decoded_reg_strb.chip1_base && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip1_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
load_next_c = '1;
end
- field_combo.chip1_base.value.next = next_c;
- field_combo.chip1_base.value.load_next = load_next_c;
+ field_combo.chip_0.range_bound.value.next = next_c;
+ field_combo.chip_0.range_bound.value.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip1_base.value.value <= 10'h1;
+ field_storage.chip_0.range_bound.value.value <= 10'h1;
end else begin
- if(field_combo.chip1_base.value.load_next) begin
- field_storage.chip1_base.value.value <= field_combo.chip1_base.value.next;
+ if(field_combo.chip_0.range_bound.value.load_next) begin
+ field_storage.chip_0.range_bound.value.value <= field_combo.chip_0.range_bound.value.next;
end
end
end
- assign hwif_out.chip1_base.value.value = field_storage.chip1_base.value.value;
- // Field: hyperbus_cfg_regs.chip1_bound.value
+ assign hwif_out.chip_0.range_bound.value.value = field_storage.chip_0.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_0.address_cfg.address_space
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip1_bound.value.value;
+ next_c = field_storage.chip_0.address_cfg.address_space.value;
load_next_c = '0;
- if(decoded_reg_strb.chip1_bound && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip1_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
load_next_c = '1;
end
- field_combo.chip1_bound.value.next = next_c;
- field_combo.chip1_bound.value.load_next = load_next_c;
+ field_combo.chip_0.address_cfg.address_space.next = next_c;
+ field_combo.chip_0.address_cfg.address_space.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip1_bound.value.value <= 10'h2;
+ field_storage.chip_0.address_cfg.address_space.value <= 8'h0;
end else begin
- if(field_combo.chip1_bound.value.load_next) begin
- field_storage.chip1_bound.value.value <= field_combo.chip1_bound.value.next;
+ if(field_combo.chip_0.address_cfg.address_space.load_next) begin
+ field_storage.chip_0.address_cfg.address_space.value <= field_combo.chip_0.address_cfg.address_space.next;
end
end
end
- assign hwif_out.chip1_bound.value.value = field_storage.chip1_bound.value.value;
- // Field: hyperbus_cfg_regs.chip2_base.value
+ assign hwif_out.chip_0.address_cfg.address_space.value = field_storage.chip_0.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_0.address_cfg.address_mask_msb
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip2_base.value.value;
+ next_c = field_storage.chip_0.address_cfg.address_mask_msb.value;
load_next_c = '0;
- if(decoded_reg_strb.chip2_base && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip2_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
load_next_c = '1;
end
- field_combo.chip2_base.value.next = next_c;
- field_combo.chip2_base.value.load_next = load_next_c;
+ field_combo.chip_0.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_0.address_cfg.address_mask_msb.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip2_base.value.value <= 10'h2;
+ field_storage.chip_0.address_cfg.address_mask_msb.value <= 8'h19;
end else begin
- if(field_combo.chip2_base.value.load_next) begin
- field_storage.chip2_base.value.value <= field_combo.chip2_base.value.next;
+ if(field_combo.chip_0.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_0.address_cfg.address_mask_msb.value <= field_combo.chip_0.address_cfg.address_mask_msb.next;
end
end
end
- assign hwif_out.chip2_base.value.value = field_storage.chip2_base.value.value;
- // Field: hyperbus_cfg_regs.chip2_bound.value
+ assign hwif_out.chip_0.address_cfg.address_mask_msb.value = field_storage.chip_0.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_0.address_cfg.enable
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip2_bound.value.value;
+ next_c = field_storage.chip_0.address_cfg.enable.value;
load_next_c = '0;
- if(decoded_reg_strb.chip2_bound && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip2_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
load_next_c = '1;
end
- field_combo.chip2_bound.value.next = next_c;
- field_combo.chip2_bound.value.load_next = load_next_c;
+ field_combo.chip_0.address_cfg.enable.next = next_c;
+ field_combo.chip_0.address_cfg.enable.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip2_bound.value.value <= 10'h3;
+ field_storage.chip_0.address_cfg.enable.value <= 1'h1;
end else begin
- if(field_combo.chip2_bound.value.load_next) begin
- field_storage.chip2_bound.value.value <= field_combo.chip2_bound.value.next;
+ if(field_combo.chip_0.address_cfg.enable.load_next) begin
+ field_storage.chip_0.address_cfg.enable.value <= field_combo.chip_0.address_cfg.enable.next;
end
end
end
- assign hwif_out.chip2_bound.value.value = field_storage.chip2_bound.value.value;
- // Field: hyperbus_cfg_regs.chip3_base.value
+ assign hwif_out.chip_0.address_cfg.enable.value = field_storage.chip_0.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_0.latency_cfg.t_latency_access
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip3_base.value.value;
+ next_c = field_storage.chip_0.latency_cfg.t_latency_access.value;
load_next_c = '0;
- if(decoded_reg_strb.chip3_base && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip3_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
load_next_c = '1;
end
- field_combo.chip3_base.value.next = next_c;
- field_combo.chip3_base.value.load_next = load_next_c;
+ field_combo.chip_0.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_0.latency_cfg.t_latency_access.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip3_base.value.value <= 10'h3;
+ field_storage.chip_0.latency_cfg.t_latency_access.value <= 8'h6;
end else begin
- if(field_combo.chip3_base.value.load_next) begin
- field_storage.chip3_base.value.value <= field_combo.chip3_base.value.next;
+ if(field_combo.chip_0.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_0.latency_cfg.t_latency_access.value <= field_combo.chip_0.latency_cfg.t_latency_access.next;
end
end
end
- assign hwif_out.chip3_base.value.value = field_storage.chip3_base.value.value;
- // Field: hyperbus_cfg_regs.chip3_bound.value
+ assign hwif_out.chip_0.latency_cfg.t_latency_access.value = field_storage.chip_0.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_0.latency_cfg.rwds_sample_delay
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip3_bound.value.value;
+ next_c = field_storage.chip_0.latency_cfg.rwds_sample_delay.value;
load_next_c = '0;
- if(decoded_reg_strb.chip3_bound && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip3_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
load_next_c = '1;
end
- field_combo.chip3_bound.value.next = next_c;
- field_combo.chip3_bound.value.load_next = load_next_c;
+ field_combo.chip_0.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_0.latency_cfg.rwds_sample_delay.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip3_bound.value.value <= 10'h4;
+ field_storage.chip_0.latency_cfg.rwds_sample_delay.value <= 8'h0;
end else begin
- if(field_combo.chip3_bound.value.load_next) begin
- field_storage.chip3_bound.value.value <= field_combo.chip3_bound.value.next;
+ if(field_combo.chip_0.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_0.latency_cfg.rwds_sample_delay.value <= field_combo.chip_0.latency_cfg.rwds_sample_delay.next;
end
end
end
- assign hwif_out.chip3_bound.value.value = field_storage.chip3_bound.value.value;
- // Field: hyperbus_cfg_regs.chip4_base.value
+ assign hwif_out.chip_0.latency_cfg.rwds_sample_delay.value = field_storage.chip_0.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_0.latency_cfg.en_latency_additional
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip4_base.value.value;
+ next_c = field_storage.chip_0.latency_cfg.en_latency_additional.value;
load_next_c = '0;
- if(decoded_reg_strb.chip4_base && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip4_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
load_next_c = '1;
end
- field_combo.chip4_base.value.next = next_c;
- field_combo.chip4_base.value.load_next = load_next_c;
+ field_combo.chip_0.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_0.latency_cfg.en_latency_additional.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip4_base.value.value <= 10'h4;
+ field_storage.chip_0.latency_cfg.en_latency_additional.value <= 1'h0;
end else begin
- if(field_combo.chip4_base.value.load_next) begin
- field_storage.chip4_base.value.value <= field_combo.chip4_base.value.next;
+ if(field_combo.chip_0.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_0.latency_cfg.en_latency_additional.value <= field_combo.chip_0.latency_cfg.en_latency_additional.next;
end
end
end
- assign hwif_out.chip4_base.value.value = field_storage.chip4_base.value.value;
- // Field: hyperbus_cfg_regs.chip4_bound.value
+ assign hwif_out.chip_0.latency_cfg.en_latency_additional.value = field_storage.chip_0.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_0.burst_cfg.t_burst_max
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [15:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip4_bound.value.value;
+ next_c = field_storage.chip_0.burst_cfg.t_burst_max.value;
load_next_c = '0;
- if(decoded_reg_strb.chip4_bound && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip4_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
load_next_c = '1;
end
- field_combo.chip4_bound.value.next = next_c;
- field_combo.chip4_bound.value.load_next = load_next_c;
+ field_combo.chip_0.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_0.burst_cfg.t_burst_max.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip4_bound.value.value <= 10'h5;
+ field_storage.chip_0.burst_cfg.t_burst_max.value <= 16'h15e;
end else begin
- if(field_combo.chip4_bound.value.load_next) begin
- field_storage.chip4_bound.value.value <= field_combo.chip4_bound.value.next;
+ if(field_combo.chip_0.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_0.burst_cfg.t_burst_max.value <= field_combo.chip_0.burst_cfg.t_burst_max.next;
end
end
end
- assign hwif_out.chip4_bound.value.value = field_storage.chip4_bound.value.value;
- // Field: hyperbus_cfg_regs.chip5_base.value
+ assign hwif_out.chip_0.burst_cfg.t_burst_max.value = field_storage.chip_0.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_0.chip_timing.t_read_write_recovery
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip5_base.value.value;
+ next_c = field_storage.chip_0.chip_timing.t_read_write_recovery.value;
load_next_c = '0;
- if(decoded_reg_strb.chip5_base && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip5_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
load_next_c = '1;
end
- field_combo.chip5_base.value.next = next_c;
- field_combo.chip5_base.value.load_next = load_next_c;
+ field_combo.chip_0.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_0.chip_timing.t_read_write_recovery.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip5_base.value.value <= 10'h5;
+ field_storage.chip_0.chip_timing.t_read_write_recovery.value <= 8'h6;
end else begin
- if(field_combo.chip5_base.value.load_next) begin
- field_storage.chip5_base.value.value <= field_combo.chip5_base.value.next;
+ if(field_combo.chip_0.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_0.chip_timing.t_read_write_recovery.value <= field_combo.chip_0.chip_timing.t_read_write_recovery.next;
end
end
end
- assign hwif_out.chip5_base.value.value = field_storage.chip5_base.value.value;
- // Field: hyperbus_cfg_regs.chip5_bound.value
+ assign hwif_out.chip_0.chip_timing.t_read_write_recovery.value = field_storage.chip_0.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_0.chip_timing.t_csh_cycles
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip5_bound.value.value;
+ next_c = field_storage.chip_0.chip_timing.t_csh_cycles.value;
load_next_c = '0;
- if(decoded_reg_strb.chip5_bound && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip5_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
load_next_c = '1;
end
- field_combo.chip5_bound.value.next = next_c;
- field_combo.chip5_bound.value.load_next = load_next_c;
+ field_combo.chip_0.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_0.chip_timing.t_csh_cycles.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip5_bound.value.value <= 10'h6;
+ field_storage.chip_0.chip_timing.t_csh_cycles.value <= 8'h1;
end else begin
- if(field_combo.chip5_bound.value.load_next) begin
- field_storage.chip5_bound.value.value <= field_combo.chip5_bound.value.next;
+ if(field_combo.chip_0.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_0.chip_timing.t_csh_cycles.value <= field_combo.chip_0.chip_timing.t_csh_cycles.next;
end
end
end
- assign hwif_out.chip5_bound.value.value = field_storage.chip5_bound.value.value;
- // Field: hyperbus_cfg_regs.chip6_base.value
+ assign hwif_out.chip_0.chip_timing.t_csh_cycles.value = field_storage.chip_0.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_0.chip_timing.csn_to_ck_cycles
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip6_base.value.value;
+ next_c = field_storage.chip_0.chip_timing.csn_to_ck_cycles.value;
load_next_c = '0;
- if(decoded_reg_strb.chip6_base && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip6_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
load_next_c = '1;
end
- field_combo.chip6_base.value.next = next_c;
- field_combo.chip6_base.value.load_next = load_next_c;
+ field_combo.chip_0.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_0.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip6_base.value.value <= 10'h6;
+ field_storage.chip_0.chip_timing.csn_to_ck_cycles.value <= 8'h0;
end else begin
- if(field_combo.chip6_base.value.load_next) begin
- field_storage.chip6_base.value.value <= field_combo.chip6_base.value.next;
+ if(field_combo.chip_0.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_0.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_0.chip_timing.csn_to_ck_cycles.next;
end
end
end
- assign hwif_out.chip6_base.value.value = field_storage.chip6_base.value.value;
- // Field: hyperbus_cfg_regs.chip6_bound.value
+ assign hwif_out.chip_0.chip_timing.csn_to_ck_cycles.value = field_storage.chip_0.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_0.rx_delay.value
always_comb begin
- automatic logic [9:0] next_c;
+ automatic logic [7:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip6_bound.value.value;
+ next_c = field_storage.chip_0.rx_delay.value.value;
load_next_c = '0;
- if(decoded_reg_strb.chip6_bound && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip6_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_0.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
load_next_c = '1;
end
- field_combo.chip6_bound.value.next = next_c;
- field_combo.chip6_bound.value.load_next = load_next_c;
+ field_combo.chip_0.rx_delay.value.next = next_c;
+ field_combo.chip_0.rx_delay.value.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip6_bound.value.value <= 10'h7;
+ field_storage.chip_0.rx_delay.value.value <= 8'h10;
end else begin
- if(field_combo.chip6_bound.value.load_next) begin
- field_storage.chip6_bound.value.value <= field_combo.chip6_bound.value.next;
+ if(field_combo.chip_0.rx_delay.value.load_next) begin
+ field_storage.chip_0.rx_delay.value.value <= field_combo.chip_0.rx_delay.value.next;
end
end
end
- assign hwif_out.chip6_bound.value.value = field_storage.chip6_bound.value.value;
- // Field: hyperbus_cfg_regs.chip7_base.value
+ assign hwif_out.chip_0.rx_delay.value.value = field_storage.chip_0.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_1.range_base.value
always_comb begin
automatic logic [9:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip7_base.value.value;
+ next_c = field_storage.chip_1.range_base.value.value;
load_next_c = '0;
- if(decoded_reg_strb.chip7_base && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip7_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_1.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
load_next_c = '1;
end
- field_combo.chip7_base.value.next = next_c;
- field_combo.chip7_base.value.load_next = load_next_c;
+ field_combo.chip_1.range_base.value.next = next_c;
+ field_combo.chip_1.range_base.value.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip7_base.value.value <= 10'h7;
+ field_storage.chip_1.range_base.value.value <= 10'h1;
end else begin
- if(field_combo.chip7_base.value.load_next) begin
- field_storage.chip7_base.value.value <= field_combo.chip7_base.value.next;
+ if(field_combo.chip_1.range_base.value.load_next) begin
+ field_storage.chip_1.range_base.value.value <= field_combo.chip_1.range_base.value.next;
end
end
end
- assign hwif_out.chip7_base.value.value = field_storage.chip7_base.value.value;
- // Field: hyperbus_cfg_regs.chip7_bound.value
+ assign hwif_out.chip_1.range_base.value.value = field_storage.chip_1.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_1.range_bound.value
always_comb begin
automatic logic [9:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.chip7_bound.value.value;
+ next_c = field_storage.chip_1.range_bound.value.value;
load_next_c = '0;
- if(decoded_reg_strb.chip7_bound && decoded_req_is_wr) begin // SW write
- next_c = (field_storage.chip7_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ if(decoded_reg_strb.chip_1.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
load_next_c = '1;
end
- field_combo.chip7_bound.value.next = next_c;
- field_combo.chip7_bound.value.load_next = load_next_c;
+ field_combo.chip_1.range_bound.value.next = next_c;
+ field_combo.chip_1.range_bound.value.load_next = load_next_c;
end
always_ff @(posedge clk or negedge arst_n) begin
if(~arst_n) begin
- field_storage.chip7_bound.value.value <= 10'h8;
+ field_storage.chip_1.range_bound.value.value <= 10'h2;
end else begin
- if(field_combo.chip7_bound.value.load_next) begin
- field_storage.chip7_bound.value.value <= field_combo.chip7_bound.value.next;
+ if(field_combo.chip_1.range_bound.value.load_next) begin
+ field_storage.chip_1.range_bound.value.value <= field_combo.chip_1.range_bound.value.next;
end
end
end
- assign hwif_out.chip7_bound.value.value = field_storage.chip7_bound.value.value;
-
- //--------------------------------------------------------------------------
- // Write response
- //--------------------------------------------------------------------------
- assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
- // Writes are always granted with no error response
- assign cpuif_wr_err = '0;
-
- //--------------------------------------------------------------------------
- // Readback
- //--------------------------------------------------------------------------
-
- logic [6:0] rd_mux_addr;
- assign rd_mux_addr = decoded_addr;
-
- logic readback_err;
- logic readback_done;
- logic [31:0] readback_data;
+ assign hwif_out.chip_1.range_bound.value.value = field_storage.chip_1.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_1.address_cfg.address_space
always_comb begin
- automatic logic [31:0] readback_data_var;
- readback_data_var = '0;
- if(rd_mux_addr == 7'h0) begin
- readback_data_var[3:0] = field_storage.t_latency_access.value.value;
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.address_cfg.address_space.next = next_c;
+ field_combo.chip_1.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_1.address_cfg.address_space.load_next) begin
+ field_storage.chip_1.address_cfg.address_space.value <= field_combo.chip_1.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.address_cfg.address_space.value = field_storage.chip_1.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_1.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_1.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_1.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_1.address_cfg.address_mask_msb.value <= field_combo.chip_1.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.address_cfg.address_mask_msb.value = field_storage.chip_1.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_1.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.address_cfg.enable.next = next_c;
+ field_combo.chip_1.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_1.address_cfg.enable.load_next) begin
+ field_storage.chip_1.address_cfg.enable.value <= field_combo.chip_1.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.address_cfg.enable.value = field_storage.chip_1.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_1.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_1.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_1.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_1.latency_cfg.t_latency_access.value <= field_combo.chip_1.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.latency_cfg.t_latency_access.value = field_storage.chip_1.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_1.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_1.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_1.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_1.latency_cfg.rwds_sample_delay.value <= field_combo.chip_1.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.latency_cfg.rwds_sample_delay.value = field_storage.chip_1.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_1.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_1.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_1.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_1.latency_cfg.en_latency_additional.value <= field_combo.chip_1.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.latency_cfg.en_latency_additional.value = field_storage.chip_1.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_1.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_1.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_1.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_1.burst_cfg.t_burst_max.value <= field_combo.chip_1.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.burst_cfg.t_burst_max.value = field_storage.chip_1.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_1.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_1.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_1.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_1.chip_timing.t_read_write_recovery.value <= field_combo.chip_1.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.chip_timing.t_read_write_recovery.value = field_storage.chip_1.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_1.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_1.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_1.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_1.chip_timing.t_csh_cycles.value <= field_combo.chip_1.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.chip_timing.t_csh_cycles.value = field_storage.chip_1.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_1.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_1.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_1.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_1.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_1.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.chip_timing.csn_to_ck_cycles.value = field_storage.chip_1.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_1.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.rx_delay.value.next = next_c;
+ field_combo.chip_1.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_1.rx_delay.value.load_next) begin
+ field_storage.chip_1.rx_delay.value.value <= field_combo.chip_1.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.rx_delay.value.value = field_storage.chip_1.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_2.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.range_base.value.next = next_c;
+ field_combo.chip_2.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.range_base.value.value <= 10'h2;
+ end else begin
+ if(field_combo.chip_2.range_base.value.load_next) begin
+ field_storage.chip_2.range_base.value.value <= field_combo.chip_2.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.range_base.value.value = field_storage.chip_2.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_2.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.range_bound.value.next = next_c;
+ field_combo.chip_2.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.range_bound.value.value <= 10'h3;
+ end else begin
+ if(field_combo.chip_2.range_bound.value.load_next) begin
+ field_storage.chip_2.range_bound.value.value <= field_combo.chip_2.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.range_bound.value.value = field_storage.chip_2.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_2.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.address_cfg.address_space.next = next_c;
+ field_combo.chip_2.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_2.address_cfg.address_space.load_next) begin
+ field_storage.chip_2.address_cfg.address_space.value <= field_combo.chip_2.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.address_cfg.address_space.value = field_storage.chip_2.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_2.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_2.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_2.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_2.address_cfg.address_mask_msb.value <= field_combo.chip_2.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.address_cfg.address_mask_msb.value = field_storage.chip_2.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_2.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.address_cfg.enable.next = next_c;
+ field_combo.chip_2.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_2.address_cfg.enable.load_next) begin
+ field_storage.chip_2.address_cfg.enable.value <= field_combo.chip_2.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.address_cfg.enable.value = field_storage.chip_2.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_2.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_2.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_2.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_2.latency_cfg.t_latency_access.value <= field_combo.chip_2.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.latency_cfg.t_latency_access.value = field_storage.chip_2.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_2.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_2.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_2.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_2.latency_cfg.rwds_sample_delay.value <= field_combo.chip_2.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.latency_cfg.rwds_sample_delay.value = field_storage.chip_2.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_2.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_2.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_2.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_2.latency_cfg.en_latency_additional.value <= field_combo.chip_2.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.latency_cfg.en_latency_additional.value = field_storage.chip_2.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_2.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_2.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_2.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_2.burst_cfg.t_burst_max.value <= field_combo.chip_2.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.burst_cfg.t_burst_max.value = field_storage.chip_2.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_2.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_2.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_2.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_2.chip_timing.t_read_write_recovery.value <= field_combo.chip_2.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.chip_timing.t_read_write_recovery.value = field_storage.chip_2.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_2.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_2.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_2.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_2.chip_timing.t_csh_cycles.value <= field_combo.chip_2.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.chip_timing.t_csh_cycles.value = field_storage.chip_2.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_2.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_2.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_2.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_2.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_2.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.chip_timing.csn_to_ck_cycles.value = field_storage.chip_2.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_2.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.rx_delay.value.next = next_c;
+ field_combo.chip_2.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_2.rx_delay.value.load_next) begin
+ field_storage.chip_2.rx_delay.value.value <= field_combo.chip_2.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.rx_delay.value.value = field_storage.chip_2.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_3.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.range_base.value.next = next_c;
+ field_combo.chip_3.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.range_base.value.value <= 10'h3;
+ end else begin
+ if(field_combo.chip_3.range_base.value.load_next) begin
+ field_storage.chip_3.range_base.value.value <= field_combo.chip_3.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.range_base.value.value = field_storage.chip_3.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_3.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.range_bound.value.next = next_c;
+ field_combo.chip_3.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.range_bound.value.value <= 10'h4;
+ end else begin
+ if(field_combo.chip_3.range_bound.value.load_next) begin
+ field_storage.chip_3.range_bound.value.value <= field_combo.chip_3.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.range_bound.value.value = field_storage.chip_3.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_3.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.address_cfg.address_space.next = next_c;
+ field_combo.chip_3.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_3.address_cfg.address_space.load_next) begin
+ field_storage.chip_3.address_cfg.address_space.value <= field_combo.chip_3.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.address_cfg.address_space.value = field_storage.chip_3.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_3.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_3.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_3.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_3.address_cfg.address_mask_msb.value <= field_combo.chip_3.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.address_cfg.address_mask_msb.value = field_storage.chip_3.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_3.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.address_cfg.enable.next = next_c;
+ field_combo.chip_3.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_3.address_cfg.enable.load_next) begin
+ field_storage.chip_3.address_cfg.enable.value <= field_combo.chip_3.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.address_cfg.enable.value = field_storage.chip_3.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_3.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_3.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_3.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_3.latency_cfg.t_latency_access.value <= field_combo.chip_3.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.latency_cfg.t_latency_access.value = field_storage.chip_3.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_3.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_3.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_3.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_3.latency_cfg.rwds_sample_delay.value <= field_combo.chip_3.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.latency_cfg.rwds_sample_delay.value = field_storage.chip_3.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_3.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_3.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_3.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_3.latency_cfg.en_latency_additional.value <= field_combo.chip_3.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.latency_cfg.en_latency_additional.value = field_storage.chip_3.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_3.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_3.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_3.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_3.burst_cfg.t_burst_max.value <= field_combo.chip_3.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.burst_cfg.t_burst_max.value = field_storage.chip_3.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_3.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_3.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_3.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_3.chip_timing.t_read_write_recovery.value <= field_combo.chip_3.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.chip_timing.t_read_write_recovery.value = field_storage.chip_3.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_3.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_3.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_3.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_3.chip_timing.t_csh_cycles.value <= field_combo.chip_3.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.chip_timing.t_csh_cycles.value = field_storage.chip_3.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_3.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_3.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_3.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_3.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_3.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.chip_timing.csn_to_ck_cycles.value = field_storage.chip_3.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_3.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.rx_delay.value.next = next_c;
+ field_combo.chip_3.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_3.rx_delay.value.load_next) begin
+ field_storage.chip_3.rx_delay.value.value <= field_combo.chip_3.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.rx_delay.value.value = field_storage.chip_3.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_4.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.range_base.value.next = next_c;
+ field_combo.chip_4.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.range_base.value.value <= 10'h4;
+ end else begin
+ if(field_combo.chip_4.range_base.value.load_next) begin
+ field_storage.chip_4.range_base.value.value <= field_combo.chip_4.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.range_base.value.value = field_storage.chip_4.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_4.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.range_bound.value.next = next_c;
+ field_combo.chip_4.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.range_bound.value.value <= 10'h5;
+ end else begin
+ if(field_combo.chip_4.range_bound.value.load_next) begin
+ field_storage.chip_4.range_bound.value.value <= field_combo.chip_4.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.range_bound.value.value = field_storage.chip_4.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_4.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.address_cfg.address_space.next = next_c;
+ field_combo.chip_4.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_4.address_cfg.address_space.load_next) begin
+ field_storage.chip_4.address_cfg.address_space.value <= field_combo.chip_4.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.address_cfg.address_space.value = field_storage.chip_4.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_4.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_4.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_4.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_4.address_cfg.address_mask_msb.value <= field_combo.chip_4.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.address_cfg.address_mask_msb.value = field_storage.chip_4.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_4.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.address_cfg.enable.next = next_c;
+ field_combo.chip_4.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_4.address_cfg.enable.load_next) begin
+ field_storage.chip_4.address_cfg.enable.value <= field_combo.chip_4.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.address_cfg.enable.value = field_storage.chip_4.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_4.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_4.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_4.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_4.latency_cfg.t_latency_access.value <= field_combo.chip_4.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.latency_cfg.t_latency_access.value = field_storage.chip_4.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_4.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_4.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_4.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_4.latency_cfg.rwds_sample_delay.value <= field_combo.chip_4.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.latency_cfg.rwds_sample_delay.value = field_storage.chip_4.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_4.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_4.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_4.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_4.latency_cfg.en_latency_additional.value <= field_combo.chip_4.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.latency_cfg.en_latency_additional.value = field_storage.chip_4.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_4.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_4.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_4.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_4.burst_cfg.t_burst_max.value <= field_combo.chip_4.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.burst_cfg.t_burst_max.value = field_storage.chip_4.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_4.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_4.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_4.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_4.chip_timing.t_read_write_recovery.value <= field_combo.chip_4.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.chip_timing.t_read_write_recovery.value = field_storage.chip_4.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_4.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_4.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_4.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_4.chip_timing.t_csh_cycles.value <= field_combo.chip_4.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.chip_timing.t_csh_cycles.value = field_storage.chip_4.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_4.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_4.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_4.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_4.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_4.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.chip_timing.csn_to_ck_cycles.value = field_storage.chip_4.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_4.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.rx_delay.value.next = next_c;
+ field_combo.chip_4.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_4.rx_delay.value.load_next) begin
+ field_storage.chip_4.rx_delay.value.value <= field_combo.chip_4.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.rx_delay.value.value = field_storage.chip_4.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_5.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.range_base.value.next = next_c;
+ field_combo.chip_5.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.range_base.value.value <= 10'h5;
+ end else begin
+ if(field_combo.chip_5.range_base.value.load_next) begin
+ field_storage.chip_5.range_base.value.value <= field_combo.chip_5.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.range_base.value.value = field_storage.chip_5.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_5.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.range_bound.value.next = next_c;
+ field_combo.chip_5.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.range_bound.value.value <= 10'h6;
+ end else begin
+ if(field_combo.chip_5.range_bound.value.load_next) begin
+ field_storage.chip_5.range_bound.value.value <= field_combo.chip_5.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.range_bound.value.value = field_storage.chip_5.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_5.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.address_cfg.address_space.next = next_c;
+ field_combo.chip_5.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_5.address_cfg.address_space.load_next) begin
+ field_storage.chip_5.address_cfg.address_space.value <= field_combo.chip_5.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.address_cfg.address_space.value = field_storage.chip_5.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_5.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_5.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_5.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_5.address_cfg.address_mask_msb.value <= field_combo.chip_5.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.address_cfg.address_mask_msb.value = field_storage.chip_5.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_5.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.address_cfg.enable.next = next_c;
+ field_combo.chip_5.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_5.address_cfg.enable.load_next) begin
+ field_storage.chip_5.address_cfg.enable.value <= field_combo.chip_5.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.address_cfg.enable.value = field_storage.chip_5.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_5.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_5.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_5.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_5.latency_cfg.t_latency_access.value <= field_combo.chip_5.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.latency_cfg.t_latency_access.value = field_storage.chip_5.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_5.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_5.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_5.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_5.latency_cfg.rwds_sample_delay.value <= field_combo.chip_5.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.latency_cfg.rwds_sample_delay.value = field_storage.chip_5.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_5.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_5.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_5.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_5.latency_cfg.en_latency_additional.value <= field_combo.chip_5.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.latency_cfg.en_latency_additional.value = field_storage.chip_5.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_5.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_5.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_5.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_5.burst_cfg.t_burst_max.value <= field_combo.chip_5.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.burst_cfg.t_burst_max.value = field_storage.chip_5.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_5.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_5.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_5.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_5.chip_timing.t_read_write_recovery.value <= field_combo.chip_5.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.chip_timing.t_read_write_recovery.value = field_storage.chip_5.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_5.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_5.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_5.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_5.chip_timing.t_csh_cycles.value <= field_combo.chip_5.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.chip_timing.t_csh_cycles.value = field_storage.chip_5.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_5.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_5.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_5.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_5.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_5.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.chip_timing.csn_to_ck_cycles.value = field_storage.chip_5.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_5.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.rx_delay.value.next = next_c;
+ field_combo.chip_5.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_5.rx_delay.value.load_next) begin
+ field_storage.chip_5.rx_delay.value.value <= field_combo.chip_5.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.rx_delay.value.value = field_storage.chip_5.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_6.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.range_base.value.next = next_c;
+ field_combo.chip_6.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.range_base.value.value <= 10'h6;
+ end else begin
+ if(field_combo.chip_6.range_base.value.load_next) begin
+ field_storage.chip_6.range_base.value.value <= field_combo.chip_6.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.range_base.value.value = field_storage.chip_6.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_6.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.range_bound.value.next = next_c;
+ field_combo.chip_6.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.range_bound.value.value <= 10'h7;
+ end else begin
+ if(field_combo.chip_6.range_bound.value.load_next) begin
+ field_storage.chip_6.range_bound.value.value <= field_combo.chip_6.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.range_bound.value.value = field_storage.chip_6.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_6.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.address_cfg.address_space.next = next_c;
+ field_combo.chip_6.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_6.address_cfg.address_space.load_next) begin
+ field_storage.chip_6.address_cfg.address_space.value <= field_combo.chip_6.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.address_cfg.address_space.value = field_storage.chip_6.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_6.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_6.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_6.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_6.address_cfg.address_mask_msb.value <= field_combo.chip_6.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.address_cfg.address_mask_msb.value = field_storage.chip_6.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_6.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.address_cfg.enable.next = next_c;
+ field_combo.chip_6.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_6.address_cfg.enable.load_next) begin
+ field_storage.chip_6.address_cfg.enable.value <= field_combo.chip_6.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.address_cfg.enable.value = field_storage.chip_6.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_6.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_6.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_6.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_6.latency_cfg.t_latency_access.value <= field_combo.chip_6.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.latency_cfg.t_latency_access.value = field_storage.chip_6.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_6.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_6.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_6.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_6.latency_cfg.rwds_sample_delay.value <= field_combo.chip_6.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.latency_cfg.rwds_sample_delay.value = field_storage.chip_6.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_6.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_6.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_6.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_6.latency_cfg.en_latency_additional.value <= field_combo.chip_6.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.latency_cfg.en_latency_additional.value = field_storage.chip_6.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_6.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_6.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_6.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_6.burst_cfg.t_burst_max.value <= field_combo.chip_6.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.burst_cfg.t_burst_max.value = field_storage.chip_6.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_6.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_6.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_6.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_6.chip_timing.t_read_write_recovery.value <= field_combo.chip_6.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.chip_timing.t_read_write_recovery.value = field_storage.chip_6.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_6.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_6.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_6.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_6.chip_timing.t_csh_cycles.value <= field_combo.chip_6.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.chip_timing.t_csh_cycles.value = field_storage.chip_6.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_6.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_6.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_6.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_6.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_6.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.chip_timing.csn_to_ck_cycles.value = field_storage.chip_6.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_6.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.rx_delay.value.next = next_c;
+ field_combo.chip_6.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_6.rx_delay.value.load_next) begin
+ field_storage.chip_6.rx_delay.value.value <= field_combo.chip_6.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.rx_delay.value.value = field_storage.chip_6.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_7.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.range_base.value.next = next_c;
+ field_combo.chip_7.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.range_base.value.value <= 10'h7;
+ end else begin
+ if(field_combo.chip_7.range_base.value.load_next) begin
+ field_storage.chip_7.range_base.value.value <= field_combo.chip_7.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.range_base.value.value = field_storage.chip_7.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_7.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.range_bound.value.next = next_c;
+ field_combo.chip_7.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.range_bound.value.value <= 10'h8;
+ end else begin
+ if(field_combo.chip_7.range_bound.value.load_next) begin
+ field_storage.chip_7.range_bound.value.value <= field_combo.chip_7.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.range_bound.value.value = field_storage.chip_7.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_7.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.address_cfg.address_space.next = next_c;
+ field_combo.chip_7.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_7.address_cfg.address_space.load_next) begin
+ field_storage.chip_7.address_cfg.address_space.value <= field_combo.chip_7.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.address_cfg.address_space.value = field_storage.chip_7.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_7.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_7.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_7.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_7.address_cfg.address_mask_msb.value <= field_combo.chip_7.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.address_cfg.address_mask_msb.value = field_storage.chip_7.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_7.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.address_cfg.enable.next = next_c;
+ field_combo.chip_7.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_7.address_cfg.enable.load_next) begin
+ field_storage.chip_7.address_cfg.enable.value <= field_combo.chip_7.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.address_cfg.enable.value = field_storage.chip_7.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_7.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_7.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_7.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_7.latency_cfg.t_latency_access.value <= field_combo.chip_7.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.latency_cfg.t_latency_access.value = field_storage.chip_7.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_7.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_7.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_7.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_7.latency_cfg.rwds_sample_delay.value <= field_combo.chip_7.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.latency_cfg.rwds_sample_delay.value = field_storage.chip_7.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_7.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_7.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_7.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_7.latency_cfg.en_latency_additional.value <= field_combo.chip_7.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.latency_cfg.en_latency_additional.value = field_storage.chip_7.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_7.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_7.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_7.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_7.burst_cfg.t_burst_max.value <= field_combo.chip_7.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.burst_cfg.t_burst_max.value = field_storage.chip_7.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_7.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_7.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_7.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_7.chip_timing.t_read_write_recovery.value <= field_combo.chip_7.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.chip_timing.t_read_write_recovery.value = field_storage.chip_7.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_7.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_7.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_7.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_7.chip_timing.t_csh_cycles.value <= field_combo.chip_7.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.chip_timing.t_csh_cycles.value = field_storage.chip_7.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_7.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_7.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_7.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_7.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_7.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.chip_timing.csn_to_ck_cycles.value = field_storage.chip_7.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_7.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.rx_delay.value.next = next_c;
+ field_combo.chip_7.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_7.rx_delay.value.load_next) begin
+ field_storage.chip_7.rx_delay.value.value <= field_combo.chip_7.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.rx_delay.value.value = field_storage.chip_7.rx_delay.value.value;
+ assign hwif_out.reserved_top.value.value = 32'h0;
+
+ //--------------------------------------------------------------------------
+ // Write response
+ //--------------------------------------------------------------------------
+ assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
+ // Writes are always granted with no error response
+ assign cpuif_wr_err = '0;
+
+ //--------------------------------------------------------------------------
+ // Readback
+ //--------------------------------------------------------------------------
+
+ logic [11:0] rd_mux_addr;
+ assign rd_mux_addr = decoded_addr;
+
+ logic readback_err;
+ logic readback_done;
+ logic [31:0] readback_data;
+ always_comb begin
+ automatic logic [31:0] readback_data_var;
+ readback_data_var = '0;
+ if(rd_mux_addr == 12'h0) begin
+ readback_data_var[7:0] = 8'h0;
+ readback_data_var[15:8] = 8'h9;
+ readback_data_var[23:16] = 8'h0;
+ readback_data_var[31:24] = 8'h0;
+ end
+ if(rd_mux_addr == 12'h4) begin
+ readback_data_var[15:0] = 16'h0;
+ readback_data_var[31:16] = 16'h1;
+ end
+ if(rd_mux_addr == 12'h8) begin
+ readback_data_var[7:0] = field_storage.global_cfg.capability.num_chips.value;
+ readback_data_var[15:8] = field_storage.global_cfg.capability.num_phys.value;
+ readback_data_var[16] = field_storage.global_cfg.capability.per_chip_cfg.value;
+ readback_data_var[17] = field_storage.global_cfg.capability.per_phy_cfg.value;
+ readback_data_var[18] = field_storage.global_cfg.capability.chip_enable.value;
+ readback_data_var[19] = field_storage.global_cfg.capability.clock_divider.value;
+ readback_data_var[20] = field_storage.global_cfg.capability.staged_apply.value;
+ readback_data_var[21] = field_storage.global_cfg.capability.error_status.value;
+ readback_data_var[22] = field_storage.global_cfg.capability.rwds_sample_timing.value;
+ readback_data_var[23] = field_storage.global_cfg.capability.rwds_oe_timing.value;
+ end
+ if(rd_mux_addr == 12'hc) begin
+ readback_data_var[0] = field_storage.global_cfg.command.flush.value;
+ readback_data_var[1] = field_storage.global_cfg.command.apply.value;
+ end
+ if(rd_mux_addr == 12'h10) begin
+ readback_data_var[0] = field_storage.global_cfg.status.decode_error.value;
+ readback_data_var[1] = field_storage.global_cfg.status.busy.value;
+ readback_data_var[2] = field_storage.global_cfg.status.dirty.value;
+ end
+ if(rd_mux_addr == 12'h100) begin
+ readback_data_var[0] = field_storage.frontend.frontend_cfg.dual_phy.value;
+ end
+ if(rd_mux_addr == 12'h200) begin
+ readback_data_var[7:0] = field_storage.backend.clock_cfg.divider.value;
+ end
+ if(rd_mux_addr == 12'h300) begin
+ readback_data_var[7:0] = field_storage.phy_0.tx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h304) begin
+ readback_data_var[7:0] = field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value;
+ end
+ if(rd_mux_addr == 12'h340) begin
+ readback_data_var[7:0] = field_storage.phy_1.tx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h344) begin
+ readback_data_var[7:0] = field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value;
+ end
+ if(rd_mux_addr == 12'h400) begin
+ readback_data_var[31:22] = field_storage.chip_0.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h404) begin
+ readback_data_var[31:22] = field_storage.chip_0.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h408) begin
+ readback_data_var[7:0] = field_storage.chip_0.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_0.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_0.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h40c) begin
+ readback_data_var[7:0] = field_storage.chip_0.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_0.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_0.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h410) begin
+ readback_data_var[15:0] = field_storage.chip_0.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h414) begin
+ readback_data_var[7:0] = field_storage.chip_0.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_0.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_0.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h418) begin
+ readback_data_var[7:0] = field_storage.chip_0.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h440) begin
+ readback_data_var[31:22] = field_storage.chip_1.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h444) begin
+ readback_data_var[31:22] = field_storage.chip_1.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h448) begin
+ readback_data_var[7:0] = field_storage.chip_1.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_1.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_1.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h44c) begin
+ readback_data_var[7:0] = field_storage.chip_1.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_1.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_1.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h450) begin
+ readback_data_var[15:0] = field_storage.chip_1.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h454) begin
+ readback_data_var[7:0] = field_storage.chip_1.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_1.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_1.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h458) begin
+ readback_data_var[7:0] = field_storage.chip_1.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h480) begin
+ readback_data_var[31:22] = field_storage.chip_2.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h484) begin
+ readback_data_var[31:22] = field_storage.chip_2.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h488) begin
+ readback_data_var[7:0] = field_storage.chip_2.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_2.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_2.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h48c) begin
+ readback_data_var[7:0] = field_storage.chip_2.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_2.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_2.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h490) begin
+ readback_data_var[15:0] = field_storage.chip_2.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h494) begin
+ readback_data_var[7:0] = field_storage.chip_2.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_2.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_2.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h498) begin
+ readback_data_var[7:0] = field_storage.chip_2.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h4c0) begin
+ readback_data_var[31:22] = field_storage.chip_3.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h4c4) begin
+ readback_data_var[31:22] = field_storage.chip_3.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h4c8) begin
+ readback_data_var[7:0] = field_storage.chip_3.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_3.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_3.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h4cc) begin
+ readback_data_var[7:0] = field_storage.chip_3.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_3.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_3.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h4d0) begin
+ readback_data_var[15:0] = field_storage.chip_3.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h4d4) begin
+ readback_data_var[7:0] = field_storage.chip_3.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_3.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_3.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h4d8) begin
+ readback_data_var[7:0] = field_storage.chip_3.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h500) begin
+ readback_data_var[31:22] = field_storage.chip_4.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h504) begin
+ readback_data_var[31:22] = field_storage.chip_4.range_bound.value.value;
end
- if(rd_mux_addr == 7'h4) begin
- readback_data_var[0] = field_storage.en_latency_additional.value.value;
+ if(rd_mux_addr == 12'h508) begin
+ readback_data_var[7:0] = field_storage.chip_4.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_4.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_4.address_cfg.enable.value;
end
- if(rd_mux_addr == 7'h8) begin
- readback_data_var[15:0] = field_storage.t_burst_max.value.value;
+ if(rd_mux_addr == 12'h50c) begin
+ readback_data_var[7:0] = field_storage.chip_4.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_4.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_4.latency_cfg.en_latency_additional.value;
end
- if(rd_mux_addr == 7'hc) begin
- readback_data_var[3:0] = field_storage.t_read_write_recovery.value.value;
+ if(rd_mux_addr == 12'h510) begin
+ readback_data_var[15:0] = field_storage.chip_4.burst_cfg.t_burst_max.value;
end
- if(rd_mux_addr == 7'h10) begin
- readback_data_var[4:0] = field_storage.t_rx_clk_delay.fine.value;
- readback_data_var[7:5] = field_storage.t_rx_clk_delay.coarse.value;
+ if(rd_mux_addr == 12'h514) begin
+ readback_data_var[7:0] = field_storage.chip_4.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_4.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_4.chip_timing.csn_to_ck_cycles.value;
end
- if(rd_mux_addr == 7'h14) begin
- readback_data_var[4:0] = field_storage.t_tx_clk_delay.fine.value;
- readback_data_var[7:5] = field_storage.t_tx_clk_delay.coarse.value;
+ if(rd_mux_addr == 12'h518) begin
+ readback_data_var[7:0] = field_storage.chip_4.rx_delay.value.value;
end
- if(rd_mux_addr == 7'h18) begin
- readback_data_var[4:0] = field_storage.address_mask_msb.value.value;
+ if(rd_mux_addr == 12'h540) begin
+ readback_data_var[31:22] = field_storage.chip_5.range_base.value.value;
end
- if(rd_mux_addr == 7'h1c) begin
- readback_data_var[0] = field_storage.address_space.value.value;
+ if(rd_mux_addr == 12'h544) begin
+ readback_data_var[31:22] = field_storage.chip_5.range_bound.value.value;
end
- if(rd_mux_addr == 7'h20) begin
- readback_data_var[0] = field_storage.phys_in_use.value.value;
+ if(rd_mux_addr == 12'h548) begin
+ readback_data_var[7:0] = field_storage.chip_5.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_5.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_5.address_cfg.enable.value;
end
- if(rd_mux_addr == 7'h24) begin
- readback_data_var[0] = field_storage.which_phy.value.value;
+ if(rd_mux_addr == 12'h54c) begin
+ readback_data_var[7:0] = field_storage.chip_5.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_5.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_5.latency_cfg.en_latency_additional.value;
end
- if(rd_mux_addr == 7'h28) begin
- readback_data_var[3:0] = field_storage.t_csh_cycles.value.value;
+ if(rd_mux_addr == 12'h550) begin
+ readback_data_var[15:0] = field_storage.chip_5.burst_cfg.t_burst_max.value;
end
- if(rd_mux_addr == 7'h2c) begin
- readback_data_var[3:0] = field_storage.csn_to_ck_cycles.value.value;
+ if(rd_mux_addr == 12'h554) begin
+ readback_data_var[7:0] = field_storage.chip_5.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_5.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_5.chip_timing.csn_to_ck_cycles.value;
end
- if(rd_mux_addr == 7'h30) begin
- readback_data_var[31:22] = field_storage.chip0_base.value.value;
+ if(rd_mux_addr == 12'h558) begin
+ readback_data_var[7:0] = field_storage.chip_5.rx_delay.value.value;
end
- if(rd_mux_addr == 7'h34) begin
- readback_data_var[31:22] = field_storage.chip0_bound.value.value;
+ if(rd_mux_addr == 12'h580) begin
+ readback_data_var[31:22] = field_storage.chip_6.range_base.value.value;
end
- if(rd_mux_addr == 7'h38) begin
- readback_data_var[31:22] = field_storage.chip1_base.value.value;
+ if(rd_mux_addr == 12'h584) begin
+ readback_data_var[31:22] = field_storage.chip_6.range_bound.value.value;
end
- if(rd_mux_addr == 7'h3c) begin
- readback_data_var[31:22] = field_storage.chip1_bound.value.value;
+ if(rd_mux_addr == 12'h588) begin
+ readback_data_var[7:0] = field_storage.chip_6.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_6.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_6.address_cfg.enable.value;
end
- if(rd_mux_addr == 7'h40) begin
- readback_data_var[31:22] = field_storage.chip2_base.value.value;
+ if(rd_mux_addr == 12'h58c) begin
+ readback_data_var[7:0] = field_storage.chip_6.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_6.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_6.latency_cfg.en_latency_additional.value;
end
- if(rd_mux_addr == 7'h44) begin
- readback_data_var[31:22] = field_storage.chip2_bound.value.value;
+ if(rd_mux_addr == 12'h590) begin
+ readback_data_var[15:0] = field_storage.chip_6.burst_cfg.t_burst_max.value;
end
- if(rd_mux_addr == 7'h48) begin
- readback_data_var[31:22] = field_storage.chip3_base.value.value;
+ if(rd_mux_addr == 12'h594) begin
+ readback_data_var[7:0] = field_storage.chip_6.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_6.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_6.chip_timing.csn_to_ck_cycles.value;
end
- if(rd_mux_addr == 7'h4c) begin
- readback_data_var[31:22] = field_storage.chip3_bound.value.value;
+ if(rd_mux_addr == 12'h598) begin
+ readback_data_var[7:0] = field_storage.chip_6.rx_delay.value.value;
end
- if(rd_mux_addr == 7'h58) begin
- readback_data_var[31:22] = field_storage.chip4_base.value.value;
+ if(rd_mux_addr == 12'h5c0) begin
+ readback_data_var[31:22] = field_storage.chip_7.range_base.value.value;
end
- if(rd_mux_addr == 7'h5c) begin
- readback_data_var[31:22] = field_storage.chip4_bound.value.value;
+ if(rd_mux_addr == 12'h5c4) begin
+ readback_data_var[31:22] = field_storage.chip_7.range_bound.value.value;
end
- if(rd_mux_addr == 7'h60) begin
- readback_data_var[31:22] = field_storage.chip5_base.value.value;
+ if(rd_mux_addr == 12'h5c8) begin
+ readback_data_var[7:0] = field_storage.chip_7.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_7.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_7.address_cfg.enable.value;
end
- if(rd_mux_addr == 7'h64) begin
- readback_data_var[31:22] = field_storage.chip5_bound.value.value;
+ if(rd_mux_addr == 12'h5cc) begin
+ readback_data_var[7:0] = field_storage.chip_7.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_7.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_7.latency_cfg.en_latency_additional.value;
end
- if(rd_mux_addr == 7'h68) begin
- readback_data_var[31:22] = field_storage.chip6_base.value.value;
+ if(rd_mux_addr == 12'h5d0) begin
+ readback_data_var[15:0] = field_storage.chip_7.burst_cfg.t_burst_max.value;
end
- if(rd_mux_addr == 7'h6c) begin
- readback_data_var[31:22] = field_storage.chip6_bound.value.value;
+ if(rd_mux_addr == 12'h5d4) begin
+ readback_data_var[7:0] = field_storage.chip_7.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_7.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_7.chip_timing.csn_to_ck_cycles.value;
end
- if(rd_mux_addr == 7'h70) begin
- readback_data_var[31:22] = field_storage.chip7_base.value.value;
+ if(rd_mux_addr == 12'h5d8) begin
+ readback_data_var[7:0] = field_storage.chip_7.rx_delay.value.value;
end
- if(rd_mux_addr == 7'h74) begin
- readback_data_var[31:22] = field_storage.chip7_bound.value.value;
+ if(rd_mux_addr == 12'hffc) begin
+ readback_data_var[31:0] = 32'h0;
end
readback_data = readback_data_var;
readback_done = decoded_req & ~decoded_req_is_wr;
diff --git a/src/regs/hyperbus_cfg_regblock_pkg.sv b/src/regs/hyperbus_cfg_regblock_pkg.sv
index 85c5edb..807817d 100644
--- a/src/regs/hyperbus_cfg_regblock_pkg.sv
+++ b/src/regs/hyperbus_cfg_regblock_pkg.sv
@@ -4,271 +4,563 @@
package hyperbus_cfg_regblock_pkg;
localparam HYPERBUS_CFG_REGBLOCK_DATA_WIDTH = 32;
- localparam HYPERBUS_CFG_REGBLOCK_MIN_ADDR_WIDTH = 7;
- localparam HYPERBUS_CFG_REGBLOCK_SIZE = 'h78;
+ localparam HYPERBUS_CFG_REGBLOCK_MIN_ADDR_WIDTH = 12;
+ localparam HYPERBUS_CFG_REGBLOCK_SIZE = 'h1000;
typedef struct {
- logic [3:0] value;
- } hyperbus_cfg_regs__t_latency_access__value__out_t;
+ logic [7:0] next;
+ } hyperbus_cfg_regs__capability__num_chips__in_t;
typedef struct {
- hyperbus_cfg_regs__t_latency_access__value__out_t value;
- } hyperbus_cfg_regs__t_latency_access__out_t;
+ logic [7:0] next;
+ } hyperbus_cfg_regs__capability__num_phys__in_t;
typedef struct {
- logic value;
- } hyperbus_cfg_regs__en_latency_additional__value__out_t;
+ logic next;
+ } hyperbus_cfg_regs__capability__per_chip_cfg__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__per_phy_cfg__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__chip_enable__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__clock_divider__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__staged_apply__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__error_status__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__rwds_sample_timing__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__rwds_oe_timing__in_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__capability__num_chips__in_t num_chips;
+ hyperbus_cfg_regs__capability__num_phys__in_t num_phys;
+ hyperbus_cfg_regs__capability__per_chip_cfg__in_t per_chip_cfg;
+ hyperbus_cfg_regs__capability__per_phy_cfg__in_t per_phy_cfg;
+ hyperbus_cfg_regs__capability__chip_enable__in_t chip_enable;
+ hyperbus_cfg_regs__capability__clock_divider__in_t clock_divider;
+ hyperbus_cfg_regs__capability__staged_apply__in_t staged_apply;
+ hyperbus_cfg_regs__capability__error_status__in_t error_status;
+ hyperbus_cfg_regs__capability__rwds_sample_timing__in_t rwds_sample_timing;
+ hyperbus_cfg_regs__capability__rwds_oe_timing__in_t rwds_oe_timing;
+ } hyperbus_cfg_regs__capability__in_t;
+
+ typedef struct {
+ logic next;
+ logic hwset;
+ } hyperbus_cfg_regs__status__decode_error__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__status__busy__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__status__dirty__in_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__status__decode_error__in_t decode_error;
+ hyperbus_cfg_regs__status__busy__in_t busy;
+ hyperbus_cfg_regs__status__dirty__in_t dirty;
+ } hyperbus_cfg_regs__status__in_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__capability__in_t capability;
+ hyperbus_cfg_regs__status__in_t status;
+ } hyperbus_cfg_regs__global_regs__in_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__global_regs__in_t global_cfg;
+ } hyperbus_cfg_regs__in_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__ip_version__revision__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__ip_version__patch__out_t;
typedef struct {
- hyperbus_cfg_regs__en_latency_additional__value__out_t value;
- } hyperbus_cfg_regs__en_latency_additional__out_t;
+ logic [7:0] value;
+ } hyperbus_cfg_regs__ip_version__minor__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__ip_version__major__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__ip_version__revision__out_t revision;
+ hyperbus_cfg_regs__ip_version__patch__out_t patch;
+ hyperbus_cfg_regs__ip_version__minor__out_t minor;
+ hyperbus_cfg_regs__ip_version__major__out_t major;
+ } hyperbus_cfg_regs__ip_version__out_t;
typedef struct {
logic [15:0] value;
- } hyperbus_cfg_regs__t_burst_max__value__out_t;
+ } hyperbus_cfg_regs__reg_if_version__minor__out_t;
+
+ typedef struct {
+ logic [15:0] value;
+ } hyperbus_cfg_regs__reg_if_version__major__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__reg_if_version__minor__out_t minor;
+ hyperbus_cfg_regs__reg_if_version__major__out_t major;
+ } hyperbus_cfg_regs__reg_if_version__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__capability__num_chips__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__capability__num_phys__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__capability__per_chip_cfg__out_t;
typedef struct {
- hyperbus_cfg_regs__t_burst_max__value__out_t value;
- } hyperbus_cfg_regs__t_burst_max__out_t;
+ logic value;
+ } hyperbus_cfg_regs__capability__per_phy_cfg__out_t;
typedef struct {
- logic [3:0] value;
- } hyperbus_cfg_regs__t_read_write_recovery__value__out_t;
+ logic value;
+ } hyperbus_cfg_regs__capability__chip_enable__out_t;
typedef struct {
- hyperbus_cfg_regs__t_read_write_recovery__value__out_t value;
- } hyperbus_cfg_regs__t_read_write_recovery__out_t;
+ logic value;
+ } hyperbus_cfg_regs__capability__clock_divider__out_t;
typedef struct {
- logic [4:0] value;
- } hyperbus_cfg_regs__t_rx_clk_delay__fine__out_t;
+ logic value;
+ } hyperbus_cfg_regs__capability__staged_apply__out_t;
typedef struct {
- logic [2:0] value;
- } hyperbus_cfg_regs__t_rx_clk_delay__coarse__out_t;
+ logic value;
+ } hyperbus_cfg_regs__capability__error_status__out_t;
typedef struct {
- hyperbus_cfg_regs__t_rx_clk_delay__fine__out_t fine;
- hyperbus_cfg_regs__t_rx_clk_delay__coarse__out_t coarse;
- } hyperbus_cfg_regs__t_rx_clk_delay__out_t;
+ logic value;
+ } hyperbus_cfg_regs__capability__rwds_sample_timing__out_t;
typedef struct {
- logic [4:0] value;
- } hyperbus_cfg_regs__t_tx_clk_delay__fine__out_t;
+ logic value;
+ } hyperbus_cfg_regs__capability__rwds_oe_timing__out_t;
typedef struct {
- logic [2:0] value;
- } hyperbus_cfg_regs__t_tx_clk_delay__coarse__out_t;
+ hyperbus_cfg_regs__capability__num_chips__out_t num_chips;
+ hyperbus_cfg_regs__capability__num_phys__out_t num_phys;
+ hyperbus_cfg_regs__capability__per_chip_cfg__out_t per_chip_cfg;
+ hyperbus_cfg_regs__capability__per_phy_cfg__out_t per_phy_cfg;
+ hyperbus_cfg_regs__capability__chip_enable__out_t chip_enable;
+ hyperbus_cfg_regs__capability__clock_divider__out_t clock_divider;
+ hyperbus_cfg_regs__capability__staged_apply__out_t staged_apply;
+ hyperbus_cfg_regs__capability__error_status__out_t error_status;
+ hyperbus_cfg_regs__capability__rwds_sample_timing__out_t rwds_sample_timing;
+ hyperbus_cfg_regs__capability__rwds_oe_timing__out_t rwds_oe_timing;
+ } hyperbus_cfg_regs__capability__out_t;
typedef struct {
- hyperbus_cfg_regs__t_tx_clk_delay__fine__out_t fine;
- hyperbus_cfg_regs__t_tx_clk_delay__coarse__out_t coarse;
- } hyperbus_cfg_regs__t_tx_clk_delay__out_t;
+ logic value;
+ } hyperbus_cfg_regs__command__flush__out_t;
typedef struct {
- logic [4:0] value;
- } hyperbus_cfg_regs__address_mask_msb__value__out_t;
+ logic value;
+ } hyperbus_cfg_regs__command__apply__out_t;
typedef struct {
- hyperbus_cfg_regs__address_mask_msb__value__out_t value;
- } hyperbus_cfg_regs__address_mask_msb__out_t;
+ hyperbus_cfg_regs__command__flush__out_t flush;
+ hyperbus_cfg_regs__command__apply__out_t apply;
+ } hyperbus_cfg_regs__command__out_t;
typedef struct {
logic value;
- } hyperbus_cfg_regs__address_space__value__out_t;
+ } hyperbus_cfg_regs__status__decode_error__out_t;
typedef struct {
- hyperbus_cfg_regs__address_space__value__out_t value;
- } hyperbus_cfg_regs__address_space__out_t;
+ logic value;
+ } hyperbus_cfg_regs__status__busy__out_t;
typedef struct {
logic value;
- } hyperbus_cfg_regs__phys_in_use__value__out_t;
+ } hyperbus_cfg_regs__status__dirty__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__status__decode_error__out_t decode_error;
+ hyperbus_cfg_regs__status__busy__out_t busy;
+ hyperbus_cfg_regs__status__dirty__out_t dirty;
+ } hyperbus_cfg_regs__status__out_t;
typedef struct {
- hyperbus_cfg_regs__phys_in_use__value__out_t value;
- } hyperbus_cfg_regs__phys_in_use__out_t;
+ hyperbus_cfg_regs__ip_version__out_t ip_version;
+ hyperbus_cfg_regs__reg_if_version__out_t reg_if_version;
+ hyperbus_cfg_regs__capability__out_t capability;
+ hyperbus_cfg_regs__command__out_t command;
+ hyperbus_cfg_regs__status__out_t status;
+ } hyperbus_cfg_regs__global_regs__out_t;
typedef struct {
logic value;
- } hyperbus_cfg_regs__which_phy__value__out_t;
+ } hyperbus_cfg_regs__frontend_cfg__dual_phy__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__frontend_cfg__dual_phy__out_t dual_phy;
+ } hyperbus_cfg_regs__frontend_cfg__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__frontend_cfg__out_t frontend_cfg;
+ } hyperbus_cfg_regs__frontend_regs__out_t;
typedef struct {
- hyperbus_cfg_regs__which_phy__value__out_t value;
- } hyperbus_cfg_regs__which_phy__out_t;
+ logic [7:0] value;
+ } hyperbus_cfg_regs__clock_cfg__divider__out_t;
typedef struct {
- logic [3:0] value;
- } hyperbus_cfg_regs__t_csh_cycles__value__out_t;
+ hyperbus_cfg_regs__clock_cfg__divider__out_t divider;
+ } hyperbus_cfg_regs__clock_cfg__out_t;
typedef struct {
- hyperbus_cfg_regs__t_csh_cycles__value__out_t value;
- } hyperbus_cfg_regs__t_csh_cycles__out_t;
+ hyperbus_cfg_regs__clock_cfg__out_t clock_cfg;
+ } hyperbus_cfg_regs__backend_regs__out_t;
typedef struct {
- logic [3:0] value;
- } hyperbus_cfg_regs__csn_to_ck_cycles__value__out_t;
+ logic [7:0] value;
+ } hyperbus_cfg_regs__tx_delay__value__out_t;
typedef struct {
- hyperbus_cfg_regs__csn_to_ck_cycles__value__out_t value;
- } hyperbus_cfg_regs__csn_to_ck_cycles__out_t;
+ hyperbus_cfg_regs__tx_delay__value__out_t value;
+ } hyperbus_cfg_regs__tx_delay__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__rwds_timing__rwds_oe_setup_cycles__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__rwds_timing__rwds_oe_setup_cycles__out_t rwds_oe_setup_cycles;
+ } hyperbus_cfg_regs__rwds_timing__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__tx_delay__out_t tx_delay;
+ hyperbus_cfg_regs__rwds_timing__out_t rwds_timing;
+ } hyperbus_cfg_regs__phy_regs__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip0_base__value__out_t;
+ } hyperbus_cfg_regs__range_base__value__out_t;
typedef struct {
- hyperbus_cfg_regs__chip0_base__value__out_t value;
- } hyperbus_cfg_regs__chip0_base__out_t;
+ hyperbus_cfg_regs__range_base__value__out_t value;
+ } hyperbus_cfg_regs__range_base__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip0_bound__value__out_t;
+ } hyperbus_cfg_regs__range_bound__value__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound__value__out_t value;
+ } hyperbus_cfg_regs__range_bound__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__address_cfg__address_space__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__address_cfg__address_mask_msb__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__address_cfg__enable__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__address_cfg__address_space__out_t address_space;
+ hyperbus_cfg_regs__address_cfg__address_mask_msb__out_t address_mask_msb;
+ hyperbus_cfg_regs__address_cfg__enable__out_t enable;
+ } hyperbus_cfg_regs__address_cfg__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__latency_cfg__t_latency_access__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__latency_cfg__rwds_sample_delay__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__latency_cfg__en_latency_additional__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__latency_cfg__t_latency_access__out_t t_latency_access;
+ hyperbus_cfg_regs__latency_cfg__rwds_sample_delay__out_t rwds_sample_delay;
+ hyperbus_cfg_regs__latency_cfg__en_latency_additional__out_t en_latency_additional;
+ } hyperbus_cfg_regs__latency_cfg__out_t;
+
+ typedef struct {
+ logic [15:0] value;
+ } hyperbus_cfg_regs__burst_cfg__t_burst_max__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__burst_cfg__t_burst_max__out_t t_burst_max;
+ } hyperbus_cfg_regs__burst_cfg__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__chip_timing__t_read_write_recovery__out_t;
typedef struct {
- hyperbus_cfg_regs__chip0_bound__value__out_t value;
- } hyperbus_cfg_regs__chip0_bound__out_t;
+ logic [7:0] value;
+ } hyperbus_cfg_regs__chip_timing__t_csh_cycles__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__chip_timing__csn_to_ck_cycles__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__chip_timing__t_read_write_recovery__out_t t_read_write_recovery;
+ hyperbus_cfg_regs__chip_timing__t_csh_cycles__out_t t_csh_cycles;
+ hyperbus_cfg_regs__chip_timing__csn_to_ck_cycles__out_t csn_to_ck_cycles;
+ } hyperbus_cfg_regs__chip_timing__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__rx_delay__value__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__rx_delay__value__out_t value;
+ } hyperbus_cfg_regs__rx_delay__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base__out_t range_base;
+ hyperbus_cfg_regs__range_bound__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip1_base__value__out_t;
+ } hyperbus_cfg_regs__range_base_value_aea1d0e1__value_reset_1__out_t;
typedef struct {
- hyperbus_cfg_regs__chip1_base__value__out_t value;
- } hyperbus_cfg_regs__chip1_base__out_t;
+ hyperbus_cfg_regs__range_base_value_aea1d0e1__value_reset_1__out_t value;
+ } hyperbus_cfg_regs__range_base_value_aea1d0e1__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip1_bound__value__out_t;
+ } hyperbus_cfg_regs__range_bound_value_e30f0c3f__value_reset_2__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_e30f0c3f__value_reset_2__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_e30f0c3f__out_t;
typedef struct {
- hyperbus_cfg_regs__chip1_bound__value__out_t value;
- } hyperbus_cfg_regs__chip1_bound__out_t;
+ hyperbus_cfg_regs__range_base_value_aea1d0e1__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_e30f0c3f__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_de2a4636_range_bound_d40fd139__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip2_base__value__out_t;
+ } hyperbus_cfg_regs__range_base_value_e30f0c3f__value_reset_2__out_t;
typedef struct {
- hyperbus_cfg_regs__chip2_base__value__out_t value;
- } hyperbus_cfg_regs__chip2_base__out_t;
+ hyperbus_cfg_regs__range_base_value_e30f0c3f__value_reset_2__out_t value;
+ } hyperbus_cfg_regs__range_base_value_e30f0c3f__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip2_bound__value__out_t;
+ } hyperbus_cfg_regs__range_bound_value_2f629ec9__value_reset_3__out_t;
typedef struct {
- hyperbus_cfg_regs__chip2_bound__value__out_t value;
- } hyperbus_cfg_regs__chip2_bound__out_t;
+ hyperbus_cfg_regs__range_bound_value_2f629ec9__value_reset_3__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_2f629ec9__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_e30f0c3f__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_2f629ec9__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_b054dd4c_range_bound_a4d5f83b__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip3_base__value__out_t;
+ } hyperbus_cfg_regs__range_base_value_2f629ec9__value_reset_3__out_t;
typedef struct {
- hyperbus_cfg_regs__chip3_base__value__out_t value;
- } hyperbus_cfg_regs__chip3_base__out_t;
+ hyperbus_cfg_regs__range_base_value_2f629ec9__value_reset_3__out_t value;
+ } hyperbus_cfg_regs__range_base_value_2f629ec9__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip3_bound__value__out_t;
+ } hyperbus_cfg_regs__range_bound_value_a1e733c2__value_reset_4__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_a1e733c2__value_reset_4__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_a1e733c2__out_t;
typedef struct {
- hyperbus_cfg_regs__chip3_bound__value__out_t value;
- } hyperbus_cfg_regs__chip3_bound__out_t;
+ hyperbus_cfg_regs__range_base_value_2f629ec9__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_a1e733c2__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_f7266ded_range_bound_5bf260e9__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip4_base__value__out_t;
+ } hyperbus_cfg_regs__range_base_value_a1e733c2__value_reset_4__out_t;
typedef struct {
- hyperbus_cfg_regs__chip4_base__value__out_t value;
- } hyperbus_cfg_regs__chip4_base__out_t;
+ hyperbus_cfg_regs__range_base_value_a1e733c2__value_reset_4__out_t value;
+ } hyperbus_cfg_regs__range_base_value_a1e733c2__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip4_bound__value__out_t;
+ } hyperbus_cfg_regs__range_bound_value_342915db__value_reset_5__out_t;
typedef struct {
- hyperbus_cfg_regs__chip4_bound__value__out_t value;
- } hyperbus_cfg_regs__chip4_bound__out_t;
+ hyperbus_cfg_regs__range_bound_value_342915db__value_reset_5__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_342915db__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_a1e733c2__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_342915db__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_0d543b99_range_bound_1fffc3a2__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip5_base__value__out_t;
+ } hyperbus_cfg_regs__range_base_value_342915db__value_reset_5__out_t;
typedef struct {
- hyperbus_cfg_regs__chip5_base__value__out_t value;
- } hyperbus_cfg_regs__chip5_base__out_t;
+ hyperbus_cfg_regs__range_base_value_342915db__value_reset_5__out_t value;
+ } hyperbus_cfg_regs__range_base_value_342915db__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip5_bound__value__out_t;
+ } hyperbus_cfg_regs__range_bound_value_883c384f__value_reset_6__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_883c384f__value_reset_6__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_883c384f__out_t;
typedef struct {
- hyperbus_cfg_regs__chip5_bound__value__out_t value;
- } hyperbus_cfg_regs__chip5_bound__out_t;
+ hyperbus_cfg_regs__range_base_value_342915db__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_883c384f__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_e068ab2e_range_bound_9afa5911__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip6_base__value__out_t;
+ } hyperbus_cfg_regs__range_base_value_883c384f__value_reset_6__out_t;
typedef struct {
- hyperbus_cfg_regs__chip6_base__value__out_t value;
- } hyperbus_cfg_regs__chip6_base__out_t;
+ hyperbus_cfg_regs__range_base_value_883c384f__value_reset_6__out_t value;
+ } hyperbus_cfg_regs__range_base_value_883c384f__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip6_bound__value__out_t;
+ } hyperbus_cfg_regs__range_bound_value_d0d03147__value_reset_7__out_t;
typedef struct {
- hyperbus_cfg_regs__chip6_bound__value__out_t value;
- } hyperbus_cfg_regs__chip6_bound__out_t;
+ hyperbus_cfg_regs__range_bound_value_d0d03147__value_reset_7__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_d0d03147__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_883c384f__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_d0d03147__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_ac4fb754_range_bound_24b9644b__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip7_base__value__out_t;
+ } hyperbus_cfg_regs__range_base_value_d0d03147__value_reset_7__out_t;
typedef struct {
- hyperbus_cfg_regs__chip7_base__value__out_t value;
- } hyperbus_cfg_regs__chip7_base__out_t;
+ hyperbus_cfg_regs__range_base_value_d0d03147__value_reset_7__out_t value;
+ } hyperbus_cfg_regs__range_base_value_d0d03147__out_t;
typedef struct {
logic [9:0] value;
- } hyperbus_cfg_regs__chip7_bound__value__out_t;
-
- typedef struct {
- hyperbus_cfg_regs__chip7_bound__value__out_t value;
- } hyperbus_cfg_regs__chip7_bound__out_t;
-
- typedef struct {
- hyperbus_cfg_regs__t_latency_access__out_t t_latency_access;
- hyperbus_cfg_regs__en_latency_additional__out_t en_latency_additional;
- hyperbus_cfg_regs__t_burst_max__out_t t_burst_max;
- hyperbus_cfg_regs__t_read_write_recovery__out_t t_read_write_recovery;
- hyperbus_cfg_regs__t_rx_clk_delay__out_t t_rx_clk_delay;
- hyperbus_cfg_regs__t_tx_clk_delay__out_t t_tx_clk_delay;
- hyperbus_cfg_regs__address_mask_msb__out_t address_mask_msb;
- hyperbus_cfg_regs__address_space__out_t address_space;
- hyperbus_cfg_regs__phys_in_use__out_t phys_in_use;
- hyperbus_cfg_regs__which_phy__out_t which_phy;
- hyperbus_cfg_regs__t_csh_cycles__out_t t_csh_cycles;
- hyperbus_cfg_regs__csn_to_ck_cycles__out_t csn_to_ck_cycles;
- hyperbus_cfg_regs__chip0_base__out_t chip0_base;
- hyperbus_cfg_regs__chip0_bound__out_t chip0_bound;
- hyperbus_cfg_regs__chip1_base__out_t chip1_base;
- hyperbus_cfg_regs__chip1_bound__out_t chip1_bound;
- hyperbus_cfg_regs__chip2_base__out_t chip2_base;
- hyperbus_cfg_regs__chip2_bound__out_t chip2_bound;
- hyperbus_cfg_regs__chip3_base__out_t chip3_base;
- hyperbus_cfg_regs__chip3_bound__out_t chip3_bound;
- hyperbus_cfg_regs__chip4_base__out_t chip4_base;
- hyperbus_cfg_regs__chip4_bound__out_t chip4_bound;
- hyperbus_cfg_regs__chip5_base__out_t chip5_base;
- hyperbus_cfg_regs__chip5_bound__out_t chip5_bound;
- hyperbus_cfg_regs__chip6_base__out_t chip6_base;
- hyperbus_cfg_regs__chip6_bound__out_t chip6_bound;
- hyperbus_cfg_regs__chip7_base__out_t chip7_base;
- hyperbus_cfg_regs__chip7_bound__out_t chip7_bound;
+ } hyperbus_cfg_regs__range_bound_value_971bab53__value_reset_8__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_971bab53__value_reset_8__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_971bab53__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_d0d03147__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_971bab53__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_63c2ba90_range_bound_602aea67__out_t;
+
+ typedef struct {
+ logic [31:0] value;
+ } hyperbus_cfg_regs__reserved_top__value__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__reserved_top__value__out_t value;
+ } hyperbus_cfg_regs__reserved_top__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__global_regs__out_t global_cfg;
+ hyperbus_cfg_regs__frontend_regs__out_t frontend;
+ hyperbus_cfg_regs__backend_regs__out_t backend;
+ hyperbus_cfg_regs__phy_regs__out_t phy_0;
+ hyperbus_cfg_regs__phy_regs__out_t phy_1;
+ hyperbus_cfg_regs__chip_regs__out_t chip_0;
+ hyperbus_cfg_regs__chip_regs_range_base_de2a4636_range_bound_d40fd139__out_t chip_1;
+ hyperbus_cfg_regs__chip_regs_range_base_b054dd4c_range_bound_a4d5f83b__out_t chip_2;
+ hyperbus_cfg_regs__chip_regs_range_base_f7266ded_range_bound_5bf260e9__out_t chip_3;
+ hyperbus_cfg_regs__chip_regs_range_base_0d543b99_range_bound_1fffc3a2__out_t chip_4;
+ hyperbus_cfg_regs__chip_regs_range_base_e068ab2e_range_bound_9afa5911__out_t chip_5;
+ hyperbus_cfg_regs__chip_regs_range_base_ac4fb754_range_bound_24b9644b__out_t chip_6;
+ hyperbus_cfg_regs__chip_regs_range_base_63c2ba90_range_bound_602aea67__out_t chip_7;
+ hyperbus_cfg_regs__reserved_top__out_t reserved_top;
} hyperbus_cfg_regs__out_t;
endpackage
diff --git a/src/regs/hyperbus_cfg_regs.rdl b/src/regs/hyperbus_cfg_regs.rdl
index 515e294..a81f7f9 100644
--- a/src/regs/hyperbus_cfg_regs.rdl
+++ b/src/regs/hyperbus_cfg_regs.rdl
@@ -1,194 +1,148 @@
addrmap hyperbus_cfg_regs {
- desc = "HyperBus controller configuration. Chip address ranges must be 4 MiB aligned, ordered by chip-select index, and non-overlapping.";
-
- reg t_latency_access {
- desc = "Initial latency cycles before read or write data.";
- field { sw = rw; hw = r; reset = 4'h6; } value[3:0];
- };
-
- reg en_latency_additional {
- desc = "Enable additional latency cycles when requested by RWDS.";
- field { sw = rw; hw = r; reset = 1'b0; } value;
- };
-
- reg t_burst_max {
- desc = "Maximum continuous burst length before the PHY restarts a transfer.";
- field { sw = rw; hw = r; reset = 16'd350; } value[15:0];
- };
-
- reg t_read_write_recovery {
- desc = "Recovery cycles inserted between read and write phases.";
- field { sw = rw; hw = r; reset = 4'h6; } value[3:0];
- };
-
- reg t_rx_clk_delay {
- desc = "RX sampling delay with fine taps in bits 4:0 and coarse taps in bits 7:5.";
- field {
- desc = "Fine delay-line tap setting, nominally about 78 ps per tap.";
- sw = rw;
- hw = r;
- reset = 5'h10;
- } fine[4:0];
- field {
- desc = "Coarse delay-line tap setting with an implementation-defined step size.";
- sw = rw;
- hw = r;
- reset = 3'h0;
- } coarse[7:5];
- };
-
- reg t_tx_clk_delay {
- desc = "TX clock delay with fine taps in bits 4:0 and coarse taps in bits 7:5.";
- field {
- desc = "Fine delay-line tap setting, nominally about 78 ps per tap.";
- sw = rw;
- hw = r;
- reset = 5'h10;
- } fine[4:0];
- field {
- desc = "Coarse delay-line tap setting with an implementation-defined step size.";
- sw = rw;
- hw = r;
- reset = 3'h0;
- } coarse[7:5];
- };
-
- reg address_mask_msb {
- desc = "Most-significant address bit used by frontend address packing.";
- field { sw = rw; hw = r; reset = 5'd25; } value[4:0];
- };
-
- reg address_space {
- desc = "Select HyperRAM or HyperFlash address-space interpretation.";
- field { sw = rw; hw = r; reset = 1'b0; } value;
- };
-
- reg phys_in_use {
- desc = "Select whether one or both PHY lanes are active.";
- field { sw = rw; hw = r; reset = 1'b1; } value;
- };
-
- reg which_phy {
- desc = "Select the PHY lane used when only one PHY is active.";
- field { sw = rw; hw = r; reset = 1'b1; } value;
- };
-
- reg t_csh_cycles {
- desc = "Chip-select high time between transfers.";
- field { sw = rw; hw = r; reset = 4'h1; } value[3:0];
- };
-
- reg csn_to_ck_cycles {
- desc = "Delay cycles from chip-select assertion to clock start.";
- field { sw = rw; hw = r; reset = 4'h0; } value[3:0];
- };
-
- reg chip0_base {
- desc = "Inclusive 4 MiB-aligned address for chip-select 0 decoding.";
+ desc = "HyperBus controller configuration register map. Enabled chip ranges must be 4 MiB aligned, ordered by chip-select index, and non-overlapping.";
+
+ reg ip_version {
+ desc = "IP version (major.minor.patch.revision).";
+ field { sw = r; hw = r; reset = 8'd0; } major[31:24];
+ field { sw = r; hw = r; reset = 8'd0; } minor[23:16];
+ field { sw = r; hw = r; reset = 8'd9; } patch[15:8];
+ field { sw = r; hw = r; reset = 8'd0; } revision[7:0];
+ };
+ reg reg_if_version {
+ desc = "Register interface version.";
+ field { sw = r; hw = r; reset = 16'd1; } major[31:16];
+ field { sw = r; hw = r; reset = 16'd0; } minor[15:0];
+ };
+ reg capability {
+ desc = "Hardware-provided implementation capabilities.";
+ field { desc = "Number of implemented chip selects."; sw = r; hw = rw; reset = 8'd0; } num_chips[7:0];
+ field { desc = "Number of implemented PHY lanes."; sw = r; hw = rw; reset = 8'd0; } num_phys[15:8];
+ field { desc = "Each chip record controls its corresponding chip rather than chip 0 being shared."; sw = r; hw = rw; reset = 1'b0; } per_chip_cfg[16:16];
+ field { desc = "Each PHY record controls its corresponding lane rather than PHY 0 being shared."; sw = r; hw = rw; reset = 1'b0; } per_phy_cfg[17:17];
+ field { desc = "Per-chip enable bits participate in address decoding."; sw = r; hw = rw; reset = 1'b0; } chip_enable[18:18];
+ field { desc = "CLOCK_CFG controls an implemented backend clock divider."; sw = r; hw = rw; reset = 1'b0; } clock_divider[19:19];
+ field { desc = "FLUSH and APPLY commands implement a staged configuration barrier."; sw = r; hw = rw; reset = 1'b0; } staged_apply[20:20];
+ field { desc = "STATUS reports sticky controller errors."; sw = r; hw = rw; reset = 1'b0; } error_status[21:21];
+ field { desc = "Per-chip RWDS sample timing is implemented."; sw = r; hw = rw; reset = 1'b0; } rwds_sample_timing[22:22];
+ field { desc = "Per-PHY RWDS output-enable timing is implemented."; sw = r; hw = rw; reset = 1'b0; } rwds_oe_timing[23:23];
+ };
+ reg command {
+ desc = "Single-cycle write-one command strobes, active when capability.staged_apply is set; otherwise writes are retained only as inert pulses.";
+ field { sw = rw; hw = r; singlepulse = true; reset = 1'b0; } flush;
+ field { sw = rw; hw = r; singlepulse = true; reset = 1'b0; } apply;
+ };
+ reg status {
+ desc = "Controller status.";
+ field { sw = rw; hw = rw; onwrite = woclr; hwset = true; precedence = hw; reset = 1'b0; } decode_error;
+ field { sw = r; hw = rw; reset = 1'b0; } busy;
+ field { sw = r; hw = rw; reset = 1'b0; } dirty;
+ };
+ reg frontend_cfg {
+ desc = "Frontend configuration. dual_phy must be 0 or 1.";
+ field { sw = rw; hw = r; reset = 1'b1; } dual_phy;
+ };
+ reg clock_cfg {
+ desc = "Backend clock-divider configuration, active when capability.clock_divider is set; divider values must be at least 2.";
+ field { sw = rw; hw = r; reset = 8'd8; } divider[7:0];
+ };
+ reg tx_delay {
+ desc = "PHY transmit delay. PHY 0 is shared when capability.per_phy_cfg is clear.";
+ field { sw = rw; hw = r; reset = 8'h10; } value[7:0];
+ };
+ reg rwds_timing {
+ desc = "PHY RWDS output-enable timing. rwds_oe_setup_cycles must be at most 15 and is active when capability.rwds_oe_timing is set.";
+ field { sw = rw; hw = r; reset = 8'd1; } rwds_oe_setup_cycles[7:0];
+ };
+ reg range_base {
+ desc = "Inclusive 4 MiB-aligned chip address range base.";
field { sw = rw; hw = r; reset = 10'd0; } value[31:22];
};
-
- reg chip0_bound {
- desc = "Exclusive 4 MiB-aligned address for chip-select 0 decoding.";
- field { sw = rw; hw = r; reset = 10'd1; } value[31:22];
- };
-
- reg chip1_base {
- desc = "Inclusive 4 MiB-aligned address for chip-select 1 decoding.";
+ reg range_bound {
+ desc = "Exclusive 4 MiB-aligned chip address range bound.";
field { sw = rw; hw = r; reset = 10'd1; } value[31:22];
};
-
- reg chip1_bound {
- desc = "Exclusive 4 MiB-aligned address for chip-select 1 decoding.";
- field { sw = rw; hw = r; reset = 10'd2; } value[31:22];
- };
-
- reg chip2_base {
- desc = "Inclusive 4 MiB-aligned address for chip-select 2 decoding.";
- field { sw = rw; hw = r; reset = 10'd2; } value[31:22];
- };
-
- reg chip2_bound {
- desc = "Exclusive 4 MiB-aligned address for chip-select 2 decoding.";
- field { sw = rw; hw = r; reset = 10'd3; } value[31:22];
- };
-
- reg chip3_base {
- desc = "Inclusive 4 MiB-aligned address for chip-select 3 decoding.";
- field { sw = rw; hw = r; reset = 10'd3; } value[31:22];
- };
-
- reg chip3_bound {
- desc = "Exclusive 4 MiB-aligned address for chip-select 3 decoding.";
- field { sw = rw; hw = r; reset = 10'd4; } value[31:22];
- };
-
- reg chip4_base {
- desc = "Inclusive 4 MiB-aligned address for chip-select 4 decoding.";
- field { sw = rw; hw = r; reset = 10'd4; } value[31:22];
- };
-
- reg chip4_bound {
- desc = "Exclusive 4 MiB-aligned address for chip-select 4 decoding.";
- field { sw = rw; hw = r; reset = 10'd5; } value[31:22];
- };
-
- reg chip5_base {
- desc = "Inclusive 4 MiB-aligned address for chip-select 5 decoding.";
- field { sw = rw; hw = r; reset = 10'd5; } value[31:22];
- };
-
- reg chip5_bound {
- desc = "Exclusive 4 MiB-aligned address for chip-select 5 decoding.";
- field { sw = rw; hw = r; reset = 10'd6; } value[31:22];
- };
-
- reg chip6_base {
- desc = "Inclusive 4 MiB-aligned address for chip-select 6 decoding.";
- field { sw = rw; hw = r; reset = 10'd6; } value[31:22];
- };
-
- reg chip6_bound {
- desc = "Exclusive 4 MiB-aligned address for chip-select 6 decoding.";
- field { sw = rw; hw = r; reset = 10'd7; } value[31:22];
- };
-
- reg chip7_base {
- desc = "Inclusive 4 MiB-aligned address for chip-select 7 decoding.";
- field { sw = rw; hw = r; reset = 10'd7; } value[31:22];
- };
-
- reg chip7_bound {
- desc = "Exclusive 4 MiB-aligned address for chip-select 7 decoding.";
- field { sw = rw; hw = r; reset = 10'd8; } value[31:22];
- };
-
- t_latency_access t_latency_access @ 0x00;
- en_latency_additional en_latency_additional @ 0x04;
- t_burst_max t_burst_max @ 0x08;
- t_read_write_recovery t_read_write_recovery @ 0x0c;
- t_rx_clk_delay t_rx_clk_delay @ 0x10;
- t_tx_clk_delay t_tx_clk_delay @ 0x14;
- address_mask_msb address_mask_msb @ 0x18;
- address_space address_space @ 0x1c;
- phys_in_use phys_in_use @ 0x20;
- which_phy which_phy @ 0x24;
- t_csh_cycles t_csh_cycles @ 0x28;
- csn_to_ck_cycles csn_to_ck_cycles @ 0x2c;
- chip0_base chip0_base @ 0x30;
- chip0_bound chip0_bound @ 0x34;
- chip1_base chip1_base @ 0x38;
- chip1_bound chip1_bound @ 0x3c;
- chip2_base chip2_base @ 0x40;
- chip2_bound chip2_bound @ 0x44;
- chip3_base chip3_base @ 0x48;
- chip3_bound chip3_bound @ 0x4c;
- chip4_base chip4_base @ 0x58;
- chip4_bound chip4_bound @ 0x5c;
- chip5_base chip5_base @ 0x60;
- chip5_bound chip5_bound @ 0x64;
- chip6_base chip6_base @ 0x68;
- chip6_bound chip6_bound @ 0x6c;
- chip7_base chip7_base @ 0x70;
- chip7_bound chip7_bound @ 0x74;
+ reg address_cfg {
+ desc = "Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.";
+ field { sw = rw; hw = r; reset = 8'd0; } address_space[7:0];
+ field { sw = rw; hw = r; reset = 8'd25; } address_mask_msb[15:8];
+ field { sw = rw; hw = r; reset = 1'b1; } enable[16:16];
+ };
+ reg latency_cfg {
+ desc = "Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.";
+ field { sw = rw; hw = r; reset = 8'd6; } t_latency_access[7:0];
+ field { sw = rw; hw = r; reset = 8'd0; } rwds_sample_delay[15:8];
+ field { sw = rw; hw = r; reset = 1'b0; } en_latency_additional[16:16];
+ };
+ reg burst_cfg {
+ desc = "Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.";
+ field { sw = rw; hw = r; reset = 16'd350; } t_burst_max[15:0];
+ };
+ reg chip_timing {
+ desc = "Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.";
+ field { sw = rw; hw = r; reset = 8'd6; } t_read_write_recovery[7:0];
+ field { sw = rw; hw = r; reset = 8'd1; } t_csh_cycles[15:8];
+ field { sw = rw; hw = r; reset = 8'd0; } csn_to_ck_cycles[23:16];
+ };
+ reg rx_delay {
+ desc = "Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.";
+ field { sw = rw; hw = r; reset = 8'h10; } value[7:0];
+ };
+ reg reserved_top {
+ desc = "Reserved endpoint that fixes the register window size to 4 KiB.";
+ field { sw = r; hw = r; reset = 32'd0; } value[31:0];
+ };
+ regfile phy_regs {
+ tx_delay tx_delay @0x00;
+ rwds_timing rwds_timing @0x04;
+ };
+ regfile chip_regs {
+ range_base range_base @0x00;
+ range_bound range_bound @0x04;
+ address_cfg address_cfg @0x08;
+ latency_cfg latency_cfg @0x0c;
+ burst_cfg burst_cfg @0x10;
+ chip_timing chip_timing @0x14;
+ rx_delay rx_delay @0x18;
+ };
+ regfile global_regs {
+ ip_version ip_version @0x000;
+ reg_if_version reg_if_version @0x004;
+ capability capability @0x008;
+ command command @0x00c;
+ status status @0x010;
+ };
+ regfile frontend_regs {
+ frontend_cfg frontend_cfg @0x000;
+ };
+ regfile backend_regs {
+ clock_cfg clock_cfg @0x000;
+ };
+ global_regs global_cfg @0x000;
+ frontend_regs frontend @0x100;
+ backend_regs backend @0x200;
+ phy_regs phy_0 @0x300;
+ phy_regs phy_1 @0x340;
+ chip_regs chip_0 @0x400;
+ chip_regs chip_1 @0x440;
+ chip_regs chip_2 @0x480;
+ chip_regs chip_3 @0x4c0;
+ chip_regs chip_4 @0x500;
+ chip_regs chip_5 @0x540;
+ chip_regs chip_6 @0x580;
+ chip_regs chip_7 @0x5c0;
+ chip_1.range_base.value->reset = 10'd1;
+ chip_1.range_bound.value->reset = 10'd2;
+ chip_2.range_base.value->reset = 10'd2;
+ chip_2.range_bound.value->reset = 10'd3;
+ chip_3.range_base.value->reset = 10'd3;
+ chip_3.range_bound.value->reset = 10'd4;
+ chip_4.range_base.value->reset = 10'd4;
+ chip_4.range_bound.value->reset = 10'd5;
+ chip_5.range_base.value->reset = 10'd5;
+ chip_5.range_bound.value->reset = 10'd6;
+ chip_6.range_base.value->reset = 10'd6;
+ chip_6.range_bound.value->reset = 10'd7;
+ chip_7.range_base.value->reset = 10'd7;
+ chip_7.range_bound.value->reset = 10'd8;
+ reserved_top reserved_top @0xffc;
};
diff --git a/test/axi_hyper_tb.sv b/test/axi_hyper_tb.sv
index fcd42cd..fd1d57f 100644
--- a/test/axi_hyper_tb.sv
+++ b/test/axi_hyper_tb.sv
@@ -235,6 +235,10 @@ module axi_hyper_tb
// Address Ranges //
////////////////////
localparam axi_addr_t MemRegionStart = axi_addr_t'(32'h8000_0000);
+ localparam logic [31:0] CfgFrontendAddr = 32'h0000_0100;
+ localparam logic [31:0] CfgChip0AddressAddr = 32'h0000_0408;
+ localparam logic [31:0] CfgChip0Memory = 32'h0001_1900;
+ localparam logic [31:0] CfgChip0Register = 32'h0001_1901;
localparam axi_addr_t MemRegionLength = axi_addr_t'(TbDramDataWidth * TbDramLenWidth);
logic s_error;
@@ -378,7 +382,7 @@ module axi_hyper_tb
#600350ns;
// switch memory address space to register space
- reg_master.send_write(32'h7<<2, 1'b1, '1, s_reg_error);
+ reg_master.send_write(CfgChip0AddressAddr, CfgChip0Register, '1, s_reg_error);
if (s_reg_error != 1'b0) $error("unexpected error");
// enable variable latency so we can test RWDS sampling
@@ -386,7 +390,7 @@ module axi_hyper_tb
axi_write_32(32'h8000_0000 + S27KS_CFG0_REG_OFFSET, (s27ks_cfg0 | s27ks_cfg0 << 16));
// switch back to memory address space
- reg_master.send_write(32'h7<<2, 1'b0, '1, s_reg_error);
+ reg_master.send_write(CfgChip0AddressAddr, CfgChip0Memory, '1, s_reg_error);
if (s_reg_error != 1'b0) $error("unexpected error");
check_consecutive_reads(axi_ctrl_mst);
@@ -411,31 +415,7 @@ module axi_hyper_tb
$display("= Use only phy 0 =");
$display("===========================");
- reg_master.send_write(32'h20,1'b0,'1,s_reg_error);
- reg_master.send_write(32'h24,1'b0,'1,s_reg_error);
- if (s_reg_error != 1'b0) $error("unexpected error");
-
- axi_rand_mst.reset();
- axi_ctrl_mst.reset_master();
- check_odd_subword_accesses(axi_ctrl_mst);
-
- $display("===========================");
- $display("= Random AXI transactions =");
- $display("===========================");
-
- axi_rand_mst.run(TbNumReads, TbNumWrites);
-
- $display("===========================");
- $display("= Test finished =");
- $display("===========================");
-
- mst_scoreboard.clear_range(32'h8000_0000, 32'h8000_0000 + ( TbDramDataWidth * TbDramLenWidth ));
-
- $display("===========================");
- $display("= Use only phy 1 =");
- $display("===========================");
-
- reg_master.send_write(32'h24,1'b1,'1,s_reg_error);
+ reg_master.send_write(CfgFrontendAddr, 32'h0, '1, s_reg_error);
if (s_reg_error != 1'b0) $error("unexpected error");
axi_rand_mst.reset();
diff --git a/test/hyperbus_cfg_regs_tb.sv b/test/hyperbus_cfg_regs_tb.sv
index 2209dcb..a9e8f9f 100644
--- a/test/hyperbus_cfg_regs_tb.sv
+++ b/test/hyperbus_cfg_regs_tb.sv
@@ -7,7 +7,7 @@ module hyperbus_cfg_regs_tb;
localparam int unsigned NumChips = 8;
typedef struct packed {
- logic [7:0] addr;
+ logic [31:0] addr;
logic write;
logic [31:0] wdata;
logic [3:0] wstrb;
@@ -34,58 +34,70 @@ module hyperbus_cfg_regs_tb;
hyperbus_pkg::phy_cfg_t phy_cfg;
rule_t [NumChips-1:0] chip_rules;
logic trans_active;
-
- task automatic reg_write(
- input logic [7:0] addr,
- input logic [31:0] data
- );
+ logic cfg_busy;
+ logic decode_error;
+ logic cfg_dirty;
+ logic flush_req;
+ logic apply_req;
+ int unsigned command_pulse_count;
+
+ task automatic reg_write_strobe(input logic [31:0] addr, input logic [31:0] data,
+ input logic [3:0] strb);
+ @(negedge clk);
+ reg_req = '{addr: addr, write: 1'b1, wdata: data, wstrb: strb, valid: 1'b1};
+ do @(posedge clk); while (!reg_rsp.ready);
+ if (reg_rsp.error) $error("Register write to 0x%0h failed", addr);
@(negedge clk);
- reg_req.addr = addr;
- reg_req.write = 1'b1;
- reg_req.wdata = data;
- reg_req.wstrb = '1;
- reg_req.valid = 1'b1;
+ reg_req.valid = 1'b0;
+ endtask
- do begin
- @(posedge clk);
- end while (!reg_rsp.ready);
- if (reg_rsp.error) begin
- $error("Register write to 0x%0h failed", addr);
- end
+ task automatic reg_write(input logic [31:0] addr, input logic [31:0] data);
+ reg_write_strobe(addr, data, 4'b1111);
+ endtask
+ task automatic reg_write_error(input logic [31:0] addr, input logic [31:0] data,
+ input logic [3:0] strb);
+ @(negedge clk);
+ reg_req = '{addr: addr, write: 1'b1, wdata: data, wstrb: strb, valid: 1'b1};
+ do @(posedge clk); while (!reg_rsp.ready);
+ if (!reg_rsp.error) $error("Invalid register write to 0x%0h was accepted", addr);
@(negedge clk);
reg_req.valid = 1'b0;
endtask
- task automatic reg_read(
- input logic [7:0] addr,
- output logic [31:0] data
- );
+ task automatic reg_read(input logic [31:0] addr, output logic [31:0] data);
@(negedge clk);
- reg_req.addr = addr;
- reg_req.write = 1'b0;
- reg_req.wdata = '0;
- reg_req.wstrb = '0;
- reg_req.valid = 1'b1;
-
- do begin
- @(posedge clk);
- end while (!reg_rsp.ready);
+ reg_req = '{addr: addr, write: 1'b0, wdata: '0, wstrb: '0, valid: 1'b1};
+ do @(posedge clk); while (!reg_rsp.ready);
data = reg_rsp.rdata;
- if (reg_rsp.error) begin
- $error("Register read from 0x%0h failed", addr);
- end
+ if (reg_rsp.error) $error("Register read from 0x%0h failed", addr);
+ @(negedge clk);
+ reg_req.valid = 1'b0;
+ endtask
+ task automatic reg_read_error(input logic [31:0] addr);
+ logic [31:0] unused;
+ @(negedge clk);
+ reg_req = '{addr: addr, write: 1'b0, wdata: '0, wstrb: '0, valid: 1'b1};
+ do @(posedge clk); while (!reg_rsp.ready);
+ if (!reg_rsp.error) $error("Unmapped read from 0x%0h was accepted", addr);
+ unused = reg_rsp.rdata;
@(negedge clk);
reg_req.valid = 1'b0;
endtask
always #5ns clk = ~clk;
+ always @(posedge clk) begin
+ if (rst_n && flush_req && apply_req) command_pulse_count++;
+ end
+
hyperbus_cfg_regs #(
.NumChips ( NumChips ),
.NumPhys ( 2 ),
.RegDataWidth ( 32 ),
+ .RegAddrWidth ( 32 ),
+ .CapabilityFeatures ( 8'hff ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.rule_t ( rule_t )
@@ -97,23 +109,73 @@ module hyperbus_cfg_regs_tb;
.frontend_cfg_o ( frontend_cfg ),
.phy_cfg_o ( phy_cfg ),
.chip_rules_o ( chip_rules ),
- .trans_active_i ( trans_active )
+ .trans_active_i ( trans_active ),
+ .cfg_busy_i ( cfg_busy ),
+ .decode_error_i ( decode_error ),
+ .cfg_dirty_i ( cfg_dirty ),
+ .flush_req_o ( flush_req ),
+ .apply_req_o ( apply_req )
);
initial begin : proc_stimulus
- logic [31:0] chip_addr;
- logic [31:0] rx_clk_delay;
- logic [31:0] tx_clk_delay;
+ logic [31:0] data;
clk = 1'b0;
rst_n = 1'b0;
reg_req = '0;
trans_active = 1'b0;
-
+ cfg_busy = 1'b0;
+ decode_error = 1'b0;
+ cfg_dirty = 1'b0;
+ command_pulse_count = 0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (2) @(posedge clk);
+ reg_read(12'h000, data);
+ if (data != 32'h0000_0900) $error("Unexpected IP_VERSION reset: %h", data);
+ reg_read(12'h004, data);
+ if (data != 32'h0001_0000) $error("Unexpected REG_IF_VERSION reset: %h", data);
+ @(negedge clk);
+ reg_req = '{addr: 32'h00c, write: 1'b1, wdata: 32'h3, wstrb: 4'b1111, valid: 1'b1};
+ do @(posedge clk); while (!reg_rsp.ready);
+ if (reg_rsp.error) $error("COMMAND write failed");
+ @(negedge clk);
+ reg_req.valid = 1'b0;
+ repeat (2) @(posedge clk);
+ #1ns;
+ if (command_pulse_count != 1) begin
+ $error("COMMAND strobes were sampled %0d times", command_pulse_count);
+ end
+ if (flush_req || apply_req) $error("COMMAND strobes were not one-cycle pulses");
+ reg_read(12'h00c, data);
+ if (data != 32'h0) $error("COMMAND strobes did not clear after one cycle: %h", data);
+ reg_read(12'h008, data);
+ if (data != 32'h00ff_0208) $error("Unexpected CAPABILITY reset: %h", data);
+ reg_read(12'h010, data);
+ if (data != 32'h0) $error("Unexpected STATUS reset: %h", data);
+ reg_read(12'h100, data);
+ if ((data != 32'h1) || !frontend_cfg.phys_in_use) $error("Unexpected frontend reset");
+ reg_read(12'h200, data);
+ if (data != 32'h8) $error("Unexpected CLOCK_CFG reset: %h", data);
+ reg_write_error(32'h200, 32'h1, 4'b0001);
+ reg_read(32'h200, data);
+ if (data != 32'h8) $error("Invalid divider write modified the register: %h", data);
+ reg_read(12'h300, data);
+ if (data != 32'h10) $error("Unexpected PHY0 TX_DELAY reset: %h", data);
+ reg_read(12'h340, data);
+ if (data != 32'h10) $error("Unexpected PHY1 TX_DELAY reset: %h", data);
+ reg_read(12'h408, data);
+ if (data != 32'h0001_1900) $error("Unexpected chip0 ADDRESS_CFG reset: %h", data);
+ reg_read(12'h40c, data);
+ if (data != 32'h6) $error("Unexpected chip0 LATENCY_CFG reset: %h", data);
+ reg_read(12'h410, data);
+ if (data != 32'd350) $error("Unexpected chip0 BURST_CFG reset: %h", data);
+ reg_read(12'h414, data);
+ if (data != 32'h106) $error("Unexpected chip0 CHIP_TIMING reset: %h", data);
+ reg_read(12'h418, data);
+ if (data != 32'h10) $error("Unexpected chip0 RX_DELAY reset: %h", data);
+
for (int unsigned i = 0; i < NumChips; i++) begin
if ((chip_rules[i].start_addr != i * 32'h0040_0000) ||
(chip_rules[i].end_addr != (i + 1) * 32'h0040_0000)) begin
@@ -121,45 +183,69 @@ module hyperbus_cfg_regs_tb;
end
end
- // Exercise both the fine [4:0] and coarse [7:5] delay settings.
- reg_write(8'h10, 8'hb5);
- reg_write(8'h14, 8'h6a);
- reg_read(8'h10, rx_clk_delay);
- reg_read(8'h14, tx_clk_delay);
- if ((rx_clk_delay != 8'hb5) || (tx_clk_delay != 8'h6a) ||
- (phy_cfg.chip.t_rx_clk_delay != 8'hb5) ||
- (phy_cfg.t_tx_clk_delay != 8'h6a)) begin
- $error("Delay-line configuration fields did not take effect");
- end
-
- // Low address bits are not stored and read back as zero.
- reg_write(8'h70, 32'h8134_5678);
- reg_read(8'h70, chip_addr);
- if ((chip_addr != 32'h8100_0000) ||
- (chip_rules[7].start_addr != 32'h8100_0000)) begin
- $error("Chip address alignment was not applied");
- end
+ reg_write(12'h340, 32'h0000_00a5);
+ reg_read(12'h340, data);
+ if ((data != 8'ha5) || (phy_cfg.t_tx_clk_delay != 8'h10))
+ $error("PHY1 write/read or PHY0 mapping failed");
+ reg_write(12'h300, 32'h0000_005a);
+ if (phy_cfg.t_tx_clk_delay != 8'h5a) $error("PHY0 TX_DELAY mapping failed");
+
+ reg_write(12'h400 + 12'h1c0, 32'h8134_5678);
+ reg_read(12'h400 + 12'h1c0, data);
+ if ((data != 32'h8100_0000) || (chip_rules[7].start_addr != 32'h8100_0000))
+ $error("Chip7 address alignment was not applied");
+
+ reg_write(12'h40c, 32'h0001_0007);
+ reg_read(12'h40c, data);
+ if ((data != 32'h0001_0007) || (phy_cfg.chip.t_latency_access != 7) ||
+ !phy_cfg.chip.en_latency_additional) $error("Chip0 latency mapping failed");
+ reg_write(12'h414, 32'h0000_010a);
+ reg_write_strobe(32'h414, 32'h0000_0007, 4'b0001);
+ reg_read(32'h414, data);
+ if (data != 32'h0000_0107) $error("Partial timing write failed: %h", data);
+ reg_write_error(32'h414, 32'h0000_0010, 4'b0001);
+ reg_read(32'h414, data);
+ if (data != 32'h0000_0107) $error("Invalid timing write modified the register: %h", data);
+ reg_write_error(32'h40c, 32'h0000_0002, 4'b0001);
+ reg_read(32'h40c, data);
+ if (data != 32'h0001_0007) $error("Invalid latency write modified the register: %h", data);
+ reg_read_error(12'h415);
+
+ reg_read_error(12'h104);
+ reg_read_error(32'h0000_1000);
+ reg_read(12'hffc, data);
+ if (data != '0) $error("Reserved endpoint did not read as zero");
- // A new configuration access must wait for an active transfer to finish.
+ trans_active = 1'b1;
+ cfg_busy = 1'b1;
+ reg_read(32'h010, data);
+ if ((data & 32'h2) == 0) $error("STATUS read was blocked during active transfer");
+ decode_error = 1'b1;
+ cfg_dirty = 1'b1;
+ reg_read(32'h010, data);
+ if ((data & 32'h5) != 32'h5) $error("STATUS hardware bits were not set: %h", data);
+ trans_active = 1'b0;
+ reg_write(32'h010, 32'h1);
+ reg_read(32'h010, data);
+ if ((data & 32'h1) == 0) $error("STATUS hwset did not win over W1C");
+ decode_error = 1'b0;
+ cfg_dirty = 1'b0;
+ reg_write(32'h010, 32'h1);
+ reg_read(32'h010, data);
+ if ((data & 32'h1) != 0) $error("STATUS W1C did not clear decode_error");
trans_active = 1'b1;
@(negedge clk);
- reg_req.addr = 8'h00;
- reg_req.write = 1'b0;
- reg_req.valid = 1'b1;
+ reg_req = '{addr: 32'h000, write: 1'b0, wdata: '0, wstrb: '0, valid: 1'b1};
repeat (3) begin
@(posedge clk);
- if (reg_rsp.ready) begin
- $error("Configuration access completed during an active transfer");
- end
+ if (reg_rsp.ready) $error("Access completed during active transfer");
end
trans_active = 1'b0;
- do begin
- @(posedge clk);
- end while (!reg_rsp.ready);
+ cfg_busy = 1'b0;
+ do @(posedge clk); while (!reg_rsp.ready);
@(negedge clk);
reg_req.valid = 1'b0;
$finish;
end
-
endmodule