Thinking about an internal divider to create an arbitrary clock waveform.
An input clock is needed to generate the PHY clock. The source of this clock could be a dedicated FLL, but if it is not available it could be the system clock.
The idea is to have a clock that has a frequency x2 with respect the PHY clock so to easily manage the double data rate. The negedge of the x2 clock can be used to generate the CK/CK_N signal to have proper skew between bus clock and data to allow the receiver to sample data properly.
If the input clock available has a frequency that is pretty higher than the PHY one, the idea is to have a divider with programmable duty cycle to have a kind of flexibility on this skew, that could be further refined with a delay line.
For example let's consider a 1 GHz input clock. In order to have a 200 MHz PHY clock, a 400 MHz is required for the DDR, meaning a 2.5 divider.
A 2.5 divider is feasible, but it cannot have a 50% dutycycle. For this application this may not be an issue, but a feature. The duty cycle if programmale can give flexibility to the skew between CK and output data on write protocol
10101010101010101010 1 GHz input clock
10000100001000010000 400 MHz x2 PHY clock with 20% duty cycle
11000110001100011000 400 MHz x2 PHY clock with 40% duty cycle
11100111001110011100 400 MHz x2 PHY clock with 60% duty cycle
11110111101111011110 400 MHz x2 PHY clock with 80% duty cycle
For all above 4 cases the PHY clock is always the same, 200 MHz, 50% duty cycle
11111000001111100000 200 MHz PHY clock with 50% duty cycle
Notes: This kind of divider uses both edges of the input clock. If the input clock is not a 50% duty-cycle, this could lead to some jitter for the DDR. To evaluate.
Thinking about an internal divider to create an arbitrary clock waveform.
An input clock is needed to generate the PHY clock. The source of this clock could be a dedicated FLL, but if it is not available it could be the system clock.
The idea is to have a clock that has a frequency x2 with respect the PHY clock so to easily manage the double data rate. The negedge of the x2 clock can be used to generate the CK/CK_N signal to have proper skew between bus clock and data to allow the receiver to sample data properly.
If the input clock available has a frequency that is pretty higher than the PHY one, the idea is to have a divider with programmable duty cycle to have a kind of flexibility on this skew, that could be further refined with a delay line.
For example let's consider a 1 GHz input clock. In order to have a 200 MHz PHY clock, a 400 MHz is required for the DDR, meaning a 2.5 divider.
A 2.5 divider is feasible, but it cannot have a 50% dutycycle. For this application this may not be an issue, but a feature. The duty cycle if programmale can give flexibility to the skew between CK and output data on write protocol
10101010101010101010 1 GHz input clock10000100001000010000 400 MHz x2 PHY clock with 20% duty cycle11000110001100011000 400 MHz x2 PHY clock with 40% duty cycle11100111001110011100 400 MHz x2 PHY clock with 60% duty cycle11110111101111011110 400 MHz x2 PHY clock with 80% duty cycleFor all above 4 cases the PHY clock is always the same, 200 MHz, 50% duty cycle
11111000001111100000 200 MHz PHY clock with 50% duty cycleNotes: This kind of divider uses both edges of the input clock. If the input clock is not a 50% duty-cycle, this could lead to some jitter for the DDR. To evaluate.