profilingv1gpu.md

Streaming output truncated to the last 5000 lines.
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.75
    Achieved Active Warps Per SM           warp         7.92
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.25%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.8%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     2,318.50
    Total DRAM Elapsed Cycles        cycle      188,416
    Average L1 Active Cycles         cycle     1,233.25
    Total L1 Elapsed Cycles          cycle      111,480
    Average L2 Active Cycles         cycle       864.56
    Total L2 Elapsed Cycles          cycle      131,904
    Average SM Active Cycles         cycle     1,233.25
    Total SM Elapsed Cycles          cycle      111,480
    Average SMSP Active Cycles       cycle     1,244.81
    Total SMSP Elapsed Cycles        cycle      445,920
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.907%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 22.39% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 11.47%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 25.68% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.907%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 22.39% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.972%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 33.24% above the average, while the minimum instance value is 28.40% below the      
          average.                                                                                                      

  relu_backward_kernel(float *, float *, float *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.73
    SM Frequency                    Mhz       573.16
    Elapsed Cycles                cycle        2,625
    Memory Throughput                 %         5.68
    DRAM Throughput                   %         5.68
    Duration                         us         4.58
    L1/TEX Cache Throughput           %         4.88
    L2 Cache Throughput               %         3.22
    SM Active Cycles              cycle     1,048.62
    Compute (SM) Throughput           %         2.00
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        25.40
    Achieved Active Warps Per SM           warp         8.13
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 74.6%                                                                                     
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (25.4%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        1,228
    Total DRAM Elapsed Cycles        cycle      173,056
    Average L1 Active Cycles         cycle     1,048.62
    Total L1 Elapsed Cycles          cycle      102,392
    Average L2 Active Cycles         cycle       857.81
    Total L2 Elapsed Cycles          cycle      122,848
    Average SM Active Cycles         cycle     1,048.62
    Total SM Elapsed Cycles          cycle      102,392
    Average SMSP Active Cycles       cycle     1,013.09
    Total SMSP Elapsed Cycles        cycle      409,568
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.564%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 23.35% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.248%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 23.37% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.564%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 23.35% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.061%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 22.65% above the average, while the minimum instance value is 20.38% below the      
          average.                                                                                                      

  conv2d_backward_naive_kernel(float *, float *, float *, float *, float *, float *, int, int, int, int, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.98
    SM Frequency                    Mhz       584.98
    Elapsed Cycles                cycle    1,840,607
    Memory Throughput                 %        33.73
    DRAM Throughput                   %         0.28
    Duration                         ms         3.15
    L1/TEX Cache Throughput           %        67.47
    L2 Cache Throughput               %        19.95
    SM Active Cycles              cycle 1,090,481.70
    Compute (SM) Throughput           %        14.83
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              42
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        23.97
    Achieved Active Warps Per SM           warp         7.67
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 76.03%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    43,829.50
    Total DRAM Elapsed Cycles        cycle  125,461,504
    Average L1 Active Cycles         cycle 1,090,481.70
    Total L1 Elapsed Cycles          cycle   73,633,144
    Average L2 Active Cycles         cycle 2,471,036.56
    Total L2 Elapsed Cycles          cycle   86,083,712
    Average SM Active Cycles         cycle 1,090,481.70
    Total SM Elapsed Cycles          cycle   73,633,144
    Average SMSP Active Cycles       cycle 1,089,423.04
    Total SMSP Elapsed Cycles        cycle  294,532,576
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 24.08%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 40.65% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 24.09%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 40.70% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 24.08%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 40.65% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  maxpool_backward_kernel(float *, float *, int *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.85
    SM Frequency                    Mhz       577.38
    Elapsed Cycles                cycle        2,626
    Memory Throughput                 %        17.11
    DRAM Throughput                   %        17.11
    Duration                         us         4.54
    L1/TEX Cache Throughput           %        10.94
    L2 Cache Throughput               %         5.11
    SM Active Cycles              cycle     1,056.53
    Compute (SM) Throughput           %         2.01
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.48
    Achieved Active Warps Per SM           warp         7.83
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.52%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        3,766
    Total DRAM Elapsed Cycles        cycle      176,128
    Average L1 Active Cycles         cycle     1,056.53
    Total L1 Elapsed Cycles          cycle      101,776
    Average L2 Active Cycles         cycle     1,323.81
    Total L2 Elapsed Cycles          cycle      123,168
    Average SM Active Cycles         cycle     1,056.53
    Total SM Elapsed Cycles          cycle      101,776
    Average SMSP Active Cycles       cycle     1,026.92
    Total SMSP Elapsed Cycles        cycle      407,104
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.313%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 22.43% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.659%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 23.93% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.313%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 22.43% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 7.113%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 20.68% above the average, while the minimum instance value is 14.94% below the      
          average.                                                                                                      

  relu_backward_kernel(float *, float *, float *, int) (128, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.76
    SM Frequency                    Mhz       574.92
    Elapsed Cycles                cycle        3,019
    Memory Throughput                 %        18.62
    DRAM Throughput                   %        18.62
    Duration                         us         5.25
    L1/TEX Cache Throughput           %        13.17
    L2 Cache Throughput               %         9.75
    SM Active Cycles              cycle     1,555.47
    Compute (SM) Throughput           %         7.01
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        77.36
    Achieved Active Warps Per SM           warp        24.76
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 22.64%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (77.4%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     4,647.50
    Total DRAM Elapsed Cycles        cycle      199,680
    Average L1 Active Cycles         cycle     1,555.47
    Total L1 Elapsed Cycles          cycle      116,808
    Average L2 Active Cycles         cycle     1,656.44
    Total L2 Elapsed Cycles          cycle      141,792
    Average SM Active Cycles         cycle     1,555.47
    Total SM Elapsed Cycles          cycle      116,808
    Average SMSP Active Cycles       cycle     1,502.86
    Total SMSP Elapsed Cycles        cycle      467,232
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.178%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 10.06% above the average, while the minimum instance value is 12.50% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.514%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 17.43% above the average, while the minimum instance value is 11.32% below the      
          average.                                                                                                      

  conv2d_backward_naive_kernel(float *, float *, float *, float *, float *, float *, int, int, int, int, int) (128, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- -------------
    Metric Name             Metric Unit  Metric Value
    ----------------------- ----------- -------------
    DRAM Frequency                  Ghz          5.00
    SM Frequency                    Mhz        585.00
    Elapsed Cycles                cycle    12,604,307
    Memory Throughput                 %         42.48
    DRAM Throughput                   %          0.10
    Duration                         ms         21.55
    L1/TEX Cache Throughput           %         84.96
    L2 Cache Throughput               %         25.73
    SM Active Cycles              cycle 10,673,739.57
    Compute (SM) Throughput           %         18.82
    ----------------------- ----------- -------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              42
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        57.67
    Achieved Active Warps Per SM           warp        18.45
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 42.33%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (57.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- -------------
    Metric Name                Metric Unit  Metric Value
    -------------------------- ----------- -------------
    Average DRAM Active Cycles       cycle    110,739.50
    Total DRAM Elapsed Cycles        cycle   861,163,520
    Average L1 Active Cycles         cycle 10,673,739.57
    Total L1 Elapsed Cycles          cycle   504,283,928
    Average L2 Active Cycles         cycle 17,198,882.09
    Total L2 Elapsed Cycles          cycle   589,493,728
    Average SM Active Cycles         cycle 10,673,739.57
    Total SM Elapsed Cycles          cycle   504,283,928
    Average SMSP Active Cycles       cycle 10,671,910.97
    Total SMSP Elapsed Cycles        cycle 2,017,135,712
    -------------------------- ----------- -------------

    OPT   Est. Speedup: 12.93%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 15.28% above the average, while the minimum instance value is 11.19% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.96%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 15.31% above the average, while the minimum instance value is 11.24% below the      
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.93%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 15.28% above the average, while the minimum instance value is 11.19% below the      
          average.                                                                                                      

  maxpool_backward_kernel(float *, float *, int *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.61
    SM Frequency                    Mhz       577.82
    Elapsed Cycles                cycle        5,460
    Memory Throughput                 %        69.27
    DRAM Throughput                   %        69.27
    Duration                         us         9.44
    L1/TEX Cache Throughput           %        33.63
    L2 Cache Throughput               %        17.71
    SM Active Cycles              cycle     3,563.78
    Compute (SM) Throughput           %         7.99
    ----------------------- ----------- ------------

    OPT   Memory is more heavily utilized than Compute: Look at the Memory Workload Analysis section to identify the    
          DRAM bottleneck. Check memory replay (coalescing) metrics to make sure you're efficiently utilizing the       
          bytes transferred. Also consider whether it is possible to do more work per memory access (kernel fusion) or  
          whether there are values you can (re)compute.                                                                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 50%                                                                                             
          A wave of thread blocks is defined as the maximum number of blocks that can be executed in parallel on the    
          target GPU. The number of blocks in a wave depends on the number of multiprocessors and the theoretical       
          occupancy of the kernel. This kernel launch results in 1 full waves and a partial wave of 96 thread blocks.   
          Under the assumption of a uniform execution duration of all thread blocks, the partial wave may account for   
          up to 50.0% of the total kernel runtime with a lower occupancy of 23.9%. Try launching a grid with no         
          partial wave. The overall impact of this tail effect also lessens with the number of full waves executed for  
          a grid. See the Hardware Model                                                                                
          (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model) description for more      
          details on launch configurations.                                                                             

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        76.12
    Achieved Active Warps Per SM           warp        24.36
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 23.88%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (76.1%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       30,148
    Total DRAM Elapsed Cycles        cycle      348,160
    Average L1 Active Cycles         cycle     3,563.78
    Total L1 Elapsed Cycles          cycle      204,944
    Average L2 Active Cycles         cycle     5,418.53
    Total L2 Elapsed Cycles          cycle      256,096
    Average SM Active Cycles         cycle     3,563.78
    Total SM Elapsed Cycles          cycle      204,944
    Average SMSP Active Cycles       cycle     3,491.36
    Total SMSP Elapsed Cycles        cycle      819,776
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 6.54%                                                                                           
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Additionally, other SMSPs have a much lower number of active cycles than the average number of active         
          cycles. Maximum instance value is 9.60% above the average, while the minimum instance value is 10.95% below   
          the average.                                                                                                  

  relu_backward_kernel(float *, float *, float *, int) (1024, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.63
    SM Frequency                    Mhz       582.95
    Elapsed Cycles                cycle        9,665
    Memory Throughput                 %        55.43
    DRAM Throughput                   %        55.43
    Duration                         us        16.58
    L1/TEX Cache Throughput           %        23.76
    L2 Cache Throughput               %        22.05
    SM Active Cycles              cycle     7,368.50
    Compute (SM) Throughput           %        18.28
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        89.54
    Achieved Active Warps Per SM           warp        28.65
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 10.46%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (89.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       42,574
    Total DRAM Elapsed Cycles        cycle      614,400
    Average L1 Active Cycles         cycle     7,368.50
    Total L1 Elapsed Cycles          cycle      358,512
    Average L2 Active Cycles         cycle    10,275.47
    Total L2 Elapsed Cycles          cycle      452,640
    Average SM Active Cycles         cycle     7,368.50
    Total SM Elapsed Cycles          cycle      358,512
    Average SMSP Active Cycles       cycle     7,296.68
    Total SMSP Elapsed Cycles        cycle    1,434,048
    -------------------------- ----------- ------------

  conv2d_backward_naive_kernel(float *, float *, float *, float *, float *, float *, int, int, int, int, int) (1024, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.03
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle    2,494,543
    Memory Throughput                 %        17.44
    DRAM Throughput                   %         0.11
    Duration                         ms         4.26
    L1/TEX Cache Throughput           %        34.88
    L2 Cache Throughput               %        14.91
    SM Active Cycles              cycle 2,454,758.58
    Compute (SM) Throughput           %         8.52
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              42
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        94.65
    Achieved Active Warps Per SM           warp        30.29
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    22,886.50
    Total DRAM Elapsed Cycles        cycle  171,470,848
    Average L1 Active Cycles         cycle 2,454,758.58
    Total L1 Elapsed Cycles          cycle   99,681,552
    Average L2 Active Cycles         cycle 2,642,874.47
    Total L2 Elapsed Cycles          cycle  116,667,648
    Average SM Active Cycles         cycle 2,454,758.58
    Total SM Elapsed Cycles          cycle   99,681,552
    Average SMSP Active Cycles       cycle 2,461,981.30
    Total SMSP Elapsed Cycles        cycle  398,726,208
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 15.82%                                                                                          
          One or more L2 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 21.82% above the average, while the minimum instance value is 27.92% below the      
          average.                                                                                                      

  conv2d_naive_kernel(float *, float *, float *, float *, int, int, int, int, int) (1024, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.97
    SM Frequency                    Mhz       584.88
    Elapsed Cycles                cycle       97,574
    Memory Throughput                 %        47.61
    DRAM Throughput                   %         0.57
    Duration                         us       166.82
    L1/TEX Cache Throughput           %        95.23
    L2 Cache Throughput               %         1.66
    SM Active Cycles              cycle    94,252.45
    Compute (SM) Throughput           %        26.82
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              41
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        93.33
    Achieved Active Warps Per SM           warp        29.86
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        4,726
    Total DRAM Elapsed Cycles        cycle    6,635,520
    Average L1 Active Cycles         cycle    94,252.45
    Total L1 Elapsed Cycles          cycle    3,873,232
    Average L2 Active Cycles         cycle    20,697.28
    Total L2 Elapsed Cycles          cycle    4,562,560
    Average SM Active Cycles         cycle    94,252.45
    Total SM Elapsed Cycles          cycle    3,873,232
    Average SMSP Active Cycles       cycle    94,132.27
    Total SMSP Elapsed Cycles        cycle   15,492,928
    -------------------------- ----------- ------------

  relu_forward_kernel(float *, float *, int) (1024, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.69
    SM Frequency                    Mhz       581.06
    Elapsed Cycles                cycle        6,605
    Memory Throughput                 %        41.52
    DRAM Throughput                   %        41.52
    Duration                         us        11.36
    L1/TEX Cache Throughput           %        30.02
    L2 Cache Throughput               %        21.61
    SM Active Cycles              cycle     4,861.55
    Compute (SM) Throughput           %        19.72
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        80.01
    Achieved Active Warps Per SM           warp        25.60
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 19.99%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (80.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       22,107
    Total DRAM Elapsed Cycles        cycle      425,984
    Average L1 Active Cycles         cycle     4,861.55
    Total L1 Elapsed Cycles          cycle      249,304
    Average L2 Active Cycles         cycle     6,435.59
    Total L2 Elapsed Cycles          cycle      309,632
    Average SM Active Cycles         cycle     4,861.55
    Total SM Elapsed Cycles          cycle      249,304
    Average SMSP Active Cycles       cycle     4,866.92
    Total SMSP Elapsed Cycles        cycle      997,216
    -------------------------- ----------- ------------

  maxpool_forward_kernel(float *, float *, int *, int, int, int, int, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.73
    SM Frequency                    Mhz       578.54
    Elapsed Cycles                cycle        5,264
    Memory Throughput                 %        44.97
    DRAM Throughput                   %        44.97
    Duration                         us         9.09
    L1/TEX Cache Throughput           %        22.70
    L2 Cache Throughput               %        20.65
    SM Active Cycles              cycle     3,609.38
    Compute (SM) Throughput           %        30.50
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              19
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        81.70
    Achieved Active Warps Per SM           warp        26.14
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 18.3%                                                                                     
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (81.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       19,340
    Total DRAM Elapsed Cycles        cycle      344,064
    Average L1 Active Cycles         cycle     3,609.38
    Total L1 Elapsed Cycles          cycle      199,808
    Average L2 Active Cycles         cycle     4,022.22
    Total L2 Elapsed Cycles          cycle      247,232
    Average SM Active Cycles         cycle     3,609.38
    Total SM Elapsed Cycles          cycle      199,808
    Average SMSP Active Cycles       cycle     3,548.01
    Total SMSP Elapsed Cycles        cycle      799,232
    -------------------------- ----------- ------------

  conv2d_naive_kernel(float *, float *, float *, float *, int, int, int, int, int) (128, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle    4,132,166
    Memory Throughput                 %        43.52
    DRAM Throughput                   %         0.13
    Duration                         ms         7.06
    L1/TEX Cache Throughput           %        87.05
    L2 Cache Throughput               %         5.71
    SM Active Cycles              cycle 3,550,420.95
    Compute (SM) Throughput           %         5.52
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              41
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        57.14
    Achieved Active Warps Per SM           warp        18.29
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 42.86%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (57.1%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       45,719
    Total DRAM Elapsed Cycles        cycle  282,196,992
    Average L1 Active Cycles         cycle 3,550,420.95
    Total L1 Elapsed Cycles          cycle  165,247,128
    Average L2 Active Cycles         cycle 4,323,863.06
    Total L2 Elapsed Cycles          cycle  193,258,208
    Average SM Active Cycles         cycle 3,550,420.95
    Total SM Elapsed Cycles          cycle  165,247,128
    Average SMSP Active Cycles       cycle 3,545,635.42
    Total SMSP Elapsed Cycles        cycle  660,988,512
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 12.02%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 13.98% above the average, while the minimum instance value is 11.53% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.14%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 14.14% above the average, while the minimum instance value is 11.59% below the      
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.02%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 13.98% above the average, while the minimum instance value is 11.53% below the      
          average.                                                                                                      

  relu_forward_kernel(float *, float *, int) (128, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.78
    SM Frequency                    Mhz       572.69
    Elapsed Cycles                cycle        2,532
    Memory Throughput                 %        10.89
    DRAM Throughput                   %        10.89
    Duration                         us         4.42
    L1/TEX Cache Throughput           %        13.25
    L2 Cache Throughput               %         7.86
    SM Active Cycles              cycle     1,159.15
    Compute (SM) Throughput           %         6.21
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        74.47
    Achieved Active Warps Per SM           warp        23.83
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 25.53%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (74.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        2,301
    Total DRAM Elapsed Cycles        cycle      168,960
    Average L1 Active Cycles         cycle     1,159.15
    Total L1 Elapsed Cycles          cycle       98,952
    Average L2 Active Cycles         cycle     1,068.47
    Total L2 Elapsed Cycles          cycle      118,912
    Average SM Active Cycles         cycle     1,159.15
    Total SM Elapsed Cycles          cycle       98,952
    Average SMSP Active Cycles       cycle     1,133.89
    Total SMSP Elapsed Cycles        cycle      395,808
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 6.047%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 21.03% above the average, while the minimum instance value is 17.08% below the      
          average.                                                                                                      

  maxpool_forward_kernel(float *, float *, int *, int, int, int, int, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.90
    SM Frequency                    Mhz       573.75
    Elapsed Cycles                cycle        2,940
    Memory Throughput                 %         9.62
    DRAM Throughput                   %         9.62
    Duration                         us         5.12
    L1/TEX Cache Throughput           %         7.73
    L2 Cache Throughput               %         5.61
    SM Active Cycles              cycle     1,325.08
    Compute (SM) Throughput           %         6.74
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              19
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.17
    Achieved Active Warps Per SM           warp         7.73
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.83%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.2%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     2,412.50
    Total DRAM Elapsed Cycles        cycle      200,704
    Average L1 Active Cycles         cycle     1,325.08
    Total L1 Elapsed Cycles          cycle      116,832
    Average L2 Active Cycles         cycle     1,034.50
    Total L2 Elapsed Cycles          cycle      138,016
    Average SM Active Cycles         cycle     1,325.08
    Total SM Elapsed Cycles          cycle      116,832
    Average SMSP Active Cycles       cycle     1,259.49
    Total SMSP Elapsed Cycles        cycle      467,328
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 10.76%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 23.71% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.44%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 24.22% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.76%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 23.71% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.109%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 25.47% above the average, while the minimum instance value is 17.45% below the      
          average.                                                                                                      

  conv2d_naive_kernel(float *, float *, float *, float *, int, int, int, int, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.96
    Elapsed Cycles                cycle      612,723
    Memory Throughput                 %        33.63
    DRAM Throughput                   %         0.38
    Duration                         ms         1.05
    L1/TEX Cache Throughput           %        67.25
    L2 Cache Throughput               %         3.07
    SM Active Cycles              cycle   349,250.55
    Compute (SM) Throughput           %         4.52
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              41
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.29
    Achieved Active Warps Per SM           warp         7.77
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.71%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.3%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       19,823
    Total DRAM Elapsed Cycles        cycle   41,870,336
    Average L1 Active Cycles         cycle   349,250.55
    Total L1 Elapsed Cycles          cycle   24,503,032
    Average L2 Active Cycles         cycle   457,260.94
    Total L2 Elapsed Cycles          cycle   28,656,608
    Average SM Active Cycles         cycle   349,250.55
    Total SM Elapsed Cycles          cycle   24,503,032
    Average SMSP Active Cycles       cycle   348,853.85
    Total SMSP Elapsed Cycles        cycle   98,012,128
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 24.43%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 42.84% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 24.45%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 42.94% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 24.43%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 42.84% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  relu_forward_kernel(float *, float *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.83
    SM Frequency                    Mhz       574.17
    Elapsed Cycles                cycle        2,206
    Memory Throughput                 %         3.35
    DRAM Throughput                   %         3.35
    Duration                         us         3.84
    L1/TEX Cache Throughput           %         4.94
    L2 Cache Throughput               %         2.87
    SM Active Cycles              cycle       778.08
    Compute (SM) Throughput           %         1.76
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.91
    Achieved Active Warps Per SM           warp         7.97
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.09%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle          621
    Total DRAM Elapsed Cycles        cycle      148,480
    Average L1 Active Cycles         cycle       778.08
    Total L1 Elapsed Cycles          cycle       87,416
    Average L2 Active Cycles         cycle       560.38
    Total L2 Elapsed Cycles          cycle      103,200
    Average SM Active Cycles         cycle       778.08
    Total SM Elapsed Cycles          cycle       87,416
    Average SMSP Active Cycles       cycle       765.84
    Total SMSP Elapsed Cycles        cycle      349,664
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.311%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 23.34% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.313%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 23.72% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.311%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 23.34% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.715%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 32.89% above the average, while the minimum instance value is 29.69% below the      
          average.                                                                                                      

  upsample_forward_kernel(float *, float *, int, int, int, int, int) (128, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.92
    SM Frequency                    Mhz       573.28
    Elapsed Cycles                cycle        2,864
    Memory Throughput                 %         5.54
    DRAM Throughput                   %         2.92
    Duration                         us         4.99
    L1/TEX Cache Throughput           %         9.67
    L2 Cache Throughput               %         5.54
    SM Active Cycles              cycle     1,588.83
    Compute (SM) Throughput           %        17.87
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        72.30
    Achieved Active Warps Per SM           warp        23.14
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 27.7%                                                                                     
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (72.3%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       716.50
    Total DRAM Elapsed Cycles        cycle      196,608
    Average L1 Active Cycles         cycle     1,588.83
    Total L1 Elapsed Cycles          cycle      113,640
    Average L2 Active Cycles         cycle     1,043.91
    Total L2 Elapsed Cycles          cycle      134,464
    Average SM Active Cycles         cycle     1,588.83
    Total SM Elapsed Cycles          cycle      113,640
    Average SMSP Active Cycles       cycle     1,555.57
    Total SMSP Elapsed Cycles        cycle      454,560
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 7.646%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 30.78% above the average, while the minimum instance value is 14.36% below the      
          average.                                                                                                      

  conv2d_naive_kernel(float *, float *, float *, float *, int, int, int, int, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       585.00
    Elapsed Cycles                cycle    3,736,267
    Memory Throughput                 %        48.53
    DRAM Throughput                   %         0.13
    Duration                         ms         6.39
    L1/TEX Cache Throughput           %        97.05
    L2 Cache Throughput               %        15.74
    SM Active Cycles              cycle 3,599,871.95
    Compute (SM) Throughput           %         6.13
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              41
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        81.01
    Achieved Active Warps Per SM           warp        25.92
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 18.99%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (81.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       42,828
    Total DRAM Elapsed Cycles        cycle  255,119,360
    Average L1 Active Cycles         cycle 3,599,871.95
    Total L1 Elapsed Cycles          cycle  148,930,288
    Average L2 Active Cycles         cycle 5,312,803.75
    Total L2 Elapsed Cycles          cycle  174,742,368
    Average SM Active Cycles         cycle 3,599,871.95
    Total SM Elapsed Cycles          cycle  148,930,288
    Average SMSP Active Cycles       cycle 3,603,198.59
    Total SMSP Elapsed Cycles        cycle  595,721,152
    -------------------------- ----------- ------------

  relu_forward_kernel(float *, float *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.92
    SM Frequency                    Mhz       577.26
    Elapsed Cycles                cycle        3,126
    Memory Throughput                 %        17.28
    DRAM Throughput                   %        17.28
    Duration                         us         5.41
    L1/TEX Cache Throughput           %        17.69
    L2 Cache Throughput               %        12.28
    SM Active Cycles              cycle     1,736.53
    Compute (SM) Throughput           %         9.93
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 50%                                                                                             
          A wave of thread blocks is defined as the maximum number of blocks that can be executed in parallel on the    
          target GPU. The number of blocks in a wave depends on the number of multiprocessors and the theoretical       
          occupancy of the kernel. This kernel launch results in 1 full waves and a partial wave of 96 thread blocks.   
          Under the assumption of a uniform execution duration of all thread blocks, the partial wave may account for   
          up to 50.0% of the total kernel runtime with a lower occupancy of 20.6%. Try launching a grid with no         
          partial wave. The overall impact of this tail effect also lessens with the number of full waves executed for  
          a grid. See the Hardware Model                                                                                
          (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model) description for more      
          details on launch configurations.                                                                             

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        79.45
    Achieved Active Warps Per SM           warp        25.42
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 20.55%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (79.4%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        4,600
    Total DRAM Elapsed Cycles        cycle      212,992
    Average L1 Active Cycles         cycle     1,736.53
    Total L1 Elapsed Cycles          cycle      123,728
    Average L2 Active Cycles         cycle        1,960
    Total L2 Elapsed Cycles          cycle      146,688
    Average SM Active Cycles         cycle     1,736.53
    Total SM Elapsed Cycles          cycle      123,728
    Average SMSP Active Cycles       cycle     1,706.08
    Total SMSP Elapsed Cycles        cycle      494,912
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.042%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 11.79% above the average, while the minimum instance value is 7.96% below the       
          average.                                                                                                      

  upsample_forward_kernel(float *, float *, int, int, int, int, int) (1024, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.93
    SM Frequency                    Mhz       580.71
    Elapsed Cycles                cycle        8,574
    Memory Throughput                 %        15.91
    DRAM Throughput                   %        11.75
    Duration                         us        14.75
    L1/TEX Cache Throughput           %        22.18
    L2 Cache Throughput               %        15.91
    SM Active Cycles              cycle     7,043.48
    Compute (SM) Throughput           %        44.80
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        81.77
    Achieved Active Warps Per SM           warp        26.17
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 18.23%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (81.8%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        8,542
    Total DRAM Elapsed Cycles        cycle      581,632
    Average L1 Active Cycles         cycle     7,043.48
    Total L1 Elapsed Cycles          cycle      338,200
    Average L2 Active Cycles         cycle     7,329.25
    Total L2 Elapsed Cycles          cycle      401,728
    Average SM Active Cycles         cycle     7,043.48
    Total SM Elapsed Cycles          cycle      338,200
    Average SMSP Active Cycles       cycle     7,020.27
    Total SMSP Elapsed Cycles        cycle    1,352,800
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.352%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 9.17% above the average, while the minimum instance value is 4.98% below the        
          average.                                                                                                      

  conv2d_naive_kernel(float *, float *, float *, float *, int, int, int, int, int) (12, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.92
    Elapsed Cycles                cycle      295,737
    Memory Throughput                 %        25.94
    DRAM Throughput                   %         1.33
    Duration                         us       505.60
    L1/TEX Cache Throughput           %        88.38
    L2 Cache Throughput               %         0.50
    SM Active Cycles              cycle    86,702.62
    Compute (SM) Throughput           %         7.44
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              41
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.92
    Achieved Active Warps Per SM           warp         7.97
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.08%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    33,696.50
    Total DRAM Elapsed Cycles        cycle   20,217,856
    Average L1 Active Cycles         cycle    86,702.62
    Total L1 Elapsed Cycles          cycle   11,817,464
    Average L2 Active Cycles         cycle    95,812.69
    Total L2 Elapsed Cycles          cycle   13,831,200
    Average SM Active Cycles         cycle    86,702.62
    Total SM Elapsed Cycles          cycle   11,817,464
    Average SMSP Active Cycles       cycle    86,474.48
    Total SMSP Elapsed Cycles        cycle   47,269,856
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 20.71%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 70.58% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.66%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 70.59% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.71%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 70.58% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  mse_loss_kernel(const float *, const float *, float *, int) (12, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.90
    SM Frequency                    Mhz       581.87
    Elapsed Cycles                cycle        8,324
    Memory Throughput                 %         1.67
    DRAM Throughput                   %         0.69
    Duration                         us        14.30
    L1/TEX Cache Throughput           %        11.00
    L2 Cache Throughput               %         1.67
    SM Active Cycles              cycle       763.55
    Compute (SM) Throughput           %         0.93
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        14.23
    Achieved Active Warps Per SM           warp         4.56
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 85.77%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (14.2%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle          482
    Total DRAM Elapsed Cycles        cycle      561,152
    Average L1 Active Cycles         cycle       763.55
    Total L1 Elapsed Cycles          cycle      330,168
    Average L2 Active Cycles         cycle       660.97
    Total L2 Elapsed Cycles          cycle      389,280
    Average SM Active Cycles         cycle       763.55
    Total SM Elapsed Cycles          cycle      330,168
    Average SMSP Active Cycles       cycle       511.18
    Total SMSP Elapsed Cycles        cycle    1,320,672
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 7.243%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 78.30% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.306%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 85.68% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 7.243%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 78.30% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.064%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Additionally, other L2 Slices have a much lower number of active cycles than the average number of active     
          cycles. Maximum instance value is 93.21% above the average, while the minimum instance value is 93.65% below  
          the average.                                                                                                  

  mse_loss_backward_kernel(float *, float *, float *, int) (12, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.79
    SM Frequency                    Mhz       574.11
    Elapsed Cycles                cycle        2,335
    Memory Throughput                 %         2.65
    DRAM Throughput                   %         2.65
    Duration                         us         4.06
    L1/TEX Cache Throughput           %         5.96
    L2 Cache Throughput               %         2.09
    SM Active Cycles              cycle          322
    Compute (SM) Throughput           %         0.85
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        25.16
    Achieved Active Warps Per SM           warp         8.05
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 74.84%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (25.2%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle          516
    Total DRAM Elapsed Cycles        cycle      155,648
    Average L1 Active Cycles         cycle          322
    Total L1 Elapsed Cycles          cycle       90,872
    Average L2 Active Cycles         cycle       419.84
    Total L2 Elapsed Cycles          cycle      109,184
    Average SM Active Cycles         cycle          322
    Total SM Elapsed Cycles          cycle       90,872
    Average SMSP Active Cycles       cycle       321.99
    Total SMSP Elapsed Cycles        cycle      363,488
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 10.09%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 71.20% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.12%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 71.40% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.09%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 71.20% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.389%                                                                                          
          One or more L2 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 43.80% above the average, while the minimum instance value is 67.85% below the      
          average.                                                                                                      

  conv2d_backward_naive_kernel(float *, float *, float *, float *, float *, float *, int, int, int, int, int) (12, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.05
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle    2,172,512
    Memory Throughput                 %        20.17
    DRAM Throughput                   %         0.40
    Duration                         ms         3.71
    L1/TEX Cache Throughput           %        71.06
    L2 Cache Throughput               %        14.09
    SM Active Cycles              cycle   618,565.28
    Compute (SM) Throughput           %         6.99
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              42
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.60
    Achieved Active Warps Per SM           warp         7.87
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.4%                                                                                     
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.6%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       74,252
    Total DRAM Elapsed Cycles        cycle  150,085,632
    Average L1 Active Cycles         cycle   618,565.28
    Total L1 Elapsed Cycles          cycle   87,187,776
    Average L2 Active Cycles         cycle 2,646,879.22
    Total L2 Elapsed Cycles          cycle  101,606,688
    Average SM Active Cycles         cycle   618,565.28
    Total SM Elapsed Cycles          cycle   87,187,776
    Average SMSP Active Cycles       cycle   622,500.73
    Total SMSP Elapsed Cycles        cycle  348,751,104
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 20.27%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 71.44% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.36%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 71.30% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.27%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 71.44% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  upsample_backward_kernel(float *, float *, int, int, int, int, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.05
    SM Frequency                    Mhz       578.29
    Elapsed Cycles                cycle        4,815
    Memory Throughput                 %        43.59
    DRAM Throughput                   %        43.59
    Duration                         us         8.32
    L1/TEX Cache Throughput           %        24.25
    L2 Cache Throughput               %        18.80
    SM Active Cycles              cycle     3,378.72
    Compute (SM) Throughput           %        25.09
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        80.44
    Achieved Active Warps Per SM           warp        25.74
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 19.56%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (80.4%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       18,301
    Total DRAM Elapsed Cycles        cycle      335,872
    Average L1 Active Cycles         cycle     3,378.72
    Total L1 Elapsed Cycles          cycle      189,616
    Average L2 Active Cycles         cycle     3,768.81
    Total L2 Elapsed Cycles          cycle      226,336
    Average SM Active Cycles         cycle     3,378.72
    Total SM Elapsed Cycles          cycle      189,616
    Average SMSP Active Cycles       cycle     3,293.07
    Total SMSP Elapsed Cycles        cycle      758,464
    -------------------------- ----------- ------------

  relu_backward_kernel(float *, float *, float *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.93
    SM Frequency                    Mhz       575.86
    Elapsed Cycles                cycle        3,892
    Memory Throughput                 %        28.59
    DRAM Throughput                   %        28.59
    Duration                         us         6.75
    L1/TEX Cache Throughput           %        16.85
    L2 Cache Throughput               %        14.33
    SM Active Cycles              cycle     2,430.62
    Compute (SM) Throughput           %        10.43
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        80.46
    Achieved Active Warps Per SM           warp        25.75
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 19.54%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (80.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     9,515.50
    Total DRAM Elapsed Cycles        cycle      266,240
    Average L1 Active Cycles         cycle     2,430.62
    Total L1 Elapsed Cycles          cycle      157,064
    Average L2 Active Cycles         cycle     3,016.16
    Total L2 Elapsed Cycles          cycle      182,880
    Average SM Active Cycles         cycle     2,430.62
    Total SM Elapsed Cycles          cycle      157,064
    Average SMSP Active Cycles       cycle     2,427.11
    Total SMSP Elapsed Cycles        cycle      628,256
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 6.165%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 9.97% above the average, while the minimum instance value is 34.33% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.274%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 9.99% above the average, while the minimum instance value is 5.24% below the        
          average.                                                                                                      

  conv2d_backward_naive_kernel(float *, float *, float *, float *, float *, float *, int, int, int, int, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- -------------
    Metric Name             Metric Unit  Metric Value
    ----------------------- ----------- -------------
    DRAM Frequency                  Ghz          4.99
    SM Frequency                    Mhz        585.00
    Elapsed Cycles                cycle    11,457,525
    Memory Throughput                 %         47.36
    DRAM Throughput                   %          0.10
    Duration                         ms         19.59
    L1/TEX Cache Throughput           %         94.73
    L2 Cache Throughput               %         32.47
    SM Active Cycles              cycle 10,995,098.40
    Compute (SM) Throughput           %         20.78
    ----------------------- ----------- -------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              42
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        81.92
    Achieved Active Warps Per SM           warp        26.22
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 18.08%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (81.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- -------------
    Metric Name                Metric Unit  Metric Value
    -------------------------- ----------- -------------
    Average DRAM Active Cycles       cycle     97,756.50
    Total DRAM Elapsed Cycles        cycle   782,360,576
    Average L1 Active Cycles         cycle 10,995,098.40
    Total L1 Elapsed Cycles          cycle   458,760,512
    Average L2 Active Cycles         cycle 16,570,455.88
    Total L2 Elapsed Cycles          cycle   535,859,680
    Average SM Active Cycles         cycle 10,995,098.40
    Total SM Elapsed Cycles          cycle   458,760,512
    Average SMSP Active Cycles       cycle 11,004,800.14
    Total SMSP Elapsed Cycles        cycle 1,835,042,048
    -------------------------- ----------- -------------

  upsample_backward_kernel(float *, float *, int, int, int, int, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.87
    SM Frequency                    Mhz       576.44
    Elapsed Cycles                cycle        2,807
    Memory Throughput                 %         9.82
    DRAM Throughput                   %         9.82
    Duration                         us         4.86
    L1/TEX Cache Throughput           %         8.39
    L2 Cache Throughput               %         4.82
    SM Active Cycles              cycle     1,220.92
    Compute (SM) Throughput           %         5.52
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.87
    Achieved Active Warps Per SM           warp         7.96
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.13%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     2,325.50
    Total DRAM Elapsed Cycles        cycle      189,440
    Average L1 Active Cycles         cycle     1,220.92
    Total L1 Elapsed Cycles          cycle      111,384
    Average L2 Active Cycles         cycle       896.06
    Total L2 Elapsed Cycles          cycle      131,712
    Average SM Active Cycles         cycle     1,220.92
    Total SM Elapsed Cycles          cycle      111,384
    Average SMSP Active Cycles       cycle     1,207.23
    Total SMSP Elapsed Cycles        cycle      445,536
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.9%                                                                                            
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 22.58% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.19%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 23.50% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.9%                                                                                            
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 22.58% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.119%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 37.29% above the average, while the minimum instance value is 22.77% below the      
          average.                                                                                                      

  relu_backward_kernel(float *, float *, float *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.91
    SM Frequency                    Mhz       574.11
    Elapsed Cycles                cycle        2,574
    Memory Throughput                 %         5.53
    DRAM Throughput                   %         5.53
    Duration                         us         4.48
    L1/TEX Cache Throughput           %         4.85
    L2 Cache Throughput               %         3.29
    SM Active Cycles              cycle     1,055.58
    Compute (SM) Throughput           %         2.01
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.69
    Achieved Active Warps Per SM           warp         7.90
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.31%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        1,217
    Total DRAM Elapsed Cycles        cycle      176,128
    Average L1 Active Cycles         cycle     1,055.58
    Total L1 Elapsed Cycles          cycle      101,928
    Average L2 Active Cycles         cycle       941.56
    Total L2 Elapsed Cycles          cycle      120,544
    Average SM Active Cycles         cycle     1,055.58
    Total SM Elapsed Cycles          cycle      101,928
    Average SMSP Active Cycles       cycle     1,080.56
    Total SMSP Elapsed Cycles        cycle      407,712
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.296%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 22.44% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.18%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 24.01% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.296%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 22.44% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.989%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 27.96% above the average, while the minimum instance value is 18.22% below the      
          average.                                                                                                      

  conv2d_backward_naive_kernel(float *, float *, float *, float *, float *, float *, int, int, int, int, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle    1,838,018
    Memory Throughput                 %        33.79
    DRAM Throughput                   %         0.28
    Duration                         ms         3.14
    L1/TEX Cache Throughput           %        67.62
    L2 Cache Throughput               %        19.98
    SM Active Cycles              cycle 1,090,301.18
    Compute (SM) Throughput           %        14.85
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              42
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        23.97
    Achieved Active Warps Per SM           warp         7.67
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 76.03%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       43,854
    Total DRAM Elapsed Cycles        cycle  125,534,208
    Average L1 Active Cycles         cycle 1,090,301.18
    Total L1 Elapsed Cycles          cycle   73,557,600
    Average L2 Active Cycles         cycle 2,472,420.09
    Total L2 Elapsed Cycles          cycle   85,962,624
    Average SM Active Cycles         cycle 1,090,301.18
    Total SM Elapsed Cycles          cycle   73,557,600
    Average SMSP Active Cycles       cycle 1,089,443.87
    Total SMSP Elapsed Cycles        cycle  294,230,400
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 24.08%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 40.62% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 24.12%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 40.72% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 24.08%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 40.62% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  maxpool_backward_kernel(float *, float *, int *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.73
    SM Frequency                    Mhz       576.76
    Elapsed Cycles                cycle        2,623
    Memory Throughput                 %        17.32
    DRAM Throughput                   %        17.32
    Duration                         us         4.54
    L1/TEX Cache Throughput           %        10.99
    L2 Cache Throughput               %         5.12
    SM Active Cycles              cycle     1,052.50
    Compute (SM) Throughput           %         2.00
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.64
    Achieved Active Warps Per SM           warp         7.88
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.36%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.6%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        3,725
    Total DRAM Elapsed Cycles        cycle      172,032
    Average L1 Active Cycles         cycle     1,052.50
    Total L1 Elapsed Cycles          cycle      102,336
    Average L2 Active Cycles         cycle     1,309.38
    Total L2 Elapsed Cycles          cycle      122,976
    Average SM Active Cycles         cycle     1,052.50
    Total SM Elapsed Cycles          cycle      102,336
    Average SMSP Active Cycles       cycle     1,026.87
    Total SMSP Elapsed Cycles        cycle      409,344
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.184%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 22.32% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.471%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 23.60% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.184%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 22.32% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.362%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 18.67% above the average, while the minimum instance value is 12.40% below the      
          average.                                                                                                      

  relu_backward_kernel(float *, float *, float *, int) (128, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.88
    SM Frequency                    Mhz       572.18
    Elapsed Cycles                cycle        3,004
    Memory Throughput                 %        18.75
    DRAM Throughput                   %        18.75
    Duration                         us         5.25
    L1/TEX Cache Throughput           %        13.21
    L2 Cache Throughput               %         9.58
    SM Active Cycles              cycle     1,550.30
    Compute (SM) Throughput           %         6.93
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        74.78
    Achieved Active Warps Per SM           warp        23.93
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 25.22%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (74.8%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     4,799.50
    Total DRAM Elapsed Cycles        cycle      204,800
    Average L1 Active Cycles         cycle     1,550.30
    Total L1 Elapsed Cycles          cycle      118,176
    Average L2 Active Cycles         cycle     1,736.81
    Total L2 Elapsed Cycles          cycle      141,184
    Average SM Active Cycles         cycle     1,550.30
    Total SM Elapsed Cycles          cycle      118,176
    Average SMSP Active Cycles       cycle     1,512.45
    Total SMSP Elapsed Cycles        cycle      472,704
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.396%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 10.28% above the average, while the minimum instance value is 13.31% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.396%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 10.28% above the average, while the minimum instance value is 13.31% below the      
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.163%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 13.12% above the average, while the minimum instance value is 8.63% below the       
          average.                                                                                                      

  conv2d_backward_naive_kernel(float *, float *, float *, float *, float *, float *, int, int, int, int, int) (128, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- -------------
    Metric Name             Metric Unit  Metric Value
    ----------------------- ----------- -------------
    DRAM Frequency                  Ghz          5.00
    SM Frequency                    Mhz        585.00
    Elapsed Cycles                cycle    12,602,790
    Memory Throughput                 %         42.49
    DRAM Throughput                   %          0.10
    Duration                         ms         21.54
    L1/TEX Cache Throughput           %         84.98
    L2 Cache Throughput               %         25.73
    SM Active Cycles              cycle 10,675,413.32
    Compute (SM) Throughput           %         18.82
    ----------------------- ----------- -------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              42
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        57.65
    Achieved Active Warps Per SM           warp        18.45
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 42.35%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (57.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- -------------
    Metric Name                Metric Unit  Metric Value
    -------------------------- ----------- -------------
    Average DRAM Active Cycles       cycle    110,721.50
    Total DRAM Elapsed Cycles        cycle   861,286,400
    Average L1 Active Cycles         cycle 10,675,413.32
    Total L1 Elapsed Cycles          cycle   504,355,800
    Average L2 Active Cycles         cycle 17,196,553.72
    Total L2 Elapsed Cycles          cycle   589,422,784
    Average SM Active Cycles         cycle 10,675,413.32
    Total SM Elapsed Cycles          cycle   504,355,800
    Average SMSP Active Cycles       cycle 10,673,504.84
    Total SMSP Elapsed Cycles        cycle 2,017,423,200
    -------------------------- ----------- -------------

    OPT   Est. Speedup: 12.93%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 15.27% above the average, while the minimum instance value is 11.36% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.94%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 15.28% above the average, while the minimum instance value is 11.19% below the      
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.93%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 15.27% above the average, while the minimum instance value is 11.36% below the      
          average.                                                                                                      

  maxpool_backward_kernel(float *, float *, int *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.67
    SM Frequency                    Mhz       578.21
    Elapsed Cycles                cycle        5,297
    Memory Throughput                 %        68.43
    DRAM Throughput                   %        68.43
    Duration                         us         9.15
    L1/TEX Cache Throughput           %        34.06
    L2 Cache Throughput               %        17.89
    SM Active Cycles              cycle     3,530.50
    Compute (SM) Throughput           %         8.28
    ----------------------- ----------- ------------

    OPT   Memory is more heavily utilized than Compute: Look at the Memory Workload Analysis section to identify the    
          DRAM bottleneck. Check memory replay (coalescing) metrics to make sure you're efficiently utilizing the       
          bytes transferred. Also consider whether it is possible to do more work per memory access (kernel fusion) or  
          whether there are values you can (re)compute.                                                                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 50%                                                                                             
          A wave of thread blocks is defined as the maximum number of blocks that can be executed in parallel on the    
          target GPU. The number of blocks in a wave depends on the number of multiprocessors and the theoretical       
          occupancy of the kernel. This kernel launch results in 1 full waves and a partial wave of 96 thread blocks.   
          Under the assumption of a uniform execution duration of all thread blocks, the partial wave may account for   
          up to 50.0% of the total kernel runtime with a lower occupancy of 22.8%. Try launching a grid with no         
          partial wave. The overall impact of this tail effect also lessens with the number of full waves executed for  
          a grid. See the Hardware Model                                                                                
          (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model) description for more      
          details on launch configurations.                                                                             

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        77.23
    Achieved Active Warps Per SM           warp        24.71
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 22.77%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (77.2%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    29,256.50
    Total DRAM Elapsed Cycles        cycle      342,016
    Average L1 Active Cycles         cycle     3,530.50
    Total L1 Elapsed Cycles          cycle      197,864
    Average L2 Active Cycles         cycle     5,361.19
    Total L2 Elapsed Cycles          cycle      248,576
    Average SM Active Cycles         cycle     3,530.50
    Total SM Elapsed Cycles          cycle      197,864
    Average SMSP Active Cycles       cycle     3,422.45
    Total SMSP Elapsed Cycles        cycle      791,456
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.259%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 7.60% above the average, while the minimum instance value is 10.71% below the average.      

  relu_backward_kernel(float *, float *, float *, int) (1024, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.57
    SM Frequency                    Mhz       581.94
    Elapsed Cycles                cycle        9,778
    Memory Throughput                 %        55.61
    DRAM Throughput                   %        55.61
    Duration                         us        16.80
    L1/TEX Cache Throughput           %        23.92
    L2 Cache Throughput               %        21.83
    SM Active Cycles              cycle     7,412.48
    Compute (SM) Throughput           %        18.40
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        89.62
    Achieved Active Warps Per SM           warp        28.68
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 10.38%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (89.6%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    42,710.50
    Total DRAM Elapsed Cycles        cycle      614,400
    Average L1 Active Cycles         cycle     7,412.48
    Total L1 Elapsed Cycles          cycle      356,104
    Average L2 Active Cycles         cycle    10,375.66
    Total L2 Elapsed Cycles          cycle      457,920
    Average SM Active Cycles         cycle     7,412.48
    Total SM Elapsed Cycles          cycle      356,104
    Average SMSP Active Cycles       cycle     7,359.39
    Total SMSP Elapsed Cycles        cycle    1,424,416
    -------------------------- ----------- ------------

  conv2d_backward_naive_kernel(float *, float *, float *, float *, float *, float *, int, int, int, int, int) (1024, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.96
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle    2,498,676
    Memory Throughput                 %        17.47
    DRAM Throughput                   %         0.11
    Duration                         ms         4.27
    L1/TEX Cache Throughput           %        34.94
    L2 Cache Throughput               %        14.89
    SM Active Cycles              cycle 2,450,828.92
    Compute (SM) Throughput           %         8.53
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              42
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        94.82
    Achieved Active Warps Per SM           warp        30.34
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    22,991.50
    Total DRAM Elapsed Cycles        cycle  169,528,320
    Average L1 Active Cycles         cycle 2,450,828.92
    Total L1 Elapsed Cycles          cycle   99,519,104
    Average L2 Active Cycles         cycle 2,660,640.19
    Total L2 Elapsed Cycles          cycle  116,861,088
    Average SM Active Cycles         cycle 2,450,828.92
    Total SM Elapsed Cycles          cycle   99,519,104
    Average SMSP Active Cycles       cycle 2,446,305.41
    Total SMSP Elapsed Cycles        cycle  398,076,416
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 15.96%                                                                                          
          One or more L2 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 21.91% above the average, while the minimum instance value is 28.40% below the      
          average.                                                                                                      

  conv2d_naive_kernel(float *, float *, float *, float *, int, int, int, int, int) (1024, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.01
    SM Frequency                    Mhz       584.93
    Elapsed Cycles                cycle       96,963
    Memory Throughput                 %        47.47
    DRAM Throughput                   %         0.57
    Duration                         us       165.76
    L1/TEX Cache Throughput           %        94.94
    L2 Cache Throughput               %         1.69
    SM Active Cycles              cycle    94,259.12
    Compute (SM) Throughput           %        26.74
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              41
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        93.31
    Achieved Active Warps Per SM           warp        29.86
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        4,740
    Total DRAM Elapsed Cycles        cycle    6,637,568
    Average L1 Active Cycles         cycle    94,259.12
    Total L1 Elapsed Cycles          cycle    3,884,760
    Average L2 Active Cycles         cycle       20,400
    Total L2 Elapsed Cycles          cycle    4,534,240
    Average SM Active Cycles         cycle    94,259.12
    Total SM Elapsed Cycles          cycle    3,884,760
    Average SMSP Active Cycles       cycle    94,166.83
    Total SMSP Elapsed Cycles        cycle   15,539,040
    -------------------------- ----------- ------------

  relu_forward_kernel(float *, float *, int) (1024, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.62
    SM Frequency                    Mhz       579.66
    Elapsed Cycles                cycle        6,627
    Memory Throughput                 %        42.01
    DRAM Throughput                   %        42.01
    Duration                         us        11.42
    L1/TEX Cache Throughput           %        30.08
    L2 Cache Throughput               %        21.53
    SM Active Cycles              cycle     4,857.10
    Compute (SM) Throughput           %        19.80
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        79.89
    Achieved Active Warps Per SM           warp        25.57
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 20.11%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (79.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    22,154.50
    Total DRAM Elapsed Cycles        cycle      421,888
    Average L1 Active Cycles         cycle     4,857.10
    Total L1 Elapsed Cycles          cycle      248,264
    Average L2 Active Cycles         cycle     6,420.91
    Total L2 Elapsed Cycles          cycle      310,784
    Average SM Active Cycles         cycle     4,857.10
    Total SM Elapsed Cycles          cycle      248,264
    Average SMSP Active Cycles       cycle     4,769.33
    Total SMSP Elapsed Cycles        cycle      993,056
    -------------------------- ----------- ------------

  maxpool_forward_kernel(float *, float *, int *, int, int, int, int, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.92
    SM Frequency                    Mhz       579.12
    Elapsed Cycles                cycle        5,176
    Memory Throughput                 %        43.58
    DRAM Throughput                   %        43.58
    Duration                         us         8.93
    L1/TEX Cache Throughput           %        22.74
    L2 Cache Throughput               %        20.91
    SM Active Cycles              cycle     3,603.07
    Compute (SM) Throughput           %        29.75
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              19
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        80.61
    Achieved Active Warps Per SM           warp        25.80
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 19.39%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (80.6%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       19,135
    Total DRAM Elapsed Cycles        cycle      351,232
    Average L1 Active Cycles         cycle     3,603.07
    Total L1 Elapsed Cycles          cycle      204,824
    Average L2 Active Cycles         cycle     4,005.91
    Total L2 Elapsed Cycles          cycle      243,168
    Average SM Active Cycles         cycle     3,603.07
    Total SM Elapsed Cycles          cycle      204,824
    Average SMSP Active Cycles       cycle     3,561.17
    Total SMSP Elapsed Cycles        cycle      819,296
    -------------------------- ----------- ------------

  conv2d_naive_kernel(float *, float *, float *, float *, int, int, int, int, int) (128, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle    4,129,570
    Memory Throughput                 %        43.51
    DRAM Throughput                   %         0.13
    Duration                         ms         7.06
    L1/TEX Cache Throughput           %        87.03
    L2 Cache Throughput               %         5.76
    SM Active Cycles              cycle 3,547,876.05
    Compute (SM) Throughput           %         5.52
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              41
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        57.20
    Achieved Active Warps Per SM           warp        18.30
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 42.8%                                                                                     
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (57.2%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       45,900
    Total DRAM Elapsed Cycles        cycle  282,313,728
    Average L1 Active Cycles         cycle 3,547,876.05
    Total L1 Elapsed Cycles          cycle  165,296,824
    Average L2 Active Cycles         cycle 4,340,453.78
    Total L2 Elapsed Cycles          cycle  193,136,800
    Average SM Active Cycles         cycle 3,547,876.05
    Total SM Elapsed Cycles          cycle  165,296,824
    Average SMSP Active Cycles       cycle 3,549,440.99
    Total SMSP Elapsed Cycles        cycle  661,187,296
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 12.11%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 14.11% above the average, while the minimum instance value is 11.45% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.03%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 14.00% above the average, while the minimum instance value is 10.60% below the      
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.11%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 14.11% above the average, while the minimum instance value is 11.45% below the      
          average.                                                                                                      

  relu_forward_kernel(float *, float *, int) (128, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.91
    SM Frequency                    Mhz       575.09
    Elapsed Cycles                cycle        2,523
    Memory Throughput                 %        10.69
    DRAM Throughput                   %        10.69
    Duration                         us         4.38
    L1/TEX Cache Throughput           %        13.39
    L2 Cache Throughput               %         8.13
    SM Active Cycles              cycle     1,147.45
    Compute (SM) Throughput           %         6.21
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        76.46
    Achieved Active Warps Per SM           warp        24.47
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 23.54%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (76.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        2,299
    Total DRAM Elapsed Cycles        cycle      172,032
    Average L1 Active Cycles         cycle     1,147.45
    Total L1 Elapsed Cycles          cycle       98,952
    Average L2 Active Cycles         cycle     1,083.19
    Total L2 Elapsed Cycles          cycle      118,528
    Average SM Active Cycles         cycle     1,147.45
    Total SM Elapsed Cycles          cycle       98,952
    Average SMSP Active Cycles       cycle     1,136.04
    Total SMSP Elapsed Cycles        cycle      395,808
    -------------------------- ----------- ------------

  maxpool_forward_kernel(float *, float *, int *, int, int, int, int, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.67
    SM Frequency                    Mhz       577.72
    Elapsed Cycles                cycle        2,979
    Memory Throughput                 %        10.10
    DRAM Throughput                   %        10.10
    Duration                         us         5.15
    L1/TEX Cache Throughput           %         7.90
    L2 Cache Throughput               %         5.33
    SM Active Cycles              cycle        1,296
    Compute (SM) Throughput           %         6.83
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              19
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        25.01
    Achieved Active Warps Per SM           warp         8.00
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 74.99%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (25.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     2,429.50
    Total DRAM Elapsed Cycles        cycle      192,512
    Average L1 Active Cycles         cycle        1,296
    Total L1 Elapsed Cycles          cycle      115,224
    Average L2 Active Cycles         cycle     1,006.88
    Total L2 Elapsed Cycles          cycle      139,872
    Average SM Active Cycles         cycle        1,296
    Total SM Elapsed Cycles          cycle      115,224
    Average SMSP Active Cycles       cycle     1,258.75
    Total SMSP Elapsed Cycles        cycle      460,896
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 10.61%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 23.58% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.54%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 24.13% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.61%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 23.58% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.235%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 22.73% above the average, while the minimum instance value is 15.58% below the      
          average.                                                                                                      

  conv2d_naive_kernel(float *, float *, float *, float *, int, int, int, int, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.97
    Elapsed Cycles                cycle      612,791
    Memory Throughput                 %        33.60
    DRAM Throughput                   %         0.37
    Duration                         ms         1.05
    L1/TEX Cache Throughput           %        67.20
    L2 Cache Throughput               %         3.05
    SM Active Cycles              cycle   349,089.70
    Compute (SM) Throughput           %         4.52
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              41
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.29
    Achieved Active Warps Per SM           warp         7.77
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.71%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.3%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       19,494
    Total DRAM Elapsed Cycles        cycle   41,878,528
    Average L1 Active Cycles         cycle   349,089.70
    Total L1 Elapsed Cycles          cycle   24,520,480
    Average L2 Active Cycles         cycle   455,872.22
    Total L2 Elapsed Cycles          cycle   28,659,808
    Average SM Active Cycles         cycle   349,089.70
    Total SM Elapsed Cycles          cycle   24,520,480
    Average SMSP Active Cycles       cycle   349,017.92
    Total SMSP Elapsed Cycles        cycle   98,081,920
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 24.44%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 42.92% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 24.46%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 42.96% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 24.44%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 42.92% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  relu_forward_kernel(float *, float *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.93
    SM Frequency                    Mhz       572.45
    Elapsed Cycles                cycle        2,200
    Memory Throughput                 %         3.28
    DRAM Throughput                   %         3.28
    Duration                         us         3.84
    L1/TEX Cache Throughput           %         4.94
    L2 Cache Throughput               %         2.83
    SM Active Cycles              cycle       777.90
    Compute (SM) Throughput           %         1.77
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.67
    Achieved Active Warps Per SM           warp         7.90
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.33%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle          621
    Total DRAM Elapsed Cycles        cycle      151,552
    Average L1 Active Cycles         cycle       777.90
    Total L1 Elapsed Cycles          cycle       86,816
    Average L2 Active Cycles         cycle          544
    Total L2 Elapsed Cycles          cycle      102,944
    Average SM Active Cycles         cycle       777.90
    Total SM Elapsed Cycles          cycle       86,816
    Average SMSP Active Cycles       cycle       765.74
    Total SMSP Elapsed Cycles        cycle      347,264
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.772%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 24.48% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.479%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 24.03% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.772%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 24.48% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.827%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 34.46% above the average, while the minimum instance value is 22.98% below the      
          average.                                                                                                      

  upsample_forward_kernel(float *, float *, int, int, int, int, int) (128, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.92
    SM Frequency                    Mhz       574.68
    Elapsed Cycles                cycle        2,870
    Memory Throughput                 %         5.49
    DRAM Throughput                   %         2.92
    Duration                         us         4.99
    L1/TEX Cache Throughput           %         9.76
    L2 Cache Throughput               %         5.49
    SM Active Cycles              cycle     1,573.40
    Compute (SM) Throughput           %        17.95
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        72.52
    Achieved Active Warps Per SM           warp        23.21
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 27.48%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (72.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       717.50
    Total DRAM Elapsed Cycles        cycle      196,608
    Average L1 Active Cycles         cycle     1,573.40
    Total L1 Elapsed Cycles          cycle      113,096
    Average L2 Active Cycles         cycle     1,029.22
    Total L2 Elapsed Cycles          cycle      134,784
    Average SM Active Cycles         cycle     1,573.40
    Total SM Elapsed Cycles          cycle      113,096
    Average SMSP Active Cycles       cycle     1,536.92
    Total SMSP Elapsed Cycles        cycle      452,384
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.208%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 21.31% above the average, while the minimum instance value is 14.89% below the      
          average.                                                                                                      

  conv2d_naive_kernel(float *, float *, float *, float *, int, int, int, int, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle    3,720,937
    Memory Throughput                 %        48.54
    DRAM Throughput                   %         0.13
    Duration                         ms         6.36
    L1/TEX Cache Throughput           %        97.08
    L2 Cache Throughput               %        15.81
    SM Active Cycles              cycle 3,614,474.33
    Compute (SM) Throughput           %         6.13
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              41
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        80.53
    Achieved Active Warps Per SM           warp        25.77
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 19.47%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (80.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    42,825.50
    Total DRAM Elapsed Cycles        cycle  254,365,696
    Average L1 Active Cycles         cycle 3,614,474.33
    Total L1 Elapsed Cycles          cycle  148,882,816
    Average L2 Active Cycles         cycle 5,320,777.62
    Total L2 Elapsed Cycles          cycle  174,025,344
    Average SM Active Cycles         cycle 3,614,474.33
    Total SM Elapsed Cycles          cycle  148,882,816
    Average SMSP Active Cycles       cycle 3,607,893.76
    Total SMSP Elapsed Cycles        cycle  595,531,264
    -------------------------- ----------- ------------

  relu_forward_kernel(float *, float *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.74
    SM Frequency                    Mhz       572.38
    Elapsed Cycles                cycle        3,154
    Memory Throughput                 %        17.62
    DRAM Throughput                   %        17.62
    Duration                         us         5.50
    L1/TEX Cache Throughput           %        17.69
    L2 Cache Throughput               %        11.97
    SM Active Cycles              cycle        1,737
    Compute (SM) Throughput           %        10.00
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 50%                                                                                             
          A wave of thread blocks is defined as the maximum number of blocks that can be executed in parallel on the    
          target GPU. The number of blocks in a wave depends on the number of multiprocessors and the theoretical       
          occupancy of the kernel. This kernel launch results in 1 full waves and a partial wave of 96 thread blocks.   
          Under the assumption of a uniform execution duration of all thread blocks, the partial wave may account for   
          up to 50.0% of the total kernel runtime with a lower occupancy of 21.3%. Try launching a grid with no         
          partial wave. The overall impact of this tail effect also lessens with the number of full waves executed for  
          a grid. See the Hardware Model                                                                                
          (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model) description for more      
          details on launch configurations.                                                                             

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        78.71
    Achieved Active Warps Per SM           warp        25.19
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 21.29%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (78.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        4,600
    Total DRAM Elapsed Cycles        cycle      208,896
    Average L1 Active Cycles         cycle        1,737
    Total L1 Elapsed Cycles          cycle      122,896
    Average L2 Active Cycles         cycle     1,934.34
    Total L2 Elapsed Cycles          cycle      147,968
    Average SM Active Cycles         cycle        1,737
    Total SM Elapsed Cycles          cycle      122,896
    Average SMSP Active Cycles       cycle     1,707.82
    Total SMSP Elapsed Cycles        cycle      491,584
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.837%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 13.95% above the average, while the minimum instance value is 6.53% below the       
          average.                                                                                                      

  upsample_forward_kernel(float *, float *, int, int, int, int, int) (1024, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.90
    SM Frequency                    Mhz       580.29
    Elapsed Cycles                cycle        8,548
    Memory Throughput                 %        15.90
    DRAM Throughput                   %        11.87
    Duration                         us        14.72
    L1/TEX Cache Throughput           %        22.40
    L2 Cache Throughput               %        15.90
    SM Active Cycles              cycle     7,058.95
    Compute (SM) Throughput           %        45.19
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        81.20
    Achieved Active Warps Per SM           warp        25.98
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 18.8%                                                                                     
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (81.2%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        8,572
    Total DRAM Elapsed Cycles        cycle      577,536
    Average L1 Active Cycles         cycle     7,058.95
    Total L1 Elapsed Cycles          cycle      335,280
    Average L2 Active Cycles         cycle     7,277.03
    Total L2 Elapsed Cycles          cycle      400,640
    Average SM Active Cycles         cycle     7,058.95
    Total SM Elapsed Cycles          cycle      335,280
    Average SMSP Active Cycles       cycle     6,997.62
    Total SMSP Elapsed Cycles        cycle    1,341,120
    -------------------------- ----------- ------------

  conv2d_naive_kernel(float *, float *, float *, float *, int, int, int, int, int) (12, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.92
    Elapsed Cycles                cycle      295,891
    Memory Throughput                 %        25.92
    DRAM Throughput                   %         1.33
    Duration                         us       505.86
    L1/TEX Cache Throughput           %        88.40
    L2 Cache Throughput               %         0.50
    SM Active Cycles              cycle    86,691.30
    Compute (SM) Throughput           %         7.43
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              41
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.94
    Achieved Active Warps Per SM           warp         7.98
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.06%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    33,698.50
    Total DRAM Elapsed Cycles        cycle   20,201,472
    Average L1 Active Cycles         cycle    86,691.30
    Total L1 Elapsed Cycles          cycle   11,827,688
    Average L2 Active Cycles         cycle    95,942.84
    Total L2 Elapsed Cycles          cycle   13,838,336
    Average SM Active Cycles         cycle    86,691.30
    Total SM Elapsed Cycles          cycle   11,827,688
    Average SMSP Active Cycles       cycle    86,512.05
    Total SMSP Elapsed Cycles        cycle   47,310,752
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 20.69%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 70.58% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.66%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 70.63% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.69%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 70.58% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  mse_loss_kernel(const float *, const float *, float *, int) (12, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.95
    SM Frequency                    Mhz       582.95
    Elapsed Cycles                cycle        8,283
    Memory Throughput                 %         1.66
    DRAM Throughput                   %         0.69
    Duration                         us        14.21
    L1/TEX Cache Throughput           %        11.02
    L2 Cache Throughput               %         1.66
    SM Active Cycles              cycle       761.92
    Compute (SM) Throughput           %         0.93
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        13.88
    Achieved Active Warps Per SM           warp         4.44
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 86.12%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (13.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle          482
    Total DRAM Elapsed Cycles        cycle      562,176
    Average L1 Active Cycles         cycle       761.92
    Total L1 Elapsed Cycles          cycle      330,104
    Average L2 Active Cycles         cycle       651.22
    Total L2 Elapsed Cycles          cycle      387,360
    Average SM Active Cycles         cycle       761.92
    Total SM Elapsed Cycles          cycle      330,104
    Average SMSP Active Cycles       cycle       506.36
    Total SMSP Elapsed Cycles        cycle    1,320,416
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 7.231%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 78.32% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.248%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 85.53% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 7.231%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 78.32% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.021%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Additionally, other L2 Slices have a much lower number of active cycles than the average number of active     
          cycles. Maximum instance value is 93.33% above the average, while the minimum instance value is 93.55% below  
          the average.                                                                                                  

  mse_loss_backward_kernel(float *, float *, float *, int) (12, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.86
    SM Frequency                    Mhz       575.20
    Elapsed Cycles                cycle        2,302
    Memory Throughput                 %         2.68
    DRAM Throughput                   %         2.68
    Duration                         us            4
    L1/TEX Cache Throughput           %         5.99
    L2 Cache Throughput               %         2.12
    SM Active Cycles              cycle       320.30
    Compute (SM) Throughput           %         0.85
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        25.17
    Achieved Active Warps Per SM           warp         8.06
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 74.83%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (25.2%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle          522
    Total DRAM Elapsed Cycles        cycle      155,648
    Average L1 Active Cycles         cycle       320.30
    Total L1 Elapsed Cycles          cycle       90,472
    Average L2 Active Cycles         cycle       420.81
    Total L2 Elapsed Cycles          cycle      107,680
    Average SM Active Cycles         cycle       320.30
    Total SM Elapsed Cycles          cycle       90,472
    Average SMSP Active Cycles       cycle       313.07
    Total SMSP Elapsed Cycles        cycle      361,888
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 10.1%                                                                                           
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 71.32% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.934%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 71.77% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.1%                                                                                           
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 71.32% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.041%                                                                                          
          One or more L2 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 40.31% above the average, while the minimum instance value is 68.16% below the      
          average.                                                                                                      

  conv2d_backward_naive_kernel(float *, float *, float *, float *, float *, float *, int, int, int, int, int) (12, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.01
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle    2,193,320
    Memory Throughput                 %        20.08
    DRAM Throughput                   %         0.40
    Duration                         ms         3.75
    L1/TEX Cache Throughput           %        71.75
    L2 Cache Throughput               %        14.02
    SM Active Cycles              cycle   612,773.22
    Compute (SM) Throughput           %         6.96
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              42
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        25.00
    Achieved Active Warps Per SM           warp         8.00
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75%                                                                                       
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (25.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       74,244
    Total DRAM Elapsed Cycles        cycle  150,290,432
    Average L1 Active Cycles         cycle   612,773.22
    Total L1 Elapsed Cycles          cycle   87,570,720
    Average L2 Active Cycles         cycle 2,653,483.34
    Total L2 Elapsed Cycles          cycle  102,579,904
    Average SM Active Cycles         cycle   612,773.22
    Total SM Elapsed Cycles          cycle   87,570,720
    Average SMSP Active Cycles       cycle   610,881.65
    Total SMSP Elapsed Cycles        cycle  350,282,880
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 20.06%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 71.68% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 19.99%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 71.66% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.06%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 71.68% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  upsample_backward_kernel(float *, float *, int, int, int, int, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.94
    SM Frequency                    Mhz       578.21
    Elapsed Cycles                cycle        4,796
    Memory Throughput                 %        44.74
    DRAM Throughput                   %        44.74
    Duration                         us         8.29
    L1/TEX Cache Throughput           %        24.27
    L2 Cache Throughput               %        19.00
    SM Active Cycles              cycle     3,375.22
    Compute (SM) Throughput           %        24.92
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        81.08
    Achieved Active Warps Per SM           warp        25.94
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 18.92%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (81.1%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       18,325
    Total DRAM Elapsed Cycles        cycle      327,680
    Average L1 Active Cycles         cycle     3,375.22
    Total L1 Elapsed Cycles          cycle      190,912
    Average L2 Active Cycles         cycle     3,671.28
    Total L2 Elapsed Cycles          cycle      225,472
    Average SM Active Cycles         cycle     3,375.22
    Total SM Elapsed Cycles          cycle      190,912
    Average SMSP Active Cycles       cycle     3,314.64
    Total SMSP Elapsed Cycles        cycle      763,648
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.888%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 11.30% above the average, while the minimum instance value is 4.83% below the       
          average.                                                                                                      

  relu_backward_kernel(float *, float *, float *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.76
    SM Frequency                    Mhz       578.30
    Elapsed Cycles                cycle        4,001
    Memory Throughput                 %        29.24
    DRAM Throughput                   %        29.24
    Duration                         us         6.91
    L1/TEX Cache Throughput           %        16.64
    L2 Cache Throughput               %        13.80
    SM Active Cycles              cycle     2,461.50
    Compute (SM) Throughput           %        10.49
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        80.72
    Achieved Active Warps Per SM           warp        25.83
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 19.28%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (80.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     9,618.50
    Total DRAM Elapsed Cycles        cycle      263,168
    Average L1 Active Cycles         cycle     2,461.50
    Total L1 Elapsed Cycles          cycle      156,160
    Average L2 Active Cycles         cycle     3,015.41
    Total L2 Elapsed Cycles          cycle      187,936
    Average SM Active Cycles         cycle     2,461.50
    Total SM Elapsed Cycles          cycle      156,160
    Average SMSP Active Cycles       cycle     2,430.71
    Total SMSP Elapsed Cycles        cycle      624,640
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.131%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 8.24% above the average, while the minimum instance value is 31.09% below the average.      

  conv2d_backward_naive_kernel(float *, float *, float *, float *, float *, float *, int, int, int, int, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- -------------
    Metric Name             Metric Unit  Metric Value
    ----------------------- ----------- -------------
    DRAM Frequency                  Ghz          5.00
    SM Frequency                    Mhz        585.00
    Elapsed Cycles                cycle    11,454,290
    Memory Throughput                 %         47.39
    DRAM Throughput                   %          0.10
    Duration                         ms         19.58
    L1/TEX Cache Throughput           %         94.77
    L2 Cache Throughput               %         32.51
    SM Active Cycles              cycle 10,995,730.93
    Compute (SM) Throughput           %         20.79
    ----------------------- ----------- -------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              42
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        81.95
    Achieved Active Warps Per SM           warp        26.22
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 18.05%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (82.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- -------------
    Metric Name                Metric Unit  Metric Value
    -------------------------- ----------- -------------
    Average DRAM Active Cycles       cycle        99,938
    Total DRAM Elapsed Cycles        cycle   783,874,048
    Average L1 Active Cycles         cycle 10,995,730.93
    Total L1 Elapsed Cycles          cycle   458,555,864
    Average L2 Active Cycles         cycle 16,573,579.03
    Total L2 Elapsed Cycles          cycle   535,708,320
    Average SM Active Cycles         cycle 10,995,730.93
    Total SM Elapsed Cycles          cycle   458,555,864
    Average SMSP Active Cycles       cycle 10,989,689.48
    Total SMSP Elapsed Cycles        cycle 1,834,223,456
    -------------------------- ----------- -------------

  upsample_backward_kernel(float *, float *, int, int, int, int, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.75
    SM Frequency                    Mhz       574.11
    Elapsed Cycles                cycle        2,851
    Memory Throughput                 %         9.82
    DRAM Throughput                   %         9.82
    Duration                         us         4.96
    L1/TEX Cache Throughput           %         8.40
    L2 Cache Throughput               %         4.75
    SM Active Cycles              cycle     1,218.35
    Compute (SM) Throughput           %         5.57
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.75
    Achieved Active Warps Per SM           warp         7.92
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.25%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.8%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     2,313.50
    Total DRAM Elapsed Cycles        cycle      188,416
    Average L1 Active Cycles         cycle     1,218.35
    Total L1 Elapsed Cycles          cycle      110,392
    Average L2 Active Cycles         cycle       858.88
    Total L2 Elapsed Cycles          cycle      133,728
    Average SM Active Cycles         cycle     1,218.35
    Total SM Elapsed Cycles          cycle      110,392
    Average SMSP Active Cycles       cycle     1,191.31
    Total SMSP Elapsed Cycles        cycle      441,568
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 10.34%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 23.42% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.45%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 24.22% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.34%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 23.42% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.095%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Additionally, other L2 Slices have a much lower number of active cycles than the average number of active     
          cycles. Maximum instance value is 24.79% above the average, while the minimum instance value is 26.76% below  
          the average.