This repository contains my Computer Organization and Architecture lab work using Verilog in ModelSim.
| Lab | Topic | Status |
|---|---|---|
| Lab 01 | Basic Logic Gates, XOR and 1's Complement | Completed |
| Lab 02 | Combinational Circuits using Gate-Level and Dataflow Modeling | Completed |
| Lab 03 | Combinational Circuits using Behavioral Modeling | Completed |
| Lab 04 | To be added | Pending |
| Lab 05 | To be added | Pending |
| Lab 06 | To be added | Pending |
| Lab 07 | To be added | Pending |
| Lab 08 | To be added | Pending |
| Lab 09 | To be added | Pending |
| Lab 10 | To be added | Pending |
| Lab 11 | To be added | Pending |
| Lab 12 | To be added | Pending |
| Lab 13 | To be added | Pending |
- ModelSim
Each lab has a separate folder containing its Verilog files and a README describing the work performed.