From ff6fa9105e13e713ad4927464e3a4a2448666df4 Mon Sep 17 00:00:00 2001 From: Kinza Qamar Date: Fri, 17 Jul 2026 16:19:20 +0100 Subject: [PATCH 1/2] [i2c, sw] Remove _time from bus_free_cycles A reviewer on #633 commented about inconsistency in the naming of tBUF timing parameter accross different places. That made me look at the name of the bus_free_time_cycles field in the i2c_timing_params_t struct and I realized that it is also inconsistent. Signed-off-by: Kinza Qamar --- sw/device/lib/hal/i2c.c | 8 ++++---- sw/device/lib/hal/i2c.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/sw/device/lib/hal/i2c.c b/sw/device/lib/hal/i2c.c index 0d880343b..350c6a0bd 100644 --- a/sw/device/lib/hal/i2c.c +++ b/sw/device/lib/hal/i2c.c @@ -67,7 +67,7 @@ static i2c_timing_params_t compute_minimum_timing_parameters(i2c_speed_mode_t sp .setup_data_cycles = rnd_up_div(250u, SYSCLK_NS), .hold_data_cycles = 1u, .setup_stop_cycles = rnd_up_div(4000u, SYSCLK_NS), - .bus_free_time_cycles = rnd_up_div(4700u, SYSCLK_NS) + .bus_free_cycles = rnd_up_div(4700u, SYSCLK_NS) }; case i2c_speed_mode_fast: return (i2c_timing_params_t){ @@ -81,7 +81,7 @@ static i2c_timing_params_t compute_minimum_timing_parameters(i2c_speed_mode_t sp .setup_data_cycles = rnd_up_div(100u, SYSCLK_NS), .hold_data_cycles = 1u, .setup_stop_cycles = rnd_up_div(600u, SYSCLK_NS), - .bus_free_time_cycles = rnd_up_div(1300u, SYSCLK_NS) + .bus_free_cycles = rnd_up_div(1300u, SYSCLK_NS) }; case i2c_speed_mode_fast_plus: return (i2c_timing_params_t){ @@ -95,7 +95,7 @@ static i2c_timing_params_t compute_minimum_timing_parameters(i2c_speed_mode_t sp .setup_data_cycles = rnd_up_div(50, SYSCLK_NS), .hold_data_cycles = 1u, .setup_stop_cycles = rnd_up_div(260u, SYSCLK_NS), - .bus_free_time_cycles = rnd_up_div(500u, SYSCLK_NS) + .bus_free_cycles = rnd_up_div(500u, SYSCLK_NS) }; default: return (i2c_timing_params_t){ 0 }; @@ -120,7 +120,7 @@ void i2c_init(i2c_t i2c, i2c_speed_mode_t speed_mode) i2c_timing3 t3_reg = { .tsu_dat = timing_params.setup_data_cycles, .thd_dat = timing_params.hold_data_cycles }; i2c_timing4 t4_reg = { .tsu_sto = timing_params.setup_stop_cycles, - .t_buf = timing_params.bus_free_time_cycles }; + .t_buf = timing_params.bus_free_cycles }; VOLATILE_WRITE(i2c->timing0, t0_reg); VOLATILE_WRITE(i2c->timing1, t1_reg); diff --git a/sw/device/lib/hal/i2c.h b/sw/device/lib/hal/i2c.h index d64f4b53f..b18233055 100644 --- a/sw/device/lib/hal/i2c.h +++ b/sw/device/lib/hal/i2c.h @@ -107,7 +107,7 @@ typedef struct { uint16_t setup_data_cycles; uint16_t hold_data_cycles; uint16_t setup_stop_cycles; - uint16_t bus_free_time_cycles; + uint16_t bus_free_cycles; } i2c_timing_params_t; void i2c_init(i2c_t i2c, i2c_speed_mode_t speed_mode); From 7545d98e24b349212d265ee3e1bacd343f9c44cc Mon Sep 17 00:00:00 2001 From: Kinza Qamar Date: Fri, 17 Jul 2026 16:27:35 +0100 Subject: [PATCH 2/2] [i2c, sw] Remove extra FMT FIFO reset step Historically, it was there to clean up FMT FIFO since that part was missing during errors. That still kept in place at the start of read / write functions as a precautionary step. I think this is no longer needed since clean up is now done during errors in i2c_host_wait_transfer_finish(). Signed-off-by: Kinza Qamar --- sw/device/lib/hal/i2c.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/sw/device/lib/hal/i2c.c b/sw/device/lib/hal/i2c.c index 350c6a0bd..90e1180c7 100644 --- a/sw/device/lib/hal/i2c.c +++ b/sw/device/lib/hal/i2c.c @@ -131,11 +131,6 @@ void i2c_init(i2c_t i2c, i2c_speed_mode_t speed_mode) void i2c_write_bytes(i2c_t i2c, uint8_t addr, const uint8_t *data, uint8_t num_bytes) { - // Reset the FMT FIFO as a precautionary step in case something goes wrong when controller's FSM - // is halted and the SW didn't manage to clear the FIFO during that scenario. - i2c_fifo_ctrl fifo_ctrl_reg = { .fmtrst = 1u }; - VOLATILE_WRITE(i2c->fifo_ctrl, fifo_ctrl_reg); - // Queue write request // // Send start bit, address and R/W bit first @@ -163,11 +158,6 @@ void i2c_write_bytes(i2c_t i2c, uint8_t addr, const uint8_t *data, uint8_t num_b void i2c_read_bytes(i2c_t i2c, uint8_t addr, uint8_t num_bytes) { - // Reset the FMT FIFO as a precautionary step in case something goes wrong when controller's FSM - // is halted and the SW didn't manage to clear the FIFO during that scenario. - i2c_fifo_ctrl fifo_ctrl_reg = { .fmtrst = 1u }; - VOLATILE_WRITE(i2c->fifo_ctrl, fifo_ctrl_reg); - // Queue read request // // Send start bit, address and R/W bit first