TOP_INTERRUPT_ROUTING requires that every interrupt-capable IP has one confirmed end-to-end delivery to the CPU. Instead of one test per IP, this is verified by a single consolidated, table-driven test: chip_rv_plic_all_irqs (V1, in the smoke regression). One test is less to maintain and a stronger check of the interrupt map, because it sweeps every source systematically and catches swapped or mis-indexed routing.
Test: chip_rv_plic_all_irqs (rv_plic_all_irqs_test / rv_plic_all_irqs_test_cheri); placeholder registered in hw/top_chip/dv/top_chip_sim_cfg.hjson.
For each PLIC-connected source, SW enables it in the owning IP and in the PLIC (priority above threshold), forces the interrupt via the IP's INTR_TEST register, then confirms delivery: MIP.MEIP asserts, SW claims the source and checks the claimed ID matches the expected source, clears the interrupt at the IP, completes the claim, and MIP.MEIP de-asserts. Machine mode is exercised for every source; supervisor mode (MIP.SEIP) for one representative source, since the source-to-PLIC routing is shared between the M and S PLIC contexts and the S-mode context plus SEIP path only need proving once.
Sources to cover (the PLIC intr_vector entries):
Forcing via INTR_TEST exercises the routing wire only, independent of whether each IP can generate its interrupt from a real hardware event; that is the IP block-level DV's responsibility and is not re-verified at the top level.
Out of scope here: PLIC priority arbitration and preemption (chip_rv_plic_priority, V2); the machine-timer interrupt, which is delivered directly and does not route through the PLIC (chip_rv_timer_irq); and KMAC, which has no PLIC-wired interrupt.
Supersedes the previous per-IP interrupt-routing plan. UART (#211) and timer (#212) no longer need separate routing tests: UART is covered by the walk, and the timer is chip_rv_timer_irq.
TOP_INTERRUPT_ROUTINGrequires that every interrupt-capable IP has one confirmed end-to-end delivery to the CPU. Instead of one test per IP, this is verified by a single consolidated, table-driven test:chip_rv_plic_all_irqs(V1, in thesmokeregression). One test is less to maintain and a stronger check of the interrupt map, because it sweeps every source systematically and catches swapped or mis-indexed routing.Test:
chip_rv_plic_all_irqs(rv_plic_all_irqs_test/rv_plic_all_irqs_test_cheri); placeholder registered inhw/top_chip/dv/top_chip_sim_cfg.hjson.For each PLIC-connected source, SW enables it in the owning IP and in the PLIC (priority above threshold), forces the interrupt via the IP's
INTR_TESTregister, then confirms delivery:MIP.MEIPasserts, SW claims the source and checks the claimed ID matches the expected source, clears the interrupt at the IP, completes the claim, andMIP.MEIPde-asserts. Machine mode is exercised for every source; supervisor mode (MIP.SEIP) for one representative source, since the source-to-PLIC routing is shared between the M and S PLIC contexts and the S-mode context plus SEIP path only need proving once.Sources to cover (the PLIC
intr_vectorentries):Forcing via
INTR_TESTexercises the routing wire only, independent of whether each IP can generate its interrupt from a real hardware event; that is the IP block-level DV's responsibility and is not re-verified at the top level.Out of scope here: PLIC priority arbitration and preemption (
chip_rv_plic_priority, V2); the machine-timer interrupt, which is delivered directly and does not route through the PLIC (chip_rv_timer_irq); and KMAC, which has no PLIC-wired interrupt.Supersedes the previous per-IP interrupt-routing plan. UART (#211) and timer (#212) no longer need separate routing tests: UART is covered by the walk, and the timer is
chip_rv_timer_irq.