diff --git a/fearless_simd/src/generated/ops.rs b/fearless_simd/src/generated/ops.rs index b05d9918..3fb94d07 100644 --- a/fearless_simd/src/generated/ops.rs +++ b/fearless_simd/src/generated/ops.rs @@ -21,6 +21,34 @@ impl core::ops::Neg for f32x4 { impl core::ops::Add for f32x4 { type Output = Self; #[doc = "Add two vectors element-wise."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, f32x4};"] + #[doc = "# fearless_simd::__simd_doctest! { add_f32x4,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_f32x4(simd: S) {"] + #[doc = " let a = f32x4::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0.0, 2.0, 4.0, 6.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = f32x4::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1.0, 3.0, 5.0, 7.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[f32; 4]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1.0, 5.0, 9.0, 13.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_f32x4(self, rhs) @@ -169,6 +197,37 @@ impl core::ops::Neg for i8x16 { impl core::ops::Add for i8x16 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, i8x16};"] + #[doc = "# fearless_simd::__simd_doctest! { add_i8x16,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_i8x16(simd: S) {"] + #[doc = " let a = i8x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, -1, 3, -3, 5, -5, 7, -7,"] + #[doc = " 9, -9, 11, -11, 13, -13, 15, -15,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = i8x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 2, -2, 4, -4, 6, -6, 8, -8,"] + #[doc = " 10, -10, 12, -12, 14, -14, 16, -16,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[i8; 16]>::from(a + b),"] + #[doc = " ["] + #[doc = " 3, -3, 7, -7, 11, -11, 15, -15,"] + #[doc = " 19, -19, 23, -23, 27, -27, 31, -31,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_i8x16(self, rhs) @@ -386,7 +445,9 @@ impl core::ops::Not for i8x16 { } impl core::ops::Shl for i8x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_i8x16(self, rhs) @@ -400,14 +461,22 @@ impl core::ops::ShlAssign for i8x16 { } impl core::ops::Shl for i8x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_i8x16(self, rhs) } } impl core::ops::ShlAssign for i8x16 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_i8x16(*self, rhs); @@ -415,7 +484,9 @@ impl core::ops::ShlAssign for i8x16 { } impl core::ops::Shr for i8x16 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_i8x16(self, rhs) @@ -429,14 +500,22 @@ impl core::ops::ShrAssign for i8x16 { } impl core::ops::Shr for i8x16 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_i8x16(self, rhs) } } impl core::ops::ShrAssign for i8x16 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_i8x16(*self, rhs); @@ -445,6 +524,37 @@ impl core::ops::ShrAssign for i8x16 { impl core::ops::Add for u8x16 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, u8x16};"] + #[doc = "# fearless_simd::__simd_doctest! { add_u8x16,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_u8x16(simd: S) {"] + #[doc = " let a = u8x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0, 2, 4, 6, 8, 10, 12, 14,"] + #[doc = " 16, 18, 20, 22, 24, 26, 28, 30,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = u8x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, 3, 5, 7, 9, 11, 13, 15,"] + #[doc = " 17, 19, 21, 23, 25, 27, 29, 31,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[u8; 16]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1, 5, 9, 13, 17, 21, 25, 29,"] + #[doc = " 33, 37, 41, 45, 49, 53, 57, 61,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_u8x16(self, rhs) @@ -662,7 +772,9 @@ impl core::ops::Not for u8x16 { } impl core::ops::Shl for u8x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_u8x16(self, rhs) @@ -676,14 +788,22 @@ impl core::ops::ShlAssign for u8x16 { } impl core::ops::Shl for u8x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_u8x16(self, rhs) } } impl core::ops::ShlAssign for u8x16 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_u8x16(*self, rhs); @@ -691,7 +811,9 @@ impl core::ops::ShlAssign for u8x16 { } impl core::ops::Shr for u8x16 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_u8x16(self, rhs) @@ -705,14 +827,22 @@ impl core::ops::ShrAssign for u8x16 { } impl core::ops::Shr for u8x16 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_u8x16(self, rhs) } } impl core::ops::ShrAssign for u8x16 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_u8x16(*self, rhs); @@ -782,6 +912,34 @@ impl core::ops::Neg for i16x8 { impl core::ops::Add for i16x8 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, i16x8};"] + #[doc = "# fearless_simd::__simd_doctest! { add_i16x8,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_i16x8(simd: S) {"] + #[doc = " let a = i16x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, -1, 3, -3, 5, -5, 7, -7,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = i16x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 2, -2, 4, -4, 6, -6, 8, -8,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[i16; 8]>::from(a + b),"] + #[doc = " ["] + #[doc = " 3, -3, 7, -7, 11, -11, 15, -15,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_i16x8(self, rhs) @@ -999,7 +1157,9 @@ impl core::ops::Not for i16x8 { } impl core::ops::Shl for i16x8 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_i16x8(self, rhs) @@ -1013,14 +1173,22 @@ impl core::ops::ShlAssign for i16x8 { } impl core::ops::Shl for i16x8 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_i16x8(self, rhs) } } impl core::ops::ShlAssign for i16x8 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_i16x8(*self, rhs); @@ -1028,7 +1196,9 @@ impl core::ops::ShlAssign for i16x8 { } impl core::ops::Shr for i16x8 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_i16x8(self, rhs) @@ -1042,14 +1212,22 @@ impl core::ops::ShrAssign for i16x8 { } impl core::ops::Shr for i16x8 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_i16x8(self, rhs) } } impl core::ops::ShrAssign for i16x8 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_i16x8(*self, rhs); @@ -1058,6 +1236,34 @@ impl core::ops::ShrAssign for i16x8 { impl core::ops::Add for u16x8 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, u16x8};"] + #[doc = "# fearless_simd::__simd_doctest! { add_u16x8,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_u16x8(simd: S) {"] + #[doc = " let a = u16x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0, 2, 4, 6, 8, 10, 12, 14,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = u16x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, 3, 5, 7, 9, 11, 13, 15,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[u16; 8]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1, 5, 9, 13, 17, 21, 25, 29,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_u16x8(self, rhs) @@ -1275,7 +1481,9 @@ impl core::ops::Not for u16x8 { } impl core::ops::Shl for u16x8 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_u16x8(self, rhs) @@ -1289,14 +1497,22 @@ impl core::ops::ShlAssign for u16x8 { } impl core::ops::Shl for u16x8 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_u16x8(self, rhs) } } impl core::ops::ShlAssign for u16x8 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_u16x8(*self, rhs); @@ -1304,7 +1520,9 @@ impl core::ops::ShlAssign for u16x8 { } impl core::ops::Shr for u16x8 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_u16x8(self, rhs) @@ -1318,14 +1536,22 @@ impl core::ops::ShrAssign for u16x8 { } impl core::ops::Shr for u16x8 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_u16x8(self, rhs) } } impl core::ops::ShrAssign for u16x8 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_u16x8(*self, rhs); @@ -1395,6 +1621,34 @@ impl core::ops::Neg for i32x4 { impl core::ops::Add for i32x4 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, i32x4};"] + #[doc = "# fearless_simd::__simd_doctest! { add_i32x4,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_i32x4(simd: S) {"] + #[doc = " let a = i32x4::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, -1, 3, -3,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = i32x4::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 2, -2, 4, -4,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[i32; 4]>::from(a + b),"] + #[doc = " ["] + #[doc = " 3, -3, 7, -7,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_i32x4(self, rhs) @@ -1612,7 +1866,9 @@ impl core::ops::Not for i32x4 { } impl core::ops::Shl for i32x4 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_i32x4(self, rhs) @@ -1626,14 +1882,22 @@ impl core::ops::ShlAssign for i32x4 { } impl core::ops::Shl for i32x4 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_i32x4(self, rhs) } } impl core::ops::ShlAssign for i32x4 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_i32x4(*self, rhs); @@ -1641,7 +1905,9 @@ impl core::ops::ShlAssign for i32x4 { } impl core::ops::Shr for i32x4 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_i32x4(self, rhs) @@ -1655,14 +1921,22 @@ impl core::ops::ShrAssign for i32x4 { } impl core::ops::Shr for i32x4 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_i32x4(self, rhs) } } impl core::ops::ShrAssign for i32x4 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_i32x4(*self, rhs); @@ -1671,6 +1945,34 @@ impl core::ops::ShrAssign for i32x4 { impl core::ops::Add for u32x4 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, u32x4};"] + #[doc = "# fearless_simd::__simd_doctest! { add_u32x4,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_u32x4(simd: S) {"] + #[doc = " let a = u32x4::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0, 2, 4, 6,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = u32x4::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, 3, 5, 7,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[u32; 4]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1, 5, 9, 13,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_u32x4(self, rhs) @@ -1888,7 +2190,9 @@ impl core::ops::Not for u32x4 { } impl core::ops::Shl for u32x4 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_u32x4(self, rhs) @@ -1902,14 +2206,22 @@ impl core::ops::ShlAssign for u32x4 { } impl core::ops::Shl for u32x4 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_u32x4(self, rhs) } } impl core::ops::ShlAssign for u32x4 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_u32x4(*self, rhs); @@ -1917,7 +2229,9 @@ impl core::ops::ShlAssign for u32x4 { } impl core::ops::Shr for u32x4 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_u32x4(self, rhs) @@ -1931,14 +2245,22 @@ impl core::ops::ShrAssign for u32x4 { } impl core::ops::Shr for u32x4 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_u32x4(self, rhs) } } impl core::ops::ShrAssign for u32x4 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_u32x4(*self, rhs); @@ -2008,6 +2330,34 @@ impl core::ops::Neg for f64x2 { impl core::ops::Add for f64x2 { type Output = Self; #[doc = "Add two vectors element-wise."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, f64x2};"] + #[doc = "# fearless_simd::__simd_doctest! { add_f64x2,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_f64x2(simd: S) {"] + #[doc = " let a = f64x2::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0.0, 2.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = f64x2::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1.0, 3.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[f64; 2]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1.0, 5.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_f64x2(self, rhs) @@ -2209,6 +2559,34 @@ impl core::ops::Neg for f32x8 { impl core::ops::Add for f32x8 { type Output = Self; #[doc = "Add two vectors element-wise."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, f32x8};"] + #[doc = "# fearless_simd::__simd_doctest! { add_f32x8,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_f32x8(simd: S) {"] + #[doc = " let a = f32x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0.0, 2.0, 4.0, 6.0, 8.0, 10.0, 12.0, 14.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = f32x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[f32; 8]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1.0, 5.0, 9.0, 13.0, 17.0, 21.0, 25.0, 29.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_f32x8(self, rhs) @@ -2357,6 +2735,43 @@ impl core::ops::Neg for i8x32 { impl core::ops::Add for i8x32 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, i8x32};"] + #[doc = "# fearless_simd::__simd_doctest! { add_i8x32,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_i8x32(simd: S) {"] + #[doc = " let a = i8x32::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, -1, 3, -3, 5, -5, 7, -7,"] + #[doc = " 9, -9, 11, -11, 13, -13, 15, -15,"] + #[doc = " 17, -17, 19, -19, 21, -21, 23, -23,"] + #[doc = " 25, -25, 27, -27, 29, -29, 31, -31,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = i8x32::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 2, -2, 4, -4, 6, -6, 8, -8,"] + #[doc = " 10, -10, 12, -12, 14, -14, 16, -16,"] + #[doc = " 18, -18, 20, -20, 22, -22, 24, -24,"] + #[doc = " 26, -26, 28, -28, 30, -30, 32, -32,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[i8; 32]>::from(a + b),"] + #[doc = " ["] + #[doc = " 3, -3, 7, -7, 11, -11, 15, -15,"] + #[doc = " 19, -19, 23, -23, 27, -27, 31, -31,"] + #[doc = " 35, -35, 39, -39, 43, -43, 47, -47,"] + #[doc = " 51, -51, 55, -55, 59, -59, 63, -63,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_i8x32(self, rhs) @@ -2574,7 +2989,9 @@ impl core::ops::Not for i8x32 { } impl core::ops::Shl for i8x32 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_i8x32(self, rhs) @@ -2588,14 +3005,22 @@ impl core::ops::ShlAssign for i8x32 { } impl core::ops::Shl for i8x32 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_i8x32(self, rhs) } } impl core::ops::ShlAssign for i8x32 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_i8x32(*self, rhs); @@ -2603,7 +3028,9 @@ impl core::ops::ShlAssign for i8x32 { } impl core::ops::Shr for i8x32 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_i8x32(self, rhs) @@ -2617,14 +3044,22 @@ impl core::ops::ShrAssign for i8x32 { } impl core::ops::Shr for i8x32 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_i8x32(self, rhs) } } impl core::ops::ShrAssign for i8x32 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_i8x32(*self, rhs); @@ -2633,6 +3068,43 @@ impl core::ops::ShrAssign for i8x32 { impl core::ops::Add for u8x32 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, u8x32};"] + #[doc = "# fearless_simd::__simd_doctest! { add_u8x32,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_u8x32(simd: S) {"] + #[doc = " let a = u8x32::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0, 2, 4, 6, 8, 10, 12, 14,"] + #[doc = " 16, 18, 20, 22, 24, 26, 28, 30,"] + #[doc = " 32, 34, 36, 38, 40, 42, 44, 46,"] + #[doc = " 48, 50, 52, 54, 56, 58, 60, 62,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = u8x32::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, 3, 5, 7, 9, 11, 13, 15,"] + #[doc = " 17, 19, 21, 23, 25, 27, 29, 31,"] + #[doc = " 33, 35, 37, 39, 41, 43, 45, 47,"] + #[doc = " 49, 51, 53, 55, 57, 59, 61, 63,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[u8; 32]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1, 5, 9, 13, 17, 21, 25, 29,"] + #[doc = " 33, 37, 41, 45, 49, 53, 57, 61,"] + #[doc = " 65, 69, 73, 77, 81, 85, 89, 93,"] + #[doc = " 97, 101, 105, 109, 113, 117, 121, 125,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_u8x32(self, rhs) @@ -2850,7 +3322,9 @@ impl core::ops::Not for u8x32 { } impl core::ops::Shl for u8x32 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_u8x32(self, rhs) @@ -2864,14 +3338,22 @@ impl core::ops::ShlAssign for u8x32 { } impl core::ops::Shl for u8x32 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_u8x32(self, rhs) } } impl core::ops::ShlAssign for u8x32 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_u8x32(*self, rhs); @@ -2879,7 +3361,9 @@ impl core::ops::ShlAssign for u8x32 { } impl core::ops::Shr for u8x32 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_u8x32(self, rhs) @@ -2893,14 +3377,22 @@ impl core::ops::ShrAssign for u8x32 { } impl core::ops::Shr for u8x32 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_u8x32(self, rhs) } } impl core::ops::ShrAssign for u8x32 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_u8x32(*self, rhs); @@ -2970,6 +3462,37 @@ impl core::ops::Neg for i16x16 { impl core::ops::Add for i16x16 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, i16x16};"] + #[doc = "# fearless_simd::__simd_doctest! { add_i16x16,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_i16x16(simd: S) {"] + #[doc = " let a = i16x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, -1, 3, -3, 5, -5, 7, -7,"] + #[doc = " 9, -9, 11, -11, 13, -13, 15, -15,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = i16x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 2, -2, 4, -4, 6, -6, 8, -8,"] + #[doc = " 10, -10, 12, -12, 14, -14, 16, -16,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[i16; 16]>::from(a + b),"] + #[doc = " ["] + #[doc = " 3, -3, 7, -7, 11, -11, 15, -15,"] + #[doc = " 19, -19, 23, -23, 27, -27, 31, -31,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_i16x16(self, rhs) @@ -3187,7 +3710,9 @@ impl core::ops::Not for i16x16 { } impl core::ops::Shl for i16x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_i16x16(self, rhs) @@ -3201,14 +3726,22 @@ impl core::ops::ShlAssign for i16x16 { } impl core::ops::Shl for i16x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_i16x16(self, rhs) } } impl core::ops::ShlAssign for i16x16 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_i16x16(*self, rhs); @@ -3216,7 +3749,9 @@ impl core::ops::ShlAssign for i16x16 { } impl core::ops::Shr for i16x16 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_i16x16(self, rhs) @@ -3230,14 +3765,22 @@ impl core::ops::ShrAssign for i16x16 { } impl core::ops::Shr for i16x16 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_i16x16(self, rhs) } } impl core::ops::ShrAssign for i16x16 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_i16x16(*self, rhs); @@ -3246,6 +3789,37 @@ impl core::ops::ShrAssign for i16x16 { impl core::ops::Add for u16x16 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, u16x16};"] + #[doc = "# fearless_simd::__simd_doctest! { add_u16x16,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_u16x16(simd: S) {"] + #[doc = " let a = u16x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0, 2, 4, 6, 8, 10, 12, 14,"] + #[doc = " 16, 18, 20, 22, 24, 26, 28, 30,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = u16x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, 3, 5, 7, 9, 11, 13, 15,"] + #[doc = " 17, 19, 21, 23, 25, 27, 29, 31,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[u16; 16]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1, 5, 9, 13, 17, 21, 25, 29,"] + #[doc = " 33, 37, 41, 45, 49, 53, 57, 61,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_u16x16(self, rhs) @@ -3463,7 +4037,9 @@ impl core::ops::Not for u16x16 { } impl core::ops::Shl for u16x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_u16x16(self, rhs) @@ -3477,14 +4053,22 @@ impl core::ops::ShlAssign for u16x16 { } impl core::ops::Shl for u16x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_u16x16(self, rhs) } } impl core::ops::ShlAssign for u16x16 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_u16x16(*self, rhs); @@ -3492,7 +4076,9 @@ impl core::ops::ShlAssign for u16x16 { } impl core::ops::Shr for u16x16 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_u16x16(self, rhs) @@ -3506,14 +4092,22 @@ impl core::ops::ShrAssign for u16x16 { } impl core::ops::Shr for u16x16 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_u16x16(self, rhs) } } impl core::ops::ShrAssign for u16x16 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_u16x16(*self, rhs); @@ -3583,6 +4177,34 @@ impl core::ops::Neg for i32x8 { impl core::ops::Add for i32x8 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, i32x8};"] + #[doc = "# fearless_simd::__simd_doctest! { add_i32x8,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_i32x8(simd: S) {"] + #[doc = " let a = i32x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, -1, 3, -3, 5, -5, 7, -7,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = i32x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 2, -2, 4, -4, 6, -6, 8, -8,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[i32; 8]>::from(a + b),"] + #[doc = " ["] + #[doc = " 3, -3, 7, -7, 11, -11, 15, -15,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_i32x8(self, rhs) @@ -3800,7 +4422,9 @@ impl core::ops::Not for i32x8 { } impl core::ops::Shl for i32x8 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_i32x8(self, rhs) @@ -3814,14 +4438,22 @@ impl core::ops::ShlAssign for i32x8 { } impl core::ops::Shl for i32x8 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_i32x8(self, rhs) } } impl core::ops::ShlAssign for i32x8 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_i32x8(*self, rhs); @@ -3829,7 +4461,9 @@ impl core::ops::ShlAssign for i32x8 { } impl core::ops::Shr for i32x8 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_i32x8(self, rhs) @@ -3843,14 +4477,22 @@ impl core::ops::ShrAssign for i32x8 { } impl core::ops::Shr for i32x8 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_i32x8(self, rhs) } } impl core::ops::ShrAssign for i32x8 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_i32x8(*self, rhs); @@ -3859,6 +4501,34 @@ impl core::ops::ShrAssign for i32x8 { impl core::ops::Add for u32x8 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, u32x8};"] + #[doc = "# fearless_simd::__simd_doctest! { add_u32x8,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_u32x8(simd: S) {"] + #[doc = " let a = u32x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0, 2, 4, 6, 8, 10, 12, 14,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = u32x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, 3, 5, 7, 9, 11, 13, 15,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[u32; 8]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1, 5, 9, 13, 17, 21, 25, 29,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_u32x8(self, rhs) @@ -4076,7 +4746,9 @@ impl core::ops::Not for u32x8 { } impl core::ops::Shl for u32x8 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_u32x8(self, rhs) @@ -4090,14 +4762,22 @@ impl core::ops::ShlAssign for u32x8 { } impl core::ops::Shl for u32x8 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_u32x8(self, rhs) } } impl core::ops::ShlAssign for u32x8 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_u32x8(*self, rhs); @@ -4105,7 +4785,9 @@ impl core::ops::ShlAssign for u32x8 { } impl core::ops::Shr for u32x8 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_u32x8(self, rhs) @@ -4119,14 +4801,22 @@ impl core::ops::ShrAssign for u32x8 { } impl core::ops::Shr for u32x8 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_u32x8(self, rhs) } } impl core::ops::ShrAssign for u32x8 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_u32x8(*self, rhs); @@ -4196,6 +4886,34 @@ impl core::ops::Neg for f64x4 { impl core::ops::Add for f64x4 { type Output = Self; #[doc = "Add two vectors element-wise."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, f64x4};"] + #[doc = "# fearless_simd::__simd_doctest! { add_f64x4,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_f64x4(simd: S) {"] + #[doc = " let a = f64x4::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0.0, 2.0, 4.0, 6.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = f64x4::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1.0, 3.0, 5.0, 7.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[f64; 4]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1.0, 5.0, 9.0, 13.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_f64x4(self, rhs) @@ -4397,6 +5115,37 @@ impl core::ops::Neg for f32x16 { impl core::ops::Add for f32x16 { type Output = Self; #[doc = "Add two vectors element-wise."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, f32x16};"] + #[doc = "# fearless_simd::__simd_doctest! { add_f32x16,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_f32x16(simd: S) {"] + #[doc = " let a = f32x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0.0, 2.0, 4.0, 6.0, 8.0, 10.0, 12.0, 14.0,"] + #[doc = " 16.0, 18.0, 20.0, 22.0, 24.0, 26.0, 28.0, 30.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = f32x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0,"] + #[doc = " 17.0, 19.0, 21.0, 23.0, 25.0, 27.0, 29.0, 31.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[f32; 16]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1.0, 5.0, 9.0, 13.0, 17.0, 21.0, 25.0, 29.0,"] + #[doc = " 33.0, 37.0, 41.0, 45.0, 49.0, 53.0, 57.0, 61.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_f32x16(self, rhs) @@ -4545,6 +5294,55 @@ impl core::ops::Neg for i8x64 { impl core::ops::Add for i8x64 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, i8x64};"] + #[doc = "# fearless_simd::__simd_doctest! { add_i8x64,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_i8x64(simd: S) {"] + #[doc = " let a = i8x64::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, -1, 3, -3, 5, -5, 7, -7,"] + #[doc = " 9, -9, 11, -11, 13, -13, 15, -15,"] + #[doc = " 17, -17, 19, -19, 21, -21, 23, -23,"] + #[doc = " 25, -25, 27, -27, 29, -29, 31, -31,"] + #[doc = " 33, -33, 35, -35, 37, -37, 39, -39,"] + #[doc = " 41, -41, 43, -43, 45, -45, 47, -47,"] + #[doc = " 49, -49, 51, -51, 53, -53, 55, -55,"] + #[doc = " 57, -57, 59, -59, 61, -61, 63, -63,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = i8x64::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 2, -2, 4, -4, 6, -6, 8, -8,"] + #[doc = " 10, -10, 12, -12, 14, -14, 16, -16,"] + #[doc = " 18, -18, 20, -20, 22, -22, 24, -24,"] + #[doc = " 26, -26, 28, -28, 30, -30, 32, -32,"] + #[doc = " 34, -34, 36, -36, 38, -38, 40, -40,"] + #[doc = " 42, -42, 44, -44, 46, -46, 48, -48,"] + #[doc = " 50, -50, 52, -52, 54, -54, 56, -56,"] + #[doc = " 58, -58, 60, -60, 62, -62, 64, -64,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[i8; 64]>::from(a + b),"] + #[doc = " ["] + #[doc = " 3, -3, 7, -7, 11, -11, 15, -15,"] + #[doc = " 19, -19, 23, -23, 27, -27, 31, -31,"] + #[doc = " 35, -35, 39, -39, 43, -43, 47, -47,"] + #[doc = " 51, -51, 55, -55, 59, -59, 63, -63,"] + #[doc = " 67, -67, 71, -71, 75, -75, 79, -79,"] + #[doc = " 83, -83, 87, -87, 91, -91, 95, -95,"] + #[doc = " 99, -99, 103, -103, 107, -107, 111, -111,"] + #[doc = " 115, -115, 119, -119, 123, -123, 127, -127,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_i8x64(self, rhs) @@ -4762,7 +5560,9 @@ impl core::ops::Not for i8x64 { } impl core::ops::Shl for i8x64 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_i8x64(self, rhs) @@ -4776,14 +5576,22 @@ impl core::ops::ShlAssign for i8x64 { } impl core::ops::Shl for i8x64 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_i8x64(self, rhs) } } impl core::ops::ShlAssign for i8x64 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_i8x64(*self, rhs); @@ -4791,7 +5599,9 @@ impl core::ops::ShlAssign for i8x64 { } impl core::ops::Shr for i8x64 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_i8x64(self, rhs) @@ -4805,14 +5615,22 @@ impl core::ops::ShrAssign for i8x64 { } impl core::ops::Shr for i8x64 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_i8x64(self, rhs) } } impl core::ops::ShrAssign for i8x64 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_i8x64(*self, rhs); @@ -4821,6 +5639,55 @@ impl core::ops::ShrAssign for i8x64 { impl core::ops::Add for u8x64 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, u8x64};"] + #[doc = "# fearless_simd::__simd_doctest! { add_u8x64,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_u8x64(simd: S) {"] + #[doc = " let a = u8x64::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0, 2, 4, 6, 8, 10, 12, 14,"] + #[doc = " 16, 18, 20, 22, 24, 26, 28, 30,"] + #[doc = " 32, 34, 36, 38, 40, 42, 44, 46,"] + #[doc = " 48, 50, 52, 54, 56, 58, 60, 62,"] + #[doc = " 64, 66, 68, 70, 72, 74, 76, 78,"] + #[doc = " 80, 82, 84, 86, 88, 90, 92, 94,"] + #[doc = " 96, 98, 100, 102, 104, 106, 108, 110,"] + #[doc = " 112, 114, 116, 118, 120, 122, 124, 126,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = u8x64::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, 3, 5, 7, 9, 11, 13, 15,"] + #[doc = " 17, 19, 21, 23, 25, 27, 29, 31,"] + #[doc = " 33, 35, 37, 39, 41, 43, 45, 47,"] + #[doc = " 49, 51, 53, 55, 57, 59, 61, 63,"] + #[doc = " 65, 67, 69, 71, 73, 75, 77, 79,"] + #[doc = " 81, 83, 85, 87, 89, 91, 93, 95,"] + #[doc = " 97, 99, 101, 103, 105, 107, 109, 111,"] + #[doc = " 113, 115, 117, 119, 121, 123, 125, 127,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[u8; 64]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1, 5, 9, 13, 17, 21, 25, 29,"] + #[doc = " 33, 37, 41, 45, 49, 53, 57, 61,"] + #[doc = " 65, 69, 73, 77, 81, 85, 89, 93,"] + #[doc = " 97, 101, 105, 109, 113, 117, 121, 125,"] + #[doc = " 129, 133, 137, 141, 145, 149, 153, 157,"] + #[doc = " 161, 165, 169, 173, 177, 181, 185, 189,"] + #[doc = " 193, 197, 201, 205, 209, 213, 217, 221,"] + #[doc = " 225, 229, 233, 237, 241, 245, 249, 253,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_u8x64(self, rhs) @@ -5038,7 +5905,9 @@ impl core::ops::Not for u8x64 { } impl core::ops::Shl for u8x64 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_u8x64(self, rhs) @@ -5052,14 +5921,22 @@ impl core::ops::ShlAssign for u8x64 { } impl core::ops::Shl for u8x64 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_u8x64(self, rhs) } } impl core::ops::ShlAssign for u8x64 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_u8x64(*self, rhs); @@ -5067,7 +5944,9 @@ impl core::ops::ShlAssign for u8x64 { } impl core::ops::Shr for u8x64 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_u8x64(self, rhs) @@ -5081,14 +5960,22 @@ impl core::ops::ShrAssign for u8x64 { } impl core::ops::Shr for u8x64 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_u8x64(self, rhs) } } impl core::ops::ShrAssign for u8x64 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_u8x64(*self, rhs); @@ -5158,6 +6045,43 @@ impl core::ops::Neg for i16x32 { impl core::ops::Add for i16x32 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, i16x32};"] + #[doc = "# fearless_simd::__simd_doctest! { add_i16x32,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_i16x32(simd: S) {"] + #[doc = " let a = i16x32::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, -1, 3, -3, 5, -5, 7, -7,"] + #[doc = " 9, -9, 11, -11, 13, -13, 15, -15,"] + #[doc = " 17, -17, 19, -19, 21, -21, 23, -23,"] + #[doc = " 25, -25, 27, -27, 29, -29, 31, -31,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = i16x32::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 2, -2, 4, -4, 6, -6, 8, -8,"] + #[doc = " 10, -10, 12, -12, 14, -14, 16, -16,"] + #[doc = " 18, -18, 20, -20, 22, -22, 24, -24,"] + #[doc = " 26, -26, 28, -28, 30, -30, 32, -32,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[i16; 32]>::from(a + b),"] + #[doc = " ["] + #[doc = " 3, -3, 7, -7, 11, -11, 15, -15,"] + #[doc = " 19, -19, 23, -23, 27, -27, 31, -31,"] + #[doc = " 35, -35, 39, -39, 43, -43, 47, -47,"] + #[doc = " 51, -51, 55, -55, 59, -59, 63, -63,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_i16x32(self, rhs) @@ -5375,7 +6299,9 @@ impl core::ops::Not for i16x32 { } impl core::ops::Shl for i16x32 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_i16x32(self, rhs) @@ -5389,14 +6315,22 @@ impl core::ops::ShlAssign for i16x32 { } impl core::ops::Shl for i16x32 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_i16x32(self, rhs) } } impl core::ops::ShlAssign for i16x32 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_i16x32(*self, rhs); @@ -5404,7 +6338,9 @@ impl core::ops::ShlAssign for i16x32 { } impl core::ops::Shr for i16x32 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_i16x32(self, rhs) @@ -5418,14 +6354,22 @@ impl core::ops::ShrAssign for i16x32 { } impl core::ops::Shr for i16x32 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_i16x32(self, rhs) } } impl core::ops::ShrAssign for i16x32 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_i16x32(*self, rhs); @@ -5434,6 +6378,43 @@ impl core::ops::ShrAssign for i16x32 { impl core::ops::Add for u16x32 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, u16x32};"] + #[doc = "# fearless_simd::__simd_doctest! { add_u16x32,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_u16x32(simd: S) {"] + #[doc = " let a = u16x32::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0, 2, 4, 6, 8, 10, 12, 14,"] + #[doc = " 16, 18, 20, 22, 24, 26, 28, 30,"] + #[doc = " 32, 34, 36, 38, 40, 42, 44, 46,"] + #[doc = " 48, 50, 52, 54, 56, 58, 60, 62,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = u16x32::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, 3, 5, 7, 9, 11, 13, 15,"] + #[doc = " 17, 19, 21, 23, 25, 27, 29, 31,"] + #[doc = " 33, 35, 37, 39, 41, 43, 45, 47,"] + #[doc = " 49, 51, 53, 55, 57, 59, 61, 63,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[u16; 32]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1, 5, 9, 13, 17, 21, 25, 29,"] + #[doc = " 33, 37, 41, 45, 49, 53, 57, 61,"] + #[doc = " 65, 69, 73, 77, 81, 85, 89, 93,"] + #[doc = " 97, 101, 105, 109, 113, 117, 121, 125,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_u16x32(self, rhs) @@ -5651,7 +6632,9 @@ impl core::ops::Not for u16x32 { } impl core::ops::Shl for u16x32 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_u16x32(self, rhs) @@ -5665,14 +6648,22 @@ impl core::ops::ShlAssign for u16x32 { } impl core::ops::Shl for u16x32 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_u16x32(self, rhs) } } impl core::ops::ShlAssign for u16x32 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_u16x32(*self, rhs); @@ -5680,7 +6671,9 @@ impl core::ops::ShlAssign for u16x32 { } impl core::ops::Shr for u16x32 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_u16x32(self, rhs) @@ -5694,14 +6687,22 @@ impl core::ops::ShrAssign for u16x32 { } impl core::ops::Shr for u16x32 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_u16x32(self, rhs) } } impl core::ops::ShrAssign for u16x32 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_u16x32(*self, rhs); @@ -5771,6 +6772,37 @@ impl core::ops::Neg for i32x16 { impl core::ops::Add for i32x16 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, i32x16};"] + #[doc = "# fearless_simd::__simd_doctest! { add_i32x16,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_i32x16(simd: S) {"] + #[doc = " let a = i32x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, -1, 3, -3, 5, -5, 7, -7,"] + #[doc = " 9, -9, 11, -11, 13, -13, 15, -15,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = i32x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 2, -2, 4, -4, 6, -6, 8, -8,"] + #[doc = " 10, -10, 12, -12, 14, -14, 16, -16,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[i32; 16]>::from(a + b),"] + #[doc = " ["] + #[doc = " 3, -3, 7, -7, 11, -11, 15, -15,"] + #[doc = " 19, -19, 23, -23, 27, -27, 31, -31,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_i32x16(self, rhs) @@ -5988,7 +7020,9 @@ impl core::ops::Not for i32x16 { } impl core::ops::Shl for i32x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_i32x16(self, rhs) @@ -6002,14 +7036,22 @@ impl core::ops::ShlAssign for i32x16 { } impl core::ops::Shl for i32x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_i32x16(self, rhs) } } impl core::ops::ShlAssign for i32x16 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_i32x16(*self, rhs); @@ -6017,7 +7059,9 @@ impl core::ops::ShlAssign for i32x16 { } impl core::ops::Shr for i32x16 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_i32x16(self, rhs) @@ -6031,14 +7075,22 @@ impl core::ops::ShrAssign for i32x16 { } impl core::ops::Shr for i32x16 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_i32x16(self, rhs) } } impl core::ops::ShrAssign for i32x16 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_i32x16(*self, rhs); @@ -6047,6 +7099,37 @@ impl core::ops::ShrAssign for i32x16 { impl core::ops::Add for u32x16 { type Output = Self; #[doc = "Add two vectors element-wise, wrapping on overflow."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, u32x16};"] + #[doc = "# fearless_simd::__simd_doctest! { add_u32x16,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_u32x16(simd: S) {"] + #[doc = " let a = u32x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0, 2, 4, 6, 8, 10, 12, 14,"] + #[doc = " 16, 18, 20, 22, 24, 26, 28, 30,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = u32x16::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1, 3, 5, 7, 9, 11, 13, 15,"] + #[doc = " 17, 19, 21, 23, 25, 27, 29, 31,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[u32; 16]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1, 5, 9, 13, 17, 21, 25, 29,"] + #[doc = " 33, 37, 41, 45, 49, 53, 57, 61,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_u32x16(self, rhs) @@ -6264,7 +7347,9 @@ impl core::ops::Not for u32x16 { } impl core::ops::Shl for u32x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] #[inline(always)] fn shl(self, rhs: u32) -> Self::Output { self.simd.shl_u32x16(self, rhs) @@ -6278,14 +7363,22 @@ impl core::ops::ShlAssign for u32x16 { } impl core::ops::Shl for u32x16 { type Output = Self; - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl(self, rhs: Self) -> Self::Output { self.simd.shlv_u32x16(self, rhs) } } impl core::ops::ShlAssign for u32x16 { - #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element left by the given number of bits."] + #[doc = ""] + #[doc = "Bits shifted out of the left side are discarded, and zeros are shifted in on the right."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shl_assign(&mut self, rhs: Self) { *self = self.simd.shlv_u32x16(*self, rhs); @@ -6293,7 +7386,9 @@ impl core::ops::ShlAssign for u32x16 { } impl core::ops::Shr for u32x16 { type Output = Self; - #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = "Shift each element right by the given number of bits."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] #[inline(always)] fn shr(self, rhs: u32) -> Self::Output { self.simd.shr_u32x16(self, rhs) @@ -6307,14 +7402,22 @@ impl core::ops::ShrAssign for u32x16 { } impl core::ops::Shr for u32x16 { type Output = Self; - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr(self, rhs: Self) -> Self::Output { self.simd.shrv_u32x16(self, rhs) } } impl core::ops::ShrAssign for u32x16 { - #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nThis operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] + #[doc = "Shift each element right by the corresponding element in another vector."] + #[doc = ""] + #[doc = "For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated."] + #[doc = ""] + #[doc = "This operation is not implemented in hardware on all platforms. On WebAssembly, and on x86 platforms without AVX2, this will use a fallback scalar implementation."] #[inline(always)] fn shr_assign(&mut self, rhs: Self) { *self = self.simd.shrv_u32x16(*self, rhs); @@ -6384,6 +7487,34 @@ impl core::ops::Neg for f64x8 { impl core::ops::Add for f64x8 { type Output = Self; #[doc = "Add two vectors element-wise."] + #[doc = ""] + #[doc = "```rust"] + #[doc = "# use fearless_simd::{prelude::*, f64x8};"] + #[doc = "# fearless_simd::__simd_doctest! { add_f64x8,"] + #[doc = "#[inline(always)]"] + #[doc = "fn add_f64x8(simd: S) {"] + #[doc = " let a = f64x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 0.0, 2.0, 4.0, 6.0, 8.0, 10.0, 12.0, 14.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = " let b = f64x8::simd_from("] + #[doc = " simd,"] + #[doc = " ["] + #[doc = " 1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = ""] + #[doc = " assert_eq!("] + #[doc = " <[f64; 8]>::from(a + b),"] + #[doc = " ["] + #[doc = " 1.0, 5.0, 9.0, 13.0, 17.0, 21.0, 25.0, 29.0,"] + #[doc = " ],"] + #[doc = " );"] + #[doc = "}"] + #[doc = "# }"] + #[doc = "```"] #[inline(always)] fn add(self, rhs: Self) -> Self::Output { self.simd.add_f64x8(self, rhs) diff --git a/fearless_simd/src/macros.rs b/fearless_simd/src/macros.rs index 09a9a150..c7273dc3 100644 --- a/fearless_simd/src/macros.rs +++ b/fearless_simd/src/macros.rs @@ -323,6 +323,82 @@ macro_rules! internal_unstable_dispatch_inner { }; } +/// Implementation detail used by generated documentation tests; this is not public API. +#[macro_export] +#[doc(hidden)] +macro_rules! __simd_doctest { + ($check:ident, $item:item $(,)?) => {{ + $item + + #[inline(always)] + fn __fearless_simd_doctest_run_one( + name: &'static str, + simd: S, + check: fn(S), + ) { + let result = ::std::panic::catch_unwind(::std::panic::AssertUnwindSafe(|| { + $crate::Simd::vectorize(simd, #[inline(always)] || check(simd)); + })); + + if let Err(payload) = result { + ::std::eprintln!("SIMD doctest failed on {name}"); + ::std::panic::resume_unwind(payload); + } + } + + __fearless_simd_doctest_run_one( + "fallback", + $crate::Fallback::new(), + $check::<$crate::Fallback>, + ); + $crate::__fearless_simd_doctest_detected_levels!( + __fearless_simd_doctest_run_one, + $check + ); + }}; +} + +/// Implementation detail used by [`__simd_doctest`]; this is not public API. +#[macro_export] +#[doc(hidden)] +#[cfg(any(feature = "std", target_arch = "wasm32"))] +macro_rules! __fearless_simd_doctest_detected_levels { + ($run_one:ident, $check:ident) => {{ + let __fearless_simd_level = $crate::Level::new(); + + #[cfg(target_arch = "aarch64")] + if let Some(neon) = __fearless_simd_level.as_neon() { + $run_one("neon", neon, $check::<$crate::aarch64::Neon>); + } + + #[cfg(all(target_arch = "wasm32", target_feature = "simd128"))] + if let Some(wasm) = __fearless_simd_level.as_wasm_simd128() { + $run_one("wasm_simd128", wasm, $check::<$crate::wasm32::WasmSimd128>); + } + + #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] + { + if let Some(sse4_2) = __fearless_simd_level.as_sse4_2() { + $run_one("sse4.2", sse4_2, $check::<$crate::x86::Sse4_2>); + } + if let Some(avx2) = __fearless_simd_level.as_avx2() { + $run_one("avx2", avx2, $check::<$crate::x86::Avx2>); + } + if let Some(avx512) = __fearless_simd_level.as_avx512() { + $run_one("avx512", avx512, $check::<$crate::x86::Avx512>); + } + } + }}; +} + +/// Implementation detail used by [`__simd_doctest`]; this is not public API. +#[macro_export] +#[doc(hidden)] +#[cfg(not(any(feature = "std", target_arch = "wasm32")))] +macro_rules! __fearless_simd_doctest_detected_levels { + ($run_one:ident, $check:ident) => {{}}; +} + #[cfg(test)] // This expect also validates that we haven't missed any levels! #[expect( diff --git a/fearless_simd_gen/src/mk_ops.rs b/fearless_simd_gen/src/mk_ops.rs index 20ddc4c2..b0dc1969 100644 --- a/fearless_simd_gen/src/mk_ops.rs +++ b/fearless_simd_gen/src/mk_ops.rs @@ -7,7 +7,7 @@ use quote::{format_ident, quote}; use crate::{ generic::generic_op_name, ops::{CoreOpTrait, OpKind, OpSig, TyFlavor, overloaded_ops_for}, - types::{SIMD_TYPES, ScalarType, type_imports}, + types::{SIMD_TYPES, ScalarType, VecType, type_imports}, }; pub(crate) fn mk_ops() -> TokenStream { @@ -30,13 +30,20 @@ pub(crate) fn mk_ops() -> TokenStream { let simd_fn = generic_op_name(simd_name, ty); let opfn = Ident::new(opfn, Span::call_site()); let doc = op.format_docstring(TyFlavor::VecImpl); + let method_doc = if core_op == CoreOpTrait::Add { + format!("{doc}\n\n{}", add_doctest(ty)) + } else { + doc.clone() + }; + let doc_attrs = make_doc_attrs(&doc); + let method_doc_attrs = make_doc_attrs(&method_doc); match core_op { CoreOpTrait::ShlVectored | CoreOpTrait::ShrVectored => { impls.push(quote! { impl core::ops::#trait_id for #simd { type Output = Self; - #[doc = #doc] + #method_doc_attrs #[inline(always)] fn #opfn(self, rhs: Self) -> Self::Output { self.simd.#simd_fn(self, rhs) @@ -44,7 +51,7 @@ pub(crate) fn mk_ops() -> TokenStream { } impl core::ops::#trait_assign_id for #simd { - #[doc = #doc] + #doc_attrs #[inline(always)] fn #op_assign_fn(&mut self, rhs: Self) { *self = self.simd.#simd_fn(*self, rhs); @@ -56,7 +63,7 @@ pub(crate) fn mk_ops() -> TokenStream { impls.push(quote! { impl core::ops::#trait_id for #simd { type Output = Self; - #[doc = #doc] + #method_doc_attrs #[inline(always)] fn #opfn(self, rhs: u32) -> Self::Output { self.simd.#simd_fn(self, rhs) @@ -75,7 +82,7 @@ pub(crate) fn mk_ops() -> TokenStream { impls.push(quote! { impl core::ops::#trait_id for #simd { type Output = Self; - #[doc = #doc] + #method_doc_attrs #[inline(always)] fn #opfn(self) -> Self::Output { self.simd.#simd_fn(self) @@ -114,7 +121,7 @@ pub(crate) fn mk_ops() -> TokenStream { impls.push(quote! { impl core::ops::#trait_id for #simd { type Output = Self; - #[doc = #doc] + #method_doc_attrs #[inline(always)] fn #opfn(self, rhs: Self) -> Self::Output { self.simd.#simd_fn(self, rhs) @@ -122,7 +129,7 @@ pub(crate) fn mk_ops() -> TokenStream { } impl core::ops::#trait_assign_id for #simd { - #[doc = #doc] + #doc_attrs #[inline(always)] fn #op_assign_fn(&mut self, rhs: Self) { *self = self.simd.#simd_fn(*self, rhs); @@ -142,3 +149,100 @@ pub(crate) fn mk_ops() -> TokenStream { #( #impls )* } } + +fn make_doc_attrs(doc: &str) -> TokenStream { + let lines = doc.lines(); + quote! { + #(#[doc = #lines])* + } +} + +fn add_doctest(ty: &VecType) -> String { + let rust_name = ty.rust_name(); + let fn_name = format!("add_{rust_name}"); + let scalar_name = ty.scalar.rust_name(ty.scalar_bits); + let (lhs, rhs, expected) = add_doctest_values(ty); + let lhs = format_array(&lhs); + let rhs = format_array(&rhs); + let expected = format_array(&expected); + let len = ty.len; + + format!( + r#"```rust +# use fearless_simd::{{prelude::*, {rust_name}}}; +# fearless_simd::__simd_doctest! {{ {fn_name}, +#[inline(always)] +fn {fn_name}(simd: S) {{ + let a = {rust_name}::simd_from( + simd, + {lhs}, + ); + let b = {rust_name}::simd_from( + simd, + {rhs}, + ); + + assert_eq!( + <[{scalar_name}; {len}]>::from(a + b), + {expected}, + ); +}} +# }} +```"# + ) +} + +fn add_doctest_values(ty: &VecType) -> (Vec, Vec, Vec) { + match ty.scalar { + ScalarType::Float | ScalarType::Unsigned => { + let lhs = (0..ty.len).map(|i| format_literal(2 * i, ty.scalar)); + let rhs = (0..ty.len).map(|i| format_literal(2 * i + 1, ty.scalar)); + let expected = (0..ty.len).map(|i| format_literal(4 * i + 1, ty.scalar)); + (lhs.collect(), rhs.collect(), expected.collect()) + } + ScalarType::Int => { + let value = |lane: usize, offset: usize| { + let magnitude = if lane % 2 == 0 { + lane + offset + } else { + lane + offset - 1 + }; + if lane % 2 == 0 { + magnitude.to_string() + } else { + format!("-{magnitude}") + } + }; + let lhs = (0..ty.len).map(|i| value(i, 1)); + let rhs = (0..ty.len).map(|i| value(i, 2)); + let expected = (0..ty.len).map(|i| { + if i % 2 == 0 { + (2 * i + 3).to_string() + } else { + format!("-{}", 2 * i + 1) + } + }); + (lhs.collect(), rhs.collect(), expected.collect()) + } + ScalarType::Mask => unreachable!("masks do not implement Add"), + } +} + +fn format_literal(value: usize, scalar: ScalarType) -> String { + if scalar == ScalarType::Float { + format!("{value}.0") + } else { + value.to_string() + } +} + +fn format_array(values: &[String]) -> String { + let mut array = String::from("[\n"); + for chunk in values.chunks(8) { + array.push_str(" "); + array.push_str(&chunk.join(", ")); + array.push_str(",\n"); + } + array.push_str(" ]"); + array +}