diff --git a/.github/scripts/check-sp11-integration.sh b/.github/scripts/check-sp11-integration.sh new file mode 100755 index 00000000000000..f1aae1ed61aef4 --- /dev/null +++ b/.github/scripts/check-sp11-integration.sh @@ -0,0 +1,163 @@ +#!/usr/bin/env bash +# SPDX-License-Identifier: GPL-2.0-only + +set -euo pipefail + +readonly SP11_BASE_COMMIT="8f953dd060bc6e8fb86ca2ea8a92f258141c0169" +readonly SP11_RANGE="${SP11_BASE_COMMIT}...HEAD" + +die() { + printf 'error: %s\n' "$*" >&2 + exit 1 +} + +git rev-parse --is-inside-work-tree >/dev/null 2>&1 || + die "run this check from the repository worktree" + +git cat-file -e "${SP11_BASE_COMMIT}^{commit}" 2>/dev/null || + die "required Surface Pro 11 base commit is unavailable" + +git merge-base --is-ancestor "${SP11_BASE_COMMIT}" HEAD || + die "HEAD does not descend from the approved Surface Pro 11 base commit" + +# When HEAD is the upstream-sync merge (two parents), the SP11 delta to +# validate is the first-parent line; the second parent is upstream's own +# code, which may carry pre-existing style patterns. +CHECKPATCH_RANGE="${SP11_RANGE}" +if git rev-parse -q --verify HEAD^2 >/dev/null 2>&1; then +CHECKPATCH_RANGE="${SP11_BASE_COMMIT}...HEAD^1" +fi + +# The style gate is scoped to the project's own delta. Upstream trees +# (jglathe's 7.2-rc line, Linux, Ubuntu) are absorbed through sync merges +# at any depth and may carry pre-existing style patterns, so checkpatch +# ERRORs are only actionable on files the SP11 integration authored or +# modified. The identities below are the project's integration authors; +# extend them if new integration identities are introduced. +readonly SP11_AUTHOR_A='Surface Pro 11 bring-up' +readonly SP11_AUTHOR_B='Leon Silcott' + +sp11_touched_files="$( + git log --format= --name-only --diff-filter=ACMRTUXB \ + --author="${SP11_AUTHOR_A}" --author="${SP11_AUTHOR_B}" \ + "${SP11_BASE_COMMIT}..HEAD" | + sed '/^$/d' | sort -u +)" + +git diff --check "${SP11_RANGE}" -- + +all_changed_paths=() +while IFS= read -r -d '' path; do + all_changed_paths+=("${path}") +done < <(git diff --name-only -z --diff-filter=ACMRTUXBD "${SP11_RANGE}" --) + +if ((${#all_changed_paths[@]} == 0)); then + printf 'No changes from the approved Surface Pro 11 base commit.\n' + exit 0 +fi + +present_paths=() +while IFS= read -r -d '' path; do + present_paths+=("${path}") +done < <(git diff --name-only -z --diff-filter=ACMRTUXB "${SP11_RANGE}" --) + +artifact_path_pattern='^(build|out|artifacts?|dist)/|(^|/)(\.config|Module\.symvers|modules\.order|System\.map|vmlinux|Image(\.gz)?)(/|$)|\.(a|bin|bz2|deb|ddeb|dwo|dtb|dtbo|dylib|efi|elf|gz|img|iso|ko|lz4|o|qcow2|rlib|rmeta|rpm|so|tar|tgz|xz|zip|zst)$' +private_file_pattern='(^|/)(\.env|id_rsa|id_ed25519|credentials?\.json)$|\.(p12|pfx)$' + +if ((${#present_paths[@]} > 0)); then + for path in "${present_paths[@]}"; do + [[ "${path}" =~ ${artifact_path_pattern} ]] && + die "generated build or binary artifact is tracked: ${path}" + [[ "${path}" =~ ${private_file_pattern} ]] && + die "possible private credential file is tracked: ${path}" + done +fi + +binary_paths="$( + git diff --numstat --diff-filter=ACMRTUXB "${SP11_RANGE}" -- | + awk -F '\t' '$1 == "-" && $2 == "-" { print $3 }' +)" +[[ -z "${binary_paths}" ]] || + die "binary changes are not accepted in the integration delta: ${binary_paths}" + +added_lines="$(mktemp)" +trap 'rm -f "${added_lines}"' EXIT + +git diff --no-ext-diff --unified=0 "${SP11_RANGE}" -- | + awk '/^\+\+\+ / { next } /^\+/ { sub(/^\+/, ""); print }' >"${added_lines}" + +local_path_pattern='/U'"sers/"'|/ho'"me/"'[[:alnum:]_.-]+/' +tunnel_pattern='ng'"rok"'|ts'"sh"'[[:space:]]' +private_key_pattern='-----BEGIN [A-Z0-9 ]*PRIV'"ATE KEY-----" +token_pattern='gh[pousr]_[A-Za-z0-9_]{20,}|AKIA[0-9A-Z]{16}' +fine_grained_token_pattern='git'"hub_pat_"'[A-Za-z0-9_]{20,}' +lfs_pointer_pattern='version https://git-'"lfs.github.com/spec/v1" +private_content_pattern="(${local_path_pattern}|${tunnel_pattern}|${private_key_pattern}|${token_pattern}|${fine_grained_token_pattern}|${lfs_pointer_pattern})" + +if LC_ALL=C grep -En -- "${private_content_pattern}" "${added_lines}"; then + die "possible workstation path, private endpoint, or credential in added content" +fi + +kernel_changed=false +for path in "${all_changed_paths[@]}"; do + case "${path}" in + *.c | *.h | *.S | *.rs | *.dts | *.dtsi | *.patch | \ + arch/*/configs/* | */Kconfig* | Kconfig* | */Makefile | Makefile | \ + Documentation/devicetree/bindings/*.yaml) + kernel_changed=true + break + ;; + esac +done + +if [[ "${kernel_changed}" == true ]]; then + [[ -x scripts/checkpatch.pl ]] || + die "scripts/checkpatch.pl is required for kernel-source changes" + kernel_pathspecs=( + ':(top,glob)**/*.c' + ':(top,glob)**/*.h' + ':(top,glob)**/*.S' + ':(top,glob)**/*.rs' + ':(top,glob)**/*.dts' + ':(top,glob)**/*.dtsi' + ':(top,glob)**/*.patch' + ':(top,glob)arch/*/configs/**' + ':(top,glob)**/Kconfig*' + ':(top,glob)**/Makefile' + ':(top,glob)Documentation/devicetree/bindings/**/*.yaml' + ) + # File changes are reviewed, but their generic MAINTAINERS reminder is + # not a style defect. --no-tree lets checkpatch run without a full + # kernel tree checkout (the workflow uses a sparse checkout). Only + # checkpatch ERROR-level findings fail the gate; WARNING and CHECK + # levels are reported for review but do not block, since upstream + # code may carry pre-existing style patterns. + checkpatch_output="$(git diff --no-ext-diff "${CHECKPATCH_RANGE}" -- "${kernel_pathspecs[@]}" | + scripts/checkpatch.pl --no-tree --strict --show-types --ignore FILE_PATH_CHANGES - || true)" + echo "${checkpatch_output}" + if echo "${checkpatch_output}" | grep -qE '^ERROR:'; then + # Report all ERROR-level findings, but only fail the gate for + # files in the SP11-authored delta; upstream-only files carry + # pre-existing style patterns and are not actionable here. + sp11_errors="$(echo "${checkpatch_output}" | + awk -v sp11="${sp11_touched_files}" ' + BEGIN { n = split(sp11, a, "\n") + for (i = 1; i <= n; i++) sp11set[a[i]] = 1 } + /^ERROR:/ { pending = $0; next } + /^[#0-9]+: FILE: / && pending != "" { + file = $0 + sub(/^[^:]*: FILE: /, "", file) + sub(/:.*$/, "", file) + if (file in sp11set) print pending " [" file "]" + pending = "" + }' )" + if [[ -n "${sp11_errors}" ]]; then + printf 'SP11 delta checkpatch errors:\n%s\n' "${sp11_errors}" >&2 + die "checkpatch.pl reported ERROR-level findings in the SP11 delta (see above)" + fi + fi +else + printf 'No kernel-source changes require checkpatch.pl.\n' +fi + +printf 'Surface Pro 11 integration checks passed for %s.\n' "$(git rev-parse HEAD)" diff --git a/.github/workflows/sp11-integration-checks.yml b/.github/workflows/sp11-integration-checks.yml new file mode 100644 index 00000000000000..8b24809c36bea7 --- /dev/null +++ b/.github/workflows/sp11-integration-checks.yml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only + +name: Surface Pro 11 integration checks + +on: + pull_request: + branches: + - sp11/integration-7.2.x + push: + branches: + - sp11/integration-7.2.x + workflow_dispatch: + +permissions: + contents: read + +concurrency: + group: sp11-integration-${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + +jobs: + validate: + name: Validate integration delta + runs-on: ubuntu-24.04 + timeout-minutes: 30 + + steps: + - name: Check out the complete history + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + # Bound history while retaining room for the integration branch to + # advance from the immutable base. The validator fails closed if the + # base ever falls outside this window. + fetch-depth: 256 + persist-credentials: false + sparse-checkout: | + .github + scripts/checkpatch.pl + sparse-checkout-cone-mode: false + + - name: Validate the Surface Pro 11 integration delta + run: .github/scripts/check-sp11-integration.sh diff --git a/.gitignore b/.gitignore index 9875120ea7bde0..111739999f097c 100644 --- a/.gitignore +++ b/.gitignore @@ -89,7 +89,7 @@ modules.order # # Debian directory (make deb-pkg) # -/debian/ +#/debian/ # # Snap directory (make snap-pkg) @@ -116,6 +116,7 @@ modules.order !.editorconfig !.get_maintainer.ignore !.gitattributes +!.github/ !.gitignore !.kunitconfig !.mailmap diff --git a/Documentation/ABI/testing/dev-g6ts-heat b/Documentation/ABI/testing/dev-g6ts-heat new file mode 100644 index 00000000000000..6e459694cb1c8e --- /dev/null +++ b/Documentation/ABI/testing/dev-g6ts-heat @@ -0,0 +1,55 @@ +What: /dev/g6ts-heat +Date: August 2026 +KernelVersion: 7.2 +Contact: linux-input@vger.kernel.org +Description: + Binary raw-frame stream for the Microsoft Surface G6 touch/pen + processor. HEAT reports 0x0b, 0x0c, 0x0d, and 0x1a plus optional + opaque sideband reports 0x07 and 0x6e are exported in transport + order before the touch-readiness filter is applied. Sideband + records are not cycle members or pen-presence notifications. + + Only one reader may open the misc character device at a time. A + blocking read waits for a complete record. O_NONBLOCK returns + -EAGAIN when empty. Every successful read returns exactly one + whole record; a buffer smaller than record_len returns -EMSGSIZE + without consuming it. poll(2) reports POLLIN while records are + queued and POLLHUP after device removal. + + The first 32 bytes are struct g6ts_heat_record_header from + , followed by content_len bytes copied exactly + from the HID-over-SPI content (the report ID is not repeated in the + payload). All multibyte fields are little-endian: + + ======= ===== ================================================== + Offset Size Meaning + ======= ===== ================================================== + 0 4 Magic 0x31483647 (ASCII bytes "G6H1") + 4 2 ABI version (1) + 6 2 Header length (32) + 8 4 Total record length + 12 4 Transport generation + 16 8 CLOCK_MONOTONIC timestamp in nanoseconds + 24 4 Enqueue sequence, including boundary records + 28 2 Content length (maximum 4349) + 30 1 HID report ID, or zero for a boundary record + 31 1 G6TS_HEAT_RECORD_F_* flags + ======= ===== ================================================== + + Generation starts at one. A panel reset, suspend, or transport + fault increments it, flushes queued frames, and enqueues a zero-data + boundary record. RESET, SUSPEND, or TRANSPORT_FAULT in that record + tells userspace to release pen state immediately. Queue overflow + drops the oldest record so retained records remain ordered and current. + Because overflow can drop the boundary record itself, readers must + also treat every generation change or sequence gap as a discontinuity, + release pen state immediately, and discard any partial measurement + cycle. + + G6TS_HEAT_IOC_GET_INFO returns the ABI/header sizes, maximum content + length, queue capacity, and supported flags in struct + g6ts_heat_info. G6TS_HEAT_IOC_GET_STATS returns the generation, + queue depth, enqueue/drop/flush counters, oversize drops, and the + four core HEAT report counts in struct g6ts_heat_stats. Both ioctl + structures begin with ABI version and structure size and reserve + zero-filled space for compatible extension. diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index e8ff36982d97bc..249a1a8c913abf 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5063,6 +5063,12 @@ Kernel parameters nomsi [MSI] If the PCI_MSI kernel config parameter is enabled, this kernel boot option can be used to disable the use of MSI interrupts system-wide. + clearmsi [X86] Clears MSI/MSI-X enable bits early in boot + time in order to avoid issues like adapters + screaming irqs and preventing boot progress. + Also, it enforces the PCI Local Bus spec + rule that those bits should be 0 in system reset + events (useful for kexec/kdump cases). noioapicquirk [APIC] Disable all boot interrupt quirks. Safety option to keep boot IRQs enabled. This should never be necessary. diff --git a/Documentation/cgroups/namespace.txt b/Documentation/cgroups/namespace.txt new file mode 100644 index 00000000000000..a5b80e8f295f93 --- /dev/null +++ b/Documentation/cgroups/namespace.txt @@ -0,0 +1,142 @@ + CGroup Namespaces + +CGroup Namespace provides a mechanism to virtualize the view of the +/proc//cgroup file. The CLONE_NEWCGROUP clone-flag can be used with +clone() and unshare() syscalls to create a new cgroup namespace. +The process running inside the cgroup namespace will have its /proc//cgroup +output restricted to cgroupns-root. cgroupns-root is the cgroup of the process +at the time of creation of the cgroup namespace. + +Prior to CGroup Namespace, the /proc//cgroup file used to show complete +path of the cgroup of a process. In a container setup (where a set of cgroups +and namespaces are intended to isolate processes), the /proc//cgroup file +may leak potential system level information to the isolated processes. + +For Example: + $ cat /proc/self/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/batchjobs/container_id1 + +The path '/batchjobs/container_id1' can generally be considered as system-data +and its desirable to not expose it to the isolated process. + +CGroup Namespaces can be used to restrict visibility of this path. +For Example: + # Before creating cgroup namespace + $ ls -l /proc/self/ns/cgroup + lrwxrwxrwx 1 root root 0 2014-07-15 10:37 /proc/self/ns/cgroup -> cgroup:[4026531835] + $ cat /proc/self/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/batchjobs/container_id1 + + # unshare(CLONE_NEWCGROUP) and exec /bin/bash + $ ~/unshare -c + [ns]$ ls -l /proc/self/ns/cgroup + lrwxrwxrwx 1 root root 0 2014-07-15 10:35 /proc/self/ns/cgroup -> cgroup:[4026532183] + # From within new cgroupns, process sees that its in the root cgroup + [ns]$ cat /proc/self/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/ + + # From global cgroupns: + $ cat /proc//cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/batchjobs/container_id1 + + # Unshare cgroupns along with userns and mountns + # Following calls unshare(CLONE_NEWCGROUP|CLONE_NEWUSER|CLONE_NEWNS), then + # sets up uid/gid map and execs /bin/bash + $ ~/unshare -c -u -m + # Originally, we were in /batchjobs/container_id1 cgroup. Mount our own cgroup + # hierarchy. + [ns]$ mount -t cgroup cgroup /tmp/cgroup + [ns]$ ls -l /tmp/cgroup + total 0 + -r--r--r-- 1 root root 0 2014-10-13 09:32 cgroup.controllers + -r--r--r-- 1 root root 0 2014-10-13 09:32 cgroup.populated + -rw-r--r-- 1 root root 0 2014-10-13 09:25 cgroup.procs + -rw-r--r-- 1 root root 0 2014-10-13 09:32 cgroup.subtree_control + +The cgroupns-root (/batchjobs/container_id1 in above example) becomes the +filesystem root for the namespace specific cgroupfs mount. + +The virtualization of /proc/self/cgroup file combined with restricting +the view of cgroup hierarchy by namespace-private cgroupfs mount +should provide a completely isolated cgroup view inside the container. + +In its current form, the cgroup namespaces patcheset provides following +behavior: + +(1) The 'cgroupns-root' for a cgroup namespace is the cgroup in which + the process calling unshare is running. + For ex. if a process in /batchjobs/container_id1 cgroup calls unshare, + cgroup /batchjobs/container_id1 becomes the cgroupns-root. + For the init_cgroup_ns, this is the real root ('/') cgroup + (identified in code as cgrp_dfl_root.cgrp). + +(2) The cgroupns-root cgroup does not change even if the namespace + creator process later moves to a different cgroup. + $ ~/unshare -c # unshare cgroupns in some cgroup + [ns]$ cat /proc/self/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/ + [ns]$ mkdir sub_cgrp_1 + [ns]$ echo 0 > sub_cgrp_1/cgroup.procs + [ns]$ cat /proc/self/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/sub_cgrp_1 + +(3) Each process gets its CGROUPNS specific view of /proc//cgroup +(a) Processes running inside the cgroup namespace will be able to see + cgroup paths (in /proc/self/cgroup) only inside their root cgroup + [ns]$ sleep 100000 & # From within unshared cgroupns + [1] 7353 + [ns]$ echo 7353 > sub_cgrp_1/cgroup.procs + [ns]$ cat /proc/7353/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/sub_cgrp_1 + +(b) From global cgroupns, the real cgroup path will be visible: + $ cat /proc/7353/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/batchjobs/container_id1/sub_cgrp_1 + +(c) From a sibling cgroupns (cgroupns root-ed at a different cgroup), cgroup + path relative to its own cgroupns-root will be shown: + # ns2's cgroupns-root is at '/batchjobs/container_id2' + [ns2]$ cat /proc/7353/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/../container_id2/sub_cgrp_1 + + Note that the relative path always starts with '/' to indicate that its + relative to the cgroupns-root of the caller. + +(4) Processes inside a cgroupns can move in-and-out of the cgroupns-root + (if they have proper access to external cgroups). + # From inside cgroupns (with cgroupns-root at /batchjobs/container_id1), and + # assuming that the global hierarchy is still accessible inside cgroupns: + $ cat /proc/7353/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/sub_cgrp_1 + $ echo 7353 > batchjobs/container_id2/cgroup.procs + $ cat /proc/7353/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/../container_id2 + + Note that this kind of setup is not encouraged. A task inside cgroupns + should only be exposed to its own cgroupns hierarchy. Otherwise it makes + the virtualization of /proc//cgroup less useful. + +(5) Setns to another cgroup namespace is allowed when: + (a) the process has CAP_SYS_ADMIN in its current userns + (b) the process has CAP_SYS_ADMIN in the target cgroupns' userns + No implicit cgroup changes happen with attaching to another cgroupns. It + is expected that the somone moves the attaching process under the target + cgroupns-root. + +(6) When some thread from a multi-threaded process unshares its + cgroup-namespace, the new cgroupns gets applied to the entire process (all + the threads). For the unified-hierarchy this is expected as it only allows + process-level containerization. For the legacy hierarchies this may be + unexpected. So all the threads in the process will have the same cgroup. + +(7) The cgroup namespace is alive as long as there is atleast 1 + process inside it. When the last process exits, the cgroup + namespace is destroyed. The cgroupns-root and the actual cgroups + remain though. + +(8) Namespace specific cgroup hierarchy can be mounted by a process running + inside cgroupns: + $ mount -t cgroup -o __DEVEL__sane_behavior cgroup $MOUNT_POINT + + This will mount the unified cgroup hierarchy with cgroupns-root as the + filesystem root. The process needs CAP_SYS_ADMIN in its userns and mntns. diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 50cc18a6ec5edd..d8b3d2c722fcc6 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1126,6 +1126,11 @@ properties: - qcom,sm8750-qrd - const: qcom,sm8750 + - items: + - enum: + - lenovo,ideapad-slim3 + - const: qcom,x126100 + - items: - enum: - qcom,x1e001de-devkit @@ -1140,6 +1145,12 @@ properties: - const: qcom,x1e78100 - const: qcom,x1e80100 + - items: + - const: microsoft,denali-lcd + - const: microsoft,denali + - const: qcom,x1p64100 + - const: qcom,x1e80100 + - items: - enum: - medion,sprchrgd14s1 @@ -1160,6 +1171,7 @@ properties: - dell,inspiron-14-plus-7441 - dell,latitude-7455 - dell,xps13-9345 + - hp,elitebook-6-g1q - hp,elitebook-ultra-g1q - hp,omnibook-x14 - lenovo,ideacentre-mini-01q8x10 @@ -1170,6 +1182,12 @@ properties: - qcom,x1e80100-qcp - const: qcom,x1e80100 + - items: + - enum: + - acer,swift-sf14-11 + - asus,zenbook-a14-ux3407qa + - const: qcom,x1p64100 + - items: - enum: - qcom,hamoa-iot-evk @@ -1200,8 +1218,16 @@ properties: - items: - enum: + - acer,swift-sf14-11 + - const: qcom,x1p64100 + - const: qcom,x1e80100 + + - items: + - enum: + - acer,swift-go14-01 - asus,vivobook-s15-x1p4 - hp,omnibook-x14-fe1 + - lenovo,ideapad-5 - lenovo,thinkbook-16 - qcom,x1p42100-crd - const: qcom,x1p42100 diff --git a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml index 1bbe0da3997c3b..518cd04f79dbe3 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml @@ -21,6 +21,8 @@ properties: - enum: # Samsung 13" 3K (2880×1920 pixels) eDP AMOLED panel - samsung,atna30dw01 + # Samsung 14" WUXGA (1920×1200 pixels) eDP AMOLED panel + - samsung,atna40ct01 # Samsung 14" FHD+ (1920x1200 pixels) eDP AMOLED panel - samsung,atna40ct06 # Samsung 14" WQXGA+ (2880x1800 pixels) eDP AMOLED panel diff --git a/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml new file mode 100644 index 00000000000000..30dc6dcd8c9f03 --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/dell,xps13-9345-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dell XPS 13 9345 Embedded Controller + +maintainers: + - Aleksandrs Vinarskis + +description: + The Dell XPS 13 9345 has an Embedded Controller (EC) which handles thermal and power + management. It is communicating with SoC over multiple i2c busses. Particular driver + is for EC subsystem that handles fan speed control, thermal shutdown, peripherals + supply including trackpad, touch-row, display. + +properties: + compatible: + const: dell,xps13-9345-ec + + reg: + const: 0x3b + + interrupts: + maxItems: 1 + + io-channels: + description: + ADC channels connected to the 7 onboard thermistors on PMK8550. + EC requires frequent thermal readings of these channels to perform + automated fan speed control. + items: + - description: ADC channel for sys_therm0 + - description: ADC channel for sys_therm1 + - description: ADC channel for sys_therm2 + - description: ADC channel for sys_therm3 + - description: ADC channel for sys_therm4 + - description: ADC channel for sys_therm5 + - description: ADC channel for sys_therm6 + + io-channel-names: + items: + - const: sys_therm0 + - const: sys_therm1 + - const: sys_therm2 + - const: sys_therm3 + - const: sys_therm4 + - const: sys_therm5 + - const: sys_therm6 + +required: + - compatible + - reg + - interrupts + - io-channels + - io-channel-names + +additionalProperties: false + +examples: + - |+ + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@3b { + compatible = "dell,xps13-9345-ec"; + reg = <0x3b>; + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_LOW>; + + io-channels = <&pmk8550_vadc PM8350_ADC7_GPIO3_100K_PU(1)>, + <&pmk8550_vadc PM8350_ADC7_GPIO4_100K_PU(1)>, + <&pmk8550_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>, + <&pmk8550_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>, + <&pmk8550_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>, + <&pmk8550_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>, + <&pmk8550_vadc PM8350_ADC7_AMUX_THM5_100K_PU(1)>; + io-channel-names = "sys_therm0", "sys_therm1", "sys_therm2", + "sys_therm3", "sys_therm4", "sys_therm5", + "sys_therm6"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-slim7x-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-slim7x-ec.yaml new file mode 100644 index 00000000000000..32f8a0b5d6673c --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-slim7x-ec.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/platform/lenovo,yoga-slim7x-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lenovo Yoga Slim 7x Embedded Controller. + +maintainers: + - Maya Matuszczyk + +description: + The Lenovo Yoga Slim 7x has an EC which handles some minor functions, like + power LED or some special keys on the keyboard. This bindings describes + how it is connected + +properties: + compatible: + const: lenovo,yoga-slim7x-ec + + reg: + const: 0x76 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - |+ + #include + i2c5 { + clock-frequency = <400000>; + + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@76 { + compatible = "lenovo,yoga-slim7x-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/embedded-controller/qcom,x1e-it8987-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/qcom,x1e-it8987-ec.yaml new file mode 100644 index 00000000000000..4a4f6eb6307268 --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/qcom,x1e-it8987-ec.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/platform/qcom,x1e-it8987-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Embedded Controller on IT8987 chip. + +maintainers: + - Maya Matuszczyk + +description: + Most x1e80100 laptops have an EC running on IT8987 MCU chip. The EC controls + minor functions, like fans, power LED, and on some laptops it also handles + keyboard hotkeys. + +properties: + compatible: + oneOf: + - const: qcom,x1e-it8987-ec + - items: + - const: lenovo,yoga-slim7x-ec + - const: qcom,x1e-it8987-ec + + reg: + const: 0x76 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@76 { + compatible = "lenovo,yoga-slim7x-ec", "qcom,x1e-it8987-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 25f62bacbc9195..55b4d566e12f8c 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -113,6 +113,14 @@ properties: Phandle to the memory region reserved for the shared memory bridge to TZ. maxItems: 1 + qcom,shm-bridge-vmid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + VMID to use as owner of shared memory bridge allocations for TZ. + QCOM_SCM_VMID_SELF_OWNER may be used to indicate that the allocations + should be self-owned rather than being assigned to a specific VMID. + Defaults to QCOM_SCM_VMID_HLOS if not specified. + qcom,sdi-enabled: description: Indicates that the SDI (Secure Debug Image) has been enabled by TZ diff --git a/Documentation/devicetree/bindings/hwmon/lenovo,thinkpad-t14s-fan-controller.yaml b/Documentation/devicetree/bindings/hwmon/lenovo,thinkpad-t14s-fan-controller.yaml new file mode 100644 index 00000000000000..112d949100f107 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/lenovo,thinkpad-t14s-fan-controller.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/lenovo,thinkpad-t14s-fan-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lenovo Thinkpad T14s Fan Controller + +maintainers: + - Sebastian Reichel + +description: + The Qualcomm Snapdragon-based Lenovo Thinkpad T14s has a custom Fan Controller, + which is not part of the Embedded Controller. + +properties: + compatible: + const: lenovo,thinkpad-t14s-fan-controller + + reg: + const: 0x36 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - |+ + i2c { + #address-cells = <1>; + #size-cells = <0>; + + fan-controller@36 { + compatible = "lenovo,thinkpad-t14s-fan-controller"; + reg = <0x36>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/input/hid-over-spi.yaml b/Documentation/devicetree/bindings/input/hid-over-spi.yaml new file mode 100644 index 00000000000000..27cf311e0aab05 --- /dev/null +++ b/Documentation/devicetree/bindings/input/hid-over-spi.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/hid-over-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HID over SPI Devices + +maintainers: + - Benjamin Tissoires + - Jiri Kosina + - Jingyuan Liang + +description: |+ + HID over SPI provides support for various Human Interface Devices over the + SPI bus. These devices can be for example touchpads, keyboards, touch screens + or sensors. + + The specification has been written by Microsoft and is currently available + here: https://www.microsoft.com/en-us/download/details.aspx?id=103325 + + The Microsoft HID over SPI specification explicitly dictates that SPI + opcodes and register addresses (such as input/output report addresses) + are not standardized. Instead, the specification requires the system + firmware (e.g., ACPI or Device Tree) to provide these board-specific + parameters to the OS. Therefore, these varying parameters must be + defined as properties in the Device Tree. + +allOf: + - $ref: /schemas/input/touchscreen/touchscreen.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + items: + - enum: + - microsoft,g6-touch-digitizer + - const: hid-over-spi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + description: + GPIO specifier for the digitizer's reset pin (active low). The line must + be flagged with GPIO_ACTIVE_LOW. + + vdd-supply: + description: + Regulator for the VDD supply voltage. + + input-report-header-address: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0xffffff + description: + A value to be included in the Read Approval packet, listing an address of + the input report header to be put on the SPI bus. This address has 24 + bits. + + input-report-body-address: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0xffffff + description: + A value to be included in the Read Approval packet, listing an address of + the input report body to be put on the SPI bus. This address has 24 bits. + + output-report-address: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0xffffff + description: + A value to be included in the Output Report sent by the host, listing an + address where the output report on the SPI bus is to be written to. This + address has 24 bits. + + read-opcode: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + Value to be used in Read Approval packets. 1 byte. + + write-opcode: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + Value to be used in Write Approval packets. 1 byte. + +required: + - compatible + - interrupts + - reset-gpios + - vdd-supply + - input-report-header-address + - input-report-body-address + - output-report-address + - read-opcode + - write-opcode + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + hid@0 { + compatible = "microsoft,g6-touch-digitizer", "hid-over-spi"; + reg = <0x0>; + interrupts-extended = <&gpio 42 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + vdd-supply = <&pm8350c_l3>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_d6_int_bias>; + input-report-header-address = <0x1000>; + input-report-body-address = <0x1004>; + output-report-address = <0x2000>; + read-opcode = /bits/ 8 <0x0b>; + write-opcode = /bits/ 8 <0x02>; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml index 217b08c8cbbd35..3e012d71bbfff3 100644 --- a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml +++ b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml @@ -65,6 +65,11 @@ properties: flash-leds: true lens-focus: true + leds: true + led-names: true + + orientation: true + rotation: enum: [ 0, 180 ] diff --git a/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml new file mode 100644 index 00000000000000..352ad85ae50cd4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8350-venus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Venus video encode and decode accelerators + +maintainers: + - Konrad Dybcio + +description: | + The Venus Iris2 IP is a video encode and decode accelerator present + on Qualcomm platforms + +allOf: + - $ref: qcom,venus-common.yaml# + +properties: + compatible: + enum: + - qcom,sc8280xp-venus + - qcom,sm8350-venus + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + + resets: + maxItems: 1 + + reset-names: + items: + - const: core + + power-domains: + maxItems: 3 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mx + + interconnects: + maxItems: 3 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + - const: video-llcc + + operating-points-v2: true + opp-table: + type: object + + iommus: + maxItems: 1 + +required: + - compatible + - power-domain-names + - iommus + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + venus: video-codec@aa00000 { + compatible = "qcom,sm8350-venus"; + reg = <0x0aa00000 0x100000>; + interrupts = ; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names = "core"; + + power-domains = <&videocc MVS0C_GDSC>, + <&videocc MVS0_GDSC>, + <&rpmhpd SM8350_MX>; + power-domain-names = "venus", + "vcodec0", + "mx"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem", + "video-llcc"; + + operating-points-v2 = <&venus_opp_table>; + iommus = <&apps_smmu 0x2100 0x400>; + memory-region = <&pil_video_mem>; + + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml index 2d1662ef522b7b..d39de96d485582 100644 --- a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -17,20 +17,16 @@ properties: const: qcom,x1e80100-camss reg: - maxItems: 17 + maxItems: 13 reg-names: items: + - const: csid_wrapper - const: csid0 - const: csid1 - const: csid2 - const: csid_lite0 - const: csid_lite1 - - const: csid_wrapper - - const: csiphy0 - - const: csiphy1 - - const: csiphy2 - - const: csiphy4 - const: csitpg0 - const: csitpg1 - const: csitpg2 @@ -40,7 +36,7 @@ properties: - const: vfe_lite1 clocks: - maxItems: 29 + maxItems: 21 clock-names: items: @@ -55,14 +51,6 @@ properties: - const: cphy_rx_clk_src - const: csid - const: csid_csiphy_rx - - const: csiphy0 - - const: csiphy0_timer - - const: csiphy1 - - const: csiphy1_timer - - const: csiphy2 - - const: csiphy2_timer - - const: csiphy4 - - const: csiphy4_timer - const: gcc_axi_hf - const: gcc_axi_sf - const: vfe0 @@ -75,7 +63,7 @@ properties: - const: vfe_lite_csid interrupts: - maxItems: 13 + maxItems: 9 interrupt-names: items: @@ -84,15 +72,17 @@ properties: - const: csid2 - const: csid_lite0 - const: csid_lite1 - - const: csiphy0 - - const: csiphy1 - - const: csiphy2 - - const: csiphy4 - const: vfe0 - const: vfe1 - const: vfe_lite0 - const: vfe_lite1 + phys: + maxItems: 4 + + phy-names: + maxItems: 4 + interconnects: maxItems: 4 @@ -166,13 +156,13 @@ required: - clock-names - interrupts - interrupt-names + - phys + - phy-names - interconnects - interconnect-names - iommus - power-domains - power-domain-names - - vdd-csiphy-0p8-supply - - vdd-csiphy-1p2-supply - ports additionalProperties: false @@ -190,19 +180,15 @@ examples: #address-cells = <2>; #size-cells = <2>; - camss: isp@acb7000 { + camss: isp@acb6000 { compatible = "qcom,x1e80100-camss"; - reg = <0 0x0acb7000 0 0x2000>, + reg = <0 0x0acb6000 0 0x1000>, + <0 0x0acb7000 0 0x2000>, <0 0x0acb9000 0 0x2000>, <0 0x0acbb000 0 0x2000>, <0 0x0acc6000 0 0x1000>, <0 0x0acca000 0 0x1000>, - <0 0x0acb6000 0 0x1000>, - <0 0x0ace4000 0 0x1000>, - <0 0x0ace6000 0 0x1000>, - <0 0x0ace8000 0 0x1000>, - <0 0x0acec000 0 0x4000>, <0 0x0acf6000 0 0x1000>, <0 0x0acf7000 0 0x1000>, <0 0x0acf8000 0 0x1000>, @@ -211,16 +197,12 @@ examples: <0 0x0acc7000 0 0x2000>, <0 0x0accb000 0 0x2000>; - reg-names = "csid0", + reg-names = "csid_wrapper", + "csid0", "csid1", "csid2", "csid_lite0", "csid_lite1", - "csid_wrapper", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy4", "csitpg0", "csitpg1", "csitpg2", @@ -240,14 +222,6 @@ examples: <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&camcc CAM_CC_CSID_CLK>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, - <&camcc CAM_CC_CSIPHY0_CLK>, - <&camcc CAM_CC_CSI0PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY1_CLK>, - <&camcc CAM_CC_CSI1PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY2_CLK>, - <&camcc CAM_CC_CSI2PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY4_CLK>, - <&camcc CAM_CC_CSI4PHYTIMER_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, <&gcc GCC_CAMERA_SF_AXI_CLK>, <&camcc CAM_CC_IFE_0_CLK>, @@ -270,14 +244,6 @@ examples: "cphy_rx_clk_src", "csid", "csid_csiphy_rx", - "csiphy0", - "csiphy0_timer", - "csiphy1", - "csiphy1_timer", - "csiphy2", - "csiphy2_timer", - "csiphy4", - "csiphy4_timer", "gcc_axi_hf", "gcc_axi_sf", "vfe0", @@ -294,10 +260,6 @@ examples: , , , - , - , - , - , , , , @@ -308,15 +270,16 @@ examples: "csid2", "csid_lite0", "csid_lite1", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy4", "vfe0", "vfe1", "vfe_lite0", "vfe_lite1"; + phys = <&csiphy0>, <&csiphy1>, + <&csiphy2>, <&csiphy4>; + phy-names = "csiphy0", "csiphy1", + "csiphy2", "csiphy4"; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS @@ -348,9 +311,6 @@ examples: "ife1", "top"; - vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; - vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; - ports { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/net/wireless/ieee80211.yaml b/Documentation/devicetree/bindings/net/wireless/ieee80211.yaml index d89f7a3f88a71d..c10a4675640be9 100644 --- a/Documentation/devicetree/bindings/net/wireless/ieee80211.yaml +++ b/Documentation/devicetree/bindings/net/wireless/ieee80211.yaml @@ -29,6 +29,12 @@ properties: different 5 GHz subbands. Using them incorrectly could not work or decrease performance noticeably + disable-rfkill: + type: boolean + description: + Disable rfkill for some devices on which Wi-Fi would be entirely hard + blocked by default otherwise + additionalProperties: true examples: diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml index dc68dd59988fc7..ab07da1bd04a32 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml @@ -21,6 +21,8 @@ properties: reg: maxItems: 1 + disable-rfkill: true + firmware-name: maxItems: 1 description: @@ -54,6 +56,9 @@ properties: vddpcie1p8-supply: description: VDD_PCIE_1P8 supply regulator handle + disable-rfkill: + type: boolean + required: - compatible - reg @@ -69,6 +74,9 @@ required: additionalProperties: false +allOf: + - $ref: ieee80211.yaml# + examples: - | #include diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index b2c5c9a375a356..9eedf54bc2653e 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -59,6 +59,7 @@ properties: - qcom,sm8550-qmp-ufs-phy - qcom,sm8650-qmp-ufs-phy - qcom,sm8750-qmp-ufs-phy + - qcom,x1e80100-qmp-ufs-phy reg: maxItems: 1 @@ -128,6 +129,7 @@ allOf: - qcom,sm8550-qmp-ufs-phy - qcom,sm8650-qmp-ufs-phy - qcom,sm8750-qmp-ufs-phy + - qcom,x1e80100-qmp-ufs-phy then: properties: clocks: diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml index 4eff92343ce4f5..9e0f065a8c0b54 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -85,8 +85,28 @@ properties: description: See include/dt-bindings/phy/phy-qcom-qmp.h - mode-switch: true - orientation-switch: true + mode-switch: + description: + Flag the PHY as possible handler of USB Type-C altmode switching + type: boolean + + orientation-switch: + description: + Flag the PHY as possible handler of USB Type-C orientation switching + type: boolean + + qcom,combo-initial-mode: + description: + Describe the initial mode of the Combo PHY configuration. + The Combo PHY is a wrapper on top of a DP PHY and an USB3 PHY, + sharing the same SuperSpeed lanes with either DisplayPort over + the 4 lanes (dp), USB3 on a pair of lanes (usb3) or both + technologies in a 2+2 configuration (usb3+dp) as default. + default: usb3+dp + enum: + - usb3+dp + - usb3 + - dp ports: $ref: /schemas/graph.yaml#/properties/ports @@ -183,7 +203,6 @@ required: - "#phy-cells" allOf: - - $ref: /schemas/usb/usb-switch.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml new file mode 100644 index 00000000000000..e0976f01251645 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MIPI CSI2 Combo PHY + +maintainers: + - Bryan O'Donoghue + +description: + Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors + to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY + modes. + +properties: + compatible: + const: qcom,x1e80100-mipi-csi2-combo-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: csiphy + - const: csiphy_timer + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + vdda-0p8-supply: + description: Phandle to a 0.8V regulator supply to a PHY. + + vdda-1p2-supply: + description: Phandle to 1.2V regulator supply to a PHY. + + phy-type: + description: D-PHY or C-PHY mode + enum: [ 10, 11 ] + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdda-0p8-supply + - vdda-1p2-supply + - phy-type + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + csiphy0: csiphy@ace4000 { + compatible = "qcom,x1e80100-mipi-csi2-combo-phy"; + reg = <0x0ace4000 0x2000>; + #phy-cells = <0>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer"; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + + phy-type = ; + }; diff --git a/Documentation/devicetree/bindings/power/limits/qcom,spel.yaml b/Documentation/devicetree/bindings/power/limits/qcom,spel.yaml new file mode 100644 index 00000000000000..4c6e6cbfbfe400 --- /dev/null +++ b/Documentation/devicetree/bindings/power/limits/qcom,spel.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/limits/qcom,spel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SoC Power and Electrical Limits (SPEL) + +maintainers: + - Manaf Meethalavalappu Pallikunhi + +description: + The Qualcomm SPEL (SoC Power and Electrical Limits) provides hardware-based + power monitoring and limiting capabilities for various power domains in + Qualcomm SoCs. + +properties: + compatible: + const: qcom,glymur-spel + + reg: + maxItems: 3 + + reg-names: + items: + - const: config + - const: constraints + - const: nodes + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +examples: + - | + power-limits@ef3b000 { + compatible = "qcom,glymur-spel"; + reg = <0x0ef3b000 0x1000>, + <0x0ef3d000 0x1000>, + <0x0ef3e000 0x1000>; + reg-names = "config", + "constraints", + "nodes"; + }; diff --git a/Documentation/devicetree/bindings/regulator/dummy-consumer.yaml b/Documentation/devicetree/bindings/regulator/dummy-consumer.yaml new file mode 100644 index 00000000000000..efe8cccab08030 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/dummy-consumer.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/dummy-consumer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dummy regulator consumer + +maintainers: + - Aleksandrs Vinarskis + +description: | + Simple dummy regulator consumer node for devices which are not/cannot be + described in the devicetree, and do not need to be powered on during + suspend. A power-friendly alternative to leaving regulator without + consumer with 'regulator-always-on' property. + +properties: + compatible: + enum: + - regulator-dummy-consumer + + vdd-supply: + description: Regulator to control + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - vdd-supply + +additionalProperties: false + +examples: + - | + integrated-usb-camera { + compatible = "regulator-dummy-consumer"; + + vdd-supply = <&vdd>; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 2db4288a8a54a3..d495285139f1e5 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -48,9 +48,11 @@ properties: - qcom,milos-pmic-glink - qcom,sm8650-pmic-glink - qcom,sm8750-pmic-glink - - qcom,x1e80100-pmic-glink - const: qcom,sm8550-pmic-glink - const: qcom,pmic-glink + - items: + - const: qcom,x1e80100-pmic-glink + - const: qcom,pmic-glink '#address-cells': const: 1 diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml index dae440ecab5903..2c59501c33c511 100644 --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml @@ -30,6 +30,7 @@ properties: - qcom,sm8750-sndcard - const: qcom,sm8450-sndcard - enum: + - dell,xps13-9345-sndcard - fairphone,fp4-sndcard - fairphone,fp5-sndcard - qcom,apq8096-sndcard diff --git a/Documentation/devicetree/bindings/sound/qcom,wsa8840.yaml b/Documentation/devicetree/bindings/sound/qcom,wsa8840.yaml index 866c5e780fb0aa..0f1efbd568e6f3 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wsa8840.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wsa8840.yaml @@ -40,8 +40,32 @@ properties: minItems: 6 maxItems: 6 + qcom,enable-cps: + type: boolean + description: Enable the dedicated CPS SoundWire source DAI on data port 6. + + qcom,cps-offset1: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Slave-only SoundWire DP6 OffsetCtrl1 override for CPS. This does not + change the physical master-port schedule selected by qcom,port-mapping. + + qcom,visense-channel-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 255 + description: | + Native WSA data-port-5 channel-enable mask for the VISENSE protection + sidechain. If absent, the codec default is used. + '#sound-dai-cells': - const: 0 + enum: [0, 1] + description: | + Zero selects the legacy single speaker-playback DAI. With one cell, + DAI 0 is speaker playback, DAI 1 is the render-coupled VISENSE + protection-feedback sidechain, and DAI 2 is the dedicated CPS feedback + sidechain when qcom,enable-cps is present. vdd-1p8-supply: true vdd-io-supply: true @@ -75,7 +99,7 @@ examples: pinctrl-names = "default"; pinctrl-0 = <&spkr_2_sd_n_active>; powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3g_1p2>; diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 516bb61a46241f..fc861020a0ea76 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -15,15 +15,7 @@ select: properties: compatible: contains: - enum: - - qcom,msm8994-ufshc - - qcom,msm8996-ufshc - - qcom,qcs615-ufshc - - qcom,sdm845-ufshc - - qcom,sm6115-ufshc - - qcom,sm6125-ufshc - - qcom,sm6350-ufshc - - qcom,sm8150-ufshc + const: qcom,ufshc required: - compatible @@ -33,15 +25,62 @@ properties: - enum: - qcom,msm8994-ufshc - qcom,msm8996-ufshc + - qcom,msm8998-ufshc - qcom,qcs615-ufshc + - qcom,qcs8300-ufshc + - qcom,sa8775p-ufshc + - qcom,sc7180-ufshc + - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc + - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6115-ufshc - qcom,sm6125-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc + - qcom,sm8250-ufshc + - qcom,sm8350-ufshc + - qcom,sm8450-ufshc + - qcom,sm8550-ufshc + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc + - qcom,x1e80100-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 + clocks: + minItems: 7 + maxItems: 9 + + clock-names: + minItems: 7 + maxItems: 9 + + dma-coherent: true + + interconnects: + minItems: 2 + maxItems: 2 + + interconnect-names: + items: + - const: ufs-ddr + - const: cpu-ufs + + iommus: + minItems: 1 + maxItems: 2 + + phys: + maxItems: 1 + + phy-names: + items: + - const: ufsphy + + power-domains: + maxItems: 1 + qcom,ice: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the Inline Crypto Engine node @@ -55,12 +94,94 @@ properties: - const: std - const: ice + required-opps: + maxItems: 1 + + resets: + maxItems: 1 + + '#reset-cells': + const: 1 + + reset-names: + items: + - const: rst + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the RESET pin of the UFS memory device. + required: - compatible - reg allOf: - - $ref: qcom,ufs-common.yaml + - $ref: ufs-common.yaml + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-ufshc + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + reg: + maxItems: 1 + reg-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-ufshc + - qcom,qcs8300-ufshc + - qcom,sa8775p-ufshc + - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc + - qcom,sc8280xp-ufshc + - qcom,sm8250-ufshc + - qcom,sm8350-ufshc + - qcom,sm8450-ufshc + - qcom,sm8550-ufshc + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc + - qcom,x1e80100-ufshc + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + - const: rx_lane1_sync_clk + reg: + minItems: 1 + maxItems: 1 + reg-names: + maxItems: 1 - if: properties: @@ -175,10 +296,10 @@ unevaluatedProperties: false examples: - | - #include + #include #include #include - #include + #include #include soc { @@ -186,12 +307,9 @@ examples: #size-cells = <2>; ufs@1d84000 { - compatible = "qcom,sm8150-ufshc", "qcom,ufshc", + compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0x0 0x01d84000 0x0 0x2500>, - <0x0 0x01d90000 0x0 0x8000>; - reg-names = "std", "ice"; - + reg = <0 0x01d84000 0 0x3000>; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -207,17 +325,11 @@ examples: vccq-max-microamp = <1200000>; power-domains = <&gcc UFS_PHY_GDSC>; - iommus = <&apps_smmu 0x300 0>; + iommus = <&apps_smmu 0xe0 0x0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; - clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", @@ -225,16 +337,23 @@ examples: "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; - freq-table-hz = <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, + "rx_lane1_sync_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = <75000000 300000000>, <0 0>, <0 0>, + <75000000 300000000>, + <75000000 300000000>, <0 0>, <0 0>, - <0 300000000>; + <0 0>; + qcom,ice = <&ice>; }; }; diff --git a/Documentation/devicetree/bindings/usb/parade,ps8830.yaml b/Documentation/devicetree/bindings/usb/parade,ps8830.yaml index eaeab1c01a594e..44242907461eb0 100644 --- a/Documentation/devicetree/bindings/usb/parade,ps8830.yaml +++ b/Documentation/devicetree/bindings/usb/parade,ps8830.yaml @@ -66,6 +66,12 @@ properties: Sideband Use (SBU) AUX lines endpoint to the Type-C connector for the purpose of handling altmode muxing and orientation switching. + parade,disable-usb4: + type: boolean + description: + When present, the retimer rejects USB4 mode (returns -EOPNOTSUPP). + This forces the Type-C stack to fall back to USB3 + DP Alternate Mode. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml index 6c0b8b6538246a..d12f6ae81ab88d 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml @@ -212,6 +212,16 @@ properties: When set, run the SOF/ITP counter based on ref_clk. type: boolean + snps,reinit-phy-on-resume: + description: + When set, the DWC3 will re-initialize the USB2 PHYs during the + host-mode fast resume path (device_may_wakeup). Some platforms + cut PHY power during deep sleep even when USB wake is enabled, + and the standard PHY runtime PM resume is insufficient to restore + the PHY register state. This quirk forces a full phy_exit() + + phy_init() cycle on each USB2 PHY. + type: boolean + snps,resume-hs-terminations: description: Fix the issue of HS terminations CRC error on resume by enabling this diff --git a/Documentation/hid/hid-transport.rst b/Documentation/hid/hid-transport.rst index 6f1692da296cf2..2008cf432af128 100644 --- a/Documentation/hid/hid-transport.rst +++ b/Documentation/hid/hid-transport.rst @@ -327,8 +327,8 @@ The available HID callbacks are: Send raw output report via intr channel. Used by some HID device drivers which require high throughput for outgoing requests on the intr channel. This - must not cause SET_REPORT calls! This must be implemented as asynchronous - output report on the intr channel! + must not cause SET_REPORT calls! This call might be asynchronous, so the + caller should not expect an immediate response! :: diff --git a/Kbuild b/Kbuild index a6a0192dea08a1..d06de1ef63ac0d 100644 --- a/Kbuild +++ b/Kbuild @@ -115,3 +115,4 @@ obj-$(CONFIG_NET) += net/ obj-y += virt/ obj-y += $(ARCH_DRIVERS) obj-$(CONFIG_DRM_HEADER_TEST) += include/ +obj-y += ubuntu/ diff --git a/Kconfig b/Kconfig index 307e581144de32..ab71a1f87e9bb0 100644 --- a/Kconfig +++ b/Kconfig @@ -19,6 +19,8 @@ source "net/Kconfig" source "drivers/Kconfig" +source "ubuntu/Kconfig" + source "fs/Kconfig" source "security/Kconfig" diff --git a/MAINTAINERS b/MAINTAINERS index 8014b9f8253edf..70fc03bf3d367d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -200,6 +200,18 @@ M: Linus Walleij F: Documentation/devicetree/bindings/power/supply/*ab8500* F: drivers/power/supply/*ab8500* +AAEON DEVICE DRIVER WITH WMI INTERFACE +M: Edward Lin +M: Kunyang Fan +M: Frank Hsieh +M: Jacob Wu +S: Supported +F: drivers/gpio/gpio-aaeon.c +F: drivers/hwmon/hwmon-aaeon.c +F: drivers/leds/leds-aaeon.c +F: drivers/mfd/mfd-aaeon.c +F: drivers/watchdog/wdt_aaeon.c + ABI/API L: linux-api@vger.kernel.org F: include/linux/syscalls.h @@ -7291,6 +7303,12 @@ S: Maintained F: Documentation/ABI/testing/sysfs-class-firmware-attributes F: drivers/platform/x86/dell/dell-wmi-sysman/ +DELL XPS EMBEDDED CONTROLLER DRIVER +M: Aleksandrs Vinarskis +S: Maintained +F: Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml +F: drivers/platform/arm64/dell-xps-ec.c + DELTA AHE-50DC FAN CONTROL MODULE DRIVER M: Zev Weiss L: linux-hwmon@vger.kernel.org @@ -14691,6 +14709,12 @@ L: platform-driver-x86@vger.kernel.org S: Maintained F: drivers/platform/x86/lenovo/wmi-hotkey-utilities.c +LENOVO YOGA SLIM 7X EC DRIVER +M: Maya Matuszczyk +S: Maintained +F: Documentation/devicetree/bindings/platform/lenovo,yoga-slim7x-ec.yaml +F: drivers/platform/arm64/lenovo-yoga-slim7x.c + LENOVO HID drivers M: Derek J. Clark M: Mark Pearson @@ -22298,6 +22322,17 @@ S: Maintained F: Documentation/devicetree/bindings/media/qcom,*-iris.yaml F: drivers/media/platform/qcom/iris/ +QUALCOMM MIPI CSI2 PHY DRIVER +M: Bryan O'Donoghue +L: linux-phy@lists.infradead.org +L: linux-media@vger.kernel.org +L: linux-arm-msm@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml +F: drivers/phy/qualcomm/phy-qcom-mipi-csi2*.c +F: drivers/phy/qualcomm/phy-qcom-mipi-csi2*.h +F: include/dt-bindings/phy/phy-qcom-mipi-csi2* + QUALCOMM NAND CONTROLLER DRIVER M: Manivannan Sadhasivam L: linux-mtd@lists.infradead.org @@ -22324,6 +22359,13 @@ S: Maintained F: Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml F: drivers/power/supply/qcom_smbx.c +QUALCOMM SPEL POWERCAP DRIVER +M: Manaf Meethalavalappu Pallikunhi +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/power/limits/qcom,spel.yaml +F: drivers/powercap/qcom_spel.c + QUALCOMM PPE DRIVER M: Luo Jie L: netdev@vger.kernel.org diff --git a/Makefile b/Makefile index ddcc6dca1ece82..a2a359f25e3a87 100644 --- a/Makefile +++ b/Makefile @@ -600,6 +600,9 @@ LINUXINCLUDE := \ -I$(objtree)/include \ $(USERINCLUDE) +# UBUNTU: Include our third party driver stuff too +LINUXINCLUDE += -I$(srctree)/ubuntu/include + KBUILD_AFLAGS := -D__ASSEMBLY__ -fno-PIE KBUILD_CFLAGS := @@ -901,6 +904,12 @@ $(KCONFIG_CONFIG): # # Do not use $(call cmd,...) here. That would suppress prompts from syncconfig, # so you cannot notice that Kconfig is waiting for the user input. +# ensure -fcf-protection is disabled when using retpoline as it is +# incompatible with -mindirect-branch=thunk-extern +ifdef CONFIG_RETPOLINE +KBUILD_CFLAGS += $(call cc-option,-fcf-protection=none,) +endif + %/config/auto.conf %/config/auto.conf.cmd %/generated/autoconf.h %/generated/rustc_cfg: $(KCONFIG_CONFIG) $(Q)$(kecho) " SYNC $@" $(Q)$(MAKE) -f $(srctree)/Makefile syncconfig @@ -1487,8 +1496,9 @@ export INSTALL_HDR_PATH = $(objtree)/usr quiet_cmd_headers_install = INSTALL $(INSTALL_HDR_PATH)/include cmd_headers_install = \ mkdir -p $(INSTALL_HDR_PATH); \ - rsync -mrl --include='*/' --include='*\.h' --exclude='*' \ - usr/include $(INSTALL_HDR_PATH) + find usr/include -type f -name '*.h' -print0 | \ + tar -czf - --null --no-recursion --no-wildcards-match-slash -T- | \ + tar -xzf - --strip-components=1 -C $(INSTALL_HDR_PATH) PHONY += headers_install headers_install: headers @@ -1505,6 +1515,7 @@ ifdef HEADER_ARCH else $(Q)$(MAKE) $(hdr-inst)=include/uapi $(Q)$(MAKE) $(hdr-inst)=arch/$(SRCARCH)/include/uapi + $(Q)$(MAKE) $(hdr-inst)=ubuntu/include dst=include oldheaders= endif ifdef CONFIG_HEADERS_INSTALL @@ -1735,7 +1746,7 @@ CLEAN_FILES += vmlinux.symvers modules-only.symvers \ # Directories & files removed with 'make mrproper' MRPROPER_FILES += include/config include/generated \ arch/$(SRCARCH)/include/generated .objdiff \ - debian snap tar-install PKGBUILD pacman \ + snap tar-install PKGBUILD pacman \ .config .config.old .version \ Module.symvers \ certs/signing_key.pem \ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b3afe0688919bd..7ee5dfeb4fc8b5 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1695,7 +1695,7 @@ config XEN # 64K | 29 | 16 | 13 | 13 | config ARCH_FORCE_MAX_ORDER int - default "13" if ARM64_64K_PAGES + default "13" if ARM64_64K_PAGES || (ARCH_THUNDER && ARM64_4K_PAGES) default "11" if ARM64_16K_PAGES default "10" help diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6f33c4e2f09c39..d92148427b851d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -18,10 +18,13 @@ dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb -hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo +hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2-pas.dtbo dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-el2.dtb -dtb-$(CONFIG_ARCH_QCOM) += hamoa-lenovo-ideacentre-mini-01q8x10.dtb + +hamoa-lenovo-ideacentre-mini-01q8x10-el2-dtbs := hamoa-lenovo-ideacentre-mini-01q8x10.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += hamoa-lenovo-ideacentre-mini-01q8x10.dtb hamoa-lenovo-ideacentre-mini-01q8x10-el2.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb @@ -159,10 +162,12 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk.dtb +purwa-iot-evk-el2-dtbs := purwa-iot-evk.dtb x1-el2-pas.dtbo +dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk-el2.dtb -purwa-iot-evk-el2-dtbs := purwa-iot-evk.dtb x1-el2.dtbo +purwa-lenovo-ideacentre-mini-01q8x10-el2-dtbs := purwa-lenovo-ideacentre-mini-01q8x10.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += purwa-lenovo-ideacentre-mini-01q8x10.dtb purwa-lenovo-ideacentre-mini-01q8x10-el2.dtb -dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb @@ -409,8 +414,18 @@ dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtb talos-evk-lvds-auo,g133han01-dtbs := \ talos-evk.dtb talos-evk-lvds-auo,g133han01.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-lvds-auo,g133han01.dtb + +dtb-$(CONFIG_ARCH_QCOM) += x1-el2.dtbo +DTC_FLAGS_x1-el2 := -Wno-avoid_default_addr_size + +x126100-lenovo-ideapad-slim3-el2-dtbs := x126100-lenovo-ideapad-slim3.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x126100-lenovo-ideapad-slim3.dtb x126100-lenovo-ideapad-slim3-el2.dtb x1e001de-devkit-el2-dtbs := x1e001de-devkit.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb x1e001de-devkit-el2.dtb +x1e001de-devkit-jg-el2-dtbs := x1e001de-devkit-jg.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit-jg.dtb x1e001de-devkit-jg-el2.dtb +x1e001de-devkit_pcie3_hdmi-el2-dtbs := x1e001de-devkit_pcie3_hdmi.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit_pcie3_hdmi.dtb x1e001de-devkit_pcie3_hdmi-el2.dtb x1e78100-lenovo-thinkpad-t14s-el2-dtbs := x1e78100-lenovo-thinkpad-t14s.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb x1e78100-lenovo-thinkpad-t14s-el2.dtb x1e78100-lenovo-thinkpad-t14s-oled-el2-dtbs := x1e78100-lenovo-thinkpad-t14s-oled.dtb x1-el2.dtbo @@ -443,6 +458,8 @@ x1e80100-microsoft-romulus15-el2-dtbs := x1e80100-microsoft-romulus15.dtb x1-el2 dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb x1e80100-microsoft-romulus15-el2.dtb x1e80100-qcp-el2-dtbs := x1e80100-qcp.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb x1e80100-qcp-el2.dtb +x1p42100-acer-swift-go14-01-el2-dtbs := x1p42100-acer-swift-go14-01.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-acer-swift-go14-01.dtb x1p42100-acer-swift-go14-01-el2.dtb x1p42100-asus-vivobook-s15-el2-dtbs := x1p42100-asus-vivobook-s15.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-vivobook-s15.dtb x1p42100-asus-vivobook-s15-el2.dtb x1p42100-asus-zenbook-a14-el2-dtbs := x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo @@ -451,9 +468,25 @@ x1p42100-asus-zenbook-a14-lcd-el2-dtbs := x1p42100-asus-zenbook-a14-lcd.dtb x1-e dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14-lcd.dtb x1p42100-asus-zenbook-a14-lcd-el2.dtb x1p42100-crd-el2-dtbs := x1p42100-crd.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb x1p42100-crd-el2.dtb +x1p42100-dell-latitude-5455-el2-dtbs := x1p42100-dell-latitude-5455.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-dell-latitude-5455.dtb x1p42100-dell-latitude-5455-el2.dtb +x1p42100-hp-elitebook-6-g1q-el2-dtbs := x1p42100-hp-elitebook-6-g1q.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-elitebook-6-g1q.dtb x1p42100-hp-elitebook-6-g1q-el2.dtb +x1p42100-hp-omnibook-5-el2-dtbs := x1p42100-hp-omnibook-5.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-omnibook-5.dtb x1p42100-hp-omnibook-5-el2.dtb x1p42100-hp-omnibook-x14-el2-dtbs := x1p42100-hp-omnibook-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omnibook-x14-el2.dtb +x1p42100-lenovo-ideapad-5-2in1-el2-dtbs := x1p42100-lenovo-ideapad-5-2in1.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-ideapad-5-2in1.dtb x1p42100-lenovo-ideapad-5-2in1-el2.dtb +x1p42100-lenovo-ideapad-slim5x-lcd-el2-dtbs := x1p42100-lenovo-ideapad-slim5x-lcd.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-ideapad-slim5x-lcd.dtb x1p42100-lenovo-ideapad-slim5x-lcd-el2.dtb +x1p42100-lenovo-ideapad-slim5x-oled-el2-dtbs := x1p42100-lenovo-ideapad-slim5x-oled.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-ideapad-slim5x-oled.dtb x1p42100-lenovo-ideapad-slim5x-oled-el2.dtb x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb +x1p42100-microsoft-sp12in-el2-dtbs := x1p42100-microsoft-sp12in.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-microsoft-sp12in.dtb x1p42100-microsoft-sp12in-el2.dtb +x1p64100-acer-swift-sf14-11-el2-dtbs := x1p64100-acer-swift-sf14-11.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p64100-acer-swift-sf14-11.dtb x1p64100-acer-swift-sf14-11-el2.dtb x1p64100-microsoft-denali-el2-dtbs := x1p64100-microsoft-denali.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index c98dfb3941fa36..76923cebe5594e 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -198,6 +198,22 @@ }; }; +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + embedded-controller@76 { + compatible = "qcom,glymur-crd-ec", "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; +}; + &mdss { status = "okay"; }; @@ -279,6 +295,12 @@ }; &tlmm { + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_bl_en: edp-bl-en-state { pins = "gpio18"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 129be417ac4245..4c3902c50e0c6c 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5045,6 +5045,16 @@ }; }; + power-limits@ef3b000 { + compatible = "qcom,glymur-spel"; + reg = <0x0 0x0ef3b000 0x0 0x1000>, + <0x0 0x0ef3d000 0x0 0x1000>, + <0x0 0x0ef3e000 0x0 0x1000>; + reg-names = "config", + "constraints", + "nodes"; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,glymur-tlmm"; reg = <0x0 0x0f100000 0x0 0xf00000>; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index c7ba4b353ddd28..5ec77c5912f8e6 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -762,6 +762,8 @@ orientation-switch; retimer-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -839,6 +841,16 @@ pinctrl-0 = <&eusb6_reset_n>; pinctrl-names = "default"; }; + + embedded-controller@76 { + compatible = "qcom,hamoa-iot-evk-ec", "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; }; &i2c7 { @@ -867,6 +879,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1341,6 +1355,12 @@ }; &tlmm { + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 9c5e77df005476..bc70fe5db96f5b 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -590,8 +590,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -611,8 +611,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -632,8 +632,8 @@ }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -670,15 +670,15 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts b/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts index bfb7cea56df964..81ccb0769164f0 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts @@ -13,7 +13,7 @@ / { model = "Lenovo IdeaCentre Mini 01Q8X10"; - compatible = "lenovo,ideacentre-mini-01q8x10", "qcom,x1e80100"; + compatible = "lenovo,ideacentre-mini-01q8x10", "lenovo,thinkpad-t14s", "qcom,x1e80100"; chassis-type = "desktop"; aliases { @@ -601,6 +601,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -666,11 +668,11 @@ }; }; -&iris { - firmware-name = "qcom/x1e80100/LENOVO/91B6/qcvss8380.mbn"; - - status = "okay"; -}; +//&iris { +// firmware-name = "qcom/x1e80100/LENOVO/91B6/qcvss8380.mbn"; +// +// status = "okay"; +//}; &gpu { status = "okay"; @@ -1101,8 +1103,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l1j>; + vdda-phy-supply = <&vreg_l1j>; + vdda-pll-supply = <&vreg_l2j>; status = "okay"; }; @@ -1112,8 +1114,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l2d>; + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1138,8 +1140,8 @@ }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l2d>; + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1186,15 +1188,15 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi index 6a31a0adf8be47..a5b347491f55d3 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2024, Linaro Limited */ +#include +#include #include #include #include @@ -270,6 +272,24 @@ #interrupt-cells = <2>; }; + pmk8550_adc_tm: adc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>, <0x9100>; + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sdam0", + "sdam1"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + #thermal-sensor-cells = <1>; + + channel@18e { + reg = ; + label = "VPH_PWR"; + }; + }; + pmk8550_pwm: pwm { compatible = "qcom,pmk8550-pwm"; diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 4ba751a65142ba..2cf6aa1ca4e958 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -6,11 +6,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -442,19 +444,19 @@ cluster_pd0: power-domain-cpu-cluster0 { #power-domain-cells = <0>; - domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; + domain-idle-states = <&cluster_cl4>; power-domains = <&system_pd>; }; cluster_pd1: power-domain-cpu-cluster1 { #power-domain-cells = <0>; - domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; + domain-idle-states = <&cluster_cl4>; power-domains = <&system_pd>; }; cluster_pd2: power-domain-cpu-cluster2 { #power-domain-cells = <0>; - domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; + domain-idle-states = <&cluster_cl4>; power-domains = <&system_pd>; }; @@ -4371,6 +4373,9 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = ; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -5550,6 +5555,346 @@ #power-domain-cells = <1>; }; + cci0: cci@ac15000 { + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac15000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac16000 { + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac16000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camss: isp@acb6000 { + compatible = "qcom,x1e80100-camss"; + + reg = <0 0x0acb6000 0 0x1000>, + <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0ac71000 0 0x4000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x1800 0x60>, + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x1900 0x00>, + <&apps_smmu 0x1980 0x20>, + <&apps_smmu 0x19a0 0x20>; + + phys = <&csiphy0>, <&csiphy1>, + <&csiphy2>, <&csiphy4>; + phy-names = "csiphy0", "csiphy1", + "csiphy2", "csiphy4"; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + csiphy0: csiphy@ace4000 { + compatible = "qcom,x1e80100-mipi-csi2-combo-phy"; + reg = <0 0x0ace4000 0 0x2000>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer"; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + csiphy1: csiphy@ace6000 { + compatible = "qcom,x1e80100-mipi-csi2-combo-phy"; + reg = <0 0x0ace6000 0 0x2000>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer"; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + csiphy2: csiphy@ace8000 { + compatible = "qcom,x1e80100-mipi-csi2-combo-phy"; + reg = <0 0x0ace8000 0 0x2000>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer"; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + csiphy4: csiphy@acec000 { + compatible = "qcom,x1e80100-mipi-csi2-combo-phy"; + reg = <0 0x0acec000 0 0x2000>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer"; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,x1e80100-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,x1e80100-mdss"; reg = <0 0x0ae00000 0 0x1000>; @@ -6137,6 +6482,78 @@ bias-disable; }; + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + drive-strength = <2>; + bias-pull-down; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio0", "gpio1"; diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index ad503beec1d3d8..9ce080b9ae8966 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -703,6 +703,8 @@ orientation-switch; retimer-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -760,6 +762,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -865,6 +869,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/purwa-lenovo-ideacentre-mini-01q8x10.dts b/arch/arm64/boot/dts/qcom/purwa-lenovo-ideacentre-mini-01q8x10.dts new file mode 100644 index 00000000000000..d2158d2acb32ee --- /dev/null +++ b/arch/arm64/boot/dts/qcom/purwa-lenovo-ideacentre-mini-01q8x10.dts @@ -0,0 +1,1199 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) Jens Glathe + */ + +/dts-v1/; + +#include +#include +#include + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Lenovo IdeaCentre Mini 01Q8X10"; + compatible = "lenovo,ideacentre-mini-01q8x10", "lenovo,thinkpad-t14s", "qcom,x1e80100"; + chassis-type = "desktop"; + + aliases { + serial0 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + mux-controls = <&us_euro_mux_ctrl>; + + vdd-buck-supply = <&vreg_l15b>; + vdd-rxtx-supply = <&vreg_l15b>; + vdd-io-supply = <&vreg_l15b>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + dp-connector { + compatible = "dp-connector"; + type = "full-size"; + + pinctrl-0 = <&usb1_dp_hot_plug_detect>; + pinctrl-names = "default"; + + port { + dp_port_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out_dp>; + }; + }; + }; + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&usb2_dp_hot_plug_detect>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_out>; + }; + }; + }; + + us_euro_mux_ctrl: mux-controller { + compatible = "gpio-mux"; + pinctrl-0 = <&us_euro_hs_sel>; + pinctrl-names = "default"; + mux-supply = <&vreg_l16b>; + #mux-control-cells = <0>; + mux-gpios = <&tlmm 68 GPIO_ACTIVE_HIGH>; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_port0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_port0_ss_in: endpoint { + remote-endpoint = <&usb0_retimer_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_port0_sbu_in: endpoint { + remote-endpoint = <&usb0_retimer_sbu_out>; + }; + }; + }; + }; + }; + + vreg_nvme1_3p3: regulator-nvme1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme2_3p3: regulator-nvme2-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME2_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme2_reg_en>; + pinctrl-names = "default"; + + startup-delay-us = <2000000>; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_v0p9: regulator-v0p9 { + compatible = "regulator-fixed"; + + regulator-name = "V0P9"; + regulator-min-microvolt = <906000>; + regulator-max-microvolt = <906000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_vdd1v8: regulator-vdd1v8 { + compatible = "regulator-fixed"; + + regulator-name = "VDD1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vreg_l15b>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_vdd33_rtmr: regulator-vdd33-rtmr { + compatible = "regulator-fixed"; + + regulator-name = "VDD33_RTMR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wifi_3v3>; + }; + + vreg_wifi_3v3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "WIFI_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + }; + + vreg_wifi_1v8: regulator-wifi-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "WIFI_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vreg_l15b>; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-IdeaCentre-Mini"; + audio-routing = "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wifi_1v8>; + vddrfa1p8-supply = <&vreg_wifi_1v8>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l2b: ldo2 { + regulator-name = "VREG_L2B"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b: ldo4 { + regulator-name = "VREG_L4B"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13b: ldo13 { + regulator-name = "VREG_L13B"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b: ldo15 { + regulator-name = "VREG_L15B"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l16b: ldo16 { + regulator-name = "VREG_L16B"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l3c: ldo3 { + regulator-name = "VREG_L3C"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vreg_l1d: ldo1 { + regulator-name = "VREG_L1D"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d: ldo2 { + regulator-name = "VREG_L2D"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d: ldo3 { + regulator-name = "VREG_L3D"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_l2e: ldo2 { + regulator-name = "VREG_L2E"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e: ldo3 { + regulator-name = "VREG_L3E"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vreg_l3i: ldo3 { + regulator-name = "VREG_L3I"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vreg_l1j: ldo1 { + regulator-name = "VREG_L1J"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j: ldo2 { + regulator-name = "VREG_L2J"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j: ldo3 { + regulator-name = "VREG_L3J"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8833", "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_v0p9>; + vdd33-supply = <&vreg_vdd33_rtmr>; + vdd33-cap-supply = <&vreg_vdd33_rtmr>; + vddar-supply = <&vreg_v0p9>; + vddat-supply = <&vreg_v0p9>; + vddio-supply = <&vreg_vdd1v8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&usb0_reset_n>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + parade,disable-usb4; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb0_retimer_out: endpoint { + remote-endpoint = <&pmic_glink_port0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + usb0_retimer_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + usb0_retimer_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_port0_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b>; + vdd1v8-supply = <&vreg_l4b>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + +}; + +//&iris { +// firmware-name = "qcom/x1p42100/LENOVO/91B6/qcvss8380_pa.mbn"; +// +// status = "okay"; +//}; + +&lpass_vamacro { + qcom,dmic-sample-rate = <2400000>; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/LENOVO/91B6/qcdxkmsucpurwa.mbn"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vreg_nvme2_3p3>; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; + + status = "okay"; +}; + +&pcie3_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i>; + vdda-pll-supply = <&vreg_l3e>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l3i>; + vdda-pll-supply = <&vreg_l3e>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme1_3p3>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d>; + vdda-pll-supply = <&vreg_l2j>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pmc8380_3_gpios { + nvme2_reg_en: nvme2-reg-en-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + input-disable; + output-enable; + drive-push-pull; + bias-disable; + qcom,drive-strength = ; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550_gpios { + usb0_reset_n: usb0-reset-n-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; + bias-disable; + input-disable; + output-enable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/LENOVO/91B6/qcadsp8380.mbn", + "qcom/x1p42100/LENOVO/91B6/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/LENOVO/91B6/qccdsp8380.mbn", + "qcom/x1p42100/LENOVO/91B6/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d>; + vdd3-supply = <&vreg_l2b>; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ + <76 4>, /* SPI19 (TZ Protected) */ + <238 1>; /* UFS Reset */ + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + us_euro_hs_sel: us-euro-hs-sel-state { + pins = "gpio68"; + function = "gpio"; + bias-pull-down; + drive-strength = <2>; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_dp_hot_plug_detect: ub1-dp-hot-plug-detect-state { + pins = "gpio124"; + function = "usb1_dp"; + bias-disable; + }; + + usb2_dp_hot_plug_detect: usb2-dp-hot-plug-detect-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie5_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_port0_hs_in>; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j>; + vdda12-supply = <&vreg_l2j>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l1j>; + vdda-pll-supply = <&vreg_l2j>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&usb0_retimer_in>; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss1_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&dp_port_in>; + }; + }; + }; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_in>; + }; + }; + }; +}; + +&usb_mp { + status = "okay"; + + phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>; + phy-names = "usb2-0", "usb3-0"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e>; + vdda12-supply = <&vreg_l3e>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-el2.dtso b/arch/arm64/boot/dts/qcom/sc7180-el2.dtso index 6e8da59597b657..ecb6327cb52224 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-el2.dtso +++ b/arch/arm64/boot/dts/qcom/sc7180-el2.dtso @@ -1,4 +1,5 @@ // SPDX-License-Identifier: BSD-3-Clause +#include /* * sc7180 specific modifications required to boot in EL2. @@ -12,6 +13,18 @@ status = "disabled"; }; +&remoteproc_adsp { + qcom,broken-reset; +}; + +&remoteproc_mpss { + /* Reset is implemented in TZ firmware, so no qcom,broken-reset here */ +}; + +&scm { + qcom,shm-bridge-vmid = ; +}; + /* Venus can be used in EL2 if booted similarly to ChromeOS devices. */ &venus { video-firmware { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index dcdeefd2872837..4a777dfd20a8f2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -490,18 +490,6 @@ status = "okay"; }; -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpi_dma2 { - status = "okay"; -}; - &gpu { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso b/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso index cff3735a12dde8..0d52641b87d37e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso +++ b/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso @@ -1,4 +1,5 @@ // SPDX-License-Identifier: BSD-3-Clause +#include /* * sc8280xp specific modifications required to boot in EL2. @@ -40,3 +41,29 @@ &pcie_smmu { status = "okay"; }; + +&remoteproc_adsp { + qcom,broken-reset; +}; + +&remoteproc_slpi { + qcom,broken-reset; +}; + +&remoteproc_nsp0 { + qcom,broken-reset; +}; + +&remoteproc_nsp1 { + qcom,broken-reset; +}; + +&scm { + qcom,shm-bridge-vmid = ; +}; + +&venus { + video-firmware { + iommus = <&apps_smmu 0x2a02 0x400>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index cd575e20d90aa2..b2941f8a0797b9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -581,18 +581,6 @@ status = "okay"; }; -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpi_dma2 { - status = "okay"; -}; - &gpu { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index abd9c5a67b9ffe..750a97257c3228 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -703,18 +703,6 @@ status = "okay"; }; -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpi_dma2 { - status = "okay"; -}; - &gpu { status = "okay"; }; @@ -733,6 +721,7 @@ &mdss0_dp0_out { data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; remote-endpoint = <&usb_0_qmpphy_dp_in>; }; @@ -742,6 +731,7 @@ &mdss0_dp1_out { data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; remote-endpoint = <&usb_1_qmpphy_dp_in>; }; @@ -1178,12 +1168,6 @@ status = "okay"; }; -&remoteproc_slpi { - firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcslpi8280.mbn"; - - status = "okay"; -}; - &rxmacro { status = "okay"; }; @@ -1334,6 +1318,8 @@ vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; max-speed = <3200000>; + + local-bd-address = [ 8c fd f0 00 5a ad ]; }; }; @@ -1361,7 +1347,6 @@ vdda-phy-supply = <&vreg_l9d>; vdda-pll-supply = <&vreg_l4d>; - mode-switch; orientation-switch; status = "okay"; @@ -1399,7 +1384,6 @@ vdda-phy-supply = <&vreg_l4b>; vdda-pll-supply = <&vreg_l3b>; - mode-switch; orientation-switch; status = "okay"; @@ -1474,6 +1458,11 @@ status = "okay"; }; +&venus { + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcvss8280.mbn"; + status = "okay"; +}; + &wsamacro { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index f2b4470d4407fb..7dbafa2e7f0919 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -443,18 +443,6 @@ status = "okay"; }; -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpi_dma2 { - status = "okay"; -}; - &gpu { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 125af356e24b96..3969c1fb41ce1d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -28,32 +28,6 @@ serial1 = &uart2; }; - wcd938x: audio-codec { - compatible = "qcom,wcd9380-codec"; - - pinctrl-0 = <&wcd_default>; - pinctrl-names = "default"; - - reset-gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; - - vdd-buck-supply = <&vreg_s10b>; - vdd-rxtx-supply = <&vreg_s10b>; - vdd-io-supply = <&vreg_s10b>; - vdd-mic-bias-supply = <&vreg_bob>; - - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - - #sound-dai-cells = <1>; - }; - dp3_connector: connector { compatible = "dp-connector"; label = "DP-3"; @@ -61,6 +35,8 @@ dp-pwr-supply = <&vreg_misc_3p3>; + //hpd-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + port { dp1_connector_in: endpoint { remote-endpoint = <&mdss0_dp2_out>; @@ -238,7 +214,7 @@ usb0-sbu-mux { compatible = "pericom,pi3usb102", "gpio-sbu-mux"; - enable-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + enable-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; select-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&usb0_sbu_default>; @@ -560,18 +536,6 @@ status = "okay"; }; -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpi_dma2 { - status = "okay"; -}; - &gpu { status = "okay"; }; @@ -585,32 +549,40 @@ }; &mdss0_dp0 { + sound-name-prefix = "DisplayPort0"; status = "okay"; }; &mdss0_dp0_out { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; + + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; remote-endpoint = <&usb_0_qmpphy_dp_in>; }; &mdss0_dp1 { + sound-name-prefix = "DisplayPort1"; status = "okay"; }; &mdss0_dp1_out { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; }; &mdss0_dp2 { + sound-name-prefix = "DisplayPort2"; compatible = "qcom,sc8280xp-dp"; - data-lanes = <0 1 2 3>; - status = "okay"; }; &mdss0_dp2_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp1_connector_in>; }; @@ -763,20 +735,11 @@ }; &pmk8280_rtc { - nvmem-cells = <&rtc_offset>; - nvmem-cell-names = "offset"; + qcom,uefi-rtc-info; status = "okay"; }; -&pmk8280_sdam_6 { - status = "okay"; - - rtc_offset: rtc-offset@bc { - reg = <0xbc 0x4>; - }; -}; - &pmk8280_vadc { channel@144 { reg = ; @@ -865,17 +828,17 @@ &sound { compatible = "qcom,sc8280xp-sndcard"; - model = "microsoft/blackrock"; + model = "SC8280XP-MICROSOFT-BLACKROCK"; - wcd-playback-dai-link { - link-name = "WCD Playback"; + dp0-dai-link { + link-name = "DP0 Playback"; - cpu { - sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + codec { + sound-dai = <&mdss0_dp0>; }; - codec { - sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; }; platform { @@ -883,15 +846,15 @@ }; }; - wcd-capture-dai-link { - link-name = "WCD Capture"; + dp1-dai-link { + link-name = "DP1 Playback"; - cpu { - sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + codec { + sound-dai = <&mdss0_dp1>; }; - codec { - sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>; + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; }; platform { @@ -899,67 +862,23 @@ }; }; - wsa-dai-link { - link-name = "WSA Playback"; - - cpu { - sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; - }; + dp2-dai-link { + link-name = "DP2 Playback"; codec { - sound-dai = <&swr0 0>, <&wsamacro 0>; - }; - - platform { - sound-dai = <&q6apm>; + sound-dai = <&mdss0_dp2>; }; - }; - - va-dai-link { - link-name = "VA Capture"; cpu { - sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; }; platform { sound-dai = <&q6apm>; }; - - codec { - sound-dai = <&vamacro 0>; - }; - }; -}; - -&swr0 { - status = "okay"; -}; - -&swr1 { - status = "okay"; - - wcd_rx: wcd9380-rx@0,4 { - compatible = "sdw20217010d00"; - reg = <0 4>; - qcom,rx-port-mapping = <1 2 3 4 5>; }; }; -&swr2 { - status = "okay"; - - wcd_tx: wcd9380-tx@0,3 { - compatible = "sdw20217010d00"; - reg = <0 3>; - qcom,tx-port-mapping = <1 1 2 3>; - }; -}; - -&txmacro { - status = "okay"; -}; - &uart2 { pinctrl-0 = <&uart2_default>; pinctrl-names = "default"; @@ -979,6 +898,8 @@ vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; max-speed = <3200000>; + + local-bd-address = [ 8d fd f0 00 5a ad ]; }; }; @@ -1003,8 +924,8 @@ }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l4d>; - vdda-pll-supply = <&vreg_l9d>; + vdda-phy-supply = <&vreg_l9d>; + vdda-pll-supply = <&vreg_l4d>; orientation-switch; @@ -1040,8 +961,8 @@ }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l3b>; - vdda-pll-supply = <&vreg_l4b>; + vdda-phy-supply = <&vreg_l4b>; + vdda-pll-supply = <&vreg_l3b>; orientation-switch; @@ -1083,18 +1004,8 @@ status = "okay"; }; -&vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic23_default>; - pinctrl-names = "default"; - - vdd-micb-supply = <&vreg_s10b>; - - qcom,dmic-sample-rate = <4800000>; - - status = "okay"; -}; - -&wsamacro { +&venus { + firmware-name = "qcom/sc8280xp/microsoft/blackrock/qcvss8280.mbn"; status = "okay"; }; @@ -1104,10 +1015,6 @@ /* PINCTRL */ -&lpass_tlmm { - status = "okay"; -}; - &pmc8280_1_gpios { misc_3p3_reg_en: misc-3p3-reg-en-state { pins = "gpio1"; @@ -1268,7 +1175,7 @@ usb0_sbu_default: usb0-sbu-state { oe-n-pins { - pins = "gpio101"; + pins = "gpio100"; function = "gpio"; bias-disable; drive-strength = <16>; @@ -1309,14 +1216,6 @@ output-low; }; - wcd_default: wcd-default-state { - reset-pins { - pins = "gpio106"; - function = "gpio"; - bias-disable; - }; - }; - wlan_en: wlan-en-state { pins = "gpio134"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index b0de9e262f299c..7fd7be7b305d7f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -11,7 +11,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -697,6 +699,11 @@ no-map; }; + pil_video_mem: pil_video_region@86700000 { + reg = <0 0x86700000 0 0x500000>; + no-map; + }; + pil_adsp_mem: adsp-region@86c00000 { reg = <0 0x86c00000 0 0x2000000>; no-map; @@ -2168,6 +2175,7 @@ <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; + iommu-map = <0 &pcie_smmu 0x60000 0x10000>; dma-coherent; linux,pci-domain = <6>; @@ -2281,6 +2289,7 @@ <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; + iommu-map = <0 &pcie_smmu 0x50000 0x10000>; dma-coherent; linux,pci-domain = <5>; @@ -2392,6 +2401,7 @@ <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; + iommu-map = <0 &pcie_smmu 0x40000 0x10000>; dma-coherent; linux,pci-domain = <4>; @@ -2506,6 +2516,7 @@ <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; + iommu-map = <0 &pcie_smmu 0x30000 0x10000>; dma-coherent; linux,pci-domain = <3>; @@ -2617,6 +2628,7 @@ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; + iommu-map = <0 &pcie_smmu 0x20000 0x10000>; dma-coherent; linux,pci-domain = <2>; @@ -3684,6 +3696,8 @@ #clock-cells = <1>; #phy-cells = <1>; + mode-switch; + status = "disabled"; ports { @@ -3799,6 +3813,8 @@ #clock-cells = <1>; #phy-cells = <1>; + mode-switch; + status = "disabled"; ports { @@ -4209,6 +4225,81 @@ }; }; + venus: video-codec@aa00000 { + compatible = "qcom,sm8350-venus"; + reg = <0 0x0aa00000 0 0x100000>; + interrupts = ; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core"; + power-domains = <&videocc MVS0C_GDSC>, + <&videocc MVS0_GDSC>, + <&rpmhpd SC8280XP_MX>; + power-domain-names = "venus", + "vcodec0", + "mx"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names = "core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem", + "video-llcc"; + + operating-points-v2 = <&venus_opp_table>; + iommus = <&apps_smmu 0x2e00 0x400>; + memory-region = <&pil_video_mem>; + + status = "disabled"; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-1098000000 { + opp-hz = /bits/ 64 <1098000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-1332000000 { + opp-hz = /bits/ 64 <1332000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + videocc: clock-controller@abf0000 { + compatible = "qcom,sc8280xp-videocc"; + reg = <0 0x0abf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + cci0: cci@ac4a000 { compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; reg = <0 0x0ac4a000 0 0x1000>; @@ -5665,10 +5756,13 @@ #iommu-cells = <1>; interrupts = , , + , ; interrupt-names = "eventq", "gerror", + "priq", "cmdq-sync"; + msi-parent = <&its 0x40000>; dma-coherent; status = "reserved"; /* Controlled by QHEE. */ }; diff --git a/arch/arm64/boot/dts/qcom/x1-acer-swift-14.dtsi b/arch/arm64/boot/dts/qcom/x1-acer-swift-14.dtsi new file mode 100644 index 00000000000000..c60ca872dbfa91 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-acer-swift-14.dtsi @@ -0,0 +1,1458 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* +* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +* Copyright (c) 2024, Linaro Limited +* Copyright (c) 2024, Victorien Alric - vickdu31 +*/ + +#include +#include +#include +#include +#include + +/ { + model = "Acer Swift AI"; + compatible = "acer,swift-ai", "qcom,x1e80100"; + chassis-type = "laptop"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-ACER-SWIFT-14"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr1_1p15_reg_en>; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr1_1p8_reg_en>; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr1_3p3_reg_en>; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@68 { + compatible = "hid-over-i2c"; + reg = <0x68>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + + //vdd-supply = <&vreg_misc_3p3>; + //vddl-supply = <&vreg_l12b_1p2>; + + //pinctrl-0 = <&tpad_default>; + //pinctrl-names = "default"; + }; + + /* ELAN06F1 or SYNA06F2 */ + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + clock-names = "xo"; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>; + + retimer-switch; + orientation-switch; + + parade,disable-usb4; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + clock-names = "xo"; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>; + + retimer-switch; + orientation-switch; + + parade,disable-usb4; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + /* ILIT2911 or GTCH1563 */ + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&i2c20 { + clock-frequency = <400000>; + + status = "okay"; + +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + backlight = <&backlight>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550_gpios { + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + bias-disable; + }; +}; + +&pm8550ve_9_gpios { + rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + bias-disable; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + input-disable; + output-enable; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; + +}; + +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + +&pmc8380_5_gpios { + rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + bias-disable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <72 2>, /* Secure EC I2C connection (?) */ + <238 1>; /* UFS Reset */ + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts0_default: ts0-default-state { + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + bt_en_default: bt-en-sleep { + pins = "gpio116"; + function = "gpio"; + output-low; + bias-disable; + qcom,drive-strength = <16>; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&uart14 { + status = "okay"; + bluetooth: bt_wcn7850 { + compatible = "qcom,wcn7850-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_default>; + enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + max-speed = <3200000>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; + + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; + + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_2 { + status = "okay"; + + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi index 48c4ad648354ea..8283a42970c00c 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi @@ -18,6 +18,32 @@ serial1 = &uart14; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&hall_int_n_default>; @@ -73,10 +99,15 @@ pmic-glink { compatible = "qcom,x1e80100-pmic-glink", - "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, <&tlmm 123 GPIO_ACTIVE_HIGH>; + nvmem-cells = <&charge_limit_en>, + <&charge_limit_end>, + <&charge_limit_delta>; + nvmem-cell-names = "charge_limit_en", + "charge_limit_end", + "charge_limit_delta"; #address-cells = <1>; #size-cells = <0>; @@ -404,6 +435,133 @@ }; }; }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-ASUS-Vivobook-S15"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; }; &apps_rsc { @@ -436,6 +594,13 @@ regulator-initial-mode = ; }; + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + vreg_l2b_3p0: ldo2 { regulator-name = "vreg_l2b_3p0"; regulator-min-microvolt = <3072000>; @@ -450,6 +615,42 @@ regulator-initial-mode = ; }; + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + vreg_l13b_3p0: ldo13 { regulator-name = "vreg_l13b_3p0"; regulator-min-microvolt = <3072000>; @@ -469,6 +670,14 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; }; }; @@ -481,6 +690,20 @@ vdd-l3-supply = <&vreg_s1f_0p7>; vdd-s4-supply = <&vph_pwr>; + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + vreg_l3c_0p8: ldo3 { regulator-name = "vreg_l3c_0p8"; regulator-min-microvolt = <912000>; @@ -576,6 +799,20 @@ vdd-s1-supply = <&vph_pwr>; vdd-s2-supply = <&vph_pwr>; + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + vreg_l3i_0p8: ldo3 { regulator-name = "vreg_l3i_0p8"; regulator-min-microvolt = <880000>; @@ -678,6 +915,8 @@ orientation-switch; retimer-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -798,6 +1037,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -829,11 +1070,31 @@ }; }; +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + &mdss { status = "okay"; }; &mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + status = "okay"; }; @@ -842,6 +1103,8 @@ }; &mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + status = "okay"; }; @@ -850,6 +1113,8 @@ }; &mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + status = "okay"; }; @@ -1036,6 +1301,59 @@ vdd3-supply = <&vreg_l14b_3p0>; }; +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ @@ -1177,6 +1495,14 @@ bias-pull-up; }; + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + wcn_bt_en: wcn-bt-en-state { pins = "gpio116"; function = "gpio"; @@ -1226,8 +1552,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1256,8 +1582,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1277,8 +1603,8 @@ }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1342,15 +1668,15 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index 66d566808f5836..f598b45a05c713 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -108,14 +109,11 @@ pinctrl-0 = <&cam_indicator_en>; pinctrl-names = "default"; - led-camera-indicator { - label = "white:camera-indicator"; + privacy_led: privacy-led { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; default-state = "off"; - /* Reuse as a panic indicator until we get a "camera on" trigger */ panic-indicator; }; }; @@ -227,6 +225,54 @@ "VA DMIC1", "VA MIC BIAS1", "TX SWR_INPUT1", "ADC2_OUTPUT"; + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + va-dai-link { link-name = "VA Capture"; @@ -546,6 +592,13 @@ regulator-initial-mode = ; }; + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + vreg_l8b_3p0: ldo8 { regulator-name = "vreg_l8b_3p0"; regulator-min-microvolt = <3072000>; @@ -796,6 +849,86 @@ regulator-initial-mode = ; }; }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; +}; + +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + csiphy4_ep: endpoint@4 { + reg = <4>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02c10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam_rgb_default>; + pinctrl-names = "default"; + + leds = <&privacy_led>; + led-names = "privacy"; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_2p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov02c10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&csiphy4_ep>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + phy-type = ; + + status = "okay"; }; &i2c0 { @@ -845,6 +978,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -945,6 +1080,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1019,6 +1156,8 @@ }; &mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + status = "okay"; }; @@ -1027,6 +1166,8 @@ }; &mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + status = "okay"; }; @@ -1035,6 +1176,8 @@ }; &mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + status = "okay"; }; @@ -1283,6 +1426,22 @@ bias-disable; }; + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; @@ -1454,8 +1613,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p9>; + vdda-phy-supply = <&vreg_l1j_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1484,8 +1643,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1505,8 +1664,8 @@ }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1551,15 +1710,15 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index a9c5c523575eec..7cd04f7da71caf 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -17,6 +18,7 @@ aliases { serial0 = &uart21; + serial1 = &uart14; }; wcd938x: audio-codec { @@ -74,7 +76,6 @@ pmic-glink { compatible = "qcom,x1e80100-pmic-glink", - "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; #address-cells = <1>; #size-cells = <0>; @@ -530,6 +531,48 @@ regulator-boot-on; }; + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; @@ -545,6 +588,65 @@ regulator-boot-on; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -897,12 +999,103 @@ regulator-initial-mode = ; }; }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1808000>; + regulator-initial-mode = ; + }; + + vreg_l4m_1p8: ldo4 { + regulator-name = "vreg_l4m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1808000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p9: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + }; }; &gpu { status = "okay"; }; +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + csiphy4_ep: endpoint@4 { + reg = <4>; + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&ov08x40_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov08x40"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam_rgb_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + avdd-supply = <&vreg_l7b_2p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov08x40_ep: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&csiphy4_ep>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + phy-type = ; + + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; @@ -967,6 +1160,8 @@ orientation-switch; retimer-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1024,6 +1219,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1074,6 +1271,16 @@ #phy-cells = <0>; }; + + embedded-controller@76 { + compatible = "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; }; &i2c7 { @@ -1102,6 +1309,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1266,6 +1475,23 @@ status = "okay"; }; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie5 { vddpe-3v3-supply = <&vreg_wwan>; @@ -1523,6 +1749,28 @@ <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; @@ -1711,6 +1959,20 @@ output-low; }; + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wwan_sw_en: wwan-sw-en-state { pins = "gpio221"; function = "gpio"; @@ -1719,6 +1981,23 @@ }; }; +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + &uart21 { compatible = "qcom,geni-debug-uart"; status = "okay"; @@ -1734,8 +2013,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1764,8 +2043,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1794,8 +2073,8 @@ }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1836,15 +2115,15 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index db291730130c7b..5c2f3461025c78 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "hamoa-pmics.dtsi" @@ -792,6 +793,66 @@ }; }; +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + camss_csiphy4_inep0: endpoint@0 { + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02e10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@10 { + compatible = "ovti,ov02e10"; + reg = <0x10>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_default>; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_2p8>; + dovdd-supply = <&vreg_cam_1p8>; + + port { + ov02e10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <360000000>; + remote-endpoint = <&camss_csiphy4_inep0>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; @@ -850,6 +911,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -945,6 +1008,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1568,8 +1633,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1598,8 +1663,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1637,8 +1702,8 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1651,8 +1716,8 @@ }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-el2-pas.dtso b/arch/arm64/boot/dts/qcom/x1-el2-pas.dtso new file mode 100644 index 00000000000000..9db91adbcc566a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-el2-pas.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * EL2 overlay variant for configurations where Linux manages remote + * processors via PAS (Peripheral Authentication Service). + */ + +/dts-v1/; +/plugin/; + +#include "x1-el2.dtso" + +&remoteproc_adsp { + iommus = <&apps_smmu 0x1000 0x80>; +}; + +&remoteproc_cdsp { + iommus = <&apps_smmu 0x0c00 0x0>; +}; diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso index ee006742d6f3b9..3b8f5ab16f2274 100644 --- a/arch/arm64/boot/dts/qcom/x1-el2.dtso +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -1,4 +1,5 @@ // SPDX-License-Identifier: BSD-3-Clause +#include /* * x1 specific modifications required to boot in EL2. @@ -7,6 +8,15 @@ /dts-v1/; /plugin/; + + +&soc { + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0 0 0 0 0x100 0>; + ranges = <0 0 0 0 0x100 0>; +}; + &apss_watchdog { status = "okay"; }; @@ -17,8 +27,13 @@ }; &iris { - /* TODO: Add video-firmware iommus to start IRIS from EL2 */ - status = "disabled"; + /* Use generic firmware in EL2 and enable it by default */ +// status = "okay"; +// firmware-name = "qcom/vpu/vpu30_p4.mbn"; + + video-firmware { + iommus = <&apps_smmu 0x1942 0x0>; + }; }; /* @@ -53,11 +68,13 @@ }; &remoteproc_adsp { - iommus = <&apps_smmu 0x1000 0x80>; + //iommus = <&apps_smmu 0x1000 0x80>; + qcom,broken-reset; }; &remoteproc_cdsp { - iommus = <&apps_smmu 0x0c00 0x0>; + //iommus = <&apps_smmu 0x0c00 0x0>; + qcom,broken-reset; }; /* @@ -67,3 +84,7 @@ &sbsa_watchdog { status = "disabled"; }; + +&scm { + qcom,shm-bridge-vmid = ; +}; diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi index 02708f23a86579..b96b699ee41b9c 100644 --- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi @@ -917,6 +917,8 @@ orientation-switch; retimer-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1466,8 +1468,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1496,8 +1498,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1533,8 +1535,8 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi index 7559557610ed40..67e0c7e3cf9672 100644 --- a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -20,8 +20,9 @@ gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&hall_int_n_default>; + pinctrl-0 = <&hall_int_n_default>, <&kypd_vol_up_n>, <&kypd_vol_down_n>; pinctrl-names = "default"; + autorepeat; switch-lid { gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; @@ -30,6 +31,20 @@ wakeup-source; wakeup-event-action = ; }; + + key-vol-up { + label = "volume_up"; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-vol-down { + label = "volume_down"; + gpios = <&pm8550_gpios 8 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; }; pmic-glink { @@ -312,13 +327,15 @@ audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", "SpkrRight IN", "WSA WSA_SPK2 OUT", "VA DMIC0", "vdd-micb", - "VA DMIC1", "vdd-micb"; + "VA DMIC1", "vdd-micb", + "TX DMIC0", "vdd-micb", + "TX DMIC1", "vdd-micb"; wsa-dai-link { link-name = "WSA Playback"; codec { - sound-dai = <&left_spkr>, <&right_spkr>, + sound-dai = <&left_spkr 0>, <&right_spkr 0>, <&swr0 0>, <&lpass_wsamacro 0>; }; @@ -331,6 +348,51 @@ }; }; + wsa-vi-dai-link { + link-name = "WSA VI Protection"; + + /* + * One two-channel Windows-equivalent feedback transport: + * amplifier VISENSE ports 10/11 -> WSA macro VI -> + * SoundWire DIN0 -> AudioReach WSA TX0. + */ + codec { + sound-dai = <&left_spkr 1>, <&right_spkr 1>, + <&swr0 9>, <&lpass_wsamacro 2>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-cps-dai-link { + link-name = "WSA CPS Protection"; + + /* + * Dedicated CPS sidechain: both WSA8845 DP6 sources share + * physical SoundWire master port 13. swr0 DAI 10 is only + * the independent ASoC/SoundWire stream handle; qcom,port-mapping + * below remains authoritative for the physical master ports. + */ + codec { + sound-dai = <&left_spkr 2>, <&right_spkr 2>, + <&swr0 10>, <&lpass_wsamacro 4>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_TX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + va-dai-link { link-name = "VA Capture"; @@ -346,6 +408,22 @@ sound-dai = <&q6apm>; }; }; + + tx-dai-link { + link-name = "TX Capture"; + + codec { + sound-dai = <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; wcn7850-pmu { @@ -720,10 +798,6 @@ status = "okay"; }; -&gpu_zap_shader { - firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; -}; - &i2c0 { clock-frequency = <100000>; @@ -759,6 +833,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -822,6 +898,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -959,6 +1037,8 @@ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + + disable-rfkill; }; }; @@ -995,6 +1075,22 @@ function = "normal"; power-source = <1>; /* 1.8V */ }; + + kypd_vol_up_n: kypd-vol-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-pull-up; + input-enable; + }; + + kypd_vol_down_n: kypd-vol-down-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-pull-up; + input-enable; + }; }; &pm8550ve_9_gpios { @@ -1035,20 +1131,6 @@ status = "okay"; }; -&remoteproc_adsp { - firmware-name = "qcom/x1e80100/microsoft/Denali/qcadsp8380.mbn", - "qcom/x1e80100/microsoft/Denali/adsp_dtb.mbn"; - - status = "okay"; -}; - -&remoteproc_cdsp { - firmware-name = "qcom/x1e80100/microsoft/Denali/qccdsp8380.mbn", - "qcom/x1e80100/microsoft/Denali/cdsp_dtb.mbn"; - - status = "okay"; -}; - &smb2360_0 { status = "okay"; }; @@ -1087,11 +1169,14 @@ compatible = "sdw20217020400"; reg = <0 0>; reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; sound-name-prefix = "SpkrLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l12b_1p2>; qcom,port-mapping = <1 2 3 7 10 13>; + qcom,visense-channel-mask = <3>; + qcom,enable-cps; + qcom,cps-offset1 = <0>; }; /* WSA8845, Right Speaker */ @@ -1099,11 +1184,14 @@ compatible = "sdw20217020400"; reg = <0 1>; reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l12b_1p2>; qcom,port-mapping = <4 5 6 7 11 13>; + qcom,visense-channel-mask = <3>; + qcom,enable-cps; + qcom,cps-offset1 = <25>; }; }; @@ -1226,6 +1314,7 @@ }; }; + &uart2 { status = "okay"; @@ -1268,14 +1357,15 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; &usb_1_ss0 { dr_mode = "host"; + snps,reinit-phy-on-resume; status = "okay"; }; @@ -1298,14 +1388,15 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; &usb_1_ss1 { dr_mode = "host"; + snps,reinit-phy-on-resume; status = "okay"; }; @@ -1317,3 +1408,71 @@ &usb_1_ss1_qmpphy_out { remote-endpoint = <&retimer_ss1_ss_in>; }; + +/* + * Disable cluster-level PSCI idle states to ensure reliable s2idle + * resume. The X1E80100 SoC's deeper cluster sleep (cluster_cl4, + * psci-suspend-param 0x01000044) can fail to resume on the Surface + * Pro 11, leaving the display or USB subsystem unresponsive after + * suspend. Override the cluster power domains to remove the deep + * cluster idle state, keeping only architectural WFI (cluster_c4, + * psci-suspend-param 0x00000004) at the CPU level. + */ +&cluster_pd0 { + domain-idle-states = <>; +}; + +&cluster_pd1 { + domain-idle-states = <>; +}; + +&cluster_pd2 { + domain-idle-states = <>; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&i2c10 { + status = "disabled"; +}; + +&tlmm { + g6ts_qspi_data23: g6ts-qspi-data23-state { + pins = "gpio49", "gpio50"; + function = "qup1_se2"; + + drive-strength = <6>; + bias-disable; + }; +}; + +&spi10 { + status = "okay"; + + qcom,biosref-qspi; + qcom,enable-gsi-dma; + + dmas = <&gpi_dma1 0 2 4>, + <&gpi_dma1 1 2 4>; + dma-names = "tx", "rx"; + + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_data_clk>, + <&qup_spi10_cs>, + <&g6ts_qspi_data23>; + + touchscreen@0 { + compatible = "microsoft,mshw0485"; + reg = <0>; + spi-max-frequency = <40000000>; + + interrupt-parent = <&tlmm>; + interrupts = <51 IRQ_TYPE_LEVEL_LOW>; + interrupt-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + + power-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/x126100-lenovo-ideapad-slim3.dts b/arch/arm64/boot/dts/qcom/x126100-lenovo-ideapad-slim3.dts new file mode 100644 index 00000000000000..c07734928289f8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x126100-lenovo-ideapad-slim3.dts @@ -0,0 +1,1680 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + * Copyright (c) 2025, Jens Glathe + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Lenovo IdeaPad Slim 3 15Q8X10"; + compatible = "lenovo,ideapad-slim3", "lenovo,thinkpad-t14s", "qcom,x126100", "qcom,x1p42100"; + chassis-type = "laptop"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + pinctrl-0 = <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + hdmi-bridge { + compatible = "realtek,rtd2171"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_pcie3_nvme: regulator-pcie3-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE3_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pcie3_nvme_reg_en>; + pinctrl-names = "default"; + + startup-delay-us = <2000000>; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "VCC3B_WAN_RCM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-Ideapad-3"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/LENOVO/83N3/qcdxkmsucpurwa.mbn"; +}; + +&i2c0 { +/* unknown yet */ + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + /* 3d PS883x */ +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + /* 1st PS883x */ +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb9_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb5_repeater: redriver@4b { + compatible = "nxp,ptn3222"; + reg = <0x4b>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; + +// embedded-controller@76 { +// compatible = "qcom,hamoa-crd-ec"; +// reg = <0x76>; +// +// interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; +// +// pinctrl-0 = <&ec_int_n_default>; +// pinctrl-names = "default"; +// }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + /* 2nd PS883x */ +}; + +&i2c9 { + clock-frequency = <400000>; + + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + status = "okay"; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; +}; + +&i2c19 { + clock-frequency = <400000>; + + pinctrl-0 = <&qup_i2c19_data_clk>; + pinctrl-names = "default"; + status = "okay"; + +// /* ELAN06FA */ +// touchpad@15 { +// compatible = "hid-over-i2c"; +// reg = <0x15>; +// +// hid-descr-addr = <0x1>; +// interrupts-extended = <&gpio67_irqmux 1>; +// +// vdd-supply = <&vreg_misc_3p3>; +// vddl-supply = <&vreg_l12b_1p2>; +// +// wakeup-source; +// }; +// +// /* CIRQ1080 or SYNA2BA6 */ +// touchpad@2c { +// compatible = "hid-over-i2c"; +// reg = <0x2c>; +// +// hid-descr-addr = <0x20>; +// interrupts-extended = <&gpio67_irqmux 1>; +// +// vdd-supply = <&vreg_misc_3p3>; +// vddl-supply = <&vreg_l12b_1p2>; +// +// wakeup-source; +// }; +// +// /* FTCS0038 */ +// touchpad@38 { +// compatible = "hid-over-i2c"; +// reg = <0x38>; +// +// hid-descr-addr = <0x1>; +// interrupts-extended = <&gpio67_irqmux 1>; +// +// vdd-supply = <&vreg_misc_3p3>; +// vddl-supply = <&vreg_l12b_1p2>; +// +// wakeup-source; +// }; + + /* GXTP5100 */ + touchpad@5d { + compatible = "hid-over-i2c"; + reg = <0x5d>; + + hid-descr-addr = <0x1>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + }; +}; + +//&iris { +// firmware-name = "qcom/x1p42100/LENOVO/83N3/qcvss8380.mbn"; +// status = "okay"; +//}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&lpass_wsamacro { + status = "okay"; + assigned-clocks = <&q6prmcc 0x42 0x01>; + assigned-clock-rates = <19200000>; + clock-output-names = "wsa-mclk"; + #clock-cells = <0>; +}; + +&lpass_wsa2macro { + status = "disabled"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + backlight = <&backlight>; + + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie3 { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_pcie3_nvme>; + + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + max-link-speed = <1>; + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l3j_0p8>; + + status = "okay"; +}; + +&pcie4 { + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + drive-push-pull; + input-disable; + output-enable; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; /* 1.8V */ + input-disable; + output-enable; + }; + pcie3_nvme_reg_en: pcie3-nvme-reg-en-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + input-disable; + output-enable; + drive-push-pull; + bias-disable; + qcom,drive-strength = ; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/LENOVO/83N3/qcadsp8380.mbn", + "qcom/x1p42100/LENOVO/83N3/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/LENOVO/83N3/qccdsp8380.mbn", + "qcom/x1p42100/LENOVO/83N3/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* TPM SPI */ + <72 2>; /* Secure EC I2C connection (?) */ + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + input-enable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie5_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + oe-n-pins { + pins = "gpio168"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio167"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_sw_en: wwan-sw-en-state { + pins = "gpio221"; + function = "gpio"; + drive-strength = <4>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; + + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&eusb9_repeater>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; + + dr_mode = "host"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + +// data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + /* No USB3 lanes connected */ + }; + }; +}; + +&usb_2 { + status = "okay"; + + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit-jg.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit-jg.dts new file mode 100644 index 00000000000000..297a84a7f70f50 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit-jg.dts @@ -0,0 +1,1865 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. X1E001DE Snapdragon Devkit for Windows (no WCN7850)"; + compatible = "qcom,x1e001de-devkit", "lenovo,thinkpad-t14s", "qcom,x1e001de", "qcom,x1e80100"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + +// lan { +// compatible = "regulator-dummy-consumer"; + +// vdd-supply = <&vreg_wcn_3p3>; +// }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + /* Back panel port closer to the RJ45 connector */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* Back panel port closer to the audio jack */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + + /* Front panel port */ + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss2_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E001DE-DEVKIT"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + thermal-zones { + soc-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU(1)>; + + trips { + soc-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + dc-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU(1)>; + + trips { + dc-critical { + temperature = <100000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + usb0-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM1_100K_PU(1)>; + + trips { + usb0-critical { + temperature = <100000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + usb2-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM2_100K_PU(1)>; + + trips { + usb2-critical { + temperature = <100000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + edp-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM3_100K_PU(1)>; + + trips { + edp-critical { + temperature = <100000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + usb1-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM5_100K_PU(1)>; + + trips { + usb1-critical { + temperature = <100000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&nvme_reg_en>; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "SDX_VPH_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcdxkmsuc8380.mbn"; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK5>; + + vdd-supply = <&vreg_rtmr2_1p15>; + vdd33-supply = <&vreg_rtmr2_3p3>; + vdd33-cap-supply = <&vreg_rtmr2_3p3>; + vddar-supply = <&vreg_rtmr2_1p15>; + vddat-supply = <&vreg_rtmr2_1p15>; + vddio-supply = <&vreg_rtmr2_1p8>; + + reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr2_default>; + pinctrl-names = "default"; + + parade,disable-usb4; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + parade,disable-usb4; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + parade,disable-usb4; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c13 { + clock-frequency = <400000>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1308"; + reg = <0x68>; + vcc-supply = <&vreg_l15b_1p8>; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <2400000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&pcie4 { + vddpe-3v3-supply = <&vreg_wcn_3p3>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie6a_default>; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8 V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8 V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8 V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8 V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmk8550_adc_tm { + channel@144 { + reg = ; + label = "SYS_THERM2"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + channel@145 { + reg = ; + label = "SYS_THERM3"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + channel@146 { + reg = ; + label = "SYS_THERM4"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + /* SYS_THERM5 is unused */ + channel@148 { + reg = ; + label = "SYS_THERM6"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + channel@14a { + reg = ; + label = "SYS_THERM0"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + channel@14b { + reg = ; + label = "SYS_THERM1"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; +}; + +&pmk8550_rtc { + /* DS1308 RTC is more useful since it is backed by battery */ + status = "disabled"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcadsp8380.mbn", + "qcom/x1e80100/Thundercomm/DEVKIT/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qccdsp8380.mbn", + "qcom/x1e80100/Thundercomm/DEVKIT/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer (SPK0 on pin header) */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter (SPK1 on pin header) */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer (SPK2 on pin header) */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter (SPK3 on pin header) */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>; /* SPI (TPM) */ + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie5_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_default: rtmr2-reset-n-active-state { + pins = "gpio185"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p15_reg_en: usb2-pwr-1p15-reg-en-state { + pins = "gpio189"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p8_reg_en: usb2-pwr-1p8-reg-en-state { + pins = "gpio126"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state { + pins = "gpio187"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_sw_en: wwan-sw-en-state { + pins = "gpio221"; + function = "gpio"; + drive-strength = <4>; + bias-disable; + }; +}; + +&uart21 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&retimer_ss2_ss_in>; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 2e38402e2c140d..58d310404aa853 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -6,6 +6,9 @@ /dts-v1/; #include +#include +#include +#include #include #include "hamoa.dtsi" @@ -13,10 +16,11 @@ / { model = "Qualcomm Technologies, Inc. X1E001DE Snapdragon Devkit for Windows"; - compatible = "qcom,x1e001de-devkit", "qcom,x1e001de", "qcom,x1e80100"; + compatible = "qcom,x1e001de-devkit", "lenovo,thinkpad-t14s", "qcom,x1e001de", "qcom,x1e80100"; aliases { serial0 = &uart21; + serial1 = &uart14; }; wcd938x: audio-codec { @@ -49,6 +53,18 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + hdmi-pwr-supply = <&hdmi_5v>; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + pmic-glink { compatible = "qcom,x1e80100-pmic-glink", "qcom,sm8550-pmic-glink", @@ -183,9 +199,17 @@ sound { compatible = "qcom,x1e80100-sndcard"; model = "X1E001DE-DEVKIT"; - audio-routing = "IN1_HPHL", "HPHL_OUT", + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", "TX SWR_INPUT1", "ADC2_OUTPUT"; wcd-playback-dai-link { @@ -219,6 +243,159 @@ sound-dai = <&q6apm>; }; }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + thermal-zones { + soc-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU(1)>; + + trips { + soc-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + dc-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU(1)>; + + trips { + dc-critical { + temperature = <100000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + usb0-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM1_100K_PU(1)>; + + trips { + usb0-critical { + temperature = <100000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + usb2-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM2_100K_PU(1)>; + + trips { + usb2-critical { + temperature = <100000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + edp-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM3_100K_PU(1)>; + + trips { + edp-critical { + temperature = <100000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + usb1-thermal { + thermal-sensors = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM5_100K_PU(1)>; + + trips { + usb1-critical { + temperature = <100000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_g_card: regulator-g-card-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "G_CARD_POWER_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&g_card_reg_en>; + pinctrl-names = "default"; + + vin-supply = <&vreg_wcn_3p3>; + + regulator-boot-on; + }; + + hdmi_5v: regulator-hdmi-5v { + compatible = "regulator-fixed"; + + regulator-name = "HDMI_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vreg_edp_3p3>; }; vreg_nvme: regulator-nvme { @@ -247,7 +424,7 @@ gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; enable-active-high; - pinctrl-0 = <&usb0_pwr_1p15_en>; + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; pinctrl-names = "default"; regulator-boot-on; @@ -295,7 +472,7 @@ gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; enable-active-high; - pinctrl-0 = <&rtmr1_1p15_reg_en>; + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; pinctrl-names = "default"; regulator-boot-on; @@ -311,7 +488,7 @@ gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; enable-active-high; - pinctrl-0 = <&rtmr1_1p8_reg_en>; + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; pinctrl-names = "default"; regulator-boot-on; @@ -327,7 +504,7 @@ gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; enable-active-high; - pinctrl-0 = <&rtmr1_3p3_reg_en>; + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; pinctrl-names = "default"; regulator-boot-on; @@ -343,7 +520,7 @@ gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>; enable-active-high; - pinctrl-0 = <&rtmr2_1p15_reg_en>; + pinctrl-0 = <&usb2_pwr_1p15_reg_en>; pinctrl-names = "default"; regulator-boot-on; @@ -359,7 +536,7 @@ gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>; enable-active-high; - pinctrl-0 = <&rtmr2_1p8_reg_en>; + pinctrl-0 = <&usb2_pwr_1p8_reg_en>; pinctrl-names = "default"; regulator-boot-on; @@ -375,7 +552,7 @@ gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; enable-active-high; - pinctrl-0 = <&rtmr2_3p3_reg_en>; + pinctrl-0 = <&usb2_pwr_3p3_reg_en>; pinctrl-names = "default"; regulator-boot-on; @@ -392,6 +569,48 @@ regulator-boot-on; }; + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; @@ -407,6 +626,65 @@ regulator-boot-on; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -795,6 +1073,8 @@ orientation-switch; retimer-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -852,6 +1132,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -943,6 +1225,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -974,6 +1258,43 @@ }; }; +&i2c13 { + clock-frequency = <400000>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1308"; + reg = <0x68>; + vcc-supply = <&vreg_l15b_1p8>; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <2400000>; +}; + &mdss { status = "okay"; }; @@ -1002,6 +1323,53 @@ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; +&mdss_dp3 { + status = "okay"; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + ports { + port@1 { + reg = <1>; + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&hdmi_con>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie3_port0 { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; + + vpcie3v3-supply = <&vreg_g_card>; + vpcie3v3aux-supply = <&vreg_g_card>; +}; + &pcie4 { pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -1019,6 +1387,20 @@ &pcie4_port0 { reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; }; &pcie5 { @@ -1063,6 +1445,11 @@ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; }; +&pm8010 { + /* Used for the CSI connectors, which are not modeled at the moment */ + status = "okay"; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; @@ -1083,8 +1470,19 @@ }; }; +&pmc8380_3_gpios { + g_card_reg_en: g-card-reg-en-state { + pins = "gpio6"; + function = "normal"; + power-source = <0>; + bias-disable; + input-disable; + output-enable; + }; +}; + &pmc8380_5_gpios { - usb0_pwr_1p15_en: usb0-pwr-1p15-en-state { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { pins = "gpio8"; function = "normal"; power-source = <1>; /* 1.8 V */ @@ -1105,6 +1503,57 @@ }; }; +&pmk8550_adc_tm { + channel@144 { + reg = ; + label = "SYS_THERM2"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + channel@145 { + reg = ; + label = "SYS_THERM3"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + channel@146 { + reg = ; + label = "SYS_THERM4"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + /* SYS_THERM5 is unused */ + channel@148 { + reg = ; + label = "SYS_THERM6"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + channel@14a { + reg = ; + label = "SYS_THERM0"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + channel@14b { + reg = ; + label = "SYS_THERM1"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; +}; + +&pmk8550_rtc { + /* DS1308 RTC is more useful since it is backed by battery */ + status = "disabled"; +}; + &qupv3_0 { status = "okay"; }; @@ -1171,6 +1620,37 @@ vdd3-supply = <&vreg_l8b_3p0>; }; +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer (SPK0 on pin header) */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter (SPK1 on pin header) */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + &swr1 { status = "okay"; @@ -1193,9 +1673,47 @@ }; }; +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer (SPK2 on pin header) */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter (SPK3 on pin header) */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + &tlmm { gpio-reserved-ranges = <44 4>; /* SPI (TPM) */ + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + eusb3_reset_n: eusb3-reset-n-state { pins = "gpio6"; function = "gpio"; @@ -1219,6 +1737,29 @@ bias-disable; }; + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; @@ -1302,42 +1843,42 @@ bias-disable; }; - rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { pins = "gpio188"; function = "gpio"; drive-strength = <2>; bias-disable; }; - rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { pins = "gpio175"; function = "gpio"; drive-strength = <2>; bias-disable; }; - rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { pins = "gpio186"; function = "gpio"; drive-strength = <2>; bias-disable; }; - rtmr2_1p15_reg_en: rtmr2-1p15-reg-en-state { + usb2_pwr_1p15_reg_en: usb2-pwr-1p15-reg-en-state { pins = "gpio189"; function = "gpio"; drive-strength = <2>; bias-disable; }; - rtmr2_1p8_reg_en: rtmr2-1p8-reg-en-state { + usb2_pwr_1p8_reg_en: usb2-pwr-1p8-reg-en-state { pins = "gpio126"; function = "gpio"; drive-strength = <2>; bias-disable; }; - rtmr2_3p3_reg_en: rtmr2-3p3-reg-en-state { + usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state { pins = "gpio187"; function = "gpio"; drive-strength = <2>; @@ -1359,6 +1900,20 @@ output-low; }; + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wwan_sw_en: wwan-sw-en-state { pins = "gpio221"; function = "gpio"; @@ -1367,6 +1922,23 @@ }; }; +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + &uart21 { compatible = "qcom,geni-debug-uart"; status = "okay"; @@ -1382,8 +1954,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1413,8 +1985,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1443,8 +2015,8 @@ }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1486,15 +2058,15 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit_pcie3_hdmi.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit_pcie3_hdmi.dts new file mode 100644 index 00000000000000..0adebabfe8b636 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit_pcie3_hdmi.dts @@ -0,0 +1,1697 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. X1E001DE Snapdragon Devkit with PCIE3 and HDMI"; + compatible = "qcom,x1e001de-devkit", "qcom,x1e001de", "qcom,x1e80100"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + /* Back panel port closer to the RJ45 connector */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* Back panel port closer to the audio jack */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + + /* Front panel port */ + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss2_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E001DE-DEVKIT"; + audio-routing = "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&nvme_reg_en>; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr1_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr1_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr1_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr2_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr2_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr2_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "SDX_VPH_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK5>; + clock-names = "xo"; + + vdd-supply = <&vreg_rtmr2_1p15>; + vdd33-supply = <&vreg_rtmr2_3p3>; + vdd33-cap-supply = <&vreg_rtmr2_3p3>; + vddar-supply = <&vreg_rtmr2_1p15>; + vddat-supply = <&vreg_rtmr2_1p15>; + vddio-supply = <&vreg_rtmr2_1p8>; + + reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>; + + orientation-switch; + retimer-switch; + + parade,disable-usb4; + + ps8830,boot-on; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + clock-names = "xo"; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>; + + retimer-switch; + orientation-switch; + + parade,disable-usb4; + + ps8830,boot-on; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + clock-names = "xo"; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>; + + retimer-switch; + orientation-switch; + + parade,disable-usb4; + + ps8830,boot-on; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + connector { + compatible = "dp-connector"; +// dp-pwr-supply = <&vreg_misc_3p3>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&dp_connector_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie3 { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3_phy { +// vdda-phy-supply = <&vreg_l3c>; +// vdda-pll-supply = <&vreg_l3e>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie6a_default>; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_gpios { + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_en: usb0-pwr-1p15-en-state { + pins = "gpio8"; + function = "normal"; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcadsp8380.mbn", + "qcom/x1e80100/Thundercomm/DEVKIT/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qccdsp8380.mbn", + "qcom/x1e80100/Thundercomm/DEVKIT/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>; /* SPI (TPM) */ + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie5_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_1p15_reg_en: rtmr2-1p15-reg-en-state { + pins = "gpio189"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_1p8_reg_en: rtmr2-1p8-reg-en-state { + pins = "gpio126"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_3p3_reg_en: rtmr2-3p3-reg-en-state { + pins = "gpio187"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_sw_en: wwan-sw-en-state { + pins = "gpio221"; + function = "gpio"; + drive-strength = <4>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&uart21 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; + + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; + + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; + + dr_mode = "host"; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&retimer_ss2_ss_in>; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 5d49df41be02a5..f015917a0e7012 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include @@ -20,6 +22,10 @@ compatible = "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100"; chassis-type = "laptop"; + aliases { + serial1 = &uart14; + }; + wcd938x: audio-codec { compatible = "qcom,wcd9385-codec"; @@ -62,6 +68,45 @@ }; }; + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 215 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 216 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-0 = <&i2c_imu_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@18 { + compatible = "st,lis2dw12"; + reg = <0x18>; + interrupts-extended = <&tlmm 28 IRQ_TYPE_LEVEL_LOW>; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + pinctrl-0 = <&imu_int_n_default>; + pinctrl-names = "default"; + vdd-supply = <&vreg_l10b_1p8>; + vddio-supply = <&vreg_l10b_1p8>; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam_indicator_en>; + + privacy_led: led-camera-indicator { + label = "platform:white:camera-indicator"; + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + }; + hdmi-bridge { compatible = "realtek,rtd2171"; @@ -360,6 +405,48 @@ regulator-boot-on; }; + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; @@ -502,6 +589,65 @@ }; }; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -562,6 +708,13 @@ regulator-initial-mode = ; }; + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + vreg_l8b_3p0: ldo8 { regulator-name = "vreg_l8b_3p0"; regulator-min-microvolt = <3072000>; @@ -805,6 +958,124 @@ regulator-initial-mode = ; }; }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p2: ldo1 { + regulator-name = "vreg_l1m_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l2m_1p2: ldo2 { + regulator-name = "vreg_l2m_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l4m_1p8: ldo4 { + regulator-name = "vreg_l4m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l5m_2p8: ldo5 { + regulator-name = "vreg_l5m_2p9"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p8: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + }; + +}; + +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + csiphy4_ep: endpoint@4 { + reg = <4>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02c10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_default>; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + leds = <&privacy_led>; + led-names = "privacy"; + + orientation = <0>; /* front facing */ + rotation = <0>; /* not rotated */ + + avdd-supply = <&vreg_l7m_2p8>; + dvdd-supply = <&vreg_l2m_1p2>; + dovdd-supply = <&vreg_l4m_1p8>; + + port { + ov02c10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&csiphy4_ep>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + phy-type = ; + + status = "okay"; }; &gpu { @@ -895,6 +1166,8 @@ orientation-switch; retimer-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -931,6 +1204,11 @@ status = "okay"; + fan-controller@36 { + compatible = "lenovo,thinkpad-t14s-fan-controller"; + reg = <0x36>; + }; + eusb5_repeater: redriver@43 { compatible = "nxp,ptn3222"; reg = <0x43>; @@ -979,7 +1257,7 @@ status = "okay"; - embedded-controller@28 { + ec: embedded-controller@28 { compatible = "lenovo,thinkpad-t14s-ec"; reg = <0x28>; @@ -988,6 +1266,8 @@ pinctrl-0 = <&ec_int_n_default>; pinctrl-names = "default"; + #thermal-sensor-cells = <1>; + wakeup-source; }; }; @@ -1018,6 +1298,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1052,9 +1334,12 @@ &i2c8 { clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c8_data_clk>, <&ts0_default>; + pinctrl-names = "default"; + status = "okay"; - /* ILIT2911 or GTCH1563 */ + /* GTCH1563 */ touchscreen@10 { compatible = "hid-over-i2c"; reg = <0x10>; @@ -1064,12 +1349,19 @@ vdd-supply = <&vreg_misc_3p3>; vddl-supply = <&vreg_l15b_1p8>; - - pinctrl-0 = <&ts0_default>; - pinctrl-names = "default"; }; - /* TODO: second-sourced touchscreen @ 0x41 */ + /* ILIT2911 */ + touchscreen@41 { + compatible = "hid-over-i2c"; + reg = <0x41>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_1p8>; + }; }; &iris { @@ -1100,6 +1392,8 @@ }; &mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + status = "okay"; }; @@ -1108,6 +1402,8 @@ }; &mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + status = "okay"; }; @@ -1123,6 +1419,10 @@ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; +&mdss_dp2 { + sound-name-prefix = "DisplayPort2"; +}; + &mdss_dp3 { /delete-property/ #sound-dai-cells; @@ -1176,6 +1476,21 @@ &pcie4_port0 { reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; }; &pcie5 { @@ -1383,10 +1698,10 @@ }; &tlmm { - gpio-reserved-ranges = <34 2>, /* Unused */ - <44 4>, /* SPI (TPM) */ - <72 2>, /* Secure EC I2C connection (?) */ - <238 1>; /* UFS Reset */ + gpio-reserved-ranges = <34 2>, /* GPIO34 = unused, GPIO35 = TPM interrupt */ + <44 4>, /* SPI11 (Nuvoton NPCT760 TPM) */ + <72 2>, /* I2C18 (Secure EC I2C connection) */ + <238 1>; /* UFS Reset (unused) */ ec_int_n_default: ec-int-n-state { pins = "gpio66"; @@ -1394,6 +1709,29 @@ bias-disable; }; + cam_indicator_en: cam-indicator-en-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + eusb3_reset_n: eusb3-reset-n-state { pins = "gpio6"; function = "gpio"; @@ -1471,6 +1809,18 @@ bias-disable; }; + imu_int_n_default: imu-int-n-state { + pins = "gpio28"; + function = "gpio"; + bias-disable; + }; + + i2c_imu_default: i2c-imu-default { + pins = "gpio215", "gpio216"; + function = "gpio"; + bias-pull-up; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; @@ -1583,6 +1933,20 @@ output-low; }; + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wwan_sw_en: wwan-sw-en-state { pins = "gpio221"; function = "gpio"; @@ -1591,6 +1955,23 @@ }; }; +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + &usb_1_ss0_hsphy { vdd-supply = <&vreg_l3j_0p8>; vdda12-supply = <&vreg_l2j_1p2>; @@ -1601,8 +1982,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1631,8 +2012,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1652,8 +2033,8 @@ }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1717,15 +2098,79 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; + +&thermal_zones { + ec-keyboard-thermal { + polling-delay = <5000>; + polling-delay-passive = <1000>; + + thermal-sensors = <&ec 1>; + + trips { + trip-point0 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <62000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + ec-charging-thermal { + polling-delay = <5000>; + polling-delay-passive = <2000>; + + thermal-sensors = <&ec 3>; + + trips { + psv0: trip-point0 { + temperature = <55000>; + hysteresis = <0>; + type = "passive"; + }; + + alert0: trip-point1 { + temperature = <63000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&psv0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu8 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu9 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu10 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu11 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + + }; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts index 75e10d97c38674..83e3a7e5e66c1d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts @@ -55,3 +55,7 @@ status = "okay"; }; + +&vreg_edp_3p3 { + regulator-always-on; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index ce7b10ea89b6dc..6f2950498d1096 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -7,9 +7,11 @@ /dts-v1/; #include +#include #include #include #include +#include #include #include "hamoa.dtsi" @@ -43,24 +45,20 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; - led-camera-indicator { - label = "white:camera-indicator"; + privacy_led: privacy-led { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; default-state = "off"; - /* Reuse as a panic indicator until we get a "camera on" trigger */ panic-indicator; }; }; pmic-glink { compatible = "qcom,x1e80100-pmic-glink", - "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, <&tlmm 123 GPIO_ACTIVE_HIGH>; @@ -151,6 +149,67 @@ }; }; + sound { + compatible = "dell,xps13-9345-sndcard"; + model = "X1E80100-Dell-XPS-13-9345"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK1 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + channels-swapped; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_cam_1p8: regulator-cam-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_CAM_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_ldo_en>; + pinctrl-names = "default"; + }; + vreg_edp_3p3: regulator-edp-3p3 { compatible = "regulator-fixed"; @@ -415,6 +474,13 @@ regulator-initial-mode = ; }; + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + vreg_l2b_3p0: ldo2 { regulator-name = "vreg_l2b_3p0"; regulator-min-microvolt = <3072000>; @@ -436,6 +502,13 @@ regulator-initial-mode = ; }; + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + vreg_l8b_3p0: ldo8 { regulator-name = "vreg_l8b_3p0"; regulator-min-microvolt = <3072000>; @@ -682,6 +755,76 @@ firmware-name = "qcom/x1e80100/dell/xps13-9345/qcdxkmsuc8380.mbn"; }; +&camcc { + status = "okay"; +}; + +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + csiphy4_ep: endpoint@4 { + reg = <4>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02e10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_default>; + + leds = <&privacy_led>; + led-names = "privacy"; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + rotation = <180>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_2p8>; + dovdd-supply = <&vreg_cam_1p8>; + + port { + ov02e10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&csiphy4_ep>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -726,6 +869,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -759,8 +904,29 @@ &i2c5 { clock-frequency = <100000>; - status = "disabled"; - /* EC @0x3b */ + status = "okay"; + + embedded-controller@3b { + compatible = "dell,xps13-9345-ec"; + reg = <0x3b>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + + io-channels = <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU(1)>, + <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU(1)>, + <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM1_100K_PU(1)>, + <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM2_100K_PU(1)>, + <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM3_100K_PU(1)>, + <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM4_100K_PU(1)>, + <&pmk8550_adc_tm PM8550_ADC5_GEN3_AMUX_THM5_100K_PU(1)>; + + io-channel-names = "sys_therm0", "sys_therm1", "sys_therm2", + "sys_therm3", "sys_therm4", "sys_therm5", + "sys_therm6"; + }; }; &i2c7 { @@ -789,6 +955,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -880,6 +1048,32 @@ status = "okay"; }; +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + &mdss { status = "okay"; }; @@ -1025,6 +1219,71 @@ }; }; +&pmk8550_adc_tm { + /* sys_therm0, around DRAM */ + channel@14c { + reg = ; + label = "sys_therm0"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + + /* sys_therm1, around left Type-C charging controller */ + channel@14d { + reg = ; + label = "sys_therm1"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + + /* sys_therm2, around upper-left side of motherboard */ + channel@144 { + reg = ; + label = "sys_therm2"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + + /* sys_therm3, around right Type-C charging controller */ + channel@145 { + reg = ; + label = "sys_therm3"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + + /* sys_therm4, around SSD connector */ + channel@146 { + reg = ; + label = "sys_therm4"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + + /* sys_therm5, around battery charging circuit */ + channel@147 { + reg = ; + label = "sys_therm5"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; + + /* sys_therm6, around keyboard */ + channel@148 { + reg = ; + label = "sys_therm6"; + qcom,hw-settle-time = <100>; + qcom,ratiometric; + qcom,adc-tm; + }; +}; + &qupv3_0 { status = "okay"; }; @@ -1069,11 +1328,91 @@ vdd3-supply = <&vreg_l14b_3p0>; }; +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ + <65 1>, /* EC Reset */ <76 4>, /* SPI19 (TZ Protected) */ <238 1>; /* UFS Reset */ + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + /* cam_aon_mclk4 */ + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + cam_indicator_en: cam-indicator-en-state { pins = "gpio110"; function = "gpio"; @@ -1081,6 +1420,19 @@ bias-disable; }; + cam_ldo_en: cam-ldo-en-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_bl_en: edp-bl-en-state { pins = "gpio74"; function = "gpio"; @@ -1286,8 +1638,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p9>; + vdda-phy-supply = <&vreg_l1j_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1316,8 +1668,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1344,6 +1696,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&eusb6_repeater>; + status = "okay"; }; @@ -1351,21 +1705,19 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb6_repeater>; - status = "okay"; }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index beb1475d7fa0c7..d67ff523928483 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include #include "hamoa.dtsi" @@ -40,6 +42,21 @@ }; }; + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; + + privacy_led: privacy-led { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + }; + pmic-glink { compatible = "qcom,x1e80100-pmic-glink", "qcom,sm8550-pmic-glink", @@ -183,6 +200,54 @@ "VA DMIC2", "vdd-micb", "VA DMIC3", "vdd-micb"; + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + wsa-dai-link { link-name = "WSA Playback"; @@ -552,6 +617,13 @@ regulator-initial-mode = ; }; + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + vreg_l8b_3p0: ldo8 { regulator-name = "vreg_l8b_3p0"; regulator-min-microvolt = <3072000>; @@ -795,6 +867,57 @@ regulator-initial-mode = ; }; }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p2: ldo1 { + regulator-name = "vreg_l1m_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l2m_1p2: ldo2 { + regulator-name = "vreg_l2m_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l4m_1p8: ldo4 { + regulator-name = "vreg_l4m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l5m_2p8: ldo5 { + regulator-name = "vreg_l5m_2p9"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p8: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + }; }; &gpu { @@ -805,6 +928,71 @@ firmware-name = "qcom/x1e80100/LENOVO/83ED/qcdxkmsuc8380.mbn"; }; +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + csiphy4_ep: endpoint@4 { + reg = <4>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02c10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_default>; + + leds = <&privacy_led>; + led-names = "privacy"; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + avdd-supply = <&vreg_l7m_2p8>; + dvdd-supply = <&vreg_l2m_1p2>; + dovdd-supply = <&vreg_l4m_1p8>; + + port { + ov02c10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&csiphy4_ep>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + phy-type = ; + + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; @@ -863,6 +1051,8 @@ orientation-switch; retimer-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -920,6 +1110,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -951,6 +1143,22 @@ }; }; +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + embedded-controller@76 { + compatible = "lenovo,yoga-slim7x-ec", "qcom,x1e-it8987-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; +}; + &i2c7 { clock-frequency = <400000>; @@ -977,6 +1185,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1352,6 +1562,35 @@ <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; @@ -1564,8 +1803,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1594,8 +1833,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1624,8 +1863,8 @@ }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts index f95b1f9f439d36..504e29d82e2a30 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts @@ -19,7 +19,7 @@ / { model = "Medion SPRCHRGD 14 S1"; - compatible = "medion,sprchrgd14s1", "qcom,x1e78100", "qcom,x1e80100"; + compatible = "medion,sprchrgd14s1", "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100"; aliases { serial0 = &uart21; @@ -857,6 +857,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -971,8 +973,6 @@ }; &mdss_dp0 { - sound-name-prefix = "DisplayPort0"; - status = "okay"; }; @@ -981,8 +981,6 @@ }; &mdss_dp2 { - sound-name-prefix = "DisplayPort2"; - status = "okay"; }; @@ -1250,8 +1248,9 @@ &tlmm { gpio-reserved-ranges = <28 4>, /* Unused */ + <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ - <238 1>; /* UFS Reset */ + <72 2>; /* Secure EC I2C connection (?) */ edp_reg_en: edp-reg-en-state { pins = "gpio54"; @@ -1407,8 +1406,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p9>; + vdda-phy-supply = <&vreg_l1j_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1428,8 +1427,8 @@ }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1497,16 +1496,16 @@ /* Right side USB-A (USB-SS 3) */ &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; /* Left side USB-A (USB-SS 4) */ &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts index 07ce43ccf39430..b3f94d74261c7e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts @@ -5,15 +5,160 @@ /dts-v1/; +#include +#include +#include + #include "hamoa.dtsi" #include "x1-microsoft-denali.dtsi" / { model = "Microsoft Surface Pro 11th Edition (OLED)"; compatible = "microsoft,denali-oled", "microsoft,denali", + "lenovo,thinkpad-t14s", "qcom,x1e80100"; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; + + privacy_led: privacy-led { + function = LED_FUNCTION_INDICATOR; + color = ; + /* GPIO225 polarity is pending hardware validation. */ + gpios = <&tlmm 225 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&apps_rsc { + regulators-0 { + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; +}; + +&camss { + status = "okay"; + + ports { + port@2 { + csiphy2_ep: endpoint@4 { + reg = <4>; + bus-type = ; + data-lanes = <0>; + remote-endpoint = <&imx681_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + clock-frequency = <400000>; + + imx681: camera@10 { + compatible = "sony,imx681"; + reg = <0x10>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam_front_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + avdd-supply = <&vreg_l7b_2p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + leds = <&privacy_led>; + led-names = "privacy"; + + orientation = <0>; + rotation = <0>; + + port { + imx681_ep: endpoint { + bus-type = ; + data-lanes = <0>; + /* Half of the observed 2406-Msymbol/s C-PHY rate. */ + link-frequencies = /bits/ 64 <1203000000>; + remote-endpoint = <&csiphy2_ep>; + }; + }; + }; +}; + +&csiphy2 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + phy-type = ; + + status = "okay"; +}; + +&gpu_zap_shader { + memory-region = <&gpu_microcode_mem>; + firmware-name = "qcom/x1e80100/microsoft/Denali/qcdxkmsuc8380.mbn"; }; &panel { compatible = "samsung,atna30dw01", "samsung,atna33xc20"; }; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/microsoft/Denali/qcadsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/microsoft/Denali/qccdsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&tlmm { + cam_front_default: cam-front-default-state { + mclk4-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 28342cb84ded76..746e1b70d79a65 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -902,6 +902,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -984,6 +986,8 @@ retimer-switch; orientation-switch; + parade,disable-usb4; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1491,8 +1495,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l1j>; + vdda-phy-supply = <&vreg_l1j>; + vdda-pll-supply = <&vreg_l2j>; status = "okay"; }; @@ -1521,8 +1525,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l2d>; + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; status = "okay"; }; @@ -1565,15 +1569,15 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 8afbac349cc910..78380fec8839eb 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -1416,8 +1416,8 @@ }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1446,8 +1446,8 @@ }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1476,8 +1476,8 @@ }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1519,15 +1519,15 @@ }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-acer-swift-go14-01.dts b/arch/arm64/boot/dts/qcom/x1p42100-acer-swift-go14-01.dts new file mode 100644 index 00000000000000..b6a359a7702554 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-acer-swift-go14-01.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* +* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +* Copyright (c) 2024, Linaro Limited +*/ + +/dts-v1/; + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" +#include "x1-acer-swift-14.dtsi" +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Acer Swift Go 14 AI (SFG14-01)"; + compatible = "acer,swift-go14-01","lenovo,thinkpad-t14s", "qcom,x1p42100", "qcom,x1e80100"; + chassis-type = "laptop"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/ACER/SFG14-01/qcdxkmsucpurwa.mbn"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/ACER/SFG14-01/qcadsp8380.mbn", + "qcom/x1e80100/ACER/SFG14-01/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/ACER/SFG14-01/qccdsp8380.mbn", + "qcom/x1e80100/ACER/SFG14-01/cdsp_dtbs.elf"; + + status = "okay"; +}; + + + diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts index 63e29d2cc4abc0..d3fc71d9dfb445 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts @@ -14,7 +14,7 @@ / { model = "ASUS Vivobook S 15 X1P-42-100"; - compatible = "asus,vivobook-s15-x1p4", "qcom,x1p42100"; + compatible = "asus,vivobook-s15-x1p4", "lenovo,thinkpad-t14s", "qcom,x1p42100"; chassis-type = "laptop"; }; @@ -22,11 +22,11 @@ firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qcdxkmsucpurwa.mbn"; }; -&iris { - firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qcvss8380.mbn"; - - status = "okay"; -}; +//&iris { +// firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qcvss8380.mbn"; +// +// status = "okay"; +//}; &remoteproc_adsp { firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qcadsp8380.mbn", diff --git a/arch/arm64/boot/dts/qcom/x1p42100-dell-latitude-5455.dts b/arch/arm64/boot/dts/qcom/x1p42100-dell-latitude-5455.dts new file mode 100644 index 00000000000000..eba4328d0111e9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-dell-latitude-5455.dts @@ -0,0 +1,53 @@ +/dts-v1/; + +#include "purwa.dtsi" +#include "x1-dell-thena.dtsi" + +/ { + model = "Dell Latitude 5455"; + compatible = "dell,latitude-5455", "lenovo,thinkpad-t14s", "qcom,x1p42100"; +}; + +/* GPU */ +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/dell/latitude-5455/qcdxkmsucpurwa.mbn"; +}; + +/* Audio DSPs */ +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/dell/latitude-5455/qcadsp8380.mbn", + "qcom/x1p42100/dell/latitude-5455/adsp_dtbs.elf"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/dell/latitude-5455/qccdsp8380.mbn", + "qcom/x1p42100/dell/latitude-5455/cdsp_dtbs.elf"; + status = "okay"; +}; + +/* Audio */ +&sound { + model = "X1E80100-Dell-Latitude-7455"; +}; + +/* Video Encoder/Decoder (Hardware Video Acceleration) */ +&iris { + firmware-name = "qcom/x1p42100/dell/latitude-5455/qcvss8380.mbn"; + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + /* Specifically kill only the phantom touchscreen */ + /delete-node/ touchscreen@9; +}; + +&vreg_edp_3p3 { + regulator-always-on; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-hp-elitebook-6-g1q.dts b/arch/arm64/boot/dts/qcom/x1p42100-hp-elitebook-6-g1q.dts new file mode 100644 index 00000000000000..ee3cc8586a10f4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-hp-elitebook-6-g1q.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" +#include "x1-hp-omnibook-x14.dtsi" +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "HP EliteBook 6 G1q 14 inch Notebook Next Gen AI PC"; + compatible = "hp,elitebook-6-g1q", "lenovo,thinkpad-t14s", "qcom,x1p42100"; + chassis-type = "laptop"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/hp/elitebook-6-g1q/qcdxkmsucpurwa.mbn"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/hp/elitebook-6-g1q/qcadsp8380.mbn", + "qcom/x1p42100/hp/elitebook-6-g1q/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/hp/elitebook-6-g1q/qccdsp8380.mbn", + "qcom/x1p42100/hp/elitebook-6-g1q/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&i2c0 { + /* The touchpad in the EliteBook is on a different I2C address */ + /delete-node/ touchpad@15; + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-5.dts b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-5.dts new file mode 100644 index 00000000000000..05f59bfb1c30fc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-5.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" +#include "x1-hp-omnibook-x14.dtsi" +/delete-node/ &backlight; +/delete-node/ &edp_bl_pwm; +/delete-node/ &edp_bl_reg_en; +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; +/delete-node/ &vreg_edp_bl; + +/ { + model = "HP OmniBook 5"; + compatible = "hp,omnibook-5", "lenovo,thinkpad-t14s", "qcom,x1p42100"; + chassis-type = "laptop"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/hp/omnibook-5/qcdxkmsucpurwa.mbn"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/hp/omnibook-5/qcadsp8380.mbn", + "qcom/x1p42100/hp/omnibook-5/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/hp/omnibook-5/qccdsp8380.mbn", + "qcom/x1p42100/hp/omnibook-5/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&edp_bl_en { + power-source = <0>; +}; + +&i2c0 { + /delete-node/ touchpad@15; +}; + +&i2c2 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c5 { + eusb9_repeater: redriver@4b { + compatible = "nxp,ptn3222"; + reg = <0x4b>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb9_reset_n>; + pinctrl-names = "default"; + }; +}; + +&mdss_dp3 { + aux-bus { + panel { + /delete-property/ backlight; + + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + }; + }; +}; + +&sound { + model = "X1P42100-HP-OMNIBOOK-5"; +}; + +&tlmm { + eusb9_reset_n: eusb9-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb9_repeater>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts index 0f338e457abda9..43a00ef27932a5 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts @@ -10,7 +10,7 @@ / { model = "HP Omnibook X 14-fe1"; - compatible = "hp,omnibook-x14-fe1", "qcom,x1p42100"; + compatible = "hp,omnibook-x14-fe1", "lenovo,thinkpad-t14s", "qcom,x1p42100"; chassis-type = "laptop"; }; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-5-2in1.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-5-2in1.dts new file mode 100644 index 00000000000000..7e66eeff861455 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-5-2in1.dts @@ -0,0 +1,1676 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + * Copyright (c) 2025, Jens Glathe + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Lenovo IdeaPad 5 2in1 14Q8X9"; + compatible = "lenovo,ideapad-5-2in1", "lenovo,thinkpad-t14s", "qcom,x1p42100"; + chassis-type = "laptop"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + camera { + compatible = "regulator-dummy-consumer"; + + vdd-supply = <&vreg_cam_5p0>; + }; + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; + }; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-Ideapad-5"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 167 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 168 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 179 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; + + vreg_cam_5p0: regulator-cam-5p0 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_CAM_5P0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/LENOVO/83GH/qcdxkmsucpurwa.mbn"; +}; + +&i2c2 { + clock-frequency = <400000>; + + pinctrl-0 = <&qup_i2c2_data_clk>, <&tpad_default>, <&kybd_default>; + pinctrl-names = "default"; + status = "okay"; + + /* ELAN06FA */ + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* CIRQ1080 or SYNA2BA6 */ + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* FTCS0038 */ + touchpad@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* GXTP5100 */ + touchpad@5d { + compatible = "hid-over-i2c"; + reg = <0x5d>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb9_repeater: redriver@4b { + compatible = "nxp,ptn3222"; + reg = <0x4b>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + /* WACF2200 */ + touchscreen@a { + compatible = "hid-over-i2c"; + reg = <0x0a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +//&iris { +// firmware-name = "qcom/x1p42100/LENOVO/83GH/qcvss8380_pa.mbn"; +// status = "okay"; +//}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <2400000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + power-supply = <&vreg_edp_3p3>; + + max-brightness = <2047>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + drive-push-pull; + input-disable; + output-enable; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/LENOVO/83GH/qcadsp8380.mbn", + "qcom/x1p42100/LENOVO/83GH/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/LENOVO/83GH/qccdsp8380.mbn", + "qcom/x1p42100/LENOVO/83GH/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; +// bus-width = <4>; +// no-sdio; +// no-mmc; + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <72 2>; /* Secure EC I2C connection (?) */ + + cam_reg_en: cam-reg-en-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + oe-n-pins { + pins = "gpio167"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio168"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + }; + + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + oe-n-pins { + pins = "gpio178"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio179"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2 { + dr_mode = "host"; + maximum-speed = "high-speed"; + phys = <&usb_1_ss2_hsphy>; + phy-names = "usb2-phy"; + qcom,select-utmi-as-pipe-clk; + status = "okay"; + /delete-property/ port@1; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <0 1 2 3>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + }; + }; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb9_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-5.dtsi b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-5.dtsi new file mode 100644 index 00000000000000..b126e8c5e48d27 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-5.dtsi @@ -0,0 +1,1510 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + * Copyright (c) 2026 Jens Glathe + */ + +#include +#include +#include +#include +#include + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; + }; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-Ideapad-5"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb9_repeater: redriver@4b { + compatible = "nxp,ptn3222"; + reg = <0x4b>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb9_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <2400000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + drive-push-pull; + input-disable; + output-enable; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&remoteproc_adsp { + status = "okay"; +}; + +&remoteproc_cdsp { + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <72 2>; /* Secure EC I2C connection (?) */ + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb9_reset_n: eusb9-reset-n-state { + pins = "gpio9"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + oe-n-pins { + pins = "gpio168"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio167"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + }; + + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + oe-n-pins { + pins = "gpio179"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio178"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2 { + dr_mode = "host"; + maximum-speed = "high-speed"; + phys = <&usb_1_ss2_hsphy>; + phy-names = "usb2-phy"; + + status = "okay"; + /delete-property/ port@1; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&eusb9_repeater>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + }; + }; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-slim5x-lcd.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-slim5x-lcd.dts new file mode 100644 index 00000000000000..762e3da470966f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-slim5x-lcd.dts @@ -0,0 +1,1712 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + * Copyright (c) 2026 Jens Glathe + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Lenovo IdeaPad Slim 5x 14Q8X9 (LCD)"; + compatible = "lenovo,ideapad-slim5x-lcd", "lenovo,thinkpad-t14s", "qcom,x1p42100"; + chassis-type = "laptop"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 4166667>; + + power-supply = <&vreg_edp_3p3>; + }; + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; + }; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-Ideapad-5"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/LENOVO/83HL/qcdxkmsucpurwa.mbn"; +}; + +&i2c0 { + clock-frequency = <400000>; + + pinctrl-0 = <&qup_i2c0_data_clk>, <&tpad_default>, <&kybd_default>; + pinctrl-names = "default"; + status = "okay"; + + /* ELAN06FA */ + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* CIRQ1080 or SYNA2BA6 */ + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* FTCS0038 */ + touchpad@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* GXTP5100 */ + touchpad@5d { + compatible = "hid-over-i2c"; + reg = <0x5d>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + /* 3d PS883x */ +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + /* 1st PS883x */ +}; + +&i2c4 { + clock-frequency = <400000>; + + status = "okay"; + + /* unknown but active on Windows */ +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb9_repeater: redriver@4b { + compatible = "nxp,ptn3222"; + reg = <0x4b>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb9_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + /* 2nd PS883x */ +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + /* unknown but active on Windows */ +}; + +//&iris { +// firmware-name = "qcom/x1p42100/LENOVO/83HL/qcvss8380.mbn"; +// status = "okay"; +//}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <2400000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + backlight = <&backlight>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + max-link-speed = <1>; + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l3j_0p8>; + + status = "okay"; +}; + +&pcie3_port0 { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + drive-push-pull; + input-disable; + output-enable; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/LENOVO/83HL/qcadsp8380.mbn", + "qcom/x1p42100/LENOVO/83HL/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/LENOVO/83HL/qccdsp8380.mbn", + "qcom/x1p42100/LENOVO/83HL/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&spi10 { + status = "disabled"; + + /* Unknown device */ +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, + <72 2>; /* Secure EC I2C connection (?) */ + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb9_reset_n: eusb9-reset-n-state { + pins = "gpio9"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + oe-n-pins { + pins = "gpio168"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio167"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + }; + + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + oe-n-pins { + pins = "gpio179"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio178"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; + + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2 { + dr_mode = "host"; + maximum-speed = "high-speed"; + phys = <&usb_1_ss2_hsphy>; + phy-names = "usb2-phy"; + qcom,select-utmi-as-pipe-clk; + status = "okay"; + /delete-property/ port@1; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&eusb9_repeater>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + }; + }; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-slim5x-oled.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-slim5x-oled.dts new file mode 100644 index 00000000000000..de7422c87011e4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-ideapad-slim5x-oled.dts @@ -0,0 +1,1701 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + * Copyright (c) 2026 Jens Glathe + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Lenovo IdeaPad Slim 5x 14Q8X9 (OLED)"; + compatible = "lenovo,ideapad-slim5x-oled", "lenovo,thinkpad-t14s", "qcom,x1p42100"; + chassis-type = "laptop"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; + }; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-Ideapad-5"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/LENOVO/83HL/qcdxkmsucpurwa.mbn"; +}; + +&i2c0 { + clock-frequency = <400000>; + + pinctrl-0 = <&qup_i2c0_data_clk>, <&tpad_default>, <&kybd_default>; + pinctrl-names = "default"; + status = "okay"; + + /* ELAN06FA */ + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* CIRQ1080 or SYNA2BA6 */ + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* FTCS0038 */ + touchpad@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* GXTP5100 */ + touchpad@5d { + compatible = "hid-over-i2c"; + reg = <0x5d>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + /* 3d PS883x */ +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + /* 1st PS883x */ +}; + +&i2c4 { + clock-frequency = <400000>; + + status = "okay"; + + /* unknown but active on Windows */ +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb9_repeater: redriver@4b { + compatible = "nxp,ptn3222"; + reg = <0x4b>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb9_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + /* 2nd PS883x */ +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + /* unknown but active on Windows */ +}; + +//&iris { +// firmware-name = "qcom/x1p42100/LENOVO/83HL/qcvss8380.mbn"; +// status = "okay"; +//}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <2400000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + max-link-speed = <1>; + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l3j_0p8>; + + status = "okay"; +}; + +&pcie3_port0 { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + drive-push-pull; + input-disable; + output-enable; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/LENOVO/83HL/qcadsp8380.mbn", + "qcom/x1p42100/LENOVO/83HL/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/LENOVO/83HL/qccdsp8380.mbn", + "qcom/x1p42100/LENOVO/83HL/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&spi10 { + status = "disabled"; + + /* Unknown device */ +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, + <72 2>; /* Secure EC I2C connection (?) */ + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb9_reset_n: eusb9-reset-n-state { + pins = "gpio9"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + oe-n-pins { + pins = "gpio168"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio167"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + }; + + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + oe-n-pins { + pins = "gpio179"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio178"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2 { + dr_mode = "host"; + maximum-speed = "high-speed"; + phys = <&usb_1_ss2_hsphy>; + phy-names = "usb2-phy"; + qcom,select-utmi-as-pipe-clk; + status = "okay"; + /delete-property/ port@1; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&eusb9_repeater>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + }; + }; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index 500809772097e2..1768f5594ed163 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -21,7 +22,7 @@ / { model = "Lenovo ThinkBook 16 Gen 7 QOY"; - compatible = "lenovo,thinkbook-16", "qcom,x1p42100"; + compatible = "lenovo,thinkbook-16", "lenovo,thinkpad-t14s", "qcom,x1p42100"; chassis-type = "laptop"; aliases { @@ -46,6 +47,7 @@ qcom,tx-device = <&wcd_tx>; reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + mux-controls = <&us_euro_mux_ctrl>; vdd-buck-supply = <&vreg_l15b_1p8>; vdd-rxtx-supply = <&vreg_l15b_1p8>; @@ -79,9 +81,7 @@ }; hdmi-bridge { - compatible = "realtek,rtd2171"; - - enable-gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>; + compatible = "parade,ps185hdm"; pinctrl-0 = <&hdmi_hpd_default>; pinctrl-names = "default"; @@ -226,12 +226,60 @@ "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", "AMIC2", "MIC BIAS2", - "VA DMIC0", "MIC BIAS3", - "VA DMIC1", "MIC BIAS3", - "VA DMIC2", "MIC BIAS1", - "VA DMIC3", "MIC BIAS1", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", "TX SWR_INPUT1", "ADC2_OUTPUT"; + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + wcd-playback-dai-link { link-name = "WCD Playback"; @@ -297,6 +345,16 @@ }; }; + /* two muxes together support CTIA and OMTP switching */ + us_euro_mux_ctrl: mux-controller { + compatible = "gpio-mux"; + pinctrl-0 = <&us_euro_hs_sel>; + pinctrl-names = "default"; + mux-supply = <&vreg_l16b_2p5>; + #mux-control-cells = <0>; + mux-gpios = <&tlmm 68 GPIO_ACTIVE_HIGH>; + }; + usb-1-ss0-sbu-mux { compatible = "onnn,fsusb42", "gpio-sbu-mux"; @@ -572,6 +630,10 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + }; }; vreg_l5b_3p0: ldo5 { @@ -629,6 +691,10 @@ regulator-min-microvolt = <3072000>; regulator-max-microvolt = <3072000>; regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + }; }; vreg_l14b_3p0: ldo14 { @@ -646,10 +712,10 @@ regulator-always-on; }; - vreg_l16b_2p9: ldo16 { - regulator-name = "vreg_l16b_2p9"; - regulator-min-microvolt = <2912000>; - regulator-max-microvolt = <2912000>; + vreg_l16b_2p5: ldo16 { + regulator-name = "vreg_l16b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; regulator-initial-mode = ; }; @@ -973,6 +1039,11 @@ vdd3v3-supply = <&vreg_l13b_3p0>; vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; }; eusb3_repeater: redriver@47 { @@ -996,11 +1067,6 @@ vdd3v3-supply = <&vreg_l13b_3p0>; vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb9_reset_n>; - pinctrl-names = "default"; }; eusb6_repeater: redriver@4f { @@ -1039,6 +1105,11 @@ }; }; +&iris { + firmware-name = "qcom/x1p42100/LENOVO/21NH/qcvss8380.mbn"; + status = "okay"; +}; + &lpass_tlmm { spkr_01_sd_n_active: spkr-01-sd-n-active-state { pins = "gpio12"; @@ -1050,11 +1121,11 @@ }; &lpass_vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-0 = <&dmic01_default>; pinctrl-names = "default"; vdd-micb-supply = <&vreg_l1b_1p8>; - qcom,dmic-sample-rate = <4800000>; + qcom,dmic-sample-rate = <2400000>; }; &mdss { @@ -1062,24 +1133,28 @@ }; &mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + status = "okay"; }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + status = "okay"; }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + status = "okay"; }; @@ -1090,7 +1165,7 @@ &mdss_dp3 { /delete-property/ #sound-dai-cells; - pinctrl-0 = <&edp_hpd_default>; + pinctrl-0 = <&edp0_hpd_default>; pinctrl-names = "default"; status = "okay"; @@ -1194,9 +1269,9 @@ pins = "gpio6"; function = "normal"; bias-disable; + drive-push-pull; input-disable; output-enable; - drive-push-pull; power-source = <1>; /* 1.8 V */ qcom,drive-strength = ; }; @@ -1229,6 +1304,18 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/x1p42100/LENOVO/21NH/qcadsp8380.mbn", "qcom/x1p42100/LENOVO/21NH/adsp_dtbs.elf"; @@ -1250,6 +1337,9 @@ pinctrl-names = "default", "sleep"; vmmc-supply = <&vreg_l9b_2p9>; vqmmc-supply = <&vreg_l6b_1p8>; +// bus-width = <4>; +// no-sdio; +// no-mmc; status = "okay"; }; @@ -1328,12 +1418,6 @@ gpio-reserved-ranges = <34 2>, /* Unused */ <72 2>; /* Secure EC I2C connection (?) */ - edp_hpd_default: edp-hpd-default-state { - pins = "gpio119"; - function = "edp0_hot"; - bias-disable; - }; - cam_reg_en: cam-reg-en-state { pins = "gpio44"; function = "gpio"; @@ -1349,16 +1433,16 @@ output-low; }; - eusb6_reset_n: eusb6-reset-n-state { - pins = "gpio184"; + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; function = "gpio"; drive-strength = <2>; bias-disable; output-low; }; - eusb9_reset_n: eusb9-reset-n-state { - pins = "gpio7"; + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; function = "gpio"; drive-strength = <2>; bias-disable; @@ -1378,13 +1462,6 @@ bias-disable; }; - hdmi_bridge_en: hdmi-bridge-en-state { - pins = "gpio120"; - function = "gpio"; - drive-strength = <16>; - bias-pull-down; - }; - hdmi_hpd_default: hdmi-hpd-default-state { pins = "gpio126"; function = "usb2_dp"; @@ -1478,6 +1555,13 @@ }; }; + us_euro_hs_sel: us-euro-hs-sel-state { + pins = "gpio68"; + function = "gpio"; + bias-pull-down; + drive-strength = <2>; + }; + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { oe-n-pins { pins = "gpio167"; @@ -1616,7 +1700,7 @@ maximum-speed = "high-speed"; phys = <&usb_1_ss2_hsphy>; phy-names = "usb2-phy"; - + qcom,select-utmi-as-pipe-clk; status = "okay"; /delete-property/ port@1; }; @@ -1625,7 +1709,7 @@ vdd-supply = <&vreg_l3j_0p8>; vdda12-supply = <&vreg_l2j_1p2>; - phys = <&eusb5_repeater>; + phys = <&eusb9_repeater>; status = "okay"; }; @@ -1666,7 +1750,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb9_repeater>; + phys = <&eusb5_repeater>; status = "okay"; }; @@ -1679,7 +1763,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb6_repeater>; + phys = <&eusb3_repeater>; status = "okay"; }; @@ -1695,7 +1779,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb3_repeater>; + phys = <&eusb6_repeater>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts b/arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts new file mode 100644 index 00000000000000..6c2129a0d6ad00 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts @@ -0,0 +1,1236 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + * Copyright (c) 2025, Jens Glathe + * Copyright (c) 2025, Harrison Vanderbyl + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Surface Pro 12in 1st Edition"; + compatible = "microsoft,surface-pro-12in", "lenovo,thinkpad-t14s", "qcom,x1p42100"; + chassis-type = "tablet"; + + aliases { + serial0 = &uart2; + serial1 = &uart14; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + + power-supply = <&vreg_edp_3p3>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>, <&vol_up_n_default>, <&vol_down_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + + key-vol-up { + gpios = <&pm8550_gpios 8 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-vol-down { + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Right-side upper port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + + /* Right-side lower port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x20000000>; + reusable; + linux,cma-default; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + vin-supply = <&vreg_panel_en>; + }; + + vreg_panel_en: regulator-panel-en { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PANEL_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-enable-ramp-delay = <150000>; + + pinctrl-0 = <&panel_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1P42100-Microsoft-Surface-Pro-12in"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/Microsoft/Surface12/qcdxkmsucpurwa.mbn"; +}; + +&i2c8 { + clock-frequency = <1000000>; + + status = "okay"; + + touchscreen@16 { + compatible = "hid-over-i2c"; + reg = <0x16>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 38 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + + vddl-supply = <&vreg_l15b_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + + /* MAX34417 @12 */ + /* MAX34417 @14 */ + /* MAX34417 @16 */ + /* MAX34417 @18 */ + /* MAX34417 @1a */ + + status = "okay"; +}; + +&i2c9 { + clock-frequency = <400000>; + + /* NFC @28, commercial devices only */ + + status = "okay"; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + qcom,dmic-sample-rate = <4800000>; + + vdd-micb-supply = <&vreg_l1b_1p8>; + + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + sound-name-prefix = "DisplayPort1"; + + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + + disable-rfkill; + local-mac-address = [ 8d fd f0 00 5a ae ]; + + }; +}; + +&pm8550_gpios { + vol_up_n_default: vol-up-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + vol_down_n_default: vol-down-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/Microsoft/Surface12/qcadsp8380.mbn", + "qcom/x1p42100/Microsoft/Surface12/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/Microsoft/Surface12/qccdsp8380.mbn", + "qcom/x1p42100/Microsoft/Surface12/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + status = "okay"; + + /* WSA8845, Left speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>; /* SPI (TPM) */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio2"; + function = "gpio"; + bias-disable; + }; + + panel_en: panel-en-state { + pins = "gpio29"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ssam_state: ssam-state-state { + pins = "gpio91"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio38"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + oe-n-pins { + pins = "gpio168"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio167"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + oe-n-pins { + pins = "gpio179"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio178"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; +}; + +&uart2 { + status = "okay"; + + embedded-controller { + compatible = "microsoft,surface-sam"; + + interrupts-extended = <&tlmm 91 IRQ_TYPE_EDGE_RISING>; + + current-speed = <4000000>; + + pinctrl-0 = <&ssam_state>; + pinctrl-names = "default"; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + + local-bd-address = [ 8d fd f0 00 5a ad ]; + }; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l2i_1p2>; + vccq-max-microamp = <900000>; + + vdd-hba-supply = <&vreg_l3j_0p8>; + + status = "okay"; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p64100-acer-swift-sf14-11.dts b/arch/arm64/boot/dts/qcom/x1p64100-acer-swift-sf14-11.dts new file mode 100644 index 00000000000000..9abfe359566e77 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p64100-acer-swift-sf14-11.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* +* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +* Copyright (c) 2024, Linaro Limited +*/ + +/dts-v1/; + +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" +#include "x1-acer-swift-14.dtsi" + +/ { + model = "Acer Swift 14 AI (SF14-11)"; + compatible = "acer,swift-sf14-11","lenovo,thinkpad-t14s", "qcom,x1p64100", "qcom,x1e80100"; + chassis-type = "laptop"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/ACER/SF14-11/qcdxkmsuc8380.mbn"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/ACER/SF14-11/qcadsp8380.mbn", + "qcom/x1e80100/ACER/SF14-11/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/ACER/SF14-11/qccdsp8380.mbn", + "qcom/x1e80100/ACER/SF14-11/cdsp_dtbs.elf"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts b/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts index d96202e2afc617..72a9c3b6b7bfc5 100644 --- a/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts +++ b/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts @@ -11,5 +11,37 @@ / { model = "Microsoft Surface Pro 11th Edition (LCD)"; compatible = "microsoft,denali-lcd", "microsoft,denali", + "lenovo,thinkpad-t14s", "qcom,x1p64100", "qcom,x1e80100"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + + power-supply = <&vreg_edp_3p3>; + }; + +}; + +&gpu_zap_shader { + memory-region = <&gpu_microcode_mem>; + firmware-name = "qcom/x1e80100/microsoft/Denali/qcdxkmsuc8380.mbn"; +}; + +&pmk8550_pwm { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/microsoft/Denali/qcadsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/microsoft/Denali/qccdsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/cdsp_dtb.mbn"; + + status = "okay"; }; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 654a102cb5bc55..a73b80c36cc2ad 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -949,8 +949,12 @@ CONFIG_VIDEO_TI_J721E_CSI2RX=m CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_OV02C10=m +CONFIG_VIDEO_OV02E10=m +CONFIG_VIDEO_OV08X40=m CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5675=m CONFIG_VIDEO_S5KJN1=m CONFIG_DRM=m CONFIG_DRM_HDLCD=m @@ -1369,6 +1373,9 @@ CONFIG_RTC_DRV_RENESAS_RTCA3=m CONFIG_RTC_DRV_MACSMC=m CONFIG_RTC_DRV_S32G=m CONFIG_DMADEVICES=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_UDMABUF=y CONFIG_APPLE_ADMAC=m CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m @@ -1476,6 +1483,7 @@ CONFIG_CLK_X1E80100_CAMCC=m CONFIG_CLK_X1E80100_DISPCC=m CONFIG_CLK_X1E80100_GCC=y CONFIG_CLK_X1E80100_GPUCC=m +CONFIG_CLK_X1P42100_GPUCC=m CONFIG_CLK_X1E80100_TCSRCC=y CONFIG_CLK_X1P42100_GPUCC=m CONFIG_CLK_QCM2290_GPUCC=m @@ -1575,6 +1583,7 @@ CONFIG_SA_VIDEOCC_8775P=m CONFIG_SM_VIDEOCC_6350=m CONFIG_SM_VIDEOCC_MILOS=m CONFIG_SM_VIDEOCC_8250=y +CONFIG_SM_VIDEOCC_8350=m CONFIG_SM_VIDEOCC_8550=m CONFIG_SM_VIDEOCC_8750=m CONFIG_QCOM_HFPLL=y @@ -1932,6 +1941,8 @@ CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_SHA3=m CONFIG_CRYPTO_SM3=m CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_GHASH_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_BS=m diff --git a/arch/arm64/configs/qcom_laptops.config b/arch/arm64/configs/qcom_laptops.config new file mode 100644 index 00000000000000..144cf7f8e1fc30 --- /dev/null +++ b/arch/arm64/configs/qcom_laptops.config @@ -0,0 +1,102 @@ +# Disable other archs to speed up builds and reduce size of kernel +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_AIROHA is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_APPLE is not set +# CONFIG_ARCH_AXIADO is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BLAIZE is not set +# CONFIG_ARCH_CIX is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SPARX5 is not set +# CONFIG_ARCH_K3 is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEEMBAY is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_NXP is not set +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_S32 is not set +# CONFIG_ARCH_MA35 is not set +# CONFIG_ARCH_NPCM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set +# CONFIG_ARCH_SOPHGO is not set +# CONFIG_ARCH_STM32 is not set +# CONFIG_ARCH_SYNQUACER is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_TESLA_FSD is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VISCONTI is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZYNQMP is not set + +# Disable bigger drivers for non-existing hardware (e.g. other SoCs) +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_LIMA is not set +# CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_PANTHOR is not set +# CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_POWERVR is not set + +# Needed to have SCM calls properly working in EL2 +# TODO: Is this stable enough to be enabled for all SoCs in defconfig? +CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE=y + +# Modern Bluetooth devices (like mice) need this to work properly +# Without, they will connect but not actually work +CONFIG_BT_LE=y +CONFIG_BT_LE_L2CAP_ECRED=y + +# Full disk encryption +CONFIG_DM_CRYPT=m + +# libcamera softisp +CONFIG_DMABUF_HEAPS_CMA=y + +# For Ubuntu/snap +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +# For Ubuntu/localsearch +CONFIG_SECURITY_LANDLOCK=y + +# For network sharing, e.g. in Ubuntu connection sharing with test boards +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NFT_NAT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_CT=m +CONFIG_NFT_REJECT=m +CONFIG_NF_CONNTRACK=m + +# Network from mobile phone (so as a device) +CONFIG_USB_NET_RNDIS_HOST=m + +# Typical use-cases for desktop/laptop +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC_USB=m +CONFIG_SND_USB_AUDIO_MIDI_V2=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_UHID=m diff --git a/arch/arm64/configs/ubuntu_x1e_defconfig b/arch/arm64/configs/ubuntu_x1e_defconfig new file mode 100644 index 00000000000000..c4b9d53013b6df --- /dev/null +++ b/arch/arm64/configs/ubuntu_x1e_defconfig @@ -0,0 +1,7573 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_ZSTD=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_WATCH_QUEUE=y +CONFIG_NO_HZ_FULL=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_LSM=y +CONFIG_PREEMPT=y +CONFIG_PREEMPT_DYNAMIC=y +CONFIG_SCHED_CORE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_RCU_LAZY=y +CONFIG_RCU_LAZY_DEFAULT_OFF=y +CONFIG_IKHEADERS=m +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_UCLAMP_TASK=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_UCLAMP_TASK_GROUP=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_EXPERT=y +CONFIG_SGETMASK_SYSCALL=y +CONFIG_PROFILING=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_KEXEC_SIG=y +CONFIG_ARCH_ACTIONS=y +CONFIG_ARCH_AIROHA=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_APPLE=y +CONFIG_ARCH_BERLIN=y +CONFIG_ARCH_BITMAIN=y +CONFIG_ARCH_K3=y +CONFIG_ARCH_LG1K=y +CONFIG_ARCH_HISI=y +CONFIG_ARCH_KEEMBAY=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MESON=y +CONFIG_ARCH_MICROCHIP=y +CONFIG_ARCH_SPARX5=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_NXP=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_S32=y +CONFIG_ARCH_MA35=y +CONFIG_ARCH_NPCM=y +CONFIG_ARCH_PENSANDO=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_REALTEK=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARCH_SEATTLE=y +CONFIG_ARCH_INTEL_SOCFPGA=y +CONFIG_ARCH_STM32=y +CONFIG_ARCH_SYNQUACER=y +CONFIG_ARCH_TEGRA=y +CONFIG_ARCH_SPRD=y +CONFIG_ARCH_THUNDER=y +CONFIG_ARCH_THUNDER2=y +CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_VISCONTI=y +CONFIG_ARCH_XGENE=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_ARM64_ERRATUM_834220=y +CONFIG_ARM64_ERRATUM_2441007=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_ARM64_ERRATUM_2441009=y +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=6 +CONFIG_HZ_1000=y +CONFIG_XEN=y +CONFIG_ARM64_SW_TTBR0_PAN=y +CONFIG_COMPAT=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +CONFIG_ARM64_PMEM=y +CONFIG_ARM64_PSEUDO_NMI=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y +CONFIG_CMDLINE="console=ttyAMA0" +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ENERGY_MODEL=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m +CONFIG_ARM_APPLE_SOC_CPUFREQ=m +CONFIG_ARM_ARMADA_37XX_CPUFREQ=m +CONFIG_ARM_ARMADA_8K_CPUFREQ=m +CONFIG_ARM_SCPI_CPUFREQ=m +CONFIG_ARM_IMX6Q_CPUFREQ=m +CONFIG_ARM_IMX_CPUFREQ_DT=m +CONFIG_ARM_MEDIATEK_CPUFREQ=m +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=m +CONFIG_ARM_QCOM_CPUFREQ_HW=m +CONFIG_ARM_SCMI_CPUFREQ=y +CONFIG_ARM_TEGRA186_CPUFREQ=m +CONFIG_ARM_TEGRA194_CPUFREQ=m +CONFIG_QORIQ_CPUFREQ=m +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ACPI=y +CONFIG_ACPI_FPDT=y +CONFIG_ACPI_TAD=m +CONFIG_ACPI_DOCK=y +CONFIG_ACPI_IPMI=m +# CONFIG_ACPI_DEBUG is not set +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_HOTPLUG_MEMORY=y +CONFIG_ACPI_BGRT=y +CONFIG_ACPI_NFIT=m +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=m +CONFIG_ACPI_CONFIGFS=m +CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_AGDI=y +CONFIG_ACPI_FFH=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16 +CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_EXTENDED_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_ZSTD=y +CONFIG_MODULE_DECOMPRESS=y +CONFIG_BLK_DEV_ZONED=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_BLK_WBT=y +CONFIG_BLK_CGROUP_FC_APPID=y +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_SED_OPAL=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AIX_PARTITION=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_OF_PARTITION=y +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +CONFIG_BINFMT_MISC=m +CONFIG_ZSWAP=y +CONFIG_ZSWAP_SHRINKER_DEFAULT_ON=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_KMALLOC_PARTITION_CACHES=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_MEMORY_FAILURE=y +CONFIG_HWPOISON_INJECT=m +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_CMA_SYSFS=y +CONFIG_CMA_AREAS=7 +CONFIG_PAGE_BLOCK_MAX_ORDER=10 +CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_ZONE_DEVICE=y +CONFIG_ANON_VMA_NAME=y +CONFIG_USERFAULTFD=y +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX_DIAG=m +CONFIG_TLS_DEVICE=y +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_ESPINTCP=y +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_AO=y +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_IOAM6_LWTUNNEL=y +CONFIG_MPTCP=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XTABLES_COMPAT=y +CONFIG_NETFILTER_XTABLES_LEGACY=y +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_SCTP=m +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +CONFIG_TIPC=m +CONFIG_TIPC_MEDIA_IB=y +CONFIG_ATM=m +CONFIG_ATM_BR2684=m +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +CONFIG_BRIDGE_CFM=y +CONFIG_NET_DSA=m +CONFIG_NET_DSA_TAG_RZN1_A5PSW=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=m +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_ETS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_TC_SKB_EXT=y +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_VMWARE_VMCI_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_HSR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_NET_NCSI=y +CONFIG_NCSI_OEM_CMD_GET_MAC=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=y +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_AOSPEXT=y +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBCM4377=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_QCOMSMD=m +CONFIG_BT_VIRTIO=m +CONFIG_BT_NXPUART=m +CONFIG_BT_INTEL_PCIE=m +CONFIG_AF_RXRPC_IPV6=y +CONFIG_RXKAD=y +CONFIG_RXPERF=m +CONFIG_AF_KCM=m +CONFIG_MCTP=y +CONFIG_CFG80211=m +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_DEBUGFS=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_XEN=m +CONFIG_NET_9P_RDMA=m +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y +CONFIG_NFC_TRF7970A=m +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_VIRTUAL_NCI=m +CONFIG_NFC_FDP=m +CONFIG_NFC_FDP_I2C=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_MRVL_SPI=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_S3FWRN82_UART=m +CONFIG_NFC_ST95HF=m +CONFIG_NET_IFE=m +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_PTM=y +CONFIG_PCIE_EDR=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_PCI_P2PDMA=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_HOTPLUG_PCI_ACPI_AMPERE_ALTRA=m +CONFIG_HOTPLUG_PCI_ACPI_IBM=m +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=y +CONFIG_PCI_AARDVARK=y +CONFIG_PCIE_ALTERA=y +CONFIG_PCIE_ALTERA_MSI=y +CONFIG_PCIE_APPLE=m +CONFIG_PCI_HOST_THUNDER_PEM=y +CONFIG_PCI_HOST_THUNDER_ECAM=y +CONFIG_PCI_FTPCI100=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_HISI_ERR=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_MEDIATEK_GEN3=m +CONFIG_PCI_TEGRA=y +CONFIG_PCIE_RCAR_HOST=y +CONFIG_PCIE_RCAR_EP=y +CONFIG_PCIE_ROCKCHIP_HOST=m +CONFIG_PCIE_ROCKCHIP_EP=y +CONFIG_PCI_XGENE=y +CONFIG_PCIE_XILINX=y +CONFIG_PCIE_XILINX_DMA_PL=y +CONFIG_PCIE_XILINX_NWL=y +CONFIG_PCIE_XILINX_CPM=y +CONFIG_PCIE_CADENCE_PLAT_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +CONFIG_PCI_J721E_HOST=y +CONFIG_PCI_J721E_EP=y +CONFIG_PCIE_AL=y +CONFIG_PCI_IMX6_HOST=y +CONFIG_PCI_IMX6_EP=y +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_LAYERSCAPE_EP=y +CONFIG_PCI_HISI=y +CONFIG_PCIE_KIRIN=y +CONFIG_PCIE_HISI_STB=y +CONFIG_PCIE_KEEMBAY_HOST=y +CONFIG_PCIE_KEEMBAY_EP=y +CONFIG_PCIE_ARMADA_8K=y +CONFIG_PCIE_TEGRA194_HOST=m +CONFIG_PCIE_TEGRA194_EP=m +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCIE_QCOM=y +CONFIG_PCIE_QCOM_EP=m +CONFIG_PCIE_RCAR_GEN4_HOST=m +CONFIG_PCIE_RCAR_GEN4_EP=m +CONFIG_PCIE_ROCKCHIP_DW_HOST=y +CONFIG_PCIE_ROCKCHIP_DW_EP=y +CONFIG_PCI_KEYSTONE_HOST=y +CONFIG_PCI_KEYSTONE_EP=y +CONFIG_PCIE_VISCONTI_HOST=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_NTB=m +CONFIG_PCI_EPF_VNTB=m +CONFIG_PCI_EPF_MHI=m +CONFIG_CXL_BUS=m +CONFIG_PCCARD=m +CONFIG_YENTA=m +CONFIG_RAPIDIO=y +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAPIDIO_DMA_ENGINE=y +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_MPORT_CDEV=m +CONFIG_RAPIDIO_CPS_XX=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_RXS_GEN3=m +CONFIG_PC104=y +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_MOXTET=m +CONFIG_HISILICON_LPC=y +CONFIG_IMX_WEIM=y +CONFIG_QCOM_SSC_BLOCK_BUS=y +CONFIG_SUNXI_RSB=m +CONFIG_TEGRA_ACONNECT=m +CONFIG_TEGRA_GMI=m +CONFIG_FSL_MC_UAPI_SUPPORT=y +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_BUS_EP=m +CONFIG_CONNECTOR=y +CONFIG_ARM_SCMI_RAW_MODE_SUPPORT=y +CONFIG_ARM_SCMI_RAW_MODE_SUPPORT_COEX=y +CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE=y +CONFIG_ARM_SCMI_POWER_CONTROL=m +CONFIG_ARM_SCPI_PROTOCOL=m +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_DMI_SYSFS=m +CONFIG_ISCSI_IBFT=m +CONFIG_FW_CFG_SYSFS=m +CONFIG_INTEL_STRATIX10_SERVICE=m +CONFIG_INTEL_STRATIX10_RSU=m +CONFIG_MTK_ADSP_IPC=m +CONFIG_SYSFB_SIMPLEFB=y +CONFIG_TURRIS_MOX_RWTM=m +CONFIG_ARM_FFA_TRANSPORT=m +CONFIG_EFI_VARS_PSTORE=m +CONFIG_EFI_ZBOOT=y +# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set +CONFIG_EFI_BOOTLOADER_CONTROL=m +CONFIG_EFI_CAPSULE_LOADER=m +CONFIG_EFI_TEST=m +CONFIG_RESET_ATTACK_MITIGATION=y +CONFIG_EFI_COCO_SECRET=y +CONFIG_IMX_DSP=m +CONFIG_IMX_SCU=y +CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE=y +CONFIG_QCOM_QSEECOM=y +CONFIG_QCOM_QSEECOM_UEFISECAPP=y +CONFIG_TEGRA_BPMP=y +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +CONFIG_MTD=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_AFS_PARTS=m +CONFIG_MTD_PARSER_TRX=m +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_QCOMSMEM_PARTS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m +CONFIG_FTL=m +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_INFTL=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m +CONFIG_SM_FTL=m +CONFIG_MTD_OOPS=m +CONFIG_MTD_PSTORE=m +CONFIG_MTD_SWAP=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m +CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PHYSMAP_VERSATILE=y +CONFIG_MTD_PHYSMAP_GEMINI=y +CONFIG_MTD_PHYSMAP_GPIO_ADDR=y +CONFIG_MTD_PCI=m +CONFIG_MTD_PLATRAM=m +CONFIG_MTD_PMC551=m +CONFIG_MTD_DATAFLASH=m +CONFIG_MTD_DATAFLASH_OTP=y +CONFIG_MTD_MCHP23K256=m +CONFIG_MTD_MCHP48L640=m +CONFIG_MTD_SST25L=m +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_ONENAND=m +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_ONENAND_GENERIC=m +CONFIG_MTD_ONENAND_2X_PROGRAM=y +CONFIG_MTD_RAW_NAND=m +CONFIG_MTD_NAND_DENALI_PCI=m +CONFIG_MTD_NAND_DENALI_DT=m +CONFIG_MTD_NAND_OMAP2=m +CONFIG_MTD_NAND_OMAP_BCH=y +CONFIG_MTD_NAND_CAFE=m +CONFIG_MTD_NAND_MARVELL=m +CONFIG_MTD_NAND_BRCMNAND=m +CONFIG_MTD_NAND_BRCMNAND_BCM63XX=m +CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m +CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m +CONFIG_MTD_NAND_BRCMNAND_IPROC=m +CONFIG_MTD_NAND_GPMI_NAND=m +CONFIG_MTD_NAND_FSL_IFC=m +CONFIG_MTD_NAND_MXC=m +CONFIG_MTD_NAND_HISI504=m +CONFIG_MTD_NAND_QCOM=m +CONFIG_MTD_NAND_MTK=m +CONFIG_MTD_NAND_MXIC=m +CONFIG_MTD_NAND_TEGRA=m +CONFIG_MTD_NAND_STM32_FMC2=m +CONFIG_MTD_NAND_MESON=m +CONFIG_MTD_NAND_GPIO=m +CONFIG_MTD_NAND_PLATFORM=m +CONFIG_MTD_NAND_CADENCE=m +CONFIG_MTD_NAND_ARASAN=m +CONFIG_MTD_NAND_INTEL_LGM=m +CONFIG_MTD_NAND_ROCKCHIP=m +CONFIG_MTD_NAND_RENESAS=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_NAND_RICOH=m +CONFIG_MTD_NAND_DISKONCHIP=m +CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_NAND_ECC_MEDIATEK=m +CONFIG_MTD_LPDDR=m +CONFIG_SPI_HISI_SFC=m +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_GLUEBI=m +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_NVMEM=m +CONFIG_MTD_HYPERBUS=m +CONFIG_HBMC_AM654=m +CONFIG_PARPORT=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_SERIAL=m +CONFIG_PARPORT_PC_FIFO=y +CONFIG_PARPORT_1284=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m +CONFIG_ZRAM=m +CONFIG_ZRAM_BACKEND_LZ4=y +CONFIG_ZRAM_BACKEND_LZ4HC=y +CONFIG_ZRAM_BACKEND_ZSTD=y +CONFIG_ZRAM_BACKEND_DEFLATE=y +CONFIG_ZRAM_BACKEND_842=y +CONFIG_ZRAM_BACKEND_LZO=y +CONFIG_ZRAM_WRITEBACK=y +CONFIG_ZRAM_MEMORY_TRACKING=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_ATA_OVER_ETH=m +CONFIG_XEN_BLKDEV_BACKEND=m +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_UBLK=m +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m +CONFIG_BLK_DEV_NVME=m +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_RDMA=m +CONFIG_NVME_FC=m +CONFIG_NVME_TCP=m +CONFIG_NVME_TCP_TLS=y +CONFIG_NVME_HOST_AUTH=y +CONFIG_NVME_APPLE=m +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_TCP=m +CONFIG_NVME_TARGET_TCP_TLS=y +CONFIG_NVME_TARGET_AUTH=y +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +CONFIG_AD525X_DPOT_SPI=m +CONFIG_DUMMY_IRQ=m +CONFIG_PHANTOM=m +CONFIG_ICS932S401=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_SMPRO_ERRMON=m +CONFIG_SMPRO_MISC=m +CONFIG_HI6421V600_IRQ=m +CONFIG_HP_ILO=m +CONFIG_QCOM_COINCELL=m +CONFIG_QCOM_FASTRPC=m +CONFIG_APDS9802ALS=m +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1770=m +CONFIG_HMC6352=m +CONFIG_DS1682=m +CONFIG_LATTICE_ECP3_CONFIG=m +CONFIG_DW_XDATA_PCIE=m +CONFIG_XILINX_SDFEC=m +CONFIG_HISI_HIKEY_USB=m +CONFIG_OPEN_DICE=m +CONFIG_NTSYNC=y +CONFIG_VCPU_STALL_DETECTOR=m +CONFIG_NSM=m +CONFIG_MARVELL_CN10K_DPI=m +CONFIG_C2PORT=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_93XX46=m +CONFIG_EEPROM_IDT_89HPESX=m +CONFIG_EEPROM_EE1004=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_VMWARE_VMCI=m +CONFIG_GENWQE=m +CONFIG_BCM_VK=m +CONFIG_BCM_VK_TTY=y +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_UACCE=m +CONFIG_PVPANIC=y +CONFIG_PVPANIC_MMIO=m +CONFIG_PVPANIC_PCI=m +CONFIG_GP_PCI1XXXX=m +CONFIG_KEBA_CP500=m +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_ISCSI_TCP=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 +CONFIG_SCSI_AIC79XX=m +CONFIG_SCSI_AIC94XX=m +CONFIG_SCSI_HISI_SAS=m +CONFIG_SCSI_HISI_SAS_PCI=m +CONFIG_SCSI_MVSAS=m +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_ADVANSYS=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_ESAS2R=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_BUSLOGIC=m +CONFIG_SCSI_FLASHPOINT=y +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +CONFIG_XEN_SCSI_FRONTEND=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_SCSI_SNIC=m +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_PPA=m +CONFIG_SCSI_IMM=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_IPR=m +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_QEDI=m +CONFIG_QEDF=m +CONFIG_SCSI_LPFC=m +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_VIRTIO=y +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_ATA=y +CONFIG_SATA_ZPODD=y +CONFIG_SATA_AHCI=m +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_AHCI_DWC=m +CONFIG_AHCI_IMX=y +CONFIG_AHCI_CEVA=m +CONFIG_AHCI_MTK=m +CONFIG_AHCI_MVEBU=m +CONFIG_AHCI_TEGRA=m +CONFIG_AHCI_XGENE=m +CONFIG_AHCI_QORIQ=m +CONFIG_SATA_AHCI_SEATTLE=m +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_SIL24=m +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_PIIX=m +CONFIG_SATA_DWC=m +CONFIG_SATA_DWC_OLD_DMA=y +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_RCAR=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +CONFIG_PATA_IMX=m +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_RADISYS=m +CONFIG_PATA_RDC=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_OF_PLATFORM=m +CONFIG_PATA_RZ1000=m +CONFIG_PATA_PARPORT=m +CONFIG_PATA_PARPORT_ATEN=m +CONFIG_PATA_PARPORT_BPCK=m +CONFIG_PATA_PARPORT_BPCK6=m +CONFIG_PATA_PARPORT_DSTR=m +CONFIG_PATA_PARPORT_FIT2=m +CONFIG_PATA_PARPORT_FIT3=m +CONFIG_PATA_PARPORT_EPAT=m +CONFIG_PATA_PARPORT_EPATC8=y +CONFIG_PATA_PARPORT_EPIA=m +CONFIG_PATA_PARPORT_FRIQ=m +CONFIG_PATA_PARPORT_FRPW=m +CONFIG_PATA_PARPORT_KBIC=m +CONFIG_PATA_PARPORT_KTTI=m +CONFIG_PATA_PARPORT_ON20=m +CONFIG_PATA_PARPORT_ON26=m +CONFIG_PATA_ACPI=m +CONFIG_ATA_GENERIC=m +CONFIG_PATA_LEGACY=m +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_CLUSTER=m +CONFIG_BCACHE=m +CONFIG_BCACHE_ASYNC_REGISTRATION=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_EBS=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_DELAY=m +CONFIG_DM_INIT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_DM_ZONED=m +CONFIG_DM_VDO=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_SBP_TARGET=m +CONFIG_REMOTE_TARGET=m +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m +CONFIG_FUSION_LOGGING=y +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_FC=y +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_PFCP=m +CONFIG_AMT=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NTB_NETDEV=m +CONFIG_RIONET=m +CONFIG_TUN=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=y +CONFIG_NLMON=m +CONFIG_NETKIT=y +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_MHI_NET=m +CONFIG_ARCNET=m +CONFIG_ARCNET_1201=m +CONFIG_ARCNET_1051=m +CONFIG_ARCNET_RAW=m +CONFIG_ARCNET_CAP=m +CONFIG_ARCNET_COM20020=m +CONFIG_ARCNET_COM20020_PCI=m +CONFIG_ATM_SOLOS=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +CONFIG_NET_DSA_LANTIQ_GSWIP=m +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m +CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m +CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_MSCC_OCELOT_EXT=m +CONFIG_NET_DSA_MSCC_FELIX=m +CONFIG_NET_DSA_MSCC_SEVILLE=m +CONFIG_NET_DSA_AR9331=m +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_NET_DSA_SJA1105_TAS=y +CONFIG_NET_DSA_SJA1105_VL=y +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_DSA_REALTEK=m +CONFIG_NET_DSA_REALTEK_MDIO=y +CONFIG_NET_DSA_REALTEK_SMI=y +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_OWL_EMAC=m +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_ET131X=m +CONFIG_SLICOSS=m +CONFIG_ALTERA_TSE=m +CONFIG_ENA_ETHERNET=m +CONFIG_AMD8111_ETH=m +CONFIG_PCNET32=m +CONFIG_AMD_XGBE=m +CONFIG_AMD_XGBE_DCB=y +CONFIG_PDS_CORE=m +CONFIG_NET_XGENE=m +CONFIG_NET_XGENE_V2=m +CONFIG_AQTION=m +CONFIG_EMAC_ROCKCHIP=m +CONFIG_SPI_AX88796C=m +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +CONFIG_B44=m +CONFIG_BCMGENET=m +CONFIG_TIGON3=m +CONFIG_BNX2X=m +CONFIG_SYSTEMPORT=m +CONFIG_BNXT=m +CONFIG_BNXT_DCB=y +CONFIG_MACB=m +CONFIG_MACB_PCI=m +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_VF=m +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_VF=m +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T4_DCB=y +CONFIG_CHELSIO_T4_FCOE=y +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_ENIC=m +CONFIG_GEMINI_ETHERNET=m +CONFIG_DM9051=m +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_TULIP=m +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_DL2K=m +CONFIG_TSNEP=m +CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m +CONFIG_FEC=y +CONFIG_FSL_FMAN=y +CONFIG_FSL_XGMAC_MDIO=y +CONFIG_GIANFAR=m +CONFIG_FSL_DPAA_ETH=m +CONFIG_FSL_DPAA2_ETH=m +CONFIG_FSL_DPAA2_ETH_DCB=y +CONFIG_FSL_DPAA2_SWITCH=m +CONFIG_FSL_ENETC=m +CONFIG_FSL_ENETC_VF=m +CONFIG_FSL_ENETC_QOS=y +CONFIG_FUN_ETH=m +CONFIG_GVE=m +CONFIG_HIX5HD2_GMAC=m +CONFIG_HISI_FEMAC=m +CONFIG_HIP04_ETH=m +CONFIG_HI13X1_GMAC=y +CONFIG_HNS_DSAF=m +CONFIG_HNS_ENET=m +CONFIG_HNS3=m +CONFIG_HNS3_DCB=y +CONFIG_HNS3_HCLGEVF=m +CONFIG_HINIC=m +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IXGBE=m +CONFIG_IXGBE_DCB=y +CONFIG_IXGBEVF=m +CONFIG_I40E=m +CONFIG_I40E_DCB=y +CONFIG_I40EVF=m +CONFIG_ICE=m +CONFIG_FM10K=m +CONFIG_IGC=m +CONFIG_IDPF=m +CONFIG_JME=m +CONFIG_ADIN1110=m +CONFIG_LITEX_LITEETH=m +CONFIG_MVNETA=m +CONFIG_MVPP2=m +CONFIG_MVPP2_PTP=y +CONFIG_PXA168_ETH=m +CONFIG_SKGE=m +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +CONFIG_OCTEONTX2_AF=m +CONFIG_NDC_DIS_DYNAMIC_CACHING=y +CONFIG_OCTEONTX2_PF=m +CONFIG_OCTEONTX2_VF=m +CONFIG_OCTEON_EP=m +CONFIG_OCTEON_EP_VF=m +CONFIG_PRESTERA=m +CONFIG_MLX4_EN=m +CONFIG_MLX5_CORE=m +CONFIG_MLX5_FPGA=y +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_IPOIB=y +CONFIG_MLX5_MACSEC=y +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_TLS=y +CONFIG_MLX5_SF=y +CONFIG_MLX5_DPLL=m +CONFIG_MLXSW_CORE=m +CONFIG_MLXBF_GIGE=m +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_KSZ884X_PCI=m +CONFIG_ENC28J60=m +CONFIG_ENCX24J600=m +CONFIG_LAN743X=m +CONFIG_LAN966X_SWITCH=m +CONFIG_SPARX5_SWITCH=m +CONFIG_MSCC_OCELOT_SWITCH=m +CONFIG_MYRI10GE=m +CONFIG_FEALNX=m +CONFIG_NI_XGE_MANAGEMENT_ENET=m +CONFIG_NATSEMI=m +CONFIG_NS83820=m +CONFIG_NFP=m +CONFIG_NE2K_PCI=m +CONFIG_FORCEDETH=m +CONFIG_ETHOC=m +CONFIG_IONIC=m +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_NETXEN_NIC=m +CONFIG_QED=m +CONFIG_QEDE=m +CONFIG_BNA=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_R6040=m +CONFIG_8139CP=m +CONFIG_8139TOO=m +CONFIG_8139TOO_8129=y +CONFIG_R8169=m +CONFIG_R8169_LEDS=y +CONFIG_SH_ETH=m +CONFIG_RAVB=m +CONFIG_RENESAS_ETHER_SWITCH=m +CONFIG_RTSN=m +CONFIG_ROCKER=m +CONFIG_SXGBE_ETH=m +CONFIG_SC92031=m +CONFIG_SIS900=m +CONFIG_SIS190=m +CONFIG_SFC=m +CONFIG_SFC_FALCON=m +CONFIG_SFC_SIENA=m +CONFIG_SFC_SIENA_SRIOV=y +CONFIG_SMC91X=y +CONFIG_EPIC100=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_SNI_NETSEC=m +CONFIG_STMMAC_ETH=m +CONFIG_DWMAC_DWC_QOS_ETH=m +CONFIG_DWMAC_MEDIATEK=m +CONFIG_DWMAC_INTEL_PLAT=m +CONFIG_DWMAC_TEGRA=m +CONFIG_STMMAC_PCI=m +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NIU=m +CONFIG_DWC_XLGMAC=m +CONFIG_DWC_XLGMAC_PCI=m +CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m +CONFIG_TI_DAVINCI_MDIO=y +CONFIG_TI_K3_AM65_CPSW_NUSS=m +CONFIG_TI_K3_AM65_CPSW_SWITCHDEV=y +CONFIG_TI_K3_AM65_CPTS=m +CONFIG_TI_AM65_CPSW_QOS=y +CONFIG_TLAN=m +CONFIG_TI_ICSSG_PRUETH=m +CONFIG_TI_ICSSG_PRUETH_SR1=m +CONFIG_MSE102X=m +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_NGBE=m +CONFIG_TXGBE=m +CONFIG_WIZNET_W5100=m +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_AXI_EMAC=m +CONFIG_XILINX_LL_TEMAC=m +CONFIG_FDDI=y +CONFIG_DEFXX=m +CONFIG_SKFP=m +CONFIG_QCOM_IPA=m +CONFIG_LED_TRIGGER_PHY=y +CONFIG_AIR_EN8811H_PHY=m +CONFIG_AMD_PHY=m +CONFIG_MESON_GXL_PHY=m +CONFIG_ADIN_PHY=m +CONFIG_ADIN1100_PHY=m +CONFIG_AQUANTIA_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_BCM84881_PHY=y +CONFIG_BCM87XX_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_CORTINA_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_LXT_PHY=m +CONFIG_INTEL_XWAY_PHY=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MARVELL_88Q2XXX_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MICROCHIP_T1S_PHY=m +CONFIG_MICROCHIP_T1_PHY=m +CONFIG_MICROSEMI_PHY=m +CONFIG_MOTORCOMM_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_NXP_CBTX_PHY=m +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_TJA11XX_PHY=m +CONFIG_NCN26000_PHY=m +CONFIG_AT803X_PHY=y +CONFIG_QCA83XX_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA807X_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_REALTEK_PHY_HWMON=y +CONFIG_RENESAS_PHY=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_STE10XP=m +CONFIG_TERANETICS_PHY=m +CONFIG_DP83822_PHY=m +CONFIG_DP83TC811_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +CONFIG_DP83TD510_PHY=m +CONFIG_DP83TG720_PHY=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_PSE_CONTROLLER=y +CONFIG_PSE_REGULATOR=m +CONFIG_PSE_PD692X0=m +CONFIG_PSE_TPS23881=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_BXCAN=m +CONFIG_CAN_CAN327=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_GRCAN=m +CONFIG_CAN_JANZ_ICAN3=m +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_XILINXCAN=m +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PLATFORM=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_CC770=m +CONFIG_CAN_CC770_PLATFORM=m +CONFIG_CAN_CTUCANFD_PCI=m +CONFIG_CAN_CTUCANFD_PLATFORM=m +CONFIG_CAN_ESD_402_PCI=m +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_RCAR=m +CONFIG_CAN_RCAR_CANFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_F81601=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SOFTING=m +CONFIG_CAN_HI311X=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_F81604=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +CONFIG_MCTP_SERIAL=m +CONFIG_MCTP_TRANSPORT_I2C=m +CONFIG_MCTP_TRANSPORT_I3C=m +CONFIG_MDIO_GPIO=m +CONFIG_MDIO_HISI_FEMAC=m +CONFIG_MDIO_MVUSB=m +CONFIG_MDIO_OCTEON=m +CONFIG_MDIO_IPQ4019=m +CONFIG_MDIO_IPQ8064=m +CONFIG_MDIO_BUS_MUX_GPIO=m +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m +CONFIG_MDIO_BUS_MUX_MMIOREG=m +CONFIG_PLIP=m +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +CONFIG_ADM8211=m +CONFIG_ATH5K=m +CONFIG_ATH9K=m +CONFIG_ATH9K_AHB=y +CONFIG_ATH9K_DEBUGFS=y +CONFIG_ATH9K_STATION_STATISTICS=y +CONFIG_ATH9K_WOW=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_HTC=m +CONFIG_ATH9K_HTC_DEBUGFS=y +CONFIG_ATH9K_HWRNG=y +CONFIG_ATH9K_COMMON_SPECTRAL=y +CONFIG_CARL9170=m +CONFIG_CARL9170_HWRNG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_WIL6210_TRACING=y +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_AHB=y +CONFIG_ATH10K_SDIO=m +CONFIG_ATH10K_USB=m +CONFIG_ATH10K_SNOC=m +CONFIG_ATH10K_DEBUGFS=y +CONFIG_ATH10K_SPECTRAL=y +CONFIG_ATH10K_TRACING=y +CONFIG_WCN36XX=m +CONFIG_ATH11K=m +CONFIG_ATH11K_AHB=m +CONFIG_ATH11K_PCI=m +CONFIG_ATH11K_DEBUGFS=y +CONFIG_ATH11K_TRACING=y +CONFIG_ATH11K_SPECTRAL=y +CONFIG_ATH12K=m +CONFIG_ATH12K_AHB=y +CONFIG_ATH12K_DEBUGFS=y +CONFIG_ATH12K_TRACING=y +CONFIG_AT76C50X_USB=m +CONFIG_B43=m +CONFIG_B43LEGACY=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +CONFIG_BRCM_TRACING=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IWL4965=m +CONFIG_IWL3945=m +CONFIG_IWLEGACY_DEBUGFS=y +CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_DEBUGFS=y +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +CONFIG_P54_SPI=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x0E=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7603E=m +CONFIG_MT7615E=m +CONFIG_MT7663U=m +CONFIG_MT7663S=m +CONFIG_MT7915E=m +CONFIG_MT798X_WMAC=y +CONFIG_MT7921E=m +CONFIG_MT7921S=m +CONFIG_MT7921U=m +CONFIG_MT7996E=m +CONFIG_MT7925E=m +CONFIG_MT7925U=m +CONFIG_WILC1000_SDIO=m +CONFIG_WILC1000_SPI=m +CONFIG_WILC1000_HW_OOB_INTR=y +CONFIG_PLFXLC=m +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +CONFIG_RTL8192DU=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DS=m +CONFIG_RTW88_8723CS=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +CONFIG_RTW88_8821AU=m +CONFIG_RTW88_8812AU=m +CONFIG_RTW88_DEBUG=y +CONFIG_RTW88_DEBUGFS=y +CONFIG_RTW89=m +CONFIG_RTW89_8851BE=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852BU=m +CONFIG_RTW89_8852CE=m +CONFIG_RTW89_8922AE=m +CONFIG_RTW89_DEBUGMSG=y +CONFIG_RTW89_DEBUGFS=y +CONFIG_RSI_91X=m +CONFIG_WFX=m +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +CONFIG_CW1200_WLAN_SPI=m +CONFIG_WL1251=m +CONFIG_WL1251_SPI=m +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE_SPI=m +CONFIG_WLCORE_SDIO=m +CONFIG_ZD1211RW=m +CONFIG_QTNFMAC_PCIE=m +CONFIG_MAC80211_HWSIM=m +CONFIG_VIRT_WIFI=m +CONFIG_WAN=y +CONFIG_HDLC=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_X25=m +CONFIG_FRAMER=m +CONFIG_FRAMER_PEF2256=m +CONFIG_PCI200SYN=m +CONFIG_WANXL=m +CONFIG_PC300TOO=m +CONFIG_FARSYNC=m +CONFIG_FSL_UCC_HDLC=m +CONFIG_SLIC_DS26522=m +CONFIG_LAPBETHER=m +CONFIG_IEEE802154_FAKELB=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_IEEE802154_ATUSB=m +CONFIG_IEEE802154_ADF7242=m +CONFIG_IEEE802154_CA8210=m +CONFIG_IEEE802154_CA8210_DEBUGFS=y +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_HWSIM=m +CONFIG_WWAN=m +CONFIG_WWAN_HWSIM=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +CONFIG_QCOM_BAM_DMUX=m +CONFIG_RPMSG_WWAN_CTRL=m +CONFIG_IOSM=m +CONFIG_MTK_T7XX=m +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_VMXNET3=m +CONFIG_FUJITSU_ES=m +CONFIG_USB4_NET=m +CONFIG_NETDEVSIM=m +CONFIG_INPUT_LEDS=m +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_ADP5520=m +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_DLINK_DIR685=m +CONFIG_KEYBOARD_LKKBD=m +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_SNVS_PWRKEY=m +CONFIG_KEYBOARD_IMX=m +CONFIG_KEYBOARD_IMX_SC_KEY=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_TEGRA=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_PINEPHONE=m +CONFIG_KEYBOARD_SAMSUNG=m +CONFIG_KEYBOARD_STOWAWAY=m +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_STMPE=m +CONFIG_KEYBOARD_IQS62X=m +CONFIG_KEYBOARD_OMAP4=m +CONFIG_KEYBOARD_TC3589X=m +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +CONFIG_KEYBOARD_TWL4030=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_CROS_EC=m +CONFIG_KEYBOARD_CAP11XX=m +CONFIG_KEYBOARD_BCM=m +CONFIG_KEYBOARD_MT6779=m +CONFIG_KEYBOARD_MTK_PMIC=m +CONFIG_KEYBOARD_CYPRESS_SF=m +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_SENSEHAT=m +CONFIG_JOYSTICK_SEESAW=m +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_88PM860X=m +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_AD7877=m +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +CONFIG_TOUCHSCREEN_AD7879_SPI=m +CONFIG_TOUCHSCREEN_ADC=m +CONFIG_TOUCHSCREEN_APPLE_Z2=y +CONFIG_TOUCHSCREEN_AR1021_I2C=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_BU21029=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +CONFIG_TOUCHSCREEN_CYTTSP_SPI=m +CONFIG_TOUCHSCREEN_CYTTSP5=m +CONFIG_TOUCHSCREEN_DA9034=m +CONFIG_TOUCHSCREEN_DA9052=m +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C=m +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI=m +CONFIG_TOUCHSCREEN_HIDEEP=m +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_S6SY761=m +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MELFAS_MIP4=m +CONFIG_TOUCHSCREEN_MSG2638=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m +CONFIG_TOUCHSCREEN_IMAGIS=m +CONFIG_TOUCHSCREEN_IMX6UL_TSC=m +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM831X=m +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_MC13783=m +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC2004=m +CONFIG_TOUCHSCREEN_TSC2005=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_STMFTS=m +CONFIG_TOUCHSCREEN_STMPE=m +CONFIG_TOUCHSCREEN_SUR40=m +CONFIG_TOUCHSCREEN_SURFACE3_SPI=m +CONFIG_TOUCHSCREEN_SX8654=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_IQS7211=m +CONFIG_TOUCHSCREEN_ZINITIX=m +CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m +CONFIG_TOUCHSCREEN_MSHW0485=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_88PM860X_ONKEY=m +CONFIG_INPUT_88PM80X_ONKEY=m +CONFIG_INPUT_88PM886_ONKEY=m +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ARIZONA_HAPTICS=m +CONFIG_INPUT_ATC260X_ONKEY=m +CONFIG_INPUT_ATMEL_CAPTOUCH=m +CONFIG_INPUT_BBNSM_PWRKEY=m +CONFIG_INPUT_BMA150=m +CONFIG_INPUT_CS40L50_VIBRA=m +CONFIG_INPUT_E3X0_BUTTON=m +CONFIG_INPUT_PM8941_PWRKEY=m +CONFIG_INPUT_PM8XXX_VIBRATOR=m +CONFIG_INPUT_MAX77650_ONKEY=m +CONFIG_INPUT_MAX77693_HAPTIC=m +CONFIG_INPUT_MAX8925_ONKEY=m +CONFIG_INPUT_MAX8997_HAPTIC=m +CONFIG_INPUT_MC13783_PWRBUTTON=m +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_GPIO_BEEPER=m +CONFIG_INPUT_GPIO_DECODER=m +CONFIG_INPUT_GPIO_VIBRA=m +CONFIG_INPUT_CPCAP_PWRBUTTON=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_RETU_PWRBUTTON=m +CONFIG_INPUT_TPS65218_PWRBUTTON=m +CONFIG_INPUT_TPS65219_PWRBUTTON=m +CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_TWL4030_PWRBUTTON=m +CONFIG_INPUT_TWL4030_VIBRA=m +CONFIG_INPUT_TWL6040_VIBRA=m +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_PALMAS_PWRBUTTON=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_RK805_PWRKEY=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_DA7280_HAPTICS=m +CONFIG_INPUT_DA9052_ONKEY=m +CONFIG_INPUT_DA9055_ONKEY=m +CONFIG_INPUT_DA9063_ONKEY=m +CONFIG_INPUT_WM831X_ON=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_IBM_PANEL=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +CONFIG_INPUT_IQS7222=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_XEN_KBDDEV_FRONTEND=m +CONFIG_INPUT_SOC_BUTTON_ARRAY=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2665_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_INPUT_HISI_POWERKEY=m +CONFIG_INPUT_RAVE_SP_PWRBUTTON=m +CONFIG_INPUT_SC27XX_VIBRA=m +CONFIG_INPUT_RT5120_PWRKEY=m +CONFIG_INPUT_STPMIC1_ONKEY=m +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SPI=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_F34=y +CONFIG_RMI4_F54=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_PARKBD=m +CONFIG_SERIO_AMBAKMI=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_PS2MULT=m +CONFIG_SERIO_ARC_PS2=m +CONFIG_SERIO_APBPS2=m +CONFIG_SERIO_GPIO_PS2=m +CONFIG_USERIO=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +CONFIG_LEGACY_PTY_COUNT=0 +# CONFIG_LEGACY_TIOCSTI is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_FINTEK=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXAR=m +CONFIG_SERIAL_8250_MEN_MCB=m +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_PCI1XXXX=m +CONFIG_SERIAL_8250_DFL=m +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_8250_OMAP=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_PERICOM=m +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL010=m +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_EARLYCON_SEMIHOST=y +CONFIG_SERIAL_MESON=y +CONFIG_SERIAL_MESON_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=m +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_TEGRA=m +CONFIG_SERIAL_TEGRA_TCU=y +CONFIG_SERIAL_MAX3100=m +CONFIG_SERIAL_MAX310X=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_UARTLITE=m +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=2 +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_QCOM_GENI=m +CONFIG_SERIAL_QCOM_GENI_CONSOLE=y +CONFIG_SERIAL_SIFIVE=m +CONFIG_SERIAL_QE=m +CONFIG_SERIAL_SCCNXP=y +CONFIG_SERIAL_SCCNXP_CONSOLE=y +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_ALTERA_JTAGUART=m +CONFIG_SERIAL_ALTERA_UART=m +CONFIG_SERIAL_XILINX_PS_UART=m +CONFIG_SERIAL_ARC=m +CONFIG_SERIAL_RP2=m +CONFIG_SERIAL_FSL_LPUART=m +CONFIG_SERIAL_FSL_LINFLEXUART=m +CONFIG_SERIAL_CONEXANT_DIGICOLOR=m +CONFIG_SERIAL_MEN_Z135=m +CONFIG_SERIAL_SPRD=m +CONFIG_SERIAL_STM32=m +CONFIG_SERIAL_MVEBU_UART=y +CONFIG_SERIAL_OWL=y +CONFIG_SERIAL_LITEUART=m +CONFIG_SERIAL_NUVOTON_MA35D1=m +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_MOXA_INTELLIO=m +CONFIG_MOXA_SMARTIO=m +CONFIG_N_HDLC=m +CONFIG_N_GSM=m +CONFIG_NOZOMI=m +CONFIG_NULL_TTY=m +CONFIG_RPMSG_TTY=m +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_PRINTER=m +CONFIG_PPDEV=m +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_IPMB=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_NPCM7XX_KCS_IPMI_BMC=m +CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m +CONFIG_IPMI_KCS_BMC_SERIO=m +CONFIG_SSIF_IPMI_BMC=m +CONFIG_IPMB_DEVICE_INTERFACE=m +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_BA431=m +CONFIG_HW_RANDOM_OMAP=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_HISI=m +CONFIG_HW_RANDOM_HISTB=m +CONFIG_HW_RANDOM_XGENE=m +CONFIG_HW_RANDOM_STM32=m +CONFIG_HW_RANDOM_MESON=m +CONFIG_HW_RANDOM_CAVIUM=m +CONFIG_HW_RANDOM_MTK=m +CONFIG_HW_RANDOM_NPCM=m +CONFIG_HW_RANDOM_CCTRNG=m +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m +CONFIG_HW_RANDOM_CN10K=m +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_SPI=y +CONFIG_TCG_TIS_SPI_CR50=y +CONFIG_TCG_TIS_I2C=m +CONFIG_TCG_TIS_SYNQUACER=m +CONFIG_TCG_TIS_I2C_CR50=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_ATMEL=m +CONFIG_TCG_INFINEON=m +CONFIG_TCG_XEN=m +CONFIG_TCG_VTPM_PROXY=m +CONFIG_TCG_FTPM_TEE=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYBUS_OF=m +CONFIG_XILLYUSB=m +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=m +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_DEMUX_PINCTRL=m +CONFIG_I2C_MUX_MLXCPLD=m +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_HIX5HD2=m +CONFIG_I2C_I801=m +CONFIG_I2C_ISCH=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +CONFIG_I2C_VIA=m +CONFIG_I2C_VIAPRO=m +CONFIG_I2C_ZHAOXIN=m +CONFIG_I2C_SCMI=m +CONFIG_I2C_ALTERA=m +CONFIG_I2C_CBUS_GPIO=m +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_GPIO=m +CONFIG_I2C_HISI=m +CONFIG_I2C_IMX=m +CONFIG_I2C_IMX_LPI2C=m +CONFIG_I2C_KEMPLD=m +CONFIG_I2C_MLXBF=m +CONFIG_I2C_MESON=m +CONFIG_I2C_MT65XX=m +CONFIG_I2C_MT7621=m +CONFIG_I2C_MV64XXX=m +CONFIG_I2C_NOMADIK=m +CONFIG_I2C_NPCM=m +CONFIG_I2C_OCORES=m +CONFIG_I2C_OMAP=y +CONFIG_I2C_OWL=m +CONFIG_I2C_APPLE=m +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_PXA=m +CONFIG_I2C_PXA_SLAVE=y +CONFIG_I2C_QCOM_CCI=m +CONFIG_I2C_QCOM_GENI=m +CONFIG_I2C_QUP=m +CONFIG_I2C_RIIC=m +CONFIG_I2C_RK3X=m +CONFIG_I2C_RZV2M=m +CONFIG_I2C_SH_MOBILE=m +CONFIG_I2C_SIMTEC=m +CONFIG_I2C_SPRD=y +CONFIG_I2C_STM32F4=m +CONFIG_I2C_STM32F7=m +CONFIG_I2C_SYNQUACER=m +CONFIG_I2C_TEGRA=m +CONFIG_I2C_TEGRA_BPMP=m +CONFIG_I2C_VERSATILE=m +CONFIG_I2C_THUNDERX=m +CONFIG_I2C_XLP9XX=m +CONFIG_I2C_RCAR=m +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +CONFIG_I2C_CP2615=m +CONFIG_I2C_PARPORT=m +CONFIG_I2C_PCI1XXXX=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIPERBOARD=m +CONFIG_I2C_MLXCPLD=m +CONFIG_I2C_CROS_EC_TUNNEL=m +CONFIG_I2C_XGENE_SLIMPRO=m +CONFIG_I2C_FSI=m +CONFIG_I2C_VIRTIO=m +CONFIG_I2C_STUB=m +CONFIG_I2C_SLAVE_EEPROM=m +CONFIG_I3C=m +CONFIG_CDNS_I3C_MASTER=m +CONFIG_DW_I3C_MASTER=m +CONFIG_SVC_I3C_MASTER=m +CONFIG_MIPI_I3C_HCI=m +CONFIG_SPI=y +CONFIG_SPI_AIROHA_SNFI=m +CONFIG_SPI_ALTERA=m +CONFIG_SPI_ALTERA_DFL=m +CONFIG_SPI_AMLOGIC_SPIFC_A1=m +CONFIG_SPI_APPLE=m +CONFIG_SPI_ARMADA_3700=m +CONFIG_SPI_AXI_SPI_ENGINE=m +CONFIG_SPI_BUTTERFLY=m +CONFIG_SPI_CADENCE=m +CONFIG_SPI_CADENCE_QUADSPI=m +CONFIG_SPI_CADENCE_XSPI=m +CONFIG_SPI_CH341=m +CONFIG_SPI_CS42L43=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_DLN2=m +CONFIG_SPI_FSI=m +CONFIG_SPI_FSL_LPSPI=m +CONFIG_SPI_FSL_QUADSPI=m +CONFIG_SPI_HISI_KUNPENG=m +CONFIG_SPI_HISI_SFC_V3XX=m +CONFIG_SPI_NXP_FLEXSPI=m +CONFIG_SPI_GPIO=m +CONFIG_SPI_IMX=m +CONFIG_SPI_LM70_LLP=m +CONFIG_SPI_FSL_SPI=y +CONFIG_SPI_FSL_DSPI=m +CONFIG_SPI_MESON_SPICC=m +CONFIG_SPI_MESON_SPIFC=m +CONFIG_SPI_MICROCHIP_CORE_QSPI=m +CONFIG_SPI_MT65XX=m +CONFIG_SPI_MTK_NOR=m +CONFIG_SPI_MTK_SNFI=m +CONFIG_SPI_WPCM_FIU=m +CONFIG_SPI_NPCM_FIU=m +CONFIG_SPI_NPCM_PSPI=m +CONFIG_SPI_OC_TINY=m +CONFIG_SPI_OMAP24XX=y +CONFIG_SPI_ORION=m +CONFIG_SPI_PCI1XXXX=m +CONFIG_SPI_PL022=m +CONFIG_SPI_ROCKCHIP=m +CONFIG_SPI_ROCKCHIP_SFC=m +CONFIG_SPI_RPCIF=m +CONFIG_SPI_RSPI=m +CONFIG_SPI_RZV2M_CSI=m +CONFIG_SPI_QCOM_QSPI=m +CONFIG_SPI_QUP=m +CONFIG_SPI_QCOM_GENI=m +CONFIG_SPI_SC18IS602=m +CONFIG_SPI_SH_MSIOF=m +CONFIG_SPI_SH_HSPI=m +CONFIG_SPI_SIFIVE=m +CONFIG_SPI_SLAVE_MT27XX=m +CONFIG_SPI_SN_F_OSPI=m +CONFIG_SPI_SPRD=m +CONFIG_SPI_SPRD_ADI=m +CONFIG_SPI_STM32=m +CONFIG_SPI_STM32_QSPI=m +CONFIG_SPI_SUN6I=m +CONFIG_SPI_SYNQUACER=m +CONFIG_SPI_MXIC=m +CONFIG_SPI_TEGRA210_QUAD=y +CONFIG_SPI_TEGRA114=m +CONFIG_SPI_TEGRA20_SFLASH=m +CONFIG_SPI_TEGRA20_SLINK=m +CONFIG_SPI_THUNDERX=m +CONFIG_SPI_XCOMM=m +CONFIG_SPI_XLP=m +CONFIG_SPI_ZYNQMP_GQSPI=m +CONFIG_SPI_AMD=m +CONFIG_SPI_MUX=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_LOOPBACK_TEST=m +CONFIG_SPI_TLE62X0=m +CONFIG_SPI_SLAVE_TIME=m +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m +CONFIG_SPMI=y +CONFIG_SPMI_MTK_PMIF=y +CONFIG_HSI=m +CONFIG_HSI_CHAR=m +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_DP83640_PHY=m +CONFIG_PTP_1588_CLOCK_INES=m +CONFIG_PTP_1588_CLOCK_KVM=m +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +CONFIG_PTP_1588_CLOCK_FC3W=m +CONFIG_PTP_1588_CLOCK_MOCK=m +CONFIG_PTP_1588_CLOCK_OCP=m +CONFIG_PTP_DFL_TOD=m +CONFIG_PINCTRL_AMD=y +CONFIG_PINCTRL_APPLE_GPIO=m +CONFIG_PINCTRL_AS3722=y +CONFIG_PINCTRL_AXP209=m +CONFIG_PINCTRL_AW9523=m +CONFIG_PINCTRL_CY8C95X0=m +CONFIG_PINCTRL_DA9062=m +CONFIG_PINCTRL_KEEMBAY=m +CONFIG_PINCTRL_MAX77620=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_MICROCHIP_SGPIO=y +CONFIG_PINCTRL_OCELOT=y +CONFIG_PINCTRL_PALMAS=y +CONFIG_PINCTRL_PEF2256=m +CONFIG_PINCTRL_RK805=m +CONFIG_PINCTRL_SCMI=m +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_STMFX=m +CONFIG_PINCTRL_SX150X=y +CONFIG_PINCTRL_ZYNQMP=m +CONFIG_PINCTRL_MLXBF3=m +CONFIG_PINCTRL_OWL=y +CONFIG_PINCTRL_S700=y +CONFIG_PINCTRL_S900=y +CONFIG_PINCTRL_AS370=y +CONFIG_PINCTRL_BERLIN_BG4CT=y +CONFIG_PINCTRL_CS42L43=m +CONFIG_PINCTRL_LOCHNAGAR=m +CONFIG_PINCTRL_IMX_SCMI=m +CONFIG_PINCTRL_IMX8ULP=m +CONFIG_PINCTRL_IMX91=m +CONFIG_PINCTRL_MT6779=m +CONFIG_PINCTRL_MESON_S4=m +CONFIG_PINCTRL_AMLOGIC_C3=m +CONFIG_PINCTRL_AMLOGIC_T7=m +CONFIG_PINCTRL_NPCM8XX=m +CONFIG_PINCTRL_MA35D1=y +CONFIG_PINCTRL_S32G2=y +# CONFIG_PINCTRL_ELIZA is not set +# CONFIG_PINCTRL_GLYMUR is not set +# CONFIG_PINCTRL_HAWI is not set +CONFIG_PINCTRL_IPQ5018=m +# CONFIG_PINCTRL_IPQ5210 is not set +CONFIG_PINCTRL_IPQ5332=m +CONFIG_PINCTRL_IPQ5424=m +CONFIG_PINCTRL_IPQ8074=m +CONFIG_PINCTRL_IPQ6018=m +CONFIG_PINCTRL_IPQ9574=m +# CONFIG_PINCTRL_KAANAPALI is not set +CONFIG_PINCTRL_MDM9607=m +CONFIG_PINCTRL_MSM8916=m +CONFIG_PINCTRL_MSM8953=m +CONFIG_PINCTRL_MSM8976=m +CONFIG_PINCTRL_MSM8994=m +CONFIG_PINCTRL_MSM8996=m +CONFIG_PINCTRL_MSM8998=m +CONFIG_PINCTRL_QCM2290=m +CONFIG_PINCTRL_QCS404=m +CONFIG_PINCTRL_QCS615=m +CONFIG_PINCTRL_QCS8300=m +CONFIG_PINCTRL_QDF2XXX=m +CONFIG_PINCTRL_QDU1000=m +CONFIG_PINCTRL_SA8775P=m +CONFIG_PINCTRL_SAR2130P=m +CONFIG_PINCTRL_SC7180=m +CONFIG_PINCTRL_SC7280=m +CONFIG_PINCTRL_SC8180X=m +CONFIG_PINCTRL_SC8280XP=m +CONFIG_PINCTRL_SDM660=m +CONFIG_PINCTRL_SDM670=m +CONFIG_PINCTRL_SDM845=m +CONFIG_PINCTRL_SDX75=m +CONFIG_PINCTRL_SM4450=m +CONFIG_PINCTRL_SM6115=m +CONFIG_PINCTRL_SM6125=m +CONFIG_PINCTRL_SM6350=m +CONFIG_PINCTRL_SM6375=m +CONFIG_PINCTRL_SM7150=m +# CONFIG_PINCTRL_MILOS is not set +CONFIG_PINCTRL_SM8150=m +CONFIG_PINCTRL_SM8250=m +CONFIG_PINCTRL_SM8350=m +CONFIG_PINCTRL_SM8450=m +CONFIG_PINCTRL_SM8550=m +CONFIG_PINCTRL_SM8650=m +CONFIG_PINCTRL_SM8750=m +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_QCOM_SSBI_PMIC=m +CONFIG_PINCTRL_LPASS_LPI=m +CONFIG_PINCTRL_SC7280_LPASS_LPI=m +CONFIG_PINCTRL_SM4250_LPASS_LPI=m +CONFIG_PINCTRL_SM6115_LPASS_LPI=m +CONFIG_PINCTRL_SM8250_LPASS_LPI=m +CONFIG_PINCTRL_SM8450_LPASS_LPI=m +CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m +CONFIG_PINCTRL_SM8550_LPASS_LPI=m +CONFIG_PINCTRL_SM8650_LPASS_LPI=m +CONFIG_PINCTRL_RTD=m +CONFIG_PINCTRL_SPRD_SC9860=y +CONFIG_PINCTRL_SUN4I_A10=y +CONFIG_PINCTRL_SUN5I=y +CONFIG_PINCTRL_SUN6I_A31=y +CONFIG_PINCTRL_SUN6I_A31_R=y +CONFIG_PINCTRL_SUN8I_A23=y +CONFIG_PINCTRL_SUN8I_A33=y +CONFIG_PINCTRL_SUN8I_A83T=y +CONFIG_PINCTRL_SUN8I_A83T_R=y +CONFIG_PINCTRL_SUN8I_A23_R=y +CONFIG_PINCTRL_SUN8I_H3=y +CONFIG_PINCTRL_SUN8I_V3S=y +CONFIG_PINCTRL_SUN9I_A80=y +CONFIG_PINCTRL_SUN9I_A80_R=y +CONFIG_PINCTRL_SUN20I_D1=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_74XX_MMIO=m +CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_AMDPT=m +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_DAVINCI=y +CONFIG_GPIO_DWAPB=m +CONFIG_GPIO_EIC_SPRD=m +CONFIG_GPIO_EN7523=m +CONFIG_GPIO_EXAR=m +CONFIG_GPIO_FTGPIO010=y +CONFIG_GPIO_GRGPIO=m +CONFIG_GPIO_HISI=m +CONFIG_GPIO_HLWD=m +CONFIG_GPIO_LOGICVC=m +CONFIG_GPIO_MB86S7X=m +CONFIG_GPIO_MENZ127=m +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_NPCM_SGPIO=y +CONFIG_GPIO_PL061=y +CONFIG_GPIO_RCAR=m +CONFIG_GPIO_ROCKCHIP=m +CONFIG_GPIO_RTD=m +CONFIG_GPIO_SIFIVE=y +CONFIG_GPIO_SIOX=m +CONFIG_GPIO_SPRD=m +CONFIG_GPIO_SYSCON=m +CONFIG_GPIO_THUNDERX=m +CONFIG_GPIO_VF610=y +CONFIG_GPIO_VISCONTI=m +CONFIG_GPIO_WCD934X=m +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_XGENE_SB=m +CONFIG_GPIO_XILINX=y +CONFIG_GPIO_XLP=m +CONFIG_GPIO_ZYNQ=m +CONFIG_GPIO_ZYNQMP_MODEPIN=m +CONFIG_GPIO_AMD_FCH=m +CONFIG_GPIO_ADNP=m +CONFIG_GPIO_FXL6408=m +CONFIG_GPIO_DS4520=m +CONFIG_GPIO_GW_PLD=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCA9570=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_TPIC2810=m +CONFIG_GPIO_ADP5520=m +CONFIG_GPIO_ALTERA_A10SR=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_BD71815=m +CONFIG_GPIO_BD71828=m +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_CROS_EC=m +CONFIG_GPIO_DA9052=m +CONFIG_GPIO_DA9055=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_JANZ_TTL=m +CONFIG_GPIO_KEMPLD=m +CONFIG_GPIO_LP3943=m +CONFIG_GPIO_LP873X=m +CONFIG_GPIO_LP87565=m +CONFIG_GPIO_MADERA=m +CONFIG_GPIO_MAX77620=m +CONFIG_GPIO_MAX77650=m +CONFIG_GPIO_PALMAS=y +CONFIG_GPIO_PMIC_EIC_SPRD=m +CONFIG_GPIO_RC5T583=y +CONFIG_GPIO_SL28CPLD=m +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_TC3589X=y +CONFIG_GPIO_TPS65086=m +CONFIG_GPIO_TPS65218=m +CONFIG_GPIO_TPS6586X=y +CONFIG_GPIO_TPS65910=y +CONFIG_GPIO_TPS65912=m +CONFIG_GPIO_TQMX86=m +CONFIG_GPIO_TWL4030=m +CONFIG_GPIO_TWL6040=m +CONFIG_GPIO_WM831X=m +CONFIG_GPIO_WM8350=m +CONFIG_GPIO_WM8994=m +CONFIG_GPIO_MLXBF=m +CONFIG_GPIO_MLXBF2=m +CONFIG_GPIO_MLXBF3=m +CONFIG_GPIO_PCI_IDIO_16=m +CONFIG_GPIO_PCIE_IDIO_24=m +CONFIG_GPIO_RDC321X=m +CONFIG_GPIO_74X164=m +CONFIG_GPIO_MAX3191X=m +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MC33880=m +CONFIG_GPIO_PISOSR=m +CONFIG_GPIO_XRA1403=m +CONFIG_GPIO_MOXTET=m +CONFIG_GPIO_VIPERBOARD=m +CONFIG_GPIO_AGGREGATOR=m +CONFIG_GPIO_LATCH=m +CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_SIM=m +CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER=m +CONFIG_GPIO_VIRTUSER=m +CONFIG_W1_MASTER_AMD_AXI=m +CONFIG_W1_MASTER_MATROX=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_MXC=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_MASTER_SGI=m +CONFIG_W1_MASTER_UART=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS250X=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +CONFIG_POWER_RESET_AS3722=y +CONFIG_POWER_RESET_ATC260X=m +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_HISI=y +CONFIG_POWER_RESET_LINKSTATION=m +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_QCOM_PON=m +CONFIG_POWER_RESET_OCELOT_RESET=y +CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF=y +CONFIG_POWER_RESET_LTC2952=y +CONFIG_POWER_RESET_MT6323=y +CONFIG_POWER_RESET_REGULATOR=y +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_TPS65086=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_SYSCON_REBOOT_MODE=m +CONFIG_POWER_RESET_SC27XX=m +CONFIG_NVMEM_REBOOT_MODE=m +CONFIG_POWER_MLXBF=m +CONFIG_GENERIC_ADC_BATTERY=m +CONFIG_IP5XXX_POWER=m +CONFIG_MAX8925_POWER=m +CONFIG_WM831X_BACKUP=m +CONFIG_WM831X_POWER=m +CONFIG_WM8350_POWER=m +CONFIG_TEST_POWER=m +CONFIG_BATTERY_88PM860X=m +CONFIG_CHARGER_ADP5061=m +CONFIG_BATTERY_ACT8945A=m +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_DS2780=m +CONFIG_BATTERY_DS2781=m +CONFIG_BATTERY_DS2782=m +CONFIG_BATTERY_LENOVO_YOGA_C630=m +CONFIG_BATTERY_QCOM_BATTMGR=m +CONFIG_BATTERY_SAMSUNG_SDI=y +CONFIG_BATTERY_SBS=m +CONFIG_CHARGER_SBS=m +CONFIG_MANAGER_SBS=m +CONFIG_BATTERY_BQ27XXX=m +CONFIG_BATTERY_DA9030=m +CONFIG_BATTERY_DA9052=m +CONFIG_CHARGER_DA9150=m +CONFIG_BATTERY_DA9150=m +CONFIG_CHARGER_AXP20X=m +CONFIG_BATTERY_AXP20X=m +CONFIG_AXP20X_POWER=m +CONFIG_BATTERY_MAX17040=m +CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1720X=m +CONFIG_BATTERY_MAX1721X=m +CONFIG_BATTERY_TWL4030_MADC=m +CONFIG_CHARGER_88PM860X=m +CONFIG_BATTERY_RX51=m +CONFIG_CHARGER_ISP1704=m +CONFIG_CHARGER_MAX8903=m +CONFIG_CHARGER_TWL4030=m +CONFIG_CHARGER_TWL6030=m +CONFIG_CHARGER_LP8727=m +CONFIG_CHARGER_LP8788=m +CONFIG_CHARGER_GPIO=m +CONFIG_CHARGER_MANAGER=y +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +CONFIG_CHARGER_MAX14577=m +CONFIG_CHARGER_DETECTOR_MAX14656=m +CONFIG_CHARGER_MAX77650=m +CONFIG_CHARGER_MAX77693=m +CONFIG_CHARGER_MAX77976=m +CONFIG_CHARGER_MAX8997=m +CONFIG_CHARGER_MAX8998=m +CONFIG_CHARGER_MP2629=m +CONFIG_CHARGER_MT6360=m +CONFIG_CHARGER_MT6370=m +CONFIG_CHARGER_QCOM_SMBB=m +CONFIG_BATTERY_PM8916_BMS_VM=m +CONFIG_CHARGER_PM8916_LBC=m +CONFIG_CHARGER_BQ2415X=m +CONFIG_CHARGER_BQ24190=m +CONFIG_CHARGER_BQ24257=m +CONFIG_CHARGER_BQ24735=m +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_BQ256XX=m +CONFIG_CHARGER_RK817=m +CONFIG_CHARGER_SMB347=m +CONFIG_CHARGER_TPS65090=m +CONFIG_CHARGER_TPS65217=m +CONFIG_BATTERY_GAUGE_LTC2941=m +CONFIG_BATTERY_GOLDFISH=m +CONFIG_BATTERY_RT5033=m +CONFIG_CHARGER_RT5033=m +CONFIG_CHARGER_RT9455=m +CONFIG_CHARGER_RT9467=m +CONFIG_CHARGER_RT9471=m +CONFIG_CHARGER_CROS_USBPD=m +CONFIG_CHARGER_SC2731=m +CONFIG_FUEL_GAUGE_SC27XX=m +CONFIG_CHARGER_UCS1002=m +CONFIG_CHARGER_BD99954=m +CONFIG_RN5T618_POWER=m +CONFIG_BATTERY_SURFACE=m +CONFIG_CHARGER_SURFACE=m +CONFIG_BATTERY_UG3105=m +CONFIG_CHARGER_QCOM_SMB2=m +CONFIG_FUEL_GAUGE_MM8013=m +CONFIG_SENSORS_SMPRO=m +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM1177=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +CONFIG_SENSORS_AS370=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_ASUS_ROG_RYUJIN=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_ARM_SCMI=m +CONFIG_SENSORS_ARM_SCPI=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_CHIPCAP2=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DA9052_ADC=m +CONFIG_SENSORS_DA9055=m +CONFIG_SENSORS_I5K_AMB=m +CONFIG_SENSORS_SPARX5=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_GSC=m +CONFIG_SENSORS_MC13783_ADC=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_GIGABYTE_WATERFORCE=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_HIH6130=m +CONFIG_SENSORS_HS3001=m +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWERZ=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LOCHNAGAR=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2991=m +CONFIG_SENSORS_LTC2992=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +CONFIG_SENSORS_LTC4282=m +CONFIG_SENSORS_MAX1111=m +CONFIG_SENSORS_MAX127=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +CONFIG_SENSORS_MAX31722=m +CONFIG_SENSORS_MAX31730=m +CONFIG_SENSORS_MAX31760=m +CONFIG_MAX31827=m +CONFIG_SENSORS_MAX6620=m +CONFIG_SENSORS_MAX6621=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MC34VR500=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_MLXREG_FAN=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TPS23861=m +CONFIG_SENSORS_MENF21BMC_HWMON=m +CONFIG_SENSORS_MR75203=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT6775_I2C=m +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +CONFIG_SENSORS_NZXT_KRAKEN3=m +CONFIG_SENSORS_NZXT_SMART2=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_PECI_CPUTEMP=m +CONFIG_SENSORS_PECI_DIMMTEMP=m +CONFIG_PMBUS=m +CONFIG_SENSORS_ACBEL_FSG032=m +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_ADP1050=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +CONFIG_SENSORS_FSP_3Y=m +CONFIG_SENSORS_IBM_CFFPS=m +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_INSPUR_IPSPS=m +CONFIG_SENSORS_IR35221=m +CONFIG_SENSORS_IR36021=m +CONFIG_SENSORS_IR38064=m +CONFIG_SENSORS_IR38064_REGULATOR=y +CONFIG_SENSORS_IRPS5401=m +CONFIG_SENSORS_ISL68137=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LM25066_REGULATOR=y +CONFIG_SENSORS_LT7182S=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_LTC2978_REGULATOR=y +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_LTC4286=y +CONFIG_SENSORS_MAX15301=m +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16601=m +CONFIG_SENSORS_MAX20730=m +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX31785=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MP2856=m +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP2993=m +CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m +CONFIG_SENSORS_MP5990=m +CONFIG_SENSORS_MP9941=m +CONFIG_SENSORS_MPQ7932_REGULATOR=y +CONFIG_SENSORS_MPQ7932=m +CONFIG_SENSORS_MPQ8785=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +CONFIG_SENSORS_PLI1209BC_REGULATOR=y +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_PXE1610=m +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_STPDDC60=m +CONFIG_SENSORS_TDA38640=m +CONFIG_SENSORS_TDA38640_REGULATOR=y +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_XDP710=m +CONFIG_SENSORS_XDPE152=m +CONFIG_SENSORS_XDPE122=m +CONFIG_SENSORS_XDPE122_REGULATOR=y +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_PT5161L=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SL28CPLD=m +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SY7636A=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_STTS751=m +CONFIG_SENSORS_SURFACE_FAN=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA238=m +CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_SPD5118=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m +CONFIG_SENSORS_TMP513=m +CONFIG_SENSORS_VEXPRESS=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_WM831X=m +CONFIG_SENSORS_WM8350=m +CONFIG_SENSORS_XGENE=m +CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m +CONFIG_SENSORS_ACPI_POWER=m +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_CORE_TESTING=m +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_IDLE_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_MMIO=m +CONFIG_HISI_THERMAL=m +CONFIG_IMX_THERMAL=m +CONFIG_IMX_SC_THERMAL=m +CONFIG_IMX8MM_THERMAL=m +CONFIG_K3_THERMAL=m +CONFIG_MAX77620_THERMAL=m +CONFIG_QORIQ_THERMAL=m +CONFIG_SUN8I_THERMAL=m +CONFIG_ROCKCHIP_THERMAL=m +CONFIG_ARMADA_THERMAL=y +CONFIG_DA9062_THERMAL=m +CONFIG_MTK_THERMAL=m +CONFIG_MTK_SOC_THERMAL=m +CONFIG_MTK_LVTS_THERMAL=m +CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y +CONFIG_AMLOGIC_THERMAL=m +CONFIG_ST_THERMAL_MEMMAP=m +CONFIG_RCAR_THERMAL=m +CONFIG_RCAR_GEN3_THERMAL=m +CONFIG_RZG2L_THERMAL=m +CONFIG_TEGRA_BPMP_THERMAL=m +CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_QCOM_TSENS=y +CONFIG_QCOM_SPMI_ADC_TM5=m +CONFIG_QCOM_SPMI_TEMP_ALARM=m +CONFIG_QCOM_LMH=m +CONFIG_SPRD_THERMAL=m +CONFIG_KHADAS_MCU_FAN_THERMAL=m +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y +CONFIG_BD957XMUF_WATCHDOG=m +CONFIG_BD96801_WATCHDOG=m +CONFIG_CROS_EC_WATCHDOG=m +CONFIG_DA9052_WATCHDOG=m +CONFIG_DA9055_WATCHDOG=m +CONFIG_DA9063_WATCHDOG=m +CONFIG_DA9062_WATCHDOG=m +CONFIG_GPIO_WATCHDOG=m +CONFIG_MENF21BMC_WATCHDOG=m +CONFIG_MENZ069_WATCHDOG=m +CONFIG_WDAT_WDT=m +CONFIG_WM831X_WATCHDOG=m +CONFIG_WM8350_WATCHDOG=m +CONFIG_XILINX_WATCHDOG=m +CONFIG_XILINX_WINDOW_WATCHDOG=m +CONFIG_ZIIRAVE_WATCHDOG=m +CONFIG_RAVE_SP_WATCHDOG=m +CONFIG_MLX_WDT=m +CONFIG_SL28CPLD_WATCHDOG=m +CONFIG_ARM_SP805_WATCHDOG=m +CONFIG_ARM_SBSA_WATCHDOG=m +CONFIG_ARMADA_37XX_WATCHDOG=m +CONFIG_CADENCE_WATCHDOG=m +CONFIG_DW_WATCHDOG=m +CONFIG_K3_RTI_WATCHDOG=m +CONFIG_RN5T618_WATCHDOG=m +CONFIG_SUNXI_WATCHDOG=m +CONFIG_NPCM7XX_WATCHDOG=y +CONFIG_TWL4030_WATCHDOG=m +CONFIG_MAX63XX_WATCHDOG=m +CONFIG_MAX77620_WATCHDOG=m +CONFIG_IMX2_WDT=m +CONFIG_IMX_SC_WDT=m +CONFIG_IMX7ULP_WDT=m +CONFIG_RETU_WATCHDOG=m +CONFIG_TEGRA_WATCHDOG=m +CONFIG_QCOM_WDT=m +CONFIG_MESON_GXBB_WATCHDOG=m +CONFIG_MESON_WATCHDOG=m +CONFIG_MEDIATEK_WATCHDOG=m +CONFIG_ARM_SMC_WATCHDOG=m +CONFIG_RENESAS_WDT=m +CONFIG_RENESAS_RZAWDT=m +CONFIG_RENESAS_RZN1WDT=m +CONFIG_RENESAS_RZG2LWDT=m +CONFIG_STM32_WATCHDOG=m +CONFIG_STPMIC1_WATCHDOG=m +CONFIG_SPRD_WATCHDOG=m +CONFIG_PM8916_WATCHDOG=m +CONFIG_VISCONTI_WATCHDOG=m +CONFIG_APPLE_WATCHDOG=m +CONFIG_ALIM7101_WDT=m +CONFIG_I6300ESB_WDT=m +CONFIG_HP_WATCHDOG=m +CONFIG_KEMPLD_WDT=m +CONFIG_MARVELL_GTI_WDT=m +CONFIG_MEN_A21_WDT=m +CONFIG_XEN_WDT=m +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m +CONFIG_USBPCWATCHDOG=m +CONFIG_KEEMBAY_WATCHDOG=m +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_MFD_ALTERA_A10SR=y +CONFIG_MFD_ALTERA_SYSMGR=y +CONFIG_MFD_ACT8945A=m +CONFIG_MFD_SUN4I_GPADC=m +CONFIG_MFD_AS3711=y +CONFIG_MFD_SMPRO=m +CONFIG_MFD_AS3722=y +CONFIG_PMIC_ADP5520=y +CONFIG_MFD_AAT2870_CORE=y +CONFIG_MFD_ATMEL_FLEXCOM=m +CONFIG_MFD_ATMEL_HLCDC=m +CONFIG_MFD_BCM590XX=m +CONFIG_MFD_BD9571MWV=m +CONFIG_MFD_AXP20X_I2C=m +CONFIG_MFD_AXP20X_RSB=m +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m +CONFIG_MFD_CS42L43_I2C=m +CONFIG_MFD_CS42L43_SDW=m +CONFIG_MFD_LOCHNAGAR=y +CONFIG_MFD_MADERA=m +CONFIG_MFD_MADERA_I2C=m +CONFIG_MFD_MADERA_SPI=m +CONFIG_MFD_CS47L15=y +CONFIG_MFD_CS47L35=y +CONFIG_MFD_CS47L85=y +CONFIG_MFD_CS47L90=y +CONFIG_MFD_CS47L92=y +CONFIG_PMIC_DA903X=y +CONFIG_MFD_DA9052_SPI=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_DA9055=y +CONFIG_MFD_DA9062=m +CONFIG_MFD_DA9063=y +CONFIG_MFD_DA9150=m +CONFIG_MFD_DLN2=m +CONFIG_MFD_GATEWORKS_GSC=m +CONFIG_MFD_MC13XXX_SPI=m +CONFIG_MFD_MC13XXX_I2C=m +CONFIG_MFD_MP2629=m +CONFIG_MFD_HI6421_PMIC=m +CONFIG_MFD_HI6421_SPMI=m +CONFIG_MFD_HI655X_PMIC=m +CONFIG_LPC_ICH=m +CONFIG_MFD_IQS62X=m +CONFIG_MFD_JANZ_CMODIO=m +CONFIG_MFD_KEMPLD=m +CONFIG_MFD_88PM800=m +CONFIG_MFD_88PM805=m +CONFIG_MFD_88PM860X=y +CONFIG_MFD_88PM886_PMIC=y +CONFIG_MFD_MAX5970=m +CONFIG_MFD_MAX14577=y +CONFIG_MFD_MAX77541=m +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MAX77650=m +CONFIG_MFD_MAX77686=y +CONFIG_MFD_MAX77693=y +CONFIG_MFD_MAX77714=m +CONFIG_MFD_MAX77843=y +CONFIG_MFD_MAX8907=m +CONFIG_MFD_MAX8925=y +CONFIG_MFD_MAX8997=y +CONFIG_MFD_MAX8998=y +CONFIG_MFD_MT6360=m +CONFIG_MFD_MT6370=m +CONFIG_MFD_MT6397=m +CONFIG_MFD_MENF21BMC=m +CONFIG_MFD_CPCAP=m +CONFIG_MFD_VIPERBOARD=m +CONFIG_MFD_NTXEC=m +CONFIG_MFD_RETU=m +CONFIG_MFD_QCOM_RPM=y +CONFIG_MFD_SPMI_PMIC=m +CONFIG_MFD_SY7636A=m +CONFIG_MFD_RT4831=m +CONFIG_MFD_RT5033=m +CONFIG_MFD_RT5120=m +CONFIG_MFD_RC5T583=y +CONFIG_MFD_RK8XX_I2C=m +CONFIG_MFD_RK8XX_SPI=m +CONFIG_MFD_RN5T618=m +CONFIG_MFD_SI476X_CORE=m +CONFIG_MFD_SL28CPLD=m +CONFIG_MFD_SM501=m +CONFIG_MFD_SM501_GPIO=y +CONFIG_MFD_SKY81452=m +CONFIG_MFD_SC27XX_PMIC=m +CONFIG_RZ_MTU3=y +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_SUN6I_PRCM=y +CONFIG_MFD_TI_AM335X_TSCADC=m +CONFIG_MFD_LP3943=m +CONFIG_MFD_LP8788=y +CONFIG_MFD_TI_LMU=m +CONFIG_MFD_PALMAS=y +CONFIG_TPS6105X=m +CONFIG_TPS65010=m +CONFIG_TPS6507X=m +CONFIG_MFD_TPS65086=m +CONFIG_MFD_TPS65090=y +CONFIG_MFD_TPS65217=m +CONFIG_MFD_TI_LP873X=m +CONFIG_MFD_TI_LP87565=m +CONFIG_MFD_TPS65218=m +CONFIG_MFD_TPS65219=m +CONFIG_MFD_TPS6586X=y +CONFIG_MFD_TPS65910=y +CONFIG_MFD_TPS65912_I2C=y +CONFIG_MFD_TPS65912_SPI=y +CONFIG_MFD_TPS6594_I2C=m +CONFIG_MFD_TPS6594_SPI=m +CONFIG_TWL4030_CORE=y +CONFIG_TWL6040_CORE=y +CONFIG_MFD_LM3533=m +CONFIG_MFD_TC3589X=y +CONFIG_MFD_TQMX86=m +CONFIG_MFD_VX855=m +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_CS47L24=y +CONFIG_MFD_WM5102=y +CONFIG_MFD_WM5110=y +CONFIG_MFD_WM8997=y +CONFIG_MFD_WM8998=y +CONFIG_MFD_WM8400=y +CONFIG_MFD_WM831X_I2C=y +CONFIG_MFD_WM831X_SPI=y +CONFIG_MFD_WM8350_I2C=y +CONFIG_MFD_ROHM_BD718XX=m +CONFIG_MFD_ROHM_BD71828=m +CONFIG_MFD_ROHM_BD957XMUF=m +CONFIG_MFD_ROHM_BD96801=m +CONFIG_MFD_STM32_LPTIMER=m +CONFIG_MFD_STPMIC1=m +CONFIG_MFD_WCD934X=m +CONFIG_MFD_ATC260X_I2C=m +CONFIG_MFD_KHADAS_MCU=m +CONFIG_MFD_QCOM_PM8008=m +CONFIG_RAVE_SP_CORE=m +CONFIG_MFD_INTEL_M10_BMC_SPI=m +CONFIG_MFD_INTEL_M10_BMC_PMCI=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m +CONFIG_REGULATOR_VIRTUAL_CONSUMER=m +CONFIG_REGULATOR_USERSPACE_CONSUMER=m +CONFIG_REGULATOR_NETLINK_EVENTS=y +CONFIG_REGULATOR_88PG86X=m +CONFIG_REGULATOR_88PM800=m +CONFIG_REGULATOR_88PM8607=m +CONFIG_REGULATOR_88PM886=m +CONFIG_REGULATOR_ACT8865=m +CONFIG_REGULATOR_ACT8945A=m +CONFIG_REGULATOR_AD5398=m +CONFIG_REGULATOR_ANATOP=m +CONFIG_REGULATOR_AAT2870=m +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_AS3711=m +CONFIG_REGULATOR_AS3722=m +CONFIG_REGULATOR_ATC260X=m +CONFIG_REGULATOR_AW37503=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BCM590XX=m +CONFIG_REGULATOR_BD71815=m +CONFIG_REGULATOR_BD71828=m +CONFIG_REGULATOR_BD718XX=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD957XMUF=m +CONFIG_REGULATOR_BD96801=m +CONFIG_REGULATOR_CPCAP=m +CONFIG_REGULATOR_CROS_EC=m +CONFIG_REGULATOR_DA903X=m +CONFIG_REGULATOR_DA9052=m +CONFIG_REGULATOR_DA9055=m +CONFIG_REGULATOR_DA9062=m +CONFIG_REGULATOR_DA9063=m +CONFIG_REGULATOR_DA9121=m +CONFIG_REGULATOR_DA9210=m +CONFIG_REGULATOR_DA9211=m +CONFIG_REGULATOR_FAN53555=m +CONFIG_REGULATOR_FAN53880=m +CONFIG_REGULATOR_GPIO=m +CONFIG_REGULATOR_HI6421=m +CONFIG_REGULATOR_HI6421V530=m +CONFIG_REGULATOR_HI655X=m +CONFIG_REGULATOR_HI6421V600=m +CONFIG_REGULATOR_ISL9305=m +CONFIG_REGULATOR_ISL6271A=m +CONFIG_REGULATOR_LM363X=m +CONFIG_REGULATOR_LOCHNAGAR=m +CONFIG_REGULATOR_LP3971=m +CONFIG_REGULATOR_LP3972=m +CONFIG_REGULATOR_LP872X=m +CONFIG_REGULATOR_LP873X=m +CONFIG_REGULATOR_LP8755=m +CONFIG_REGULATOR_LP87565=m +CONFIG_REGULATOR_LP8788=m +CONFIG_REGULATOR_LTC3589=m +CONFIG_REGULATOR_LTC3676=m +CONFIG_REGULATOR_MAX14577=m +CONFIG_REGULATOR_MAX1586=m +CONFIG_REGULATOR_MAX5970=m +CONFIG_REGULATOR_MAX77503=m +CONFIG_REGULATOR_MAX77541=m +CONFIG_REGULATOR_MAX77620=m +CONFIG_REGULATOR_MAX77650=m +CONFIG_REGULATOR_MAX77857=m +CONFIG_REGULATOR_MAX8649=m +CONFIG_REGULATOR_MAX8660=m +CONFIG_REGULATOR_MAX8893=m +CONFIG_REGULATOR_MAX8907=m +CONFIG_REGULATOR_MAX8925=m +CONFIG_REGULATOR_MAX8952=m +CONFIG_REGULATOR_MAX8973=m +CONFIG_REGULATOR_MAX8997=m +CONFIG_REGULATOR_MAX8998=m +CONFIG_REGULATOR_MAX20086=m +CONFIG_REGULATOR_MAX20411=m +CONFIG_REGULATOR_MAX77686=m +CONFIG_REGULATOR_MAX77693=m +CONFIG_REGULATOR_MAX77802=m +CONFIG_REGULATOR_MAX77826=m +CONFIG_REGULATOR_MC13783=m +CONFIG_REGULATOR_MC13892=m +CONFIG_REGULATOR_MCP16502=m +CONFIG_REGULATOR_MP5416=m +CONFIG_REGULATOR_MP8859=m +CONFIG_REGULATOR_MP886X=m +CONFIG_REGULATOR_MPQ7920=m +CONFIG_REGULATOR_MT6311=m +CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_MT6323=m +CONFIG_REGULATOR_MT6331=m +CONFIG_REGULATOR_MT6332=m +CONFIG_REGULATOR_MT6357=m +CONFIG_REGULATOR_MT6358=m +CONFIG_REGULATOR_MT6359=m +CONFIG_REGULATOR_MT6360=m +CONFIG_REGULATOR_MT6370=m +CONFIG_REGULATOR_MT6380=m +CONFIG_REGULATOR_MT6397=m +CONFIG_REGULATOR_MTK_DVFSRC=m +CONFIG_REGULATOR_PALMAS=m +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF9453=m +CONFIG_REGULATOR_PF8X00=m +CONFIG_REGULATOR_PFUZE100=m +CONFIG_REGULATOR_PV88060=m +CONFIG_REGULATOR_PV88080=m +CONFIG_REGULATOR_PV88090=m +CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_QCOM_PM8008=m +CONFIG_REGULATOR_QCOM_REFGEN=y +CONFIG_REGULATOR_QCOM_RPM=y +CONFIG_REGULATOR_QCOM_RPMH=y +CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_QCOM_USB_VBUS=y +CONFIG_REGULATOR_RAA215300=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_REGULATOR_RC5T583=m +CONFIG_REGULATOR_RK808=m +CONFIG_REGULATOR_RN5T618=m +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4803=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5033=m +CONFIG_REGULATOR_RT5120=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5739=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6190=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_RTQ2208=m +CONFIG_REGULATOR_SC2731=m +CONFIG_REGULATOR_SKY81452=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_REGULATOR_STM32_BOOSTER=m +CONFIG_REGULATOR_STM32_VREFBUF=m +CONFIG_REGULATOR_STM32_PWR=y +CONFIG_REGULATOR_STPMIC1=m +CONFIG_REGULATOR_SUN20I=m +CONFIG_REGULATOR_SY7636A=m +CONFIG_REGULATOR_SY8106A=m +CONFIG_REGULATOR_SY8824X=m +CONFIG_REGULATOR_SY8827N=m +CONFIG_REGULATOR_TPS51632=m +CONFIG_REGULATOR_TPS62360=m +CONFIG_REGULATOR_TPS6286X=m +CONFIG_REGULATOR_TPS6287X=m +CONFIG_REGULATOR_TPS65023=m +CONFIG_REGULATOR_TPS6507X=m +CONFIG_REGULATOR_TPS65086=m +CONFIG_REGULATOR_TPS65090=m +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_TPS65217=m +CONFIG_REGULATOR_TPS65218=m +CONFIG_REGULATOR_TPS65219=m +CONFIG_REGULATOR_TPS6524X=m +CONFIG_REGULATOR_TPS6586X=m +CONFIG_REGULATOR_TPS65910=m +CONFIG_REGULATOR_TPS65912=m +CONFIG_REGULATOR_TWL4030=m +CONFIG_REGULATOR_VCTRL=m +CONFIG_REGULATOR_VEXPRESS=m +CONFIG_REGULATOR_VQMMC_IPQ4019=m +CONFIG_REGULATOR_WM831X=m +CONFIG_REGULATOR_WM8350=m +CONFIG_REGULATOR_WM8400=m +CONFIG_REGULATOR_WM8994=m +CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_RC_CORE=m +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_ENE=m +CONFIG_IR_FINTEK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_ITE_CIR=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_MESON=m +CONFIG_IR_MESON_TX=m +CONFIG_IR_MTK=m +CONFIG_IR_NUVOTON=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_SUNXI=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_RC_XBOX_DVD=m +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_CEC_CH7322=m +CONFIG_CEC_CROS_EC=m +CONFIG_CEC_MESON_AO=m +CONFIG_CEC_MESON_G12A_AO=m +CONFIG_CEC_GPIO=m +CONFIG_CEC_STM32=m +CONFIG_CEC_TEGRA=m +CONFIG_USB_PULSE8_CEC=m +CONFIG_USB_RAINSHADOW_CEC=m +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_V4L2_FLASH_LED_CLASS=m +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m +CONFIG_MEDIA_PCI_SUPPORT=y +CONFIG_VIDEO_MGB4=m +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_TW5864=m +CONFIG_VIDEO_TW68=m +CONFIG_VIDEO_TW686X=m +CONFIG_VIDEO_DT3155=m +CONFIG_VIDEO_IVTV=m +CONFIG_VIDEO_IVTV_ALSA=m +CONFIG_VIDEO_FB_IVTV=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_MXB=m +CONFIG_VIDEO_BT848=m +CONFIG_DVB_BT8XX=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX23885=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_VIDEO_CX25821=m +CONFIG_VIDEO_CX25821_ALSA=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7164=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +CONFIG_DVB_DDBRIDGE=m +CONFIG_DVB_DM1105=m +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_DVB_SMIPCIE=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_IPU_BRIDGE=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_SI476X=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_USB_RAREMONO=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_USB_SI4713=m +CONFIG_PLATFORM_SI4713=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_ALLEGRO_DVT=m +CONFIG_VIDEO_MESON_GE2D=m +CONFIG_VIDEO_AMPHION_VPU=m +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m +CONFIG_VIDEO_CODA=m +CONFIG_VIDEO_WAVE_VPU=m +CONFIG_VIDEO_E5010_JPEG_ENC=m +CONFIG_VIDEO_CAFE_CCIC=m +CONFIG_VIDEO_MEDIATEK_VPU=m +CONFIG_VIDEO_NPCM_VCD_ECE=m +CONFIG_VIDEO_TEGRA_VDE=m +CONFIG_VIDEO_IMX7_CSI=m +CONFIG_VIDEO_IMX8MQ_MIPI_CSI2=m +CONFIG_VIDEO_IMX_MIPI_CSIS=m +CONFIG_VIDEO_IMX8_ISI=m +CONFIG_VIDEO_IMX8_ISI_M2M=y +CONFIG_VIDEO_IMX_PXP=m +CONFIG_VIDEO_DW100=m +CONFIG_VIDEO_IMX8_JPEG=m +CONFIG_VIDEO_QCOM_CAMSS=m +CONFIG_VIDEO_QCOM_IRIS=m +CONFIG_VIDEO_QCOM_VENUS=m +CONFIG_VIDEO_RCAR_CSI2=m +CONFIG_VIDEO_RCAR_ISP=m +CONFIG_VIDEO_RCAR_VIN=m +CONFIG_VIDEO_RZG2L_CSI2=m +CONFIG_VIDEO_RZG2L_CRU=m +CONFIG_VIDEO_RENESAS_FCP=m +CONFIG_VIDEO_RENESAS_FDP1=m +CONFIG_VIDEO_RENESAS_JPU=m +CONFIG_VIDEO_RENESAS_VSP1=m +CONFIG_VIDEO_RCAR_DRIF=m +CONFIG_VIDEO_ROCKCHIP_RGA=m +CONFIG_VIDEO_ROCKCHIP_ISP1=m +CONFIG_VIDEO_ROCKCHIP_VDEC=m +CONFIG_VIDEO_STM32_DCMI=m +CONFIG_VIDEO_STM32_DCMIPP=m +CONFIG_VIDEO_STM32_DMA2D=m +CONFIG_VIDEO_SUN4I_CSI=m +CONFIG_VIDEO_SUN6I_CSI=m +CONFIG_VIDEO_SUN6I_MIPI_CSI2=m +CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m +CONFIG_VIDEO_SUN8I_DEINTERLACE=m +CONFIG_VIDEO_SUN8I_ROTATE=m +CONFIG_VIDEO_TI_CAL=m +CONFIG_VIDEO_TI_CAL_MC=y +CONFIG_VIDEO_TI_J721E_CSI2RX=m +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_XILINX=m +CONFIG_VIDEO_XILINX_CSI2RXSS=m +CONFIG_VIDEO_XILINX_TPG=m +CONFIG_SMS_SDIO_DRV=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_VIDEO_VISL=m +CONFIG_DVB_FIREDTV=m +CONFIG_SMS_SIANO_DEBUGFS=y +CONFIG_VIDEO_ALVIUM_CSI2=m +CONFIG_VIDEO_AR0521=m +CONFIG_VIDEO_GC0308=m +CONFIG_VIDEO_GC0310=m +CONFIG_VIDEO_GC05A2=m +CONFIG_VIDEO_GC08A3=m +CONFIG_VIDEO_GC2145=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_IMX415=m +CONFIG_VIDEO_IMX681=m +CONFIG_VIDEO_MT9M001=m +CONFIG_VIDEO_MT9M111=m +CONFIG_VIDEO_MT9M114=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V032=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OG0VE1B=m +CONFIG_VIDEO_OV01A10=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV02E10=m +CONFIG_VIDEO_OV02C10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV08X40=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +CONFIG_VIDEO_OV2735=m +CONFIG_VIDEO_OV2740=m +CONFIG_VIDEO_OV4689=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV6211=m +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8858=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_OV9734=m +CONFIG_VIDEO_RDACM20=m +CONFIG_VIDEO_RDACM21=m +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_VGXY61=m +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_ET8EK8=m +CONFIG_VIDEO_THP7312=m +CONFIG_VIDEO_AD5820=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9719=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_ADP1653=m +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TLV320AIC23B=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7183=m +CONFIG_VIDEO_ADV748X=m +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=m +CONFIG_VIDEO_ADV7842_CEC=y +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_ISL7998X=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_MAX9286=m +CONFIG_VIDEO_ML86V7667=m +CONFIG_VIDEO_SAA7110=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TC358743_CEC=y +CONFIG_VIDEO_TC358746=m +CONFIG_VIDEO_TVP514X=m +CONFIG_VIDEO_TVP7002=m +CONFIG_VIDEO_TW9900=m +CONFIG_VIDEO_TW9910=m +CONFIG_VIDEO_VPX3220=m +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_ADV7343=m +CONFIG_VIDEO_ADV7393=m +CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_THS8200=m +CONFIG_SDR_MAX2175=m +CONFIG_VIDEO_I2C=m +CONFIG_VIDEO_ST_MIPID02=m +CONFIG_VIDEO_THS7303=m +CONFIG_VIDEO_DS90UB913=m +CONFIG_VIDEO_DS90UB953=m +CONFIG_VIDEO_DS90UB960=m +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m +CONFIG_CXD2880_SPI_DRV=m +CONFIG_VIDEO_GS1662=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_CXD2880=m +CONFIG_DVB_MN88443X=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_DUMMY_FE=m +CONFIG_HD44780=m +CONFIG_LCD2S=m +CONFIG_KS0108=m +CONFIG_IMG_ASCII_LCD=m +CONFIG_HT16K33=m +CONFIG_MAX6959=m +CONFIG_SEG_LED_GPIO=m +CONFIG_PANEL=m +CONFIG_DRM=y +CONFIG_DRM_PANIC=y +CONFIG_DRM_PANIC_BACKGROUND_COLOR=0x5e2750 +CONFIG_DRM_CLIENT_LOG=y +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_DISPLAY_DP_AUX_CEC=y +CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMD_ISP=y +CONFIG_DRM_AMD_ACP=y +CONFIG_DRM_AMD_DC_SI=y +CONFIG_DRM_AMD_SECURE_DISPLAY=y +CONFIG_HSA_AMD=y +CONFIG_DRM_HDLCD=m +CONFIG_DRM_MALI_DISPLAY=m +CONFIG_DRM_KOMEDA=m +CONFIG_DRM_AST=m +CONFIG_DRM_CHIPONE_ICN6211=m +CONFIG_DRM_CHRONTEL_CH7033=m +CONFIG_DRM_CROS_EC_ANX7688=m +CONFIG_DRM_FSL_LDB=m +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_ITE_IT6263=m +CONFIG_DRM_ITE_IT6505=m +CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9211=m +CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_ITE_IT66121=m +CONFIG_DRM_LVDS_CODEC=m +CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m +CONFIG_DRM_NWL_MIPI_DSI=m +CONFIG_DRM_NXP_PTN3460=m +CONFIG_DRM_PARADE_PS8622=m +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SAMSUNG_DSIM=m +CONFIG_DRM_SIL_SII8620=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SII9234=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TOSHIBA_TC358764=m +CONFIG_DRM_TOSHIBA_TC358767=m +CONFIG_DRM_TOSHIBA_TC358768=m +CONFIG_DRM_TOSHIBA_TC358775=m +CONFIG_DRM_TI_DLPC3433=m +CONFIG_DRM_TI_TDP158=m +CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_SN65DSI83=m +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_TI_TPD12S015=m +CONFIG_DRM_ANALOGIX_ANX6345=m +CONFIG_DRM_ANALOGIX_ANX78XX=m +CONFIG_DRM_ANALOGIX_ANX7625=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_CDNS_DSI=m +CONFIG_DRM_CDNS_MHDP8546=m +CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m +CONFIG_DRM_IMX8QM_LDB=m +CONFIG_DRM_IMX8QXP_LDB=m +CONFIG_DRM_IMX8QXP_PIXEL_COMBINER=m +CONFIG_DRM_IMX8QXP_PIXEL_LINK=m +CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI=m +CONFIG_DRM_IMX93_MIPI_DSI=m +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_GP_AUDIO=m +CONFIG_DRM_DW_HDMI_CEC=m +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_GUD=m +CONFIG_DRM_HISI_HIBMC=m +CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_POWERVR=m +CONFIG_DRM_IMX_DCSS=m +CONFIG_DRM_IMX_LCDC=m +CONFIG_DRM_KMB_DISPLAY=m +CONFIG_DRM_LIMA=m +CONFIG_DRM_LOGICVC=m +CONFIG_DRM_MEDIATEK=m +CONFIG_DRM_MEDIATEK_DP=m +CONFIG_DRM_MEDIATEK_HDMI=m +CONFIG_DRM_MESON=m +CONFIG_DRM_MGAG200=m +CONFIG_DRM_MSM=m +CONFIG_DRM_MXSFB=m +CONFIG_DRM_IMX_LCDIF=m +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_PANEL_ABT_Y030XX067A=m +CONFIG_DRM_PANEL_ARM_VERSATILE=m +CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m +CONFIG_DRM_PANEL_AUO_A030JTN01=m +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m +CONFIG_DRM_PANEL_BOE_HIMAX8279D=m +CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_EBBG_FT8719=m +CONFIG_DRM_PANEL_ELIDA_KD35T133=m +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_DSI_CM=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m +CONFIG_DRM_PANEL_HIMAX_HX83112A=m +CONFIG_DRM_PANEL_HIMAX_HX8394=m +CONFIG_DRM_PANEL_ILITEK_IL9322=m +CONFIG_DRM_PANEL_ILITEK_ILI9341=m +CONFIG_DRM_PANEL_ILITEK_ILI9805=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_ILITEK_ILI9882T=m +CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m +CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m +CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m +CONFIG_DRM_PANEL_JDI_LPM102A188A=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_JDI_R63452=m +CONFIG_DRM_PANEL_KHADAS_TS050=m +CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m +CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m +CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m +CONFIG_DRM_PANEL_LG_LB035Q02=m +CONFIG_DRM_PANEL_LG_LG4573=m +CONFIG_DRM_PANEL_LG_SW43408=m +CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_NEC_NL8048HL11=m +CONFIG_DRM_PANEL_NEWVISION_NV3051D=m +CONFIG_DRM_PANEL_NEWVISION_NV3052C=m +CONFIG_DRM_PANEL_NOVATEK_NT35510=m +CONFIG_DRM_PANEL_NOVATEK_NT35560=m +CONFIG_DRM_PANEL_NOVATEK_NT35950=m +CONFIG_DRM_PANEL_NOVATEK_NT36523=m +CONFIG_DRM_PANEL_NOVATEK_NT36672A=m +CONFIG_DRM_PANEL_NOVATEK_NT36672E=m +CONFIG_DRM_PANEL_NOVATEK_NT39016=m +CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m +CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m +CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=m +CONFIG_DRM_PANEL_RAYDIUM_RM68200=m +CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m +CONFIG_DRM_PANEL_RAYDIUM_RM69380=m +CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01=m +CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08=m +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24=m +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m +CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +CONFIG_DRM_PANEL_SAMSUNG_LD9040=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7=m +CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m +CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m +CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m +CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m +CONFIG_DRM_PANEL_SEIKO_43WVF1G=m +CONFIG_DRM_PANEL_SHARP_LQ079L1SX01=m +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m +CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m +CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m +CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_SITRONIX_ST7789V=m +CONFIG_DRM_PANEL_SONY_ACX565AKM=m +CONFIG_DRM_PANEL_SONY_TD4353_JDI=m +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m +CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m +CONFIG_DRM_PANEL_EDP=y +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_SYNAPTICS_R63353=m +CONFIG_DRM_PANEL_TDO_TL070WSH30=m +CONFIG_DRM_PANEL_TPO_TD028TTEC1=m +CONFIG_DRM_PANEL_TPO_TD043MTEA1=m +CONFIG_DRM_PANEL_TPO_TPG110=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_PANEL_VISIONOX_R66451=m +CONFIG_DRM_PANEL_VISIONOX_RM69299=m +CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +CONFIG_DRM_PANEL_XINPENG_XPP055C272=m +CONFIG_DRM_PANFROST=m +CONFIG_DRM_PANTHOR=m +CONFIG_DRM_PL111=m +CONFIG_DRM_QXL=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_RCAR_DU=m +CONFIG_DRM_RCAR_DW_HDMI=m +CONFIG_DRM_RZG2L_DU=m +CONFIG_DRM_SHMOBILE=m +CONFIG_DRM_ROCKCHIP=m +CONFIG_ROCKCHIP_VOP2=y +CONFIG_ROCKCHIP_ANALOGIX_DP=y +CONFIG_ROCKCHIP_CDN_DP=y +CONFIG_ROCKCHIP_DW_HDMI=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_ROCKCHIP_INNO_HDMI=y +CONFIG_ROCKCHIP_LVDS=y +CONFIG_ROCKCHIP_RGB=y +CONFIG_ROCKCHIP_RK3066_HDMI=y +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X_SPI=m +CONFIG_DRM_SPRD=m +CONFIG_DRM_STM=m +CONFIG_DRM_STM_DSI=m +CONFIG_DRM_STM_LVDS=m +CONFIG_DRM_SUN4I=m +CONFIG_DRM_SIMPLEDRM=y +CONFIG_DRM_TEGRA=m +CONFIG_DRM_TEGRA_STAGING=y +CONFIG_DRM_TIDSS=m +CONFIG_DRM_ARCPGU=m +CONFIG_DRM_BOCHS=m +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_GM12U320=m +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9163=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_SHARP_MEMORY=m +CONFIG_DRM_UDL=m +CONFIG_DRM_VGEM=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VKMS=m +CONFIG_DRM_VMWGFX=m +CONFIG_DRM_XE=m +CONFIG_DRM_XEN_FRONTEND=m +CONFIG_DRM_ZYNQMP_DPSUB=m +CONFIG_FB=y +CONFIG_FB_CIRRUS=m +CONFIG_FB_PM2=m +CONFIG_FB_PM2_FIFO_DISCONNECT=y +CONFIG_FB_IMX=m +CONFIG_FB_CYBER2000=m +CONFIG_FB_ASILIANT=y +CONFIG_FB_IMSTT=y +CONFIG_FB_UVESA=m +CONFIG_FB_EFI=y +CONFIG_FB_OPENCORES=m +CONFIG_FB_S1D13XXX=m +CONFIG_FB_NVIDIA=m +CONFIG_FB_NVIDIA_I2C=y +CONFIG_FB_RIVA=m +CONFIG_FB_RIVA_I2C=y +CONFIG_FB_I740=m +CONFIG_FB_MATROX=m +CONFIG_FB_MATROX_MILLENIUM=y +CONFIG_FB_MATROX_MYSTIQUE=y +CONFIG_FB_MATROX_G=y +CONFIG_FB_MATROX_I2C=m +CONFIG_FB_MATROX_MAVEN=m +CONFIG_FB_RADEON=m +CONFIG_FB_ATY128=m +CONFIG_FB_ATY=m +CONFIG_FB_ATY_CT=y +CONFIG_FB_ATY_GX=y +CONFIG_FB_S3=m +CONFIG_FB_SAVAGE=m +CONFIG_FB_SAVAGE_I2C=y +CONFIG_FB_SIS=m +CONFIG_FB_SIS_300=y +CONFIG_FB_SIS_315=y +CONFIG_FB_NEOMAGIC=m +CONFIG_FB_KYRO=m +CONFIG_FB_3DFX=m +# CONFIG_FB_3DFX_I2C is not set +CONFIG_FB_VOODOO1=m +CONFIG_FB_VT8623=m +CONFIG_FB_TRIDENT=m +CONFIG_FB_ARK=m +CONFIG_FB_PM3=m +CONFIG_FB_CARMINE=m +CONFIG_FB_SM501=m +CONFIG_FB_SMSCUFX=m +CONFIG_FB_UDL=m +CONFIG_FB_XILINX=m +CONFIG_XEN_FBDEV_FRONTEND=m +CONFIG_FB_METRONOME=m +CONFIG_FB_MB862XX=m +CONFIG_FB_SSD1307=m +CONFIG_FB_SM712=m +CONFIG_FB_TILEBLITTING=y +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_LCD_L4F00242T03=m +CONFIG_LCD_LMS283GF05=m +CONFIG_LCD_LTV350QV=m +CONFIG_LCD_ILI922X=m +CONFIG_LCD_TDO24M=m +CONFIG_LCD_VGG2432A4=m +CONFIG_LCD_PLATFORM=m +CONFIG_LCD_AMS369FG06=m +CONFIG_LCD_LMS501KF03=m +CONFIG_LCD_HX8357=m +CONFIG_LCD_OTM3225A=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_KTD253=m +CONFIG_BACKLIGHT_KTD2801=m +CONFIG_BACKLIGHT_KTZ8866=m +CONFIG_BACKLIGHT_LM3533=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_DA903X=m +CONFIG_BACKLIGHT_DA9052=m +CONFIG_BACKLIGHT_MAX8925=m +CONFIG_BACKLIGHT_MT6370=m +CONFIG_BACKLIGHT_QCOM_WLED=m +CONFIG_BACKLIGHT_RT4831=m +CONFIG_BACKLIGHT_WM831X=m +CONFIG_BACKLIGHT_ADP5520=m +CONFIG_BACKLIGHT_ADP8860=m +CONFIG_BACKLIGHT_ADP8870=m +CONFIG_BACKLIGHT_88PM860X=m +CONFIG_BACKLIGHT_AAT2870=m +CONFIG_BACKLIGHT_LM3509=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_LM3639=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_LP8788=m +CONFIG_BACKLIGHT_MP3309C=m +CONFIG_BACKLIGHT_PANDORA=m +CONFIG_BACKLIGHT_SKY81452=m +CONFIG_BACKLIGHT_TPS65217=m +CONFIG_BACKLIGHT_AS3711=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_BACKLIGHT_LV5207LP=m +CONFIG_BACKLIGHT_BD6107=m +CONFIG_BACKLIGHT_ARCXCNN=m +CONFIG_BACKLIGHT_RAVE_SP=m +CONFIG_BACKLIGHT_LED=m +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_DRM_ACCEL=y +CONFIG_DRM_ACCEL_ARM_ETHOSU=m +CONFIG_DRM_ACCEL_QAIC=m +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_HRTIMER=m +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_PCMTEST=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SERIAL_GENERIC=m +CONFIG_SND_MPU401=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AD1889=m +CONFIG_SND_ALS300=m +CONFIG_SND_ALI5451=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AW2=m +CONFIG_SND_AZT3328=m +CONFIG_SND_BT87X=m +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_EMU10K1=m +CONFIG_SND_EMU10K1X=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_ES1938=m +CONFIG_SND_ES1968=m +CONFIG_SND_ES1968_INPUT=y +CONFIG_SND_ES1968_RADIO=y +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1712=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MAESTRO3=m +CONFIG_SND_MAESTRO3_INPUT=y +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_SONICVIBES=m +CONFIG_SND_TRIDENT=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=0 +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1 +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_TEGRA=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m +CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m +CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m +CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m +CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_MIDI_V2=y +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_DICE=m +CONFIG_SND_OXFW=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_BEBOB=m +CONFIG_SND_FIREWIRE_DIGI00X=m +CONFIG_SND_FIREWIRE_TASCAM=m +CONFIG_SND_FIREWIRE_MOTU=m +CONFIG_SND_FIREFACE=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m +CONFIG_SND_AMD_ACP_CONFIG=m +CONFIG_SND_SOC_APPLE_MCA=m +CONFIG_SND_SOC_MIKROE_PROTO=m +CONFIG_SND_BCM63XX_I2S_WHISTLER=m +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_DESIGNWARE_PCM=y +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_RPMSG=m +CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_IMX_ES8328=m +CONFIG_SND_SOC_IMX_SGTL5000=m +CONFIG_SND_SOC_FSL_ASOC_CARD=m +CONFIG_SND_SOC_IMX_AUDMIX=m +CONFIG_SND_SOC_IMX_HDMI=m +CONFIG_SND_SOC_IMX_CARD=m +CONFIG_SND_SOC_CHV3_I2S=m +CONFIG_SND_I2S_HI6210_I2S=m +CONFIG_SND_KIRKWOOD_SOC=m +CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB=m +CONFIG_SND_SOC_INTEL_KEEMBAY=m +CONFIG_SND_SOC_MT6797=m +CONFIG_SND_SOC_MT6797_MT6351=m +CONFIG_SND_SOC_MT7986=m +CONFIG_SND_SOC_MT7986_WM8960=m +CONFIG_SND_SOC_MT8183=m +CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A=m +CONFIG_SND_SOC_MT8183_DA7219_MAX98357A=m +CONFIG_SND_SOC_MT8186=m +CONFIG_SND_SOC_MT8186_MT6366=m +CONFIG_SND_SOC_MTK_BTCVSD=m +CONFIG_SND_SOC_MT8188=m +CONFIG_SND_SOC_MT8188_MT6359=m +CONFIG_SND_SOC_MT8192=m +CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=m +CONFIG_SND_SOC_MT8195=m +CONFIG_SND_SOC_MT8195_MT6359=m +CONFIG_SND_MESON_AXG_SOUND_CARD=m +CONFIG_SND_MESON_GX_SOUND_CARD=m +CONFIG_SND_SOC_QCOM=m +CONFIG_SND_SOC_STORM=m +CONFIG_SND_SOC_APQ8016_SBC=m +CONFIG_SND_SOC_MSM8996=m +CONFIG_SND_SOC_SDM845=m +CONFIG_SND_SOC_SM8250=m +CONFIG_SND_SOC_SC8280XP=m +CONFIG_SND_SOC_SC7180=m +CONFIG_SND_SOC_SC7280=m +CONFIG_SND_SOC_X1E80100=m +CONFIG_SND_SOC_SH4_FSI=m +CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SOC_RZ=m +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m +CONFIG_SND_SOC_ROCKCHIP_PDM=m +CONFIG_SND_SOC_ROCKCHIP_SPDIF=m +CONFIG_SND_SOC_ROCKCHIP_MAX98090=m +CONFIG_SND_SOC_ROCKCHIP_RT5645=m +CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m +CONFIG_SND_SOC_RK3399_GRU_SOUND=m +CONFIG_SND_SOC_SPRD=m +CONFIG_SND_SOC_SPRD_MCDT=m +CONFIG_SND_SOC_STM32_SAI=m +CONFIG_SND_SOC_STM32_I2S=m +CONFIG_SND_SOC_STM32_SPDIFRX=m +CONFIG_SND_SOC_STM32_DFSDM=m +CONFIG_SND_SUN8I_CODEC=m +CONFIG_SND_SUN8I_CODEC_ANALOG=m +CONFIG_SND_SUN50I_CODEC_ANALOG=m +CONFIG_SND_SUN50I_DMIC=m +CONFIG_SND_SOC_TEGRA=m +CONFIG_SND_SOC_TEGRA20_I2S=m +CONFIG_SND_SOC_TEGRA20_SPDIF=m +CONFIG_SND_SOC_TEGRA30_I2S=m +CONFIG_SND_SOC_TEGRA210_AHUB=m +CONFIG_SND_SOC_TEGRA210_DMIC=m +CONFIG_SND_SOC_TEGRA210_I2S=m +CONFIG_SND_SOC_TEGRA210_OPE=m +CONFIG_SND_SOC_TEGRA186_ASRC=m +CONFIG_SND_SOC_TEGRA186_DSPK=m +CONFIG_SND_SOC_TEGRA210_ADMAIF=m +CONFIG_SND_SOC_TEGRA210_MVC=m +CONFIG_SND_SOC_TEGRA210_SFC=m +CONFIG_SND_SOC_TEGRA210_AMX=m +CONFIG_SND_SOC_TEGRA210_ADX=m +CONFIG_SND_SOC_TEGRA210_MIXER=m +CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m +CONFIG_SND_SOC_TEGRA_RT5631=m +CONFIG_SND_SOC_TEGRA_RT5640=m +CONFIG_SND_SOC_TEGRA_WM8753=m +CONFIG_SND_SOC_TEGRA_WM8903=m +CONFIG_SND_SOC_TEGRA_WM9712=m +CONFIG_SND_SOC_TEGRA_TRIMSLICE=m +CONFIG_SND_SOC_TEGRA_ALC5632=m +CONFIG_SND_SOC_TEGRA_MAX98090=m +CONFIG_SND_SOC_TEGRA_MAX98088=m +CONFIG_SND_SOC_TEGRA_RT5677=m +CONFIG_SND_SOC_TEGRA_SGTL5000=m +CONFIG_SND_SOC_J721E_EVM=m +CONFIG_SND_SOC_XILINX_I2S=m +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m +CONFIG_SND_SOC_XILINX_SPDIF=m +CONFIG_SND_SOC_XTFPGA_I2S=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_PCI=m +CONFIG_SND_SOC_SOF_ACPI=m +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y +CONFIG_SND_SOC_SOF_IMX8=m +CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y +CONFIG_SND_SOC_SOF_MT8186=m +CONFIG_SND_SOC_SOF_MT8195=m +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_ADAU1372_I2C=m +CONFIG_SND_SOC_ADAU1372_SPI=m +CONFIG_SND_SOC_ADAU1373=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_AK4104=m +CONFIG_SND_SOC_AK4118=m +CONFIG_SND_SOC_AK4375=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_AK4619=m +CONFIG_SND_SOC_AK4642=m +CONFIG_SND_SOC_AK5386=m +CONFIG_SND_SOC_ALC5623=m +CONFIG_SND_SOC_AUDIO_IIO_AUX=m +CONFIG_SND_SOC_AW8738=m +CONFIG_SND_SOC_AW88395=m +CONFIG_SND_SOC_AW88261=m +CONFIG_SND_SOC_AW88081=m +CONFIG_SND_SOC_AW87390=m +CONFIG_SND_SOC_AW88399=m +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_CHV3_CODEC=m +CONFIG_SND_SOC_CPCAP=m +CONFIG_SND_SOC_CS35L32=m +CONFIG_SND_SOC_CS35L33=m +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +CONFIG_SND_SOC_CS35L41_SPI=m +CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS35L56_I2C=m +CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS35L56_SDW=m +CONFIG_SND_SOC_CS40L50=m +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L42_SDW=m +CONFIG_SND_SOC_CS42L43=m +CONFIG_SND_SOC_CS42L43_SDW=m +CONFIG_SND_SOC_CS42L51_I2C=m +CONFIG_SND_SOC_CS42L52=m +CONFIG_SND_SOC_CS42L56=m +CONFIG_SND_SOC_CS42L73=m +CONFIG_SND_SOC_CS42L83=m +CONFIG_SND_SOC_CS42L84=m +CONFIG_SND_SOC_CS4234=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_CS4270=m +CONFIG_SND_SOC_CS4271_I2C=m +CONFIG_SND_SOC_CS4271_SPI=m +CONFIG_SND_SOC_CS42XX8_I2C=m +CONFIG_SND_SOC_CS43130=m +CONFIG_SND_SOC_CS4341=m +CONFIG_SND_SOC_CS4349=m +CONFIG_SND_SOC_CS53L30=m +CONFIG_SND_SOC_CS530X_I2C=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_ES8311=m +CONFIG_SND_SOC_ES8323=m +CONFIG_SND_SOC_FRAMER=m +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_HDA=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_IDT821034=m +CONFIG_SND_SOC_INNO_RK3036=m +CONFIG_SND_SOC_LOCHNAGAR_SC=m +CONFIG_SND_SOC_MAX98504=m +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98520=m +CONFIG_SND_SOC_MAX98363=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98373_SDW=m +CONFIG_SND_SOC_MAX98388=m +CONFIG_SND_SOC_MAX98396=m +CONFIG_SND_SOC_MAX9860=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m +CONFIG_SND_SOC_PCM1681=m +CONFIG_SND_SOC_PCM1789_I2C=m +CONFIG_SND_SOC_PCM179X_I2C=m +CONFIG_SND_SOC_PCM179X_SPI=m +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +CONFIG_SND_SOC_PCM3168A_SPI=m +CONFIG_SND_SOC_PCM5102A=m +CONFIG_SND_SOC_PCM512x_I2C=m +CONFIG_SND_SOC_PCM512x_SPI=m +CONFIG_SND_SOC_PCM6240=m +CONFIG_SND_SOC_PEB2466=m +CONFIG_SND_SOC_RK3308=m +CONFIG_SND_SOC_RK3328=m +CONFIG_SND_SOC_RK817=m +CONFIG_SND_SOC_RT1017_SDCA_SDW=m +CONFIG_SND_SOC_RT1308_SDW=m +CONFIG_SND_SOC_RT1316_SDW=m +CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m +CONFIG_SND_SOC_RT5616=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_RT5682_SDW=m +CONFIG_SND_SOC_RT700_SDW=m +CONFIG_SND_SOC_RT711_SDW=m +CONFIG_SND_SOC_RT711_SDCA_SDW=m +CONFIG_SND_SOC_RT712_SDCA_SDW=m +CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m +CONFIG_SND_SOC_RT721_SDCA_SDW=m +CONFIG_SND_SOC_RT722_SDCA_SDW=m +CONFIG_SND_SOC_RT715_SDW=m +CONFIG_SND_SOC_RT715_SDCA_SDW=m +CONFIG_SND_SOC_RT9120=m +CONFIG_SND_SOC_RT9123P=m +CONFIG_SND_SOC_RTQ9128=m +CONFIG_SND_SOC_SDW_MOCKUP=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SMA1303=m +CONFIG_SND_SOC_SMA1307=m +CONFIG_SND_SOC_SRC4XXX_I2C=m +CONFIG_SND_SOC_SSM2305=m +CONFIG_SND_SOC_SSM2518=m +CONFIG_SND_SOC_SSM2602_SPI=m +CONFIG_SND_SOC_SSM2602_I2C=m +CONFIG_SND_SOC_SSM3515=m +CONFIG_SND_SOC_SSM4567=m +CONFIG_SND_SOC_STA32X=m +CONFIG_SND_SOC_STA350=m +CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TAS2552=m +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m +CONFIG_SND_SOC_TAS2781_I2C=m +CONFIG_SND_SOC_TAS5086=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TAS5720=m +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +CONFIG_SND_SOC_TFA9879=m +CONFIG_SND_SOC_TFA989X=m +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320AIC23_SPI=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m +CONFIG_SND_SOC_TLV320AIC3X_SPI=m +CONFIG_SND_SOC_TLV320ADCX140=m +CONFIG_SND_SOC_TSCS42XX=m +CONFIG_SND_SOC_TSCS454=m +CONFIG_SND_SOC_UDA1334=m +CONFIG_SND_SOC_UDA1342=m +CONFIG_SND_SOC_WCD9335=m +CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WCD937X_SDW=m +CONFIG_SND_SOC_WCD939X_SDW=m +CONFIG_SND_SOC_WM8510=m +CONFIG_SND_SOC_WM8523=m +CONFIG_SND_SOC_WM8524=m +CONFIG_SND_SOC_WM8580=m +CONFIG_SND_SOC_WM8711=m +CONFIG_SND_SOC_WM8728=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m +CONFIG_SND_SOC_WM8737=m +CONFIG_SND_SOC_WM8741=m +CONFIG_SND_SOC_WM8750=m +CONFIG_SND_SOC_WM8770=m +CONFIG_SND_SOC_WM8776=m +CONFIG_SND_SOC_WM8782=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8804_SPI=m +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8940=m +CONFIG_SND_SOC_WM8961=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WM8974=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SOC_WM8985=m +CONFIG_SND_SOC_WM8998=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA883X=m +CONFIG_SND_SOC_WSA884X=m +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_MT6359_ACCDET=m +CONFIG_SND_SOC_MT6660=m +CONFIG_SND_SOC_NAU8540=m +CONFIG_SND_SOC_NAU8810=m +CONFIG_SND_SOC_NAU8821=m +CONFIG_SND_SOC_NAU8822=m +CONFIG_SND_SOC_NAU8824=m +CONFIG_SND_SOC_NTP8918=m +CONFIG_SND_SOC_NTP8835=m +CONFIG_SND_SOC_TPA6130A2=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m +CONFIG_SND_TEST_COMPONENT=m +CONFIG_SND_XEN_FRONTEND=m +CONFIG_SND_VIRTIO=m +CONFIG_HID=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_ASUS=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_MACALLY=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CMEDIA=m +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EVISION=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_GOOGLE_HAMMER=m +CONFIG_HID_GOOGLE_STADIA_FF=m +CONFIG_HID_VIVALDI=m +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_KYSONA=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VRC2=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_REDRAGON=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=m +CONFIG_HID_NVIDIA_SHIELD=m +CONFIG_NVIDIA_SHIELD_FF=y +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_PXRC=m +CONFIG_HID_RAZER=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_RETRODE=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_STEAM_FF=y +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TOPRE=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_WINWING=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_ALPS=m +CONFIG_HID_MCP2200=m +CONFIG_HID_MCP2221=m +CONFIG_HID_BPF=y +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m +CONFIG_I2C_HID_OF_GOODIX=m +CONFIG_SURFACE_HID=m +CONFIG_SURFACE_KBD=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_ULPI_BUS=y +CONFIG_USB=y +CONFIG_USB_PCI_AMD=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_MON=m +CONFIG_USB_C67X00_HCD=m +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DBGCAP=y +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_XHCI_HISTB=m +CONFIG_USB_XHCI_MVEBU=m +CONFIG_USB_XHCI_RCAR=m +CONFIG_USB_XHCI_RZV2M=y +CONFIG_USB_XHCI_TEGRA=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_FSL=m +CONFIG_USB_EHCI_HCD_NPCM7XX=m +CONFIG_USB_EHCI_TEGRA=m +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_MAX3421_HCD=m +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_HCD_ISO=y +CONFIG_USB_R8A66597_HCD=m +CONFIG_USB_RENESAS_USBHS_HCD=m +CONFIG_USB_HCD_BCMA=m +CONFIG_USB_HCD_SSB=m +CONFIG_USB_XEN_HCD=m +CONFIG_USB_RENESAS_USBHS=m +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_MTU3=m +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_SUNXI=m +CONFIG_USB_MUSB_MEDIATEK=m +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_PCI=m +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_KEYSTONE=m +CONFIG_USB_DWC3_MESON_G12A=m +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC3_IMX8MP=m +CONFIG_USB_DWC3_XILINX=m +CONFIG_USB_DWC3_AM62=m +CONFIG_USB_DWC3_RTK=m +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y +CONFIG_USB_DWC2_PCI=m +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_ISP1760=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_USS720=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_QCOM_EUD=m +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_USB_LJCA=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_LINK_LAYER_TEST=m +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_ONBOARD_DEV=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m +CONFIG_USB_GPIO_VBUS=m +CONFIG_TAHVO_USB=m +CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y +CONFIG_USB_ISP1301=m +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_U_SERIAL_CONSOLE=y +CONFIG_USB_GR_UDC=m +CONFIG_USB_R8A66597=m +CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_RZV2M_USB3DRD=m +CONFIG_USB_RENESAS_USB3=m +CONFIG_USB_RENESAS_USBF=m +CONFIG_USB_PXA27X=m +CONFIG_USB_SNP_UDC_PLAT=m +CONFIG_USB_BDC_UDC=m +CONFIG_USB_AMD5536UDC=m +CONFIG_USB_NET2280=m +CONFIG_USB_GOKU=m +CONFIG_USB_EG20T=m +CONFIG_USB_GADGET_XILINX=m +CONFIG_USB_MAX3420_UDC=m +CONFIG_USB_TEGRA_XUDC=m +CONFIG_USB_CDNS2_UDC=m +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_PHONET=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_MIDI2=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_CONFIGFS_F_TCM=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_GADGET_UAC1=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_GADGET_TARGET=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +CONFIG_USB_G_WEBCAM=m +CONFIG_USB_RAW_GADGET=m +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_RT1711H=m +CONFIG_TYPEC_MT6360=m +CONFIG_TYPEC_TCPCI_MT6370=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_QCOM_PMIC=m +CONFIG_TYPEC_UCSI=m +CONFIG_UCSI_CCG=m +CONFIG_UCSI_ACPI=m +CONFIG_UCSI_STM32G0=m +CONFIG_UCSI_PMIC_GLINK=m +CONFIG_UCSI_LENOVO_YOGA_C630=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_ANX7411=m +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_WUSB3801=m +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_GPIO_SBU=m +CONFIG_TYPEC_MUX_PI3USB30532=m +CONFIG_TYPEC_MUX_IT5205=m +CONFIG_TYPEC_MUX_NB7VPQ904M=m +CONFIG_TYPEC_MUX_PS883X=m +CONFIG_TYPEC_MUX_PTN36502=m +CONFIG_TYPEC_MUX_TUSB1046=m +CONFIG_TYPEC_MUX_WCD939X_USBSS=m +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_NVIDIA_ALTMODE=m +CONFIG_TYPEC_TBT_ALTMODE=m +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SD8787=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_SDIO_UART=m +CONFIG_MMC_CRYPTO=y +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_SDHCI=m +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_ACPI=m +CONFIG_MMC_SDHCI_PLTFM=m +CONFIG_MMC_SDHCI_OF_ARASAN=m +CONFIG_MMC_SDHCI_OF_AT91=m +CONFIG_MMC_SDHCI_OF_ESDHC=m +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_OF_SPARX5=m +CONFIG_MMC_SDHCI_CADENCE=m +CONFIG_MMC_SDHCI_ESDHC_IMX=m +CONFIG_MMC_SDHCI_TEGRA=m +CONFIG_MMC_SDHCI_PXAV3=m +CONFIG_MMC_SDHCI_F_SDH30=m +CONFIG_MMC_SDHCI_MILBEAUT=m +CONFIG_MMC_SDHCI_NPCM=m +CONFIG_MMC_MESON_GX=m +CONFIG_MMC_MESON_MX_SDIO=m +CONFIG_MMC_ALCOR=m +CONFIG_MMC_SDHCI_MSM=m +CONFIG_MMC_MXC=m +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_SPI=m +CONFIG_MMC_SDHCI_SPRD=m +CONFIG_MMC_SDHI=m +CONFIG_MMC_SDHI_SYS_DMAC=m +CONFIG_MMC_CB710=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_CAVIUM_THUNDERX=m +CONFIG_MMC_DW=m +CONFIG_MMC_DW_BLUEFIELD=m +CONFIG_MMC_DW_EXYNOS=m +CONFIG_MMC_DW_HI3798CV200=m +CONFIG_MMC_DW_HI3798MV200=m +CONFIG_MMC_DW_K3=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_DW_ROCKCHIP=m +CONFIG_MMC_SH_MMCIF=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +CONFIG_MMC_USDHI6ROL0=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_SUNXI=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_MTK=m +CONFIG_MMC_SDHCI_XENON=m +CONFIG_MMC_SDHCI_AM654=m +CONFIG_MMC_OWL=m +CONFIG_MMC_LITEX=m +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_SCSI_UFSHCD_PCI=m +CONFIG_SCSI_UFS_DWC_TC_PCI=m +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m +CONFIG_SCSI_UFS_QCOM=m +CONFIG_SCSI_UFS_MEDIATEK=m +CONFIG_SCSI_UFS_HISI=m +CONFIG_SCSI_UFS_RENESAS=m +CONFIG_SCSI_UFS_TI_J721E=m +CONFIG_SCSI_UFS_SPRD=m +CONFIG_MEMSTICK=m +CONFIG_MSPRO_BLOCK=m +CONFIG_MS_BLOCK=m +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y +CONFIG_LEDS_88PM860X=m +CONFIG_LEDS_AN30259A=m +CONFIG_LEDS_AW200XX=m +CONFIG_LEDS_AW2013=m +CONFIG_LEDS_BCM6328=m +CONFIG_LEDS_BCM6358=m +CONFIG_LEDS_CPCAP=m +CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_EL15203000=m +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +CONFIG_LEDS_LM3533=m +CONFIG_LEDS_LM3642=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_MT6323=m +CONFIG_LEDS_SUN50I_A100=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +CONFIG_LEDS_LP55XX_COMMON=m +CONFIG_LEDS_LP5521=m +CONFIG_LEDS_LP5523=m +CONFIG_LEDS_LP5562=m +CONFIG_LEDS_LP5569=m +CONFIG_LEDS_LP8501=m +CONFIG_LEDS_LP8788=m +CONFIG_LEDS_LP8860=m +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA955X_GPIO=y +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_PCA995X=m +CONFIG_LEDS_WM831X_STATUS=m +CONFIG_LEDS_WM8350=m +CONFIG_LEDS_DA903X=m +CONFIG_LEDS_DA9052=m +CONFIG_LEDS_DAC124S085=m +CONFIG_LEDS_PWM=m +CONFIG_LEDS_REGULATOR=m +CONFIG_LEDS_BD2606MVV=m +CONFIG_LEDS_BD2802=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_ADP5520=m +CONFIG_LEDS_MAX5970=m +CONFIG_LEDS_MC13783=m +CONFIG_LEDS_TCA6507=m +CONFIG_LEDS_TLC591XX=m +CONFIG_LEDS_MAX77650=m +CONFIG_LEDS_MAX8997=m +CONFIG_LEDS_LM355x=m +CONFIG_LEDS_MENF21BMC=m +CONFIG_LEDS_IS31FL319X=m +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_SC27XX_BLTC=m +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_USER=m +CONFIG_LEDS_SPI_BYTE=m +CONFIG_LEDS_LM3697=m +CONFIG_LEDS_LM36274=m +CONFIG_LEDS_AAT1290=m +CONFIG_LEDS_AS3645A=m +CONFIG_LEDS_KTD2692=m +CONFIG_LEDS_LM3601X=m +CONFIG_LEDS_MAX77693=m +CONFIG_LEDS_MT6360=m +CONFIG_LEDS_MT6370_FLASH=m +CONFIG_LEDS_QCOM_FLASH=m +CONFIG_LEDS_RT4505=m +CONFIG_LEDS_RT8515=m +CONFIG_LEDS_SGM3140=m +CONFIG_LEDS_SY7802=m +CONFIG_LEDS_GROUP_MULTICOLOR=m +CONFIG_LEDS_KTD202X=m +CONFIG_LEDS_NCP5623=m +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_QCOM_LPG=m +CONFIG_LEDS_MT6370_RGB=m +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_TTY=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m +CONFIG_ACCESSIBILITY=y +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +CONFIG_SPEAKUP_SYNTH_DECTLK=m +CONFIG_SPEAKUP_SYNTH_DECEXT=m +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +CONFIG_SPEAKUP_SYNTH_DUMMY=m +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_ERDMA=m +CONFIG_INFINIBAND_HNS_HIP08=m +CONFIG_INFINIBAND_IRDMA=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_QEDR=m +CONFIG_INFINIBAND_VMWARE_PVRDMA=m +CONFIG_RDMA_RXE=m +CONFIG_RDMA_SIW=m +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_EDAC=y +CONFIG_EDAC_GHES=y +CONFIG_EDAC_LAYERSCAPE=m +CONFIG_EDAC_THUNDERX=m +CONFIG_EDAC_ALTERA=y +CONFIG_EDAC_ALTERA_SDRAM=y +CONFIG_EDAC_ALTERA_OCRAM=y +CONFIG_EDAC_ALTERA_ETHERNET=y +CONFIG_EDAC_ALTERA_NAND=y +CONFIG_EDAC_ALTERA_USB=y +CONFIG_EDAC_ALTERA_QSPI=y +CONFIG_EDAC_ALTERA_SDMMC=y +CONFIG_EDAC_SYNOPSYS=m +CONFIG_EDAC_XGENE=m +CONFIG_EDAC_QCOM=m +CONFIG_EDAC_BLUEFIELD=m +CONFIG_EDAC_DMC520=m +CONFIG_EDAC_ZYNQMP=m +CONFIG_EDAC_NPCM=m +CONFIG_EDAC_VERSAL=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_88PM860X=m +CONFIG_RTC_DRV_88PM80X=m +CONFIG_RTC_DRV_88PM886=m +CONFIG_RTC_DRV_ABB5ZES3=m +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_AS3722=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1307_CENTURY=y +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_HYM8563=m +CONFIG_RTC_DRV_LP8788=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX8907=m +CONFIG_RTC_DRV_MAX8925=m +CONFIG_RTC_DRV_MAX8998=m +CONFIG_RTC_DRV_MAX8997=m +CONFIG_RTC_DRV_MAX31335=m +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_NCT3018Y=m +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_ISL12026=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BD70528=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_TWL4030=m +CONFIG_RTC_DRV_PALMAS=m +CONFIG_RTC_DRV_TPS6586X=m +CONFIG_RTC_DRV_TPS65910=m +CONFIG_RTC_DRV_RC5T583=m +CONFIG_RTC_DRV_RC5T619=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8111=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_DS1302=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_MAX6916=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_RTC_DRV_RX6110=m +CONFIG_RTC_DRV_DS1286=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1742=m +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_DA9052=m +CONFIG_RTC_DRV_DA9055=m +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_STK17TA8=m +CONFIG_RTC_DRV_M48T86=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_WM831X=m +CONFIG_RTC_DRV_WM8350=m +CONFIG_RTC_DRV_SC27XX=m +CONFIG_RTC_DRV_OPTEE=m +CONFIG_RTC_DRV_ZYNQMP=m +CONFIG_RTC_DRV_CROS_EC=m +CONFIG_RTC_DRV_NTXEC=m +CONFIG_RTC_DRV_IMXDI=m +CONFIG_RTC_DRV_FSL_FTM_ALARM=m +CONFIG_RTC_DRV_SH=m +CONFIG_RTC_DRV_PL030=m +CONFIG_RTC_DRV_PL031=m +CONFIG_RTC_DRV_SUN6I=y +CONFIG_RTC_DRV_MV=y +CONFIG_RTC_DRV_ARMADA38X=m +CONFIG_RTC_DRV_CADENCE=m +CONFIG_RTC_DRV_FTRTC010=m +CONFIG_RTC_DRV_MC13XXX=m +CONFIG_RTC_DRV_PM8XXX=m +CONFIG_RTC_DRV_TEGRA=m +CONFIG_RTC_DRV_MXC=m +CONFIG_RTC_DRV_MXC_V2=m +CONFIG_RTC_DRV_SNVS=m +CONFIG_RTC_DRV_BBNSM=m +CONFIG_RTC_DRV_IMX_SC=m +CONFIG_RTC_DRV_MT2712=m +CONFIG_RTC_DRV_MT6397=m +CONFIG_RTC_DRV_MT7622=m +CONFIG_RTC_DRV_XGENE=y +CONFIG_RTC_DRV_R7301=m +CONFIG_RTC_DRV_STM32=m +CONFIG_RTC_DRV_CPCAP=m +CONFIG_RTC_DRV_TI_K3=m +CONFIG_RTC_DRV_MA35D1=m +CONFIG_RTC_DRV_RENESAS_RTCA3=m +CONFIG_RTC_DRV_GOLDFISH=m +CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_DMADEVICES=y +CONFIG_ALTERA_MSGDMA=m +CONFIG_AMBA_PL08X=y +CONFIG_APPLE_ADMAC=m +CONFIG_AXI_DMAC=m +CONFIG_BCM_SBA_RAID=m +CONFIG_DMA_SUN6I=m +CONFIG_DW_AXI_DMAC=m +CONFIG_FSL_EDMA=m +CONFIG_FSL_QDMA=m +CONFIG_IMX_DMA=m +CONFIG_IMX_SDMA=m +CONFIG_INTEL_IDMA64=m +CONFIG_K3_DMA=m +CONFIG_MV_XOR=y +CONFIG_MV_XOR_V2=y +CONFIG_MXS_DMA=y +CONFIG_OWL_DMA=m +CONFIG_PL330_DMA=m +CONFIG_PLX_DMA=m +CONFIG_SPRD_DMA=m +CONFIG_TEGRA186_GPC_DMA=m +CONFIG_TEGRA20_APB_DMA=y +CONFIG_TEGRA210_ADMA=m +CONFIG_XGENE_DMA=m +CONFIG_XILINX_DMA=m +CONFIG_XILINX_ZYNQMP_DMA=m +CONFIG_XILINX_ZYNQMP_DPDMA=m +CONFIG_MTK_HSDMA=m +CONFIG_MTK_CQDMA=m +CONFIG_MTK_UART_APDMA=m +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_GPI_DMA=m +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_PCI=m +CONFIG_DW_EDMA=m +CONFIG_DW_EDMA_PCIE=m +CONFIG_SF_PDMA=m +CONFIG_RCAR_DMAC=m +CONFIG_RENESAS_USB_DMAC=m +CONFIG_RZ_DMAC=m +CONFIG_TI_K3_UDMA=y +CONFIG_TI_K3_UDMA_GLUE_LAYER=y +CONFIG_FSL_DPAA2_QDMA=m +CONFIG_STM32_DMA=y +CONFIG_STM32_DMAMUX=y +CONFIG_STM32_MDMA=y +CONFIG_STM32_DMA3=m +CONFIG_ASYNC_TX_DMA=y +CONFIG_SW_SYNC=y +CONFIG_UDMABUF=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_UIO_CIF=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_NETX=m +CONFIG_UIO_MF624=m +CONFIG_UIO_DFL=m +CONFIG_VFIO=m +CONFIG_VFIO_DEVICE_CDEV=y +CONFIG_VFIO_NOIOMMU=y +CONFIG_VFIO_PCI=m +CONFIG_MLX5_VFIO_PCI=m +CONFIG_HISI_ACC_VFIO_PCI=m +CONFIG_PDS_VFIO_PCI=m +CONFIG_NVGRACE_GPU_VFIO_PCI=m +CONFIG_QAT_VFIO_PCI=m +CONFIG_VFIO_PLATFORM=m +CONFIG_VFIO_AMBA=m +CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m +CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m +CONFIG_VFIO_FSL_MC=m +CONFIG_VFIO_CDX=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VMGENID=m +CONFIG_NITRO_ENCLAVES=m +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_PMEM=m +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_MEM=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VDPA=m +CONFIG_VDPA_SIM=m +CONFIG_VDPA_SIM_NET=m +CONFIG_VDPA_SIM_BLOCK=m +CONFIG_VDPA_USER=m +CONFIG_IFCVF=m +CONFIG_MLX5_VDPA_NET=m +CONFIG_MLX5_VDPA_STEERING_DEBUG=y +CONFIG_VP_VDPA=m +CONFIG_SNET_VDPA=m +CONFIG_PDS_VDPA=m +CONFIG_OCTEONEP_VDPA=m +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_VDPA=m +CONFIG_XEN_DEV_EVTCHN=m +CONFIG_XENFS=m +CONFIG_XEN_GNTDEV_DMABUF=y +CONFIG_XEN_GRANT_DMA_ALLOC=y +CONFIG_XEN_PVCALLS_FRONTEND=m +CONFIG_XEN_SCSI_BACKEND=m +CONFIG_XEN_PRIVCMD_EVENTFD=y +CONFIG_XEN_VIRTIO=y +CONFIG_GREYBUS=m +CONFIG_GREYBUS_BEAGLEPLAY=m +CONFIG_GREYBUS_ES2=m +CONFIG_COMEDI=m +CONFIG_COMEDI_MISC_DRIVERS=y +CONFIG_COMEDI_BOND=m +CONFIG_COMEDI_TEST=m +CONFIG_COMEDI_PARPORT=m +CONFIG_COMEDI_ISA_DRIVERS=y +CONFIG_COMEDI_PCL711=m +CONFIG_COMEDI_PCL724=m +CONFIG_COMEDI_PCL726=m +CONFIG_COMEDI_PCL730=m +CONFIG_COMEDI_PCL812=m +CONFIG_COMEDI_PCL816=m +CONFIG_COMEDI_PCL818=m +CONFIG_COMEDI_PCM3724=m +CONFIG_COMEDI_AMPLC_DIO200_ISA=m +CONFIG_COMEDI_AMPLC_PC236_ISA=m +CONFIG_COMEDI_AMPLC_PC263_ISA=m +CONFIG_COMEDI_RTI800=m +CONFIG_COMEDI_RTI802=m +CONFIG_COMEDI_DAC02=m +CONFIG_COMEDI_DAS16M1=m +CONFIG_COMEDI_DAS08_ISA=m +CONFIG_COMEDI_DAS16=m +CONFIG_COMEDI_DAS800=m +CONFIG_COMEDI_DAS1800=m +CONFIG_COMEDI_DAS6402=m +CONFIG_COMEDI_DT2801=m +CONFIG_COMEDI_DT2811=m +CONFIG_COMEDI_DT2814=m +CONFIG_COMEDI_DT2815=m +CONFIG_COMEDI_DT2817=m +CONFIG_COMEDI_DT282X=m +CONFIG_COMEDI_DMM32AT=m +CONFIG_COMEDI_FL512=m +CONFIG_COMEDI_AIO_AIO12_8=m +CONFIG_COMEDI_AIO_IIRO_16=m +CONFIG_COMEDI_II_PCI20KC=m +CONFIG_COMEDI_C6XDIGIO=m +CONFIG_COMEDI_MPC624=m +CONFIG_COMEDI_ADQ12B=m +CONFIG_COMEDI_NI_AT_A2150=m +CONFIG_COMEDI_NI_AT_AO=m +CONFIG_COMEDI_NI_ATMIO=m +CONFIG_COMEDI_NI_ATMIO16D=m +CONFIG_COMEDI_NI_LABPC_ISA=m +CONFIG_COMEDI_PCMAD=m +CONFIG_COMEDI_PCMDA12=m +CONFIG_COMEDI_PCMMIO=m +CONFIG_COMEDI_PCMUIO=m +CONFIG_COMEDI_MULTIQ3=m +CONFIG_COMEDI_S526=m +CONFIG_COMEDI_PCI_DRIVERS=m +CONFIG_COMEDI_8255_PCI=m +CONFIG_COMEDI_ADDI_APCI_1032=m +CONFIG_COMEDI_ADDI_APCI_1500=m +CONFIG_COMEDI_ADDI_APCI_1516=m +CONFIG_COMEDI_ADDI_APCI_1564=m +CONFIG_COMEDI_ADDI_APCI_16XX=m +CONFIG_COMEDI_ADDI_APCI_2032=m +CONFIG_COMEDI_ADDI_APCI_2200=m +CONFIG_COMEDI_ADDI_APCI_3120=m +CONFIG_COMEDI_ADDI_APCI_3501=m +CONFIG_COMEDI_ADDI_APCI_3XXX=m +CONFIG_COMEDI_ADL_PCI6208=m +CONFIG_COMEDI_ADL_PCI7X3X=m +CONFIG_COMEDI_ADL_PCI8164=m +CONFIG_COMEDI_ADL_PCI9111=m +CONFIG_COMEDI_ADL_PCI9118=m +CONFIG_COMEDI_ADV_PCI1710=m +CONFIG_COMEDI_ADV_PCI1720=m +CONFIG_COMEDI_ADV_PCI1723=m +CONFIG_COMEDI_ADV_PCI1724=m +CONFIG_COMEDI_ADV_PCI1760=m +CONFIG_COMEDI_ADV_PCI_DIO=m +CONFIG_COMEDI_AMPLC_DIO200_PCI=m +CONFIG_COMEDI_AMPLC_PC236_PCI=m +CONFIG_COMEDI_AMPLC_PC263_PCI=m +CONFIG_COMEDI_AMPLC_PCI224=m +CONFIG_COMEDI_AMPLC_PCI230=m +CONFIG_COMEDI_CONTEC_PCI_DIO=m +CONFIG_COMEDI_DAS08_PCI=m +CONFIG_COMEDI_DT3000=m +CONFIG_COMEDI_DYNA_PCI10XX=m +CONFIG_COMEDI_GSC_HPDI=m +CONFIG_COMEDI_MF6X4=m +CONFIG_COMEDI_ICP_MULTI=m +CONFIG_COMEDI_DAQBOARD2000=m +CONFIG_COMEDI_JR3_PCI=m +CONFIG_COMEDI_KE_COUNTER=m +CONFIG_COMEDI_CB_PCIDAS64=m +CONFIG_COMEDI_CB_PCIDAS=m +CONFIG_COMEDI_CB_PCIDDA=m +CONFIG_COMEDI_CB_PCIMDAS=m +CONFIG_COMEDI_CB_PCIMDDA=m +CONFIG_COMEDI_ME4000=m +CONFIG_COMEDI_ME_DAQ=m +CONFIG_COMEDI_NI_6527=m +CONFIG_COMEDI_NI_65XX=m +CONFIG_COMEDI_NI_660X=m +CONFIG_COMEDI_NI_670X=m +CONFIG_COMEDI_NI_LABPC_PCI=m +CONFIG_COMEDI_NI_PCIDIO=m +CONFIG_COMEDI_NI_PCIMIO=m +CONFIG_COMEDI_RTD520=m +CONFIG_COMEDI_S626=m +CONFIG_COMEDI_USB_DRIVERS=m +CONFIG_COMEDI_DT9812=m +CONFIG_COMEDI_NI_USB6501=m +CONFIG_COMEDI_USBDUX=m +CONFIG_COMEDI_USBDUXFAST=m +CONFIG_COMEDI_USBDUXSIGMA=m +CONFIG_COMEDI_VMK80XX=m +CONFIG_COMEDI_8255_SA=m +CONFIG_COMEDI_TESTS=m +CONFIG_COMEDI_TESTS_EXAMPLE=m +CONFIG_COMEDI_TESTS_NI_ROUTES=m +CONFIG_STAGING=y +CONFIG_RTL8723BS=m +CONFIG_ADIS16203=m +CONFIG_AD7816=m +CONFIG_ADT7316=m +CONFIG_ADT7316_I2C=m +CONFIG_AD9832=m +CONFIG_AD9834=m +CONFIG_AD5933=m +CONFIG_FB_SM750=m +CONFIG_MFD_NVEC=m +CONFIG_KEYBOARD_NVEC=m +CONFIG_SERIO_NVEC_PS2=m +CONFIG_NVEC_POWER=m +CONFIG_NVEC_PAZ00=m +CONFIG_STAGING_MEDIA=y +CONFIG_DVB_AV7110=m +CONFIG_VIDEO_MAX96712=m +CONFIG_VIDEO_MESON_VDEC=m +CONFIG_VIDEO_SUNXI=y +CONFIG_VIDEO_SUNXI_CEDRUS=m +CONFIG_VIDEO_SUN6I_ISP=m +CONFIG_VIDEO_TEGRA=m +CONFIG_VIDEO_TEGRA_TPG=y +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SEPS525=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1305=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_MOST_COMPONENTS=m +CONFIG_MOST_NET=m +CONFIG_MOST_VIDEO=m +CONFIG_MOST_DIM2=m +CONFIG_GREYBUS_AUDIO=m +CONFIG_GREYBUS_AUDIO_APB_CODEC=m +CONFIG_GREYBUS_BOOTROM=m +CONFIG_GREYBUS_FIRMWARE=m +CONFIG_GREYBUS_HID=m +CONFIG_GREYBUS_LIGHT=m +CONFIG_GREYBUS_LOG=m +CONFIG_GREYBUS_LOOPBACK=m +CONFIG_GREYBUS_POWER=m +CONFIG_GREYBUS_RAW=m +CONFIG_GREYBUS_VIBRATOR=m +CONFIG_GREYBUS_BRIDGED_PHY=m +CONFIG_GREYBUS_GPIO=m +CONFIG_GREYBUS_I2C=m +CONFIG_GREYBUS_PWM=m +CONFIG_GREYBUS_SDIO=m +CONFIG_GREYBUS_SPI=m +CONFIG_GREYBUS_UART=m +CONFIG_GREYBUS_USB=m +CONFIG_XIL_AXIS_FIFO=m +CONFIG_VME_BUS=y +CONFIG_VME_TSI148=m +CONFIG_VME_FAKE=m +CONFIG_VME_USER=m +CONFIG_CHROME_PLATFORMS=y +CONFIG_CHROMEOS_ACPI=m +CONFIG_CHROMEOS_TBMC=m +CONFIG_CROS_EC=m +CONFIG_CROS_EC_I2C=m +CONFIG_CROS_EC_RPMSG=m +CONFIG_CROS_EC_SPI=m +CONFIG_CROS_EC_UART=m +CONFIG_CROS_KBD_LED_BACKLIGHT=m +CONFIG_CROS_HPS_I2C=m +CONFIG_CHROMEOS_PRIVACY_SCREEN=m +CONFIG_MELLANOX_PLATFORM=y +CONFIG_MLXREG_HOTPLUG=m +CONFIG_MLXREG_IO=m +CONFIG_MLXREG_LC=m +CONFIG_MLXBF_TMFIFO=m +CONFIG_MLXBF_BOOTCTL=m +CONFIG_MLXBF_PMC=m +CONFIG_NVSW_SN2201=m +CONFIG_SURFACE_ACPI_NOTIFY=m +CONFIG_SURFACE_AGGREGATOR_CDEV=m +CONFIG_SURFACE_AGGREGATOR_HUB=m +CONFIG_SURFACE_AGGREGATOR_REGISTRY=m +CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m +CONFIG_SURFACE_DTX=m +CONFIG_SURFACE_GPE=m +CONFIG_SURFACE_HOTPLUG=m +CONFIG_SURFACE_PLATFORM_PROFILE=m +CONFIG_SURFACE_AGGREGATOR=m +CONFIG_EC_ACER_ASPIRE1=m +CONFIG_EC_HUAWEI_GAOKUN=m +CONFIG_EC_LENOVO_YOGA_C630=m +CONFIG_EC_LENOVO_THINKPAD_T14S=m +CONFIG_COMMON_CLK_WM831X=m +CONFIG_CLK_ICST=y +CONFIG_CLK_SP810=y +CONFIG_LMK04832=m +CONFIG_COMMON_CLK_APPLE_NCO=m +CONFIG_COMMON_CLK_MAX77686=m +CONFIG_COMMON_CLK_MAX9485=m +CONFIG_COMMON_CLK_RK808=m +CONFIG_COMMON_CLK_SCPI=m +CONFIG_COMMON_CLK_SI5341=m +CONFIG_COMMON_CLK_SI5351=m +CONFIG_COMMON_CLK_SI514=m +CONFIG_COMMON_CLK_SI544=m +CONFIG_COMMON_CLK_SI570=m +CONFIG_COMMON_CLK_CDCE706=m +CONFIG_COMMON_CLK_CDCE925=m +CONFIG_COMMON_CLK_CS2000_CP=m +CONFIG_COMMON_CLK_FSL_SAI=y +CONFIG_CLK_TWL=m +CONFIG_CLK_TWL6040=m +CONFIG_COMMON_CLK_AXI_CLKGEN=m +CONFIG_CLK_LS1028A_PLLDIG=m +CONFIG_COMMON_CLK_LOCHNAGAR=m +CONFIG_COMMON_CLK_NPCM8XX=m +CONFIG_COMMON_CLK_PALMAS=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_RS9_PCIE=m +CONFIG_COMMON_CLK_SI521XX=m +CONFIG_COMMON_CLK_VC3=m +CONFIG_COMMON_CLK_VC5=m +CONFIG_COMMON_CLK_VC7=m +CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_FIXED_MMIO=y +CONFIG_COMMON_CLK_HI3516CV300=m +CONFIG_COMMON_CLK_HI3519=m +CONFIG_COMMON_CLK_HI3798CV200=m +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +CONFIG_CLK_IMX8QXP=y +CONFIG_CLK_IMX8ULP=m +CONFIG_CLK_IMX93=m +CONFIG_CLK_IMX95_BLK_CTL=m +CONFIG_TI_SCI_CLK=m +CONFIG_COMMON_CLK_MT2712_BDPSYS=y +CONFIG_COMMON_CLK_MT2712_IMGSYS=y +CONFIG_COMMON_CLK_MT2712_JPGDECSYS=y +CONFIG_COMMON_CLK_MT2712_MFGCFG=y +CONFIG_COMMON_CLK_MT2712_MMSYS=y +CONFIG_COMMON_CLK_MT2712_VDECSYS=y +CONFIG_COMMON_CLK_MT2712_VENCSYS=y +CONFIG_COMMON_CLK_MT6735=m +CONFIG_COMMON_CLK_MT6735_IMGSYS=m +CONFIG_COMMON_CLK_MT6735_MFGCFG=m +CONFIG_COMMON_CLK_MT6735_VDECSYS=m +CONFIG_COMMON_CLK_MT6735_VENCSYS=m +CONFIG_COMMON_CLK_MT6765_AUDIOSYS=y +CONFIG_COMMON_CLK_MT6765_CAMSYS=y +CONFIG_COMMON_CLK_MT6765_GCESYS=y +CONFIG_COMMON_CLK_MT6765_MMSYS=y +CONFIG_COMMON_CLK_MT6765_IMGSYS=y +CONFIG_COMMON_CLK_MT6765_VCODECSYS=y +CONFIG_COMMON_CLK_MT6765_MFGSYS=y +CONFIG_COMMON_CLK_MT6765_MIPI0ASYS=y +CONFIG_COMMON_CLK_MT6765_MIPI0BSYS=y +CONFIG_COMMON_CLK_MT6765_MIPI1ASYS=y +CONFIG_COMMON_CLK_MT6765_MIPI1BSYS=y +CONFIG_COMMON_CLK_MT6765_MIPI2ASYS=y +CONFIG_COMMON_CLK_MT6765_MIPI2BSYS=y +CONFIG_COMMON_CLK_MT6779_MMSYS=y +CONFIG_COMMON_CLK_MT6779_IMGSYS=y +CONFIG_COMMON_CLK_MT6779_IPESYS=y +CONFIG_COMMON_CLK_MT6779_CAMSYS=y +CONFIG_COMMON_CLK_MT6779_VDECSYS=y +CONFIG_COMMON_CLK_MT6779_VENCSYS=y +CONFIG_COMMON_CLK_MT6779_MFGCFG=y +CONFIG_COMMON_CLK_MT6779_AUDSYS=y +CONFIG_COMMON_CLK_MT6795=m +CONFIG_COMMON_CLK_MT6797_MMSYS=y +CONFIG_COMMON_CLK_MT6797_IMGSYS=y +CONFIG_COMMON_CLK_MT6797_VDECSYS=y +CONFIG_COMMON_CLK_MT6797_VENCSYS=y +CONFIG_COMMON_CLK_MT7622_ETHSYS=y +CONFIG_COMMON_CLK_MT7622_HIFSYS=y +CONFIG_COMMON_CLK_MT7622_AUDSYS=y +CONFIG_COMMON_CLK_MT7981_ETHSYS=m +CONFIG_COMMON_CLK_MT7988=m +CONFIG_COMMON_CLK_MT8173_IMGSYS=m +CONFIG_COMMON_CLK_MT8173_VDECSYS=m +CONFIG_COMMON_CLK_MT8173_VENCSYS=m +CONFIG_COMMON_CLK_MT8186_CAMSYS=m +CONFIG_COMMON_CLK_MT8186_IMGSYS=m +CONFIG_COMMON_CLK_MT8186_IMP_IIC_WRAP=m +CONFIG_COMMON_CLK_MT8186_MCUSYS=m +CONFIG_COMMON_CLK_MT8186_MDPSYS=m +CONFIG_COMMON_CLK_MT8186_MFGCFG=m +CONFIG_COMMON_CLK_MT8186_MMSYS=m +CONFIG_COMMON_CLK_MT8186_VDECSYS=m +CONFIG_COMMON_CLK_MT8186_VENCSYS=m +CONFIG_COMMON_CLK_MT8188=m +CONFIG_COMMON_CLK_MT8195_APUSYS=m +CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP=m +CONFIG_COMMON_CLK_MT8195_MFGCFG=m +CONFIG_COMMON_CLK_MT8195_SCP_ADSP=m +CONFIG_COMMON_CLK_MT8195_VDOSYS=m +CONFIG_COMMON_CLK_MT8195_VPPSYS=m +CONFIG_COMMON_CLK_MT8365=m +CONFIG_COMMON_CLK_MT8516_AUDSYS=y +CONFIG_COMMON_CLK_A1_PLL=m +CONFIG_COMMON_CLK_A1_PERIPHERALS=m +CONFIG_COMMON_CLK_C3_PERIPHERALS=m +CONFIG_COMMON_CLK_S4_PLL=m +CONFIG_COMMON_CLK_S4_PERIPHERALS=m +CONFIG_COMMON_CLK_QCOM=y +CONFIG_CLK_X1E80100_CAMCC=y +CONFIG_CLK_X1E80100_DISPCC=m +CONFIG_CLK_X1E80100_GPUCC=m +CONFIG_CLK_X1E80100_TCSRCC=m +CONFIG_CLK_X1P42100_GPUCC=m +CONFIG_CLK_QCM2290_GPUCC=m +CONFIG_QCOM_A53PLL=y +CONFIG_QCOM_A7PLL=m +CONFIG_QCOM_CLK_APCS_MSM8916=y +CONFIG_QCOM_CLK_APCC_MSM8996=y +CONFIG_QCOM_CLK_RPM=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_QCOM_CLK_RPMH=y +CONFIG_IPQ_APSS_6018=m +CONFIG_IPQ_GCC_4019=m +CONFIG_IPQ_GCC_5018=m +CONFIG_IPQ_GCC_5332=m +CONFIG_IPQ_GCC_5424=m +CONFIG_IPQ_GCC_6018=m +CONFIG_IPQ_GCC_8074=m +CONFIG_IPQ_GCC_9574=m +CONFIG_IPQ_NSSCC_QCA8K=m +CONFIG_MSM_GCC_8916=y +CONFIG_MSM_GCC_8917=m +CONFIG_MSM_GCC_8939=m +CONFIG_MSM_GCC_8953=m +CONFIG_MSM_GCC_8976=m +CONFIG_MSM_MMCC_8994=m +CONFIG_MSM_MMCC_8996=m +CONFIG_MSM_GPUCC_8998=m +CONFIG_MSM_MMCC_8998=m +CONFIG_QCM_DISPCC_2290=m +CONFIG_QCS_GCC_404=y +CONFIG_SA_CAMCC_8775P=m +CONFIG_QCS_GCC_8300=m +CONFIG_SC_CAMCC_7180=m +CONFIG_SC_CAMCC_7280=m +CONFIG_SC_CAMCC_8280XP=m +CONFIG_SA_DISPCC_8775P=m +CONFIG_SC_DISPCC_7180=m +CONFIG_SC_DISPCC_7280=m +CONFIG_SC_DISPCC_8280XP=m +CONFIG_SA_GPUCC_8775P=m +CONFIG_SAR_GPUCC_2130P=m +CONFIG_SC_GCC_8180X=m +CONFIG_SC_GPUCC_7180=m +CONFIG_SC_GPUCC_7280=m +CONFIG_SC_GPUCC_8280XP=m +CONFIG_SC_LPASSCC_7280=m +CONFIG_SC_LPASSCC_8280XP=m +CONFIG_SC_LPASS_CORECC_7180=m +CONFIG_SC_LPASS_CORECC_7280=m +CONFIG_SC_VIDEOCC_7180=m +CONFIG_SC_VIDEOCC_7280=m +CONFIG_SDM_CAMCC_845=m +CONFIG_SDM_MMCC_660=m +CONFIG_SDM_GPUCC_660=m +CONFIG_QCS_TURING_404=m +CONFIG_QCS_Q6SSTOP_404=m +CONFIG_QDU_ECPRICC_1000=m +CONFIG_SDM_GPUCC_845=m +CONFIG_SDM_VIDEOCC_845=m +CONFIG_SDM_DISPCC_845=m +CONFIG_SDM_LPASSCC_845=m +CONFIG_SDX_GCC_75=m +CONFIG_SM_CAMCC_6350=m +CONFIG_SM_CAMCC_7150=m +CONFIG_SM_CAMCC_8250=m +CONFIG_SM_CAMCC_8450=m +CONFIG_SM_CAMCC_8550=m +CONFIG_SM_CAMCC_8650=m +CONFIG_SM_DISPCC_6115=m +CONFIG_SM_DISPCC_6125=m +CONFIG_SM_DISPCC_7150=m +CONFIG_SM_DISPCC_8250=m +CONFIG_SM_DISPCC_6350=m +CONFIG_SM_DISPCC_6375=m +CONFIG_SM_DISPCC_8450=m +CONFIG_SM_DISPCC_8550=m +CONFIG_SM_DISPCC_8750=m +CONFIG_SM_GCC_4450=m +CONFIG_SM_GCC_8750=m +CONFIG_SM_GPUCC_6115=m +CONFIG_SM_GPUCC_6125=m +CONFIG_SM_GPUCC_6375=m +CONFIG_SM_GPUCC_6350=m +CONFIG_SM_GPUCC_8150=m +CONFIG_SM_GPUCC_8250=m +CONFIG_SM_GPUCC_8350=m +CONFIG_SM_GPUCC_8450=m +CONFIG_SM_GPUCC_8550=m +CONFIG_SM_GPUCC_8650=m +CONFIG_SM_TCSRCC_8550=m +CONFIG_SM_TCSRCC_8650=m +CONFIG_SA_VIDEOCC_8775P=m +CONFIG_SM_VIDEOCC_7150=m +CONFIG_SM_VIDEOCC_8150=m +CONFIG_SM_VIDEOCC_8250=m +CONFIG_SM_VIDEOCC_8350=m +CONFIG_SM_VIDEOCC_8550=m +CONFIG_SPMI_PMIC_CLKDIV=m +CONFIG_QCOM_HFPLL=y +CONFIG_KPSS_XCC=m +CONFIG_CLK_GFM_LPASS_SM8250=m +CONFIG_SM_VIDEOCC_8450=m +CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y +CONFIG_CLK_RENESAS_VBATTB=m +CONFIG_SPRD_COMMON_CLK=m +CONFIG_SUN6I_RTC_CCU=m +CONFIG_XILINX_VCU=m +CONFIG_COMMON_CLK_XLNX_CLKWZRD=m +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_OMAP=m +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_HWSPINLOCK_SPRD=m +CONFIG_HWSPINLOCK_SUN6I=m +CONFIG_TEGRA186_TIMER=y +CONFIG_CLKSRC_STM32_LP=y +CONFIG_RENESAS_OSTM=y +CONFIG_ARM_MHU=m +CONFIG_ARM_MHU_V2=m +CONFIG_ARM_MHU_V3=m +CONFIG_IMX_MBOX=m +CONFIG_PLATFORM_MHU=m +CONFIG_PL320_MBOX=y +CONFIG_OMAP2PLUS_MBOX=m +CONFIG_ROCKCHIP_MBOX=y +CONFIG_ALTERA_MBOX=m +CONFIG_HI3660_MBOX=m +CONFIG_HI6220_MBOX=m +CONFIG_MAILBOX_TEST=m +CONFIG_QCOM_APCS_IPC=y +CONFIG_TEGRA_HSP_MBOX=y +CONFIG_XGENE_SLIMPRO_MBOX=m +CONFIG_MTK_ADSP_MBOX=m +# CONFIG_MTK_GPUEB_MBOX is not set +CONFIG_SPRD_MBOX=m +CONFIG_QCOM_CPUCP_MBOX=m +CONFIG_QCOM_IPCC=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_QCOM_DEBUG=y +CONFIG_ARM_SMMU_V3=y +CONFIG_ARM_SMMU_V3_SVA=y +CONFIG_QCOM_IOMMU=y +CONFIG_IOMMUFD=m +CONFIG_ROCKCHIP_IOMMU=y +CONFIG_SUN50I_IOMMU=y +CONFIG_TEGRA_IOMMU_SMMU=y +CONFIG_APPLE_DART=m +CONFIG_MTK_IOMMU=m +CONFIG_VIRTIO_IOMMU=y +CONFIG_SPRD_IOMMU=m +CONFIG_REMOTEPROC_CDEV=y +CONFIG_IMX_REMOTEPROC=m +CONFIG_IMX_DSP_REMOTEPROC=m +CONFIG_MTK_SCP=m +CONFIG_QCOM_Q6V5_ADSP=m +CONFIG_QCOM_Q6V5_MSS=m +CONFIG_QCOM_Q6V5_PAS=m +CONFIG_QCOM_Q6V5_WCSS=m +CONFIG_QCOM_SYSMON=m +CONFIG_QCOM_WCNSS_PIL=m +CONFIG_RCAR_REMOTEPROC=m +CONFIG_STM32_RPROC=m +CONFIG_TI_K3_DSP_REMOTEPROC=m +CONFIG_TI_K3_R5_REMOTEPROC=m +CONFIG_XLNX_R5_REMOTEPROC=m +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=m +CONFIG_RPMSG_QCOM_SMD=y +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_AMD=m +CONFIG_SOUNDWIRE_INTEL=m +CONFIG_SOUNDWIRE_QCOM=m +CONFIG_APPLE_MAILBOX=m +CONFIG_APPLE_RTKIT=m +CONFIG_APPLE_SART=m +CONFIG_FSL_DPAA=y +CONFIG_FSL_DPAA_CHECKING=y +CONFIG_FSL_BMAN_TEST=m +CONFIG_QUICC_ENGINE=y +CONFIG_FSL_MC_DPIO=m +CONFIG_DPAA2_CONSOLE=m +CONFIG_FSL_RCPM=y +CONFIG_A64FX_DIAG=y +CONFIG_KUNPENG_HCCS=m +CONFIG_SOC_IMX9=m +CONFIG_LITEX_SOC_CONTROLLER=m +CONFIG_MTK_CMDQ=m +CONFIG_MTK_DEVAPC=m +CONFIG_MTK_DVFSRC=m +CONFIG_MTK_PMIC_WRAP=m +CONFIG_MTK_SVS=m +CONFIG_WPCM450_SOC=m +CONFIG_QCOM_AOSS_QMP=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QCOM_GENI_SE=y +CONFIG_QCOM_GSBI=m +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_OCMEM=m +CONFIG_QCOM_PMIC_PDCHARGER_ULOG=m +CONFIG_QCOM_PMIC_GLINK=y +CONFIG_QCOM_RAMP_CTRL=m +CONFIG_QCOM_RMTFS_MEM=m +CONFIG_QCOM_RPM_MASTER_STATS=m +CONFIG_QCOM_RPMH=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_SMP2P=y +CONFIG_QCOM_SMSM=y +CONFIG_QCOM_SOCINFO=m +CONFIG_QCOM_SPM=y +CONFIG_QCOM_STATS=m +CONFIG_QCOM_WCNSS_CTRL=m +CONFIG_QCOM_APR=m +CONFIG_QCOM_ICC_BWMON=m +CONFIG_QCOM_PBS=m +# CONFIG_ARCH_R9A09G047 is not set +CONFIG_ROCKCHIP_IODOMAIN=m +CONFIG_ROCKCHIP_DTPM=m +# CONFIG_ARCH_TEGRA_264_SOC is not set +CONFIG_SOC_TEGRA_CBB=m +CONFIG_TI_PRUSS=m +CONFIG_OWL_PM_DOMAINS=y +CONFIG_ARM_SCMI_POWER_DOMAIN=m +CONFIG_IMX_SCU_PD=y +CONFIG_QCOM_CPR=y +CONFIG_QCOM_RPMHPD=y +CONFIG_QCOM_RPMPD=y +CONFIG_TI_SCI_PM_DOMAINS=m +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y +CONFIG_ARM_IMX_BUS_DEVFREQ=m +CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m +CONFIG_ARM_TEGRA_DEVFREQ=m +CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m +CONFIG_ARM_RK3399_DMC_DEVFREQ=m +CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m +CONFIG_EXTCON_ADC_JACK=m +CONFIG_EXTCON_FSA9480=m +CONFIG_EXTCON_GPIO=m +CONFIG_EXTCON_LC824206XA=m +CONFIG_EXTCON_MAX14577=m +CONFIG_EXTCON_MAX3355=m +CONFIG_EXTCON_MAX77693=m +CONFIG_EXTCON_MAX77843=m +CONFIG_EXTCON_MAX8997=m +CONFIG_EXTCON_PALMAS=m +CONFIG_EXTCON_PTN5150=m +CONFIG_EXTCON_QCOM_SPMI_MISC=m +CONFIG_EXTCON_RT8973A=m +CONFIG_EXTCON_SM5502=m +CONFIG_EXTCON_USB_GPIO=m +CONFIG_EXTCON_USBC_CROS_EC=m +CONFIG_EXTCON_USBC_TUSB320=m +CONFIG_EXTCON_RTK_TYPE_C=m +CONFIG_ARM_PL172_MPMC=m +CONFIG_OMAP_GPMC=y +CONFIG_FPGA_DFL_EMIF=m +CONFIG_FSL_IFC=y +CONFIG_RENESAS_RPCIF=m +CONFIG_STM32_FMC2_EBI=m +CONFIG_TEGRA210_EMC=m +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_ADIS16201=m +CONFIG_ADIS16209=m +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXL372_I2C=m +CONFIG_ADXL380_SPI=m +CONFIG_ADXL380_I2C=m +CONFIG_BMA220=m +CONFIG_BMA400=m +CONFIG_BMC150_ACCEL=m +CONFIG_BMI088_ACCEL=m +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DMARD06=m +CONFIG_DMARD09=m +CONFIG_DMARD10=m +CONFIG_FXLS8962AF_I2C=m +CONFIG_FXLS8962AF_SPI=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m +CONFIG_IIO_KX022A_SPI=m +CONFIG_IIO_KX022A_I2C=m +CONFIG_KXSD9=m +CONFIG_KXCJK1013=m +CONFIG_MC3230=m +CONFIG_MMA7455_I2C=m +CONFIG_MMA7455_SPI=m +CONFIG_MMA7660=m +CONFIG_MMA8452=m +CONFIG_MMA9551=m +CONFIG_MMA9553=m +CONFIG_MSA311=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +CONFIG_SCA3000=m +CONFIG_SCA3300=m +CONFIG_STK8312=m +CONFIG_STK8BA50=m +CONFIG_AD4000=m +CONFIG_AD4030=m +CONFIG_AD4130=m +CONFIG_AD4695=m +CONFIG_AD4851=m +CONFIG_AD7091R5=m +CONFIG_AD7091R8=m +CONFIG_AD7124=m +CONFIG_AD7173=m +CONFIG_AD7191=m +CONFIG_AD7192=m +CONFIG_AD7266=m +CONFIG_AD7280=m +CONFIG_AD7291=m +CONFIG_AD7292=m +CONFIG_AD7298=m +CONFIG_AD7380=m +CONFIG_AD7476=m +CONFIG_AD7606_IFACE_PARALLEL=m +CONFIG_AD7606_IFACE_SPI=m +CONFIG_AD7625=m +CONFIG_AD7766=m +CONFIG_AD7768_1=m +CONFIG_AD7779=m +CONFIG_AD7780=m +CONFIG_AD7791=m +CONFIG_AD7793=m +CONFIG_AD7887=m +CONFIG_AD7923=m +CONFIG_AD7944=m +CONFIG_AD7949=m +CONFIG_AD799X=m +CONFIG_AD9467=m +CONFIG_ADI_AXI_ADC=m +CONFIG_AXP20X_ADC=m +CONFIG_AXP288_ADC=m +CONFIG_BERLIN2_ADC=m +CONFIG_CC10001_ADC=m +CONFIG_CPCAP_ADC=m +CONFIG_DA9150_GPADC=m +CONFIG_DLN2_ADC=m +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_GEHC_PMC_ADC=m +CONFIG_HI8435=m +CONFIG_HX711=m +CONFIG_INA2XX_ADC=m +CONFIG_IMX7D_ADC=m +CONFIG_IMX8QXP_ADC=m +CONFIG_IMX93_ADC=m +CONFIG_LP8788_ADC=m +CONFIG_LTC2309=m +CONFIG_LTC2471=m +CONFIG_LTC2485=m +CONFIG_LTC2496=m +CONFIG_LTC2497=m +CONFIG_MAX1027=m +CONFIG_MAX11100=m +CONFIG_MAX1118=m +CONFIG_MAX11205=m +CONFIG_MAX11410=m +CONFIG_MAX1241=m +CONFIG_MAX1363=m +CONFIG_MAX34408=m +CONFIG_MAX77541_ADC=m +CONFIG_MAX9611=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_MCP3564=m +CONFIG_MCP3911=m +CONFIG_MEDIATEK_MT6359_AUXADC=m +CONFIG_MEDIATEK_MT6360_ADC=m +CONFIG_MEDIATEK_MT6370_ADC=m +CONFIG_MEDIATEK_MT6577_AUXADC=m +CONFIG_MEN_Z188_ADC=m +CONFIG_MP2629_ADC=m +CONFIG_NAU7802=m +CONFIG_NPCM_ADC=m +CONFIG_PAC1934=m +CONFIG_PALMAS_GPADC=m +CONFIG_QCOM_SPMI_RRADC=m +CONFIG_QCOM_SPMI_IADC=m +CONFIG_QCOM_SPMI_VADC=m +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_RN5T618_ADC=m +CONFIG_ROCKCHIP_SARADC=m +CONFIG_RICHTEK_RTQ6056=m +CONFIG_RZG2L_ADC=m +CONFIG_SC27XX_ADC=m +CONFIG_SD_ADC_MODULATOR=m +CONFIG_STM32_ADC_CORE=m +CONFIG_STM32_ADC=m +CONFIG_STM32_DFSDM_ADC=m +CONFIG_STMPE_ADC=m +CONFIG_SUN20I_GPADC=m +CONFIG_TI_ADC081C=m +CONFIG_TI_ADC0832=m +CONFIG_TI_ADC084S021=m +CONFIG_TI_ADC108S102=m +CONFIG_TI_ADC12138=m +CONFIG_TI_ADC128S052=m +CONFIG_TI_ADC161S626=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS1100=m +CONFIG_TI_ADS1119=m +CONFIG_TI_ADS124S08=m +CONFIG_TI_ADS1298=m +CONFIG_TI_ADS131E08=m +CONFIG_TI_ADS7924=m +CONFIG_TI_ADS7950=m +CONFIG_TI_ADS8344=m +CONFIG_TI_ADS8688=m +CONFIG_TI_AM335X_ADC=m +CONFIG_TI_LMP92064=m +CONFIG_TI_TLC4541=m +CONFIG_TI_TSC2046=m +CONFIG_TWL4030_MADC=m +CONFIG_TWL6030_GPADC=m +CONFIG_VF610_ADC=m +CONFIG_VIPERBOARD_ADC=m +CONFIG_XILINX_XADC=m +CONFIG_XILINX_AMS=m +CONFIG_AD74115=m +CONFIG_AD74413R=m +CONFIG_IIO_RESCALE=m +CONFIG_AD8366=m +CONFIG_ADA4250=m +CONFIG_HMC425=m +CONFIG_AD7150=m +CONFIG_AD7746=m +CONFIG_AOSONG_AGS02MA=m +CONFIG_ATLAS_PH_SENSOR=m +CONFIG_ATLAS_EZO_SENSOR=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_ENS160=m +CONFIG_IAQCORE=m +CONFIG_PMS7003=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m +CONFIG_SCD4X=m +CONFIG_SENSIRION_SGP30=m +CONFIG_SENSIRION_SGP40=m +CONFIG_SPS30_I2C=m +CONFIG_SPS30_SERIAL=m +CONFIG_SENSEAIR_SUNRISE_CO2=m +CONFIG_VZ89X=m +CONFIG_IIO_CROS_EC_SENSORS_CORE=m +CONFIG_IIO_CROS_EC_SENSORS=m +CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m +CONFIG_IIO_SCMI=m +CONFIG_IIO_SSP_SENSORS_COMMONS=m +CONFIG_IIO_SSP_SENSORHUB=m +CONFIG_AD3530R=m +CONFIG_AD3552R_HS=m +CONFIG_AD3552R=m +CONFIG_AD5064=m +CONFIG_AD5360=m +CONFIG_AD5380=m +CONFIG_AD5421=m +CONFIG_AD5449=m +CONFIG_AD5592R=m +CONFIG_AD5593R=m +CONFIG_AD5504=m +CONFIG_AD5624R_SPI=m +CONFIG_AD9739A=m +CONFIG_ADI_AXI_DAC=m +CONFIG_LTC2688=m +CONFIG_AD5686_SPI=m +CONFIG_AD5696_I2C=m +CONFIG_AD5755=m +CONFIG_AD5758=m +CONFIG_AD5761=m +CONFIG_AD5764=m +CONFIG_AD5766=m +CONFIG_AD5770R=m +CONFIG_AD5791=m +CONFIG_AD7293=m +CONFIG_AD7303=m +CONFIG_AD8460=m +CONFIG_AD8801=m +CONFIG_BD79703=m +CONFIG_DPOT_DAC=m +CONFIG_DS4424=m +CONFIG_LTC1660=m +CONFIG_LTC2632=m +CONFIG_M62332=m +CONFIG_MAX517=m +CONFIG_MAX5522=m +CONFIG_MAX5821=m +CONFIG_MCP4725=m +CONFIG_MCP4728=m +CONFIG_MCP4821=m +CONFIG_MCP4922=m +CONFIG_STM32_DAC=m +CONFIG_TI_DAC082S085=m +CONFIG_TI_DAC5571=m +CONFIG_TI_DAC7311=m +CONFIG_TI_DAC7612=m +CONFIG_VF610_DAC=m +CONFIG_IIO_SIMPLE_DUMMY=m +CONFIG_ADMV8818=m +CONFIG_AD9523=m +CONFIG_ADF4350=m +CONFIG_ADF4371=m +CONFIG_ADF4377=m +CONFIG_ADMFM2000=m +CONFIG_ADMV1013=m +CONFIG_ADMV1014=m +CONFIG_ADMV4420=m +CONFIG_ADRF6780=m +CONFIG_ADIS16080=m +CONFIG_ADIS16130=m +CONFIG_ADIS16136=m +CONFIG_ADIS16260=m +CONFIG_ADXRS290=m +CONFIG_ADXRS450=m +CONFIG_BMG160=m +CONFIG_FXAS21002C=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_MPU3050_I2C=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_ITG3200=m +CONFIG_AFE4403=m +CONFIG_AFE4404=m +CONFIG_MAX30100=m +CONFIG_MAX30102=m +CONFIG_AM2315=m +CONFIG_DHT11=m +CONFIG_ENS210=m +CONFIG_HDC100X=m +CONFIG_HDC2010=m +CONFIG_HDC3020=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HTS221=m +CONFIG_HTU21=m +CONFIG_SI7005=m +CONFIG_SI7020=m +CONFIG_ADIS16400=m +CONFIG_ADIS16460=m +CONFIG_ADIS16475=m +CONFIG_ADIS16480=m +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_BMI270_I2C=m +CONFIG_BMI270_SPI=m +CONFIG_BMI323_I2C=m +CONFIG_BMI323_SPI=m +CONFIG_BOSCH_BNO055_SERIAL=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_KMX61=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_INV_MPU6050_SPI=m +CONFIG_SMI240=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_IIO_ST_LSM9DS0=m +CONFIG_ACPI_ALS=m +CONFIG_ADJD_S311=m +CONFIG_ADUX1020=m +CONFIG_AL3010=m +CONFIG_AL3320A=m +CONFIG_APDS9160=m +CONFIG_APDS9300=m +CONFIG_APDS9306=m +CONFIG_APDS9960=m +CONFIG_AS73211=m +CONFIG_BH1745=m +CONFIG_BH1750=m +CONFIG_BH1780=m +CONFIG_CM32181=m +CONFIG_CM3232=m +CONFIG_CM3323=m +CONFIG_CM3605=m +CONFIG_CM36651=m +CONFIG_IIO_CROS_EC_LIGHT_PROX=m +CONFIG_GP2AP002=m +CONFIG_GP2AP020A00F=m +CONFIG_IQS621_ALS=m +CONFIG_SENSORS_ISL29018=m +CONFIG_SENSORS_ISL29028=m +CONFIG_ISL29125=m +CONFIG_ISL76682=m +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_PROX=m +CONFIG_JSA1212=m +CONFIG_ROHM_BU27034=m +CONFIG_RPR0521=m +CONFIG_SENSORS_LM3533=m +CONFIG_LTR390=m +CONFIG_LTR501=m +CONFIG_LTRF216A=m +CONFIG_LV0104CS=m +CONFIG_MAX44000=m +CONFIG_MAX44009=m +CONFIG_NOA1305=m +CONFIG_OPT3001=m +CONFIG_OPT4001=m +CONFIG_PA12203001=m +CONFIG_SI1133=m +CONFIG_SI1145=m +CONFIG_STK3310=m +CONFIG_ST_UVIS25=m +CONFIG_TCS3414=m +CONFIG_TCS3472=m +CONFIG_SENSORS_TSL2563=m +CONFIG_TSL2583=m +CONFIG_TSL2591=m +CONFIG_TSL2772=m +CONFIG_TSL4531=m +CONFIG_US5182D=m +CONFIG_VCNL4000=m +CONFIG_VCNL4035=m +CONFIG_VEML3235=m +CONFIG_VEML6030=m +CONFIG_VEML6040=m +CONFIG_VEML6046X00=m +CONFIG_VEML6070=m +CONFIG_VEML6075=m +CONFIG_VL6180=m +CONFIG_ZOPT2201=m +CONFIG_AF8133J=m +CONFIG_AK8974=m +CONFIG_AK09911=m +CONFIG_ALS31300=m +CONFIG_BMC150_MAGN_I2C=m +CONFIG_BMC150_MAGN_SPI=m +CONFIG_MAG3110=m +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +CONFIG_MMC35240=m +CONFIG_SENSORS_HMC5843_I2C=m +CONFIG_SENSORS_HMC5843_SPI=m +CONFIG_SENSORS_RM3100_I2C=m +CONFIG_SENSORS_RM3100_SPI=m +CONFIG_TI_TMAG5273=m +CONFIG_YAMAHA_YAS530=m +CONFIG_IIO_MUX=m +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_STM32_LPTIMER_TRIGGER=m +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_IQS624_POS=m +CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m +CONFIG_AD5110=m +CONFIG_AD5272=m +CONFIG_DS1803=m +CONFIG_MAX5432=m +CONFIG_MAX5481=m +CONFIG_MAX5487=m +CONFIG_MCP4018=m +CONFIG_MCP4131=m +CONFIG_MCP4531=m +CONFIG_MCP41010=m +CONFIG_TPL0102=m +CONFIG_X9250=m +CONFIG_LMP91000=m +CONFIG_ABP060MG=m +CONFIG_ROHM_BM1390=m +CONFIG_BMP280=m +CONFIG_IIO_CROS_EC_BARO=m +CONFIG_DLHL60D=m +CONFIG_DPS310=m +CONFIG_HID_SENSOR_PRESS=m +CONFIG_HP03=m +CONFIG_HSC030PA=m +CONFIG_ICP10100=m +CONFIG_MPL115_I2C=m +CONFIG_MPL115_SPI=m +CONFIG_MPL3115=m +CONFIG_MPRLS0025PA_I2C=m +CONFIG_MPRLS0025PA_SPI=m +CONFIG_MS5611=m +CONFIG_MS5611_I2C=m +CONFIG_MS5611_SPI=m +CONFIG_MS5637=m +CONFIG_IIO_ST_PRESS=m +CONFIG_T5403=m +CONFIG_HP206C=m +CONFIG_ZPA2326=m +CONFIG_AS3935=m +CONFIG_CROS_EC_MKBP_PROXIMITY=m +CONFIG_IRSD200=m +CONFIG_ISL29501=m +CONFIG_LIDAR_LITE_V2=m +CONFIG_MB1232=m +CONFIG_PING=m +CONFIG_RFD77402=m +CONFIG_SRF04=m +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +CONFIG_SX9500=m +CONFIG_SRF08=m +CONFIG_VCNL3020=m +CONFIG_VL53L0X_I2C=m +CONFIG_AD2S90=m +CONFIG_AD2S1200=m +CONFIG_AD2S1210=m +CONFIG_IQS620AT_TEMP=m +CONFIG_LTC2983=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_HID_SENSOR_TEMP=m +CONFIG_MLX90614=m +CONFIG_MLX90632=m +CONFIG_MLX90635=m +CONFIG_TMP006=m +CONFIG_TMP007=m +CONFIG_TMP117=m +CONFIG_TSYS01=m +CONFIG_TSYS02D=m +CONFIG_MAX30208=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +CONFIG_MCP9600=m +CONFIG_NTB=m +CONFIG_NTB_MSI=y +CONFIG_NTB_IDT=m +CONFIG_NTB_EPF=m +CONFIG_NTB_SWITCHTEC=m +CONFIG_NTB_PINGPONG=m +CONFIG_NTB_TOOL=m +CONFIG_NTB_PERF=m +CONFIG_NTB_TRANSPORT=m +CONFIG_PWM=y +CONFIG_PWM_APPLE=m +CONFIG_PWM_ATMEL_HLCDC_PWM=m +CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_AXI_PWMGEN=m +CONFIG_PWM_BERLIN=m +CONFIG_PWM_CLK=m +CONFIG_PWM_CROS_EC=m +CONFIG_PWM_DWC=m +CONFIG_PWM_FSL_FTM=m +CONFIG_PWM_GPIO=m +CONFIG_PWM_HIBVT=m +CONFIG_PWM_IMX1=m +CONFIG_PWM_IMX27=m +CONFIG_PWM_IMX_TPM=m +CONFIG_PWM_IQS620A=m +CONFIG_PWM_KEEMBAY=m +CONFIG_PWM_LP3943=m +CONFIG_PWM_MEDIATEK=m +CONFIG_PWM_MESON=m +CONFIG_PWM_MTK_DISP=m +CONFIG_PWM_NTXEC=m +CONFIG_PWM_OMAP_DMTIMER=m +CONFIG_PWM_PCA9685=m +CONFIG_PWM_RENESAS_TPU=m +CONFIG_PWM_ROCKCHIP=m +CONFIG_PWM_SL28CPLD=m +CONFIG_PWM_SPRD=m +CONFIG_PWM_STM32=m +CONFIG_PWM_STM32_LP=m +CONFIG_PWM_STMPE=y +CONFIG_PWM_SUN4I=m +CONFIG_PWM_TEGRA=m +CONFIG_PWM_TIECAP=m +CONFIG_PWM_TIEHRPWM=m +CONFIG_PWM_TWL=m +CONFIG_PWM_TWL_LED=m +CONFIG_PWM_VISCONTI=m +CONFIG_PWM_XILINX=m +CONFIG_AL_FIC=y +CONFIG_XILINX_INTC=y +CONFIG_STM32MP_EXTI=m +CONFIG_QCOM_PDC=y +CONFIG_QCOM_MPM=y +CONFIG_TI_SCI_INTR_IRQCHIP=y +CONFIG_TI_SCI_INTA_IRQCHIP=y +CONFIG_IPACK_BUS=m +CONFIG_BOARD_TPCI200=m +CONFIG_SERIAL_IPOCTAL=m +CONFIG_RESET_A10SR=m +CONFIG_RESET_BERLIN=y +CONFIG_RESET_GPIO=m +CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=m +CONFIG_RESET_MCHP_SPARX5=y +CONFIG_RESET_QCOM_AOSS=y +CONFIG_RESET_QCOM_PDC=m +CONFIG_RESET_RZG2L_USBPHY_CTRL=y +CONFIG_RESET_SCMI=m +CONFIG_RESET_TI_SCI=m +CONFIG_RESET_TI_TPS380X=m +CONFIG_COMMON_RESET_HI3660=m +CONFIG_COMMON_RESET_HI6220=m +CONFIG_PHY_AIROHA_PCIE=m +CONFIG_PHY_CAN_TRANSCEIVER=m +CONFIG_PHY_NXP_PTN3222=m +CONFIG_PHY_SNPS_EUSB2=y +CONFIG_PHY_XGENE=y +CONFIG_PHY_SUN4I_USB=m +CONFIG_PHY_SUN50I_USB3=m +CONFIG_PHY_MESON8B_USB2=m +CONFIG_PHY_MESON_GXL_USB2=m +CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m +CONFIG_PHY_MESON_G12A_USB2=m +CONFIG_PHY_MESON_G12A_USB3_PCIE=m +CONFIG_PHY_MESON_AXG_MIPI_DPHY=m +CONFIG_BCM_KONA_USB2_PHY=m +CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_PHY_CADENCE_DPHY_RX=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_SALVO=m +CONFIG_PHY_FSL_IMX8MQ_USB=m +CONFIG_PHY_MIXEL_LVDS_PHY=m +CONFIG_PHY_MIXEL_MIPI_DPHY=m +CONFIG_PHY_FSL_IMX8M_PCIE=m +CONFIG_PHY_FSL_IMX8QM_HSIO=m +CONFIG_PHY_FSL_LYNX_28G=m +CONFIG_PHY_HI6220_USB=m +CONFIG_PHY_HI3660_USB=m +CONFIG_PHY_HI3670_USB=m +CONFIG_PHY_HI3670_PCIE=m +CONFIG_PHY_HISTB_COMBPHY=m +CONFIG_PHY_HISI_INNO_USB2=m +CONFIG_PHY_INTEL_KEEMBAY_EMMC=m +CONFIG_PHY_INTEL_KEEMBAY_USB=m +CONFIG_PHY_BERLIN_SATA=m +CONFIG_PHY_BERLIN_USB=m +CONFIG_PHY_MVEBU_A3700_COMPHY=m +CONFIG_PHY_MVEBU_A3700_UTMI=m +CONFIG_PHY_MVEBU_A38X_COMPHY=m +CONFIG_PHY_MVEBU_CP110_COMPHY=m +CONFIG_PHY_MVEBU_CP110_UTMI=m +CONFIG_PHY_PXA_28NM_HSIC=m +CONFIG_PHY_PXA_28NM_USB2=m +CONFIG_PHY_MTK_PCIE=m +CONFIG_PHY_MTK_XFI_TPHY=m +CONFIG_PHY_MTK_TPHY=m +CONFIG_PHY_MTK_XSPHY=m +CONFIG_PHY_MTK_HDMI=m +CONFIG_PHY_MTK_MIPI_CSI_0_5=m +CONFIG_PHY_MTK_MIPI_DSI=m +CONFIG_PHY_MTK_DP=m +CONFIG_PHY_CPCAP_USB=m +CONFIG_PHY_MAPPHONE_MDM6600=m +CONFIG_PHY_OCELOT_SERDES=m +CONFIG_PHY_QCOM_APQ8064_SATA=m +CONFIG_PHY_QCOM_EDP=m +CONFIG_PHY_QCOM_IPQ4019_USB=m +CONFIG_PHY_QCOM_IPQ806X_SATA=m +CONFIG_PHY_QCOM_PCIE2=m +CONFIG_PHY_QCOM_QMP=y +CONFIG_PHY_QCOM_QMP_USB_LEGACY=m +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_PHY_QCOM_EUSB2_REPEATER=y +CONFIG_PHY_QCOM_M31_USB=m +CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP=y +CONFIG_PHY_QCOM_USB_HS=m +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y +CONFIG_PHY_QCOM_USB_HSIC=m +CONFIG_PHY_QCOM_USB_HS_28NM=m +CONFIG_PHY_QCOM_USB_SS=m +CONFIG_PHY_QCOM_IPQ806X_USB=m +CONFIG_PHY_QCOM_SGMII_ETH=m +CONFIG_PHY_RTK_RTD_USB2PHY=m +CONFIG_PHY_RTK_RTD_USB3PHY=m +CONFIG_PHY_R8A779F0_ETHERNET_SERDES=m +CONFIG_PHY_RCAR_GEN2=m +CONFIG_PHY_RCAR_GEN3_PCIE=m +CONFIG_PHY_RCAR_GEN3_USB2=m +CONFIG_PHY_RCAR_GEN3_USB3=m +CONFIG_PHY_ROCKCHIP_DP=m +CONFIG_PHY_ROCKCHIP_DPHY_RX0=m +CONFIG_PHY_ROCKCHIP_EMMC=m +CONFIG_PHY_ROCKCHIP_INNO_HDMI=m +CONFIG_PHY_ROCKCHIP_INNO_USB2=m +CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m +CONFIG_PHY_ROCKCHIP_PCIE=m +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m +CONFIG_PHY_ROCKCHIP_TYPEC=m +CONFIG_PHY_ROCKCHIP_USB=m +CONFIG_PHY_ROCKCHIP_USBDP=m +CONFIG_PHY_SAMSUNG_USB2=m +CONFIG_PHY_STM32_COMBOPHY=m +CONFIG_PHY_STM32_USBPHYC=m +CONFIG_PHY_TEGRA_XUSB=m +CONFIG_OMAP_USB2=m +CONFIG_PHY_AM654_SERDES=m +CONFIG_PHY_J721E_WIZ=m +CONFIG_PHY_TUSB1210=m +CONFIG_PHY_XILINX_ZYNQMP=m +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y +CONFIG_ARM_SCMI_POWERCAP=m +CONFIG_DTPM=y +CONFIG_DTPM_CPU=y +CONFIG_QCOM_SPEL=y +CONFIG_MCB=m +CONFIG_MCB_PCI=m +CONFIG_MCB_LPC=m +CONFIG_ARM_CCI_PMU=y +CONFIG_ARM_CCN=y +CONFIG_ARM_CMN=m +CONFIG_ARM_SMMU_V3_PMU=m +CONFIG_ARM_DSU_PMU=m +CONFIG_FSL_IMX8_DDR_PMU=m +CONFIG_FSL_IMX9_DDR_PMU=m +CONFIG_QCOM_L2_PMU=y +CONFIG_QCOM_L3_PMU=y +CONFIG_XGENE_PMU=y +CONFIG_ARM_SPE_PMU=m +CONFIG_ARM_DMC620_PMU=m +CONFIG_MARVELL_CN10K_TAD_PMU=m +CONFIG_APPLE_M1_CPU_PMU=y +CONFIG_ALIBABA_UNCORE_DRW_PMU=m +CONFIG_HISI_PMU=m +CONFIG_HISI_PCIE_PMU=m +CONFIG_HNS3_PMU=m +CONFIG_MARVELL_CN10K_DDR_PMU=m +CONFIG_DWC_PCIE_PMU=m +CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m +CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m +CONFIG_AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m +CONFIG_MESON_DDR_PMU=m +CONFIG_CXL_PMU=m +CONFIG_MARVELL_PEM_PMU=m +CONFIG_USB4=m +CONFIG_ANDROID_BINDER_IPC=m +CONFIG_ANDROID_BINDERFS=m +CONFIG_LIBNVDIMM=y +CONFIG_BLK_DEV_PMEM=m +CONFIG_OF_PMEM=m +CONFIG_DEV_DAX=m +CONFIG_NVMEM_LAYOUT_SL28_VPD=m +CONFIG_NVMEM_LAYOUT_ONIE_TLV=m +CONFIG_NVMEM_APPLE_EFUSES=m +CONFIG_NVMEM_IMX_IIM=m +CONFIG_NVMEM_IMX_OCOTP=m +CONFIG_NVMEM_IMX_OCOTP_ELE=m +CONFIG_NVMEM_IMX_OCOTP_SCU=m +CONFIG_NVMEM_LAYERSCAPE_SFP=m +CONFIG_NVMEM_MESON_EFUSE=m +CONFIG_NVMEM_MESON_MX_EFUSE=m +CONFIG_NVMEM_MTK_EFUSE=m +CONFIG_NVMEM_QCOM_QFPROM=y +CONFIG_NVMEM_QCOM_SEC_QFPROM=m +CONFIG_NVMEM_RAVE_SP_EEPROM=m +CONFIG_NVMEM_RCAR_EFUSE=m +CONFIG_NVMEM_RMEM=m +CONFIG_NVMEM_ROCKCHIP_EFUSE=m +CONFIG_NVMEM_ROCKCHIP_OTP=m +CONFIG_NVMEM_SC27XX_EFUSE=m +CONFIG_NVMEM_SNVS_LPGPR=m +CONFIG_NVMEM_SPMI_SDAM=m +CONFIG_NVMEM_SPRD_EFUSE=m +CONFIG_NVMEM_STM32_ROMEM=m +CONFIG_NVMEM_SUNXI_SID=m +CONFIG_NVMEM_U_BOOT_ENV=m +CONFIG_NVMEM_ZYNQMP=y +CONFIG_STM=m +CONFIG_STM_DUMMY=m +CONFIG_STM_SOURCE_CONSOLE=m +CONFIG_STM_SOURCE_HEARTBEAT=m +CONFIG_STM_SOURCE_FTRACE=m +CONFIG_INTEL_TH=m +CONFIG_INTEL_TH_PCI=m +CONFIG_INTEL_TH_ACPI=m +CONFIG_INTEL_TH_GTH=m +CONFIG_INTEL_TH_STH=m +CONFIG_INTEL_TH_MSU=m +CONFIG_INTEL_TH_PTI=m +CONFIG_HISI_PTT=m +CONFIG_FPGA=m +CONFIG_FPGA_MGR_SOCFPGA=m +CONFIG_FPGA_MGR_SOCFPGA_A10=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_PR_IP_CORE_PLAT=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_STRATIX10_SOC=m +CONFIG_FPGA_MGR_XILINX_SELECTMAP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_MGR_ICE40_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +CONFIG_SOCFPGA_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_XILINX_PR_DECOUPLER=m +CONFIG_OF_FPGA_REGION=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL_AFU=m +CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m +CONFIG_FPGA_DFL_PCI=m +CONFIG_FPGA_MGR_ZYNQMP_FPGA=m +CONFIG_FPGA_MGR_VERSAL_FPGA=m +CONFIG_FPGA_MGR_MICROCHIP_SPI=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m +CONFIG_FSI=m +CONFIG_FSI_MASTER_GPIO=m +CONFIG_FSI_MASTER_HUB=m +CONFIG_FSI_MASTER_ASPEED=m +CONFIG_FSI_MASTER_I2CR=m +CONFIG_FSI_SCOM=m +CONFIG_FSI_SBEFIFO=m +CONFIG_FSI_OCC=m +CONFIG_I2CR_SCOM=m +CONFIG_TEE=m +CONFIG_OPTEE=m +CONFIG_ARM_TSTEE=m +CONFIG_MUX_ADG792A=m +CONFIG_MUX_ADGS1408=m +CONFIG_MUX_GPIO=m +CONFIG_SIOX=m +CONFIG_SIOX_BUS_GPIO=m +CONFIG_SLIM_QCOM_NGD_CTRL=m +CONFIG_INTERCONNECT_IMX=m +CONFIG_INTERCONNECT_IMX8MM=m +CONFIG_INTERCONNECT_IMX8MN=m +CONFIG_INTERCONNECT_IMX8MQ=m +CONFIG_INTERCONNECT_IMX8MP=m +CONFIG_INTERCONNECT_MTK=y +CONFIG_INTERCONNECT_MTK_DVFSRC_EMI=m +CONFIG_INTERCONNECT_MTK_MT8183=m +CONFIG_INTERCONNECT_MTK_MT8195=m +CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_MSM8916=m +CONFIG_INTERCONNECT_QCOM_MSM8937=m +CONFIG_INTERCONNECT_QCOM_MSM8939=m +CONFIG_INTERCONNECT_QCOM_MSM8953=m +CONFIG_INTERCONNECT_QCOM_MSM8976=m +CONFIG_INTERCONNECT_QCOM_MSM8996=m +CONFIG_INTERCONNECT_QCOM_OSM_L3=m +CONFIG_INTERCONNECT_QCOM_QCM2290=m +CONFIG_INTERCONNECT_QCOM_QCS404=m +CONFIG_INTERCONNECT_QCOM_QCS615=m +CONFIG_INTERCONNECT_QCOM_QCS8300=m +CONFIG_INTERCONNECT_QCOM_QDU1000=m +CONFIG_INTERCONNECT_QCOM_SA8775P=m +CONFIG_INTERCONNECT_QCOM_SAR2130P=m +CONFIG_INTERCONNECT_QCOM_SC7180=m +CONFIG_INTERCONNECT_QCOM_SC7280=m +CONFIG_INTERCONNECT_QCOM_SC8180X=m +CONFIG_INTERCONNECT_QCOM_SC8280XP=m +CONFIG_INTERCONNECT_QCOM_SDM660=m +CONFIG_INTERCONNECT_QCOM_SDM670=m +CONFIG_INTERCONNECT_QCOM_SDM845=m +CONFIG_INTERCONNECT_QCOM_SDX75=m +CONFIG_INTERCONNECT_QCOM_SM6115=m +CONFIG_INTERCONNECT_QCOM_SM6350=m +CONFIG_INTERCONNECT_QCOM_SM7150=m +CONFIG_INTERCONNECT_QCOM_SM8150=m +CONFIG_INTERCONNECT_QCOM_SM8250=m +CONFIG_INTERCONNECT_QCOM_SM8350=m +CONFIG_INTERCONNECT_QCOM_SM8450=m +CONFIG_INTERCONNECT_QCOM_SM8550=m +CONFIG_INTERCONNECT_QCOM_SM8650=m +CONFIG_INTERCONNECT_QCOM_X1E80100=y +CONFIG_COUNTER=m +CONFIG_INTERRUPT_CNT=m +CONFIG_RZ_MTU3_CNT=m +CONFIG_STM32_LPTIMER_CNT=m +CONFIG_STM32_TIMER_CNT=m +CONFIG_TI_ECAP_CAPTURE=m +CONFIG_TI_EQEP=m +CONFIG_MOST=m +CONFIG_MOST_USB_HDM=m +CONFIG_MOST_CDEV=m +CONFIG_MOST_SND=m +CONFIG_PECI=m +CONFIG_PECI_NPCM=m +CONFIG_HTE=y +CONFIG_HTE_TEGRA194=m +CONFIG_HTE_TEGRA194_TEST=m +CONFIG_CDX_BUS=y +CONFIG_CDX_CONTROLLER=m +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_SUPPORT_V4=y +CONFIG_XFS_SUPPORT_ASCII_CI=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_ONLINE_SCRUB is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_ZONEFS_FS=m +CONFIG_FS_DAX=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +CONFIG_FS_VERITY=y +CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=y +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=y +CONFIG_CUSE=m +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +CONFIG_OVERLAY_FS_XINO_AUTO=y +CONFIG_NETFS_DEBUG=y +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_CACHEFILES_ERROR_INJECTION=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS3_FS=m +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE_DEVICE_DUMP=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_INODE64=y +CONFIG_TMPFS_QUOTA=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_ORANGEFS_FS=m +CONFIG_ADFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=y +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_CMODE_FAVOURLZO=y +CONFIG_UBIFS_FS=m +CONFIG_UBIFS_FS_AUTHENTICATION=y +CONFIG_CRAMFS=m +CONFIG_CRAMFS_MTD=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_PSTORE_RAM=m +CONFIG_PSTORE_BLK=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_EROFS_FS_ZIP_DEFLATE=y +CONFIG_EROFS_FS_ZIP_ZSTD=y +CONFIG_EROFS_FS_PCPU_KTHREAD=y +# CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI is not set +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_NFSD_LEGACY_CLIENT_TRACKING=y +CONFIG_SUNRPC_DEBUG=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +CONFIG_CEPH_FS_SECURITY_LABEL=y +CONFIG_CIFS=m +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SWN_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_SMB_SERVER_SMBDIRECT=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +CONFIG_AFS_FSCACHE=y +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_UNICODE=y +CONFIG_KEYS_REQUEST_CACHE=y +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_TRUSTED_KEYS=y +CONFIG_USER_DECRYPTED_DATA=y +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_PROC_MEM_ALWAYS_FORCE=y +CONFIG_SECURITY=y +CONFIG_SECURITY_INFINIBAND=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_SMACK_NETFILTER=y +CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y +CONFIG_SECURITY_TOMOYO=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_SECURITY_SAFESETID=y +CONFIG_SECURITY_LOCKDOWN_LSM=y +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y +CONFIG_SECURITY_LANDLOCK=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_PLATFORM_KEYRING=y +CONFIG_INTEGRITY_MACHINE_KEYRING=y +CONFIG_IMA=y +CONFIG_IMA_KEXEC=y +CONFIG_IMA_DEFAULT_HASH_SHA256=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_ARCH_POLICY=y +CONFIG_IMA_APPRAISE_MODSIG=y +CONFIG_EVM=y +CONFIG_EVM_EXTRA_SMACK_XATTRS=y +CONFIG_EVM_ADD_XATTRS=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_LSM="landlock,lockdown,yama,integrity,apparmor" +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +CONFIG_ZERO_CALL_USED_REGS=y +CONFIG_FORTIFY_SOURCE=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_ECDSA=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XXHASH=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_GHASH_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_SM4_ARM64_CE=m +CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=m +CONFIG_CRYPTO_SM4_ARM64_CE_CCM=m +CONFIG_CRYPTO_SM4_ARM64_CE_GCM=m +CONFIG_CRYPTO_DEV_SUN4I_SS=m +CONFIG_CRYPTO_DEV_SUN8I_CE=m +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y +CONFIG_CRYPTO_DEV_SUN8I_SS=m +CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y +CONFIG_CRYPTO_DEV_FSL_CAAM=m +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m +CONFIG_CRYPTO_DEV_SAHARA=m +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +CONFIG_CRYPTO_DEV_CCP=y +CONFIG_CAVIUM_CPT=m +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +CONFIG_CRYPTO_DEV_MARVELL_CESA=m +CONFIG_CRYPTO_DEV_OCTEONTX_CPT=m +CONFIG_CRYPTO_DEV_OCTEONTX2_CPT=m +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4=m +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB=y +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS=y +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC=m +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU=m +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224=y +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m +CONFIG_CRYPTO_DEV_QAT_C3XXX=m +CONFIG_CRYPTO_DEV_QAT_C62X=m +CONFIG_CRYPTO_DEV_QAT_4XXX=m +CONFIG_CRYPTO_DEV_QAT_420XX=m +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m +CONFIG_CRYPTO_DEV_QAT_C62XVF=m +CONFIG_CRYPTO_DEV_QCE=m +CONFIG_CRYPTO_DEV_QCOM_RNG=m +CONFIG_CRYPTO_DEV_ROCKCHIP=m +CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG=y +CONFIG_CRYPTO_DEV_TEGRA=m +CONFIG_CRYPTO_DEV_ZYNQMP_AES=m +CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=m +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DEV_STM32_HASH=m +CONFIG_CRYPTO_DEV_STM32_CRYP=m +CONFIG_CRYPTO_DEV_SAFEXCEL=m +CONFIG_CRYPTO_DEV_CCREE=m +CONFIG_CRYPTO_DEV_HISI_SEC=m +CONFIG_CRYPTO_DEV_HISI_SEC2=m +CONFIG_CRYPTO_DEV_HISI_ZIP=m +CONFIG_CRYPTO_DEV_HISI_HPRE=m +CONFIG_CRYPTO_DEV_SA2UL=m +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_PKCS7_TEST_KEY=m +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +CONFIG_SYSTEM_EXTRA_CERTIFICATE=y +CONFIG_SECONDARY_TRUSTED_KEYRING=y +CONFIG_SYSTEM_BLACKLIST_KEYRING=y +CONFIG_SYSTEM_REVOCATION_LIST=y +CONFIG_TRACE_MMIO_ACCESS=y +CONFIG_XZ_DEC_TEST=m +CONFIG_SWIOTLB_DYNAMIC=y +CONFIG_DMA_RESTRICTED_POOL=y +CONFIG_DMA_NUMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_FONT_6x10=y +CONFIG_FONT_TER16x32=y +CONFIG_PRINTK_TIME=y +CONFIG_CONSOLE_LOGLEVEL_QUIET=3 +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_FRAME_WARN=1024 +CONFIG_VMLINUX_MAP=y +CONFIG_BUILTIN_MODULE_RANGES=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6 +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y +CONFIG_UBSAN=y +CONFIG_UBSAN_SHIFT=y +CONFIG_PAGE_POISONING=y +CONFIG_DEBUG_WX=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m +CONFIG_KFENCE=y +CONFIG_KFENCE_SAMPLE_INTERVAL=0 +CONFIG_HARDLOCKUP_DETECTOR=y +CONFIG_WQ_CPU_INTENSIVE_REPORT=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_CPUTIME=y +CONFIG_LATENCYTOP=y +CONFIG_BOOTTIME_TRACING=y +CONFIG_FUNCTION_GRAPH_RETVAL=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_BPF_KPROBE_OVERRIDE=y +CONFIG_USER_EVENTS=y +CONFIG_HIST_TRIGGERS=y +CONFIG_TRACE_EVENT_INJECT=y +CONFIG_RV=y +CONFIG_RV_MON_WWNR=y +CONFIG_SAMPLES=y +CONFIG_SAMPLE_TRACE_PRINTK=m +CONFIG_SAMPLE_TRACE_ARRAY=m +CONFIG_NOTIFIER_ERROR_INJECTION=m +CONFIG_FUNCTION_ERROR_INJECTION=y +CONFIG_TEST_BPF=m +CONFIG_MEMTEST=y diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index a58b1029592ce2..2fa154f5fdfe60 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -225,7 +225,7 @@ KBUILD_CFLAGS += $(cflags-y) all: zImage # With make 3.82 we cannot mix normal and wildcard targets -BOOT_TARGETS1 := zImage zImage.initrd uImage +BOOT_TARGETS1 := zImage zImage.initrd uImage vmlinux.strip BOOT_TARGETS2 := zImage% dtbImage% treeImage.% cuImage.% simpleImage.% uImage.% PHONY += $(BOOT_TARGETS1) $(BOOT_TARGETS2) diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h index 49039074b33fd5..f5a441ad94097d 100644 --- a/arch/powerpc/include/asm/uaccess.h +++ b/arch/powerpc/include/asm/uaccess.h @@ -15,11 +15,6 @@ #define TASK_SIZE_MAX TASK_SIZE_USER64 #endif -/* Threshold above which VMX copy path is used */ -#define VMX_COPY_THRESHOLD 3328 - -#define __access_ok __access_ok - #include /* @@ -355,62 +350,40 @@ do { \ extern unsigned long __copy_tofrom_user(void __user *to, const void __user *from, unsigned long size); -unsigned long __copy_tofrom_user_base(void __user *to, - const void __user *from, unsigned long size); - -unsigned long __copy_tofrom_user_power7_vmx(void __user *to, - const void __user *from, unsigned long size); - -static __always_inline bool will_use_vmx(unsigned long n) -{ - return IS_ENABLED(CONFIG_ALTIVEC) && cpu_has_feature(CPU_FTR_VMX_COPY) && - n > VMX_COPY_THRESHOLD; -} - -static __always_inline unsigned long -raw_copy_tofrom_user(void __user *to, const void __user *from, - unsigned long n, unsigned long dir) +#ifdef __powerpc64__ +static inline unsigned long +raw_copy_in_user(void __user *to, const void __user *from, unsigned long n) { unsigned long ret; - if (will_use_vmx(n) && enter_vmx_usercopy()) { - allow_user_access(to, dir); - ret = __copy_tofrom_user_power7_vmx(to, from, n); - prevent_user_access(dir); - exit_vmx_usercopy(); - - if (unlikely(ret)) { - allow_user_access(to, dir); - ret = __copy_tofrom_user_base(to, from, n); - prevent_user_access(dir); - } - return ret; - } - - allow_user_access(to, dir); + barrier_nospec(); + allow_user_access(to, KUAP_READ_WRITE); ret = __copy_tofrom_user(to, from, n); - prevent_user_access(dir); + prevent_user_access(KUAP_READ_WRITE); return ret; } +#endif /* __powerpc64__ */ -#ifdef CONFIG_PPC64 -static inline unsigned long -raw_copy_in_user(void __user *to, const void __user *from, unsigned long n) +static inline unsigned long raw_copy_from_user(void *to, + const void __user *from, unsigned long n) { - barrier_nospec(); - return raw_copy_tofrom_user(to, from, n, KUAP_READ_WRITE); -} -#endif /* CONFIG_PPC64 */ + unsigned long ret; -static inline unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long n) -{ - return raw_copy_tofrom_user((__force void __user *)to, from, n, KUAP_READ); + allow_user_access(NULL, KUAP_READ); + ret = __copy_tofrom_user((__force void __user *)to, from, n); + prevent_user_access(KUAP_READ); + return ret; } static inline unsigned long raw_copy_to_user(void __user *to, const void *from, unsigned long n) { - return raw_copy_tofrom_user(to, (__force const void __user *)from, n, KUAP_WRITE); + unsigned long ret; + + allow_user_access(to, KUAP_WRITE); + ret = __copy_tofrom_user(to, (__force const void __user *)from, n); + prevent_user_access(KUAP_WRITE); + return ret; } unsigned long __arch_clear_user(void __user *addr, unsigned long size); diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 3c4ca90e2ab772..ebc82f2744760a 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -360,6 +360,7 @@ struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) } return NULL; } +EXPORT_SYMBOL(pci_find_hose_for_OF_device); struct pci_controller *pci_find_controller_for_domain(int domain_nr) { @@ -1634,6 +1635,7 @@ int early_find_capability(struct pci_controller *hose, int bus, int devfn, { return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); } +EXPORT_SYMBOL_GPL(early_find_capability); struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) { diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c index 67c545f61f0d71..e33d6ecfc66568 100644 --- a/arch/powerpc/kernel/setup-common.c +++ b/arch/powerpc/kernel/setup-common.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -68,6 +69,7 @@ #include #include #include +#include #include #include "setup.h" @@ -931,6 +933,16 @@ void __init setup_arch(char **cmdline_p) */ initialize_cache_info(); + /* + * Lock down the kernel if booted in secure mode. This is required to + * maintain kernel integrity. + */ + if (IS_ENABLED(CONFIG_LOCK_DOWN_IN_SECURE_BOOT)) { + if (is_ppc_secureboot_enabled()) + security_lock_kernel_down("PowerNV Secure Boot mode", + LOCKDOWN_INTEGRITY_MAX); + } + /* Initialize RTAS if available. */ rtas_initialize(); diff --git a/arch/powerpc/lib/copyuser_64.S b/arch/powerpc/lib/copyuser_64.S index 25a99108caff4e..9af969d2cc0cb7 100644 --- a/arch/powerpc/lib/copyuser_64.S +++ b/arch/powerpc/lib/copyuser_64.S @@ -562,4 +562,3 @@ exc; std r10,32(3) li r5,4096 b .Ldst_aligned EXPORT_SYMBOL(__copy_tofrom_user) -EXPORT_SYMBOL(__copy_tofrom_user_base) diff --git a/arch/powerpc/lib/copyuser_power7.S b/arch/powerpc/lib/copyuser_power7.S index 17dbcfbae25f0e..8474c682a17849 100644 --- a/arch/powerpc/lib/copyuser_power7.S +++ b/arch/powerpc/lib/copyuser_power7.S @@ -5,9 +5,13 @@ * * Author: Anton Blanchard */ -#include #include +#ifndef SELFTEST_CASE +/* 0 == don't use VMX, 1 == use VMX */ +#define SELFTEST_CASE 0 +#endif + #ifdef __BIG_ENDIAN__ #define LVS(VRT,RA,RB) lvsl VRT,RA,RB #define VPERM(VRT,VRA,VRB,VRC) vperm VRT,VRA,VRB,VRC @@ -43,14 +47,10 @@ ld r15,STK_REG(R15)(r1) ld r14,STK_REG(R14)(r1) .Ldo_err3: - ld r6,STK_REG(R31)(r1) /* original destination pointer */ - ld r5,STK_REG(R29)(r1) /* original number of bytes */ - subf r7,r6,r3 /* #bytes copied */ - subf r3,r7,r5 /* #bytes not copied in r3 */ + bl CFUNC(exit_vmx_usercopy) ld r0,STACKFRAMESIZE+16(r1) mtlr r0 - addi r1,r1,STACKFRAMESIZE - blr + b .Lexit #endif /* CONFIG_ALTIVEC */ .Ldo_err2: @@ -74,6 +74,7 @@ _GLOBAL(__copy_tofrom_user_power7) cmpldi r5,16 + cmpldi cr1,r5,3328 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1) std r4,-STACKFRAMESIZE+STK_REG(R30)(r1) @@ -81,6 +82,12 @@ _GLOBAL(__copy_tofrom_user_power7) blt .Lshort_copy +#ifdef CONFIG_ALTIVEC +test_feature = SELFTEST_CASE +BEGIN_FTR_SECTION + bgt cr1,.Lvmx_copy +END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) +#endif .Lnonvmx_copy: /* Get the source 8B aligned */ @@ -256,14 +263,23 @@ err1; stb r0,0(r3) 15: li r3,0 blr +.Lunwind_stack_nonvmx_copy: + addi r1,r1,STACKFRAMESIZE + b .Lnonvmx_copy + +.Lvmx_copy: #ifdef CONFIG_ALTIVEC -_GLOBAL(__copy_tofrom_user_power7_vmx) mflr r0 std r0,16(r1) stdu r1,-STACKFRAMESIZE(r1) + bl CFUNC(enter_vmx_usercopy) + cmpwi cr1,r3,0 + ld r0,STACKFRAMESIZE+16(r1) + ld r3,STK_REG(R31)(r1) + ld r4,STK_REG(R30)(r1) + ld r5,STK_REG(R29)(r1) + mtlr r0 - std r3,STK_REG(R31)(r1) - std r5,STK_REG(R29)(r1) /* * We prefetch both the source and destination using enhanced touch * instructions. We use a stream ID of 0 for the load side and @@ -284,6 +300,8 @@ _GLOBAL(__copy_tofrom_user_power7_vmx) DCBT_SETUP_STREAMS(r6, r7, r9, r10, r8) + beq cr1,.Lunwind_stack_nonvmx_copy + /* * If source and destination are not relatively aligned we use a * slower permute loop. @@ -460,8 +478,7 @@ err3; lbz r0,0(r4) err3; stb r0,0(r3) 15: addi r1,r1,STACKFRAMESIZE - li r3,0 - blr + b CFUNC(exit_vmx_usercopy) /* tail call optimise */ .Lvmx_unaligned_copy: /* Get the destination 16B aligned */ @@ -664,7 +681,5 @@ err3; lbz r0,0(r4) err3; stb r0,0(r3) 15: addi r1,r1,STACKFRAMESIZE - li r3,0 - blr -EXPORT_SYMBOL(__copy_tofrom_user_power7_vmx) + b CFUNC(exit_vmx_usercopy) /* tail call optimise */ #endif /* CONFIG_ALTIVEC */ diff --git a/arch/powerpc/lib/vmx-helper.c b/arch/powerpc/lib/vmx-helper.c index cc9fb72cb4ebed..7548b4ce53a2a7 100644 --- a/arch/powerpc/lib/vmx-helper.c +++ b/arch/powerpc/lib/vmx-helper.c @@ -27,7 +27,6 @@ int enter_vmx_usercopy(void) return 1; } -EXPORT_SYMBOL(enter_vmx_usercopy); /* * This function must return 0 because we tail call optimise when calling @@ -50,7 +49,6 @@ int exit_vmx_usercopy(void) set_dec(1); return 0; } -EXPORT_SYMBOL(exit_vmx_usercopy); /* * Can be called from kexec copy_page() path with MMU off. The kexec diff --git a/arch/powerpc/platforms/pseries/vio.c b/arch/powerpc/platforms/pseries/vio.c index 572bdf42335ed1..283514800c547c 100644 --- a/arch/powerpc/platforms/pseries/vio.c +++ b/arch/powerpc/platforms/pseries/vio.c @@ -40,7 +40,6 @@ static struct vio_dev vio_bus_device = { /* fake "parent" device */ .name = "vio", .type = "", .dev.init_name = "vio", - .dev.bus = &vio_bus_type, }; #ifdef CONFIG_PPC_SMLPAR diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 6150f3397bff92..b25167e995adbe 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -42,7 +42,7 @@ }; }; cpu1: cpu@1 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; @@ -69,7 +69,7 @@ }; }; cpu2: cpu@2 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; @@ -96,7 +96,7 @@ }; }; cpu3: cpu@3 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; @@ -123,7 +123,7 @@ }; }; cpu4: cpu@4 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts new file mode 100644 index 00000000000000..4d25606f4e0cfb --- /dev/null +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "hifive-unleashed-a00.dts" + +/ { + soc { + pcie: pcie@2030000000 { + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + compatible = "microsemi,ms-pf-axi-pcie-host"; + device_type = "pci"; + bus-range = <0x01 0x7f>; + interrupt-map = <0 0 0 1 &ms_pcie_intc 0 0 0 0 2 &ms_pcie_intc 1 0 0 0 3 &ms_pcie_intc 2 0 0 0 4 &ms_pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&plic0>; + interrupts = <32>; + ranges = <0x3000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; + reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>; + reg-names = "control", "apb"; + ms_pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; +}; diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 01d252c741d272..34c4da293a544f 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -889,6 +889,10 @@ static __init void set_satp_mode(uintptr_t dtb_pa) disable_pgtable_l4(); } + /* UBUNTU: Force disable sv57 and fallback to sv48 */ + if (pgtable_l5_enabled) + disable_pgtable_l5(); + out: memset(early_pg_dir, 0, PAGE_SIZE); memset(early_p4d, 0, PAGE_SIZE); diff --git a/arch/s390/include/asm/ipl.h b/arch/s390/include/asm/ipl.h index b0d00032479d68..afb9544fb0074a 100644 --- a/arch/s390/include/asm/ipl.h +++ b/arch/s390/include/asm/ipl.h @@ -139,6 +139,7 @@ int ipl_report_add_component(struct ipl_report *report, struct kexec_buf *kbuf, unsigned char flags, unsigned short cert); int ipl_report_add_certificate(struct ipl_report *report, void *key, unsigned long addr, unsigned long len); +bool ipl_get_secureboot(void); /* * DIAG 308 support diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c index 3c346b02ceb953..30e16a0d4490c9 100644 --- a/arch/s390/kernel/ipl.c +++ b/arch/s390/kernel/ipl.c @@ -2527,3 +2527,8 @@ int ipl_report_free(struct ipl_report *report) } #endif + +bool ipl_get_secureboot(void) +{ + return !!ipl_secure_flag; +} diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index b60284328fe3de..0e680e83e0056c 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include @@ -917,6 +918,9 @@ void __init setup_arch(char **cmdline_p) log_component_list(); + if (ipl_get_secureboot()) + security_lock_kernel_down("Secure IPL mode", LOCKDOWN_INTEGRITY_MAX); + /* Have one command line that is parsed and saved in /proc/cmdline */ /* boot_command_line has been already set up in early.c */ *cmdline_p = boot_command_line; diff --git a/arch/x86/include/asm/pci-direct.h b/arch/x86/include/asm/pci-direct.h index 94597a3cf3d0f1..ebb3db2eee41b9 100644 --- a/arch/x86/include/asm/pci-direct.h +++ b/arch/x86/include/asm/pci-direct.h @@ -10,9 +10,11 @@ extern u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset); extern u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset); extern u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset); +extern u32 pci_early_find_cap(int bus, int slot, int func, int cap); extern void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, u32 val); extern void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val); extern void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val); +extern unsigned int pci_early_clear_msi; extern int early_pci_allowed(void); #endif /* _ASM_X86_PCI_DIRECT_H */ diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c index 769321185a0815..79a52cd9901bd7 100644 --- a/arch/x86/kernel/aperture_64.c +++ b/arch/x86/kernel/aperture_64.c @@ -136,32 +136,6 @@ static u32 __init allocate_aperture(void) } -/* Find a PCI capability */ -static u32 __init find_cap(int bus, int slot, int func, int cap) -{ - int bytes; - u8 pos; - - if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & - PCI_STATUS_CAP_LIST)) - return 0; - - pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); - for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { - u8 id; - - pos &= ~3; - id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); - if (id == 0xff) - break; - if (id == cap) - return pos; - pos = read_pci_config_byte(bus, slot, func, - pos+PCI_CAP_LIST_NEXT); - } - return 0; -} - /* Read a standard AGPv3 bridge header */ static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order) { @@ -250,8 +224,8 @@ static u32 __init search_agp_bridge(u32 *order, int *valid_agp) case PCI_CLASS_BRIDGE_HOST: case PCI_CLASS_BRIDGE_OTHER: /* needed? */ /* AGP bridge? */ - cap = find_cap(bus, slot, func, - PCI_CAP_ID_AGP); + cap = pci_early_find_cap(bus, slot, + func, PCI_CAP_ID_AGP); if (!cap) break; *valid_agp = 1; diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index abb3984336ebf2..1ba19b7be538f2 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -202,6 +202,7 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) static void early_init_intel(struct cpuinfo_x86 *c) { u64 misc_enable; + bool allow_fast_string = true; if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) c->microcode = intel_get_microcode_revision(); @@ -301,6 +302,19 @@ static void early_init_intel(struct cpuinfo_x86 *c) */ if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) { rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable); + + if (allow_fast_string && + !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { + misc_enable |= MSR_IA32_MISC_ENABLE_FAST_STRING; + wrmsrl_safe(MSR_IA32_MISC_ENABLE, misc_enable); + + /* Re-read to make sure it stuck. */ + rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); + + if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) + printk_once(KERN_INFO FW_WARN "IA32_MISC_ENABLE.FAST_STRING_ENABLE was not set\n"); + } + if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) { /* X86_FEATURE_ERMS is set based on CPUID */ set_cpu_cap(c, X86_FEATURE_REP_GOOD); diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 6b6f32f40cbeb4..257c853995e905 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -29,6 +29,37 @@ #include #include +static void __init early_pci_clear_msi(int bus, int slot, int func) +{ + int pos; + u16 ctrl; + + if (likely(!pci_early_clear_msi)) + return; + + pr_info_once("Clearing MSI/MSI-X enable bits early in boot (quirk)\n"); + + pos = pci_early_find_cap(bus, slot, func, PCI_CAP_ID_MSI); + if (pos) { + ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSI_FLAGS); + ctrl &= ~PCI_MSI_FLAGS_ENABLE; + write_pci_config_16(bus, slot, func, pos + PCI_MSI_FLAGS, ctrl); + + /* Read again to flush previous write */ + ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSI_FLAGS); + } + + pos = pci_early_find_cap(bus, slot, func, PCI_CAP_ID_MSIX); + if (pos) { + ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSIX_FLAGS); + ctrl &= ~PCI_MSIX_FLAGS_ENABLE; + write_pci_config_16(bus, slot, func, pos + PCI_MSIX_FLAGS, ctrl); + + /* Read again to flush previous write */ + ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSIX_FLAGS); + } +} + static void __init fix_hypertransport_config(int num, int slot, int func) { u32 htcfg; @@ -727,6 +758,7 @@ static struct chipset early_qrk[] __initdata = { PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, { PCI_VENDOR_ID_BROADCOM, 0x4331, PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset}, + { PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, early_pci_clear_msi}, {} }; @@ -779,6 +811,10 @@ static int __init check_dev_quirk(int num, int slot, int func) PCI_HEADER_TYPE); if ((type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { + /* pci_early_clear_msi scans the buses differently. */ + if (pci_early_clear_msi) + return -1; + sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS); if (sec > num) early_pci_scan_bus(sec); @@ -805,8 +841,13 @@ static void __init early_pci_scan_bus(int bus) void __init early_quirks(void) { + int bus; + if (!early_pci_allowed()) return; early_pci_scan_bus(0); + /* pci_early_clear_msi scans more buses. */ + for (bus = 1; pci_early_clear_msi && bus < 256; bus++) + early_pci_scan_bus(bus); } diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 0fed6d0d7e322c..ed427d8bd8f186 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -490,7 +490,46 @@ static const struct dmi_system_id reboot_dmi_table[] __initconst = { DMI_MATCH(DMI_PRODUCT_NAME, "VGN-Z540N"), }, }, - + { /* Handle problems with rebooting on the Latitude E6520. */ + .callback = set_pci_reboot, + .ident = "Dell Latitude E6520", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Latitude E6520"), + }, + }, + { /* Handle problems with rebooting on the OptiPlex 790. */ + .callback = set_pci_reboot, + .ident = "Dell OptiPlex 790", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 790"), + }, + }, + { /* Handle problems with rebooting on the OptiPlex 990. */ + .callback = set_pci_reboot, + .ident = "Dell OptiPlex 990", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 990"), + }, + }, + { /* Handle problems with rebooting on the Latitude E6220. */ + .callback = set_pci_reboot, + .ident = "Dell Latitude E6220", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Latitude E6220"), + }, + }, + { /* Handle problems with rebooting on the OptiPlex 390. */ + .callback = set_pci_reboot, + .ident = "Dell OptiPlex 390", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 390"), + }, + }, { } }; diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 46882ce79c3a4d..0407996b0371ee 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -998,6 +999,13 @@ void __init setup_arch(char **cmdline_p) reserve_ibft_region(); x86_init.resources.dmi_setup(); + efi_set_secure_boot(boot_params.secure_boot); + +#ifdef CONFIG_LOCK_DOWN_IN_SECURE_BOOT + if (efi_enabled(EFI_SECURE_BOOT)) + security_lock_kernel_down("EFI Secure Boot mode", LOCKDOWN_INTEGRITY_MAX); +#endif + /* * VMware detection requires dmi to be available, so this * needs to be done after dmi_setup(), for the boot CPU. @@ -1156,19 +1164,7 @@ void __init setup_arch(char **cmdline_p) /* Allocate bigger log buffer */ setup_log_buf(1); - if (efi_enabled(EFI_BOOT)) { - switch (boot_params.secure_boot) { - case efi_secureboot_mode_disabled: - pr_info("Secure boot disabled\n"); - break; - case efi_secureboot_mode_enabled: - pr_info("Secure boot enabled\n"); - break; - default: - pr_info("Secure boot could not be determined\n"); - break; - } - } + efi_set_secure_boot(boot_params.secure_boot); reserve_initrd(); diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 63105b29fbf540..45ab8c7a02ad6f 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -34,6 +34,7 @@ int noioapicreroute = 1; #endif int pcibios_last_bus = -1; unsigned long pirq_table_addr; +unsigned int pci_early_clear_msi; const struct pci_raw_ops *__read_mostly raw_pci_ops; const struct pci_raw_ops *__read_mostly raw_pci_ext_ops; @@ -614,6 +615,9 @@ char *__init pcibios_setup(char *str) } else if (!strcmp(str, "skip_isa_align")) { pci_probe |= PCI_CAN_SKIP_ISA_ALIGN; return NULL; + } else if (!strcmp(str, "clearmsi")) { + pci_early_clear_msi = 1; + return NULL; } else if (!strcmp(str, "noioapicquirk")) { noioapicquirk = 1; return NULL; diff --git a/arch/x86/pci/early.c b/arch/x86/pci/early.c index f5fc953e584832..f1ba9d781b5249 100644 --- a/arch/x86/pci/early.c +++ b/arch/x86/pci/early.c @@ -51,6 +51,31 @@ void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val) outw(val, 0xcfc + (offset&2)); } +u32 pci_early_find_cap(int bus, int slot, int func, int cap) +{ + int bytes; + u8 pos; + + if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & + PCI_STATUS_CAP_LIST)) + return 0; + + pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); + for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { + u8 id; + + pos &= ~3; + id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); + if (id == 0xff) + break; + if (id == cap) + return pos; + pos = read_pci_config_byte(bus, slot, func, + pos+PCI_CAP_LIST_NEXT); + } + return 0; +} + int early_pci_allowed(void) { return (pci_probe & (PCI_PROBE_CONF1|PCI_PROBE_NOEARLY)) == diff --git a/certs/blacklist.c b/certs/blacklist.c index fa561c12eabfe9..b70c3fbe125e15 100644 --- a/certs/blacklist.c +++ b/certs/blacklist.c @@ -277,6 +277,9 @@ int add_key_to_revocation_list(const char *data, size_t size) if (IS_ERR(key)) { pr_err("Problem with revocation key (%ld)\n", PTR_ERR(key)); return PTR_ERR(key); + } else { + pr_notice("Revoked X.509 cert '%s'\n", + key_ref_to_ptr(key)->description); } return 0; diff --git a/crypto/aegis128-neon-inner.c b/crypto/aegis128-neon-inner.c index 56b534eeb68071..64ffda05e9b004 100644 --- a/crypto/aegis128-neon-inner.c +++ b/crypto/aegis128-neon-inner.c @@ -146,8 +146,8 @@ void crypto_aegis128_init_neon(void *state, const void *key, const void *iv) kiv, vld1q_u8(const1), vld1q_u8(const0), - k ^ vld1q_u8(const0), - k ^ vld1q_u8(const1), + (uint8x16_t) (k ^ vld1q_u8(const0)), + (uint8x16_t) (k ^ vld1q_u8(const1)), }}; int i; diff --git a/crypto/asymmetric_keys/x509_loader.c b/crypto/asymmetric_keys/x509_loader.c index 0d516c77cc26ac..619186a1bb223b 100644 --- a/crypto/asymmetric_keys/x509_loader.c +++ b/crypto/asymmetric_keys/x509_loader.c @@ -41,6 +41,7 @@ int x509_load_certificate_list(const u8 cert_list[], if (IS_ERR(key)) { pr_err("Problem loading in-kernel X.509 certificate (%ld)\n", PTR_ERR(key)); + WARN_ON_ONCE(1); } else { pr_notice("Loaded X.509 cert '%s'\n", key_ref_to_ptr(key)->description); diff --git a/crypto/fips.c b/crypto/fips.c index c59711248d9569..15678b01eb4e6c 100644 --- a/crypto/fips.c +++ b/crypto/fips.c @@ -15,7 +15,8 @@ #include #include -int fips_enabled; +/* LP: #2049082 UBUNTU: SAUCE: FIPS kernels default to FIPS mode */ +int fips_enabled = 1; EXPORT_SYMBOL_GPL(fips_enabled); ATOMIC_NOTIFIER_HEAD(fips_fail_notif_chain); diff --git a/debian.master/changelog b/debian.master/changelog new file mode 100644 index 00000000000000..8fa8c14b987398 --- /dev/null +++ b/debian.master/changelog @@ -0,0 +1,6 @@ +linux (7.1.1-070101.202606191302) resolute; urgency=low + + Mainline build at commit: v7.1.1 + + -- Mainline Build Fri, 19 Jun 2026 13:02:42 +0000 + diff --git a/debian.master/config/README.rst b/debian.master/config/README.rst new file mode 100644 index 00000000000000..751ce7f3b284d4 --- /dev/null +++ b/debian.master/config/README.rst @@ -0,0 +1,185 @@ +================== +Config Annotations +================== + +:Author: Andrea Righi + +Overview +======== + +Each Ubuntu kernel needs to maintain its own .config for each supported +architecture and each flavour. + +Every time a new patch is applied or a kernel is rebased on top of a new +one, we need to update the .config's accordingly (config options can be +added, removed and also renamed). + +So, we need to make sure that some critical config options are always +matching the desired value in order to have a functional kernel. + +State of the art +================ + +At the moment configs are maintained as a set of Kconfig chunks (inside +`debian./config/`): a global one, plus per-arch / per-flavour +chunks. + +In addition to that, we need to maintain also a file called +'annotations'; the purpose of this file is to make sure that some +critical config options are not silently removed or changed when the +real .config is re-generated (for example after a rebase or after +applying a new set of patches). + +The main problem with this approach is that, often, we have duplicate +information that is stored both in the Kconfig chunks *and* in the +annotations files and, at the same time, the whole .config's information +is distributed between Kconfig chunks and annotations, making it hard to +maintain, review and manage in general. + +Proposed solution +================= + +The proposed solution is to store all the config information into the +"annotations" format and get rid of the config chunks (basically the +real .config's can be produced "compiling" annotations). + +Implementation +============== + +To help the management of the annotations an helper script is provided +(`debian/scripts/misc/annotations`): + +``` +usage: annotations [-h] [--version] [--file FILE] [--arch ARCH] [--flavour FLAVOUR] [--config CONFIG] + (--query | --export | --import FILE | --update FILE | --check FILE) + +Manage Ubuntu kernel .config and annotations + +options: + -h, --help show this help message and exit + --version, -v show program's version number and exit + --file FILE, -f FILE Pass annotations or .config file to be parsed + --arch ARCH, -a ARCH Select architecture + --flavour FLAVOUR, -l FLAVOUR + Select flavour (default is "generic") + --config CONFIG, -c CONFIG + Select a specific config option + +Action: + --query, -q Query annotations + --export, -e Convert annotations to .config format + --import FILE, -i FILE + Import a full .config for a specific arch and flavour into annotations + --update FILE, -u FILE + Import a partial .config into annotations (only resync configs specified in FILE) + --check FILE, -k FILE + Validate kernel .config with annotations +``` + +This script allows to query config settings (per arch/flavour/config), +export them into the Kconfig format (generating the real .config files) +and check if the final .config matches the rules defined in the +annotations. + +Examples (annotations is defined as an alias to `debian/scripts/annotations`): + + - Show settings for `CONFIG_DEBUG_INFO_BTF` for master kernel across all the + supported architectures and flavours: + +``` +$ annotations --query --config CONFIG_DEBUG_INFO_BTF +{ + "policy": { + "amd64": "y", + "arm64": "y", + "armhf": "n", + "ppc64el": "y", + "riscv64": "y", + "s390x": "y" + }, + "note": "'Needs newer pahole for armhf'" +} +``` + + - Dump kernel .config for arm64 and flavour generic-64k: + +``` +$ annotations --arch arm64 --flavour generic-64k --export +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_COMPAT=y +... +``` + + - Update annotations file with a new kernel .config for amd64 flavour + generic: + +``` +$ annotations --arch amd64 --flavour generic --import build/.config +``` + +Moreover, an additional kernelconfig commands are provided +(via debian/rules targets): + - `migrateconfigs`: automatically merge all the previous configs into + annotations (local changes still need to be committed) + +Annotations headers +=================== + +The main annotations file should contain a header to define the architectures +and flavours that are supported. + +Here is the format of the header for the generic kernel: +``` +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 armhf ppc64el riscv64 s390x +# FLAVOUR: amd64-generic arm64-generic arm64-generic-64k armhf-generic armhf-generic-lpae ppc64el-generic riscv64-generic s390x-generic + +``` + +Example header of a derivative (linux-aws): +``` +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 +# FLAVOUR: amd64-aws arm64-aws +# FLAVOUR_DEP: {'amd64-aws': 'amd64-generic', 'arm64-aws': 'arm64-generic'} + +include "../../debian.master/config/annotations" + +# Below you can define only the specific linux-aws configs that differ from linux generic + +``` + +Pros and Cons +============= + + Pros: + - avoid duplicate information in .config's and annotations + - allow to easily define groups of config settings (for a specific + environment or feature, such as annotations.clouds, annotations.ubuntu, + annotations.snapd, etc.) + - config options are more accessible, easy to change and review + - we can easily document how config options are managed (and external + contributors won't be discouraged anymore when they need to to change a + config option) + + Cons: + - potential regressions: the new tool/scripts can have potential bugs, + so we could experience regressions due to some missed config changes + - kernel team need to understand the new process (even if everything + is transparent, kernel cranking process is the same, there might be + corner cases that need to be addressed and resolved manually) + +TODO +==== + + - Migrate all flavour and arch definitions into annotations (rather + than having this information defined in multiple places inside + debian/scripts); right now this information is "partially" migrated, + meaning that we need to define arches and flavours in the headers + section of annotations (so that the annotations tool can figure out + the list of supported arches and flavours), but arches and flavours + are still defined elsewhere, ideally we would like to have arches and + flavours defined only in one place: annotations. diff --git a/debian.master/config/annotations b/debian.master/config/annotations new file mode 100644 index 00000000000000..70958c9d76f5d2 --- /dev/null +++ b/debian.master/config/annotations @@ -0,0 +1,16843 @@ +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 armhf ppc64el riscv64 s390x +# FLAVOUR: amd64-generic arm64-generic arm64-generic-64k armhf-generic ppc64el-generic riscv64-generic s390x-generic + +CONFIG_ACCESSIBILITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_ACCESSIBILITY note<'LP: #1967702'> + +CONFIG_AGP policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_AGP note<'not autoloadable'> + +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE note<'LP: #2051835'> + +CONFIG_ARCH_MMAP_RND_BITS policy<{'amd64': '32', 'arm64': '33', 'arm64-generic-64k': '29', 'armhf': '16', 'ppc64el': '29', 'riscv64': '24'}> +CONFIG_ARCH_MMAP_RND_BITS note<'LP: #1983357'> + +CONFIG_ARCH_MMAP_RND_COMPAT_BITS policy<{'amd64': '16', 'arm64': '16', 'arm64-generic-64k': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS note<'LP: #1983357'> + +CONFIG_ARCH_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_ROCKCHIP note<'LP: #1825222'> + +CONFIG_ARM64_ERRATUM_843419 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_843419 note<'LP: #1647793'> + +CONFIG_ARM64_ERRATUM_858921 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_858921 note<'LP: #1675509'> + +CONFIG_ARM64_VA_BITS_48 policy<{'arm64': 'y'}> +CONFIG_ARM64_VA_BITS_48 note<'Cavium ThunderX 2-socket needs a minimum of 41 bits of VA'> + +CONFIG_ARMV8_DEPRECATED policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_ARMV8_DEPRECATED note<'LP: #1545542'> + +CONFIG_ARM_HIGHBANK_CPUIDLE policy<{'armhf': 'y'}> +CONFIG_ARM_HIGHBANK_CPUIDLE note<'broken on ecx-1000'> + +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT policy<{'arm64': 'n', 'armhf': '-'}> +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT note<'LP: #1845820'> + +CONFIG_ASYMMETRIC_KEY_TYPE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ASYMMETRIC_KEY_TYPE note<'module signing'> + +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE note<'module signing'> + +CONFIG_ATA_PIIX policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATA_PIIX note<'LP: #1627324'> + +CONFIG_BINFMT_SCRIPT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BINFMT_SCRIPT note<'required if init is a shell script such as in initramfs-tools'> + +CONFIG_BLK_DEV_DM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_DM note<'LP: #560717'> + +CONFIG_BLK_DEV_NVME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_NVME note<'LP: #1759893'> + +CONFIG_BLK_DEV_RAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_RAM note<'LP: #1593293'> + +CONFIG_BLK_DEV_RAM_SIZE policy<{'amd64': '65536', 'arm64': '65536', 'armhf': '65536', 'ppc64el': '65536', 'riscv64': '65536', 's390x': '65536'}> +CONFIG_BLK_DEV_RAM_SIZE note<'Ramdisk size should be a minimum of 64M'> + +CONFIG_BLK_DEV_SD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_SD note<'LP: #1627330'> + +CONFIG_BLK_DEV_SR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_SR note<'LP: #1627330'> + +CONFIG_BLK_DEV_THROTTLING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_THROTTLING note<'CGROUP disk consumption control'> + +CONFIG_BPF_UNPRIV_DEFAULT_OFF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_UNPRIV_DEFAULT_OFF note<'security reason'> + +CONFIG_CHR_DEV_SG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CHR_DEV_SG note<'not autoloadable'> + +CONFIG_CMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CMA note<'LP: #1803206'> + +CONFIG_CMA_SIZE_MBYTES policy<{'amd64': '0', 'arm64': '32', 'armhf': '32', 'riscv64': '32'}> +CONFIG_CMA_SIZE_MBYTES note<'LP: #1823753'> + +CONFIG_COMPAT_BRK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_COMPAT_BRK note<'disables brk ASLR'> + +CONFIG_CONSOLE_LOGLEVEL_QUIET policy<{'amd64': '3', 'arm64': '3', 'armhf': '3', 'ppc64el': '3', 'riscv64': '3', 's390x': '3'}> +CONFIG_CONSOLE_LOGLEVEL_QUIET note<'LP: #2049390'> + +CONFIG_CP15_BARRIER_EMULATION policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_CP15_BARRIER_EMULATION note<'LP: #1545542'> + +CONFIG_CPUFREQ_DT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPUFREQ_DT note<'not autoloadable'> + +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE note<'for bootspeed'> + +CONFIG_CPU_FREQ_GOV_CONSERVATIVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_CONSERVATIVE note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_ONDEMAND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_ONDEMAND note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_PERFORMANCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_PERFORMANCE note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_POWERSAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_POWERSAVE note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_USERSPACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_USERSPACE note<'not autoloadable'> + +CONFIG_CPU_FREQ_STAT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_STAT note<'dependancy of boot essential'> + +CONFIG_CRASH_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRASH_DUMP note<'LP: #1363180'> + +CONFIG_CRYPTO_HMAC_S390 policy<{'s390x': 'm'}> +CONFIG_CRYPTO_HMAC_S390 note<'LP: #2096812'> + +CONFIG_CRYPTO_LIB_SHA512_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA512_ARCH note<'LP: #2034061'> + +CONFIG_CRYPTO_SHA512 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SHA512 note<'module signing'> + +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE note<'Obsolete w/ no known userspace dependencies'> + +CONFIG_DEBUG_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_FS note<'required debug option'> + +CONFIG_DEBUG_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_INFO note<'required for debug packages'> + +CONFIG_DEBUG_INFO_BTF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_INFO_BTF note<'Needs newer pahole for armhf'> + +CONFIG_DEBUG_INFO_SPLIT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_SPLIT note<'LP: #1413664'> + +CONFIG_DEBUG_KERNEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_KERNEL note<'required debug option'> + +CONFIG_DEFAULT_MMAP_MIN_ADDR policy<{'amd64': '65536', 'arm64': '32768', 'armhf': '32768', 'ppc64el': '65536', 'riscv64': '65536', 's390x': '65536'}> +CONFIG_DEFAULT_MMAP_MIN_ADDR note<'LP: #1531327'> + +CONFIG_DEVTMPFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVTMPFS note<'upstart requirement'> + +CONFIG_DEVTMPFS_MOUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVTMPFS_MOUNT note<'upstart requirement'> + +CONFIG_DMA_CMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DMA_CMA note<'LP: #1803206'> + +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING note<'LP: #2019040'> + +CONFIG_DRM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM note<'LP: #1965303'> + +CONFIG_DRM_AMDGPU_CIK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMDGPU_CIK note<'for zesty'> + +CONFIG_DRM_I915_REPLAY_GPU_HANGS_API policy<{'amd64': 'n'}> +CONFIG_DRM_I915_REPLAY_GPU_HANGS_API note<'Only useful for upstream developers'> + +CONFIG_DRM_I915_REPLAY_GPU_HANGS_API policy<{'amd64': 'n'}> +CONFIG_DRM_I915_REPLAY_GPU_HANGS_API note<'Only useful for upstream developers'> + +CONFIG_DRM_MGAG200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_MGAG200 note<'LP: #1693337'> + +CONFIG_DRM_SIMPLEDRM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DRM_SIMPLEDRM note<'LP: #1965303'> + +CONFIG_DRM_VBOXVIDEO policy<{'amd64': 'm'}> +CONFIG_DRM_VBOXVIDEO note<'LP: #1718679'> + +CONFIG_DVB_DUMMY_FE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DUMMY_FE note<'expert use only'> + +CONFIG_ECRYPT_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ECRYPT_FS note<'not autoloadable'> + +CONFIG_EFIVAR_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFIVAR_FS note<'needed for variable EFI update'> + +CONFIG_EFI_HANDOVER_PROTOCOL policy<{'amd64': 'y'}> +CONFIG_EFI_HANDOVER_PROTOCOL note<'{GRUB may include some downstream patches that may rely on the handover protocol, so make sure this is enabled}'> + +CONFIG_EFI_ZBOOT policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_EFI_ZBOOT note<'LP: #2002226'> + +CONFIG_EVM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EVM note<'LP: #1643652'> + +CONFIG_EVM_ATTR_FSUUID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EVM_ATTR_FSUUID note<'LP: #1643652'> + +CONFIG_EVM_LOAD_X509 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EVM_LOAD_X509 note<'LP: #1643652'> + +CONFIG_EVM_X509_PATH policy<{'ppc64el': '"/etc/keys/x509_evm.der"'}> +CONFIG_EVM_X509_PATH note<'LP: #1643652'> + +CONFIG_EXT2_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EXT2_FS note<'ext4 handling via EXT4_USE_FOR_EXT23'> + +CONFIG_FA_DUMP policy<{'ppc64el': 'y'}> +CONFIG_FA_DUMP note<'LP: #1415562'> + +CONFIG_FB_EFI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_FB_EFI note<'LP: #1965303'> + +CONFIG_FB_VESA policy<{'amd64': 'n'}> +CONFIG_FB_VESA note<'LP: #1965303'> + +CONFIG_FHANDLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FHANDLE note<'LP: #1412543'> + +CONFIG_FUSE_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUSE_FS note<'not autoloadable'> + +CONFIG_FW_LOADER_USER_HELPER_FALLBACK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FW_LOADER_USER_HELPER_FALLBACK note<'LP: #1398458'> + +CONFIG_GPIO_CDEV_V1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIO_CDEV_V1 note<'LP: #1953613'> + +CONFIG_GPIO_EM policy<{'armhf': 'n'}> +CONFIG_GPIO_EM note<'h/w not encounted'> + +CONFIG_GPIO_TWL4030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_TWL4030 note<'LP: #921934'> + +CONFIG_HIBERNATION policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'y'}> +CONFIG_HIBERNATION note<'LP: #1867753'> + +CONFIG_HIPERDISPATCH_ON policy<{'s390x': 'y'}> +CONFIG_HIPERDISPATCH_ON note<'LP: #2072760'> + +CONFIG_HOTPLUG_PCI_PCIE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HOTPLUG_PCI_PCIE note<'LP: #1374440'> + +CONFIG_HOTPLUG_PCI_SHPC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HOTPLUG_PCI_SHPC note<'LP: #1374440'> + +CONFIG_HSA_AMD_P2P policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HSA_AMD_P2P note<'LP: #1987394'> + +CONFIG_HSU_DMA policy<{'amd64': 'y'}> +CONFIG_HSU_DMA note<'required by CONFIG_SERIAL_8250_MID (LP: #2009283)'> + +CONFIG_HVC_UDBG policy<{'ppc64el': 'n'}> +CONFIG_HVC_UDBG note<'LP: #1680888'> + +CONFIG_HZ_100 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_HZ_100 note<'LP: #2051342'> + +CONFIG_HZ_1000 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_HZ_1000 note<'LP: #2051342'> + +CONFIG_HZ_250 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HZ_250 note<'LP: #2051342'> + +CONFIG_I2C_CHARDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_I2C_CHARDEV note<'LP: #1417032'> + +CONFIG_IBMVNIC policy<{'ppc64el': 'm'}> +CONFIG_IBMVNIC note<'LP: #1628187'> + +CONFIG_IDLE_PAGE_TRACKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IDLE_PAGE_TRACKING note<'is there a cost associated with this?'> + +CONFIG_IGH_ECAT policy<{'amd64': 'm', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IGH_ECAT note<'{LP: #2138621}'> + +CONFIG_IIO_SIMPLE_DUMMY_BUFFER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_IIO_SIMPLE_DUMMY_BUFFER note<'dummy driver'> + +CONFIG_IIO_SIMPLE_DUMMY_EVENTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_IIO_SIMPLE_DUMMY_EVENTS note<'dummy driver'> + +CONFIG_IMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA note<'LP: #1643652'> + +CONFIG_IMA_APPRAISE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_APPRAISE note<'LP: #1643652'> + +CONFIG_IMA_ARCH_POLICY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_ARCH_POLICY note<'LP: #1866909'> + +CONFIG_IMA_DEFAULT_HASH_SHA256 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_DEFAULT_HASH_SHA256 note<'LP: #2041735'> + +CONFIG_IMA_KEXEC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IMA_KEXEC note<'LP: #1643652'> + +CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY note<'LP: #1667490'> + +CONFIG_IMA_READ_POLICY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_READ_POLICY note<'LP: #1866909'> + +CONFIG_IMA_SIG_TEMPLATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_SIG_TEMPLATE note<'LP: #1643652'> + +CONFIG_IMA_WRITE_POLICY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_WRITE_POLICY note<'LP: #1667490'> + +CONFIG_INPUT_UINPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_INPUT_UINPUT note<'LP: #584812'> + +CONFIG_INTEGRITY_PLATFORM_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEGRITY_PLATFORM_KEYRING note<'Required for lockdown'> + +CONFIG_INTEL_ATOMISP policy<{'amd64': 'n'}> +CONFIG_INTEL_ATOMISP note<'LP: #2017444'> + +CONFIG_INTEL_ATOMISP2_PM policy<{'amd64': 'm'}> +CONFIG_INTEL_ATOMISP2_PM note<'LP: #2017444'> + +CONFIG_INTEL_IOMMU_DEFAULT_ON policy<{'amd64': 'y'}> +CONFIG_INTEL_IOMMU_DEFAULT_ON note<'LP: #1951440'> + +CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON policy<{'amd64': 'y'}> +CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON note<'LP: #1951440'> + +CONFIG_IOMMU_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IOMMU_DEBUGFS note<'LP: #1861057'> + +CONFIG_IOMMU_DEFAULT_DMA_LAZY policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_IOMMU_DEFAULT_DMA_LAZY note<'LP: #2071471'> + +CONFIG_IOMMU_DEFAULT_DMA_STRICT policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_IOMMU_DEFAULT_DMA_STRICT note<'LP: #2071471'> + +CONFIG_IPMMU_VMSA policy<{'arm64': 'n', 'armhf': 'n', 'riscv64': '-'}> +CONFIG_IPMMU_VMSA note<'LP: #1718734'> + +CONFIG_IPV6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6 note<'if this is a module we get a module load for every ipv6 packet'> + +CONFIG_IP_PNP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IP_PNP note<'LP: #1259861'> + +CONFIG_KERNEL_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KERNEL_ZSTD note<'LP: #193172'> + +CONFIG_KEXEC_BZIMAGE_VERIFY_SIG policy<{'amd64': 'y'}> +CONFIG_KEXEC_BZIMAGE_VERIFY_SIG note<'Q: check this is in sync with the kexec/kdump userspace'> + +CONFIG_KFENCE_STATIC_KEYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KFENCE_STATIC_KEYS note<'LP: #1948038'> + +CONFIG_KGDB_SERIAL_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KGDB_SERIAL_CONSOLE note<'early debugging support'> + +CONFIG_KVM policy<{'amd64': 'm', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'y'}> +CONFIG_KVM note<'LP: #1532886'> + +CONFIG_LATENCYTOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LATENCYTOP note<'LP: #2051342'> + +CONFIG_LEGACY_TIOCSTI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LEGACY_TIOCSTI note<'LP:#2046192'> + +CONFIG_LOAD_PPC_KEYS policy<{'ppc64el': 'y'}> +CONFIG_LOAD_PPC_KEYS note<'LP: #1866909'> + +CONFIG_LOCALVERSION_AUTO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOCALVERSION_AUTO note<'triggers packaging failures'> + +CONFIG_LRU_GEN policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LRU_GEN note<'{Enable multi-gen LRU by default - LP: #2023629}'> + +CONFIG_LRU_GEN_ENABLED policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LRU_GEN_ENABLED note<'{Enable multi-gen LRU by default - LP: #2023629}'> + +CONFIG_MFD_SM501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SM501 note<'boot essential on OMAP4'> + +CONFIG_MFD_TPS65217 policy<{'arm64': 'm', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_MFD_TPS65217 note<'boot essential on AM335x'> + +CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE note<'LP: #1848492'> + +CONFIG_MHP_MEMMAP_ON_MEMORY policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MHP_MEMMAP_ON_MEMORY note<'LP: #2051835'> + +CONFIG_MMC_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_BLOCK note<'boot essential on armhf/arm64'> + +CONFIG_MMC_OMAP_HS policy<{'armhf': 'y'}> +CONFIG_MMC_OMAP_HS note<'boot essential on arm'> + +CONFIG_MMC_SDHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_SDHCI note<'installation essential on omap/highbank'> + +CONFIG_MMC_SDHCI_PLTFM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_PLTFM note<'boot essential on highbank'> + +CONFIG_MODIFY_LDT_SYSCALL policy<{'amd64': 'y'}> +CONFIG_MODIFY_LDT_SYSCALL note<'Q: check this with security'> + +CONFIG_MODULE_COMPRESS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_COMPRESS_ZSTD note<'LP: #2028568'> + +CONFIG_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODVERSIONS note<'required as we have a livepatch/drivers modules signing key'> + +CONFIG_MTD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MTD note<'boot essential on arm'> + +CONFIG_MTD_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MTD_BLOCK note<'boot essential on arm'> + +CONFIG_MTD_DOCG3 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_DOCG3 note<'LP: #1792205'> + +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE note<'can be enabled at runtime'> + +CONFIG_MTD_OF_PARTS policy<{'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_OF_PARTS note<'boot essential on arm'> + +CONFIG_MTD_ONENAND_VERIFY_WRITE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_ONENAND_VERIFY_WRITE note<'writes here are not checked in full without'> + +CONFIG_MTD_RAW_NAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MTD_RAW_NAND note<'boot essential on arm'> + +CONFIG_NETWORK_PHY_TIMESTAMPING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETWORK_PHY_TIMESTAMPING note<'LP: #1785816'> + +CONFIG_NET_9P policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_9P note<'LP: #1557994'> + +CONFIG_NET_DROP_MONITOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_DROP_MONITOR note<'LP: #1660634'> + +CONFIG_NET_SWITCHDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SWITCHDEV note<'updated to y for s390x starting with focal'> + +CONFIG_NET_VENDOR_EMULEX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_EMULEX note<'LP: #1543165'> + +CONFIG_NLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NLS note<'dependancy of boot essential'> + +CONFIG_NOP_USB_XCEIV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NOP_USB_XCEIV note<'boot essential on omap/highbank'> + +CONFIG_NO_HZ_FULL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_NO_HZ_FULL note<'LP: #2051342'> + +CONFIG_NO_HZ_IDLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NO_HZ_IDLE note<'LP: #2051342'> + +CONFIG_NR_CPUS policy<{'amd64': '8192', 'arm64': '512', 'armhf': '4', 'ppc64el': '2048', 'riscv64': '512', 's390x': '512'}> +CONFIG_NR_CPUS note<'LP: #2042897 (arm64), LP: #1864198 (s390x)'> + +CONFIG_NUMA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NUMA note<'LP: #1557690'> + +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED note<'LP: #1557690'> + +CONFIG_NUMA_EMU policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_NUMA_EMU note<'LP: #1864198'> + +CONFIG_NVMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NVMEM note<'LP: #1543165'> + +CONFIG_NVRAM policy<{'amd64': 'm', 'ppc64el': 'y'}> +CONFIG_NVRAM note<'LP: #1837726'> + +CONFIG_N_GSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_N_GSM note<'LP: #1404670'> + +CONFIG_OSNOISE_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OSNOISE_TRACER note<'This enables the osnoise tracer for the kernel. LP: #2018591'> + +CONFIG_PAGE_POISONING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_POISONING note<'LP: #1783651'> + +CONFIG_PANIC_ON_OOPS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PANIC_ON_OOPS note<'keep working if at all possible'> + +CONFIG_PATA_HPT3X3_DMA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PATA_HPT3X3_DMA note<'DMA mode is documented problematic'> + +CONFIG_PCIEASPM_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIEASPM_DEFAULT note<'LP: #1398544'> + +CONFIG_PCIEPORTBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIEPORTBUS note<'LP: #1665404'> + +CONFIG_PCI_DYNAMIC_OF_NODES policy<{'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PCI_DYNAMIC_OF_NODES note<'LP: #2074376, ok for arm64 as MISC_RP1 needs it'> + +CONFIG_PCI_MESON policy<{'amd64': 'n', 'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCI_MESON note<'LP: #2007745'> + +CONFIG_PCI_NR_FUNCTIONS policy<{'s390x': '512'}> +CONFIG_PCI_NR_FUNCTIONS note<'LP: #1866056'> + +CONFIG_PINCTRL_CHERRYVIEW policy<{'amd64': 'y'}> +CONFIG_PINCTRL_CHERRYVIEW note<'LP: #1630238'> + +CONFIG_PM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM note<'LP: #1867753'> + +CONFIG_PPC_MEM_KEYS policy<{'ppc64el': 'n'}> +CONFIG_PPC_MEM_KEYS note<'LP: #1776967'> + +CONFIG_PPC_SECURE_BOOT policy<{'ppc64el': 'y'}> +CONFIG_PPC_SECURE_BOOT note<'LP: #1855668'> + +CONFIG_PPC_SECVAR_SYSFS policy<{'ppc64el': 'y'}> +CONFIG_PPC_SECVAR_SYSFS note<'LP: #1866909'> + +CONFIG_PREEMPT_DYNAMIC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PREEMPT_DYNAMIC note<'LP: #2051342'> + +CONFIG_PSI_DEFAULT_DISABLED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_PSI_DEFAULT_DISABLED note<'LP: #1876044'> + +CONFIG_QCOM_QDF2400_ERRATUM_0065 policy<{'arm64': 'y'}> +CONFIG_QCOM_QDF2400_ERRATUM_0065 note<'LP: #1672486'> + +CONFIG_QETH_OSX policy<{'s390x': 'n'}> +CONFIG_QETH_OSX note<'LP: #1959890'> + +CONFIG_RCU_LAZY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_RCU_LAZY note<'LP: #2051342'> + +CONFIG_RCU_LAZY_DEFAULT_OFF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_RCU_LAZY_DEFAULT_OFF note<'LP: #2051342'> + +CONFIG_RCU_NOCB_CPU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_RCU_NOCB_CPU note<'LP: #2051342'> + +CONFIG_RCU_NOCB_CPU_DEFAULT_ALL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_RCU_NOCB_CPU_DEFAULT_ALL note<'LP: #2051342'> + +CONFIG_REGULATOR_TPS65217 policy<{'arm64': 'm', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS65217 note<'boot essential on AM335x'> + +CONFIG_REGULATOR_TWL4030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TWL4030 note<'boot requisite for omap4'> + +CONFIG_RTC_DRV_CMOS policy<{'amd64': 'y', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_RTC_DRV_CMOS note<'boot essential on i386/amd64'> + +CONFIG_RTC_DRV_EFI policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'm'}> +CONFIG_RTC_DRV_EFI note<'LP: #1583738'> + +CONFIG_RTC_DRV_TWL4030 policy<{'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_TWL4030 note<'boot essential on OMAP3/OMAP4'> + +CONFIG_RT_GROUP_SCHED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RT_GROUP_SCHED note<'LP: #1875665'> + +CONFIG_S390_UV_UAPI policy<{'s390x': 'y'}> +CONFIG_S390_UV_UAPI note<'LP: #2048919'> + +CONFIG_SAMPLE_TRACE_PRINTK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SAMPLE_TRACE_PRINTK note<'Required for ftrace selftests'> + +CONFIG_SATA_AHCI_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_AHCI_PLATFORM note<'boot essential on highbank'> + +CONFIG_SATA_HIGHBANK policy<{'armhf': 'y'}> +CONFIG_SATA_HIGHBANK note<'LP: #1703430'> + +CONFIG_SCHED_TOPOLOGY_VERTICAL policy<{'s390x': 'y'}> +CONFIG_SCHED_TOPOLOGY_VERTICAL note<'LP: #2072760'> + +CONFIG_SCSI_IPR_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_IPR_DUMP note<'LP: #1343109'> + +CONFIG_SCSI_IPR_TRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_IPR_TRACE note<'LP: #1343109'> + +CONFIG_SCSI_SYM53C8XX_2 policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_SYM53C8XX_2 note<'{LP: #2118499}'> + +CONFIG_SCSI_VIRTIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_VIRTIO note<'enable initrdless boot in VMs for ease of use, cloud-kernel parity and disaster recovery, LP: #1685291'> + +CONFIG_SECURITY_SAFESETID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SAFESETID note<'LP: #1845391'> + +CONFIG_SERIAL_8250_DW policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_DW note<'several RISC-V boards needs this for console output'> + +CONFIG_SERIAL_8250_MID policy<{'amd64': 'y'}> +CONFIG_SERIAL_8250_MID note<'required to provide console on some Intel SoC platforms (LP: #2009283)'> + +CONFIG_SERIAL_DEV_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SERIAL_DEV_BUS note<'LP: #1739939'> + +CONFIG_SERIAL_DEV_CTRL_TTYPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SERIAL_DEV_CTRL_TTYPORT note<'LP: #1739939'> + +CONFIG_SERIAL_SH_SCI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_SH_SCI note<'LP: #2022361'> + +CONFIG_SERIAL_SH_SCI_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_SH_SCI_CONSOLE note<'LP: #2022361'> + +CONFIG_SERIAL_SH_SCI_EARLYCON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_SH_SCI_EARLYCON note<'LP: #2022361'> + +CONFIG_SETEND_EMULATION policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_SETEND_EMULATION note<'LP: #1545542'> + +CONFIG_SMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMC note<'LP: #1789934'> + +CONFIG_SMC_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMC_DIAG note<'LP: #1789934'> + +CONFIG_SND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND note<'not autoloadable on omap'> + +CONFIG_SND_HDA_POWER_SAVE_DEFAULT policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_SND_HDA_POWER_SAVE_DEFAULT note<'LP: #1804265'> + +CONFIG_SND_HDA_RECONFIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_RECONFIG note<'allows fixes to be tested live'> + +CONFIG_SND_PCM_OSS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_PCM_OSS note<'deprecated in favour of pulseaudio emulation'> + +CONFIG_SND_SOC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC note<'not autoloadable on omap'> + +CONFIG_SND_SOC_AMD_RENOIR policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_RENOIR note<'LP: #1881046'> + +CONFIG_SND_SOC_AMD_RENOIR_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_RENOIR_MACH note<'LP: #1881046'> + +CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH note<'LP: #1921632'> + +CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES policy<{'amd64': 'y'}> +CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES note<'LP: #1921632'> + +CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC note<'LP: #1848490'> + +CONFIG_SND_SOC_SOF_HDA_LINK policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SOF_HDA_LINK note<'LP: #1848490'> + +CONFIG_SOUND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SOUND note<'not autoloadable on omap'> + +CONFIG_SOUNDWIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SOUNDWIRE note<'LP: #1855685'> + +CONFIG_SOUND_OSS_CORE_PRECLAIM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SOUND_OSS_CORE_PRECLAIM note<'LP: #1385510'> + +CONFIG_SQUASHFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS note<'LP: #1593134'> + +CONFIG_SQUASHFS_4K_DEVBLK_SIZE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SQUASHFS_4K_DEVBLK_SIZE note<'non-default block size'> + +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU note<'LP: #1980861'> + +CONFIG_STACK_VALIDATION policy<{'amd64': 'y'}> +CONFIG_STACK_VALIDATION note<'needed for livepatch'> + +CONFIG_SWP_EMULATION policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_SWP_EMULATION note<'LP: #1545542'> + +CONFIG_SYSFB_SIMPLEFB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_SYSFB_SIMPLEFB note<'LP: #1965303'> + +CONFIG_TCG_TIS_I2C_ATMEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_I2C_ATMEL note<'LP: #1643652'> + +CONFIG_TCG_TIS_I2C_INFINEON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_I2C_INFINEON note<'LP: #1643652'> + +CONFIG_TCG_TIS_I2C_NUVOTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_I2C_NUVOTON note<'LP: #1643652'> + +CONFIG_TCG_TPM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCG_TPM note<'needed for early validation'> + +CONFIG_TIMERLAT_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIMERLAT_TRACER note<'This enables the osnoise tracer for the kernel. LP: #2018591'> + +CONFIG_TMPFS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TMPFS_POSIX_ACL note<'some /dev nodes require POSIX ACLs, like /dev/dsp'> + +CONFIG_TOUCHSCREEN_APPLE_Z2 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_APPLE_Z2 note<'LP: #2115758'> + +CONFIG_TOUCHSCREEN_ELAN policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ELAN note<'LP: #1630238'> + +CONFIG_TUNE_Z16 policy<{'s390x': 'y'}> +CONFIG_TUNE_Z16 note<'LP: #1982833 in general, always pick the newest tune available'> + +CONFIG_UBSAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_UBSAN note<'LP: #1942215'> + +CONFIG_UNWINDER_FRAME_POINTER policy<{'amd64': 'y', 'armhf': 'y'}> +CONFIG_UNWINDER_FRAME_POINTER note<'needed for livepatch'> + +CONFIG_USB_EHCI_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EHCI_HCD note<'ensures USB 2.0/1.1 probe ordering'> + +CONFIG_USB_EHCI_HCD_PLATFORM policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_EHCI_HCD_PLATFORM note<'Dont use the generic ehci/ohci code on omap, it doesnt work'> + +CONFIG_USB_HCD_BCMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_HCD_BCMA note<'USB_{O,E}HCI_HCD_PLATFORM must be off on omap'> + +CONFIG_USB_HCD_SSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_HCD_SSB note<'USB_{O,E}HCI_HCD_PLATFORM must be off on omap'> + +CONFIG_USB_M66592 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_M66592 note<'gadget device'> + +CONFIG_USB_MUSB_HDRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MUSB_HDRC note<'not autoloadable on omap'> + +CONFIG_USB_OTG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'y'}> +CONFIG_USB_OTG note<'LP: #1411295'> + +CONFIG_USB_SERIAL_DEBUG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_DEBUG note<'not actually debug'> + +CONFIG_USB_UHCI_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_UHCI_HCD note<'ensures USB 2.0/1.1 probe ordering'> + +CONFIG_USB_XHCI_DBGCAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_XHCI_DBGCAP note<'LP: #1730832'> + +CONFIG_USB_XHCI_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_XHCI_HCD note<'ensures USB 2.0/1.1 probe ordering'> + +CONFIG_VFAT_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFAT_FS note<'needed on arm to ensure we can write the kernel when replacing'> + +CONFIG_VFIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VFIO note<'LP: #1636733'> + +CONFIG_VFIO_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VFIO_PCI note<'LP: #1636733'> + +CONFIG_VFIO_PCI_ZDEV_KVM policy<{'s390x': 'y'}> +CONFIG_VFIO_PCI_ZDEV_KVM note<'LP: #2042853'> + +CONFIG_VIDEO_VIMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VIMC note<'LP: #1831482'> + +CONFIG_VIRTIO_BLK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_BLK note<'LP: #2030745'> + +CONFIG_VIRTIO_MMIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_VIRTIO_MMIO note<'LP: #1557689'> + +CONFIG_VIRTIO_NET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_NET note<'KVM paravirt support -- cloud-init currently racy with this as a module (LP: #2036968)'> + +CONFIG_WWAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_WWAN note<'LP: #2033406'> + +CONFIG_X509_CERTIFICATE_PARSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_X509_CERTIFICATE_PARSER note<'module signing'> + +CONFIG_X86_ACPI_CPUFREQ policy<{'amd64': 'y'}> +CONFIG_X86_ACPI_CPUFREQ note<'not autoloadable'> + +CONFIG_X86_KERNEL_IBT policy<{'amd64': 'n'}> +CONFIG_X86_KERNEL_IBT note<'LP: #1980484'> + +CONFIG_X86_PCC_CPUFREQ policy<{'amd64': 'y'}> +CONFIG_X86_PCC_CPUFREQ note<'not autoloadable'> + +CONFIG_X86_POWERNOW_K8 policy<{'amd64': 'y'}> +CONFIG_X86_POWERNOW_K8 note<'not autoloadable'> + +CONFIG_X86_SPEEDSTEP_CENTRINO policy<{'amd64': 'y'}> +CONFIG_X86_SPEEDSTEP_CENTRINO note<'not autoloadable'> + +CONFIG_X86_UV policy<{'amd64': 'y'}> +CONFIG_X86_UV note<'LP: #1863810'> + +CONFIG_X86_X32_ABI policy<{'amd64': 'n'}> +CONFIG_X86_X32_ABI note<'LP: #1994516'> + +CONFIG_XEN_512GB policy<{'amd64': 'y'}> +CONFIG_XEN_512GB note<'Q: is this related to the utlemming questions on memory size?'> + +CONFIG_XEN_ACPI_PROCESSOR policy<{'amd64': 'y'}> +CONFIG_XEN_ACPI_PROCESSOR note<'boot essential on XEN host'> + +CONFIG_XEN_BLKDEV_FRONTEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_BLKDEV_FRONTEND note<'not autoloadable -- XEN paravirt support'> + +CONFIG_XEN_NETDEV_FRONTEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_NETDEV_FRONTEND note<'not autoloadable -- XEN paravirt support'> + +CONFIG_XZ_DEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC note<'boot essential -- initramfs decompressor'> + +CONFIG_ZLIB_DFLTCC policy<{'s390x': 'y'}> +CONFIG_ZLIB_DFLTCC note<'LP: #1830208'> + +CONFIG_ZONE_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 's390x': 'y'}> +CONFIG_ZONE_DMA note<'LP: #1628523'> + + +# ---- Annotations without notes ---- + +CONFIG_104_QUAD_8 policy<{'amd64': 'm'}> +CONFIG_60XX_WDT policy<{'amd64': 'm'}> +CONFIG_64BIT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_6LOWPAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_6LOWPAN_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_ICMPV6 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_UDP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_NHC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_DEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_FRAGMENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_HOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_MOBILITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_ROUTING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_UDP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_8139CP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_8139TOO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_8139TOO_8129 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_8139TOO_PIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_8139TOO_TUNE_TWISTER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_8139_OLD_RX_RESET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_842_COMPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_842_DECOMPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_88PM886_GPADC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_9P_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_9P_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_9P_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_9P_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_A11Y_BRAILLE_CONSOLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_A64FX_DIAG policy<{'arm64': 'y'}> +CONFIG_ABP060MG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ABP2030PA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ABP2030PA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ABP2030PA_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AC97_BUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ACERHDF policy<{'amd64': 'm'}> +CONFIG_ACER_WIRELESS policy<{'amd64': 'm'}> +CONFIG_ACER_WMI policy<{'amd64': 'm'}> +CONFIG_ACLINT_SSWI policy<{'riscv64': 'n'}> +CONFIG_ACORN_PARTITION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_AC policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_ADXL policy<{'amd64': 'y'}> +CONFIG_ACPI_AGDI policy<{'arm64': 'y'}> +CONFIG_ACPI_ALS policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_APEI policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_APEI_EINJ policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_ACPI_APEI_EINJ_CXL policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_APEI_ERST_DEBUG policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_ACPI_APEI_GHES policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_APEI_GHES_NVIDIA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_ACPI_APEI_MEMORY_FAILURE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_APEI_PCIEAER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_APEI_SEA policy<{'arm64': 'y'}> +CONFIG_ACPI_APMT policy<{'arm64': 'y'}> +CONFIG_ACPI_BATTERY policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_BGRT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_BUTTON policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_CCA_REQUIRED policy<{'arm64': 'y'}> +CONFIG_ACPI_CMPC policy<{'amd64': 'm'}> +CONFIG_ACPI_CONFIGFS policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_CONTAINER policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_CPPC_CPUFREQ policy<{'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_CPPC_CPUFREQ_FIE policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_CPPC_LIB policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_CPU_FREQ_PSS policy<{'amd64': 'y'}> +CONFIG_ACPI_CUSTOM_DSDT_FILE policy<{'amd64': '""'}> +CONFIG_ACPI_DEBUG policy<{'amd64': 'y', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_ACPI_DEBUGGER policy<{'amd64': 'y', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_ACPI_DEBUGGER_USER policy<{'amd64': 'y'}> +CONFIG_ACPI_DOCK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_DPTF policy<{'amd64': 'y'}> +CONFIG_ACPI_EC policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_EC_DEBUGFS policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_EXTLOG policy<{'amd64': 'm'}> +CONFIG_ACPI_FAN policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_FFH policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_FPDT policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_GENERIC_GSI policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_GTDT policy<{'arm64': 'y'}> +CONFIG_ACPI_HED policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_HMAT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_HOTPLUG_CPU policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_HOTPLUG_IOAPIC policy<{'amd64': 'y'}> +CONFIG_ACPI_HOTPLUG_MEMORY policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_I2C_OPREGION policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_IORT policy<{'arm64': 'y'}> +CONFIG_ACPI_IPMI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_LEGACY_TABLES_LOOKUP policy<{'amd64': 'y'}> +CONFIG_ACPI_LPIT policy<{'amd64': 'y'}> +CONFIG_ACPI_MADT_WAKEUP policy<{'amd64': 'y'}> +CONFIG_ACPI_MCFG policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_MDIO policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_MPAM policy<{'arm64': 'y'}> +CONFIG_ACPI_MRRM policy<{'amd64': 'y'}> +CONFIG_ACPI_NFIT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_NHLT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_NUMA policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_PCC policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_PCI_SLOT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_PFRUT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_PLATFORM_PROFILE policy<{'amd64': 'y', 'arm64': 'm', 'riscv64': '-'}> +CONFIG_ACPI_PPTT policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_PRMT policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_PROCESSOR policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_PROCESSOR_AGGREGATOR policy<{'amd64': 'm'}> +CONFIG_ACPI_PROCESSOR_CSTATE policy<{'amd64': 'y'}> +CONFIG_ACPI_PROCESSOR_IDLE policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_QUICKSTART policy<{'amd64': 'm'}> +CONFIG_ACPI_REDUCED_HARDWARE_ONLY policy<{'amd64': 'n', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_REV_OVERRIDE_POSSIBLE policy<{'amd64': 'y'}> +CONFIG_ACPI_RIMT policy<{'riscv64': 'y'}> +CONFIG_ACPI_SBS policy<{'amd64': 'm'}> +CONFIG_ACPI_SLEEP policy<{'amd64': 'y'}> +CONFIG_ACPI_SPCR_TABLE policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT policy<{'amd64': 'y'}> +CONFIG_ACPI_TABLE_LIB policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_TABLE_UPGRADE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_TAD policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_THERMAL policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_THERMAL_LIB policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_THERMAL_REL policy<{'amd64': 'm'}> +CONFIG_ACPI_TOSHIBA policy<{'amd64': 'm'}> +CONFIG_ACPI_VIDEO policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_VIOT policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_WATCHDOG policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_WMI policy<{'amd64': 'm'}> +CONFIG_ACPI_WMI_LEGACY_DEVICE_NAMES policy<{'amd64': 'y'}> +CONFIG_ACQUIRE_WDT policy<{'amd64': 'm'}> +CONFIG_ACRN_GUEST policy<{'amd64': 'y'}> +CONFIG_ACRN_HSM policy<{'amd64': 'm'}> +CONFIG_AD2S1200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD2S1210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD2S90 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD3530R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD3552R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD3552R_HS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD3552R_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4062 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4080 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4130 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4134 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4170_4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4695 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4851 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5064 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD525X_DPOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AD525X_DPOT_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD525X_DPOT_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5272 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5380 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5421 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5446 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5446_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5446_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5449 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5504 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5592R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5592R_BASE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5593R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5624R_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5686 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5686_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5696_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5755 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5758 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5761 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5764 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5766 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5770R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5791 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5933 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7091R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7091R5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7091R8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7124 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7173 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7191 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7192 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7266 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7280 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7291 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7292 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7293 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7298 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7380 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7405 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD74115 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD74413R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7476 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7606 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7606_IFACE_PARALLEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7606_IFACE_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7625 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7746 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7766 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7768_1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7779 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7791 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7793 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7816 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7887 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7923 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7944 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7949 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD799X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD8366 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD8460 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD8801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD9467 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD9523 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD9739A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD9832 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD9834 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADA4250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADAPTEC_STARFIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ADC_BATTERY_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADE9000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADF4350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADF4371 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADF4377 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ADFS_FS_RW policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ADIN1100_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ADIN1110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIN_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ADIS16080 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16130 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16136 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16203 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16209 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16260 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16400 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16460 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16475 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16480 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16550 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADI_AXI_ADC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_ADI_AXI_DAC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_ADI_I3C_MASTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADJD_S311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADL8113 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADM8211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADMFM2000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADMV1013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADMV1014 policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADMV4420 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADMV8818 policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADP810 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADRF6780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADT7316 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADT7316_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADT7316_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADUX1020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADVANTECH_EC_WDT policy<{'amd64': 'm'}> +CONFIG_ADVANTECH_WDT policy<{'amd64': 'm'}> +CONFIG_ADVISE_SYSCALLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ADV_SWBUTTON policy<{'amd64': 'm'}> +CONFIG_ADXL313 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL313_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL313_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL345 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL345_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL345_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL355 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL355_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL355_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL367 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL367_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL367_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL372 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL372_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL372_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL380 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL380_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL380_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXRS290 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXRS450 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD_SIGMA_DELTA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AEABI policy<{'armhf': 'y'}> +CONFIG_AF8133J policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AFE4403 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AFE4404 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AFFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AFIUCV policy<{'s390x': 'm'}> +CONFIG_AFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AFS_DEBUG_CURSOR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AFS_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AF_KCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AF_RXRPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AF_RXRPC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AF_RXRPC_INJECT_LOSS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AF_RXRPC_INJECT_RX_DELAY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AF_RXRPC_IPV6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AF_UNIX_OOB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AGP_AMD64 policy<{'amd64': 'y'}> +CONFIG_AGP_INTEL policy<{'amd64': 'y'}> +CONFIG_AGP_SIS policy<{'amd64': 'm'}> +CONFIG_AGP_VIA policy<{'amd64': 'y'}> +CONFIG_AHCI_CEVA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AHCI_DM816 policy<{'armhf': 'm'}> +CONFIG_AHCI_DWC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AHCI_IMX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_AHCI_MTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AHCI_MVEBU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AHCI_QORIQ policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_AHCI_SUNXI policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_AHCI_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AHCI_XGENE policy<{'arm64': 'm'}> +CONFIG_AIC79XX_CMDS_PER_DEVICE policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32'}> +CONFIG_AIC79XX_DEBUG_ENABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_AIC79XX_DEBUG_MASK policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_AIC79XX_REG_PRETTY_PRINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_AIC79XX_RESET_DELAY_MS policy<{'amd64': '5000', 'arm64': '5000', 'armhf': '5000', 'ppc64el': '5000', 'riscv64': '5000'}> +CONFIG_AIC7XXX_CMDS_PER_DEVICE policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8'}> +CONFIG_AIC7XXX_DEBUG_ENABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_AIC7XXX_DEBUG_MASK policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_AIC7XXX_REG_PRETTY_PRINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_AIC7XXX_RESET_DELAY_MS policy<{'amd64': '5000', 'arm64': '5000', 'armhf': '5000', 'ppc64el': '5000', 'riscv64': '5000'}> +CONFIG_AIC94XX_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_AIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AIROHA_CPU_PM_DOMAIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AIROHA_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AIROHA_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AIR_EN8811H_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AIX_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_AK09911 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AK8974 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AK8975 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AL3000A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AL3010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AL3320A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ALIBABA_ENI_VDPA policy<{'amd64': 'm'}> +CONFIG_ALIBABA_UNCORE_DRW_PMU policy<{'arm64': 'm'}> +CONFIG_ALIENWARE_WMI policy<{'amd64': 'm'}> +CONFIG_ALIENWARE_WMI_LEGACY policy<{'amd64': 'y'}> +CONFIG_ALIENWARE_WMI_WMAX policy<{'amd64': 'y'}> +CONFIG_ALIGNMENT_TRAP policy<{'armhf': 'y'}> +CONFIG_ALIM1535_WDT policy<{'amd64': 'm'}> +CONFIG_ALIM7101_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ALLOW_DEV_COREDUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ALS31300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ALTERA_FREEZE_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ALTERA_MBOX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ALTERA_MSGDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ALTERA_PR_IP_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ALTERA_PR_IP_CORE_PLAT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ALTERA_STAPL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ALTERA_TSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ALTERNATE_USER_ADDRESS_SPACE policy<{'s390x': 'y'}> +CONFIG_ALTIVEC policy<{'ppc64el': 'y'}> +CONFIG_ALX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_AL_FIC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_AM2315 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AM335X_CONTROL_USB policy<{'armhf': 'm'}> +CONFIG_AM335X_PHY_USB policy<{'armhf': 'm'}> +CONFIG_AMBA_PL08X policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_AMD8111_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_AMDTEE policy<{'amd64': 'm'}> +CONFIG_AMD_3D_VCACHE policy<{'amd64': 'm'}> +CONFIG_AMD_AE4DMA policy<{'amd64': 'm'}> +CONFIG_AMD_ATL policy<{'amd64': 'm'}> +CONFIG_AMD_ATL_PRM policy<{'amd64': 'y'}> +CONFIG_AMD_HFI policy<{'amd64': 'y'}> +CONFIG_AMD_HSMP policy<{'amd64': 'm'}> +CONFIG_AMD_HSMP_ACPI policy<{'amd64': 'm'}> +CONFIG_AMD_HSMP_PLAT policy<{'amd64': 'm'}> +CONFIG_AMD_IOMMU policy<{'amd64': 'y'}> +CONFIG_AMD_IOMMU_IOMMUFD policy<{'amd64': 'n'}> +CONFIG_AMD_ISP_PLATFORM policy<{'amd64': 'm'}> +CONFIG_AMD_MEM_ENCRYPT policy<{'amd64': 'y'}> +CONFIG_AMD_MP2_STB policy<{'amd64': 'y'}> +CONFIG_AMD_NB policy<{'amd64': 'y'}> +CONFIG_AMD_NODE policy<{'amd64': 'y'}> +CONFIG_AMD_NUMA policy<{'amd64': 'y'}> +CONFIG_AMD_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AMD_PMC policy<{'amd64': 'm'}> +CONFIG_AMD_PMF policy<{'amd64': 'm'}> +CONFIG_AMD_PMF_DEBUG policy<{'amd64': 'y'}> +CONFIG_AMD_PTDMA policy<{'amd64': 'm'}> +CONFIG_AMD_QDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AMD_SBRMI_HWMON policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_AMD_SBRMI_I2C policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_AMD_SECURE_AVIC policy<{'amd64': 'y'}> +CONFIG_AMD_SFH_HID policy<{'amd64': 'm'}> +CONFIG_AMD_WBRF policy<{'amd64': 'y'}> +CONFIG_AMD_XGBE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_AMD_XGBE_DCB policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_AMD_XGBE_HAVE_ECC policy<{'amd64': 'y'}> +CONFIG_AMIGA_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_AMILO_RFKILL policy<{'amd64': 'm'}> +CONFIG_AMLOGIC_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU policy<{'arm64': 'm'}> +CONFIG_AMPERE_ERRATUM_AC03_CPU_38 policy<{'arm64': 'y'}> +CONFIG_AMPERE_ERRATUM_AC04_CPU_23 policy<{'arm64': 'y'}> +CONFIG_AMT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ANDROID_BINDER_IPC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ANON_VMA_NAME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AOSONG_AGS02MA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AP policy<{'s390x': 'y'}> +CONFIG_APDS9160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_APDS9300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_APDS9306 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_APDS9802ALS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_APDS9960 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_APERTURE_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_APM_EMULATION policy<{'armhf': 'n'}> +CONFIG_APPLDATA_BASE policy<{'s390x': 'y'}> +CONFIG_APPLDATA_MEM policy<{'s390x': 'm'}> +CONFIG_APPLDATA_NET_SUM policy<{'s390x': 'm'}> +CONFIG_APPLDATA_OS policy<{'s390x': 'm'}> +CONFIG_APPLE_ADMAC policy<{'arm64': 'm'}> +CONFIG_APPLE_AIC policy<{'arm64': 'y'}> +CONFIG_APPLE_DART policy<{'arm64': 'm'}> +CONFIG_APPLE_GMUX policy<{'amd64': 'm'}> +CONFIG_APPLE_M1_CPU_PMU policy<{'arm64': 'y'}> +CONFIG_APPLE_MAILBOX policy<{'arm64': 'm'}> +CONFIG_APPLE_MFI_FASTCHARGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_APPLE_PMGR_PWRSTATE policy<{'arm64': 'y'}> +CONFIG_APPLE_PROPERTIES policy<{'amd64': 'y'}> +CONFIG_APPLE_RTKIT policy<{'arm64': 'm'}> +CONFIG_APPLE_SART policy<{'arm64': 'm'}> +CONFIG_APPLE_TUNABLE policy<{'arm64': 'm'}> +CONFIG_APPLE_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_APPLICOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_APQ_GCC_8084 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_APQ_MMCC_8084 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_AP_DEBUG policy<{'s390x': 'n'}> +CONFIG_AQTION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AQUANTIA_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AR5523 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCH_32BIT_OFF_T policy<{'armhf': 'y'}> +CONFIG_ARCH_32BIT_USTAT_F_TINODE policy<{'s390x': 'y'}> +CONFIG_ARCH_ACTIONS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_AIROHA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_ALPINE policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_ARCH_ANDES policy<{'riscv64': 'n'}> +CONFIG_ARCH_ANLOGIC policy<{'riscv64': 'n'}> +CONFIG_ARCH_APPLE policy<{'arm64': 'y'}> +CONFIG_ARCH_ARTPEC policy<{'armhf': 'y'}> +CONFIG_ARCH_ASPEED policy<{'armhf': 'y'}> +CONFIG_ARCH_AT91 policy<{'armhf': 'n'}> +CONFIG_ARCH_AXIADO policy<{'arm64': 'y'}> +CONFIG_ARCH_AXXIA policy<{'armhf': 'y'}> +CONFIG_ARCH_BCM policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_ARCH_BERLIN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS policy<{'arm64': 'y'}> +CONFIG_ARCH_BINFMT_ELF_STATE policy<{'arm64': 'y', 's390x': '-'}> +CONFIG_ARCH_BITMAIN policy<{'arm64': 'y'}> +CONFIG_ARCH_BLAIZE policy<{'arm64': 'y'}> +CONFIG_ARCH_BST policy<{'arm64': 'y'}> +CONFIG_ARCH_CANAAN policy<{'riscv64': 'n'}> +CONFIG_ARCH_CC_CAN_LINK policy<{'armhf': 'y', 's390x': 'y'}> +CONFIG_ARCH_CIX policy<{'arm64': 'y'}> +CONFIG_ARCH_CLOCKSOURCE_INIT policy<{'amd64': 'y', 'riscv64': '-'}> +CONFIG_ARCH_CONFIGURES_CPU_MITIGATIONS policy<{'amd64': 'y'}> +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 's390x': 'y'}> +CONFIG_ARCH_CPUIDLE_HALTPOLL policy<{'amd64': 'y'}> +CONFIG_ARCH_CPU_PROBE_RELEASE policy<{'ppc64el': 'y'}> +CONFIG_ARCH_DEFAULT_CRASH_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG policy<{'arm64': 'y'}> +CONFIG_ARCH_DIGICOLOR policy<{'armhf': 'n'}> +CONFIG_ARCH_DISABLE_KASAN_INLINE policy<{'ppc64el': 'y'}> +CONFIG_ARCH_DMA_ADDR_T_64BIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_DMA_DEFAULT_COHERENT policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_DOVE policy<{'armhf': 'n'}> +CONFIG_ARCH_EMEV2 policy<{'armhf': 'y'}> +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_ENABLE_THP_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_ESWIN policy<{'riscv64': 'n'}> +CONFIG_ARCH_EXYNOS policy<{'arm64': 'n', 'armhf': 'y'}> +CONFIG_ARCH_EXYNOS3 policy<{'armhf': 'n'}> +CONFIG_ARCH_EXYNOS4 policy<{'armhf': 'n'}> +CONFIG_ARCH_EXYNOS5 policy<{'armhf': 'n'}> +CONFIG_ARCH_FLATMEM_ENABLE policy<{'armhf': 'y'}> +CONFIG_ARCH_FORCE_MAX_ORDER policy<{'arm64': '13', 'arm64-generic': '10', 'armhf': '11', 'ppc64el': '8'}> +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAS_ADD_PAGES policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_HAS_BANDGAP policy<{'armhf': 'y'}> +CONFIG_ARCH_HAS_BATCHED_DMA_SYNC policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_BINFMT_FLAT policy<{'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_CACHE_LINE_SIZE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_HAS_CC_CAN_LINK policy<{'armhf': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_CC_PLATFORM policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_HAS_COPY_MC policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_HAS_CPU_ATTACK_VECTORS policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_CPU_CACHE_ALIASING policy<{'armhf': 'y'}> +CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAS_CPU_FINALIZE_INIT policy<{'amd64': 'y', 'armhf': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_CPU_PASID policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_CPU_RELAX policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_CPU_RESCTRL policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DEBUG_VIRTUAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DEBUG_WX policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DMA_ALLOC policy<{'armhf': 'y'}> +CONFIG_ARCH_HAS_DMA_MAP_DIRECT policy<{'ppc64el': 'y'}> +CONFIG_ARCH_HAS_DMA_OPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DMA_PREP_COHERENT policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_EARLY_DEBUG policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_ELFCORE_COMPAT policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_ELF_CORE_EFLAGS policy<{'riscv64': 'y'}> +CONFIG_ARCH_HAS_ELF_RANDOMIZE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_EXECMEM_ROX policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_FAST_MULTIPLIER policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_FORTIFY_SOURCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_GIGANTIC_PAGE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_HW_PTE_YOUNG policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_KCOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_KEEPINITRD policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_LAZY_MMU_MODE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_MEMREMAP_COMPAT_ALIGN policy<{'ppc64el': 'y'}> +CONFIG_ARCH_HAS_MEM_ENCRYPT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_MMIOWB policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_PHYS_TO_DMA policy<{'ppc64el': 'y'}> +CONFIG_ARCH_HAS_PKEYS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAS_PMEM_API policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_PREEMPT_LAZY policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_PREPARE_SYNC_CORE_CMD policy<{'riscv64': 'y'}> +CONFIG_ARCH_HAS_PTDUMP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_PTE_SPECIAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_RELR policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_RESET_CONTROLLER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_HAS_SCALED_CPUTIME policy<{'s390x': 'y'}> +CONFIG_ARCH_HAS_SETUP_DMA_OPS policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_SET_DIRECT_MAP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_SET_MEMORY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_STRICT_MODULE_RWX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_SUBPAGE_FAULTS policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_SYSCALL_WRAPPER policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS policy<{'arm64': '-', 'armhf': 'y'}> +CONFIG_ARCH_HAS_TICK_BROADCAST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_HAS_UBSAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_USER_SHADOW_STACK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_VDSO_ARCH_DATA policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_VDSO_TIME_DATA policy<{'riscv64': '-', 's390x': 'y'}> +CONFIG_ARCH_HAS_ZONE_DMA_SET policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAVE_ELF_PROT policy<{'arm64': 'y'}> +CONFIG_ARCH_HAVE_EXTRA_ELF_NOTES policy<{'amd64': 'y'}> +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS policy<{'arm64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HI3xxx policy<{'armhf': 'y'}> +CONFIG_ARCH_HIBERNATION_HEADER policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HIBERNATION_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HIGHBANK policy<{'armhf': 'y'}> +CONFIG_ARCH_HIP01 policy<{'armhf': 'n'}> +CONFIG_ARCH_HIP04 policy<{'armhf': 'y'}> +CONFIG_ARCH_HISI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_HIX5HD2 policy<{'armhf': 'y'}> +CONFIG_ARCH_HPE policy<{'armhf': 'y'}> +CONFIG_ARCH_HPE_GXP policy<{'armhf': 'y'}> +CONFIG_ARCH_INLINE_READ_LOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_LOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_LOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_UNLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_LOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_LOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_UNLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_LOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_LOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_UNLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_ARCH_INTEL_SOCFPGA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_K3 policy<{'arm64': 'y'}> +CONFIG_ARCH_KEEMBAY policy<{'arm64': 'y'}> +CONFIG_ARCH_KEEP_MEMBLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_KEYSTONE policy<{'armhf': 'n'}> +CONFIG_ARCH_LAN969X policy<{'arm64': 'y'}> +CONFIG_ARCH_LAYERSCAPE policy<{'arm64': 'y'}> +CONFIG_ARCH_LG1K policy<{'arm64': 'y'}> +CONFIG_ARCH_MA35 policy<{'arm64': 'y'}> +CONFIG_ARCH_MAY_HAVE_PC_FDC policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_MEDIATEK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_MEMORY_PROBE policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_MESON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_MICROCHIP policy<{'arm64': 'y', 'riscv64': 'n'}> +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC policy<{'amd64': 'y'}> +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_MILBEAUT policy<{'armhf': 'y'}> +CONFIG_ARCH_MILBEAUT_M10V policy<{'armhf': 'y'}> +CONFIG_ARCH_MMAP_RND_BITS_MAX policy<{'amd64': '32', 'arm64': '33', 'arm64-generic-64k': '29', 'armhf': '16', 'ppc64el': '29', 'riscv64': '24'}> +CONFIG_ARCH_MMAP_RND_BITS_MIN policy<{'amd64': '28', 'arm64': '18', 'arm64-generic-64k': '14', 'armhf': '8', 'ppc64el': '14', 'riscv64': '18'}> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX policy<{'amd64': '16', 'arm64': '16', 'ppc64el': '13', 'riscv64': '17'}> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN policy<{'amd64': '8', 'arm64': '11', 'arm64-generic-64k': '7', 'ppc64el': '7', 'riscv64': '8'}> +CONFIG_ARCH_MMP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_MSTARV7 policy<{'armhf': 'y'}> +CONFIG_ARCH_MULTIPLATFORM policy<{'armhf': 'y'}> +CONFIG_ARCH_MULTI_V6 policy<{'armhf': 'n'}> +CONFIG_ARCH_MULTI_V6_V7 policy<{'armhf': 'y'}> +CONFIG_ARCH_MULTI_V7 policy<{'armhf': 'y'}> +CONFIG_ARCH_MVEBU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_MXC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED policy<{'armhf': 'y'}> +CONFIG_ARCH_NEEDS_DEFER_KASAN policy<{'ppc64el': 'y'}> +CONFIG_ARCH_NPCM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_NPCM7XX policy<{'armhf': 'y'}> +CONFIG_ARCH_NXP policy<{'arm64': 'y'}> +CONFIG_ARCH_OMAP policy<{'armhf': 'y'}> +CONFIG_ARCH_OMAP2PLUS policy<{'armhf': 'y'}> +CONFIG_ARCH_OMAP2PLUS_TYPICAL policy<{'armhf': 'y'}> +CONFIG_ARCH_OMAP3 policy<{'armhf': 'n'}> +CONFIG_ARCH_OMAP4 policy<{'armhf': 'n'}> +CONFIG_ARCH_OPTIONAL_KERNEL_RWX policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_PENSANDO policy<{'arm64': 'y'}> +CONFIG_ARCH_PKEY_BITS policy<{'amd64': '4', 'arm64': '3', 'ppc64el': '5'}> +CONFIG_ARCH_PROC_KCORE_TEXT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_QCOM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_QCOM_RESERVE_SMEM policy<{'armhf': 'y'}> +CONFIG_ARCH_R7S72100 policy<{'armhf': 'y'}> +CONFIG_ARCH_R7S9210 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A73A4 policy<{'armhf': 'n'}> +CONFIG_ARCH_R8A7740 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7742 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7743 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7744 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7745 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A77470 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A7778 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7779 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7790 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7791 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7792 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7793 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7794 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A77951 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77960 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77961 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77965 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77970 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77980 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77990 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77995 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A78000 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A06G032 policy<{'armhf': 'y'}> +CONFIG_ARCH_R9A07G043 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A07G044 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A07G054 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A08G045 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A08G046 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G011 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G047 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G056 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G057 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G077 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G087 policy<{'arm64': 'y'}> +CONFIG_ARCH_RCAR_GEN1 policy<{'armhf': 'y'}> +CONFIG_ARCH_RCAR_GEN2 policy<{'armhf': 'y'}> +CONFIG_ARCH_RCAR_GEN3 policy<{'arm64': 'y'}> +CONFIG_ARCH_RCAR_GEN4 policy<{'arm64': 'y'}> +CONFIG_ARCH_RCAR_GEN5 policy<{'arm64': 'y'}> +CONFIG_ARCH_RDA policy<{'armhf': 'y'}> +CONFIG_ARCH_REALTEK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_REALVIEW policy<{'armhf': 'n'}> +CONFIG_ARCH_RENESAS policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'n'}> +CONFIG_ARCH_RMOBILE policy<{'armhf': 'y'}> +CONFIG_ARCH_RV64I policy<{'riscv64': 'y'}> +CONFIG_ARCH_RZG2L policy<{'arm64': 'y'}> +CONFIG_ARCH_RZN1 policy<{'armhf': 'y'}> +CONFIG_ARCH_S32 policy<{'arm64': 'y'}> +CONFIG_ARCH_S5PV210 policy<{'armhf': 'n'}> +CONFIG_ARCH_SEATTLE policy<{'arm64': 'y'}> +CONFIG_ARCH_SELECTS_CRASH_DUMP policy<{'ppc64el': 'y'}> +CONFIG_ARCH_SELECTS_KEXEC policy<{'riscv64': 'y'}> +CONFIG_ARCH_SELECTS_KEXEC_FILE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SELECT_MEMORY_MODEL policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SH73A0 policy<{'armhf': 'y'}> +CONFIG_ARCH_SIFIVE policy<{'riscv64': 'n'}> +CONFIG_ARCH_SOPHGO policy<{'arm64': 'y', 'riscv64': 'n'}> +CONFIG_ARCH_SPACEMIT policy<{'riscv64': 'n'}> +CONFIG_ARCH_SPARSEMEM_DEFAULT policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_SPARSEMEM_ENABLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SPARX5 policy<{'arm64': 'y'}> +CONFIG_ARCH_SPRD policy<{'arm64': 'y'}> +CONFIG_ARCH_STACKWALK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_STI policy<{'armhf': 'n'}> +CONFIG_ARCH_STM32 policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_ARCH_SUNPLUS policy<{'armhf': 'y'}> +CONFIG_ARCH_SUNXI policy<{'arm64': 'y', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_ARCH_SUPPORTS_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_AUTOFDO_CLANG policy<{'amd64': 'y'}> +CONFIG_ARCH_SUPPORTS_CFI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_CRASH_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_CRASH_HOTPLUG policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_HUGETLBFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_INT128 policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_BZIMAGE_VERIFY_SIG policy<{'amd64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_FILE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_HANDOVER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_JUMP policy<{'amd64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_SIG policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_SIG_FORCE policy<{'amd64': 'y'}> +CONFIG_ARCH_SUPPORTS_LTO_CLANG policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_PMD_PFNMAP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_PROPELLER_CLANG policy<{'amd64': 'y'}> +CONFIG_ARCH_SUPPORTS_PUD_PFNMAP policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_RT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_SCHED_CLUSTER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_SCHED_MC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_SCHED_SMT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_UPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUSPEND_NONZERO_CPU policy<{'ppc64el': 'y'}> +CONFIG_ARCH_SUSPEND_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SYNQUACER policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_TEGRA_114_SOC policy<{'armhf': 'y'}> +CONFIG_ARCH_TEGRA_124_SOC policy<{'armhf': 'y'}> +CONFIG_ARCH_TEGRA_132_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_186_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_194_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_210_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_234_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_238_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_241_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_264_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_2x_SOC policy<{'armhf': 'y'}> +CONFIG_ARCH_TEGRA_3x_SOC policy<{'armhf': 'y'}> +CONFIG_ARCH_TENSTORRENT policy<{'riscv64': 'n'}> +CONFIG_ARCH_THEAD policy<{'riscv64': 'n'}> +CONFIG_ARCH_THUNDER policy<{'arm64': 'y'}> +CONFIG_ARCH_THUNDER2 policy<{'arm64': 'y'}> +CONFIG_ARCH_U8500 policy<{'armhf': 'n'}> +CONFIG_ARCH_UNIPHIER policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_ARCH_USERFLAGS policy<{'armhf': '"-mlittle-endian"', 's390x': '"-m64"'}> +CONFIG_ARCH_USES_CFI_GENERIC_LLVM_PASS policy<{'armhf': 'y'}> +CONFIG_ARCH_USES_HIGH_VMA_FLAGS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_USES_PG_ARCH_2 policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_USES_PG_ARCH_3 policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_BUILTIN_BSWAP policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_USE_CMPXCHG_LOCKREF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_USE_GNU_PROPERTY policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_MEMREMAP_PROT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_USE_MEMTEST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_USE_QUEUED_RWLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_USE_QUEUED_SPINLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_USE_SYM_ANNOTATIONS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_USING_PATCHABLE_FUNCTION_ENTRY policy<{'ppc64el': 'y'}> +CONFIG_ARCH_VEXPRESS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA policy<{'armhf': 'y'}> +CONFIG_ARCH_VEXPRESS_SPC policy<{'armhf': 'y'}> +CONFIG_ARCH_VEXPRESS_TC2_PM policy<{'armhf': 'y'}> +CONFIG_ARCH_VIRT policy<{'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_VISCONTI policy<{'arm64': 'y'}> +CONFIG_ARCH_VMLINUX_NEEDS_RELOCS policy<{'amd64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANTS_CLOCKSOURCE_READ_INLINE policy<{'amd64': 'y'}> +CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT policy<{'amd64': 'y', 's390x': '-'}> +CONFIG_ARCH_WANTS_EXECMEM_LATE policy<{'arm64': 'y'}> +CONFIG_ARCH_WANTS_NO_INSTR policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANTS_PRE_LINK_VMLINUX policy<{'ppc64el': 'y'}> +CONFIG_ARCH_WANTS_THP_SWAP policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 's390x': '-'}> +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_WANT_FLAT_DTB_INSTALL policy<{'armhf': 'y'}> +CONFIG_ARCH_WANT_FRAME_POINTERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_WANT_GENERAL_HUGETLB policy<{'amd64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_ARCH_WANT_HUGETLB_VMEMMAP_PREINIT policy<{'amd64': 'y'}> +CONFIG_ARCH_WANT_HUGE_PMD_SHARE policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'riscv64': 'y'}> +CONFIG_ARCH_WANT_IPC_PARSE_VERSION policy<{'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANT_IRQS_OFF_ACTIVATE_MM policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANT_KERNEL_PMD_MKWRITE policy<{'s390x': 'y'}> +CONFIG_ARCH_WANT_LD_ORPHAN_WARN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANT_OLD_COMPAT_IPC policy<{'amd64': 'y', 'ppc64el': '-', 's390x': '-'}> +CONFIG_ARCH_WANT_OPTIMIZE_DAX_VMEMMAP policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP policy<{'amd64': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_ARCH_WANT_PMD_MKWRITE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_WEAK_RELEASE_ACQUIRE policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_WM8850 policy<{'armhf': 'n'}> +CONFIG_ARCH_XGENE policy<{'arm64': 'y'}> +CONFIG_ARCH_ZYNQ policy<{'armhf': 'n'}> +CONFIG_ARCH_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_ARCNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ARCNET_1051 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_1201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_CAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_COM20020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_COM20020_CS policy<{'amd64': 'm'}> +CONFIG_ARCNET_COM20020_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_COM90xx policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_COM90xxIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_RIM_I policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARC_EMAC_CORE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM policy<{'armhf': 'y'}> +CONFIG_ARM64 policy<{'arm64': 'y'}> +CONFIG_ARM64_16K_PAGES policy<{'arm64': 'n'}> +CONFIG_ARM64_4K_PAGES policy<{'arm64': 'y', 'arm64-generic-64k': 'n'}> +CONFIG_ARM64_64K_PAGES policy<{'arm64': 'n', 'arm64-generic-64k': 'y'}> +CONFIG_ARM64_ACPI_PARKING_PROTOCOL policy<{'arm64': 'y'}> +CONFIG_ARM64_AMU_EXTN policy<{'arm64': 'y'}> +CONFIG_ARM64_AS_HAS_MTE policy<{'arm64': 'y'}> +CONFIG_ARM64_BRBE policy<{'arm64': 'y'}> +CONFIG_ARM64_BTI policy<{'arm64': 'y'}> +CONFIG_ARM64_CNP policy<{'arm64': 'y'}> +CONFIG_ARM64_CONTPTE policy<{'arm64': 'y'}> +CONFIG_ARM64_CONT_PMD_SHIFT policy<{'arm64': '4', 'arm64-generic-64k': '5'}> +CONFIG_ARM64_CONT_PTE_SHIFT policy<{'arm64': '4', 'arm64-generic-64k': '5'}> +CONFIG_ARM64_DEBUG_PRIORITY_MASKING policy<{'arm64': 'n'}> +CONFIG_ARM64_E0PD policy<{'arm64': 'y'}> +CONFIG_ARM64_EPAN policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1024718 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1165522 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1286807 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1319367 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1418040 policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_ARM64_ERRATUM_1463225 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1508412 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1530923 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1542419 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1742098 policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_ARM64_ERRATUM_2051678 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2054223 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2067961 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2077057 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2441007 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2441009 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2457168 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2645198 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2658417 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2966298 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_3117295 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_3194386 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_4118414 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_4193714 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_4311569 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_819472 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_824069 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_826319 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_827319 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_832075 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_834220 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_845719 policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_ARM64_GCS policy<{'arm64': 'y'}> +CONFIG_ARM64_HAFT policy<{'arm64': 'y'}> +CONFIG_ARM64_HW_AFDBM policy<{'arm64': 'y'}> +CONFIG_ARM64_LSUI policy<{'arm64': 'y'}> +CONFIG_ARM64_MPAM policy<{'arm64': 'y'}> +CONFIG_ARM64_MPAM_DRIVER policy<{'arm64': 'y'}> +CONFIG_ARM64_MPAM_DRIVER_DEBUG policy<{'arm64': 'n'}> +CONFIG_ARM64_MPAM_RESCTRL_FS policy<{'arm64': 'y'}> +CONFIG_ARM64_MTE policy<{'arm64': 'y'}> +CONFIG_ARM64_PA_BITS policy<{'arm64': '48'}> +CONFIG_ARM64_PA_BITS_48 policy<{'arm64': 'y'}> +CONFIG_ARM64_PA_BITS_52 policy<{'arm64-generic-64k': 'n'}> +CONFIG_ARM64_PLATFORM_DEVICES policy<{'arm64': 'y'}> +CONFIG_ARM64_PMEM policy<{'arm64': 'y'}> +CONFIG_ARM64_POE policy<{'arm64': 'y'}> +CONFIG_ARM64_PSEUDO_NMI policy<{'arm64': 'y'}> +CONFIG_ARM64_PTR_AUTH policy<{'arm64': 'y'}> +CONFIG_ARM64_PTR_AUTH_KERNEL policy<{'arm64': 'y'}> +CONFIG_ARM64_RAS_EXTN policy<{'arm64': 'y'}> +CONFIG_ARM64_RELOC_TEST policy<{'arm64': 'n'}> +CONFIG_ARM64_SME policy<{'arm64': 'y'}> +CONFIG_ARM64_SVE policy<{'arm64': 'y'}> +CONFIG_ARM64_SW_TTBR0_PAN policy<{'arm64': 'y'}> +CONFIG_ARM64_TAGGED_ADDR_ABI policy<{'arm64': 'y'}> +CONFIG_ARM64_TLB_RANGE policy<{'arm64': 'y'}> +CONFIG_ARM64_VA_BITS policy<{'arm64': '48'}> +CONFIG_ARM64_VA_BITS_39 policy<{'arm64': 'n', 'arm64-generic-64k': '-'}> +CONFIG_ARM64_VA_BITS_42 policy<{'arm64-generic-64k': 'n'}> +CONFIG_ARM64_VA_BITS_52 policy<{'arm64': 'n'}> +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE policy<{'arm64': 'y'}> +CONFIG_ARMADA375_USBCLUSTER_PHY policy<{'armhf': 'y'}> +CONFIG_ARMADA_370_CLK policy<{'armhf': 'y'}> +CONFIG_ARMADA_370_XP_IRQ policy<{'armhf': 'y'}> +CONFIG_ARMADA_370_XP_TIMER policy<{'armhf': 'y'}> +CONFIG_ARMADA_375_CLK policy<{'armhf': 'y'}> +CONFIG_ARMADA_37XX_CLK policy<{'arm64': 'y'}> +CONFIG_ARMADA_37XX_RWTM_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARMADA_37XX_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARMADA_38X_CLK policy<{'armhf': 'y'}> +CONFIG_ARMADA_39X_CLK policy<{'armhf': 'y'}> +CONFIG_ARMADA_AP806_SYSCON policy<{'arm64': 'y'}> +CONFIG_ARMADA_AP_CPU_CLK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARMADA_AP_CP_HELPER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARMADA_CP110_SYSCON policy<{'arm64': 'y'}> +CONFIG_ARMADA_THERMAL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARMADA_XP_CLK policy<{'armhf': 'y'}> +CONFIG_ARM_AIROHA_SOC_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_ARM_AMBA policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_ARM_APPENDED_DTB policy<{'armhf': 'y'}> +CONFIG_ARM_APPLE_SOC_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_ARCH_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_ARCH_TIMER_EVTSTREAM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND policy<{'arm64': 'y'}> +CONFIG_ARM_ARMADA_37XX_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_ARMADA_8K_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_ATAG_DTB_COMPAT policy<{'armhf': 'n'}> +CONFIG_ARM_BIG_LITTLE_CPUIDLE policy<{'armhf': 'y'}> +CONFIG_ARM_CCA_GUEST policy<{'arm64': 'm'}> +CONFIG_ARM_CCI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CCI400_COMMON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CCI400_PMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CCI400_PORT_CTRL policy<{'armhf': 'y'}> +CONFIG_ARM_CCI5xx_PMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CCI_PMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CCN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CHARLCD policy<{'armhf': 'y'}> +CONFIG_ARM_CMN policy<{'arm64': 'm'}> +CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_CPUIDLE policy<{'armhf': 'y'}> +CONFIG_ARM_CPU_SUSPEND policy<{'armhf': 'y'}> +CONFIG_ARM_CPU_TOPOLOGY policy<{'armhf': 'y'}> +CONFIG_ARM_DEBUG_WX policy<{'armhf': 'y'}> +CONFIG_ARM_DMA350 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_DMA_IOMMU_ALIGNMENT policy<{'armhf': '8'}> +CONFIG_ARM_DMA_MEM_BUFFERABLE policy<{'armhf': 'y'}> +CONFIG_ARM_DMA_USE_IOMMU policy<{'armhf': 'y'}> +CONFIG_ARM_DMC620_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_DSU_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_ERRATA_430973 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_643719 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_720789 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_754322 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_754327 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_764319 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_764369 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_773022 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_775420 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_798181 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_814220 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_818325_852422 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_821420 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_825619 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_852421 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_852423 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_857271 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_857272 policy<{'armhf': 'y'}> +CONFIG_ARM_EXYNOS_BUS_DEVFREQ policy<{'armhf': 'n'}> +CONFIG_ARM_EXYNOS_CPUIDLE policy<{'armhf': 'n'}> +CONFIG_ARM_FFA_SMCCC policy<{'arm64': 'y'}> +CONFIG_ARM_FFA_TRANSPORT policy<{'arm64': 'm'}> +CONFIG_ARM_GIC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_GIC_ITS_PARENT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_GIC_MAX_NR policy<{'arm64': '1', 'armhf': '1'}> +CONFIG_ARM_GIC_PM policy<{'arm64': 'y'}> +CONFIG_ARM_GIC_V2M policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_GIC_V3 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_GIC_V3_ITS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_GIC_V3_ITS_FSL_MC policy<{'arm64': 'y'}> +CONFIG_ARM_GIC_V5 policy<{'arm64': 'y'}> +CONFIG_ARM_GLOBAL_TIMER policy<{'armhf': 'y'}> +CONFIG_ARM_GT_INITIAL_PRESCALER_VAL policy<{'armhf': '1'}> +CONFIG_ARM_HAS_GROUP_RELOCS policy<{'armhf': 'y'}> +CONFIG_ARM_HEAVY_MB policy<{'armhf': 'y'}> +CONFIG_ARM_HIGHBANK_CPUFREQ policy<{'armhf': 'm'}> +CONFIG_ARM_HISI_UNCORE_DEVFREQ policy<{'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ARM_IMX6Q_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_IMX8M_DDRC_DEVFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_IMX_BUS_DEVFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_IMX_CPUFREQ_DT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_KPROBES_TEST policy<{'armhf': 'm'}> +CONFIG_ARM_L1_CACHE_SHIFT policy<{'armhf': '6'}> +CONFIG_ARM_L1_CACHE_SHIFT_6 policy<{'armhf': 'y'}> +CONFIG_ARM_LPAE policy<{'armhf': 'y'}> +CONFIG_ARM_MEDIATEK_CCI_DEVFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_MEDIATEK_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_MEDIATEK_CPUFREQ_HW policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_MHU policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_ARM_MHU_V2 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_ARM_MHU_V3 policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_ARM_MODULE_PLTS policy<{'armhf': 'y'}> +CONFIG_ARM_MVEBU_V7_CPUIDLE policy<{'armhf': 'y'}> +CONFIG_ARM_NI policy<{'arm64': 'n'}> +CONFIG_ARM_PAN policy<{'armhf': 'y'}> +CONFIG_ARM_PATCH_IDIV policy<{'armhf': 'y'}> +CONFIG_ARM_PATCH_PHYS_VIRT policy<{'armhf': 'y'}> +CONFIG_ARM_PKVM_GUEST policy<{'arm64': 'n'}> +CONFIG_ARM_PL172_MPMC policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_ARM_PMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_PMUV3 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_PMU_ACPI policy<{'arm64': 'y'}> +CONFIG_ARM_PSCI policy<{'armhf': 'y'}> +CONFIG_ARM_PSCI_CHECKER policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_ARM_PSCI_CPUIDLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_PSCI_FW policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_PTDUMP_CORE policy<{'armhf': 'y'}> +CONFIG_ARM_PTDUMP_DEBUGFS policy<{'armhf': 'n'}> +CONFIG_ARM_QCOM_CPUFREQ_HW policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_QCOM_CPUFREQ_NVMEM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_QCOM_SPM_CPUIDLE policy<{'armhf': 'y'}> +CONFIG_ARM_RK3399_DMC_DEVFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SBSA_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_ARM_SCMI_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_DEBUG_COUNTERS policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_ARM_SCMI_HAVE_MSG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_HAVE_SHMEM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_HAVE_TRANSPORT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_NEED_DEBUGFS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_PERF_DOMAIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_POWERCAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_POWER_CONTROL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_POWER_DOMAIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_PROTOCOL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_QUIRKS policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_RAW_MODE_SUPPORT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_RAW_MODE_SUPPORT_COEX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_MAILBOX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_OPTEE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_TRANSPORT_SMC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCPI_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCPI_POWER_DOMAIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCPI_PROTOCOL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SDE_INTERFACE policy<{'arm64': 'y'}> +CONFIG_ARM_SMCCC_SOC_ID policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SMC_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SMMU policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS policy<{'arm64': 'n', 'armhf': '-'}> +CONFIG_ARM_SMMU_MMU_500_CPRE_ERRATA policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_QCOM policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_QCOM_DEBUG policy<{'arm64': 'y', 'arm64-generic-64k': 'n'}> +CONFIG_ARM_SMMU_V3 policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_V3_IOMMUFD policy<{'arm64': 'n'}> +CONFIG_ARM_SMMU_V3_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_SMMU_V3_SVA policy<{'arm64': 'y'}> +CONFIG_ARM_SP805_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SPE_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_ARM_TEGRA124_CPUFREQ policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_TEGRA186_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_TEGRA194_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_TEGRA20_CPUFREQ policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_TEGRA_CPUIDLE policy<{'armhf': 'n'}> +CONFIG_ARM_TEGRA_DEVFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_THUMB policy<{'armhf': 'y'}> +CONFIG_ARM_THUMBEE policy<{'armhf': 'y'}> +CONFIG_ARM_TIMER_SP804 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_TI_CPUFREQ policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_TSTEE policy<{'arm64': 'm'}> +CONFIG_ARM_V7_PMU policy<{'armhf': 'y'}> +CONFIG_ARM_VEXPRESS_SPC_CPUFREQ policy<{'armhf': 'm'}> +CONFIG_ARM_VIC policy<{'armhf': 'y'}> +CONFIG_ARM_VIC_NR policy<{'armhf': '2'}> +CONFIG_ARM_VIRT_EXT policy<{'armhf': 'y'}> +CONFIG_AS21XXX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AS3935 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AS73211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ASM_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ASN1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ASN1_ENCODER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ASPEED_ADC policy<{'armhf': 'm'}> +CONFIG_ASPEED_BT_IPMI_BMC policy<{'armhf': 'm'}> +CONFIG_ASPEED_KCS_IPMI_BMC policy<{'armhf': 'm'}> +CONFIG_ASPEED_LPC_CTRL policy<{'armhf': 'm'}> +CONFIG_ASPEED_LPC_SNOOP policy<{'armhf': 'm'}> +CONFIG_ASPEED_P2A_CTRL policy<{'armhf': 'm'}> +CONFIG_ASPEED_SOCINFO policy<{'armhf': 'y'}> +CONFIG_ASPEED_UART_ROUTING policy<{'armhf': 'm'}> +CONFIG_ASPEED_WATCHDOG policy<{'armhf': 'y'}> +CONFIG_ASSOCIATIVE_ARRAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AST2600_I3C_MASTER policy<{'armhf': 'm'}> +CONFIG_AST2700_MBOX policy<{'armhf': 'm'}> +CONFIG_ASUS_ARMOURY policy<{'amd64': 'm'}> +CONFIG_ASUS_LAPTOP policy<{'amd64': 'm'}> +CONFIG_ASUS_NB_WMI policy<{'amd64': 'm'}> +CONFIG_ASUS_TF103C_DOCK policy<{'amd64': 'm'}> +CONFIG_ASUS_WIRELESS policy<{'amd64': 'm'}> +CONFIG_ASUS_WMI policy<{'amd64': 'm'}> +CONFIG_ASUS_WMI_DEPRECATED_ATTRS policy<{'amd64': 'y'}> +CONFIG_ASYNC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ASYNC_KERNEL_PGTABLE_FREE policy<{'amd64': 'y'}> +CONFIG_ASYNC_MEMCPY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ASYNC_PQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ASYNC_RAID6_RECOV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ASYNC_RAID6_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA policy<{'arm64': 'y'}> +CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA policy<{'arm64': 'y'}> +CONFIG_ASYNC_TX_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ASYNC_XOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AS_HAS_ARMV8_5 policy<{'arm64': 'y'}> +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE policy<{'arm64': 'y'}> +CONFIG_AS_HAS_INSN policy<{'riscv64': 'y'}> +CONFIG_AS_HAS_LSUI policy<{'arm64': 'y'}> +CONFIG_AS_HAS_MOPS policy<{'arm64': 'y'}> +CONFIG_AS_HAS_NON_CONST_ULEB128 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AS_HAS_OPTION_ARCH policy<{'riscv64': 'y'}> +CONFIG_AS_HAS_ULEB128 policy<{'riscv64': 'y'}> +CONFIG_AS_IS_GNU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AS_VERSION policy<{'amd64': '24600', 'arm64': '24600', 'armhf': '24600', 'ppc64el': '24600', 'riscv64': '24600', 's390x': '24600'}> +CONFIG_AS_WRUSS policy<{'amd64': 'y'}> +CONFIG_AT76C50X_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AT803X_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_ATAGS policy<{'armhf': 'y'}> +CONFIG_ATAGS_PROC policy<{'armhf': 'y'}> +CONFIG_ATALK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ATARI_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_ATA_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ATA_BMDMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATA_FORCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATA_GENERIC policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATA_OVER_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ATA_SFF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATA_VERBOSE_ERROR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH10K_AHB policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_CE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH10K_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH10K_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH10K_SNOC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ATH10K_SPECTRAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH11K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH11K_AHB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH11K_CFR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH11K_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH11K_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH11K_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH11K_SPECTRAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH11K_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH12K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_ATH12K_AHB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ATH12K_COREDUMP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_ATH12K_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_ATH12K_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ATH12K_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ATH5K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH5K_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH5K_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH5K_TRACER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH6KL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH6KL_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH6KL_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH6KL_TRACING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH6KL_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K_AHB policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_BTCOEX_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_CHANNEL_CONTEXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K_COMMON_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_COMMON_SPECTRAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_DYNACK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH9K_HTC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K_HTC_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_HW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K_HWRNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_PCI_NO_EEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K_PCOEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_RFKILL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_STATION_STATISTICS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_WOW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATL1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATL1C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATL1E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATL2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATLAS_EZO_SENSOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATLAS_PH_SENSOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ATM_BR2684 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_BR2684_IPFILTER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATM_SOLOS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATOMIC64_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AT_XDMAC policy<{'arm64': 'm'}> +CONFIG_AUDIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AUDITSYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AUDIT_ARCH policy<{'amd64': 'y', 'ppc64el': '-', 's390x': 'y'}> +CONFIG_AUDIT_ARCH_COMPAT_GENERIC policy<{'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_AUDIT_COMPAT_GENERIC policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_AUDIT_GENERIC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_AUTOFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'y'}> +CONFIG_AUTO_ZRELADDR policy<{'armhf': 'y'}> +CONFIG_AUXDISPLAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_AUXILIARY_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AW96103 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AX45MP_L2_CACHE policy<{'riscv64': 'n'}> +CONFIG_AX88796 policy<{'armhf': 'm'}> +CONFIG_AX88796B_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AX88796_93CX6 policy<{'armhf': 'n'}> +CONFIG_AXI_DMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AXP20X_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AXP20X_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AXP288_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AXP288_CHARGER policy<{'amd64': 'm'}> +CONFIG_AXP288_FUEL_GAUGE policy<{'amd64': 'm'}> +CONFIG_AYANEO_EC policy<{'amd64': 'm'}> +CONFIG_B43 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B43LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B43LEGACY_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43LEGACY_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_DMA_AND_PIO_MODE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_DMA_MODE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43LEGACY_HWRNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_PCICORE_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_PCI_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_PIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_PIO_MODE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43_BCMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_BCMA_PIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_BUSES_BCMA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43_BUSES_BCMA_AND_SSB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_BUSES_SSB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43_HWRNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PCICORE_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PCI_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PHY_G policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PHY_HT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PHY_LP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PHY_N policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_SDIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43_SSB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B44 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_B44_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B44_PCICORE_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B44_PCI_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B53 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B53_MDIO_DRIVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B53_MMAP_DRIVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B53_SERDES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B53_SPI_DRIVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B53_SRAB_DRIVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_AAT2870 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_ADP5520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_ADP8860 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_ADP8870 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_APPLE policy<{'amd64': 'm'}> +CONFIG_BACKLIGHT_APPLE_DWI policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_ARCXCNN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_AS3711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_AW99706 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_BD6107 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_CGBC policy<{'amd64': 'm'}> +CONFIG_BACKLIGHT_CLASS_DEVICE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BACKLIGHT_DA903X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_KTD253 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_KTD2801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_KTZ8866 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_LED policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_LM3509 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_LM3533 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_LM3630A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_LM3639 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_LP855X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_LP8788 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_LV5207LP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_MAX8925 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_MP3309C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_MT6370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_PANDORA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_QCOM_WLED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_RAVE_SP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_RT4831 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_SAHARA policy<{'amd64': 'm'}> +CONFIG_BACKLIGHT_SKY81452 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_TPS65217 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKTRACE_SELF_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BACKTRACE_VERBOSE policy<{'armhf': 'n'}> +CONFIG_BALLOON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BALLOON_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BARCO_P50_GPIO policy<{'amd64': 'm'}> +CONFIG_BAREUDP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BASE_SMALL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BASIC_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BATMAN_ADV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BATMAN_ADV_BATMAN_V policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BATMAN_ADV_BLA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BATMAN_ADV_DAT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BATMAN_ADV_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BATMAN_ADV_MCAST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BATMAN_ADV_TRACING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BATTERY_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_ACER_A500 policy<{'armhf': 'm'}> +CONFIG_BATTERY_ACT8945A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_AXP20X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_BQ27XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BATTERY_BQ27XXX_HDQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_BQ27XXX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_CHAGALL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_CW2015 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DA9030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DA9150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_DS2760 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DS2780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DS2781 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DS2782 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_GAUGE_LTC2941 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_GOLDFISH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_HUAWEI_GAOKUN policy<{'arm64': 'm'}> +CONFIG_BATTERY_INTEL_DC_TI policy<{'amd64': 'm'}> +CONFIG_BATTERY_LENOVO_YOGA_C630 policy<{'arm64-generic': 'm'}> +CONFIG_BATTERY_MAX17040 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_MAX17042 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_MAX1720X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_MAX1721X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_OLPC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_BATTERY_PM8916_BMS_VM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_BATTERY_QCOM_BATTMGR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_RT5033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_RX51 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_S2MU005 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_SAMSUNG_SDI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BATTERY_SBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_SURFACE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_BATTERY_TWL4030_MADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_UG3105 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BCACHE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCACHE_ASYNC_REGISTRATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BCACHE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BCM54140_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCM7XXX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCM84881_PHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BCM87XX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BCMA_BLOCKIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BCMA_DRIVER_GMAC_CMN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_DRIVER_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_DRIVER_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_HOST_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_HOST_PCI_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_HOST_SOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BCMA_SFLASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMGENET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BCM_KONA_USB2_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BCM_NET_PHYLIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCM_NET_PHYPTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCM_SBA_RAID policy<{'arm64': 'm'}> +CONFIG_BCM_VK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BCM_VK_TTY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BD79703 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BD957XMUF_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BD96801_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BE2ISCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BE2NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BE2NET_BE2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BE2NET_BE3 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BE2NET_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BE2NET_LANCER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BE2NET_SKYHAWK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BEFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BEFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BERLIN2_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_BFQ_CGROUP_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BFQ_GROUP_IOSCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BH1745 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BH1750 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BH1780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BHYVE_GUEST policy<{'amd64': 'y'}> +CONFIG_BIG_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BIG_LITTLE policy<{'armhf': 'y'}> +CONFIG_BINARY_PRINTF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BINFMT_ELF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BINFMT_ELF_FDPIC policy<{'armhf': 'y'}> +CONFIG_BINFMT_FLAT policy<{'armhf': 'y', 'riscv64': 'n'}> +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK policy<{'armhf': 'y'}> +CONFIG_BINFMT_FLAT_OLD policy<{'armhf': 'y'}> +CONFIG_BINFMT_MISC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BINFMT_ZFLAT policy<{'armhf': 'y'}> +CONFIG_BITLAND_MIFS_WMI policy<{'amd64': 'm'}> +CONFIG_BITREVERSE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLKDEV_UBLK_LEGACY_OPCODES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_BLK_CGROUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_CGROUP_FC_APPID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_CGROUP_IOCOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_CGROUP_IOLATENCY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BLK_CGROUP_IOPRIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_CGROUP_PUNT_BIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_CGROUP_RWSTAT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEBUG_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_3W_XXXX_RAID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BLK_DEV_BSG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_BSGLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_BSG_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_DM_BUILTIN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_DRBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_FD policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_BLK_DEV_FD_RAWCMD policy<{'amd64': 'n', 'ppc64el': 'n'}> +CONFIG_BLK_DEV_INITRD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_INTEGRITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_IO_TRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_LOOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_LOOP_MIN_COUNT policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8', 's390x': '8'}> +CONFIG_BLK_DEV_MD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_NBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_NULL_BLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_PCIESSD_MTIP32XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BLK_DEV_PMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BLK_DEV_RAM_COUNT policy<{'amd64': '16', 'arm64': '16', 'armhf': '16', 'ppc64el': '16', 'riscv64': '16', 's390x': '16'}> +CONFIG_BLK_DEV_RBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_RNBD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_RNBD_CLIENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_RNBD_SERVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_UBLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BLK_DEV_WRITE_MOUNTED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_ZONED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_ZONED_LOOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_ICQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_INLINE_ENCRYPTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_MQ_STACKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_PM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BLK_RQ_ALLOC_TIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_SED_OPAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_WBT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_WBT_MQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLOCK_HOLDER_DEPRECATED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLOCK_LEGACY_AUTOLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BL_SWITCHER policy<{'armhf': 'y'}> +CONFIG_BL_SWITCHER_DUMMY_IF policy<{'armhf': 'm'}> +CONFIG_BMA220 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMA220_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMA220_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMA400 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMA400_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMA400_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_ACCEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_ACCEL_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_ACCEL_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_MAGN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_MAGN_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_MAGN_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BME680 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BME680_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BME680_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMG160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMG160_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMG160_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI088_ACCEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI088_ACCEL_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI088_ACCEL_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI160_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI160_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI270 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI270_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI270_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI323_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI323_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMP280 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMP280_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMP280_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BNA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BNGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BNX2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BNX2X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BNX2X_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BNXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BNXT_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BNXT_FLOWER_OFFLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BNXT_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BNXT_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BOARD_TPCI200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BONDING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_BOOTPARAM_HUNG_TASK_PANIC policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_BOOTTIME_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BOOTX_TEXT policy<{'ppc64el': 'n'}> +CONFIG_BOOT_CONFIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BOOT_CONFIG_EMBED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BOOT_CONFIG_FORCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BOOT_PRINTK_DELAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_BOOT_VESA_SUPPORT policy<{'amd64': 'y'}> +CONFIG_BOSCH_BNO055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BOSCH_BNO055_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BOSCH_BNO055_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_JIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_JIT_ALWAYS_ON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_JIT_DEFAULT_ON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_KPROBE_OVERRIDE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_LSM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_PRELOAD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BPF_STREAM_PARSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_SYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BQL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BRANCH_PROFILE_NONE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BRCMDBG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_BRCMFMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BRCMFMAC_PCIE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMFMAC_PROTO_BCDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMFMAC_PROTO_MSGBUF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMFMAC_SDIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMFMAC_USB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMSMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BRCMSMAC_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMUTIL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BRCM_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_CFM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BRIDGE_EBT_802_3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_AMONG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_ARP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_ARPREPLY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_BROUTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_DNAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_IP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_IP6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_LIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_LOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_MARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_MARK_T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_NFLOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_PKTTYPE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_REDIRECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_SNAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_STP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_T_FILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_T_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_VLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_IGMP_SNOOPING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BRIDGE_MRP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BRIDGE_NETFILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_NF_EBTABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_NF_EBTABLES_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_VLAN_FILTERING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BROADCAST_TLB_FLUSH policy<{'amd64': 'y'}> +CONFIG_BROADCOM_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BSD_DISKLABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_BSD_PROCESS_ACCT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BSD_PROCESS_ACCT_V3 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BTREE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BTRFS_ASSERT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BTRFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BTRFS_EXPERIMENTAL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BTRFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BTRFS_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BTRFS_FS_RUN_SANITY_TESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BTT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_6LOWPAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_AOSPEXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_ATH3K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_BCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_BNEP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_BNEP_MC_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_BNEP_PROTO_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_BREDR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIBCM203X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBCM4377 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBFUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBLUECARD policy<{'amd64': 'm'}> +CONFIG_BT_HCIBPA10X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBT3C policy<{'amd64': 'm'}> +CONFIG_BT_HCIBTSDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBTUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBTUSB_AUTOSUSPEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIBTUSB_BCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIBTUSB_MTK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIBTUSB_POLL_SYNC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIBTUSB_RTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIDTL1 policy<{'amd64': 'm'}> +CONFIG_BT_HCIRSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIUART_3WIRE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_AG6XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_AML policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_ATH3K policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_BCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_BCSP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_H4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_INTEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_LL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_MRVL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_NOKIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIUART_QCA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_RTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_SERDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIVHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HIDP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_INTEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_INTEL_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_LE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_LE_L2CAP_ECRED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_MRVL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_MRVL_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_MSFTEXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_MTK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_MTKSDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_MTKUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_NXPUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_QCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_QCOMSMD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_BT_RFCOMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_RFCOMM_TTY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_RTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_BT_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BUFFER_HEAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BUG_ON_DATA_CORRUPTION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BUILDTIME_MCOUNT_SORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 's390x': 'y'}> +CONFIG_BUILDTIME_TABLE_SORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BUILD_SALT policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_BUILTIN_MODULE_RANGES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC policy<{'arm64': 'y'}> +CONFIG_BXT_WC_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_BYTCRC_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_C2PORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_C2PORT_DURAMAR_2150 policy<{'amd64': 'm'}> +CONFIG_CACHEFILES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CACHEFILES_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CACHEFILES_ERROR_INJECTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CACHEFILES_ONDEMAND policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CACHEMAINT_FOR_DMA policy<{'riscv64': 'y'}> +CONFIG_CACHEMAINT_FOR_HOTPLUG policy<{'arm64': 'y'}> +CONFIG_CACHESTAT_SYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CACHE_FEROCEON_L2 policy<{'armhf': 'y'}> +CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH policy<{'armhf': 'n'}> +CONFIG_CACHE_L2X0 policy<{'armhf': 'y'}> +CONFIG_CACHE_L2X0_PMU policy<{'armhf': 'y'}> +CONFIG_CACHE_TAUROS2 policy<{'armhf': 'y'}> +CONFIG_CADENCE_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CALL_PADDING policy<{'amd64': 'y'}> +CONFIG_CALL_THUNKS policy<{'amd64': 'y'}> +CONFIG_CALL_THUNKS_DEBUG policy<{'amd64': 'n'}> +CONFIG_CAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CAN_8DEV_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_BCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_BXCAN policy<{'arm64': 'm'}> +CONFIG_CAN_CALC_BITTIMING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CAN_CAN327 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CC770 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CC770_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CC770_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CTUCANFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CTUCANFD_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CTUCANFD_PLATFORM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_C_CAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_C_CAN_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_C_CAN_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_DEBUG_DEVICES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CAN_DEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_EMS_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_EMS_PCMCIA policy<{'amd64': 'm'}> +CONFIG_CAN_EMS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_ESD_402_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_ESD_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_ETAS_ES58X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_F81601 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_F81604 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_FLEXCAN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_GRCAN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_GS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_GW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_HI311X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_IFI_CANFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_ISOTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_J1939 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_JANZ_ICAN3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_KVASER_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_KVASER_PCIEFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_KVASER_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_MCBA_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_MCP251X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_MCP251XFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_MCP251XFD_SANITY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CAN_MSCAN policy<{'ppc64el': 'm'}> +CONFIG_CAN_M_CAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_M_CAN_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_M_CAN_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_M_CAN_TCAN4X5X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_NETLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CAN_PEAK_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_PEAK_PCIEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CAN_PEAK_PCIEFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_PEAK_PCMCIA policy<{'amd64': 'm'}> +CONFIG_CAN_PEAK_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_PLX_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CAN_RCAR_CANFD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CAN_ROCKCHIP_CANFD policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_CAN_RX_OFFLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CAN_SJA1000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_SJA1000_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_SJA1000_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_SLCAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_SOFTING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_SOFTING_CS policy<{'amd64': 'm'}> +CONFIG_CAN_TI_HECC policy<{'armhf': 'm'}> +CONFIG_CAN_UCAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_VCAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_VXCAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_XILINXCAN policy<{'arm64': 'm'}> +CONFIG_CARDBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_CARL9170 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CARL9170_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CARL9170_HWRNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CARL9170_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CARL9170_WPC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CARMINE_DRAM_CUSTOM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CASSINI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CAVIUM_CPT policy<{'arm64': 'm'}> +CONFIG_CAVIUM_ERRATUM_22375 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_23144 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_23154 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_27456 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_30115 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_PTP policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CAVIUM_TX2_ERRATUM_219 policy<{'arm64': 'y'}> +CONFIG_CB710_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CB710_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CB710_DEBUG_ASSUMPTIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CC10001_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CCS811 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CCW policy<{'s390x': 'y'}> +CONFIG_CCWGROUP policy<{'s390x': 'm'}> +CONFIG_CCW_CONSOLE policy<{'s390x': 'y'}> +CONFIG_CC_CAN_LINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ASM_AOR_FORMAT_FLAGS policy<{'s390x': 'y'}> +CONFIG_CC_HAS_ASM_GOTO_OUTPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ASM_IMMEDIATE_STRINGS policy<{'s390x': 'y'}> +CONFIG_CC_HAS_ASM_INLINE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ASSUME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET policy<{'arm64': 'y'}> +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI policy<{'arm64': 'y'}> +CONFIG_CC_HAS_COUNTED_BY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ELFV2 policy<{'ppc64el': 'y'}> +CONFIG_CC_HAS_ENTRY_PADDING policy<{'amd64': 'y'}> +CONFIG_CC_HAS_IBT policy<{'amd64': 'y'}> +CONFIG_CC_HAS_INT128 policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_KASAN_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_KASAN_SW_TAGS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_NAMED_AS policy<{'amd64': 'y'}> +CONFIG_CC_HAS_NAMED_AS_FIXED_SANITIZERS policy<{'amd64': 'y'}> +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_PCREL policy<{'ppc64el': 'y'}> +CONFIG_CC_HAS_PREFIXED policy<{'ppc64el': 'y'}> +CONFIG_CC_HAS_RETURN_THUNK policy<{'amd64': 'y'}> +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_SLS policy<{'amd64': 'y'}> +CONFIG_CC_HAS_UBSAN_BOUNDS_STRICT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ZERO_CALL_USED_REGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAVE_SHADOW_CALL_STACK policy<{'arm64': 'y'}> +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG policy<{'arm64': 'y'}> +CONFIG_CC_HAVE_STACKPROTECTOR_TLS policy<{'armhf': 'y', 'riscv64': 'y'}> +CONFIG_CC_IMPLICIT_FALLTHROUGH policy<{'amd64': '"-Wimplicit-fallthrough=5"', 'arm64': '"-Wimplicit-fallthrough=5"', 'armhf': '"-Wimplicit-fallthrough=5"', 'ppc64el': '"-Wimplicit-fallthrough=5"', 'riscv64': '"-Wimplicit-fallthrough=5"', 's390x': '"-Wimplicit-fallthrough=5"'}> +CONFIG_CC_IS_GCC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_MS_EXTENSIONS policy<{'amd64': '"-fms-extensions"', 'arm64': '"-fms-extensions"', 'armhf': '"-fms-extensions"', 'ppc64el': '"-fms-extensions"', 'riscv64': '"-fms-extensions"', 's390x': '"-fms-extensions"'}> +CONFIG_CC_NO_ARRAY_BOUNDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_NO_STRINGOP_OVERFLOW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_OPTIMIZE_FOR_SIZE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CC_VERSION_TEXT policy<{'amd64': '"x86_64-linux-gnu-gcc-15 (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 'arm64': '"aarch64-linux-gnu-gcc-15 (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 'armhf': '"arm-linux-gnueabihf-gcc-15 (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 'ppc64el': '"powerpc64le-linux-gnu-gcc-15 (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 'riscv64': '"riscv64-linux-gnu-gcc-15 (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 's390x': '"s390x-linux-gnu-gcc-15 (Ubuntu 15.2.0-16ubuntu1) 15.2.0"'}> +CONFIG_CDNS_I3C_MASTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CDROM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CDX_BUS policy<{'arm64': 'y'}> +CONFIG_CDX_CONTROLLER policy<{'arm64': 'm'}> +CONFIG_CEC_CH7322 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CEC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CEC_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CEC_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CEC_MESON_AO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CEC_MESON_G12A_AO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CEC_NOTIFIER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CEC_NXP_TDA9950 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CEC_PIN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CEC_PIN_ERROR_INJ policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CEC_SAMSUNG_S5P policy<{'armhf': 'n'}> +CONFIG_CEC_SECO policy<{'amd64': 'm'}> +CONFIG_CEC_SECO_RC policy<{'amd64': 'y'}> +CONFIG_CEC_STM32 policy<{'arm64': 'm'}> +CONFIG_CEC_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CEPH_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CEPH_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CEPH_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CEPH_FS_SECURITY_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CEPH_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CEPH_LIB_PRETTYDEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CEPH_LIB_USE_DNS_RESOLVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CERT_STORE policy<{'s390x': 'y'}> +CONFIG_CFAG12864B policy<{'amd64': 'm'}> +CONFIG_CFAG12864B_RATE policy<{'amd64': '20'}> +CONFIG_CFG80211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CFG80211_CERTIFICATION_ONUS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CFG80211_CRDA_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFG80211_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFG80211_DEFAULT_PS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFG80211_DEVELOPER_WARNINGS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFG80211_WEXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFS_BANDWIDTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGBC_WDT policy<{'amd64': 'm'}> +CONFIG_CGROUPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_CPUACCT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CGROUP_DEVICE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_DMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_FAVOR_DYNMODS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CGROUP_FREEZER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_HUGETLB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_MISC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_NET_CLASSID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_NET_PRIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_PERF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_PIDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_RDMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_SCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_WRITEBACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CHARGER_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_ADP5061 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_AXP20X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_BD71828 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_BD99954 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ2415X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ24190 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ24257 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ24735 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ2515X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ256XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ257XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_BQ25890 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ25980 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_CPCAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_CROS_CONTROL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_CHARGER_CROS_PCHG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_CROS_USBPD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_DA9150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_DETECTOR_MAX14656 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_ISP1704 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_LP8727 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_LP8788 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_LT3651 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_LTC4162L policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_MANAGER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHARGER_MAX14577 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_MAX77650 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX77693 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_MAX77705 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX77759 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX77976 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX8903 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_MAX8971 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX8997 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX8998 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MP2629 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MT6360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MT6370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_PF1550 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_PM8916_LBC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_QCOM_SMB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_QCOM_SMBB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_RK817 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_RT5033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_RT9455 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_RT9467 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_CHARGER_RT9471 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_RT9756 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_SBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_SC2731 policy<{'arm64': 'm'}> +CONFIG_CHARGER_SMB347 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_SURFACE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CHARGER_TPS65090 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_TPS65217 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_CHARGER_TWL4030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_TWL6030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_UCS1002 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_WILCO policy<{'amd64': 'm'}> +CONFIG_CHARLCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARLCD_BL_FLASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHARLCD_BL_OFF policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CHARLCD_BL_ON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CHECKPOINT_RESTORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CHECK_SIGNATURE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHELSIO_INLINE_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHELSIO_IPSEC_INLINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHELSIO_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHELSIO_T1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHELSIO_T1_1G policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHELSIO_T3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHELSIO_T4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHELSIO_T4VF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHELSIO_T4_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHELSIO_T4_FCOE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHELSIO_TLS_DEVICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHROMEOS_ACPI policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CHROMEOS_LAPTOP policy<{'amd64': 'm'}> +CONFIG_CHROMEOS_OF_HW_PROBER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHROMEOS_PRIVACY_SCREEN policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CHROMEOS_PSTORE policy<{'amd64': 'm'}> +CONFIG_CHROMEOS_TBMC policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CHROME_PLATFORMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_CHR_DEV_SCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CHR_DEV_ST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CHSC_SCH policy<{'s390x': 'm'}> +CONFIG_CHTCRC_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_CHT_DC_TI_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_CHT_WC_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_CICADA_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CIFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CIFS_ALLOW_INSECURE_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_COMPRESSION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CIFS_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_DEBUG2 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CIFS_DEBUG_DUMP_KEYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CIFS_DFS_UPCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_POSIX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_SMB_DIRECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CIFS_STATS2 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CIFS_SWN_UPCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_UPCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIO_DAC policy<{'amd64': 'm'}> +CONFIG_CIO_INJECT policy<{'s390x': 'n'}> +CONFIG_CIX_MBOX policy<{'arm64': 'm'}> +CONFIG_CLANG_VERSION policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_CLKBLD_I8253 policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_CLKEVT_I8253 policy<{'amd64': 'y'}> +CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK policy<{'armhf': 'y'}> +CONFIG_CLKSRC_EXYNOS_MCT policy<{'armhf': 'y'}> +CONFIG_CLKSRC_IMX_GPT policy<{'armhf': 'y'}> +CONFIG_CLKSRC_IMX_TPM policy<{'armhf': 'y'}> +CONFIG_CLKSRC_MMIO policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_CLKSRC_QCOM policy<{'armhf': 'y'}> +CONFIG_CLKSRC_STM32_LP policy<{'arm64': 'y'}> +CONFIG_CLKSRC_TI_32K policy<{'armhf': 'y'}> +CONFIG_CLKSRC_VERSATILE policy<{'armhf': 'y'}> +CONFIG_CLK_ACTIONS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_ELIZA_DISPCC policy<{'arm64': 'm'}> +CONFIG_CLK_ELIZA_GCC policy<{'arm64': 'm'}> +CONFIG_CLK_ELIZA_TCSRCC policy<{'arm64': 'm'}> +CONFIG_CLK_EMEV2 policy<{'armhf': 'y'}> +CONFIG_CLK_GFM_LPASS_SM8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_CLK_GLYMUR_DISPCC policy<{'arm64': 'm'}> +CONFIG_CLK_GLYMUR_GCC policy<{'arm64': 'm'}> +CONFIG_CLK_GLYMUR_GPUCC policy<{'arm64': 'm'}> +CONFIG_CLK_GLYMUR_TCSRCC policy<{'arm64': 'm'}> +CONFIG_CLK_GLYMUR_VIDEOCC policy<{'arm64': 'm'}> +CONFIG_CLK_ICST policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_IMX5 policy<{'armhf': 'y'}> +CONFIG_CLK_IMX6Q policy<{'armhf': 'y'}> +CONFIG_CLK_IMX6SL policy<{'armhf': 'y'}> +CONFIG_CLK_IMX6SLL policy<{'armhf': 'y'}> +CONFIG_CLK_IMX6SX policy<{'armhf': 'y'}> +CONFIG_CLK_IMX6UL policy<{'armhf': 'y'}> +CONFIG_CLK_IMX7D policy<{'armhf': 'y'}> +CONFIG_CLK_IMX7ULP policy<{'armhf': 'y'}> +CONFIG_CLK_IMX8MM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_IMX8MN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_IMX8MP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_IMX8MQ policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_IMX8QXP policy<{'arm64': 'y'}> +CONFIG_CLK_IMX8ULP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CLK_IMX93 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CLK_IMX95_BLK_CTL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CLK_INTEL_SOCFPGA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_INTEL_SOCFPGA32 policy<{'armhf': 'y'}> +CONFIG_CLK_INTEL_SOCFPGA64 policy<{'arm64': 'y'}> +CONFIG_CLK_KAANAPALI_CAMCC policy<{'arm64': 'm'}> +CONFIG_CLK_KAANAPALI_DISPCC policy<{'arm64': 'm'}> +CONFIG_CLK_KAANAPALI_GCC policy<{'arm64': 'm'}> +CONFIG_CLK_KAANAPALI_GPUCC policy<{'arm64': 'm'}> +CONFIG_CLK_KAANAPALI_TCSRCC policy<{'arm64': 'm'}> +CONFIG_CLK_KAANAPALI_VIDEOCC policy<{'arm64': 'm'}> +CONFIG_CLK_LS1028A_PLLDIG policy<{'arm64': 'm'}> +CONFIG_CLK_MA35D1 policy<{'arm64': 'y'}> +CONFIG_CLK_NORD_GCC policy<{'arm64': 'm'}> +CONFIG_CLK_NORD_TCSRCC policy<{'arm64': 'm'}> +CONFIG_CLK_OWL_S500 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_OWL_S700 policy<{'arm64': 'y'}> +CONFIG_CLK_OWL_S900 policy<{'arm64': 'y'}> +CONFIG_CLK_PX30 policy<{'arm64': 'y'}> +CONFIG_CLK_QCM2290_GPUCC policy<{'arm64-generic': 'm', 'arm64-generic-64k': 'n'}> +CONFIG_CLK_QORIQ policy<{'arm64': 'y'}> +CONFIG_CLK_R7S9210 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7740 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7742 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7743 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7745 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A77470 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A7778 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7779 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7790 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7791 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7792 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7794 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7795 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77960 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77961 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77965 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77970 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77980 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77990 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77995 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A06G032 policy<{'armhf': 'y'}> +CONFIG_CLK_R9A07G043 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A07G044 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A07G054 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A08G045 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A08G046 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G011 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G047 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G056 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G057 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G077 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G087 policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_CPG_LIB policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_GEN2_CPG policy<{'armhf': 'y'}> +CONFIG_CLK_RCAR_GEN3_CPG policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_GEN4_CPG policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_USB2_CLOCK_SEL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_RENESAS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_RENESAS_CPG_MSSR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_RENESAS_CPG_MSTP policy<{'armhf': 'y'}> +CONFIG_CLK_RENESAS_DIV6 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_RENESAS_VBATTB policy<{'arm64': 'm'}> +CONFIG_CLK_RK3036 policy<{'armhf': 'y'}> +CONFIG_CLK_RK312X policy<{'armhf': 'y'}> +CONFIG_CLK_RK3188 policy<{'armhf': 'y'}> +CONFIG_CLK_RK322X policy<{'armhf': 'y'}> +CONFIG_CLK_RK3288 policy<{'armhf': 'y'}> +CONFIG_CLK_RK3308 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3328 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3368 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3399 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3506 policy<{'armhf': 'y'}> +CONFIG_CLK_RK3528 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3562 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3568 policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_CLK_RK3576 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3588 policy<{'arm64': 'y'}> +CONFIG_CLK_RV1103B policy<{'armhf': 'y'}> +CONFIG_CLK_RV110X policy<{'armhf': 'y'}> +CONFIG_CLK_RV1126 policy<{'armhf': 'y'}> +CONFIG_CLK_RV1126B policy<{'arm64': 'y'}> +CONFIG_CLK_RZA1 policy<{'armhf': 'y'}> +CONFIG_CLK_RZG2L policy<{'arm64': 'y'}> +CONFIG_CLK_RZV2H policy<{'arm64': 'y'}> +CONFIG_CLK_SH73A0 policy<{'armhf': 'y'}> +CONFIG_CLK_SOPHGO_CV1800 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SOPHGO_SG2042_CLKGEN policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SOPHGO_SG2042_PLL policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SOPHGO_SG2042_RPGATE policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SOPHGO_SG2044 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SOPHGO_SG2044_PLL policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SP810 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_CLK_TEGRA_BPMP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_TWL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CLK_TWL6040 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CLK_VEXPRESS_OSC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_VF610 policy<{'armhf': 'y'}> +CONFIG_CLK_X1E80100_CAMCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1E80100_DISPCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1E80100_GCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1E80100_GPUCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1E80100_TCSRCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1P42100_GPUCC policy<{'arm64': 'm'}> +CONFIG_CLOCKSOURCE_WATCHDOG policy<{'amd64': 'y'}> +CONFIG_CLONE_BACKWARDS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CLONE_BACKWARDS2 policy<{'s390x': 'y'}> +CONFIG_CLOSURES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CLS_U32_MARK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CLS_U32_PERF policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CLZ_TAB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CM32181 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CM3232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CM3323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CM3605 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CM36651 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CMA_ALIGNMENT policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'riscv64': '8'}> +CONFIG_CMA_AREAS policy<{'amd64': '20', 'arm64': '7', 'armhf': '7', 'ppc64el': '7', 'riscv64': '7', 's390x': '7'}> +CONFIG_CMA_DEBUGFS policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CMA_SIZE_SEL_MAX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CMA_SIZE_SEL_MBYTES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_CMA_SIZE_SEL_MIN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CMA_SIZE_SEL_PERCENTAGE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CMA_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CMDLINE policy<{'arm64': '"console=ttyAMA0"', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""'}> +CONFIG_CMDLINE_BOOL policy<{'amd64': 'n'}> +CONFIG_CMDLINE_FORCE policy<{'arm64': 'n', 'armhf': '-'}> +CONFIG_CMDLINE_FROM_BOOTLOADER policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_CMDLINE_LOG_WRAP_IDEAL_LEN policy<{'amd64': '1021', 'arm64': '1021', 'armhf': '1021', 'ppc64el': '1021', 'riscv64': '1021', 's390x': '1021'}> +CONFIG_CMDLINE_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_CMM policy<{'ppc64el': 'm', 's390x': 'y'}> +CONFIG_CMM_IUCV policy<{'s390x': 'y'}> +CONFIG_CMODEL_MEDANY policy<{'riscv64': 'y'}> +CONFIG_CMODEL_MEDLOW policy<{'riscv64': 'n'}> +CONFIG_CNIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CODA_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CODE_PATCHING_SELFTEST policy<{'ppc64el': 'n'}> +CONFIG_COMEDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_COMEDI_8254 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_8255 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_8255_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_8255_SA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1032 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1516 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1564 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_16XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_2032 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_2200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_3120 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_3501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_3XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI6208 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI7250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI7X3X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI8164 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI9111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI9118 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADQ12B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI1710 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI1720 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI1723 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI1724 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI1760 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI_DIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AIO_AIO12_8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AIO_IIRO_16 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_DIO200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_DIO200_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_DIO200_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PC236 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PC236_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PC236_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PC263_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PC263_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PCI224 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PCI230 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_BOND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_C6XDIGIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CB_DAS16_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_CB_PCIDAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CB_PCIDAS64 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CB_PCIDDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CB_PCIMDAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CB_PCIMDDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CONTEC_PCI_DIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAC02 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAQBOARD2000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS08 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS08_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_DAS08_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS08_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS16 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS16M1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS1800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS6402 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB policy<{'amd64': '20480', 'arm64': '20480', 'armhf': '20480', 'ppc64el': '20480', 'riscv64': '20480'}> +CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB policy<{'amd64': '2048', 'arm64': '2048', 'armhf': '2048', 'ppc64el': '2048', 'riscv64': '2048'}> +CONFIG_COMEDI_DMM32AT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT2801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT2811 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT2814 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT2815 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT2817 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT282X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT9812 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DYNA_PCI10XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_FL512 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_GSC_HPDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ICP_MULTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_II_PCI20KC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ISADMA policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_COMEDI_ISA_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_COMEDI_JR3_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_KCOMEDILIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_KE_COUNTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ME4000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ME_DAQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_MF6X4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_MISC_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_COMEDI_MITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_MPC624 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_MULTIQ3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_6527 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_65XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_660X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_670X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_ATMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_ATMIO16D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_AT_A2150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_AT_AO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_DAQ_700_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_NI_DAQ_DIO24_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_NI_LABPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_LABPC_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_NI_LABPC_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_LABPC_ISADMA policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_COMEDI_NI_LABPC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_MIO_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_NI_PCIDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_PCIMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_ROUTING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_TIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_TIOCMD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_USB6501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PARPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCI_DRIVERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL724 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL726 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL730 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL812 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL816 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL818 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCM3724 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCMAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCMCIA_DRIVERS policy<{'amd64': 'm'}> +CONFIG_COMEDI_PCMDA12 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCMMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCMUIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_QUATECH_DAQP_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_RTD520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_RTI800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_RTI802 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_S526 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_S626 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_TESTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_TESTS_EXAMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_TESTS_NI_ROUTES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_USBDUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_USBDUXFAST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_USBDUXSIGMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_USB_DRIVERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_VMK80XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMAND_LINE_SIZE policy<{'s390x': '4096'}> +CONFIG_COMMON_CLK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_COMMON_CLK_A1_PERIPHERALS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_A1_PLL policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_APPLE_NCO policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_ASPEED policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_AST2700 policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_AXG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_AXG_AUDIO policy<{'arm64': 'm', 'armhf': 'n'}> +CONFIG_COMMON_CLK_AXI_CLKGEN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_BD718XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_BM1880 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_C3_PERIPHERALS policy<{'arm64-generic': 'm', 'arm64-generic-64k': 'y'}> +CONFIG_COMMON_CLK_C3_PLL policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_CDCE706 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_CDCE925 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_CS2000_CP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_EN7523 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_FIXED_MMIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_COMMON_CLK_FSL_FLEXSPI policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_FSL_SAI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_G12A policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_GXBB policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_HI3516CV300 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_HI3519 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_HI3559A policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_HI3660 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_HI3670 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_HI3798CV200 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_HI6220 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_HI655X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_LAN966X policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_LOCHNAGAR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_MAX77686 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_MAX9485 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_MEDIATEK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MEDIATEK_FHCTL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON8B policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON_AO_CLKC policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_CLKC_UTILS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON_CPU_DYNDIV policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_DUALDIV policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_MPLL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON_PHASE policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MESON_PLL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON_REGMAP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON_SCLK_DIV policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MESON_VCLK policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_VID_PLL_DIV policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MMP2 policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MMP2_AUDIO policy<{'armhf': 'm'}> +CONFIG_COMMON_CLK_MT2701 policy<{'armhf': 'n'}> +CONFIG_COMMON_CLK_MT2712 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_BDPSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_JPGDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6735 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6735_IMGSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6735_MFGCFG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6735_VDECSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6735_VENCSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6765 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_AUDIOSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_GCESYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MFGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI0ASYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI0BSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI1ASYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI1BSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI2ASYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI2BSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_VCODECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_IPESYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6795 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6795_MFGCFG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6795_MMSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6795_VDECSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6795_VENCSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6797 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT7622 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7622_AUDSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7622_ETHSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7622_HIFSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7629 policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7629_ETHSYS policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7629_HIFSYS policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7981 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7981_ETHSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT7986 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7986_ETHSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7988 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8135 policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MT8167 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8173 policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_COMMON_CLK_MT8173_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8173_MMSYS policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_COMMON_CLK_MT8173_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8173_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8183 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_AUDIOSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_ADL policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_CONN policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_CORE0 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_CORE1 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8186 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8186_CAMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_IPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MCUSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MDPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_WPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_ADSP_AUDIO26M policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_CAMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_IPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VDOSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VPPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_WPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8192 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_IPESYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MDPSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MSDC policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_SCP_ADSP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8195 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8195_APUSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_CAMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_IPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_SCP_ADSP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VDOSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VPPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_WPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_MCUSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_MDPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_MMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_PEXTPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_UFSSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8365 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_APU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_CAM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_MFG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_MMSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_VDEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_VENC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8516 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT8516_AUDSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_NPCM8XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_NUVOTON policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_PALMAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_PXA1908 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_QCOM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_RK808 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_RP1 policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_COMMON_CLK_RPMI policy<{'riscv64': 'm'}> +CONFIG_COMMON_CLK_RS9_PCIE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_S2MPS11 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_S4_PERIPHERALS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_S4_PLL policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_SAMSUNG policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_SCMI policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_COMMON_CLK_SCPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_SI514 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_SI521XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_SI5341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_SI5351 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_SI544 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_SI570 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_SP7021 policy<{'armhf': 'm'}> +CONFIG_COMMON_CLK_STM32MP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_STM32MP215 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_STM32MP257 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_T7_PERIPHERALS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_T7_PLL policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_TI_ADPLL policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_TPS68470 policy<{'amd64': 'm'}> +CONFIG_COMMON_CLK_VC3 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_VC5 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_VC7 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_VISCONTI policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_XGENE policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_XLNX_CLKWZRD policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'n'}> +CONFIG_COMMON_CLK_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_COMMON_RESET_HI3660 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_RESET_HI6220 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMPACTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_COMPACT_UNEVICTABLE_DEFAULT policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1', 's390x': '1'}> +CONFIG_COMPAL_LAPTOP policy<{'amd64': 'm'}> +CONFIG_COMPAT policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_COMPAT_32 policy<{'amd64': 'y'}> +CONFIG_COMPAT_32BIT_TIME policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_COMPAT_ALIGNMENT_FIXUPS policy<{'arm64': 'n', 'arm64-generic-64k': '-'}> +CONFIG_COMPAT_BINFMT_ELF policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 's390x': '-'}> +CONFIG_COMPAT_FOR_U64_ALIGNMENT policy<{'amd64': 'y'}> +CONFIG_COMPAT_NETLINK_MESSAGES policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-'}> +CONFIG_COMPAT_OLD_SIGACTION policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 's390x': '-'}> +CONFIG_COMPAT_VDSO policy<{'amd64': 'n'}> +CONFIG_COMPILE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_COMPRESSED_INSTALL policy<{'arm64': 'n'}> +CONFIG_CONFIGFS_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONNECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONSOLE_LOGLEVEL_DEFAULT policy<{'amd64': '7', 'arm64': '7', 'armhf': '7', 'ppc64el': '7', 'riscv64': '7', 's390x': '7'}> +CONFIG_CONSOLE_POLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CONSOLE_TRANSLATIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONTEXT_ANALYSIS_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CONTEXT_SWITCH_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONTEXT_TRACKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONTEXT_TRACKING_IDLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONTEXT_TRACKING_USER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CONTEXT_TRACKING_USER_FORCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CONTIG_ALLOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CORDIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_COREDUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CORESIGHT policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CORTINA_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_COUNTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CPA_DEBUG policy<{'amd64': 'n'}> +CONFIG_CPCAP_ADC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CPM_TSA policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n'}> +CONFIG_CPUFREQ_ARCH_CUR_FREQ policy<{'amd64': 'y'}> +CONFIG_CPUFREQ_DT_PLATDEV policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPUFREQ_VIRT policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_CPUMASK_OFFSTACK policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CPUSETS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CPUSETS_V1 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CPU_32v6K policy<{'armhf': 'y'}> +CONFIG_CPU_32v7 policy<{'armhf': 'y'}> +CONFIG_CPU_ABRT_EV7 policy<{'armhf': 'y'}> +CONFIG_CPU_BIG_ENDIAN policy<{'arm64': '-', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'y'}> +CONFIG_CPU_BPREDICT_DISABLE policy<{'armhf': 'n'}> +CONFIG_CPU_CACHE_V7 policy<{'armhf': 'y'}> +CONFIG_CPU_CACHE_VIPT policy<{'armhf': 'y'}> +CONFIG_CPU_COPY_V6 policy<{'armhf': 'y'}> +CONFIG_CPU_CP15 policy<{'armhf': 'y'}> +CONFIG_CPU_CP15_MMU policy<{'armhf': 'y'}> +CONFIG_CPU_FREQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CPU_FREQ_GOV_ATTR_SET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_SCHEDUTIL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_THERMAL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_HAS_ASID policy<{'armhf': 'y'}> +CONFIG_CPU_HOTPLUG_STATE_CONTROL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CPU_ICACHE_DISABLE policy<{'armhf': 'n'}> +CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND policy<{'armhf': 'y'}> +CONFIG_CPU_IDLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_IDLE_GOV_HALTPOLL policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_CPU_IDLE_GOV_LADDER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_IDLE_GOV_MENU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_IDLE_GOV_TEO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_CPU_IDLE_THERMAL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_ISOLATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CPU_LITTLE_ENDIAN policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_CPU_MITIGATIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CPU_PABRT_V7 policy<{'armhf': 'y'}> +CONFIG_CPU_PJ4 policy<{'armhf': 'y'}> +CONFIG_CPU_PJ4B policy<{'armhf': 'y'}> +CONFIG_CPU_PM policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_CPU_RMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CPU_SPECTRE policy<{'armhf': 'y'}> +CONFIG_CPU_SUP_AMD policy<{'amd64': 'y'}> +CONFIG_CPU_SUP_CENTAUR policy<{'amd64': 'y'}> +CONFIG_CPU_SUP_HYGON policy<{'amd64': 'y'}> +CONFIG_CPU_SUP_INTEL policy<{'amd64': 'y'}> +CONFIG_CPU_SUP_ZHAOXIN policy<{'amd64': 'y'}> +CONFIG_CPU_THERMAL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_THUMB_CAPABLE policy<{'armhf': 'y'}> +CONFIG_CPU_TLB_V7 policy<{'armhf': 'y'}> +CONFIG_CPU_TTBR0_PAN policy<{'armhf': 'y'}> +CONFIG_CPU_V7 policy<{'armhf': 'y'}> +CONFIG_CRAMFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRAMFS_BLOCKDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CRAMFS_MTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CRASH_DM_CRYPT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRASH_DM_CRYPT_CONFIGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRASH_HOTPLUG policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_CRASH_MAX_MEMORY_RANGES policy<{'amd64': '8192', 'ppc64el': '8192'}> +CONFIG_CRASH_RESERVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC16 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC32 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC32_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC4 policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CRC64 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC64_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_CRC7 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CRC8 policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRC_CCITT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC_ITU_T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRC_OPTIMIZATIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC_T10DIF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC_T10DIF_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CROSS_MEMORY_ATTACH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_CHARDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_DEBUGFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_ISHTP policy<{'amd64': 'm'}> +CONFIG_CROS_EC_LIGHTBAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_LPC policy<{'amd64': 'm'}> +CONFIG_CROS_EC_MKBP_PROXIMITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_PROTO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_RPMSG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_SENSORHUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_SYSFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_TYPEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_TYPEC_ALTMODES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_CROS_EC_UART policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CROS_EC_UCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_VBC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_HPS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_KBD_LED_BACKLIGHT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_TYPEC_SWITCH policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CROS_USBPD_LOGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_USBPD_NOTIFY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_842 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ACOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_ACOMP2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ADIANTUM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_AEAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_AEAD2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_AEGIS128 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_AEGIS128_SIMD policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_AES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_AES_ARM64_BS policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM64_CE_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM64_CE_CCM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM64_NEON_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM_BS policy<{'armhf': 'm'}> +CONFIG_CRYPTO_AES_ARM_CE policy<{'armhf': 'm'}> +CONFIG_CRYPTO_AES_GCM_P10 policy<{'ppc64el': 'm'}> +CONFIG_CRYPTO_AES_NI_INTEL policy<{'amd64': 'm'}> +CONFIG_CRYPTO_AES_S390 policy<{'s390x': 'm'}> +CONFIG_CRYPTO_AKCIPHER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_AKCIPHER2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ALGAPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ALGAPI2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ARIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_ARIA_AESNI_AVX2_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_ARIA_GFNI_AVX512_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_AUTHENC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_BENCHMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_BLAKE2B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_BLOWFISH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_BLOWFISH_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_BLOWFISH_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAMELLIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAMELLIA_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAST5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CAST5_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAST6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CAST6_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAST_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CBC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_CCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CHACHA20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CHACHA20POLY1305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CRC32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CRC32C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_CRYPTD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_CTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DEFLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_DEV_ALLWINNER policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_AMLOGIC_GXL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CRYPTO_DEV_ARTPEC6 policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_ASPEED policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_ASPEED_ACRY policy<{'armhf': 'y'}> +CONFIG_CRYPTO_DEV_ASPEED_DEBUG policy<{'armhf': 'n'}> +CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO policy<{'armhf': 'y'}> +CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH policy<{'armhf': 'y'}> +CONFIG_CRYPTO_DEV_ATMEL_AES policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ATMEL_ECC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_DEV_ATMEL_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_ATMEL_SHA204A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_DEV_CCP policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CRYPTO_DEV_CCP_CRYPTO policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CRYPTO_DEV_CCP_DD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CRYPTO_DEV_CCP_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_CRYPTO_DEV_CCREE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_CHELSIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_CPT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_EIP93 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_EXYNOS_RNG policy<{'armhf': 'n'}> +CONFIG_CRYPTO_DEV_FSL_CAAM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD policy<{'arm64': '255', 'armhf': '255'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD policy<{'arm64': '2048', 'armhf': '2048'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_JR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE policy<{'arm64': '9', 'armhf': '9'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_HPRE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_QM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_SEC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_SEC2 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_TRNG policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_ZIP policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_IAA_CRYPTO policy<{'amd64': 'm'}> +CONFIG_CRYPTO_DEV_IAA_CRYPTO_STATS policy<{'amd64': 'n'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_MARVELL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_MARVELL_CESA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_MXS_DCP policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_NITROX policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_NITROX_CNN55XX policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_DEV_NX policy<{'ppc64el': 'y'}> +CONFIG_CRYPTO_DEV_NX_COMPRESS policy<{'ppc64el': 'm'}> +CONFIG_CRYPTO_DEV_NX_COMPRESS_POWERNV policy<{'ppc64el': 'm'}> +CONFIG_CRYPTO_DEV_NX_COMPRESS_PSERIES policy<{'ppc64el': 'm'}> +CONFIG_CRYPTO_DEV_OCTEONTX2_CPT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_OCTEONTX_CPT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_OMAP policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_OMAP_AES policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_OMAP_DES policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_OMAP_SHAM policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_PADLOCK policy<{'amd64': 'y'}> +CONFIG_CRYPTO_DEV_PADLOCK_AES policy<{'amd64': 'm'}> +CONFIG_CRYPTO_DEV_PADLOCK_SHA policy<{'amd64': 'm'}> +CONFIG_CRYPTO_DEV_QAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_420XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_4XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_6XXX policy<{'amd64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C3XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C3XXXVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C62X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C62XVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_DH895xCC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CRYPTO_DEV_QCE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_QCE_AEAD policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_QCE_SHA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_QCE_SKCIPHER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN policy<{'arm64': '512', 'armhf': '512'}> +CONFIG_CRYPTO_DEV_QCOM_RNG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_S5P policy<{'armhf': 'n'}> +CONFIG_CRYPTO_DEV_SA2UL policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SAFEXCEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_DEV_SAHARA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_SP_CCP policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CRYPTO_DEV_SP_PSP policy<{'amd64': 'y'}> +CONFIG_CRYPTO_DEV_STM32_CRYP policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_STM32_HASH policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SUN4I_SS policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_HASH policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_TI_DTHEV2 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_DEV_VMX policy<{'ppc64el': 'y'}> +CONFIG_CRYPTO_DEV_VMX_ENCRYPT policy<{'ppc64el': 'm'}> +CONFIG_CRYPTO_DEV_XILINX_TRNG policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ZYNQMP_AES policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DF80090A policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DH_RFC7919_GROUPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DRBG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DRBG_CTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DRBG_HASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DRBG_HMAC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DRBG_MENU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ECB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ECC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ECDH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ECDSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ECHAINIV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ECRDSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ENGINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ESSIV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_FCRYPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_GCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_GENIV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_GHASH_ARM64_CE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_GHASH_ARM_CE policy<{'armhf': 'm'}> +CONFIG_CRYPTO_HASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_HASH2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_HASH_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_HCTR2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_HMAC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_HW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_JITTERENTROPY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS policy<{'amd64': '64', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64', 's390x': '64'}> +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32', 's390x': '32'}> +CONFIG_CRYPTO_JITTERENTROPY_OSR policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1', 's390x': '1'}> +CONFIG_CRYPTO_KDF800108_CTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_KPP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_KPP2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_KRB5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_KRB5ENC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_KRB5_SELFTESTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_AES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_AESGCM policy<{'amd64': 'y'}> +CONFIG_CRYPTO_LIB_AES_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_AES_CBC_MACS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_ARC4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_BLAKE2B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_BLAKE2B_ARCH policy<{'armhf': 'y'}> +CONFIG_CRYPTO_LIB_BLAKE2S_ARCH policy<{'amd64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_LIB_CHACHA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_CHACHA20POLY1305 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_CHACHA_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_CURVE25519 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_CURVE25519_ARCH policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_DES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_GF128HASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_GF128HASH_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_GF128MUL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_MD5 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_MD5_ARCH policy<{'ppc64el': 'y'}> +CONFIG_CRYPTO_LIB_MLDSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_NH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_NH_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305_RSIZE policy<{'amd64': '11', 'arm64': '9', 'armhf': '9', 'ppc64el': '1', 'riscv64': '2', 's390x': '1'}> +CONFIG_CRYPTO_LIB_SHA1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA1_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA256 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA256_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA3 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA3_ARCH policy<{'arm64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA512 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SM3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_SM3_ARCH policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CRYPTO_LIB_UTILS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LRW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LZ4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LZ4HC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_MANAGER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_MANAGER2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_MD4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_MD5 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_MLDSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_NULL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_PAES_S390 policy<{'s390x': 'm'}> +CONFIG_CRYPTO_PCBC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_PCRYPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_PHMAC_S390 policy<{'s390x': 'm'}> +CONFIG_CRYPTO_RMD160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_RNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_RNG2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_RSA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SELFTESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CRYPTO_SEQIV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SERPENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_SERPENT_AVX2_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SERPENT_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SERPENT_SSE2_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SHA1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SHA256 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SHA3 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SIG2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SIMD policy<{'amd64': '-', 'armhf': '-', 'ppc64el': 'm'}> +CONFIG_CRYPTO_SKCIPHER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SKCIPHER2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SM3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_SM4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE_CCM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE_GCM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_NEON_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_STREEBOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_TWOFISH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_TWOFISH_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_TWOFISH_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_TWOFISH_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_TWOFISH_X86_64_3WAY policy<{'amd64': 'm'}> +CONFIG_CRYPTO_USER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_USER_API policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_USER_API_AEAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_USER_API_HASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_USER_API_RNG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_USER_API_RNG_CAVP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CRYPTO_USER_API_SKCIPHER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_WP512 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_XCBC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_XCTR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_XTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_XXHASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ZSTD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CS89x0 policy<{'armhf': 'm'}> +CONFIG_CS89x0_PLATFORM policy<{'armhf': 'm'}> +CONFIG_CSD_LOCK_WAIT_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CTCM policy<{'s390x': 'm'}> +CONFIG_CURRENT_POINTER_IN_TPIDRURO policy<{'armhf': 'y'}> +CONFIG_CUSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CV1800_MBOX policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CW1200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CW1200_WLAN_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CW1200_WLAN_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXD2880_SPI_DRV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_CXL_ATL policy<{'amd64': 'y'}> +CONFIG_CXL_BUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CXL_EDAC_MEM_FEATURES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CXL_FEATURES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CXL_MCE policy<{'amd64': 'y'}> +CONFIG_CXL_MEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_MEM_RAW_COMMANDS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CXL_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_PMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_PMU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_PORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_RAS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CXL_REGION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CXL_REGION_INVALIDATION_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CXL_SUSPEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CX_ECAT policy<{'amd64': 'm'}> +CONFIG_CYPRESS_FIRMWARE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CZNIC_PLATFORMS policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_D3323AA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DA280 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DA311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DA9052_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DA9055_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DA9062_THERMAL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DA9062_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DA9063_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DA9150_GPADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DAMON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DASD policy<{'s390x': 'm'}> +CONFIG_DASD_DIAG policy<{'s390x': 'm'}> +CONFIG_DASD_ECKD policy<{'s390x': 'm'}> +CONFIG_DASD_EER policy<{'s390x': 'y'}> +CONFIG_DASD_FBA policy<{'s390x': 'm'}> +CONFIG_DASD_PROFILE policy<{'s390x': 'y'}> +CONFIG_DASHARO_ACPI policy<{'amd64': 'm'}> +CONFIG_DATA_SHIFT policy<{'ppc64el': '24'}> +CONFIG_DAVICOM_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DAX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DA_MON_EVENTS_ID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DCA policy<{'amd64': 'm'}> +CONFIG_DCACHE_WORD_ACCESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DCDBAS policy<{'amd64': 'm'}> +CONFIG_DCSSBLK policy<{'s390x': 'm'}> +CONFIG_DDR policy<{'armhf': 'y'}> +CONFIG_DE2104X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DE2104X_DSL policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_DEBUGGER policy<{'ppc64el': 'y'}> +CONFIG_DEBUG_ALIGN_RODATA policy<{'armhf': 'y'}> +CONFIG_DEBUG_ATOMIC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_ATOMIC_SLEEP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_BOOT_PARAMS policy<{'amd64': 'n'}> +CONFIG_DEBUG_BUGVERBOSE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_BUGVERBOSE_DETAILED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_CGROUP_REF policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_CLOSURES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_DEVRES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_DRIVER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_EFI policy<{'arm64': 'n'}> +CONFIG_DEBUG_ENTRY policy<{'amd64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_FORCE_WEAK_PER_CPU policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_FS_ALLOW_ALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_FS_ALLOW_NONE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_GENERIC_PT policy<{'amd64': 'n', 'riscv64': 'n'}> +CONFIG_DEBUG_GPIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_HIGHMEM policy<{'armhf': 'n'}> +CONFIG_DEBUG_INFO_BTF_MODULES policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_INFO_COMPRESSED_NONE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_INFO_COMPRESSED_ZLIB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_COMPRESSED_ZSTD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_DWARF4 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_DWARF5 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_NONE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_REDUCED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_IRQFLAGS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_KERNEL_DC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DEBUG_KMAP_LOCAL policy<{'armhf': 'n'}> +CONFIG_DEBUG_KMEMLEAK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_KOBJECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_LIST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_LL policy<{'armhf': 'n'}> +CONFIG_DEBUG_LL_INCLUDE policy<{'armhf': '"mach/debug-macro.S"'}> +CONFIG_DEBUG_LOCKING_API_SELFTESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_LOCK_ALLOC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_MAPLE_TREE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_MEMORY_INIT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_MISC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_MUTEXES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_NET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_NET_SMALL_RTNL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_NMI_SELFTEST policy<{'amd64': 'n'}> +CONFIG_DEBUG_NOTIFIERS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_OBJECTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PAGEALLOC policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PAGE_REF policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PERF_USE_VMALLOC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PER_CPU_MAPS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PINCTRL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DEBUG_PLIST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PREEMPT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_RODATA_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_RSEQ policy<{'amd64': '-', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': '-', 's390x': '-'}> +CONFIG_DEBUG_RT_MUTEXES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_RWSEMS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_SECTION_MISMATCH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_SG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_SHIRQ policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_SPINLOCK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_STACKOVERFLOW policy<{'ppc64el': 'n'}> +CONFIG_DEBUG_STACK_USAGE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_TEST_DRIVER_REMOVE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_TLBFLUSH policy<{'amd64': 'n'}> +CONFIG_DEBUG_USER policy<{'armhf': 'n'}> +CONFIG_DEBUG_VFS policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_VF_UART_PORT policy<{'armhf': '1'}> +CONFIG_DEBUG_VIRTUAL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_VM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_VM_PGTABLE policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_WQ_FORCE_RR_CPU policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_WW_MUTEX_SLOWPATH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_WX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_BZIP2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_GZIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_LZ4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_LZMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_XZ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEFAULT_CUBIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEFAULT_HOSTNAME policy<{'amd64': '"(none)"', 'arm64': '"(none)"', 'armhf': '"(none)"', 'ppc64el': '"(none)"', 'riscv64': '"(none)"', 's390x': '"(none)"'}> +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT policy<{'amd64': '120', 'arm64': '120', 'armhf': '120', 'ppc64el': '120', 'riscv64': '120', 's390x': '120'}> +CONFIG_DEFAULT_INIT policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_DEFAULT_RENO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFAULT_SECURITY_APPARMOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEFAULT_SECURITY_DAC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFAULT_SECURITY_SELINUX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFAULT_SECURITY_SMACK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFAULT_SECURITY_TOMOYO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFAULT_TCP_CONG policy<{'amd64': '"cubic"', 'arm64': '"cubic"', 'armhf': '"cubic"', 'ppc64el': '"cubic"', 'riscv64': '"cubic"', 's390x': '"cubic"'}> +CONFIG_DEFERRED_STRUCT_PAGE_INIT policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DELL_LAPTOP policy<{'amd64': 'm'}> +CONFIG_DELL_PC policy<{'amd64': 'm'}> +CONFIG_DELL_RBTN policy<{'amd64': 'm'}> +CONFIG_DELL_RBU policy<{'amd64': 'm'}> +CONFIG_DELL_SMBIOS policy<{'amd64': 'm'}> +CONFIG_DELL_SMBIOS_SMM policy<{'amd64': 'y'}> +CONFIG_DELL_SMBIOS_WMI policy<{'amd64': 'y'}> +CONFIG_DELL_SMO8800 policy<{'amd64': 'm'}> +CONFIG_DELL_UART_BACKLIGHT policy<{'amd64': 'm'}> +CONFIG_DELL_WMI policy<{'amd64': 'm'}> +CONFIG_DELL_WMI_AIO policy<{'amd64': 'm'}> +CONFIG_DELL_WMI_DDV policy<{'amd64': 'm'}> +CONFIG_DELL_WMI_DESCRIPTOR policy<{'amd64': 'm'}> +CONFIG_DELL_WMI_LED policy<{'amd64': 'm'}> +CONFIG_DELL_WMI_PRIVACY policy<{'amd64': 'y'}> +CONFIG_DELL_WMI_SYSMAN policy<{'amd64': 'm'}> +CONFIG_DEPRECATED_PARAM_STRUCT policy<{'armhf': 'n'}> +CONFIG_DETECT_HUNG_TASK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DETECT_HUNG_TASK_BLOCKER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP policy<{'armhf': 'n'}> +CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU policy<{'armhf': 'n'}> +CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DEVFREQ_GOV_PASSIVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVFREQ_GOV_PERFORMANCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVFREQ_GOV_POWERSAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVFREQ_GOV_USERSPACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVFREQ_THERMAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVICE_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVICE_PRIVATE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_DEVTMPFS_SAFE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEV_COREDUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEV_DAX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DEV_DAX_CXL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DEV_DAX_FSDEV policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DEV_DAX_HMEM policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_DEV_DAX_HMEM_DEVICES policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DEV_DAX_KMEM policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DEV_DAX_PMEM policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DEV_SYNC_PROBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DHT11 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DIAG288_WATCHDOG policy<{'s390x': 'm'}> +CONFIG_DIBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DIBS_LO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DIMLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DL2K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DLHL60D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DLM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DLM_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DLN2_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DM9000 policy<{'armhf': 'm'}> +CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL policy<{'armhf': 'n'}> +CONFIG_DM9051 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DM9102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DMABUF_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMABUF_HEAPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DMABUF_HEAPS_CMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DMABUF_HEAPS_SYSTEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DMABUF_SELFTESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMADEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DMADEVICES_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DMAPOOL_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMARD06 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DMARD09 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DMARD10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DMAR_TABLE policy<{'amd64': 'y'}> +CONFIG_DMATEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DMA_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DMA_API_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DMA_COHERENT_POOL policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DMA_DECLARE_COHERENT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DMA_DIRECT_REMAP policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DMA_ENGINE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DMA_ENGINE_RAID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_DMA_FENCE_TRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMA_MAP_BENCHMARK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMA_NEED_SYNC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DMA_NONCOHERENT_MMAP policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DMA_NUMA_CMA policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DMA_OF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DMA_OMAP policy<{'armhf': 'y'}> +CONFIG_DMA_OPS_BYPASS policy<{'ppc64el': 'y'}> +CONFIG_DMA_OPS_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_DMA_RESTRICTED_POOL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DMA_SHARED_BUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DMA_SUN6I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DMA_VIRTUAL_CHANNELS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DMI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DMIID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK policy<{'amd64': 'y'}> +CONFIG_DMI_SYSFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_DM_AUDIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_BIO_PRISON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_BUFIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_CACHE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_CACHE_SMQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_CLONE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_CRYPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DM_DELAY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_DUST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DM_EBS policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_ERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_FLAKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_INIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_INTEGRITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_LOG_USERSPACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_LOG_WRITES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MIRROR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MULTIPATH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MULTIPATH_HST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MULTIPATH_IOA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MULTIPATH_QL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MULTIPATH_ST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_PCACHE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DM_PERSISTENT_DATA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_RAID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_SNAPSHOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_SWITCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_THIN_PROVISIONING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_UEVENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_UNSTRIPED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_VDO policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_VERITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_VERITY_FEC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_WRITECACHE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_ZERO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_ZONED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DNOTIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DNS_RESOLVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DOVE_CLK policy<{'armhf': 'y'}> +CONFIG_DOVE_THERMAL policy<{'armhf': 'm'}> +CONFIG_DP83640_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83822_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83848_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83867_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83869_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83TC811_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83TD510_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DP83TG720_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DPAA2_CONSOLE policy<{'arm64': 'm'}> +CONFIG_DPAA_ERRATUM_A050385 policy<{'arm64': 'y'}> +CONFIG_DPLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DPLL_REFCNT_TRACKER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DPM_WATCHDOG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DPOT_DAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DPS310 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DPTF_PCH_FIVR policy<{'amd64': 'm'}> +CONFIG_DPTF_POWER policy<{'amd64': 'm'}> +CONFIG_DQL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRAGONRISE_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRBD_FAULT_INJECTION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRIVER_DEFERRED_PROBE_TIMEOUT policy<{'amd64': '10', 'arm64': '10', 'armhf': '10', 'ppc64el': '10', 'riscv64': '10', 's390x': '10'}> +CONFIG_DRM_ACCEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DRM_ACCEL_AMDXDNA policy<{'amd64': 'm'}> +CONFIG_DRM_ACCEL_ARM_ETHOSU policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_ACCEL_HABANALABS policy<{'amd64': 'm'}> +CONFIG_DRM_ACCEL_IVPU policy<{'amd64': 'm'}> +CONFIG_DRM_ACCEL_IVPU_DEBUG policy<{'amd64': 'n'}> +CONFIG_DRM_ACCEL_QAIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ACCEL_ROCKET policy<{'arm64': 'm'}> +CONFIG_DRM_ADP policy<{'arm64': 'm'}> +CONFIG_DRM_AMDGPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_AMDGPU_SI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMDGPU_USERPTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMDGPU_WERROR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n'}> +CONFIG_DRM_AMD_ACP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMD_DC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMD_DC_FP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMD_DC_SI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMD_ISP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_AMD_SECURE_DISPLAY policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_ANALOGIX_ANX6345 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ANALOGIX_ANX7625 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ANALOGIX_ANX78XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_ANALOGIX_DP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_APPLETBDRM policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_ARCPGU policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ARMADA policy<{'armhf': 'm'}> +CONFIG_DRM_ASPEED_GFX policy<{'armhf': 'm'}> +CONFIG_DRM_AST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_ATMEL_HLCDC policy<{'armhf': 'm'}> +CONFIG_DRM_AUX_BRIDGE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_AUX_HPD_BRIDGE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_BOCHS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DRM_BRIDGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_BRIDGE_CONNECTOR policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_BUDDY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_CDNS_DSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_CDNS_DSI_J721E policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_CDNS_MHDP8546 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_CDNS_MHDP8546_J721E policy<{'arm64': 'y'}> +CONFIG_DRM_CHIPONE_ICN6211 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_CHRONTEL_CH7033 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_CIRRUS_QEMU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_CLIENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_CLIENT_DEFAULT policy<{'amd64': '"fbdev"', 'arm64': '"fbdev"', 'armhf': '"fbdev"', 'ppc64el': '"fbdev"', 'riscv64': '"fbdev"', 's390x': '"fbdev"'}> +CONFIG_DRM_CLIENT_DEFAULT_FBDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_CLIENT_DEFAULT_LOG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_CLIENT_LIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM_CLIENT_LOG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_CLIENT_SELECTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM_CLIENT_SETUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_CROS_EC_ANX7688 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_DEBUG_MM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_DEBUG_MODESET_LOCK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_DISPLAY_CONNECTOR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_DISPLAY_DP_AUX_BUS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_DISPLAY_DP_AUX_CEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_DP_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_DP_TUNNEL policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_DSC_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDCP_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_AUDIO_HELPER policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_CEC_HELPER policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_DRAW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_DW_DP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_DW_HDMI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_DW_HDMI_AHB_AUDIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_DW_HDMI_CEC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_DW_HDMI_GP_AUDIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_DW_HDMI_I2S_AUDIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_DW_HDMI_QP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_DW_HDMI_QP_CEC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_DW_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_DW_MIPI_DSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_ETNAVIV policy<{'amd64': 'n', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_ETNAVIV_THERMAL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_EXEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_EXYNOS policy<{'armhf': 'm'}> +CONFIG_DRM_EXYNOS5433_DECON policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS7_DECON policy<{'armhf': 'n'}> +CONFIG_DRM_EXYNOS_DSI policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_FIMC policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_FIMD policy<{'armhf': 'n'}> +CONFIG_DRM_EXYNOS_G2D policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_GSC policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_HDMI policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_IPP policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_MIC policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_MIXER policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_ROTATOR policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_SCALER policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_VIDI policy<{'armhf': 'n'}> +CONFIG_DRM_FBDEV_EMULATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_FBDEV_OVERALLOC policy<{'amd64': '100', 'arm64': '100', 'armhf': '100', 'ppc64el': '100', 'riscv64': '100', 's390x': '100'}> +CONFIG_DRM_FSL_DCU policy<{'armhf': 'm'}> +CONFIG_DRM_FSL_LDB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_GEM_DMA_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_GEM_SHMEM_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM_GM12U320 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_GMA500 policy<{'amd64': 'm'}> +CONFIG_DRM_GPUSVM policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_DRM_GPUVM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_GUD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_HDLCD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_HDLCD_SHOW_UNDERRUN policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_DRM_HISI_HIBMC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_HISI_KIRIN policy<{'arm64': 'm'}> +CONFIG_DRM_HYPERV policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_DRM_I2C_ADV7511 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_I2C_ADV7511_AUDIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_I2C_ADV7511_CEC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_I2C_NXP_TDA998X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_I915 policy<{'amd64': 'm'}> +CONFIG_DRM_I915_CAPTURE_ERROR policy<{'amd64': 'y'}> +CONFIG_DRM_I915_COMPRESS_ERROR policy<{'amd64': 'y'}> +CONFIG_DRM_I915_DEBUG policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DEBUG_GUC policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DEBUG_MMIO policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DEBUG_RUNTIME_PM policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DEBUG_VBLANK_EVADE policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DEBUG_WAKEREF policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DP_TUNNEL policy<{'amd64': 'y'}> +CONFIG_DRM_I915_FENCE_TIMEOUT policy<{'amd64': '10000'}> +CONFIG_DRM_I915_FORCE_PROBE policy<{'amd64': '""'}> +CONFIG_DRM_I915_GVT policy<{'amd64': 'y'}> +CONFIG_DRM_I915_GVT_KVMGT policy<{'amd64': 'm'}> +CONFIG_DRM_I915_HEARTBEAT_INTERVAL policy<{'amd64': '2500'}> +CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS policy<{'amd64': 'n'}> +CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT policy<{'amd64': '8000'}> +CONFIG_DRM_I915_PREEMPT_TIMEOUT policy<{'amd64': '640'}> +CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE policy<{'amd64': '7500'}> +CONFIG_DRM_I915_PXP policy<{'amd64': 'y'}> +CONFIG_DRM_I915_REQUEST_TIMEOUT policy<{'amd64': '20000'}> +CONFIG_DRM_I915_SELFTEST policy<{'amd64': 'n'}> +CONFIG_DRM_I915_STOP_TIMEOUT policy<{'amd64': '100'}> +CONFIG_DRM_I915_SW_FENCE_CHECK_DAG policy<{'amd64': 'n'}> +CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS policy<{'amd64': 'n'}> +CONFIG_DRM_I915_TIMESLICE_DURATION policy<{'amd64': '1'}> +CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND policy<{'amd64': '250'}> +CONFIG_DRM_I915_USERPTR policy<{'amd64': 'y'}> +CONFIG_DRM_I915_WERROR policy<{'amd64': 'n'}> +CONFIG_DRM_IMX policy<{'armhf': 'm'}> +CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8MP_HDMI_PAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8MP_HDMI_PVI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8QM_LDB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8QXP_LDB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8QXP_PIXEL_COMBINER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8QXP_PIXEL_LINK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8_DC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX93_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX_DCSS policy<{'arm64': 'm'}> +CONFIG_DRM_IMX_HDMI policy<{'armhf': 'm'}> +CONFIG_DRM_IMX_LCDC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX_LCDIF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_IMX_LDB policy<{'armhf': 'm'}> +CONFIG_DRM_IMX_LDB_HELPER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX_LEGACY_BRIDGE policy<{'armhf': 'm'}> +CONFIG_DRM_IMX_PARALLEL_DISPLAY policy<{'armhf': 'm'}> +CONFIG_DRM_IMX_TVE policy<{'armhf': 'm'}> +CONFIG_DRM_INNO_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_ITE_IT6263 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ITE_IT6505 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ITE_IT66121 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_KMB_DISPLAY policy<{'arm64': 'm'}> +CONFIG_DRM_KMS_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM_KOMEDA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LIMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_LOAD_EDID_FIRMWARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_LOGICVC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LONTIUM_LT8713SX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LONTIUM_LT8912B policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LONTIUM_LT9211 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LONTIUM_LT9611 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LONTIUM_LT9611UXC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LVDS_CODEC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_MALI_DISPLAY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MCDE policy<{'armhf': 'm'}> +CONFIG_DRM_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MEDIATEK_DP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MEDIATEK_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MEDIATEK_HDMI_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MEDIATEK_HDMI_V2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MESON_DW_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MESON_DW_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER policy<{'armhf': 'm'}> +CONFIG_DRM_MIPI_DBI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_MIPI_DSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_MSM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MSM_DP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DPU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_10NM_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_14NM_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_20NM_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_28NM_8960_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_28NM_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_7NM_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_GPU_STATE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_GPU_SUDO policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_DRM_MSM_HDMI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_HDMI_HDCP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_KMS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_KMS_FBDEV policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_MDP4 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_MDP5 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_MDSS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_VALIDATE_XML policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_DRM_MXS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_MXSFB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_NOUVEAU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_NOUVEAU_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_NOUVEAU_CH7006 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_NOUVEAU_SIL164 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_NOUVEAU_SVM policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DRM_NWL_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_NXP_PTN3460 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_OFDRM policy<{'ppc64el': 'm'}> +CONFIG_DRM_OMAP policy<{'armhf': 'n'}> +CONFIG_DRM_PANEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_PANEL_ABT_Y030XX067A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ARM_VERSATILE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_AUO_A030JTN01 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BOE_HIMAX8279D policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BOE_TD4320 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BRIDGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_PANEL_DSI_CM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_EBBG_FT8719 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_EDP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ELIDA_KD35T133 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX8279 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX83102 policy<{'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX83112A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX83112B policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX83121A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX8394 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HYDIS_HV101HD1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_IL9322 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9805 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9806E_CORE policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9806E_DSI policy<{'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9806E_SPI policy<{'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9881C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9882T policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_INNOLUX_EJ030NA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_INNOLUX_P079ZCA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_JDI_LPM102A188A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_JDI_LT070ME05000 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_JDI_R63452 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_KHADAS_TS050 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LG_LB035Q02 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LG_LD070WX3 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LG_LG4573 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LG_SW43408 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 policy<{'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LVDS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LXD_M9189A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_MIPI_DBI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_MOTOROLA_MOT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NEC_NL8048HL11 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NEWVISION_NV3051D policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NEWVISION_NV3052C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT35510 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT35560 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT35950 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT36523 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT36672A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT36672E policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT37700F policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT37801 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT39016 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM_PANEL_ORISETECH_OTA5601A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ORISETECH_OTM8009A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM67191 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM67200 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM68200 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM692E5 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM69380 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RENESAS_R61307 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RENESAS_R69328 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RONBO_RB070D30 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_ATNA40CT01 policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DRM_PANEL_SAMSUNG_DB7430 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_LD9040 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_LTL106HL02 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3FC2X01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E8FC0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SEIKO_43WVF1G policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LQ079L1SX01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LS037V7DW01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LS043T1LE01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LS060T1SX01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SIMPLE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SITRONIX_ST7701 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SITRONIX_ST7703 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SITRONIX_ST7789V policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SONY_ACX565AKM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SONY_TD4353_JDI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SUMMIT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SYNAPTICS_R63353 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SYNAPTICS_TDDI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_TDO_TL070WSH30 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_TPO_TD028TTEC1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_TPO_TD043MTEA1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_TPO_TPG110 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_G2647FB105 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_R66451 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_RM69299 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_RM692E5 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_VTDR6130 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_WIDECHIPS_WS2401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_PANEL_XINPENG_XPP055C272 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANFROST policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_PANIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DRM_PANIC_BACKGROUND_COLOR policy<{'amd64': '0x5e2750', 'arm64': '0x5e2750', 'armhf': '0x5e2750', 'ppc64el': '0x5e2750', 'riscv64': '0x5e2750'}> +CONFIG_DRM_PANIC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DRM_PANIC_FOREGROUND_COLOR policy<{'amd64': '0xffffff', 'arm64': '0xffffff', 'armhf': '0xffffff', 'ppc64el': '0xffffff', 'riscv64': '0xffffff'}> +CONFIG_DRM_PANIC_SCREEN policy<{'amd64': '"user"', 'arm64': '"user"', 'armhf': '"user"', 'ppc64el': '"user"', 'riscv64': '"user"'}> +CONFIG_DRM_PANTHOR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_PARADE_PS8622 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PARADE_PS8640 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PIXPAPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PL111 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_POWERVR policy<{'arm64': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PRIVACY_SCREEN policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_DRM_QXL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_RADEON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_RADEON_USERPTR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DRM_RAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DRM_RCAR_CMM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RCAR_DU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RCAR_DW_HDMI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-'}> +CONFIG_DRM_RCAR_LVDS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-'}> +CONFIG_DRM_RCAR_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RCAR_USE_CMM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_RCAR_USE_LVDS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_DRM_RCAR_USE_MIPI_DSI policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_DRM_RCAR_VSP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_RCAR_WRITEBACK policy<{'arm64': 'y'}> +CONFIG_DRM_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RZG2L_DU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RZG2L_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RZG2L_USE_MIPI_DSI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_SAMSUNG_DSIM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SCHED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SHMOBILE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_SII902X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SII9234 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SIL_SII8620 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SIMPLE_BRIDGE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SOLOMON_SSD2825 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SPRD policy<{'arm64': 'm'}> +CONFIG_DRM_SSD130X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_SSD130X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SSD130X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ST7571 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_ST7571_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_ST7571_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ST7586 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ST7735R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ST7920 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_STM policy<{'arm64': 'm'}> +CONFIG_DRM_STM_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_STM_LVDS policy<{'arm64': 'm'}> +CONFIG_DRM_SUBALLOC_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SUN4I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DRM_SUN6I_DSI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DRM_SUN8I_DW_HDMI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DRM_SUN8I_MIXER policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DRM_SUN8I_TCON_TOP policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_DRM_SYSFB_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_TEGRA_DEBUG policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_DRM_TEGRA_STAGING policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_THINE_THC63LVD1024 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TIDSS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_TILCDC policy<{'armhf': 'm'}> +CONFIG_DRM_TILCDC_PANEL_LEGACY policy<{'armhf': 'y'}> +CONFIG_DRM_TI_DLPC3433 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TI_SN65DSI83 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TI_SN65DSI86 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TI_TDP158 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TI_TFP410 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TI_TPD12S015 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358762 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358764 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358767 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358768 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358775 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TTM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_TTM_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_TVE200 policy<{'armhf': 'm'}> +CONFIG_DRM_UDL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_VERISILICON_DC policy<{'riscv64': 'm'}> +CONFIG_DRM_VGEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_VIRTIO_GPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DRM_VIRTIO_GPU_KMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_VKMS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_VMWGFX policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_DRM_VMWGFX_MKSSTATS policy<{'amd64': 'n'}> +CONFIG_DRM_VRAM_HELPER policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_DRM_WAVESHARE_BRIDGE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_WERROR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_XE policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_XEN policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_DRM_XEN_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_DRM_XE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_DEBUG_MEM policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_DEBUG_MEMIRQ policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_DEBUG_SRIOV policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_DEBUG_VM policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_DISPLAY policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_XE_DP_TUNNEL policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_XE_FORCE_PROBE policy<{'amd64': '""', 'arm64': '""', 'arm64-generic-64k': '-', 'armhf': '""', 'ppc64el': '-', 'riscv64': '""'}> +CONFIG_DRM_XE_GPUSVM policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_XE_JOB_TIMEOUT_MAX policy<{'amd64': '10000', 'arm64': '10000', 'arm64-generic-64k': '-', 'armhf': '10000', 'ppc64el': '-', 'riscv64': '10000'}> +CONFIG_DRM_XE_JOB_TIMEOUT_MIN policy<{'amd64': '1', 'arm64': '1', 'arm64-generic-64k': '-', 'armhf': '1', 'ppc64el': '-', 'riscv64': '1'}> +CONFIG_DRM_XE_PAGEMAP policy<{'amd64': 'y', 'arm64-generic': 'y', 'riscv64': 'y'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT policy<{'amd64': '640000', 'arm64': '640000', 'arm64-generic-64k': '-', 'armhf': '640000', 'ppc64el': '-', 'riscv64': '640000'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX policy<{'amd64': '10000000', 'arm64': '10000000', 'arm64-generic-64k': '-', 'armhf': '10000000', 'ppc64el': '-', 'riscv64': '10000000'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN policy<{'amd64': '1', 'arm64': '1', 'arm64-generic-64k': '-', 'armhf': '1', 'ppc64el': '-', 'riscv64': '1'}> +CONFIG_DRM_XE_TIMESLICE_MAX policy<{'amd64': '10000000', 'arm64': '10000000', 'arm64-generic-64k': '-', 'armhf': '10000000', 'ppc64el': '-', 'riscv64': '10000000'}> +CONFIG_DRM_XE_TIMESLICE_MIN policy<{'amd64': '1', 'arm64': '1', 'arm64-generic-64k': '-', 'armhf': '1', 'ppc64el': '-', 'riscv64': '1'}> +CONFIG_DRM_XE_USERPTR_INVAL_INJECT policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_WERROR policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_ZYNQMP_DPSUB policy<{'arm64': 'm'}> +CONFIG_DRM_ZYNQMP_DPSUB_AUDIO policy<{'arm64': 'y'}> +CONFIG_DS1682 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DS1803 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DS4424 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DST_CACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DTC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DTL policy<{'ppc64el': 'y'}> +CONFIG_DTPM policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DTPM_CPU policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DTPM_DEVFREQ policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DT_IDLE_GENPD policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DT_IDLE_STATES policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DUMMY_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DUMMY_CONSOLE_COLUMNS policy<{'amd64': '80', 'arm64': '80', 'armhf': '80', 'ppc64el': '80', 'riscv64': '80', 's390x': '80'}> +CONFIG_DUMMY_CONSOLE_ROWS policy<{'amd64': '25', 'arm64': '25', 'armhf': '30', 'ppc64el': '25', 'riscv64': '25', 's390x': '25'}> +CONFIG_DUMMY_IRQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DVB_A8293 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AF9013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AF9033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AS102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AS102_FE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ASCOT2E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ATBM8830 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AU8522 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AU8522_DTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AU8522_V4L policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AV7110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AV7110_IR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_AV7110_OSD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_B2C2_FLEXCOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_B2C2_FLEXCOP_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_B2C2_FLEXCOP_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_BCM3510 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_BT8XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_BUDGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_BUDGET_AV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_BUDGET_CI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_BUDGET_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX22700 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX22702 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX24110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX24116 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX24117 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX24120 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX24123 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CXD2099 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CXD2820R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CXD2841ER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CXD2880 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DDBRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DDBRIDGE_MSIENABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_DEMUX_SECTION_LOSS_LOG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_DIB3000MB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DIB3000MC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DIB7000M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DIB7000P policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DIB8000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DIB9000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DM1105 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DRX39XYJ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DRXD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DRXK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DS3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DYNAMIC_MINORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_EC100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_FIREDTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_FIREDTV_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_GP8PSK_FE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_HELENE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_HOPPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_HORUS3A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ISL6405 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ISL6421 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ISL6423 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_IX2505V policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_L64781 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LG2160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LGDT3305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LGDT3306A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LGDT330X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LGS8GL5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LGS8GXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LNBH25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LNBH29 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LNBP21 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LNBP22 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_M88DS3103 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_M88RS2000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MANTIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MAX_ADAPTERS policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8'}> +CONFIG_DVB_MB86A16 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MB86A20S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MMAP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_MN88443X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MN88472 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MN88473 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MT312 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MT352 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MXL5XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MXL692 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_NET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_NETUP_UNIDVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_NGENE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_NXT200X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_NXT6000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_OR51132 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_OR51211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_PLATFORM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_PLL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_PLUTO2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_PT1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_PT3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_RTL2830 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_RTL2832 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_RTL2832_SDR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_S5H1409 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_S5H1411 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_S5H1420 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_S5H1432 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_S921 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SI2165 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SI2168 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SI21XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SMIPCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SP2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SP8870 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SP887X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STB0899 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STB6000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STB6100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0288 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0297 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0299 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0367 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0900 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV090x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0910 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV6110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV6110x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV6111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TC90522 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA10021 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA10023 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA10048 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA1004X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA10071 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA10086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA18271C2DD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA665x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA8083 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA8261 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA826X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TEST_DRIVERS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_TS2020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TTUSB_BUDGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TTUSB_DEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TUA6100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TUNER_CX24113 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TUNER_DIB0070 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TUNER_DIB0090 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TUNER_ITD1000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ULE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_A800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AF9005 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AF9005_REMOTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AF9015 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AF9035 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_ANYSEE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AU6610 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AZ6007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AZ6027 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_CE6230 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_CINERGY_T2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_CXUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_CXUSB_ANALOG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_USB_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_USB_DIB0700 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DIB3000MC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DIBUSB_MB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DIBUSB_MB_FAULTY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_USB_DIBUSB_MC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DIGITV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DTT200U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DTV5100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DVBSKY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DW2102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_EC168 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_GL861 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_GP8PSK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_LME2510 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_M920X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_MXL111SF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_NOVA_T_USB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_OPERA1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_PCTV452E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_RTL28XXU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_TECHNISAT_USB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_TTUSB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_UMT_010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_V2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_VP702X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_VP7045 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_ZD1301 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_VES1820 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_VES1X93 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ZD1301_DEMOD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ZL10036 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ZL10039 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ZL10353 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DWC_PCIE_PMU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DWC_XLGMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DWC_XLGMAC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DWMAC_DWC_QOS_ETH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DWMAC_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DWMAC_IMX8 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_INTEL policy<{'amd64': 'm'}> +CONFIG_DWMAC_INTEL_PLAT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DWMAC_IPQ806X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_MOTORCOMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DWMAC_NUVOTON policy<{'arm64': 'm'}> +CONFIG_DWMAC_QCOM_ETHQOS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_RENESAS_GBETH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_RZN1 policy<{'armhf': 'm'}> +CONFIG_DWMAC_S32 policy<{'arm64': 'm'}> +CONFIG_DWMAC_SOCFPGA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_SOPHGO policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_DWMAC_STM32 policy<{'arm64': 'm'}> +CONFIG_DWMAC_SUN55I policy<{'arm64': 'm'}> +CONFIG_DWMAC_SUN8I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DWMAC_SUNXI policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DWMAC_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_VISCONTI policy<{'arm64': 'm'}> +CONFIG_DW_APB_ICTL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DW_APB_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DW_APB_TIMER_OF policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DW_AXI_DMAC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DW_DMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DW_DMAC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DW_DMAC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DW_EDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DW_EDMA_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DW_I3C_MASTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DW_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DW_XDATA_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DYNAMIC_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_DEBUG_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_FTRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_ARGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS policy<{'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_JMP policy<{'amd64': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_REGS policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_DYNAMIC_PHYSICAL_MASK policy<{'amd64': 'y'}> +CONFIG_DYNAMIC_SIGFRAME policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_E100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_E1000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_E1000E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_E1000E_HWTS policy<{'amd64': 'y'}> +CONFIG_EADM_SCH policy<{'s390x': 'm'}> +CONFIG_EARLY_PRINTK policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_EARLY_PRINTK_DBGP policy<{'amd64': 'y'}> +CONFIG_EARLY_PRINTK_USB policy<{'amd64': 'y'}> +CONFIG_EARLY_PRINTK_USB_XDBC policy<{'amd64': 'y'}> +CONFIG_EBC_C384_WDT policy<{'amd64': 'm'}> +CONFIG_ECRYPT_FS_MESSAGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EC_ACER_ASPIRE1 policy<{'arm64': 'm'}> +CONFIG_EC_DELL_XPS policy<{'arm64': 'n'}> +CONFIG_EC_HUAWEI_GAOKUN policy<{'arm64': 'm'}> +CONFIG_EC_LENOVO_THINKPAD_T14S policy<{'arm64': 'm'}> +CONFIG_EC_LENOVO_YOGA_C630 policy<{'arm64-generic': 'm', 'arm64-generic-64k': 'n'}> +CONFIG_EC_LENOVO_YOGA_SLIM7X policy<{'arm64': 'n'}> +CONFIG_EC_QCOM_HAMOA policy<{'arm64': 'n'}> +CONFIG_EDAC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_EDAC_ALTERA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_ETHERNET policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_L2C policy<{'armhf': 'y'}> +CONFIG_EDAC_ALTERA_NAND policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_OCRAM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_QSPI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_SDMMC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_SDRAM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_USB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_AMD64 policy<{'amd64': 'm'}> +CONFIG_EDAC_ARMADA_XP policy<{'armhf': 'y'}> +CONFIG_EDAC_ASPEED policy<{'armhf': 'm'}> +CONFIG_EDAC_ATOMIC_SCRUB policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_EDAC_BLUEFIELD policy<{'arm64': 'm'}> +CONFIG_EDAC_CORTEX_A72 policy<{'arm64': 'm'}> +CONFIG_EDAC_CPC925 policy<{'ppc64el': 'm'}> +CONFIG_EDAC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_EDAC_DECODE_MCE policy<{'amd64': 'm'}> +CONFIG_EDAC_DMC520 policy<{'arm64': 'm'}> +CONFIG_EDAC_E752X policy<{'amd64': 'm'}> +CONFIG_EDAC_ECS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_EDAC_GHES policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_EDAC_HIGHBANK_L2 policy<{'armhf': 'm'}> +CONFIG_EDAC_HIGHBANK_MC policy<{'armhf': 'm'}> +CONFIG_EDAC_I10NM policy<{'amd64': 'm'}> +CONFIG_EDAC_I3000 policy<{'amd64': 'm'}> +CONFIG_EDAC_I3200 policy<{'amd64': 'm'}> +CONFIG_EDAC_I5100 policy<{'amd64': 'm'}> +CONFIG_EDAC_I5400 policy<{'amd64': 'm'}> +CONFIG_EDAC_I7300 policy<{'amd64': 'm'}> +CONFIG_EDAC_I7CORE policy<{'amd64': 'm'}> +CONFIG_EDAC_I82975X policy<{'amd64': 'm'}> +CONFIG_EDAC_IE31200 policy<{'amd64': 'm'}> +CONFIG_EDAC_IGEN6 policy<{'amd64': 'm'}> +CONFIG_EDAC_IMH policy<{'amd64': 'm'}> +CONFIG_EDAC_LAYERSCAPE policy<{'arm64': 'm'}> +CONFIG_EDAC_MEM_REPAIR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_EDAC_NPCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EDAC_PND2 policy<{'amd64': 'm'}> +CONFIG_EDAC_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EDAC_SBRIDGE policy<{'amd64': 'm'}> +CONFIG_EDAC_SCRUB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_EDAC_SKX policy<{'amd64': 'm'}> +CONFIG_EDAC_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_EDAC_SYNOPSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EDAC_THUNDERX policy<{'arm64': 'm'}> +CONFIG_EDAC_TI policy<{'armhf': 'm'}> +CONFIG_EDAC_VERSAL policy<{'arm64': 'm'}> +CONFIG_EDAC_VERSALNET policy<{'arm64': 'm'}> +CONFIG_EDAC_X38 policy<{'amd64': 'm'}> +CONFIG_EDAC_XGENE policy<{'arm64': 'm'}> +CONFIG_EDAC_ZYNQMP policy<{'arm64': 'm'}> +CONFIG_EDD policy<{'amd64': 'y'}> +CONFIG_EDD_OFF policy<{'amd64': 'y'}> +CONFIG_EEEPC_LAPTOP policy<{'amd64': 'm'}> +CONFIG_EEEPC_WMI policy<{'amd64': 'm'}> +CONFIG_EEH policy<{'ppc64el': 'y'}> +CONFIG_EEPROM_93CX6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EEPROM_93XX46 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EEPROM_AT24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EEPROM_AT25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EEPROM_EE1004 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EEPROM_IDT_89HPESX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EEPROM_M24LR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EEPROM_MAX6875 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EFI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_ARMSTUB_DTB_LOADER policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_EFI_BOOTLOADER_CONTROL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_EFI_CAPSULE_LOADER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_EFI_COCO_SECRET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_EFI_DEV_PATH_PARSER policy<{'amd64': 'y'}> +CONFIG_EFI_DISABLE_PCI_DMA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_EFI_DISABLE_RUNTIME policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_EFI_DXE_MEM_ATTRIBUTES policy<{'amd64': 'y'}> +CONFIG_EFI_EARLYCON policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_EFI_EMBEDDED_FIRMWARE policy<{'amd64': 'y'}> +CONFIG_EFI_ESRT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_GENERIC_STUB policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_MIXED policy<{'amd64': 'y'}> +CONFIG_EFI_PARAMS_FROM_FDT policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EFI_PGT_DUMP policy<{'amd64': 'n'}> +CONFIG_EFI_RCI2_TABLE policy<{'amd64': 'y'}> +CONFIG_EFI_RUNTIME_MAP policy<{'amd64': 'y'}> +CONFIG_EFI_RUNTIME_WRAPPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_SBAT_FILE policy<{'amd64': '""', 'arm64': '""', 'riscv64': '""'}> +CONFIG_EFI_SECRET policy<{'amd64': 'm', 'arm64': 'n'}> +CONFIG_EFI_SOFT_RESERVE policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_EFI_STUB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_EFI_VARS_PSTORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_EFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EINT_MTK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ELFCORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ELF_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EMAC_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EM_TIMER_STI policy<{'armhf': 'y'}> +CONFIG_ENA_ETHERNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ENC28J60 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ENC28J60_WRITEVERIFY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ENCLOSURE_SERVICES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ENCRYPTED_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ENCX24J600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ENERGY_MODEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ENIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ENS160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ENS160_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ENS160_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ENS210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ENVELOPE_DETECTOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_EPAPR_BOOT policy<{'ppc64el': 'y'}> +CONFIG_EPAPR_PARAVIRT policy<{'ppc64el': 'y'}> +CONFIG_EPIC100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EPOLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EPROBE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EQUALIZER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_EROFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_EROFS_FS_BACKED_BY_FILE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EROFS_FS_ONDEMAND policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EROFS_FS_PAGE_CACHE_SHARE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EROFS_FS_PCPU_KTHREAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EROFS_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_ZIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_ZIP_ACCEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_ZIP_DEFLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_ZIP_LZMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_ZIP_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ERRATA_ANDES policy<{'riscv64': 'n'}> +CONFIG_ERRATA_MIPS policy<{'riscv64': 'n'}> +CONFIG_ERRATA_SIFIVE policy<{'riscv64': 'n'}> +CONFIG_ERRATA_THEAD policy<{'riscv64': 'n'}> +CONFIG_ET131X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ETHERNET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ETHOC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ETHTOOL_NETLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EUROTECH_WDT policy<{'amd64': 'm'}> +CONFIG_EVENTFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EVENT_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EVM_ADD_XATTRS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EVM_EXTRA_SMACK_XATTRS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXAR_WDT policy<{'amd64': 'm'}> +CONFIG_EXCLUSIVE_SYSTEM_RAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXECMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXFAT_DEFAULT_IOCHARSET policy<{'amd64': '"utf8"', 'arm64': '"utf8"', 'armhf': '"utf8"', 'ppc64el': '"utf8"', 'riscv64': '"utf8"', 's390x': '"utf8"'}> +CONFIG_EXFAT_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_EXPERT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXPOLINE policy<{'s390x': 'y'}> +CONFIG_EXPOLINE_AUTO policy<{'s390x': 'y'}> +CONFIG_EXPOLINE_EXTERN policy<{'s390x': 'y'}> +CONFIG_EXPOLINE_FULL policy<{'s390x': 'n'}> +CONFIG_EXPOLINE_OFF policy<{'s390x': 'n'}> +CONFIG_EXPORTFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXPORTFS_BLOCK_OPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXT4_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EXT4_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXT4_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXT4_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXT4_USE_FOR_EXT2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXTCON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_EXTCON_ADC_JACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_EXTCON_AXP288 policy<{'amd64': 'm'}> +CONFIG_EXTCON_FSA9480 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_INTEL_CHT_WC policy<{'amd64': 'm'}> +CONFIG_EXTCON_INTEL_INT3496 policy<{'amd64': 'm'}> +CONFIG_EXTCON_INTEL_MRFLD policy<{'amd64': 'm'}> +CONFIG_EXTCON_LC824206XA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_EXTCON_MAX14526 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_EXTCON_MAX14577 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_MAX3355 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_MAX77693 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_MAX77843 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_MAX8997 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_PALMAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_PTN5150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_QCOM_SPMI_MISC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EXTCON_RT8973A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_RTK_TYPE_C policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EXTCON_SM5502 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_USBC_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_EXTCON_USBC_TUSB320 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_USB_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTENDED_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXTRA_FIRMWARE policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_EXTRA_TARGETS policy<{'ppc64el': '""'}> +CONFIG_EXT_GROUP_SCHED policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXT_SUB_SCHED policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXYNOS5422_DMC policy<{'armhf': 'n'}> +CONFIG_EXYNOS_ACPM_CLK policy<{'armhf': 'n'}> +CONFIG_EXYNOS_ACPM_PROTOCOL policy<{'armhf': 'm'}> +CONFIG_EXYNOS_ADC policy<{'armhf': 'n'}> +CONFIG_EXYNOS_AUDSS_CLK_CON policy<{'armhf': 'n'}> +CONFIG_EXYNOS_CHIPID policy<{'armhf': 'n'}> +CONFIG_EXYNOS_CLKOUT policy<{'armhf': 'n'}> +CONFIG_EXYNOS_CPU_SUSPEND policy<{'armhf': 'y'}> +CONFIG_EXYNOS_IOMMU policy<{'armhf': 'n'}> +CONFIG_EXYNOS_IRQ_COMBINER policy<{'armhf': 'y'}> +CONFIG_EXYNOS_MBOX policy<{'armhf': 'm'}> +CONFIG_EXYNOS_PMU policy<{'armhf': 'y'}> +CONFIG_EXYNOS_PMU_ARM_DRIVERS policy<{'armhf': 'y'}> +CONFIG_EXYNOS_PM_DOMAINS policy<{'armhf': 'y'}> +CONFIG_EXYNOS_SROM policy<{'armhf': 'y'}> +CONFIG_EXYNOS_THERMAL policy<{'armhf': 'y'}> +CONFIG_EXYNOS_USI policy<{'armhf': 'n'}> +CONFIG_EZCHIP_NPS_MANAGEMENT_ENET policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_EZX_PCAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_CHECK_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_F2FS_FAULT_INJECTION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_F2FS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_F2FS_FS_COMPRESSION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_LZ4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_LZ4HC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_LZORLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_IOSTAT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_F2FS_STAT_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_UNFAIR_RWSEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F71808E_WDT policy<{'amd64': 'm'}> +CONFIG_FAILOVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FAIR_GROUP_SCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FANOTIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FANOTIFY_ACCESS_PERMISSIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FARSYNC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FAT_DEFAULT_CODEPAGE policy<{'amd64': '437', 'arm64': '437', 'armhf': '437', 'ppc64el': '437', 'riscv64': '437', 's390x': '437'}> +CONFIG_FAT_DEFAULT_IOCHARSET policy<{'amd64': '"iso8859-1"', 'arm64': '"iso8859-1"', 'armhf': '"iso8859-1"', 'ppc64el': '"iso8859-1"', 'riscv64': '"iso8859-1"', 's390x': '"iso8859-1"'}> +CONFIG_FAT_DEFAULT_UTF8 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FAT_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FAULT_INJECTION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FBNIC policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_3DFX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_3DFX_ACCEL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_3DFX_I2C policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_ARC policy<{'amd64': 'm'}> +CONFIG_FB_ARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_ASILIANT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FB_ATY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_ATY128 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_ATY128_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_ATY_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_ATY_CT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_ATY_GENERIC_LCD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_ATY_GX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_CARMINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_CARMINE_DRAM_EVAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_CFB_COPYAREA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FB_CFB_FILLRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FB_CFB_IMAGEBLIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FB_CFB_REV_PIXELS_IN_BYTE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_CIRRUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_CYBER2000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_CYBER2000_DDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_DDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_DEFERRED_IO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_DEVICE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_DMAMEM_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_DMAMEM_HELPERS_DEFERRED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_FOREIGN_ENDIAN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FB_GOLDFISH policy<{'riscv64': 'm'}> +CONFIG_FB_HECUBA policy<{'amd64': 'm'}> +CONFIG_FB_HGA policy<{'amd64': 'm'}> +CONFIG_FB_I740 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_IBM_GXT4500 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FB_IMSTT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FB_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FB_IOMEM_FOPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FB_IOMEM_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_KYRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_MACMODES policy<{'ppc64el': 'm'}> +CONFIG_FB_MATROX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_MATROX_G policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_MATROX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_MATROX_MAVEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_MATROX_MILLENIUM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_MATROX_MYSTIQUE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_MB862XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_MB862XX_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_MB862XX_LIME policy<{'ppc64el': 'n'}> +CONFIG_FB_MB862XX_PCI_GDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_METRONOME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_MODE_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FB_N411 policy<{'amd64': 'm'}> +CONFIG_FB_NEOMAGIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_NOTIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_NVIDIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_NVIDIA_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_NVIDIA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_NVIDIA_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_OF policy<{'ppc64el': 'm'}> +CONFIG_FB_OMAP2 policy<{'armhf': 'm'}> +CONFIG_FB_OMAP2_CONNECTOR_ANALOG_TV policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_CONNECTOR_DVI policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_CONNECTOR_HDMI policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DEBUG_SUPPORT policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DSS policy<{'armhf': 'm'}> +CONFIG_FB_OMAP2_DSS_DEBUG policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DSS_DEBUGFS policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DSS_DPI policy<{'armhf': 'y'}> +CONFIG_FB_OMAP2_DSS_DSI policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DSS_HDMI_COMMON policy<{'armhf': 'y'}> +CONFIG_FB_OMAP2_DSS_INIT policy<{'armhf': 'y'}> +CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK policy<{'armhf': '0'}> +CONFIG_FB_OMAP2_DSS_SDI policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DSS_SLEEP_AFTER_VENC_RESET policy<{'armhf': 'y'}> +CONFIG_FB_OMAP2_DSS_VENC policy<{'armhf': 'y'}> +CONFIG_FB_OMAP2_ENCODER_OPA362 policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_ENCODER_TFP410 policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_ENCODER_TPD12S015 policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_NUM_FBS policy<{'armhf': '3'}> +CONFIG_FB_OMAP2_PANEL_DPI policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_PANEL_LGPHILIPS_LB035Q02 policy<{'armhf': 'n'}> +CONFIG_FB_OMAP4_DSS_HDMI policy<{'armhf': 'y'}> +CONFIG_FB_OMAP5_DSS_HDMI policy<{'armhf': 'n'}> +CONFIG_FB_OPENCORES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_PM2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_PM2_FIFO_DISCONNECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_PM3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA policy<{'arm64': 'y'}> +CONFIG_FB_RADEON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_RADEON_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_RADEON_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_RADEON_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_RIVA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_RIVA_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_RIVA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_RIVA_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_S1D13XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_S3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_S3_DDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_SAVAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_SAVAGE_ACCEL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_SAVAGE_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_SIMPLE policy<{'amd64': '-', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': 'n'}> +CONFIG_FB_SIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_SIS_300 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_SIS_315 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_SM501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_SM712 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_SM750 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_SMSCUFX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_SSD1307 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_SVGALIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_SYSMEM_FOPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_SYSMEM_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_SYSMEM_HELPERS_DEFERRED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_SYS_COPYAREA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_SYS_FILLRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_SYS_IMAGEBLIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_TFT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_TFT_AGM1264K_FL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_BD663474 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_HX8340BN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_HX8347D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_HX8353D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_HX8357D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9163 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9320 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9325 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9340 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9481 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9486 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_PCD8544 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_RA8875 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_S6D02A1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_S6D1121 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SEPS525 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SH1106 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SSD1289 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SSD1305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SSD1306 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SSD1331 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SSD1351 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ST7735R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ST7789V policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_TINYLCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_TLS8204 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_UC1611 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_UC1701 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_UPD161704 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TILEBLITTING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FB_TRIDENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_UDL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_UVESA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_VGA16 policy<{'amd64': 'm', 'ppc64el': '-'}> +CONFIG_FB_VIA policy<{'amd64': 'm'}> +CONFIG_FB_VIA_DIRECT_PROCFS policy<{'amd64': 'n'}> +CONFIG_FB_VIA_X_COMPATIBILITY policy<{'amd64': 'y'}> +CONFIG_FB_VIRTUAL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FB_VOODOO1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_VT8623 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_XILINX policy<{'arm64': 'm'}> +CONFIG_FCOE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FCOE_FNIC policy<{'amd64': 'm'}> +CONFIG_FDDI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FDMA policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FEALNX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FEC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_FHCI_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_FIB_RULES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FILE_LOCKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FIND_BIT_BENCHMARK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FIND_NORMAL_PAGE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_FIPS_SIGNATURE_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FIQ policy<{'armhf': 'y'}> +CONFIG_FIREWIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FIREWIRE_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FIREWIRE_NOSY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FIREWIRE_OHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FIREWIRE_SBP2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FIRMWARE_EDID policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FIRMWARE_MEMMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FIRMWARE_TABLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FIXED_PHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FIX_EARLYCON_MEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_FLATMEM_MANUAL policy<{'armhf': 'n'}> +CONFIG_FM10K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FONTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_10x18 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_6x10 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_6x11 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_6x8 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_7x14 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_8x16 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_8x8 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_ACORN_8x8 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_MINI_4x6 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_PEARL_8x8 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_SUN12x22 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_SUN8x16 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_TER10x18 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_TER16x32 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FORCEDETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FORCE_PCI policy<{'ppc64el': 'y'}> +CONFIG_FORCE_SMP policy<{'ppc64el': 'y'}> +CONFIG_FORTIFY_SOURCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_FPGA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FPGA_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FPGA_DFL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FPGA_DFL_AFU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_EMIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_FME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_FME_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_FME_MGR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_FME_REGION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_M10_BMC_SEC_UPDATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_FPGA_MGR_ALTERA_CVP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FPGA_MGR_ALTERA_PS_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FPGA_MGR_ICE40_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_MGR_MACHXO2_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FPGA_MGR_MICROCHIP_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_MGR_SOCFPGA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FPGA_MGR_SOCFPGA_A10 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FPGA_MGR_STRATIX10_SOC policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_VERSAL_FPGA policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_XILINX_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FPGA_MGR_XILINX_SELECTMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FPGA_MGR_XILINX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FPGA_MGR_ZYNQMP_FPGA policy<{'arm64': 'm'}> +CONFIG_FPGA_REGION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPROBE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FPROBE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FPU policy<{'riscv64': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FRAMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FRAMER_PEF2256 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FRAME_POINTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_FRAME_WARN policy<{'amd64': '1024', 'arm64': '1024', 'armhf': '1024', 'ppc64el': '2048', 'riscv64': '1024', 's390x': '1024'}> +CONFIG_FREEZER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FSCACHE_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_MASTER_ASPEED policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_MASTER_AST_CF policy<{'armhf': 'm'}> +CONFIG_FSI_MASTER_GPIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_MASTER_HUB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_MASTER_I2CR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_NEW_DEV_NODE policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_FSI_OCC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_SBEFIFO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_SCOM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSL_BMAN_TEST policy<{'arm64': 'm'}> +CONFIG_FSL_BMAN_TEST_API policy<{'arm64': 'n'}> +CONFIG_FSL_DPAA policy<{'arm64': 'y'}> +CONFIG_FSL_DPAA2_ETH policy<{'arm64': 'm'}> +CONFIG_FSL_DPAA2_ETH_DCB policy<{'arm64': 'y'}> +CONFIG_FSL_DPAA2_PTP_CLOCK policy<{'arm64': 'm'}> +CONFIG_FSL_DPAA2_QDMA policy<{'arm64': 'm'}> +CONFIG_FSL_DPAA2_SWITCH policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-'}> +CONFIG_FSL_DPAA_CHECKING policy<{'arm64': 'y'}> +CONFIG_FSL_DPAA_ETH policy<{'arm64': 'm'}> +CONFIG_FSL_EDMA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSL_ENETC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ENETC_CORE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ENETC_IERB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ENETC_MDIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ENETC_PTP_CLOCK policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ENETC_QOS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_FSL_ENETC_VF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ERRATUM_A008585 policy<{'arm64': 'y'}> +CONFIG_FSL_FMAN policy<{'arm64': 'y'}> +CONFIG_FSL_GTM policy<{'ppc64el': 'y'}> +CONFIG_FSL_GUTS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_FSL_IFC policy<{'arm64': 'y'}> +CONFIG_FSL_IMX8_DDR_PMU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FSL_IMX9_DDR_PMU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FSL_LBC policy<{'ppc64el': 'y'}> +CONFIG_FSL_MC_BUS policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_FSL_MC_DPIO policy<{'arm64': 'm'}> +CONFIG_FSL_MC_UAPI_SUPPORT policy<{'arm64': 'y'}> +CONFIG_FSL_PQ_MDIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_QDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FSL_QMAN_TEST policy<{'arm64': 'n'}> +CONFIG_FSL_RCPM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_FSL_UCC_HDLC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_XGMAC_MDIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_FSNOTIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_DAX policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_DAX_PMD policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_ENCRYPTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_ENCRYPTION_ALGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_ENCRYPTION_INLINE_CRYPT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_IOMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_MBCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_STACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_VERITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_VERITY_BUILTIN_SIGNATURES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FTGMAC100 policy<{'armhf': 'm'}> +CONFIG_FTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FTMAC100 policy<{'armhf': 'm'}> +CONFIG_FTRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FTRACE_MCOUNT_USE_CC policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY policy<{'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_FTRACE_RECORD_RECURSION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FTRACE_SORT_STARTUP_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 's390x': 'n'}> +CONFIG_FTRACE_STARTUP_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FTRACE_SYSCALLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FTR_FIXUP_SELFTEST policy<{'ppc64el': 'n'}> +CONFIG_FTWDT010_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_FUEL_GAUGE_MM8013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUEL_GAUGE_SC27XX policy<{'arm64': 'm'}> +CONFIG_FUEL_GAUGE_STC3117 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUJITSU_ERRATUM_010001 policy<{'arm64': 'y'}> +CONFIG_FUJITSU_ES policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_FUJITSU_LAPTOP policy<{'amd64': 'm'}> +CONFIG_FUJITSU_TABLET policy<{'amd64': 'm'}> +CONFIG_FUJITSU_UNCORE_PMU policy<{'arm64': 'm'}> +CONFIG_FUNCTION_ALIGNMENT policy<{'amd64': '16', 'arm64': '8', 'armhf': '0', 'ppc64el': '4', 'riscv64': '8', 's390x': '8'}> +CONFIG_FUNCTION_ALIGNMENT_16B policy<{'amd64': 'y'}> +CONFIG_FUNCTION_ALIGNMENT_4B policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FUNCTION_ALIGNMENT_8B policy<{'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_ERROR_INJECTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_GRAPH_RETADDR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_GRAPH_RETVAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_GRAPH_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_PADDING_BYTES policy<{'amd64': '16'}> +CONFIG_FUNCTION_PADDING_CFI policy<{'amd64': '11'}> +CONFIG_FUNCTION_PROFILER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_SELF_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_TRACE_ARGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUN_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUN_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUSE_DAX policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUSE_IO_URING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUSE_PASSTHROUGH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUSION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FUSION_CTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUSION_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FUSION_LAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUSION_LOGGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FUSION_MAX_SGE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128'}> +CONFIG_FUSION_SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FUSION_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FUTEX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUTEX_MPOL policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUTEX_PI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUTEX_PRIVATE_HASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FWCTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FWCTL_BNXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FWCTL_MLX5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FWCTL_PDS policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FWNODE_MDIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FW_ATTR_CLASS policy<{'amd64': 'm'}> +CONFIG_FW_CACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FW_CFG_SYSFS policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_FW_CFG_SYSFS_CMDLINE policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_FW_CS_DSP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FW_LOADER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_COMPRESS_XZ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_COMPRESS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_PAGED_BUF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_USER_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_UPLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FXAS21002C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXAS21002C_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXAS21002C_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXLS8962AF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXLS8962AF_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXLS8962AF_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXOS8700 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXOS8700_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXOS8700_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GACT_PROB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GADGET_UAC1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GADGET_UAC1_LEGACY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_GAMEPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GAMEPORT_EMU10K1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GAMEPORT_FM801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GARP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GART_IOMMU policy<{'amd64': 'y'}> +CONFIG_GCC10_NO_ARRAY_BOUNDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GCC_NO_STRINGOP_OVERFLOW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE policy<{'riscv64': 'y'}> +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS policy<{'arm64': 'y'}> +CONFIG_GCC_VERSION policy<{'amd64': '150200', 'arm64': '150200', 'armhf': '150200', 'ppc64el': '150200', 'riscv64': '150200', 's390x': '150200'}> +CONFIG_GCOV_KERNEL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GDB_SCRIPTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GEHC_PMC_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GEMINI_ETHERNET policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GENDWARFKSYMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_GENERIC_ADC_BATTERY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GENERIC_ADC_THERMAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GENERIC_ALLOCATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_ARCH_NUMA policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_ARCH_TOPOLOGY policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_BUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_BUG_RELATIVE_POINTERS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_CALIBRATE_DELAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST_IDLE policy<{'amd64': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS_COUPLED policy<{'amd64': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS_COUPLED_INLINE policy<{'amd64': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST policy<{'amd64': 'y'}> +CONFIG_GENERIC_CMOS_UPDATE policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_GENERIC_CPU_AUTOPROBE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_GENERIC_CPU_CACHE_MAINTENANCE policy<{'arm64': 'y'}> +CONFIG_GENERIC_CPU_DEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_CPU_VULNERABILITIES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_CSUM policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_EARLY_IOREMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_ENTRY policy<{'amd64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_FRAMER policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_GETTIMEOFDAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_HWEIGHT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_GENERIC_IDLE_POLL_SETUP policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IOMAP policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_GENERIC_IOREMAP policy<{'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_IRQ_CHIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_ENTRY policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_IRQ_IPI policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_IPI_MUX policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_MULTI_HANDLER policy<{'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_PROBE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_GENERIC_IRQ_RESERVATION_MODE policy<{'amd64': 'y'}> +CONFIG_GENERIC_IRQ_SHOW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_SHOW_LEVEL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_ISA_DMA policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_LOCKBREAK policy<{'ppc64el': 'y', 's390x': '-'}> +CONFIG_GENERIC_MSI_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_NET_UTILS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_PCI_IOMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PENDING_IRQ policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_GENERIC_PHY_MIPI_DPHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PINCONF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PINCTRL policy<{'arm64': 'y'}> +CONFIG_GENERIC_PINCTRL_GROUPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PINMUX_FUNCTIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PT policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_SCHED_CLOCK policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_SMP_IDLE_THREAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_STRNCPY_FROM_USER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_STRNLEN_USER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_SYSCALL policy<{'amd64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_TIME_VSYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_VDSO_OVERFLOW_PROTECT policy<{'amd64': 'y'}> +CONFIG_GENEVE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GENKSYMS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_GENWQE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY policy<{'amd64': '0', 'arm64': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_GEN_RTC policy<{'ppc64el': 'y'}> +CONFIG_GET_FREE_REGION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GFS2_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GFS2_FS_LOCKING_DLM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GIANFAR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_GIGABYTE_WMI policy<{'amd64': 'm'}> +CONFIG_GLOB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GNSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GNSS_MTK_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GNSS_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GNSS_SIRF_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GNSS_UBX_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GNSS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GOLDFISH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_GOLDFISH_PIPE policy<{'riscv64': 'm'}> +CONFIG_GOLDFISH_TTY policy<{'riscv64': 'm'}> +CONFIG_GOOGLE_FIRMWARE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GP2AP002 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GP2AP020A00F policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPD_POCKET_FAN policy<{'amd64': 'm'}> +CONFIG_GPIB policy<{'amd64': 'm', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GPIB_AGILENT_82350B policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIB_AGILENT_82357A policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIB_CB7210 policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIB_CEC_PCI policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIB_COMMON policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIB_HP82335 policy<{'amd64': 'm'}> +CONFIG_GPIB_HP82341 policy<{'amd64': 'm'}> +CONFIG_GPIB_INES policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIB_LPVO policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIB_NEC7210 policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIB_NI_PCI_ISA policy<{'amd64': 'm', 'arm64': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIB_NI_USB policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIB_PC2 policy<{'amd64': 'm'}> +CONFIG_GPIB_PCMCIA policy<{'amd64': 'y'}> +CONFIG_GPIB_TMS9914 policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_GPIOLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIOLIB_FASTPATH_LIMIT policy<{'amd64': '512', 'arm64': '512', 'armhf': '512', 'ppc64el': '512', 'riscv64': '512', 's390x': '512'}> +CONFIG_GPIOLIB_IRQCHIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIOLIB_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIO_104_DIO_48E policy<{'amd64': 'm'}> +CONFIG_GPIO_104_IDIO_16 policy<{'amd64': 'm'}> +CONFIG_GPIO_104_IDI_48 policy<{'amd64': 'm'}> +CONFIG_GPIO_74X164 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_74XX_MMIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_ADNP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_ADP5520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_ADP5585 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_AGGREGATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_ALTERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_ALTERA_A10SR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_AMD8111 policy<{'amd64': 'm'}> +CONFIG_GPIO_AMDPT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_AMD_FCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_ARIZONA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_ASPEED policy<{'armhf': 'm'}> +CONFIG_GPIO_ASPEED_SGPIO policy<{'armhf': 'y'}> +CONFIG_GPIO_BD71815 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_BD71828 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_BD72720 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_BD9571MWV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_BLZP1600 policy<{'arm64': 'm'}> +CONFIG_GPIO_BT8XX policy<{'s390x': 'm'}> +CONFIG_GPIO_BY_PINCTRL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_CADENCE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_CDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIO_CGBC policy<{'amd64': 'm'}> +CONFIG_GPIO_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_CRYSTAL_COVE policy<{'amd64': 'y'}> +CONFIG_GPIO_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_DA9055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_DAVINCI policy<{'arm64': 'y'}> +CONFIG_GPIO_DLN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_DS4520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_DWAPB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_EIC_SPRD policy<{'arm64': 'm'}> +CONFIG_GPIO_ELKHARTLAKE policy<{'amd64': 'm'}> +CONFIG_GPIO_EN7523 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_EXAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_F7188X policy<{'amd64': 'm'}> +CONFIG_GPIO_FTGPIO010 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_FXL6408 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_GPIO_GENERIC_PLATFORM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_GPIO_GPIO_MM policy<{'amd64': 'm'}> +CONFIG_GPIO_GRANITERAPIDS policy<{'amd64': 'm'}> +CONFIG_GPIO_GRGPIO policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_GW_PLD policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_HISI policy<{'arm64': 'm'}> +CONFIG_GPIO_HLWD policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_I8255 policy<{'amd64': 'm'}> +CONFIG_GPIO_ICH policy<{'amd64': 'm'}> +CONFIG_GPIO_IDIO_16 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_IMX_SCU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_IT87 policy<{'amd64': 'm'}> +CONFIG_GPIO_JANZ_TTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_KEMPLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LATCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_LINE_MUX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LJCA policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LOGICVC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LP3943 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LP873X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LP87565 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MACSMC policy<{'arm64': 'm'}> +CONFIG_GPIO_MADERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MAX3191X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_MAX7300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_MAX7301 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_MAX730X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MAX732X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_MAX7360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MAX77620 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MAX77650 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MAX77759 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MB86S7X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_MC33880 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_MENZ127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MLXBF policy<{'arm64': 'm'}> +CONFIG_GPIO_MLXBF2 policy<{'arm64': 'm'}> +CONFIG_GPIO_MLXBF3 policy<{'arm64': 'm'}> +CONFIG_GPIO_ML_IOH policy<{'amd64': 'm'}> +CONFIG_GPIO_MOCKUP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GPIO_MOXTET policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MPC8XXX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_MPSSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MSC313 policy<{'armhf': 'y'}> +CONFIG_GPIO_MVEBU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_MXC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_NOVALAKE policy<{'amd64': 'm'}> +CONFIG_GPIO_NPCM_SGPIO policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_OMAP policy<{'armhf': 'y'}> +CONFIG_GPIO_PALMAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_PCA953X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_PCA953X_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_PCA9570 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_PCF857X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_PCIE_IDIO_24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_PCI_IDIO_16 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_PISOSR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_PL061 policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_GPIO_PMIC_EIC_SPRD policy<{'arm64': 'm'}> +CONFIG_GPIO_POLARFIRE_SOC policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_GPIO_PXA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_QIXIS_FPGA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_RC5T583 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_RDA policy<{'armhf': 'y'}> +CONFIG_GPIO_RDC321X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_REGMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_RTD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_SCH policy<{'amd64': 'm'}> +CONFIG_GPIO_SCH311X policy<{'amd64': 'm'}> +CONFIG_GPIO_SHARED policy<{'arm64': 'y'}> +CONFIG_GPIO_SHARED_PROXY policy<{'arm64': 'm'}> +CONFIG_GPIO_SIFIVE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_SIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_SIOX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_SPRD policy<{'arm64': 'm'}> +CONFIG_GPIO_STMPE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_SWNODE_UNDEFINED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_SYSCON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIO_SYSFS_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIO_TANGIER policy<{'amd64': 'm'}> +CONFIG_GPIO_TC3589X policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_TEGRA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_TEGRA186 policy<{'arm64': 'y'}> +CONFIG_GPIO_THUNDERX policy<{'arm64': 'm'}> +CONFIG_GPIO_TN48M_CPLD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_TPIC2810 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_TPS65086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_TPS65218 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_TPS65219 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_TPS6586X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_TPS65910 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_TPS65912 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_TPS68470 policy<{'amd64': 'm'}> +CONFIG_GPIO_TQMX86 policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_TS4800 policy<{'armhf': 'm'}> +CONFIG_GPIO_TS4900 policy<{'armhf': 'm'}> +CONFIG_GPIO_TWL6040 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_USBIO policy<{'amd64': 'm', 'arm64': '-', 'riscv64': '-'}> +CONFIG_GPIO_VF610 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_VIPERBOARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_VIRTUSER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_VISCONTI policy<{'arm64': 'm'}> +CONFIG_GPIO_VX855 policy<{'amd64': 'm'}> +CONFIG_GPIO_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_WCD934X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_WHISKEY_COVE policy<{'amd64': 'm'}> +CONFIG_GPIO_WINBOND policy<{'amd64': 'm'}> +CONFIG_GPIO_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_WM8350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_WM8994 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_WS16C48 policy<{'amd64': 'm'}> +CONFIG_GPIO_XGENE policy<{'arm64': 'y'}> +CONFIG_GPIO_XGENE_SB policy<{'arm64': 'm'}> +CONFIG_GPIO_XILINX policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_GPIO_XLP policy<{'arm64': 'm'}> +CONFIG_GPIO_XRA1403 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_ZEVIO policy<{'armhf': 'y'}> +CONFIG_GPIO_ZYNQ policy<{'arm64': 'm'}> +CONFIG_GPIO_ZYNQMP_MODEPIN policy<{'arm64': 'm'}> +CONFIG_GPU_BUDDY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GP_PCI1XXXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GRACE_PERIOD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GREENASIA_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GREYBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GREYBUS_AUDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_AUDIO_APB_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_BEAGLEPLAY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_BOOTROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_BRIDGED_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_ES2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_FIRMWARE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_LIGHT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_LOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_LOOPBACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_VIBRATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GROUP_SCHED_BANDWIDTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GROUP_SCHED_WEIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GRO_CELLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GUEST_PERF_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_GUP_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GVE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_GXP_TIMER policy<{'armhf': 'y'}> +CONFIG_GXP_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_HALTPOLL_CPUIDLE policy<{'amd64': 'm'}> +CONFIG_HANGCHECK_TIMER policy<{'amd64': 'm', 'ppc64el': 'm', 's390x': 'm'}> +CONFIG_HAPPYMEAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HARDENED_USERCOPY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HARDENED_USERCOPY_DEFAULT_ON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HARDEN_BRANCH_HISTORY policy<{'armhf': 'y'}> +CONFIG_HARDEN_BRANCH_PREDICTOR policy<{'armhf': 'y'}> +CONFIG_HARDIRQS_SW_RESEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HARDLOCKUP_CHECK_TIMESTAMP policy<{'amd64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR_ARCH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n'}> +CONFIG_HARDLOCKUP_DETECTOR_BUDDY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR_COUNTS_HRTIMER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR_PERF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_HARDLOCKUP_DETECTOR_PREFER_BUDDY policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_HAS_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAS_IOMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAS_IOPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAS_IOPORT_MAP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAS_SECURITY_AUDIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_64BIT_ALIGNED_ACCESS policy<{'riscv64': 'y'}> +CONFIG_HAVE_ACPI_APEI policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_HAVE_ACPI_APEI_NMI policy<{'amd64': 'y'}> +CONFIG_HAVE_ALIGNED_STRUCT_PAGE policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_AUDITSYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_BITREVERSE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES policy<{'amd64': 'y'}> +CONFIG_HAVE_ARCH_COMPILER_H policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_GET_SECUREBOOT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_HUGE_VMALLOC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_HUGE_VMAP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_JUMP_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KASAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KASAN_HW_TAGS policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KASAN_SW_TAGS policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KASAN_VMALLOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KCSAN policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KFENCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KGDB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT policy<{'riscv64': 'y'}> +CONFIG_HAVE_ARCH_KMSAN policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KSTACK_ERASE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_MMAP_RND_BITS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-'}> +CONFIG_HAVE_ARCH_NODE_DEV_GROUP policy<{'amd64': 'y'}> +CONFIG_HAVE_ARCH_NVRAM_OPS policy<{'ppc64el': 'y'}> +CONFIG_HAVE_ARCH_PFN_VALID policy<{'armhf': 'y'}> +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_SECCOMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_SECCOMP_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_SOFT_DIRTY policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_TLB_REMOVE_TABLE policy<{'ppc64el': 'y'}> +CONFIG_HAVE_ARCH_TRACEHOOK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_USERFAULTFD_MINOR policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_USERFAULTFD_WP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_VMAP_STACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_ARM_ARCH_TIMER policy<{'armhf': 'y'}> +CONFIG_HAVE_ARM_SCU policy<{'armhf': 'y'}> +CONFIG_HAVE_ARM_SMCCC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HAVE_ARM_SMCCC_DISCOVERY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HAVE_ARM_TWD policy<{'armhf': 'y'}> +CONFIG_HAVE_ASM_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_BOOTMEM_INFO_NODE policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 's390x': 'y'}> +CONFIG_HAVE_CALL_THUNKS policy<{'amd64': 'y'}> +CONFIG_HAVE_CLK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_CLK_PREPARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_CMPXCHG_DOUBLE policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_HAVE_CMPXCHG_LOCAL policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_HAVE_CONTEXT_TRACKING_USER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_CONTEXT_TRACKING_USER_OFFSTACK policy<{'amd64': 'y'}> +CONFIG_HAVE_C_RECORDMCOUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_DEBUG_KMEMLEAK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_DEBUG_STACKOVERFLOW policy<{'ppc64el': 'y'}> +CONFIG_HAVE_DMA_CONTIGUOUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE policy<{'amd64': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS policy<{'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_JMP policy<{'amd64': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_EBPF_JIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_EXIT_THREAD policy<{'amd64': 'y', 'armhf': 'y'}> +CONFIG_HAVE_EXTRA_IPI_TRACEPOINTS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HAVE_FENTRY policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FTRACE_GRAPH_FUNC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FTRACE_REGS_HAVING_PT_REGS policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FUNCTION_ERROR_INJECTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FUNCTION_GRAPH_FREGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FUNCTION_GRAPH_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FUNCTION_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_GCC_PLUGINS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_GENERIC_TIF_BITS policy<{'amd64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_GENERIC_VDSO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_GIGANTIC_FOLIOS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_GUP_FAST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_HARDLOCKUP_DETECTOR_ARCH policy<{'ppc64el': 'y'}> +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_HW_BREAKPOINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_IMA_KEXEC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_IMX_ANATOP policy<{'armhf': 'y'}> +CONFIG_HAVE_IMX_GPC policy<{'armhf': 'y'}> +CONFIG_HAVE_IMX_MMDC policy<{'armhf': 'y'}> +CONFIG_HAVE_IMX_SRC policy<{'armhf': 'y'}> +CONFIG_HAVE_INTEL_TXT policy<{'amd64': 'y'}> +CONFIG_HAVE_IOREMAP_PROT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK policy<{'amd64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_IRQ_TIME_ACCOUNTING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_JUMP_LABEL_HACK policy<{'amd64': 'y'}> +CONFIG_HAVE_KCSAN_COMPILER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_BZIP2 policy<{'amd64': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_GZIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_LZ4 policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_LZMA policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_LZO policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_UNCOMPRESSED policy<{'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_XZ policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KLP_BUILD policy<{'amd64': 'y'}> +CONFIG_HAVE_KPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KPROBES_ON_FTRACE policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KRETPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KVM_ARCH_GMEM_INVALIDATE policy<{'amd64': 'y'}> +CONFIG_HAVE_KVM_ARCH_GMEM_POPULATE policy<{'amd64': 'y'}> +CONFIG_HAVE_KVM_ARCH_GMEM_PREPARE policy<{'amd64': 'y'}> +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KVM_DIRTY_RING policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_KVM_DIRTY_RING_TSO policy<{'amd64': 'y', 'arm64': '-'}> +CONFIG_HAVE_KVM_INVALID_WAKEUPS policy<{'s390x': 'y'}> +CONFIG_HAVE_KVM_IRQCHIP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KVM_IRQ_BYPASS policy<{'amd64': 'm', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_KVM_IRQ_ROUTING policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KVM_MSI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_KVM_NO_POLL policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KVM_PFNCACHE policy<{'amd64': 'y'}> +CONFIG_HAVE_KVM_PM_NOTIFIER policy<{'amd64': 'y'}> +CONFIG_HAVE_KVM_READONLY_MEM policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE policy<{'arm64': 'y'}> +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_LIVEPATCH policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_MARCH_Z10_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MARCH_Z13_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MARCH_Z14_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MARCH_Z15_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MARCH_Z196_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MARCH_ZEC12_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MEMBLOCK_PHYS_MAP policy<{'s390x': 'y'}> +CONFIG_HAVE_MEMORYLESS_NODES policy<{'ppc64el': 'y'}> +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS policy<{'amd64': 'y'}> +CONFIG_HAVE_MMIOTRACE_SUPPORT policy<{'amd64': 'y'}> +CONFIG_HAVE_MOD_ARCH_SPECIFIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_MOVE_PMD policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_MOVE_PUD policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_NMI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_NOINSTR_HACK policy<{'amd64': 'y'}> +CONFIG_HAVE_NOINSTR_VALIDATION policy<{'amd64': 'y'}> +CONFIG_HAVE_NOP_MCOUNT policy<{'s390x': 'y'}> +CONFIG_HAVE_OBJTOOL policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_OBJTOOL_MCOUNT policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_OBJTOOL_NOP_MCOUNT policy<{'amd64': 'y'}> +CONFIG_HAVE_OPTPROBES policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_PAGE_SIZE_4KB policy<{'amd64': 'y', 'arm64-generic': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PAGE_SIZE_64KB policy<{'arm64-generic-64k': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PCSPKR_PLATFORM policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_PERF_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PERF_EVENTS_NMI policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_PERF_REGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PERF_USER_STACK_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PNETID policy<{'s390x': 'm'}> +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PREEMPT_DYNAMIC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PREEMPT_DYNAMIC_CALL policy<{'amd64': 'y'}> +CONFIG_HAVE_PREEMPT_DYNAMIC_KEY policy<{'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PROC_CPU policy<{'armhf': 'y'}> +CONFIG_HAVE_PV_STEAL_CLOCK_GEN policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_PWRCTRL policy<{'arm64': 'y'}> +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_RELIABLE_STACKTRACE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_RETHOOK policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_RSEQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_RUST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_SCHED_AVG_IRQ policy<{'ppc64el': 'y'}> +CONFIG_HAVE_SETUP_PER_CPU_AREA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_SHARED_GPIOS policy<{'arm64': 'y'}> +CONFIG_HAVE_SINGLE_FTRACE_DIRECT_OPS policy<{'amd64': 'y'}> +CONFIG_HAVE_SMP policy<{'armhf': 'y'}> +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_STACKPROTECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_STACK_VALIDATION policy<{'amd64': 'y'}> +CONFIG_HAVE_STATIC_CALL policy<{'amd64': 'y'}> +CONFIG_HAVE_STATIC_CALL_INLINE policy<{'amd64': 'y'}> +CONFIG_HAVE_SYSCALL_TRACEPOINTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_TRUSTED_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_UACCESS_VALIDATION policy<{'amd64': 'y'}> +CONFIG_HAVE_UID16 policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 's390x': '-'}> +CONFIG_HAVE_UNSTABLE_SCHED_CLOCK policy<{'amd64': 'y'}> +CONFIG_HAVE_UNWIND_USER_FP policy<{'amd64': 'y'}> +CONFIG_HAVE_USER_RETURN_NOTIFIER policy<{'amd64': 'y'}> +CONFIG_HAVE_VIRT_CPU_ACCOUNTING policy<{'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_IDLE policy<{'s390x': 'y'}> +CONFIG_HA_MON_EVENTS_ID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HBMC_AM654 policy<{'arm64': 'm'}> +CONFIG_HCALL_STATS policy<{'ppc64el': 'n'}> +CONFIG_HD44780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HD44780_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDC100X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDC2010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDC3020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HDLC_CISCO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC_FR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC_PPP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC_RAW_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC_X25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDMI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HDMI_LPE_AUDIO policy<{'amd64': 'm'}> +CONFIG_HDQ_MASTER_OMAP policy<{'armhf': 'm'}> +CONFIG_HEADERS_INSTALL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_HFI1_DEBUG_SDMA_ORDER policy<{'amd64': 'n'}> +CONFIG_HFSPLUS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HI13X1_GMAC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HI3660_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HI6220_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HI6421V600_IRQ policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HI8435 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HIBERNATE_CALLBACKS policy<{'amd64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HIBERNATION_COMP_LZ4 policy<{'amd64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_HIBERNATION_COMP_LZO policy<{'amd64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HIBERNATION_DEF_COMP policy<{'amd64': '"lzo"', 'armhf': '"lzo"', 'riscv64': '"lzo"'}> +CONFIG_HIBERNATION_SNAPSHOT_DEV policy<{'amd64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HIBMCGE policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HIDRAW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_HID_A4TECH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ACCUTOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_ACRUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ACRUX_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_ALPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_APPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_APPLEIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_APPLETB_BL policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_HID_APPLETB_KBD policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_HID_ASUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_AUREAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_BATTERY_STRENGTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_HID_BELKIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_BETOP_FF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_BIGBEN_FF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_BPF policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_CHERRY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_CHICONY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_CMEDIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_CORSAIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_COUGAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_CP2112 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_CREATIVE_SB0540 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_CYPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_DRAGONRISE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ELAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_ELECOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ELO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_EMS_FF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_EVISION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_EZKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_FT260 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_GEMBIRD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_GFRM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_GLORIOUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_GOODIX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_GOOGLE_HAMMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_HID_GOOGLE_STADIA_FF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_GREENASIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_GT683R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_GYRATION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_HAPTIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_HOLTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_HUAWEI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_HYPERV_MOUSE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HID_ICADE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_JABRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_KENSINGTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_KEYTOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_KYE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_KYSONA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_LCPOWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_LED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_LENOVO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_LENOVO_GO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_LENOVO_GO_S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_LETSKETCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_LOGITECH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_LOGITECH_DJ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_LOGITECH_HIDPP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_MACALLY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MAGICMOUSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MALTRON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MAYFLASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MCP2200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_MCP2221 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_MEGAWORLD_FF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_MICROSOFT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MONTEREY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MULTITOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_NINTENDO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_NTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_NTRIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_NVIDIA_SHIELD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_ORTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PANTHERLORD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PENMOUNT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_PETALYNX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PICOLCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PICOLCD_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PICOLCD_CIR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PICOLCD_FB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PICOLCD_LCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PICOLCD_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PLANTRONICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PLAYSTATION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_PRIMAX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PRODIKEYS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_PXRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_RAPOO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_RAZER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_REDRAGON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_RETRODE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_RMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ROCCAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SAITEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SAMSUNG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SEMITEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SENSOR_ACCEL_3D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_ALS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_CUSTOM_SENSOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_DEVICE_ROTATION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_GYRO_3D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_HUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SENSOR_HUMIDITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_IIO_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_IIO_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_INCLINOMETER_3D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_MAGNETOMETER_3D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_PRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_PROX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_TEMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SIGMAMICRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SMARTJOYPLUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SONY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SPEEDLINK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_STEAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_STEELSERIES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SUNPLUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HID_THINGM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_THRUSTMASTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_TIVO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_TOPRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_TOPSEED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_TWINHAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_U2FZERO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_UCLOGIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_UDRAW_PS3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_UNIVERSAL_PIDFF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_VIEWSONIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_VIVALDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_VIVALDI_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_VRC2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_WACOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_WALTOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_WIIMOTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_WINWING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_XIAOMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_XINMO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ZEROPLUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ZYDACRON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HIGHMEM policy<{'armhf': 'y'}> +CONFIG_HIGHPTE policy<{'armhf': 'y'}> +CONFIG_HIGH_RES_TIMERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HINIC policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HINIC3 policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HIP04_ETH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HISILICON_ERRATUM_161010101 policy<{'arm64': 'y'}> +CONFIG_HISILICON_ERRATUM_161600802 policy<{'arm64': 'y'}> +CONFIG_HISILICON_ERRATUM_162100801 policy<{'arm64': 'y'}> +CONFIG_HISILICON_IRQ_MBIGEN policy<{'arm64': 'y'}> +CONFIG_HISILICON_LPC policy<{'arm64': 'y'}> +CONFIG_HISI_ACC_VFIO_PCI policy<{'arm64': 'm'}> +CONFIG_HISI_DMA policy<{'arm64': 'n', 'armhf': 'm'}> +CONFIG_HISI_FEMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HISI_HIKEY_USB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'n'}> +CONFIG_HISI_PCIE_PMU policy<{'arm64': 'm'}> +CONFIG_HISI_PMU policy<{'arm64': 'm'}> +CONFIG_HISI_PTT policy<{'arm64': 'm'}> +CONFIG_HISI_SOC_HHA policy<{'arm64': 'm'}> +CONFIG_HISI_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HIST_TRIGGERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HIST_TRIGGERS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_HIX5HD2_GMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HL_HLDIO policy<{'amd64': 'y'}> +CONFIG_HMC425 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HMC6352 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HMC_DRV policy<{'s390x': 'm'}> +CONFIG_HMEM_REPORTING policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HMM_MIRROR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HNS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS3_DCB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HNS3_ENET policy<{'arm64': 'm'}> +CONFIG_HNS3_HCLGE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS3_HCLGEVF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS3_PMU policy<{'arm64': 'm'}> +CONFIG_HNS_DSAF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS_ENET policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS_MDIO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HOLTEK_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_CORE_SYNC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_CORE_SYNC_DEAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_CORE_SYNC_FULL policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_CPU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HOTPLUG_PARALLEL policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HOTPLUG_PCI_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_PCI_ACPI_AMPERE_ALTRA policy<{'arm64': 'm'}> +CONFIG_HOTPLUG_PCI_ACPI_IBM policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_HOTPLUG_PCI_CPCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HOTPLUG_PCI_CPCI_GENERIC policy<{'amd64': 'm'}> +CONFIG_HOTPLUG_PCI_CPCI_ZT5550 policy<{'amd64': 'm'}> +CONFIG_HOTPLUG_PCI_OCTEONEP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HOTPLUG_PCI_POWERNV policy<{'ppc64el': 'm'}> +CONFIG_HOTPLUG_PCI_RPA policy<{'ppc64el': 'm'}> +CONFIG_HOTPLUG_PCI_RPA_DLPAR policy<{'ppc64el': 'm'}> +CONFIG_HOTPLUG_PCI_S390 policy<{'s390x': 'y'}> +CONFIG_HOTPLUG_SMT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HOTPLUG_SPLIT_STARTUP policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_HP03 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HP206C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HPET policy<{'amd64': 'y'}> +CONFIG_HPET_EMULATE_RTC policy<{'amd64': 'y'}> +CONFIG_HPET_MMAP policy<{'amd64': 'y'}> +CONFIG_HPET_MMAP_DEFAULT policy<{'amd64': 'y'}> +CONFIG_HPET_TIMER policy<{'amd64': 'y'}> +CONFIG_HPFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HPWDT_NMI_DECODING policy<{'amd64': 'y'}> +CONFIG_HP_ACCEL policy<{'amd64': 'm'}> +CONFIG_HP_BIOSCFG policy<{'amd64': 'm'}> +CONFIG_HP_ILO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HP_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HP_WMI policy<{'amd64': 'm'}> +CONFIG_HRTIMER_REARM_DEFERRED policy<{'amd64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HSA_AMD policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HSA_AMD_SVM policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HSC030PA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HSC030PA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HSC030PA_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HSI_BOARDINFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HSI_CHAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HSR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HT16K33 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HTC_EGPIO policy<{'armhf': 'y'}> +CONFIG_HTE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_HTE_TEGRA194 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HTE_TEGRA194_TEST policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HTMDUMP policy<{'ppc64el': 'm'}> +CONFIG_HTS221 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HTS221_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HTS221_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HTU21 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HUAWEI_WMI policy<{'amd64': 'm'}> +CONFIG_HUGETLBFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HUGETLB_PAGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP policy<{'amd64': 'y', 'arm64': '-', 'riscv64': 'y', 's390x': '-'}> +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON policy<{'amd64': 'n', 'arm64': '-', 'riscv64': 'n', 's390x': '-'}> +CONFIG_HUGETLB_PAGE_SIZE_VARIABLE policy<{'ppc64el': 'y'}> +CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING policy<{'amd64': 'y', 'arm64-generic': 'y', 'riscv64': 'y'}> +CONFIG_HVCS policy<{'ppc64el': 'm'}> +CONFIG_HVC_CONSOLE policy<{'ppc64el': 'y'}> +CONFIG_HVC_DCC policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_HVC_DRIVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HVC_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_HVC_IUCV policy<{'s390x': 'y'}> +CONFIG_HVC_OLD_HVSI policy<{'ppc64el': 'y'}> +CONFIG_HVC_OPAL policy<{'ppc64el': 'y'}> +CONFIG_HVC_RTAS policy<{'ppc64el': 'y'}> +CONFIG_HVC_XEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_HVC_XEN_FRONTEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_HV_PERF_CTRS policy<{'ppc64el': 'y'}> +CONFIG_HWLAT_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HWMON_DEBUG_CHIP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_HWMON_VID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HWPOISON_INJECT policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm'}> +CONFIG_HWSPINLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HWSPINLOCK_OMAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HWSPINLOCK_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HWSPINLOCK_SPRD policy<{'arm64': 'm'}> +CONFIG_HWSPINLOCK_SUN6I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_HW_PERF_EVENTS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HW_RANDOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HW_RANDOM_AIROHA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_AMD policy<{'amd64': 'm'}> +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_ATMEL policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_BA431 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_HW_RANDOM_CAVIUM policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_CCTRNG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_HW_RANDOM_CN10K policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_EXYNOS policy<{'armhf': 'n'}> +CONFIG_HW_RANDOM_HISI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_HISTB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_IMX_RNGC policy<{'armhf': 'm'}> +CONFIG_HW_RANDOM_INTEL policy<{'amd64': 'm'}> +CONFIG_HW_RANDOM_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_MTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_NPCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_OMAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_OPTEE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_POLARFIRE_SOC policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_POWERNV policy<{'ppc64el': 'm'}> +CONFIG_HW_RANDOM_PSERIES policy<{'ppc64el': 'm'}> +CONFIG_HW_RANDOM_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HW_RANDOM_S390 policy<{'s390x': 'm'}> +CONFIG_HW_RANDOM_STM32 policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_TIMERIOMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HW_RANDOM_TPM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HW_RANDOM_VIA policy<{'amd64': 'm'}> +CONFIG_HW_RANDOM_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_HW_RANDOM_XGENE policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_XIPHERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HX711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HX9023S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HYPERV policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_HYPERVISOR_GUEST policy<{'amd64': 'y'}> +CONFIG_HYPERV_BALLOON policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_IOMMU policy<{'amd64': 'y'}> +CONFIG_HYPERV_KEYBOARD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_NET policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_STORAGE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_TESTING policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_HYPERV_TIMER policy<{'amd64': 'y'}> +CONFIG_HYPERV_UTILS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_VMBUS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_VSOCKETS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_VTL_MODE policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_HZ policy<{'amd64': '1000', 'arm64': '1000', 'armhf': '250', 'ppc64el': '250', 'riscv64': '250', 's390x': '100'}> +CONFIG_HZ_200 policy<{'armhf': 'n'}> +CONFIG_HZ_300 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_HZ_500 policy<{'armhf': 'n'}> +CONFIG_HZ_FIXED policy<{'armhf': '0'}> +CONFIG_HZ_PERIODIC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_I2CR_SCOM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_ALGOBIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_ALGOPCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_ALI1535 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_ALI1563 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_ALI15X3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_ALTERA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_AMD756 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_AMD8111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_AMD_ASF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_AMD_MP2 policy<{'amd64': 'm', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_I2C_APPLE policy<{'arm64': 'm'}> +CONFIG_I2C_ARB_GPIO_CHALLENGE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_ASPEED policy<{'armhf': 'm'}> +CONFIG_I2C_AT91 policy<{'arm64': 'm'}> +CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL policy<{'arm64': 'n'}> +CONFIG_I2C_ATR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_AXXIA policy<{'armhf': 'm'}> +CONFIG_I2C_BOARDINFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_I2C_CADENCE policy<{'arm64': 'n', 'riscv64': 'm'}> +CONFIG_I2C_CBUS_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_CCGX_UCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_CGBC policy<{'amd64': 'm'}> +CONFIG_I2C_CHT_WC policy<{'amd64': 'm'}> +CONFIG_I2C_CP2615 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_CROS_EC_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_DEBUG_ALGO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_I2C_DEBUG_BUS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_I2C_DEBUG_CORE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_I2C_DEMUX_PINCTRL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_DESIGNWARE_AMDISP policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_I2C_DESIGNWARE_BAYTRAIL policy<{'amd64': 'y'}> +CONFIG_I2C_DESIGNWARE_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_I2C_DESIGNWARE_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_DESIGNWARE_PLATFORM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_I2C_DIOLAN_U2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_DLN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_EMEV2 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_I2C_EXYNOS5 policy<{'armhf': 'n'}> +CONFIG_I2C_FSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_GPIO_FAULT_INJECTOR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_I2C_GXP policy<{'armhf': 'm'}> +CONFIG_I2C_HELPER_AUTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_I2C_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HID_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HID_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HID_OF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HID_OF_ELAN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HID_OF_GOODIX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HISI policy<{'arm64': 'm'}> +CONFIG_I2C_HIX5HD2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_I801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_I801_MUX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_I2C_IMX policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_I2C_IMX_LPI2C policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_ISCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_ISMT policy<{'amd64': 'm'}> +CONFIG_I2C_KEBA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_I2C_KEMPLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_LJCA policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_I2C_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_MLXBF policy<{'arm64': 'm'}> +CONFIG_I2C_MLXCPLD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_I2C_MPC policy<{'ppc64el': 'm'}> +CONFIG_I2C_MT65XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_MT7621 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_MUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_I2C_MUX_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MUX_GPMUX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_MUX_LTC4306 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MUX_MLXCPLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MUX_MULE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_MUX_PCA9541 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MUX_PCA954x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MUX_PINCTRL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_MUX_REG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MV64XXX policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_I2C_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_NFORCE2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_NOMADIK policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_I2C_NPCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_NVIDIA_GPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_OCORES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_OMAP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_I2C_OPAL policy<{'ppc64el': 'y'}> +CONFIG_I2C_OWL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_PARPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_PCA_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_PCI1XXXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_PIIX4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_PXA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_PXA_SLAVE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_I2C_QCOM_CCI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_QCOM_GENI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_QUP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_RIIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_RK3X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_ROBOTFUZZ_OSIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_RZV2M policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_S3C2410 policy<{'armhf': 'n'}> +CONFIG_I2C_SCMI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SH_MOBILE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_SI470X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SI4713 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SIMTEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_SIS5595 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_SIS630 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_SIS96X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_SLAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_I2C_SLAVE_EEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SLAVE_TESTUNIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SMBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SPRD policy<{'arm64': 'y'}> +CONFIG_I2C_STM32F4 policy<{'arm64': 'm'}> +CONFIG_I2C_STM32F7 policy<{'arm64': 'm'}> +CONFIG_I2C_STUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_I2C_SYNQUACER policy<{'arm64': 'm'}> +CONFIG_I2C_TAOS_EVM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_TEGRA_BPMP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_THUNDERX policy<{'arm64': 'm'}> +CONFIG_I2C_TINY_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_USBIO policy<{'amd64': 'm', 'arm64': '-', 'riscv64': '-'}> +CONFIG_I2C_VERSATILE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_VIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_VIAPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_VIPERBOARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_XGENE_SLIMPRO policy<{'arm64': 'm'}> +CONFIG_I2C_XILINX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_XLP9XX policy<{'arm64': 'm'}> +CONFIG_I2C_ZHAOXIN policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_I3C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I3C_OR_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_I40E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I40EVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I40E_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_I6300ESB_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I8253_LOCK policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_I8254 policy<{'amd64': 'm'}> +CONFIG_I8K policy<{'amd64': 'y'}> +CONFIG_IA32_EMULATION policy<{'amd64': 'y'}> +CONFIG_IA32_EMULATION_DEFAULT_DISABLED policy<{'amd64': 'n'}> +CONFIG_IA32_FEAT_CTL policy<{'amd64': 'y'}> +CONFIG_IAQCORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IAVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IB700_WDT policy<{'amd64': 'm'}> +CONFIG_IBMASR policy<{'amd64': 'm'}> +CONFIG_IBMVETH policy<{'ppc64el': 'm'}> +CONFIG_IBMVIO policy<{'ppc64el': 'y'}> +CONFIG_IBMVMC policy<{'ppc64el': 'm'}> +CONFIG_IBM_ASM policy<{'amd64': 'm'}> +CONFIG_IBM_BSR policy<{'ppc64el': 'm'}> +CONFIG_IBM_PARTITION policy<{'s390x': 'y'}> +CONFIG_IBM_RTL policy<{'amd64': 'm'}> +CONFIG_ICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ICE_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ICE_HWTS policy<{'amd64': 'y'}> +CONFIG_ICE_SWITCHDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ICP10100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ICPLUS_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ICS932S401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IDEAPAD_LAPTOP policy<{'amd64': 'm'}> +CONFIG_IDLE_INJECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IDPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IDPF_SINGLEQ policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IE6XX_WDT policy<{'amd64': 'm'}> +CONFIG_IEEE802154 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IEEE802154_6LOWPAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_ADF7242 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_AT86RF230 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_ATUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_CA8210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_CA8210_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IEEE802154_CC2520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_DRIVERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_FAKELB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_HWSIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_MCR20A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_MRF24J40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_NL802154_EXPERIMENTAL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_IEEE802154_SOCKET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IFB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IFCVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IGB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IGBVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IGB_DCA policy<{'amd64': 'y'}> +CONFIG_IGB_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IGC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IGC_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IGH_ECAT_ENABLE_EOE policy<{'amd64': 'y', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_IGH_ECAT_GENERIC_DEVICE policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_IIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IIO_ADC_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ADIS_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ADIS_LIB_BUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IIO_BACKEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_BUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IIO_BUFFER_CB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_BUFFER_DMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_BUFFER_DMAENGINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_BUFFER_HW_CONSUMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_CONFIGFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_CONSUMERS_PER_TRIGGER policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2'}> +CONFIG_IIO_CROS_EC_ACCEL_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_ACTIVITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_BARO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_LIGHT_PROX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_SENSORS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_SENSORS_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_GTS_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_HRTIMER_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_INTERRUPT_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_INV_SENSORS_TIMESTAMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_KFIFO_BUF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_KX022A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_KX022A_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_KX022A_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_MS_SENSORS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_MUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_RESCALE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_SIMPLE_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SSP_SENSORHUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SSP_SENSORS_COMMONS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_STM32_LPTIMER_TRIGGER policy<{'arm64': 'm'}> +CONFIG_IIO_STM32_TIMER_TRIGGER policy<{'arm64': 'm'}> +CONFIG_IIO_ST_ACCEL_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_ACCEL_I2C_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_ACCEL_SPI_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_GYRO_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_GYRO_I2C_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_GYRO_SPI_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM6DSX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM6DSX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM6DSX_I3C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM6DSX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM9DS0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM9DS0_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM9DS0_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_MAGN_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_MAGN_I2C_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_MAGN_SPI_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_PRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_PRESS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_PRESS_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_SENSORS_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_SENSORS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_SENSORS_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SW_DEVICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SW_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SYSFS_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_TIGHTLOOP_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_TRIGGER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IIO_TRIGGERED_BUFFER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_TRIGGERED_EVENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IKCONFIG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IKHEADERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ILLEGAL_POINTER_VALUE policy<{'amd64': '0xdead000000000000', 'arm64': '0xdead000000000000', 'ppc64el': '0x5deadbeef0000000', 'riscv64': '0xdead000000000000', 's390x': '0xdead000000000000'}> +CONFIG_IMA_APPRAISE_BOOTPARAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_APPRAISE_BUILD_POLICY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_APPRAISE_MODSIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_BLACKLIST_KEYRING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_DEFAULT_HASH policy<{'amd64': '"sha256"', 'arm64': '"sha256"', 'armhf': '"sha256"', 'ppc64el': '"sha256"', 'riscv64': '"sha256"', 's390x': '"sha256"'}> +CONFIG_IMA_DEFAULT_HASH_SHA1 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_DEFAULT_HASH_SHA512 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_DEFAULT_TEMPLATE policy<{'amd64': '"ima-ng"', 'arm64': '"ima-ng"', 'armhf': '"ima-ng"', 'ppc64el': '"ima-sig"', 'riscv64': '"ima-ng"', 's390x': '"ima-ng"'}> +CONFIG_IMA_DISABLE_HTABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_KEXEC_EXTRA_MEMORY_KB policy<{'amd64': '0', 'arm64': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_IMA_LOAD_X509 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_LSM_RULES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_MEASURE_PCR_IDX policy<{'amd64': '10', 'arm64': '10', 'armhf': '10', 'ppc64el': '10', 'riscv64': '10', 's390x': '10'}> +CONFIG_IMA_NG_TEMPLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': '-', 's390x': '-'}> +CONFIG_IMG_ASCII_LCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IMX2_WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX7D_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX7ULP_WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX8MM_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX8M_BLK_CTRL policy<{'arm64': 'y'}> +CONFIG_IMX8QXP_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX91_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX93_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX9_BLK_CTRL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_AIPSTZ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_DSP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_DSP_REMOTEPROC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_GPCV2 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_GPCV2_PM_DOMAINS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_INTMUX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_IPUV3_CORE policy<{'armhf': 'm'}> +CONFIG_IMX_IRQSTEER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_MU_MSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_REMOTEPROC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCMI_BBM_EXT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_SCMI_CPU_DRV policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCMI_CPU_EXT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCMI_LMM_DRV policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCMI_LMM_EXT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCMI_MISC_DRV policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_IMX_SCMI_MISC_EXT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_SCU_PD policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_SC_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SC_WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_WEIM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INA2XX_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INDIRECT_PIO policy<{'arm64': 'y'}> +CONFIG_INET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INET6_AH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET6_ESP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET6_ESPINTCP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INET6_ESP_OFFLOAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET6_IPCOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET6_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET6_XFRM_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_AH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_DIAG_DESTROY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INET_ESP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_ESPINTCP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INET_ESP_OFFLOAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_IPCOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_MPTCP_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_PSP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INET_RAW_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_SCTP_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_TABLE_PERTURB_ORDER policy<{'amd64': '16', 'arm64': '16', 'armhf': '16', 'ppc64el': '16', 'riscv64': '16', 's390x': '16'}> +CONFIG_INET_TCP_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_UDP_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_XFRM_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINEON_TLV493D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_ADDR_TRANS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_BNG_RE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_BNXT_RE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_CXGB4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_EFA policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_ERDMA policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INFINIBAND_HFI1 policy<{'amd64': 'm'}> +CONFIG_INFINIBAND_HNS_HIP08 policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_IONIC policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_IPOIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_IPOIB_CM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_IPOIB_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INFINIBAND_IRDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_ISER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_ISERT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_MTHCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_MTHCA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INFINIBAND_OCRDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INFINIBAND_ON_DEMAND_PAGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_QEDR policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_RDMAVT policy<{'amd64': 'm'}> +CONFIG_INFINIBAND_RTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_RTRS_CLIENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_RTRS_SERVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_SRP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_SRPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_USER_ACCESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_USER_MAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_USER_MEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_USNIC policy<{'amd64': 'm'}> +CONFIG_INFINIBAND_VIRT_DMA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_VMWARE_PVRDMA policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INFTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INITRAMFS_PRESERVE_MTIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INITRAMFS_SOURCE policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_INIT_ENV_ARG_LIMIT policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32', 's390x': '32'}> +CONFIG_INIT_ON_ALLOC_DEFAULT_ON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INIT_ON_FREE_DEFAULT_ON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INIT_STACK_ALL_PATTERN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INIT_STACK_ALL_ZERO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INIT_STACK_NONE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INLINE_READ_LOCK policy<{'s390x': 'y'}> +CONFIG_INLINE_READ_LOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_READ_LOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_INLINE_READ_LOCK_IRQSAVE policy<{'s390x': 'y'}> +CONFIG_INLINE_READ_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_INLINE_READ_UNLOCK policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_INLINE_READ_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_READ_UNLOCK_IRQ policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_INLINE_READ_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_LOCK policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_LOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_LOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_LOCK_IRQSAVE policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_TRYLOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_UNLOCK_IRQ policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_INLINE_WRITE_LOCK policy<{'s390x': 'y'}> +CONFIG_INLINE_WRITE_LOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_WRITE_LOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_INLINE_WRITE_LOCK_IRQSAVE policy<{'s390x': 'y'}> +CONFIG_INLINE_WRITE_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_INLINE_WRITE_UNLOCK policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_INLINE_WRITE_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_WRITE_UNLOCK_IRQ policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_INOTIFY_USER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INPUT_88PM80X_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_88PM860X_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_88PM886_ONKEY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_AD714X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_AD714X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_AD714X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_ADXL34X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_ADXL34X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_ADXL34X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_APANEL policy<{'amd64': 'm'}> +CONFIG_INPUT_ARIEL_PWRBUTTON policy<{'armhf': 'm'}> +CONFIG_INPUT_ARIZONA_HAPTICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_ATC260X_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_ATI_REMOTE2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_ATLAS_BTNS policy<{'amd64': 'm'}> +CONFIG_INPUT_ATMEL_CAPTOUCH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_AW86927 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_AXP20X_PEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_BBNSM_PWRKEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INPUT_BMA150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_CM109 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_CMA3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_CMA3000_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_CPCAP_PWRBUTTON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_CS40L50_VIBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_DA7280_HAPTICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DA9052_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DA9055_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DA9063_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DRV260X_HAPTICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DRV2665_HAPTICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DRV2667_HAPTICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_E3X0_BUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_EVDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INPUT_FF_MEMLESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INPUT_GPIO_BEEPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_GPIO_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_GPIO_ROTARY_ENCODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_GPIO_VIBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_HISI_POWERKEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INPUT_IBM_PANEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_IDEAPAD_SLIDEBAR policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_INPUT_IMS_PCU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_IQS269A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_IQS626A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_IQS7222 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_JOYDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INPUT_JOYSTICK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_KEYBOARD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_KEYSPAN_REMOTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_KXTJ9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_LEDS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_MATRIXKMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INPUT_MAX7360_ROTARY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_MAX77650_ONKEY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_MAX77693_HAPTIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_MAX8925_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_MAX8997_HAPTIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_MC13783_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_MISC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_MMA8450 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_MOUSE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_MOUSEDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_MOUSEDEV_PSAUX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_INPUT_MOUSEDEV_SCREEN_X policy<{'amd64': '1024', 'arm64': '1024', 'armhf': '1024', 'ppc64el': '1024', 'riscv64': '1024'}> +CONFIG_INPUT_MOUSEDEV_SCREEN_Y policy<{'amd64': '768', 'arm64': '768', 'armhf': '768', 'ppc64el': '768', 'riscv64': '768'}> +CONFIG_INPUT_PALMAS_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_PCAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_PCF8574 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_PCSPKR policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_INPUT_PF1550_ONKEY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_PM8941_PWRKEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INPUT_PM8XXX_VIBRATOR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INPUT_PMIC8XXX_PWRKEY policy<{'armhf': 'm'}> +CONFIG_INPUT_POWERMATE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_PWM_BEEPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_PWM_VIBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_QNAP_MCU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_RAVE_SP_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_REGULATOR_HAPTIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_RETU_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_RK805_PWRKEY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_RT5120_PWRKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_SC27XX_VIBRA policy<{'arm64': 'm'}> +CONFIG_INPUT_SOC_BUTTON_ARRAY policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_SPARSEKMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INPUT_STPMIC1_ONKEY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_TABLET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_TOUCHSCREEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_TPS65218_PWRBUTTON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_TPS65219_PWRBUTTON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_TPS6594_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_TWL4030_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_TWL4030_VIBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_TWL6040_VIBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_VIVALDIFMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_INPUT_WM831X_ON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_XEN_KBDDEV_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_INPUT_YEALINK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INSPUR_PLATFORM_PROFILE policy<{'amd64': 'm'}> +CONFIG_INSTRUCTION_DECODER policy<{'amd64': 'y'}> +CONFIG_INT3406_THERMAL policy<{'amd64': 'm'}> +CONFIG_INT340X_THERMAL policy<{'amd64': 'm'}> +CONFIG_INTEGRITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEGRITY_ASYMMETRIC_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEGRITY_AUDIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEGRITY_CA_MACHINE_KEYRING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n'}> +CONFIG_INTEGRITY_CA_MACHINE_KEYRING_MAX policy<{'ppc64el': 'y'}> +CONFIG_INTEGRITY_MACHINE_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_INTEGRITY_SIGNATURE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEGRITY_TRUSTED_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEL_ATOMISP2_LED policy<{'amd64': 'm'}> +CONFIG_INTEL_ATOMISP2_PDX86 policy<{'amd64': 'y'}> +CONFIG_INTEL_BXTWC_PMIC_TMU policy<{'amd64': 'm'}> +CONFIG_INTEL_BXT_PMIC_THERMAL policy<{'amd64': 'm'}> +CONFIG_INTEL_BYTCRC_PWRSRC policy<{'amd64': 'm'}> +CONFIG_INTEL_CHTDC_TI_PWRBTN policy<{'amd64': 'm'}> +CONFIG_INTEL_CHTWC_INT33FE policy<{'amd64': 'm'}> +CONFIG_INTEL_DC_TI_ADC policy<{'amd64': 'm'}> +CONFIG_INTEL_EHL_PSE_IO policy<{'amd64': 'm'}> +CONFIG_INTEL_GTT policy<{'amd64': 'y'}> +CONFIG_INTEL_HFI_THERMAL policy<{'amd64': 'y'}> +CONFIG_INTEL_HID_EVENT policy<{'amd64': 'm'}> +CONFIG_INTEL_IDLE policy<{'amd64': 'y'}> +CONFIG_INTEL_IDMA64 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INTEL_IDXD policy<{'amd64': 'm'}> +CONFIG_INTEL_IDXD_BUS policy<{'amd64': 'm'}> +CONFIG_INTEL_IDXD_COMPAT policy<{'amd64': 'n'}> +CONFIG_INTEL_IDXD_PERFMON policy<{'amd64': 'y'}> +CONFIG_INTEL_IDXD_SVM policy<{'amd64': 'y'}> +CONFIG_INTEL_IFS policy<{'amd64': 'm'}> +CONFIG_INTEL_INT0002_VGPIO policy<{'amd64': 'm'}> +CONFIG_INTEL_IOATDMA policy<{'amd64': 'm'}> +CONFIG_INTEL_IOMMU policy<{'amd64': 'y'}> +CONFIG_INTEL_IOMMU_FLOPPY_WA policy<{'amd64': 'y'}> +CONFIG_INTEL_IOMMU_PERF_EVENTS policy<{'amd64': 'y'}> +CONFIG_INTEL_IOMMU_SVM policy<{'amd64': 'y'}> +CONFIG_INTEL_IPS policy<{'amd64': 'm'}> +CONFIG_INTEL_ISHTP_ECLITE policy<{'amd64': 'm'}> +CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER policy<{'amd64': 'm'}> +CONFIG_INTEL_ISH_HID policy<{'amd64': 'm'}> +CONFIG_INTEL_LDMA policy<{'amd64': 'y'}> +CONFIG_INTEL_MEI policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INTEL_MEI_CSC policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_GSC policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_GSC_PROXY policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_HDCP policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_LB policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_ME policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_PXP policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_TXE policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_VSC policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_VSC_HW policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_WDT policy<{'amd64': 'm'}> +CONFIG_INTEL_MRFLD_ADC policy<{'amd64': 'm'}> +CONFIG_INTEL_MRFLD_PWRBTN policy<{'amd64': 'm'}> +CONFIG_INTEL_OAKTRAIL policy<{'amd64': 'm'}> +CONFIG_INTEL_OC_WATCHDOG policy<{'amd64': 'm'}> +CONFIG_INTEL_PCH_THERMAL policy<{'amd64': 'm'}> +CONFIG_INTEL_PLR_TPMI policy<{'amd64': 'm'}> +CONFIG_INTEL_PMC_CORE policy<{'amd64': 'm'}> +CONFIG_INTEL_PMC_SSRAM_TELEMETRY policy<{'amd64': 'm'}> +CONFIG_INTEL_PMT_CLASS policy<{'amd64': 'm'}> +CONFIG_INTEL_PMT_CRASHLOG policy<{'amd64': 'm'}> +CONFIG_INTEL_PMT_DISCOVERY policy<{'amd64': 'm'}> +CONFIG_INTEL_PMT_TELEMETRY policy<{'amd64': 'm'}> +CONFIG_INTEL_POWERCLAMP policy<{'amd64': 'm'}> +CONFIG_INTEL_PUNIT_IPC policy<{'amd64': 'm'}> +CONFIG_INTEL_QEP policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-'}> +CONFIG_INTEL_QUICKI2C policy<{'amd64': 'm'}> +CONFIG_INTEL_QUICKSPI policy<{'amd64': 'm'}> +CONFIG_INTEL_RAPL policy<{'amd64': 'm'}> +CONFIG_INTEL_RAPL_CORE policy<{'amd64': 'm'}> +CONFIG_INTEL_RAPL_TPMI policy<{'amd64': 'm'}> +CONFIG_INTEL_RST policy<{'amd64': 'm'}> +CONFIG_INTEL_SAR_INT1092 policy<{'amd64': 'm'}> +CONFIG_INTEL_SCU policy<{'amd64': 'y'}> +CONFIG_INTEL_SCU_IPC policy<{'amd64': 'y'}> +CONFIG_INTEL_SCU_IPC_UTIL policy<{'amd64': 'm'}> +CONFIG_INTEL_SCU_PCI policy<{'amd64': 'y'}> +CONFIG_INTEL_SCU_PLATFORM policy<{'amd64': 'm'}> +CONFIG_INTEL_SDSI policy<{'amd64': 'm'}> +CONFIG_INTEL_SKL_INT3472 policy<{'amd64': 'm'}> +CONFIG_INTEL_SMARTCONNECT policy<{'amd64': 'm'}> +CONFIG_INTEL_SOC_DTS_IOSF_CORE policy<{'amd64': 'm'}> +CONFIG_INTEL_SOC_DTS_THERMAL policy<{'amd64': 'm'}> +CONFIG_INTEL_SOC_PMIC policy<{'amd64': 'y'}> +CONFIG_INTEL_SOC_PMIC_BXTWC policy<{'amd64': 'm'}> +CONFIG_INTEL_SOC_PMIC_CHTDC_TI policy<{'amd64': 'm'}> +CONFIG_INTEL_SOC_PMIC_CHTWC policy<{'amd64': 'y'}> +CONFIG_INTEL_SOC_PMIC_MRFLD policy<{'amd64': 'm'}> +CONFIG_INTEL_SPEED_SELECT_INTERFACE policy<{'amd64': 'm'}> +CONFIG_INTEL_SPEED_SELECT_TPMI policy<{'amd64': 'm'}> +CONFIG_INTEL_STRATIX10_RSU policy<{'arm64': 'm'}> +CONFIG_INTEL_STRATIX10_SERVICE policy<{'arm64': 'm'}> +CONFIG_INTEL_TCC policy<{'amd64': 'y'}> +CONFIG_INTEL_TCC_COOLING policy<{'amd64': 'm'}> +CONFIG_INTEL_TDX_GUEST policy<{'amd64': 'y'}> +CONFIG_INTEL_TDX_HOST policy<{'amd64': 'y'}> +CONFIG_INTEL_TELEMETRY policy<{'amd64': 'm'}> +CONFIG_INTEL_TH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_THC_HID policy<{'amd64': 'm'}> +CONFIG_INTEL_TH_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_TH_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INTEL_TH_GTH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_TH_MSU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_TH_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_TH_PTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_TH_STH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_TPMI policy<{'amd64': 'm'}> +CONFIG_INTEL_TPMI_POWER_DOMAINS policy<{'amd64': 'm'}> +CONFIG_INTEL_TURBO_MAX_3 policy<{'amd64': 'y'}> +CONFIG_INTEL_TXT policy<{'amd64': 'y'}> +CONFIG_INTEL_UNCORE_FREQ_CONTROL policy<{'amd64': 'm'}> +CONFIG_INTEL_UNCORE_FREQ_CONTROL_TPMI policy<{'amd64': 'm'}> +CONFIG_INTEL_VBTN policy<{'amd64': 'm'}> +CONFIG_INTEL_VSC policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'riscv64': 'm'}> +CONFIG_INTEL_VSEC policy<{'amd64': 'm'}> +CONFIG_INTEL_WMI policy<{'amd64': 'y'}> +CONFIG_INTEL_WMI_SBL_FW_UPDATE policy<{'amd64': 'm'}> +CONFIG_INTEL_WMI_THUNDERBOLT policy<{'amd64': 'm'}> +CONFIG_INTEL_XWAY_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTERCONNECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INTERCONNECT_CLK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_IMX8MM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_IMX8MN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_IMX8MP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_IMX8MQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_MTK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_MTK_DVFSRC_EMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_MTK_MT8183 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_MTK_MT8195 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_MTK_MT8196 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_QCOM_BCM_VOTER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_QCOM_ELIZA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_GLYMUR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_KAANAPALI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MILOS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_QCOM_MSM8909 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8916 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8937 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8939 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8953 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8974 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8976 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8996 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_OSM_L3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCM2290 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCS404 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCS615 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCS8300 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_QDU1000 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_RPMH policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_QCOM_RPMH_POSSIBLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_QCOM_SA8775P policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SAR2130P policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC7180 policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC7280 policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC8180X policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC8280XP policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDM660 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDM670 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDM845 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDX55 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDX65 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDX75 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM6115 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM6350 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM7150 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8150 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8250 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8350 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8450 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8550 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8650 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8750 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SMD_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_X1E80100 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_SAMSUNG policy<{'armhf': 'n'}> +CONFIG_INTERRUPT_CNT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INTERRUPT_SANITIZE_REGISTERS policy<{'ppc64el': 'y'}> +CONFIG_INTERVAL_TREE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTERVAL_TREE_SPAN_ITER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_INTERVAL_TREE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INV_ICM42600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM42600_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM42600_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM45600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM45600_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM45600_I3C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM45600_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_MPU6050_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_MPU6050_IIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_MPU6050_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IOMMUFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IOMMUFD_DRIVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IOMMUFD_DRIVER_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IOMMU_API policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IOMMU_DEBUG policy<{'amd64': 'n'}> +CONFIG_IOMMU_DEFAULT_PASSTHROUGH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IOMMU_DMA policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_IOMMU_HELPER policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_IOMMU_IOPF policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_IOMMU_IOVA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'y'}> +CONFIG_IOMMU_IO_PGTABLE policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_IOMMU_IO_PGTABLE_ARMV7S policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST policy<{'arm64': 'n'}> +CONFIG_IOMMU_IO_PGTABLE_DART policy<{'arm64': 'y'}> +CONFIG_IOMMU_IO_PGTABLE_LPAE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IOMMU_MM_DATA policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_IOMMU_PT policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_IOMMU_PT_AMDV1 policy<{'amd64': 'y', 'riscv64': 'm'}> +CONFIG_IOMMU_PT_RISCV64 policy<{'amd64': 'm', 'riscv64': 'y'}> +CONFIG_IOMMU_PT_VTDSS policy<{'amd64': 'y', 'riscv64': 'm'}> +CONFIG_IOMMU_PT_X86_64 policy<{'amd64': 'y', 'riscv64': 'm'}> +CONFIG_IOMMU_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IOMMU_SVA policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_IONIC policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IOSCHED_BFQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IOSF_MBI policy<{'amd64': 'y'}> +CONFIG_IOSF_MBI_DEBUG policy<{'amd64': 'y'}> +CONFIG_IOSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IO_DELAY_0X80 policy<{'amd64': 'n'}> +CONFIG_IO_DELAY_0XED policy<{'amd64': 'y'}> +CONFIG_IO_DELAY_NONE policy<{'amd64': 'n'}> +CONFIG_IO_DELAY_UDELAY policy<{'amd64': 'n'}> +CONFIG_IO_EVENT_IRQ policy<{'ppc64el': 'y'}> +CONFIG_IO_STRICT_DEVMEM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IO_URING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IO_URING_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IO_URING_BPF_OPS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IO_URING_MOCK_FILE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IO_URING_ZCRX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IO_WQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP5XXX_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IP6_NF_FILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_IPTABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_IPTABLES_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MANGLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_AH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_EUI64 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_FRAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_HL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_IPV6HEADER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_MH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_OPTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_RPFILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_RT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_SRH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_SECURITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_TARGET_HL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_TARGET_MASQUERADE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_TARGET_NPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_TARGET_REJECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_TARGET_SYNPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPACK_BUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IPC_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_BOOT_POLICY policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_IPE_POLICY_SIG_PLATFORM_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_POLICY_SIG_SECONDARY_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_PROP_DM_VERITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_PROP_DM_VERITY_SIGNATURE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_PROP_FS_VERITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_PROP_FS_VERITY_BUILTIN_SIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPMB_DEVICE_INTERFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_DEVICE_INTERFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_DMI_DECODE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_IPMI_HANDLER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IPMI_IPMB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_KCS_BMC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPMI_KCS_BMC_CDEV_IPMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPMI_KCS_BMC_SERIO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPMI_PANIC_EVENT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_IPMI_PLAT_DATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPMI_POWERNV policy<{'ppc64el': 'm'}> +CONFIG_IPMI_POWEROFF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_SI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_SSIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPQ_APSS_5424 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_APSS_6018 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_APSS_PLL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_CMN_PLL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_GCC_4019 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_GCC_5018 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_GCC_5210 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_5332 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_5424 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_6018 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_GCC_806X policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_IPQ_GCC_8074 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_GCC_9574 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_LCC_806X policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_IPQ_NSSCC_5424 policy<{'arm64': 'm'}> +CONFIG_IPQ_NSSCC_9574 policy<{'arm64': 'm'}> +CONFIG_IPQ_NSSCC_QCA8K policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPU_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_IPV6_FOU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_FOU_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_GRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_ILA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_IOAM6_LWTUNNEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_MIP6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_MROUTE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_MULTIPLE_TABLES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_NDISC_NODETYPE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_OPTIMISTIC_DAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_PIMSM_V2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_ROUTER_PREF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_ROUTE_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_RPL_LWTUNNEL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IPV6_SEG6_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_SEG6_HMAC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_SEG6_LWTUNNEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_SIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_SIT_6RD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_SUBTREES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_VTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPVLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPVLAN_L3S policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPVTAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPW2100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPW2100_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IPW2100_MONITOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPW2200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPW2200_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IPW2200_MONITOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPW2200_PROMISCUOUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPW2200_QOS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPW2200_RADIOTAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPWIRELESS policy<{'amd64': 'm'}> +CONFIG_IP_ADVANCED_ROUTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_FIB_TRIE_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_MROUTE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_MROUTE_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_MROUTE_MULTIPLE_TABLES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_MULTICAST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_MULTIPLE_TABLES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_NF_ARPFILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_ARPTABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_ARP_MANGLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_FILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_IPTABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_IPTABLES_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_MANGLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_MATCH_AH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_MATCH_ECN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_MATCH_RPFILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_MATCH_TTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_SECURITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_ECN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_MASQUERADE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_NETMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_REDIRECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_REJECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_SYNPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_TTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_PIMSM_V1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_PIMSM_V2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_ROUTE_CLASSID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_ROUTE_MULTIPATH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_ROUTE_VERBOSE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_SCTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_BITMAP_IP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_BITMAP_IPMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_BITMAP_PORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IPMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IPMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IPPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IPPORTIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IPPORTNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_MAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_NETIFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_NETNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_NETPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_NETPORTNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_LIST_SET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_MAX policy<{'amd64': '256', 'arm64': '256', 'armhf': '256', 'ppc64el': '256', 'riscv64': '256', 's390x': '256'}> +CONFIG_IP_VS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IP_VS_DH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_FO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_FTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_IPV6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_LBLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_LBLCR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_LC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_MH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_MH_TAB_INDEX policy<{'amd64': '12', 'arm64': '12', 'armhf': '12', 'ppc64el': '12', 'riscv64': '12', 's390x': '12'}> +CONFIG_IP_VS_NFCT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_NQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_OVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_PE_SIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_PROTO_AH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_PROTO_AH_ESP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_PROTO_ESP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_PROTO_SCTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_PROTO_TCP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_PROTO_UDP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_RR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_SED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_SH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_SH_TAB_BITS policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8', 's390x': '8'}> +CONFIG_IP_VS_TAB_BITS policy<{'amd64': '12', 'arm64': '12', 'armhf': '12', 'ppc64el': '12', 'riscv64': '12', 's390x': '12'}> +CONFIG_IP_VS_TWOS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IP_VS_WLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_WRR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IQS620AT_TEMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IQS621_ALS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IQS624_POS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IRQCHIP policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IRQSOFF_TRACER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IRQSTACKS policy<{'armhf': 'y'}> +CONFIG_IRQ_ALL_CPUS policy<{'ppc64el': 'y'}> +CONFIG_IRQ_BYPASS_MANAGER policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IRQ_CROSSBAR policy<{'armhf': 'y'}> +CONFIG_IRQ_DOMAIN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRQ_DOMAIN_HIERARCHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IRQ_FORCED_THREADING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IRQ_MSI_IOMMU policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 's390x': '-'}> +CONFIG_IRQ_MSI_LIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRQ_POLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRQ_REMAP policy<{'amd64': 'y'}> +CONFIG_IRQ_SIM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRQ_STACKS policy<{'riscv64': 'y'}> +CONFIG_IRQ_TIME_ACCOUNTING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IRQ_WORK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRSD200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_ENE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_IR_FINTEK policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_IR_GPIO_CIR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_GPIO_TX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_HIX5HD2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_IGORPLUGUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_IGUANA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_IMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_IMON_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_IMON_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_ITE_CIR policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_IR_JVC_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_MCEUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_MCE_KBD_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IR_MESON_TX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IR_MTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IR_NEC_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_NUVOTON policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_IR_PWM_TX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_RC5_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_RC6_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_RCMM_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_REDRAT3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SANYO_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SERIAL_TRANSMITTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IR_SHARP_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SONY_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_STREAMZAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SUNXI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_IR_TOY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_TTUSBIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_WINBOND_CIR policy<{'amd64': 'm'}> +CONFIG_IR_XMP_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ISA_BUS policy<{'amd64': 'y'}> +CONFIG_ISA_BUS_API policy<{'amd64': 'y'}> +CONFIG_ISA_DMA_API policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ISCSI_BOOT_SYSFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ISCSI_IBFT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ISCSI_IBFT_FIND policy<{'amd64': 'y'}> +CONFIG_ISCSI_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ISCSI_TARGET_CXGB4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ISCSI_TCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ISL29003 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ISL29020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ISL29125 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ISL29501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ISL76682 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ISM policy<{'s390x': 'm'}> +CONFIG_ISM_VFIO_PCI policy<{'s390x': 'm'}> +CONFIG_ISO9660_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IT8712F_WDT policy<{'amd64': 'm'}> +CONFIG_IT87_WDT policy<{'amd64': 'm'}> +CONFIG_ITCO_WDT policy<{'amd64': 'm'}> +CONFIG_ITG3200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IUCV policy<{'s390x': 'y'}> +CONFIG_IWL3945 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWL4965 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLDVM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLEGACY_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IWLEGACY_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IWLMLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLMVM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLWIFI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLWIFI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IWLWIFI_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IWLWIFI_DEVICE_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IWLWIFI_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IWLWIFI_OPMODE_MODULAR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IXGBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IXGBEVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IXGBEVF_IPSEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IXGBE_DCA policy<{'amd64': 'y'}> +CONFIG_IXGBE_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IXGBE_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IXGBE_IPSEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JAILHOUSE_GUEST policy<{'amd64': 'y'}> +CONFIG_JBD2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_JBD2_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_JFFS2_CMODE_FAVOURLZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_CMODE_NONE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_CMODE_PRIORITY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_CMODE_SIZE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_COMPRESSION_OPTIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JFFS2_FS_DEBUG policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_JFFS2_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_FS_WBUF_VERIFY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_FS_WRITEBUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_FS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_RTIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_RUBIN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_SUMMARY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_ZLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_JFS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFS_STATISTICS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_JOLIET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_JOYSTICK_A3D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_ADI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_ANALOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_AS5011 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_COBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_DB9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_FSIA6B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_GAMECON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_GF2K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_GRIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_GRIP_MP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_GUILLEMOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_IFORCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_IFORCE_232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_IFORCE_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_INTERACT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_JOYDUMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_MAGELLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_PSXPAD_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_PSXPAD_SPI_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JOYSTICK_PXRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_QWIIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_SEESAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_SENSEHAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_SIDEWINDER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_SPACEBALL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_SPACEORB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_STINGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_TMDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_TURBOGRAFX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_TWIDJOY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_WALKERA0701 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_WARRIOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_XPAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_XPAD_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JOYSTICK_XPAD_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JOYSTICK_ZHENHUA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JSA1212 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JUMP_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_JUMP_LABEL_FEATURE_CHECKS policy<{'ppc64el': 'y'}> +CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_K3_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_K3_RTI_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_K3_THERMAL policy<{'arm64': 'm'}> +CONFIG_KALLSYMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KALLSYMS_ALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KALLSYMS_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KARMA_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_KASAN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KCMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KCOV policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KCSAN policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_KDB_CONTINUE_CATASTROPHIC policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_KDB_DEFAULT_ENABLE policy<{'amd64': '0x1', 'arm64': '0x1', 'armhf': '0x1', 'ppc64el': '0x1', 'riscv64': '0x1'}> +CONFIG_KDB_KEYBOARD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KEBA_CP500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_KEBA_LAN9252 policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_KEEMBAY_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_KEMPLD_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KERNEL_BZIP2 policy<{'amd64': 'n', 'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNEL_GZIP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KERNEL_IMAGE_BASE policy<{'s390x': '0x3FFE0000000'}> +CONFIG_KERNEL_LZ4 policy<{'amd64': 'n', 'arm64': '-', 'armhf': 'n', 'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNEL_LZMA policy<{'amd64': 'n', 'arm64': '-', 'armhf': 'n', 'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNEL_LZO policy<{'amd64': 'n', 'arm64': '-', 'armhf': 'n', 'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNEL_MODE_NEON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_KERNEL_NOBP policy<{'s390x': 'n'}> +CONFIG_KERNEL_START policy<{'ppc64el': '0xc000000000000000'}> +CONFIG_KERNEL_UNCOMPRESSED policy<{'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNEL_XZ policy<{'amd64': 'n', 'arm64': '-', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEXEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEXEC_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEXEC_ELF policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KEXEC_FILE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEXEC_HANDOVER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_KEXEC_HANDOVER_DEBUG policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_KEXEC_HANDOVER_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_KEXEC_HANDOVER_ENABLE_DEFAULT policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_KEXEC_IMAGE_VERIFY_SIG policy<{'arm64': 'y'}> +CONFIG_KEXEC_JUMP policy<{'amd64': 'y'}> +CONFIG_KEXEC_SIG policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_KEXEC_SIG_FORCE policy<{'amd64': 'n'}> +CONFIG_KEYBOARD_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_ADP5520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_ADP5585 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_ADP5588 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_APPLESPI policy<{'amd64': 'm'}> +CONFIG_KEYBOARD_ATKBD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KEYBOARD_BCM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_CAP11XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_CHARLIEPLEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_CYPRESS_SF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_DLINK_DIR685 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_GOLDFISH_EVENTS policy<{'riscv64': 'm'}> +CONFIG_KEYBOARD_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_GPIO_POLLED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_IMX_BBM_SCMI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_KEYBOARD_IMX_SC_KEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_IQS62X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_LKKBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_LM8323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_LM8333 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_MATRIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_MAX7359 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_MAX7360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_MPR121 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_MT6779 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_MTK_PMIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_NEWTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_NVEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_OMAP4 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_OPENCORES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_PINEPHONE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_PMIC8XXX policy<{'armhf': 'm'}> +CONFIG_KEYBOARD_PXA27x policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_QT1050 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_QT1070 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_QT2160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_SAMSUNG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_SNVS_PWRKEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_STMPE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_STOWAWAY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_SUN4I_LRADC policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_KEYBOARD_SUNKBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_TC3589X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_TCA8418 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_TM2_TOUCHKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_TWL4030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_XTKBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEYS_REQUEST_CACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEY_DH_OPERATIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEY_NOTIFICATIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KFENCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KFENCE_DEFERRABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KFENCE_NUM_OBJECTS policy<{'amd64': '255', 'arm64': '255', 'armhf': '255', 'ppc64el': '255', 'riscv64': '255', 's390x': '255'}> +CONFIG_KFENCE_SAMPLE_INTERVAL policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_KFENCE_STRESS_TEST_FAULTS policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_KGDB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KGDB_HONOUR_BLOCKLIST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KGDB_KDB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KGDB_LOW_LEVEL_TRAP policy<{'amd64': 'y'}> +CONFIG_KGDB_TESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_KHADAS_MCU_FAN_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KLP_BUILD policy<{'amd64': 'y'}> +CONFIG_KMAP_LOCAL policy<{'armhf': 'y'}> +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY policy<{'armhf': 'y'}> +CONFIG_KMX61 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KPROBES_ON_FTRACE policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_KPROBE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KPROBE_EVENTS_ON_NOTRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KPROBE_EVENT_GEN_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KPSS_XCC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KRAITCC policy<{'armhf': 'm'}> +CONFIG_KRAIT_CLOCKS policy<{'armhf': 'y'}> +CONFIG_KRAIT_L2_ACCESSORS policy<{'armhf': 'y'}> +CONFIG_KRETPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KRETPROBE_ON_RETHOOK policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KS0108 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KS0108_DELAY policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2'}> +CONFIG_KS0108_PORT policy<{'amd64': '0x378', 'arm64': '0x378', 'armhf': '0x378', 'ppc64el': '0x378', 'riscv64': '0x378'}> +CONFIG_KS8842 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KS8851 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KS8851_MLL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KSM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KSZ884X_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KUNIT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KUNPENG_HCCS policy<{'arm64': 'm'}> +CONFIG_KUSER_HELPERS policy<{'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y'}> +CONFIG_KVFREE_RCU_BATCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KVM_AMD policy<{'amd64': 'm'}> +CONFIG_KVM_AMD_SEV policy<{'amd64': 'y'}> +CONFIG_KVM_ASYNC_PF policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_KVM_ASYNC_PF_SYNC policy<{'s390x': 'y'}> +CONFIG_KVM_BOOK3S_64 policy<{'ppc64el': 'm'}> +CONFIG_KVM_BOOK3S_64_HANDLER policy<{'ppc64el': 'y'}> +CONFIG_KVM_BOOK3S_64_HV policy<{'ppc64el': 'm'}> +CONFIG_KVM_BOOK3S_HANDLER policy<{'ppc64el': 'y'}> +CONFIG_KVM_BOOK3S_HV_EXIT_TIMING policy<{'ppc64el': 'y'}> +CONFIG_KVM_BOOK3S_HV_NESTED_PMU_WORKAROUND policy<{'ppc64el': 'y'}> +CONFIG_KVM_BOOK3S_HV_P9_TIMING policy<{'ppc64el': 'y'}> +CONFIG_KVM_BOOK3S_HV_PMU policy<{'ppc64el': 'm'}> +CONFIG_KVM_BOOK3S_HV_POSSIBLE policy<{'ppc64el': 'y'}> +CONFIG_KVM_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KVM_COMPAT policy<{'amd64': 'y'}> +CONFIG_KVM_ELIDE_TLB_FLUSH_IF_YOUNG policy<{'amd64': 'y'}> +CONFIG_KVM_EXTERNAL_WRITE_TRACKING policy<{'amd64': 'y'}> +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_KVM_GENERIC_HARDWARE_ENABLING policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES policy<{'amd64': 'y'}> +CONFIG_KVM_GENERIC_PRE_FAULT_MEMORY policy<{'amd64': 'y'}> +CONFIG_KVM_GUEST policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_KVM_GUEST_MEMFD policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_KVM_HYPERV policy<{'amd64': 'y'}> +CONFIG_KVM_INTEL policy<{'amd64': 'm'}> +CONFIG_KVM_INTEL_PROVE_VE policy<{'amd64': 'y'}> +CONFIG_KVM_INTEL_TDX policy<{'amd64': 'y'}> +CONFIG_KVM_IOAPIC policy<{'amd64': 'y'}> +CONFIG_KVM_MAX_NR_VCPUS policy<{'amd64': '4096'}> +CONFIG_KVM_MMIO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_KVM_MMU_LOCKLESS_AGING policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_KVM_PROVE_MMU policy<{'amd64': 'n'}> +CONFIG_KVM_S390_UCONTROL policy<{'s390x': 'n'}> +CONFIG_KVM_SMM policy<{'amd64': 'y'}> +CONFIG_KVM_SW_PROTECTED_VM policy<{'amd64': 'y'}> +CONFIG_KVM_VFIO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_KVM_WERROR policy<{'amd64': 'y'}> +CONFIG_KVM_X86 policy<{'amd64': 'm'}> +CONFIG_KVM_XEN policy<{'amd64': 'y'}> +CONFIG_KVM_XICS policy<{'ppc64el': 'y'}> +CONFIG_KVM_XIVE policy<{'ppc64el': 'y'}> +CONFIG_KXCJK1013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KXSD9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KXSD9_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KXSD9_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_L2TP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_L2TP_DEBUGFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_L2TP_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_L2TP_IP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_L2TP_V3 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LAN743X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LAN865X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LAN966X_DCB policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LAN966X_OIC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LAN966X_SWITCH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LAN969X_SWITCH policy<{'arm64': 'y'}> +CONFIG_LAPB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_LAPBETHER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LATTICE_ECP3_CONFIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LCD2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LCD_AMS369FG06 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_CLASS_DEVICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_LCD_HX8357 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_ILI922X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_ILI9320 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_L4F00242T03 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_LMS283GF05 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_LMS501KF03 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_LTV350QV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_OTM3225A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_TDO24M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_VGG2432A4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LDISC_AUTOLOAD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LDM_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_LDM_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION policy<{'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_LD_HEAD_STUB_CATCH policy<{'ppc64el': 'n'}> +CONFIG_LD_IS_BFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LD_ORPHAN_WARN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LD_ORPHAN_WARN_LEVEL policy<{'amd64': '"warn"', 'arm64': '"warn"', 'armhf': '"warn"', 'ppc64el': '"warn"', 'riscv64': '"warn"', 's390x': '"warn"'}> +CONFIG_LD_VERSION policy<{'amd64': '24600', 'arm64': '24600', 'armhf': '24600', 'ppc64el': '24600', 'riscv64': '24600', 's390x': '24600'}> +CONFIG_LEDS_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_AAT1290 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_ACER_A500 policy<{'armhf': 'm'}> +CONFIG_LEDS_ADP5520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_AN30259A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_APU policy<{'amd64': 'm'}> +CONFIG_LEDS_ARIEL policy<{'armhf': 'm'}> +CONFIG_LEDS_AS3645A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_AW200XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_AW2013 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_BCM6328 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_BCM6358 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_BD2606MVV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_BD2802 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_BLINKM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_BLINKM_MULTICOLOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_CHT_WCOVE policy<{'amd64': 'm'}> +CONFIG_LEDS_CLASS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_CLASS_FLASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_CLASS_MULTICOLOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_CR0014114 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_LEDS_DA903X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_DAC124S085 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_EL15203000 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_EXPRESSWIRE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_GROUP_MULTICOLOR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_INTEL_SS4200 policy<{'amd64': 'm'}> +CONFIG_LEDS_IS31FL319X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_IS31FL32XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_KTD202X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_KTD2692 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LM3530 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LM3532 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LM3533 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LM355x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LM3601X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LM36274 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LM3642 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LM3692X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LM3697 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP3944 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LP3952 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LP50XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LP5521 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP5523 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP5562 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP5569 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP55XX_COMMON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP5812 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP8501 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP8788 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LP8860 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP8864 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LT3593 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_MAX5970 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MAX77650 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MAX77693 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MAX77705 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MAX8997 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_MC13783 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MENF21BMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MLXCPLD policy<{'amd64': 'm'}> +CONFIG_LEDS_MLXREG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_MT6323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MT6360 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MT6370_FLASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MT6370_RGB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_NCP5623 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_NIC78BX policy<{'amd64': 'm'}> +CONFIG_LEDS_NS2 policy<{'armhf': 'm'}> +CONFIG_LEDS_OSRAM_AMS_AS3668 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_PCA9532 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_PCA9532_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_PCA955X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_PCA955X_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_PCA963X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_PCA995X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_PM8058 policy<{'armhf': 'm'}> +CONFIG_LEDS_POWERNV policy<{'ppc64el': 'm'}> +CONFIG_LEDS_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_PWM_MULTICOLOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_QCOM_FLASH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_LEDS_QCOM_LPG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_QNAP_MCU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_REGULATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_RT4505 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_RT8515 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_SC27XX_BLTC policy<{'arm64': 'm'}> +CONFIG_LEDS_SGM3140 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_SIEMENS_SIMATIC_IPC policy<{'amd64': 'm'}> +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_APOLLOLAKE policy<{'amd64': 'm'}> +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_ELKHARTLAKE policy<{'amd64': 'm'}> +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_F7188X policy<{'amd64': 'm'}> +CONFIG_LEDS_SPI_BYTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_ST1202 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_SUN50I_A100 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_LEDS_SY7802 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_SYSCON policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TCA6507 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TI_LMU_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TLC591XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TPS6105X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_TPS6131X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_TRIGGERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TRIGGER_ACTIVITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_BACKLIGHT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_CAMERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_CPU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TRIGGER_DEFAULT_ON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_DISK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TRIGGER_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_TRIGGER_HEARTBEAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_INPUT_EVENTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_TRIGGER_MTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TRIGGER_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_ONESHOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_PANIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TRIGGER_PATTERN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_TIMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_TRANSIENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_TTY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TURRIS_OMNIA policy<{'armhf': 'm'}> +CONFIG_LEDS_UPBOARD policy<{'amd64': 'm'}> +CONFIG_LEDS_USER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_WM831X_STATUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_WM8350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LED_TRIGGER_PHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEGACY_DIRECT_IO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LEGACY_PTYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LEGACY_VSYSCALL_NONE policy<{'amd64': 'n'}> +CONFIG_LEGACY_VSYSCALL_XONLY policy<{'amd64': 'y'}> +CONFIG_LENOVO_SE10_WDT policy<{'amd64': 'm'}> +CONFIG_LENOVO_SE30_WDT policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_CAMERA policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_CAPDATA policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_EVENTS policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_GAMEZONE policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_HELPERS policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_HOTKEY_UTILITIES policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_TUNING policy<{'amd64': 'm'}> +CONFIG_LENOVO_YMC policy<{'amd64': 'm'}> +CONFIG_LG_LAPTOP policy<{'amd64': 'm'}> +CONFIG_LIBERTAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBERTAS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_LIBERTAS_MESH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LIBERTAS_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBERTAS_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBERTAS_THINFIRM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBERTAS_THINFIRM_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_LIBERTAS_THINFIRM_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBERTAS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBETH_XDP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBFC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LIBFCOE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LIBFDT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LIBIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBIE_ADMINQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBIE_FWLOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBIPW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBIPW_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_LIBNVDIMM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_LIBWX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIDAR_LITE_V2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LINEAR_RANGES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LINEDISP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIQUIDIO policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LIQUIDIO_CORE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIQUIDIO_VF policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LIRC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LIST_HARDENED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LITEX policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LITEX_LITEETH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LITEX_SOC_CONTROLLER policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIVEPATCH policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_LIVEPATCH_64 policy<{'ppc64el': 'y'}> +CONFIG_LIVEUPDATE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_LIVEUPDATE_MEMFD policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_LIVEUPDATE_TEST policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_LKDTM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LLC2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_LLD_VERSION policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_LMK04832 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LMP91000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LOAD_IPL_KEYS policy<{'s390x': 'y'}> +CONFIG_LOAD_UEFI_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_LOCALVERSION policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_LOCKD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LOCKDEP_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCKD_V4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCKUP_DETECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LOCK_DEBUGGING_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCK_EVENT_COUNTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOCK_MM_AND_FIND_VMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCK_SPIN_ON_OWNER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCK_STAT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOCK_TORTURE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOGIG940_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LOGIRUMBLEPAD2_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LOGITECH_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LOGIWHEELS_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LOGO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOG_BUF_SHIFT policy<{'amd64': '18', 'arm64': '18', 'armhf': '17', 'ppc64el': '18', 'riscv64': '18', 's390x': '18'}> +CONFIG_LOG_CPU_MAX_BUF_SHIFT policy<{'amd64': '12', 'arm64': '12', 'armhf': '12', 'ppc64el': '12', 'riscv64': '12', 's390x': '12'}> +CONFIG_LOOPBACK_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LP8788_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LPARCFG policy<{'ppc64el': 'y'}> +CONFIG_LPC_ICH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_LPC_SCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_LP_CONSOLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_LRU_CACHE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LRU_GEN_STATS policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LRU_GEN_WALKS_MMU policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_LSI_ET1011C_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LSM policy<{'amd64': '"landlock,lockdown,yama,integrity,apparmor"', 'arm64': '"landlock,lockdown,yama,integrity,apparmor"', 'armhf': '"landlock,lockdown,yama,integrity,apparmor"', 'ppc64el': '"landlock,lockdown,yama,integrity,apparmor"', 'riscv64': '"landlock,lockdown,yama,integrity,apparmor"', 's390x': '"landlock,lockdown,yama,integrity,apparmor"'}> +CONFIG_LSM_MMAP_MIN_ADDR policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_LS_EXTIRQ policy<{'arm64': 'y'}> +CONFIG_LS_SCFG_MSI policy<{'arm64': 'y'}> +CONFIG_LTC1660 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2309 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2471 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2485 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2496 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2497 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2632 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2664 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2688 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2983 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTO_NONE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LTR390 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTR501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTRF216A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LV0104CS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LWQ_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LWTUNNEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LWTUNNEL_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LXT_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LZ4HC_COMPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LZ4_COMPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LZ4_DECOMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LZO_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LZO_DECOMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_M62332 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAC80211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAC80211_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_DEBUG_MENU policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MAC80211_HAS_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_HWSIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAC80211_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_MESH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_MESSAGE_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_RC_DEFAULT policy<{'amd64': '"minstrel_ht"', 'arm64': '"minstrel_ht"', 'armhf': '"minstrel_ht"', 'ppc64el': '"minstrel_ht"', 'riscv64': '"minstrel_ht"'}> +CONFIG_MAC80211_RC_DEFAULT_MINSTREL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_RC_MINSTREL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_STA_HASH_MAX_SIZE policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_MAC802154 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MACB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MACB_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MACB_USE_HWSTAMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MACHZ_WDT policy<{'amd64': 'm'}> +CONFIG_MACH_ARMADA_370 policy<{'armhf': 'y'}> +CONFIG_MACH_ARMADA_375 policy<{'armhf': 'y'}> +CONFIG_MACH_ARMADA_38X policy<{'armhf': 'y'}> +CONFIG_MACH_ARMADA_39X policy<{'armhf': 'y'}> +CONFIG_MACH_ARMADA_XP policy<{'armhf': 'y'}> +CONFIG_MACH_ARTPEC6 policy<{'armhf': 'n'}> +CONFIG_MACH_ASPEED_G6 policy<{'armhf': 'y'}> +CONFIG_MACH_BERLIN_BG2 policy<{'armhf': 'y'}> +CONFIG_MACH_BERLIN_BG2CD policy<{'armhf': 'y'}> +CONFIG_MACH_BERLIN_BG2Q policy<{'armhf': 'y'}> +CONFIG_MACH_DOVE policy<{'armhf': 'y'}> +CONFIG_MACH_INFINITY policy<{'armhf': 'y'}> +CONFIG_MACH_MESON6 policy<{'armhf': 'y'}> +CONFIG_MACH_MESON8 policy<{'armhf': 'y'}> +CONFIG_MACH_MMP2_DT policy<{'armhf': 'y'}> +CONFIG_MACH_MMP3_DT policy<{'armhf': 'y'}> +CONFIG_MACH_MT2701 policy<{'armhf': 'y'}> +CONFIG_MACH_MT6572 policy<{'armhf': 'y'}> +CONFIG_MACH_MT6582 policy<{'armhf': 'y'}> +CONFIG_MACH_MT6589 policy<{'armhf': 'y'}> +CONFIG_MACH_MT6592 policy<{'armhf': 'y'}> +CONFIG_MACH_MT7623 policy<{'armhf': 'y'}> +CONFIG_MACH_MT7629 policy<{'armhf': 'y'}> +CONFIG_MACH_MT8127 policy<{'armhf': 'y'}> +CONFIG_MACH_MT8135 policy<{'armhf': 'y'}> +CONFIG_MACH_MVEBU_ANY policy<{'armhf': 'y'}> +CONFIG_MACH_MVEBU_V7 policy<{'armhf': 'y'}> +CONFIG_MACH_OMAP_GENERIC policy<{'armhf': 'y'}> +CONFIG_MACINTOSH_DRIVERS policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_MACSEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MACSMC_POWER policy<{'arm64': 'm'}> +CONFIG_MACVLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MACVTAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MAC_EMUMOUSEBTN policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_MAC_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MADERA_IRQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAG3110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAGIC_SYSRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE policy<{'amd64': '0x01b6', 'arm64': '0x01b6', 'armhf': '0x01b6', 'ppc64el': '0x01b6', 'riscv64': '0x01b6', 's390x': '0x01b6'}> +CONFIG_MAGIC_SYSRQ_SERIAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_MAILBOX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MAILBOX_TEST policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MANAGER_SBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MANA_INFINIBAND policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_MANTIS_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAPPING_DIRTY_HELPERS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_MARCH_Z10 policy<{'s390x': 'n'}> +CONFIG_MARCH_Z13 policy<{'s390x': 'n'}> +CONFIG_MARCH_Z14 policy<{'s390x': 'n'}> +CONFIG_MARCH_Z15 policy<{'s390x': 'y'}> +CONFIG_MARCH_Z16 policy<{'s390x': 'n'}> +CONFIG_MARCH_Z16_TUNE policy<{'s390x': 'y'}> +CONFIG_MARCH_Z17 policy<{'s390x': 'n'}> +CONFIG_MARCH_Z196 policy<{'s390x': 'n'}> +CONFIG_MARCH_ZEC12 policy<{'s390x': 'n'}> +CONFIG_MARVELL_10G_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MARVELL_88Q2XXX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MARVELL_88X2222_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MARVELL_CN10K_DDR_PMU policy<{'arm64': 'm'}> +CONFIG_MARVELL_CN10K_DPI policy<{'arm64': 'm'}> +CONFIG_MARVELL_CN10K_TAD_PMU policy<{'arm64': 'm'}> +CONFIG_MARVELL_GTI_WDT policy<{'arm64-generic': 'm', 'arm64-generic-64k': 'y'}> +CONFIG_MARVELL_PEM_PMU policy<{'arm64': 'm'}> +CONFIG_MARVELL_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MATH_EMULATION policy<{'ppc64el': 'n'}> +CONFIG_MAX1027 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX11100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX1118 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX11205 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX11410 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX1241 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX1363 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX14001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX22007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX30100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX30102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX30208 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX31827 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX31856 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX31865 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX34408 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX44000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX44009 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX517 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX5432 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX5481 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX5487 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX5522 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX5821 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX63XX_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MAX6959 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX77541_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX77620_THERMAL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX77620_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX8925_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MAX9611 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAXIM_THERMOCOUPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAXLINEAR_86110_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MAXLINEAR_GPHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MAXSMP policy<{'amd64': 'y'}> +CONFIG_MAX_PHYSMEM_BITS policy<{'s390x': '46'}> +CONFIG_MAX_SKB_FRAGS policy<{'amd64': '17', 'arm64': '17', 'armhf': '17', 'ppc64el': '17', 'riscv64': '17', 's390x': '17'}> +CONFIG_MB1232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MC3230 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MCB_LPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCB_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCHP_CLK_MPFS policy<{'arm64': 'y'}> +CONFIG_MCHP_LAN966X_PCI policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MCP320X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP3422 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP3564 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP3911 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4018 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP41010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4131 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4531 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4725 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4728 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP47FEB02 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4821 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4922 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP9600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCPM policy<{'armhf': 'y'}> +CONFIG_MCPM_QUAD_CLUSTER policy<{'armhf': 'y'}> +CONFIG_MCTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MCTP_FLOWS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MCTP_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCTP_TRANSPORT_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCTP_TRANSPORT_I3C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCTP_TRANSPORT_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_AIROHA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MDIO_ASPEED policy<{'armhf': 'm'}> +CONFIG_MDIO_BCM_UNIMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MDIO_BITBANG policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MDIO_BUS_MUX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_BUS_MUX_GPIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_BUS_MUX_MESON_G12A policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MDIO_BUS_MUX_MESON_GXL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MDIO_BUS_MUX_MMIOREG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_BUS_MUX_MULTIPLEXER policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_CAVIUM policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_HISI_FEMAC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MDIO_IPQ4019 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_IPQ8064 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_MSCC_MIIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MDIO_MVUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MDIO_OCTEON policy<{'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_PIC64HPSC policy<{'arm64': 'm'}> +CONFIG_MDIO_REGMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_SUN4I policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MDIO_THUNDER policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MDIO_XGENE policy<{'arm64': 'm'}> +CONFIG_MDM_GCC_9607 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MDM_GCC_9615 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MD_AUTODETECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MD_BITMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MD_BITMAP_FILE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MD_CLUSTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MD_LINEAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MD_LLBITMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MD_RAID0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MD_RAID1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MD_RAID10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MD_RAID456 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MEDIATEK_2P5GE_PHY policy<{'arm64': 'm'}> +CONFIG_MEDIATEK_GE_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MEDIATEK_GE_SOC_PHY policy<{'amd64': 'n', 'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MEDIATEK_MT6359_AUXADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIATEK_MT6360_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIATEK_MT6370_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIATEK_MT6577_AUXADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MEDIATEK_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MEDIA_ALTERA_CI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_ANALOG_TV_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_ATTACH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_CAMERA_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_CEC_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_CEC_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MEDIA_COMMON_OPTIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_CONTROLLER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_CONTROLLER_DVB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_DIGITAL_TV_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_PCI_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_PLATFORM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_PLATFORM_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_RADIO_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_SDR_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_SUBDRV_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_SUPPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MEDIA_SUPPORT_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_TEST_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_TUNER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_E4000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_FC0011 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_FC0012 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_FC0013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_FC2580 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_IT913X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_M88RS6000T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MAX2165 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MC44S803 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MSI001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MT2060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MT2063 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MT20XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MT2131 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MT2266 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MXL301RF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MXL5005S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MXL5007T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_QM1D1B0004 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_QM1D1C0042 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_QT1010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_R820T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_SI2157 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_SIMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18212 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18218 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18271 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA827X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA8290 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA9887 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TEA5761 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TEA5767 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TUA9001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_XC2028 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_XC4000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_XC5000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_USB_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEEGOPAD_ANX7428 policy<{'amd64': 'm'}> +CONFIG_MEGARAID_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MEGARAID_MAILBOX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEGARAID_MM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MEGARAID_NEWGEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MEGARAID_SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MELLANOX_PLATFORM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_MEMBARRIER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMBLOCK_KHO_SCRATCH policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_MEMCG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMCG_NMI_SAFETY_REQUIRES_ATOMIC policy<{'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_MEMCG_V1 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MEMFD_CREATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMORY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MEMORY_FAILURE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_MEMORY_HOTPLUG policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMORY_HOTREMOVE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMORY_ISOLATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMORY_NOTIFIER_ERROR_INJECT policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MEMREGION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEMSTICK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MEMSTICK_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MEMSTICK_JMICRON_38X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEMSTICK_R592 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEMSTICK_REALTEK_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEMSTICK_TIFM_MS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEMSTICK_UNSAFE_RESUME policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MEMTEST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEM_ALLOC_PROFILING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MEM_SOFT_DIRTY policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MENF21BMC_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MENZ069_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEN_A21_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MEN_Z188_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MERAKI_MX100 policy<{'amd64': 'm'}> +CONFIG_MESON6_TIMER policy<{'armhf': 'y'}> +CONFIG_MESON_CANVAS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESON_CLK_MEASURE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MESON_DDR_PMU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESON_EE_PM_DOMAINS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MESON_GXBB_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESON_GXL_PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESON_GX_SOCINFO policy<{'arm64': 'y'}> +CONFIG_MESON_IRQ_GPIO policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MESON_MX_AO_ARC_REMOTEPROC policy<{'armhf': 'm'}> +CONFIG_MESON_MX_SOCINFO policy<{'armhf': 'y'}> +CONFIG_MESON_SARADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESON_SECURE_PM_DOMAINS policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_MESON_SM policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_MESON_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESSAGE_LOGLEVEL_DEFAULT policy<{'amd64': '4', 'arm64': '4', 'armhf': '4', 'ppc64el': '4', 'riscv64': '4', 's390x': '4'}> +CONFIG_MFD_88PM800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_88PM805 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_88PM860X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_88PM886_PMIC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_AAT2870_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_AC100 policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MFD_ACER_A500_EC policy<{'armhf': 'm'}> +CONFIG_MFD_ACT8945A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ADP5585 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ALTERA_A10SR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MFD_ALTERA_SYSMGR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MFD_ARIZONA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ARIZONA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_ARIZONA_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MFD_AS3711 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_AS3722 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_AT91_USART policy<{'arm64': 'y'}> +CONFIG_MFD_ATC260X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ATC260X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_ATMEL_FLEXCOM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ATMEL_HLCDC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_AXP20X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_AXP20X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_AXP20X_RSB policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MFD_BCM590XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_BD9571MWV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_BQ257XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_CGBC policy<{'amd64': 'm'}> +CONFIG_MFD_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_MFD_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_CROS_EC_DEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_CS40L50_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_CS40L50_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_CS40L50_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_CS42L43 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_CS42L43_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_CS42L43_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_CS47L15 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_CS47L24 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_CS47L35 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_CS47L85 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_CS47L90 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_CS47L92 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_DA9052_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_DA9052_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_DA9055 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_DA9062 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_DA9063 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MFD_DA9150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_DLN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MFD_ENE_KB3930 policy<{'armhf': 'm'}> +CONFIG_MFD_EXYNOS_LPASS policy<{'armhf': 'n'}> +CONFIG_MFD_GATEWORKS_GSC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_HI6421_PMIC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_HI6421_SPMI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_HI655X_PMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_INTEL_LPSS policy<{'amd64': 'm'}> +CONFIG_MFD_INTEL_LPSS_ACPI policy<{'amd64': 'm'}> +CONFIG_MFD_INTEL_LPSS_PCI policy<{'amd64': 'm'}> +CONFIG_MFD_INTEL_M10_BMC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_INTEL_M10_BMC_PMCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_INTEL_M10_BMC_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_INTEL_PMC_BXT policy<{'amd64': 'm'}> +CONFIG_MFD_INTEL_QUARK_I2C_GPIO policy<{'amd64': 'm'}> +CONFIG_MFD_IQS62X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_JANZ_CMODIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_KEMPLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_KHADAS_MCU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_LM3533 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_LOCHNAGAR policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_LP3943 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_LP8788 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_LS2K_BMC_CORE policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_MFD_MACSMC policy<{'arm64': 'm'}> +CONFIG_MFD_MADERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MADERA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MADERA_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MAX14577 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MFD_MAX5970 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MAX7360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MAX77541 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MAX77620 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_MAX77650 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MAX77686 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_MAX77693 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MFD_MAX77705 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MAX77714 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MAX77759 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MAX77843 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_MAX8907 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MAX8925 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_MAX8997 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_MAX8998 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_MC13XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MC13XXX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MC13XXX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MFD_MENF21BMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MP2629 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MT6360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MT6370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MT6397 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_NTXEC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_NVEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_OCELOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_OMAP_USB_HOST policy<{'armhf': 'y'}> +CONFIG_MFD_PALMAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_PF1550 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_PM8XXX policy<{'armhf': 'm'}> +CONFIG_MFD_QCOM_PM8008 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_QCOM_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_QNAP_MCU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_RC5T583 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_RDC321X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_RETU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_RK8XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RK8XX_I2C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RK8XX_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RN5T618 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ROHM_BD71828 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ROHM_BD718XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ROHM_BD957XMUF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ROHM_BD96801 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RSMU_I2C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RSMU_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RT4831 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_RT5033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_RT5120 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SC27XX_PMIC policy<{'arm64': 'm'}> +CONFIG_MFD_SEC_ACPM policy<{'armhf': 'm'}> +CONFIG_MFD_SEC_CORE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_SEC_I2C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_SI476X_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SIMPLE_MFD_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_SKY81452 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_MFD_SM501_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_SMPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SPMI_PMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_STM32_LPTIMER policy<{'arm64': 'm'}> +CONFIG_MFD_STM32_TIMERS policy<{'arm64': 'm'}> +CONFIG_MFD_STMFX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_STMPE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_STPMIC1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_SUN4I_GPADC policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MFD_SUN6I_PRCM policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MFD_SY7636A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SYSCON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MFD_TC3589X policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_TI_AM335X_TSCADC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_MFD_TI_LMU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_TI_LP873X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_TI_LP87565 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_TN48M_CPLD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_TPS65086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_TPS65090 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_TPS65218 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_TPS65219 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_TPS6586X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_TPS65910 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_TPS65912 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_TPS65912_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MFD_TPS65912_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_TPS6594 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_TPS6594_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_TPS6594_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_TQMX86 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_TWL4030_AUDIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_UPBOARD_FPGA policy<{'amd64': 'm'}> +CONFIG_MFD_VEXPRESS_SYSREG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MFD_VIPERBOARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MFD_VX855 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_WCD934X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_WM5102 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM5110 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM831X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM831X_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_WM831X_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM8350 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM8350_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_WM8400 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_WM8994 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_WM8997 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM8998 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MGBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MHI_BUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MHI_BUS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MHI_BUS_EP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MHI_BUS_PCI_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MHI_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MHI_WWAN_CTRL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MHI_WWAN_MBIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_KERNEL policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MHZ19B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MICREL_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MICROCHIP_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MICROCHIP_PHY_RDS_PTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MICROCHIP_PIT64B policy<{'arm64': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_MICROCHIP_T1S_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MICROCHIP_T1_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MICROCODE policy<{'amd64': 'y'}> +CONFIG_MICROCODE_DBG policy<{'amd64': 'n'}> +CONFIG_MICROCODE_LATE_LOADING policy<{'amd64': 'n'}> +CONFIG_MICROSEMI_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MICROSOFT_MANA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_MIGHT_HAVE_CACHE_L2X0 policy<{'armhf': 'y'}> +CONFIG_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MII policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MILBEAUT_HDMAC policy<{'armhf': 'm'}> +CONFIG_MILBEAUT_TIMER policy<{'armhf': 'y'}> +CONFIG_MILBEAUT_XDMAC policy<{'armhf': 'm'}> +CONFIG_MINIX_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MINIX_SUBPARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MIN_HEAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MIPI_I3C_HCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MIPI_I3C_HCI_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISC_ALCOR_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MISC_FILESYSTEMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MISC_RP1 policy<{'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MISC_RTSX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISC_RTSX_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MISC_RTSX_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY policy<{'arm64': 'y'}> +CONFIG_MITIGATION_CALL_DEPTH_TRACKING policy<{'amd64': 'y'}> +CONFIG_MITIGATION_GDS policy<{'amd64': 'n'}> +CONFIG_MITIGATION_IBPB_ENTRY policy<{'amd64': 'y'}> +CONFIG_MITIGATION_IBRS_ENTRY policy<{'amd64': 'y'}> +CONFIG_MITIGATION_ITS policy<{'amd64': 'y'}> +CONFIG_MITIGATION_L1TF policy<{'amd64': 'y'}> +CONFIG_MITIGATION_MDS policy<{'amd64': 'y'}> +CONFIG_MITIGATION_MMIO_STALE_DATA policy<{'amd64': 'y'}> +CONFIG_MITIGATION_PAGE_TABLE_ISOLATION policy<{'amd64': 'y'}> +CONFIG_MITIGATION_RETBLEED policy<{'amd64': 'y'}> +CONFIG_MITIGATION_RETHUNK policy<{'amd64': 'y'}> +CONFIG_MITIGATION_RETPOLINE policy<{'amd64': 'y'}> +CONFIG_MITIGATION_RFDS policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SLS policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SPECTRE_BHI policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SPECTRE_V1 policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SPECTRE_V2 policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SRBDS policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SRSO policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SSB policy<{'amd64': 'y'}> +CONFIG_MITIGATION_TAA policy<{'amd64': 'y'}> +CONFIG_MITIGATION_TSA policy<{'amd64': 'y'}> +CONFIG_MITIGATION_UNRET_ENTRY policy<{'amd64': 'y'}> +CONFIG_MITIGATION_VMSCAPE policy<{'amd64': 'y'}> +CONFIG_MLX4_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLX4_CORE_GEN2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX4_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX4_EN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLX4_EN_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX4_INFINIBAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLX5_BRIDGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_CLS_ACT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLX5_CORE_EN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_CORE_EN_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_CORE_IPOIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_DPLL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MLX5_EN_ARFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_EN_IPSEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_EN_PSP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLX5_EN_RXNFC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_EN_TLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_ESWITCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_FPGA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_HW_STEERING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_INFINIBAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLX5_MACSEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_MPFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_SF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MLX5_SF_MANAGER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLX5_SW_STEERING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_TC_CT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_TC_SAMPLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_VDPA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLX5_VDPA_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLX5_VDPA_STEERING_DEBUG policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLX5_VFIO_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MLX90614 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLX90632 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLX90635 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLXBF_BOOTCTL policy<{'arm64': 'm'}> +CONFIG_MLXBF_GIGE policy<{'arm64': 'm'}> +CONFIG_MLXBF_PMC policy<{'arm64': 'm'}> +CONFIG_MLXBF_TMFIFO policy<{'arm64': 'm'}> +CONFIG_MLXFW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLXREG_DPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MLXREG_HOTPLUG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MLXREG_IO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MLXREG_LC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MLXSW_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLXSW_CORE_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLXSW_CORE_THERMAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLXSW_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MLXSW_MINIMAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLXSW_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLXSW_SPECTRUM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLXSW_SPECTRUM_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX_PLATFORM policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_MLX_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMA7455 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA7455_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA7455_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA7660 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA8452 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA9551 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA9551_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA9553 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MMC35240 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC5633 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMCONF_FAM10H policy<{'amd64': 'y'}> +CONFIG_MMC_ALCOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_ARMMMCI policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_MMC_BLOCK_MINORS policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8'}> +CONFIG_MMC_CAVIUM_THUNDERX policy<{'arm64': 'm'}> +CONFIG_MMC_CB710 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_CQHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MMC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MMC_DW policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_BLUEFIELD policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_EXYNOS policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_HI3798CV200 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_HI3798MV200 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_K3 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_PCI policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_PLTFM policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_HSQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_LITEX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_MESON_GX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_MESON_MX_SDHC policy<{'armhf': 'm'}> +CONFIG_MMC_MESON_MX_SDIO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_MTK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_MVSDIO policy<{'armhf': 'm'}> +CONFIG_MMC_MXC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_OMAP policy<{'armhf': 'm'}> +CONFIG_MMC_OWL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_QCOM_DML policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MMC_REALTEK_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_REALTEK_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_RICOH_MMC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MMC_SDHCI_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_AM654 policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER policy<{'ppc64el': 'y'}> +CONFIG_MMC_SDHCI_BST policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_CADENCE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_DOVE policy<{'armhf': 'm'}> +CONFIG_MMC_SDHCI_ESDHC_IMX policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_MMC_SDHCI_EXTERNAL_DMA policy<{'arm64': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_MMC_SDHCI_F_SDH30 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_IO_ACCESSORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MMC_SDHCI_MILBEAUT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_MSM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SDHCI_NPCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SDHCI_OF_ARASAN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_OF_ASPEED policy<{'armhf': 'm'}> +CONFIG_MMC_SDHCI_OF_AT91 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_OF_DWCMSHC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_OF_ESDHC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_MMC_SDHCI_OF_HLWD policy<{'ppc64el': 'm'}> +CONFIG_MMC_SDHCI_OF_MA35D1 policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_OF_SPARX5 policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_OMAP policy<{'arm64': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_MMC_SDHCI_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_PXAV2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SDHCI_PXAV3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SDHCI_S3C policy<{'armhf': 'n'}> +CONFIG_MMC_SDHCI_SPRD policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SDHCI_UHS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_XENON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHI policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_MMC_SDHI_INTERNAL_DMAC policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_MMC_SDHI_SYS_DMAC policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_MMC_SDRICOH_CS policy<{'amd64': 'm'}> +CONFIG_MMC_SH_MMCIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_STM32_SDMMC policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_MMC_SUNPLUS policy<{'armhf': 'm'}> +CONFIG_MMC_SUNXI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MMC_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MMC_TIFM_SD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_TMIO_CORE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_TOSHIBA_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_USDHI6ROL0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_USHC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_VIA_SDMMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_VUB300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_WBSD policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_MMIOTRACE policy<{'amd64': 'y'}> +CONFIG_MMIOTRACE_TEST policy<{'amd64': 'n'}> +CONFIG_MMIOWB policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MMP_PDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMP_TDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MMU_GATHER_MERGE_VMAS policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_MMU_GATHER_NO_GATHER policy<{'s390x': 'y'}> +CONFIG_MMU_GATHER_PAGE_SIZE policy<{'ppc64el': 'y'}> +CONFIG_MMU_GATHER_RCU_TABLE_FREE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MMU_GATHER_TABLE_FREE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MMU_LAZY_TLB_REFCOUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MMU_LAZY_TLB_SHOOTDOWN policy<{'ppc64el': 'y'}> +CONFIG_MMU_NOTIFIER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MM_ID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODPROBE_PATH policy<{'amd64': '"/sbin/modprobe"', 'arm64': '"/sbin/modprobe"', 'armhf': '"/sbin/modprobe"', 'ppc64el': '"/sbin/modprobe"', 'riscv64': '"/sbin/modprobe"', 's390x': '"/sbin/modprobe"'}> +CONFIG_MODULES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULES_TREE_LOOKUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULES_USE_ELF_REL policy<{'armhf': 'y'}> +CONFIG_MODULES_USE_ELF_RELA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_ALLOW_BTF_MISMATCH policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_COMPRESS_ALL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_COMPRESS_GZIP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_COMPRESS_XZ policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_DECOMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_FORCE_LOAD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_FORCE_UNLOAD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SECTIONS policy<{'riscv64': 'y'}> +CONFIG_MODULE_SIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_SIG_ALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_SIG_FORCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_FORMAT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_SIG_HASH policy<{'amd64': '"sha512"', 'arm64': '"sha512"', 'armhf': '"sha512"', 'ppc64el': '"sha512"', 'riscv64': '"sha512"', 's390x': '"sha512"'}> +CONFIG_MODULE_SIG_KEY policy<{'amd64': '"certs/signing_key.pem"', 'arm64': '"certs/signing_key.pem"', 'armhf': '"certs/signing_key.pem"', 'ppc64el': '"certs/signing_key.pem"', 'riscv64': '"certs/signing_key.pem"', 's390x': '"certs/signing_key.pem"'}> +CONFIG_MODULE_SIG_KEY_TYPE_ECDSA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_44 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_65 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_87 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_RSA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_SIG_SHA256 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_SHA384 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_SHA3_256 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_SHA3_384 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_SHA3_512 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_SHA512 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_SRCVERSION_ALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_UNLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_UNLOAD_TAINT_TRACKING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MONREADER policy<{'s390x': 'm'}> +CONFIG_MONWRITER policy<{'s390x': 'm'}> +CONFIG_MOST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MOST_CDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_COMPONENTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_DIM2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_SND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_USB_HDM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_VIDEO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOTORCOMM_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MOUSE_APPLETOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_BCM5974 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_CYAPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_ELAN_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_ELAN_I2C_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_ELAN_I2C_SMBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_PS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_PS2_ALPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_BYD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_CYPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_ELANTECH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_ELANTECH_SMBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_FOCALTECH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_LIFEBOOK policy<{'amd64': 'y'}> +CONFIG_MOUSE_PS2_LOGIPS2PP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_SENTELIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_SMBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_SYNAPTICS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_TOUCHKIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_TRACKPOINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_VMMOUSE policy<{'amd64': 'y'}> +CONFIG_MOUSE_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_SYNAPTICS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_SYNAPTICS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_VSXXXAA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOXA_INTELLIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOXA_SMARTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOXTET policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MP2629_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPIC policy<{'ppc64el': 'y'}> +CONFIG_MPIC_MSGR policy<{'ppc64el': 'n'}> +CONFIG_MPILIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MPL115 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPL115_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPL115_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPL3115 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MPLS_IPTUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MPLS_ROUTING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MPRLS0025PA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPRLS0025PA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPRLS0025PA_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPROFILE_KERNEL policy<{'ppc64el': 'y'}> +CONFIG_MPTCP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MPTCP_IPV6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MPU3050 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPU3050_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MQ_IOSCHED_DEADLINE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MQ_IOSCHED_KYBER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MRP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MS5611 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MS5611_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MS5611_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MS5637 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSA311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSC313E_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_MSCC_OCELOT_SWITCH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSCC_OCELOT_SWITCH_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSDOS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MSDOS_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MSE102X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSHV_ROOT policy<{'amd64': 'm', 'arm64-generic': 'm'}> +CONFIG_MSI_BITMAP_SELFTEST policy<{'ppc64el': 'n'}> +CONFIG_MSI_EC policy<{'amd64': 'm'}> +CONFIG_MSI_LAPTOP policy<{'amd64': 'm'}> +CONFIG_MSI_WMI policy<{'amd64': 'm'}> +CONFIG_MSI_WMI_PLATFORM policy<{'amd64': 'm'}> +CONFIG_MSM_GCC_8660 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_GCC_8909 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_GCC_8916 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8917 policy<{'arm64': 'm'}> +CONFIG_MSM_GCC_8939 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8953 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8960 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_GCC_8974 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_GCC_8976 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8994 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8996 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8998 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GPUCC_8998 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_IOMMU policy<{'armhf': 'n'}> +CONFIG_MSM_LCC_8960 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_MMCC_8960 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_MMCC_8974 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_MMCC_8994 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_MMCC_8996 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_MMCC_8998 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSPRO_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSTAR_MSC313_CPUPLL policy<{'armhf': 'y'}> +CONFIG_MSTAR_MSC313_MPLL policy<{'armhf': 'y'}> +CONFIG_MST_IRQ policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MS_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7601U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7603E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7615E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7615_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7622_WMAC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MT7663S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7663U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7663_USB_SDIO_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76_CONNAC_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MT76_NPU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MT76_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x02_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x02_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x0E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x0U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x0_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x2E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x2U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x2_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7915E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7921E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7921S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7921U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7921_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7925E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7925U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7925_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT792x_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT792x_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT798X_WMAC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MT7996E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7996_NPU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTDRAM_ERASE_SIZE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128'}> +CONFIG_MTDRAM_TOTAL_SIZE policy<{'amd64': '4096', 'arm64': '4096', 'armhf': '4096', 'ppc64el': '4096', 'riscv64': '4096'}> +CONFIG_MTD_ABSENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_AFS_PARTS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_AMD76XROM policy<{'amd64': 'm'}> +CONFIG_MTD_BCM47XXSFLASH policy<{'armhf': 'm'}> +CONFIG_MTD_BLKDEVS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_BLOCK2MTD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_BLOCK_RO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CFI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CFI_ADV_OPTIONS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_CFI_AMDSTD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CFI_I1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_CFI_I2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_CFI_INTELEXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CFI_STAA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CFI_UTIL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CK804XROM policy<{'amd64': 'm'}> +CONFIG_MTD_CMDLINE_PARTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MTD_COMPLEX_MAPPINGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_DATAFLASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_DATAFLASH_OTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_DATAFLASH_WRITE_VERIFY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_ESB2ROM policy<{'amd64': 'm'}> +CONFIG_MTD_GEN_PROBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_HYPERBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_ICHXROM policy<{'amd64': 'm'}> +CONFIG_MTD_IMPA7 policy<{'armhf': 'm'}> +CONFIG_MTD_INTEL_DG policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_MTD_JEDECPROBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_L440GX policy<{'amd64': 'm'}> +CONFIG_MTD_LPDDR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_LPDDR2_NVM policy<{'armhf': 'm'}> +CONFIG_MTD_MAP_BANK_WIDTH_1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_MAP_BANK_WIDTH_2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_MAP_BANK_WIDTH_4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_MCHP23K256 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_MCHP48L640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_MTDRAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_ARASAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_BRCMNAND policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_BCM63XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_BCMBCA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_BRCMSTB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_IPROC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_CADENCE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_CAFE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_DENALI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_DENALI_DT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_DENALI_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_DISKONCHIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MTD_NAND_ECC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_NAND_ECC_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_ECC_MXIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_NAND_ECC_SW_BCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_NAND_ECC_SW_HAMMING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_NAND_FSL_IFC policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_GPMI_NAND policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_HISI504 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_INTEL_LGM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_MARVELL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_MTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_MXC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_MXIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_NANDSIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_NUVOTON_MA35 policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_OMAP2 policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_MTD_NAND_OMAP_BCH policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTD_NAND_OMAP_BCH_BUILD policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_MTD_NAND_ORION policy<{'armhf': 'm'}> +CONFIG_MTD_NAND_PL35X policy<{'armhf': 'm'}> +CONFIG_MTD_NAND_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_RENESAS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_RICOH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_STM32_FMC2 policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_SUNXI policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MTD_NAND_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_VF610_NFC policy<{'armhf': 'n'}> +CONFIG_MTD_NETtel policy<{'amd64': 'm'}> +CONFIG_MTD_ONENAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_ONENAND_2X_PROGRAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_ONENAND_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_ONENAND_OTP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_OOPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PARSER_TRX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_PARTITIONED_MASTER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PCMCIA policy<{'amd64': 'm'}> +CONFIG_MTD_PCMCIA_ANONYMOUS policy<{'amd64': 'n'}> +CONFIG_MTD_PHRAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PHYSMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PHYSMAP_COMPAT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_PHYSMAP_GEMINI policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MTD_PHYSMAP_GPIO_ADDR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_PHYSMAP_IXP4XX policy<{'armhf': 'y'}> +CONFIG_MTD_PHYSMAP_OF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_PHYSMAP_VERSATILE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MTD_PLATRAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PMC551 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PMC551_BUGFIX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_PMC551_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_POWERNV_FLASH policy<{'ppc64el': 'm'}> +CONFIG_MTD_PSTORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_QCOMSMEM_PARTS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_QINFO_PROBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_RAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK policy<{'amd64': '-1', 'arm64': '-1', 'armhf': '-1', 'ppc64el': '-1', 'riscv64': '-1'}> +CONFIG_MTD_REDBOOT_PARTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_REDBOOT_PARTS_READONLY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_ROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SBC_GXX policy<{'amd64': 'm'}> +CONFIG_MTD_SCB2_FLASH policy<{'amd64': 'm'}> +CONFIG_MTD_SLRAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SM_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SPI_NAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SPI_NOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SPI_NOR_SWP_DISABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_SPI_NOR_SWP_KEEP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_SST25L policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SWAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_TESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_UBI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_UBI_BEB_LIMIT policy<{'amd64': '20', 'arm64': '20', 'armhf': '20', 'ppc64el': '20', 'riscv64': '20'}> +CONFIG_MTD_UBI_BLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_UBI_FASTMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_UBI_GLUEBI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_UBI_NVMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_UBI_WL_THRESHOLD policy<{'amd64': '4096', 'arm64': '4096', 'armhf': '4096', 'ppc64el': '4096', 'riscv64': '4096'}> +CONFIG_MTK_ADSP_IPC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_ADSP_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_CMDQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_CMDQ_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_CPUX_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_CQDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_DEVAPC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_DVFSRC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_GPUEB_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_HSDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_INFRACFG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_IOMMU policy<{'arm64': 'm', 'armhf': 'n'}> +CONFIG_MTK_IOMMU_V1 policy<{'armhf': 'n'}> +CONFIG_MTK_LVTS_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_LVTS_THERMAL_DEBUGFS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_MFG_PM_DOMAIN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_MMSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_NET_PHYLIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTK_PMIC_WRAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_REGULATOR_COUPLER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_SCP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_SCPSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_SCPSYS_PM_DOMAINS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_SMI policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_MTK_SOCINFO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_SOC_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_SVS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_T7XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTK_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_UART_APDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_VCP_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTRR policy<{'amd64': 'y'}> +CONFIG_MTRR_SANITIZER policy<{'amd64': 'y'}> +CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT policy<{'amd64': '1'}> +CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT policy<{'amd64': '1'}> +CONFIG_MULTIPLEXER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MULTIUSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MUSB_PIO_ONLY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MUTEX_SPIN_ON_OWNER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MUX_ADG792A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MUX_ADGS1408 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MUX_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MUX_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MUX_MMIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MV643XX_ETH policy<{'armhf': 'm'}> +CONFIG_MVEBU_CLK_COMMON policy<{'armhf': 'y'}> +CONFIG_MVEBU_CLK_COREDIV policy<{'armhf': 'y'}> +CONFIG_MVEBU_CLK_CPU policy<{'armhf': 'y'}> +CONFIG_MVEBU_DEVBUS policy<{'armhf': 'y'}> +CONFIG_MVEBU_GICP policy<{'arm64': 'y'}> +CONFIG_MVEBU_ICU policy<{'arm64': 'y'}> +CONFIG_MVEBU_MBUS policy<{'armhf': 'y'}> +CONFIG_MVEBU_ODMI policy<{'arm64': 'y'}> +CONFIG_MVEBU_PIC policy<{'arm64': 'y'}> +CONFIG_MVEBU_SEI policy<{'arm64': 'y'}> +CONFIG_MVMDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MVNETA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MVNETA_BM_ENABLE policy<{'armhf': 'n'}> +CONFIG_MVPP2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MVPP2_PTP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MV_XOR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MV_XOR_V2 policy<{'arm64': 'y'}> +CONFIG_MWIFIEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MWIFIEX_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MWIFIEX_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MWIFIEX_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MWL8K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MXC4005 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MXC6255 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MXC_CLK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MXC_CLK_SCU policy<{'arm64': 'y'}> +CONFIG_MXC_TZIC policy<{'armhf': 'y'}> +CONFIG_MXM_WMI policy<{'amd64': 'm'}> +CONFIG_MXS_DMA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MYRI10GE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MYRI10GE_DCA policy<{'amd64': 'y'}> +CONFIG_NAMESPACES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NATIONAL_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NATSEMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NAU7802 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NBPFAXI_DMA policy<{'armhf': 'm'}> +CONFIG_NCN26000_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NCSI_OEM_CMD_GET_MAC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NCSI_OEM_CMD_KEEP_PHY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NCT6694_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NCT7201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NDC_DIS_DYNAMIC_CACHING policy<{'arm64': 'y'}> +CONFIG_ND_BTT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ND_CLAIM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ND_PFN policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NE2K_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NEED_DMA_MAP_STATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP policy<{'arm64': 'y'}> +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NEED_PROC_VMCORE_DEVICE_RAM policy<{'s390x': 'y'}> +CONFIG_NEED_SG_DMA_FLAGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NEED_SG_DMA_LENGTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_NEED_SRCU_NMI_SAFE policy<{'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_NEED_TASKS_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NEON policy<{'armhf': 'y'}> +CONFIG_NET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETCONSOLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETCONSOLE_DYNAMIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETCONSOLE_EXTENDED_LOG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NETDEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETDEVSIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETDEV_NOTIFIER_ERROR_INJECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NETFILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_ADVANCED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_BPF_LINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_CONNCOUNT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_EGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_FAMILY_ARP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_FAMILY_BRIDGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_INGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_NETLINK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_NETLINK_ACCT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_NETLINK_GLUE_CT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_NETLINK_HOOK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_NETLINK_LOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_NETLINK_OSF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_NETLINK_QUEUE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_SKIP_EGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_SYNPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XTABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XTABLES_COMPAT policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_NETFILTER_XTABLES_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_XT_CONNMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_BPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CGROUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CLUSTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_COMMENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNBYTES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNLABEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNTRACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_DCCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_DEVGROUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_DSCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_ECN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_ESP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_HL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_IPCOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_IPRANGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_IPVS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_L2TP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_LENGTH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_LIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_MAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_MARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_MULTIPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_NFACCT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_OSF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_OWNER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_PHYSDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_PKTTYPE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_POLICY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_QUOTA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_RATEEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_REALM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_RECENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_SCTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_SOCKET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_STATE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_STATISTIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_STRING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_TCPMSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_TIME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_U32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_SET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_AUDIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CHECKSUM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CLASSIFY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CONNMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_DSCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_HL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_HMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_IDLETIMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_LED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NETFILTER_XT_TARGET_LOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_MARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_MASQUERADE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NETMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NFLOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NFQUEUE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NOTRACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_RATEEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_REDIRECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_SECMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TCPMSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TEE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TRACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFS_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFS_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFS_SUPPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETKIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETLABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETLINK_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETPOLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETWORK_FILESYSTEMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETWORK_SECMARK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETXEN_NIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NET_9P_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_9P_FD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_9P_RDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_9P_USBG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_9P_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_9P_XEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_NET_ACT_BPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_CONNMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_CSUM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_CT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_CTINFO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_GACT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_GATE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_IFE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_ACT_MIRRED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_MPLS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_PEDIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_POLICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_SAMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_SIMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_SKBEDIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_SKBMOD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_TUNNEL_KEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_VLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_AIROHA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NET_AIROHA_FLOW_STATS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NET_AIROHA_NPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NET_CALXEDA_XGMAC policy<{'armhf': 'm'}> +CONFIG_NET_CLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_CLS_ACT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_CLS_BASIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_BPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_CGROUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_FLOW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_FLOWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_FW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_MATCHALL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_ROUTE4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_U32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_CRC32C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_DEVLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_DEVMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_DEV_REFCNT_TRACKER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_DSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NET_DSA_AR9331 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_BCM_SF2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_KS8995 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_LANTIQ_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_LANTIQ_GSWIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_LOOP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MICROCHIP_KSZ_PTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_MICROCHIP_KSZ_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MSCC_FELIX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n'}> +CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MSCC_OCELOT_EXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_NET_DSA_MSCC_SEVILLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MT7530 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MT7530_MDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MT7530_MMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MV88E6060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MV88E6XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MV88E6XXX_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_MV88E6XXX_PTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_MXL862 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MXL_GSW1XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_QCA8K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_REALTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_REALTEK_MDIO policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_REALTEK_RTL8365MB policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_REALTEK_RTL8366RB policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_REALTEK_RTL8366RB_LEDS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_REALTEK_SMI policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_RZN1_A5PSW policy<{'armhf': 'm'}> +CONFIG_NET_DSA_SJA1105 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_SJA1105_PTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_SJA1105_TAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_SJA1105_VL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_SMSC_LAN9303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_SMSC_LAN9303_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_SMSC_LAN9303_MDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_AR9331 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_LEGACY_FCS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_PREPEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_DSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_DSA_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_EDSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_GSWIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_HELLCREEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_KSZ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_LAN9303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_MTK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_MXL_862XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_MXL_GSW1XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_NONE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_OCELOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_OCELOT_8021Q policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_QCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_RTL4_A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_RTL8_4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_RZN1_A5PSW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_SJA1105 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_TRAILER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_VSC73XX_8021Q policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_XRS700X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_YT921X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_VITESSE_VSC73XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_XRS700X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_XRS700X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_XRS700X_MDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_YT921X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_EGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_EMATCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_EMATCH_CANID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_EMATCH_CMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_IPSET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_IPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_META policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_NBYTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_STACK policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32', 's390x': '32'}> +CONFIG_NET_EMATCH_TEXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_U32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_FAILOVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_FC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_FLOW_LIMIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_FOU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_FOU_IP_TUNNELS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_HANDSHAKE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_IEEE8021Q_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_IFE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_INGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_IPGRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_IPGRE_BROADCAST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_IPGRE_DEMUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_IPIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_IPVTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_IP_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_KEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_KEY_MIGRATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_L3_MASTER_DEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_MPLS_GSO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_NCSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_NSH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_NS_REFCNT_TRACKER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_PKTGEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_POLL_CONTROLLER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_PTP_CLASSIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_REDIRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_RX_BUSY_POLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SCH_BPF policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SCH_CAKE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_CBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_CHOKE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_CODEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_DEFAULT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_SCH_DRR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_DUALPI2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_ETF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_ETS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_FIFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SCH_FQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_FQ_CODEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_FQ_PIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_GRED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_HFSC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_HHF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_HTB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_INGRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_MQPRIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_MQPRIO_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_MULTIQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_NETEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_PIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_PLUG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_PRIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_QFQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_RED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_SFB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_SFQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_SKBPRIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_TAPRIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_TBF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_TEQL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SELFTESTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SHAPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SOCK_MSG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_TC_SKB_EXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_TEAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TEAM_MODE_BROADCAST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TEAM_MODE_LOADBALANCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TEAM_MODE_RANDOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TEAM_MODE_ROUNDROBIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TULIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_UDP_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_VENDOR_3COM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_8390 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_VENDOR_ACTIONS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NET_VENDOR_ADAPTEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_ADI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_VENDOR_AGERE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_AIROHA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NET_VENDOR_ALACRITECH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_ALLWINNER policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_NET_VENDOR_AMAZON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_AMD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_AQUANTIA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_ARC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_ASIX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_ATHEROS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_BROADCOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_BROCADE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_CADENCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_CAVIUM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_CHELSIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_CIRRUS policy<{'amd64': '-', 'armhf': 'y'}> +CONFIG_NET_VENDOR_CISCO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_CORTINA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_DAVICOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_DEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_DLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_ENGLEDER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_EZCHIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_FARADAY policy<{'armhf': 'y'}> +CONFIG_NET_VENDOR_FREESCALE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_NET_VENDOR_FUNGIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_GOOGLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_HISILICON policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_VENDOR_HUAWEI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_I825XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_VENDOR_IBM policy<{'ppc64el': 'y'}> +CONFIG_NET_VENDOR_INTEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_LITEX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MARVELL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MEDIATEK policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_NET_VENDOR_MELLANOX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_META policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_MICREL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MICROCHIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MICROSEMI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MICROSOFT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MUCSE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_MYRI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_NATSEMI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_NETRONOME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_NI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_NVIDIA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_OKI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_PENSANDO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_QLOGIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_QUALCOMM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_RDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_REALTEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_RENESAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_ROCKER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SAMSUNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SEEQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SILAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SMSC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SOCIONEXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_SOLARFLARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_STMICRO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SUN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SUNPLUS policy<{'armhf': 'y'}> +CONFIG_NET_VENDOR_SYNOPSYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_TEHUTI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_TI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_VERTEXCOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_VIA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_WANGXUN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_WIZNET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_XILINX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_XIRCOM policy<{'amd64': 'y'}> +CONFIG_NET_VRF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_XGENE policy<{'arm64': 'm'}> +CONFIG_NET_XGENE_V2 policy<{'arm64': 'm'}> +CONFIG_NET_XGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NEW_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NFC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NFC_DIGITAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_FDP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_FDP_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_HCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MEI_PHY policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_NFC_MICROREAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MICROREAD_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MICROREAD_MEI policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MRVL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MRVL_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MRVL_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MRVL_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MRVL_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_NCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_NCI_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_NCI_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_NXP_NCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_NXP_NCI_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN532_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN533 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN533_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN533_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN544 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN544_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN544_MEI policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PORT100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_S3FWRN5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_S3FWRN5_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_S3FWRN82_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_SHDLC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NFC_SIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST21NFCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST21NFCA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST95HF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST_NCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST_NCI_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST_NCI_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_TRF7970A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_VIRTUAL_NCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFIT_SECURITY_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_NFP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NFP_APP_ABM_NIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NFP_APP_FLOWER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NFP_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_NFP_NET_IPSEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NFSD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFSD_BLOCKLAYOUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_FLEXFILELAYOUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_LEGACY_CLIENT_TRACKING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFSD_PNFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_SCSILAYOUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_V2 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFSD_V3_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_V4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_V4_2_INTER_SSC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_V4_POSIX_ACLS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFSD_V4_SECURITY_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_ACL_SUPPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFS_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_DISABLE_UDP_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFS_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_LOCALIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFS_SWAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_USE_KERNEL_DNS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_USE_LEGACY_DNS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFS_V2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFS_V3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFS_V3_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_V4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFS_V4_0 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN policy<{'amd64': '"kernel.org"', 'arm64': '"kernel.org"', 'armhf': '"kernel.org"', 'ppc64el': '"kernel.org"', 'riscv64': '"kernel.org"', 's390x': '"kernel.org"'}> +CONFIG_NFS_V4_1_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_V4_2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_V4_2_READ_PLUS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFS_V4_2_SSC_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_V4_SECURITY_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFTL_RW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NFT_BRIDGE_META policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_BRIDGE_REJECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_COMPAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_COMPAT_ARP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_CONNLIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_CT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_DUP_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_DUP_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_DUP_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_EXTHDR_DCCP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFT_FIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FIB_INET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FIB_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FIB_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FIB_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FLOW_OFFLOAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FWD_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_HASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_LIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_LOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_MASQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_NUMGEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_OSF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_QUEUE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_QUOTA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REDIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REJECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REJECT_INET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REJECT_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REJECT_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REJECT_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_SOCKET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_SYNPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_TPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_XFRM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_AMANDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_BROADCAST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_FTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_H323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_IRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_LABELS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_MARK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_NETBIOS_NS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_OVS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_PPTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_PROCFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NF_CONNTRACK_SANE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_SECMARK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_SIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_SNMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_TFTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_TIMEOUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_TIMESTAMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_ZONES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CT_NETLINK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CT_NETLINK_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CT_NETLINK_TIMEOUT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CT_PROTO_GRE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CT_PROTO_SCTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_DEFRAG_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_DEFRAG_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_DUP_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_DUP_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_DUP_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_FLOW_TABLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_FLOW_TABLE_INET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_FLOW_TABLE_PROCFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NF_LOG_ARP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_LOG_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_LOG_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_LOG_SYSLOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_AMANDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_FTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_H323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_IRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_MASQUERADE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_NAT_OVS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_NAT_PPTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_REDIRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_NAT_SIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_SNMP_BASIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_TFTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_REJECT_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_REJECT_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_SOCKET_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_SOCKET_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_TABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_TABLES_ARP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_TABLES_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_TABLES_INET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_TABLES_IPV4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_TABLES_IPV6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_TABLES_NETDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_TPROXY_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_TPROXY_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NGBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NGBEVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NI903X_WDT policy<{'amd64': 'm'}> +CONFIG_NIC7018_WDT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_NILFS2_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NINTENDO_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NITRO_ENCLAVES policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_NIU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NI_XGE_MANAGEMENT_ENET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NL80211_TESTMODE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_NLATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NLMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ASCII policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_1250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_1251 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_437 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NLS_CODEPAGE_737 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_775 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_850 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_852 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_855 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_857 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_860 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_861 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_862 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_863 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_864 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_865 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_866 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_869 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_874 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_932 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_936 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_949 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_950 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_DEFAULT policy<{'amd64': '"utf8"', 'arm64': '"utf8"', 'armhf': '"utf8"', 'ppc64el': '"utf8"', 'riscv64': '"utf8"', 's390x': '"utf8"'}> +CONFIG_NLS_ISO8859_1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_13 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_14 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_15 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_7 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_KOI8_R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_KOI8_U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_CELTIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_CENTEURO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_CROATIAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_CYRILLIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_GAELIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_GREEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_ICELAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_INUIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_ROMAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_ROMANIAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_TURKISH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_UCS2_UTILS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_UTF8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NMI_CHECK_CPU policy<{'amd64': 'y'}> +CONFIG_NMI_IPI policy<{'ppc64el': 'y'}> +CONFIG_NOA1305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NODES_SHIFT policy<{'amd64': '10', 'arm64': '6', 'ppc64el': '8', 'riscv64': '2', 's390x': '1'}> +CONFIG_NONPORTABLE policy<{'riscv64': 'n'}> +CONFIG_NONSTATIC_KERNEL policy<{'ppc64el': 'y'}> +CONFIG_NOP_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NOTIFIER_ERROR_INJECTION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NOUVEAU_DEBUG policy<{'amd64': '5', 'arm64': '5', 'armhf': '5', 'ppc64el': '5', 'riscv64': '5'}> +CONFIG_NOUVEAU_DEBUG_DEFAULT policy<{'amd64': '3', 'arm64': '3', 'armhf': '3', 'ppc64el': '3', 'riscv64': '3'}> +CONFIG_NOUVEAU_DEBUG_MMU policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_NOUVEAU_DEBUG_PUSH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_NOUVEAU_PLATFORM_DRIVER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NOZOMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NO_HZ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NO_HZ_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NO_IOPORT_MAP policy<{'armhf': 'y', 's390x': 'y'}> +CONFIG_NO_PAGE_MAPCOUNT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NPCM7XX_KCS_IPMI_BMC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NPCM7XX_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NPCM7XX_WATCHDOG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NPCM_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NR_CPUS_DEFAULT policy<{'amd64': '8192'}> +CONFIG_NR_CPUS_RANGE_BEGIN policy<{'amd64': '8192'}> +CONFIG_NR_CPUS_RANGE_END policy<{'amd64': '8192'}> +CONFIG_NR_IRQS policy<{'ppc64el': '512'}> +CONFIG_NS83820 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NTB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NTB_AMD policy<{'amd64': 'n'}> +CONFIG_NTB_EPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_IDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_INTEL policy<{'amd64': 'm'}> +CONFIG_NTB_MSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NTB_MSI_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_NTB_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_PERF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_PINGPONG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_SWITCHTEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_TOOL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_TRANSPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTFS3_64BIT_CLUSTER policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NTFS3_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NTFS3_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NTFS3_LZX_XPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NTFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NTFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NTFS_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NTSYNC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NULL_TTY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NUMA_BALANCING policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NUMA_KEEP_MEMINFO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NUMA_MEMBLKS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_NUMA_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVDIMM_DAX policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVDIMM_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVDIMM_PFN policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVDIMM_SECURITY_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_NVEC_PAZ00 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVEC_POWER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVGRACE_GPU_VFIO_PCI policy<{'arm64': 'm'}> +CONFIG_NVHE_EL2_DEBUG policy<{'arm64': 'n'}> +CONFIG_NVIDIA_CARMEL_CNP_ERRATUM policy<{'arm64': 'y'}> +CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU policy<{'arm64': 'm'}> +CONFIG_NVIDIA_SHIELD_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVIDIA_TEGRA410_C2C_PMU policy<{'arm64': 'm'}> +CONFIG_NVIDIA_TEGRA410_CMEM_LATENCY_PMU policy<{'arm64': 'm'}> +CONFIG_NVIDIA_WMI_EC_BACKLIGHT policy<{'amd64': 'm'}> +CONFIG_NVMEM_APPLE_EFUSES policy<{'arm64': 'm'}> +CONFIG_NVMEM_APPLE_SPMI policy<{'arm64': 'm'}> +CONFIG_NVMEM_IMX_IIM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_IMX_OCOTP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_IMX_OCOTP_ELE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_IMX_OCOTP_SCU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_LAYERSCAPE_SFP policy<{'arm64': 'm'}> +CONFIG_NVMEM_LAYOUTS policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVMEM_LAYOUT_ONIE_TLV policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_LAYOUT_SL28_VPD policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_MAX77759 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_MESON_EFUSE policy<{'arm64': 'm', 'arm64-generic-64k': '-'}> +CONFIG_NVMEM_MESON_MX_EFUSE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_MTK_EFUSE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_QCOM_QFPROM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_QCOM_SEC_QFPROM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_QNAP_MCU_EEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_RAVE_SP_EEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_RCAR_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_REBOOT_MODE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_RMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NVMEM_ROCKCHIP_EFUSE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_ROCKCHIP_OTP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_S32G_OCOTP policy<{'arm64': 'm'}> +CONFIG_NVMEM_SC27XX_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_SNVS_LPGPR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_SPMI_SDAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_SPRD_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_STM32_BSEC_OPTEE_TA policy<{'arm64': 'y'}> +CONFIG_NVMEM_STM32_ROMEM policy<{'arm64': 'm'}> +CONFIG_NVMEM_SUNPLUS_OCOTP policy<{'armhf': 'm'}> +CONFIG_NVMEM_SUNXI_SID policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_NVMEM_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVMEM_U_BOOT_ENV policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_VF610_OCOTP policy<{'armhf': 'n'}> +CONFIG_NVMEM_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_NVME_APPLE policy<{'arm64': 'm'}> +CONFIG_NVME_AUTH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_FABRICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_HOST_AUTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVME_KEYRING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_MULTIPATH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_RDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_AUTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_TARGET_AUTH_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NVME_TARGET_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NVME_TARGET_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_FCLOOP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NVME_TARGET_LOOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_PASSTHRU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_TARGET_PCI_EPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_RDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_TCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_TCP_TLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_TCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TCP_TLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_VERBOSE_ERRORS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NVSW_SN2201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_NV_TCO policy<{'amd64': 'm'}> +CONFIG_NXP_C45_TJA11XX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NXP_CBTX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NXP_ENETC4 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_NXP_ENETC_PF_COMMON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_NXP_NETC_BLK_CTRL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_NXP_NETC_LIB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_NXP_NTMP policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_NXP_SAR_ADC policy<{'arm64': 'm'}> +CONFIG_NXP_STM_TIMER policy<{'arm64': 'y'}> +CONFIG_NXP_TJA11XX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_N_HDLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_OABI_COMPAT policy<{'armhf': 'n'}> +CONFIG_OA_TC6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OBJAGG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OBJTOOL policy<{'amd64': 'y', 'ppc64el': '-'}> +CONFIG_OBJTOOL_WERROR policy<{'amd64': 'n'}> +CONFIG_OCFS2_DEBUG_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_OCFS2_DEBUG_MASKLOG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OCFS2_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OCFS2_FS_O2CB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OCFS2_FS_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OCFS2_FS_USERSPACE_CLUSTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OCTEONEP_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OCTEONTX2_AF policy<{'arm64': 'm'}> +CONFIG_OCTEONTX2_MBOX policy<{'arm64': 'm'}> +CONFIG_OCTEONTX2_PF policy<{'arm64': 'm'}> +CONFIG_OCTEONTX2_VF policy<{'arm64': 'm'}> +CONFIG_OCTEON_EP policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OCTEON_EP_VF policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OCXL policy<{'ppc64el': 'm'}> +CONFIG_OCXL_BASE policy<{'ppc64el': 'y'}> +CONFIG_OF policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_OF_ADDRESS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_DYNAMIC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_EARLY_FLATTREE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_FLATTREE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_FPGA_REGION policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OF_GPIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_IOMMU policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_IRQ policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_KOBJ policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_MDIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_NUMA policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_OF_OVERLAY policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_PARTITION policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_PMEM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_OF_RESERVED_MEM policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_RESOLVE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_UNITTEST policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_OID_REGISTRY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OLD_SIGACTION policy<{'armhf': 'y', 's390x': 'y'}> +CONFIG_OLD_SIGSUSPEND policy<{'ppc64el': 'y'}> +CONFIG_OLD_SIGSUSPEND3 policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 's390x': 'y'}> +CONFIG_OLPC_EC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OLPC_XO175 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OLPC_XO175_EC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OMAP2PLUS_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OMAP2PLUS_PRM policy<{'armhf': 'y'}> +CONFIG_OMAP5_ERRATA_801819 policy<{'armhf': 'y'}> +CONFIG_OMAP_CONTROL_PHY policy<{'armhf': 'm'}> +CONFIG_OMAP_DM_SYSTIMER policy<{'armhf': 'y'}> +CONFIG_OMAP_DM_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OMAP_GPMC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OMAP_GPMC_DEBUG policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_OMAP_INTERCONNECT policy<{'armhf': 'y'}> +CONFIG_OMAP_INTERCONNECT_BARRIER policy<{'armhf': 'y'}> +CONFIG_OMAP_IOMMU policy<{'armhf': 'y'}> +CONFIG_OMAP_IOMMU_DEBUG policy<{'armhf': 'n'}> +CONFIG_OMAP_IRQCHIP policy<{'armhf': 'y'}> +CONFIG_OMAP_OCP2SCP policy<{'armhf': 'm'}> +CONFIG_OMAP_REMOTEPROC policy<{'armhf': 'm'}> +CONFIG_OMAP_REMOTEPROC_WATCHDOG policy<{'armhf': 'n'}> +CONFIG_OMAP_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OMAP_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_OMFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_OPAL_CORE policy<{'ppc64el': 'n'}> +CONFIG_OPAL_PRD policy<{'ppc64el': 'm'}> +CONFIG_OPENSSL_SUPPORTS_ML_DSA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OPENVSWITCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OPENVSWITCH_GENEVE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OPENVSWITCH_GRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OPENVSWITCH_VXLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OPEN_ALLIANCE_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OPEN_DICE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OPT3001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OPT4001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OPT4060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OPTEE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OPTEE_INSECURE_LOAD_IMAGE policy<{'arm64': 'n'}> +CONFIG_OPTEE_STATIC_PROTMEM_POOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_OPTPROBES policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_ORANGEFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ORION_IRQCHIP policy<{'armhf': 'y'}> +CONFIG_ORION_TIMER policy<{'armhf': 'y'}> +CONFIG_ORION_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_OSF_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_OUTER_CACHE policy<{'armhf': 'y'}> +CONFIG_OUTER_CACHE_SYNC policy<{'armhf': 'y'}> +CONFIG_OUTPUT_FORMAT policy<{'amd64': '"elf64-x86-64"'}> +CONFIG_OVERLAY_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OVERLAY_FS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_OVERLAY_FS_INDEX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_OVERLAY_FS_METACOPY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OVERLAY_FS_REDIRECT_DIR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_OVERLAY_FS_XINO_AUTO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OVMF_DEBUG_LOG policy<{'amd64': 'y', 'arm64-generic': 'n', 'arm64-generic-64k': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_OVPN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OWL_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OWL_EMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OWL_PM_DOMAINS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OWL_PM_DOMAINS_HELPER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OWL_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OXP_EC policy<{'amd64': 'm'}> +CONFIG_P2SB policy<{'amd64': 'y'}> +CONFIG_P54_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_P54_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_P54_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_P54_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_P54_SPI_DEFAULT_EEPROM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_P54_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PA12203001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PAC1921 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PAC1934 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PACKET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PACKET_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PACKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PADATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_BLOCK_MAX_ORDER policy<{'amd64': '10', 'arm64': '13', 'arm64-generic': '10', 'armhf': '11', 'ppc64el': '8', 'riscv64': '10', 's390x': '10'}> +CONFIG_PAGE_COUNTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_EXTENSION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PAGE_IDLE_FLAG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_MAPCOUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_OFFSET policy<{'armhf': '0xC0000000', 'ppc64el': '0xc000000000000000', 'riscv64': '-'}> +CONFIG_PAGE_OWNER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PAGE_POOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_POOL_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_REPORTING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_SHIFT policy<{'amd64': '12', 'arm64-generic': '12', 'arm64-generic-64k': '16', 'armhf': '12', 'ppc64el': '16', 'riscv64': '12', 's390x': '12'}> +CONFIG_PAGE_SIZE_4KB policy<{'amd64': 'y', 'arm64-generic': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_SIZE_64KB policy<{'arm64-generic-64k': 'y', 'ppc64el': 'y'}> +CONFIG_PAGE_SIZE_LESS_THAN_256KB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_SIZE_LESS_THAN_64KB policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_TABLE_CHECK policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PAHOLE_HAS_LANG_EXCLUDE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAHOLE_VERSION policy<{'amd64': '131', 'arm64': '131', 'armhf': '131', 'ppc64el': '131', 'riscv64': '131', 's390x': '131'}> +CONFIG_PALMAS_GPADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PANASONIC_LAPTOP policy<{'amd64': 'm'}> +CONFIG_PANEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PANEL_CHANGE_MESSAGE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PANEL_PARPORT policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_PANEL_PROFILE policy<{'amd64': '5', 'arm64': '5', 'armhf': '5', 'ppc64el': '5', 'riscv64': '5'}> +CONFIG_PANIC_TIMEOUT policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '10', 'riscv64': '0', 's390x': '0'}> +CONFIG_PANTHERLORD_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PAPR_SCM policy<{'ppc64el': 'm'}> +CONFIG_PARAVIRT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PARAVIRT_CLOCK policy<{'amd64': 'y'}> +CONFIG_PARAVIRT_SPINLOCKS policy<{'amd64': 'y'}> +CONFIG_PARAVIRT_TIME_ACCOUNTING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n'}> +CONFIG_PARAVIRT_XXL policy<{'amd64': 'y'}> +CONFIG_PARMAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PARPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PARPORT_1284 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PARPORT_NOT_PC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PARPORT_PANEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PARPORT_PC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PARPORT_PC_FIFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PARPORT_PC_PCMCIA policy<{'amd64': 'm'}> +CONFIG_PARPORT_PC_SUPERIO policy<{'amd64': 'n', 'armhf': 'n', 'ppc64el': 'n'}> +CONFIG_PARPORT_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PARTITION_ADVANCED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PATA_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_PATA_ALI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_AMD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_ARTOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_ATIIXP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_ATP867X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_CMD640_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_CMD64X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_CYPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_EFAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_HPT366 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_HPT37X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_HPT3X2N policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_HPT3X3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PATA_IT8213 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_IT821X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_JMICRON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_MARVELL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_MPIIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_NETCELL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_NINJA32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_NS87410 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_NS87415 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_OF_PLATFORM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PATA_OLDPIIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_OPTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_OPTIDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_PARPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_ATEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_BPCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_BPCK6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_COMM policy<{'amd64': 'm', 'arm64': 'n', 'arm64-generic-64k': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_DSTR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_EPAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_EPATC8 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_PATA_PARPORT_EPIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_FIT2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_FIT3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_FRIQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_FRPW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_KBIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_KTTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_ON20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_ON26 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PCMCIA policy<{'amd64': 'm'}> +CONFIG_PATA_PDC2027X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_PDC_OLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_PLATFORM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_RADISYS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_RDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_RZ1000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_SCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_SERVERWORKS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_SIL680 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_SIS policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_TIMINGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PATA_TOSHIBA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_TRIFLEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_VIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_WINBOND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PC104 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PC300TOO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PC87413_WDT policy<{'amd64': 'm'}> +CONFIG_PCC policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PCCARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCCARD_NONSTATIC policy<{'amd64': 'y'}> +CONFIG_PCENGINES_APU2 policy<{'amd64': 'm'}> +CONFIG_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI200SYN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PCIEAER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIEAER_INJECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIEASPM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIEASPM_PERFORMANCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIEASPM_POWERSAVE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIEASPM_POWER_SUPERSAVE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_AL policy<{'arm64': 'y'}> +CONFIG_PCIE_ALTERA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ALTERA_MSI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_AMD_MDB policy<{'arm64': 'y'}> +CONFIG_PCIE_APPLE policy<{'arm64': 'm'}> +CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR policy<{'arm64': '0xfffff000'}> +CONFIG_PCIE_ARMADA_8K policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ASPEED policy<{'armhf': 'y'}> +CONFIG_PCIE_BUS_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_BUS_PEER2PEER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_BUS_PERFORMANCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_BUS_SAFE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_BUS_TUNE_OFF policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_CADENCE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_CADENCE_EP policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_CADENCE_HOST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_CADENCE_PLAT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_CADENCE_PLAT_EP policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_CADENCE_PLAT_HOST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_DPC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_DW_EP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW_PLAT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW_PLAT_EP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW_PLAT_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_ECRC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_EDR policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_HISI_ERR policy<{'arm64': 'y'}> +CONFIG_PCIE_HISI_STB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_KEEMBAY policy<{'arm64': 'y'}> +CONFIG_PCIE_KEEMBAY_EP policy<{'arm64': 'y'}> +CONFIG_PCIE_KEEMBAY_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_KIRIN policy<{'arm64': 'y'}> +CONFIG_PCIE_LAYERSCAPE_GEN4 policy<{'arm64': 'n'}> +CONFIG_PCIE_MEDIATEK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_MEDIATEK_GEN3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_MICROCHIP_HOST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_MOBIVEIL_PLAT policy<{'arm64': 'n'}> +CONFIG_PCIE_NXP_S32G policy<{'arm64': 'y'}> +CONFIG_PCIE_PLDA_HOST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_PME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_PTM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_QCOM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_QCOM_COMMON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_QCOM_EP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_RCAR_EP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_RCAR_GEN4 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_RCAR_GEN4_EP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_RCAR_GEN4_HOST policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_RCAR_HOST policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_RENESAS_RZG3S_HOST policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP_DW policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP_DW_EP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP_DW_HOST policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP_EP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP_HOST policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_SG2042_HOST policy<{'arm64': 'm'}> +CONFIG_PCIE_SOPHGO_DW policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PCIE_STM32_EP policy<{'arm64': 'm'}> +CONFIG_PCIE_STM32_HOST policy<{'arm64': 'm'}> +CONFIG_PCIE_TEGRA194 policy<{'arm64': 'm'}> +CONFIG_PCIE_TEGRA194_EP policy<{'arm64': 'm'}> +CONFIG_PCIE_TEGRA194_HOST policy<{'arm64': 'm'}> +CONFIG_PCIE_THERMAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_TPH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_VISCONTI_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_XILINX policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_XILINX_CPM policy<{'arm64': 'y'}> +CONFIG_PCIE_XILINX_DMA_PL policy<{'arm64': 'y'}> +CONFIG_PCIE_XILINX_NWL policy<{'arm64': 'y'}> +CONFIG_PCIPCWATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PCI_AARDVARK policy<{'arm64': 'y'}> +CONFIG_PCI_ATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_BRIDGE_EMUL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCI_DIRECT policy<{'amd64': 'y'}> +CONFIG_PCI_DOE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_DOMAINS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_DOMAINS_GENERIC policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_PCI_DRA7XX policy<{'armhf': 'm'}> +CONFIG_PCI_DRA7XX_EP policy<{'armhf': 'm'}> +CONFIG_PCI_DRA7XX_HOST policy<{'armhf': 'm'}> +CONFIG_PCI_ECAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_ENDPOINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_ENDPOINT_CONFIGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_ENDPOINT_MSI_DOORBELL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_ENDPOINT_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCI_EPF_MHI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PCI_EPF_NTB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PCI_EPF_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCI_EPF_VNTB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PCI_EXYNOS policy<{'armhf': 'n'}> +CONFIG_PCI_FTPCI100 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCI_HISI policy<{'arm64': 'y'}> +CONFIG_PCI_HOST_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_HOST_GENERIC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCI_HOST_THUNDER_ECAM policy<{'arm64': 'y'}> +CONFIG_PCI_HOST_THUNDER_PEM policy<{'arm64': 'y'}> +CONFIG_PCI_HYPERV policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_PCI_HYPERV_INTERFACE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_PCI_IDE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCI_IMX6 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_IMX6_EP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_IMX6_HOST policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_IOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_J721E policy<{'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_PCI_J721E_EP policy<{'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_PCI_J721E_HOST policy<{'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_PCI_KEYSTONE_EP policy<{'arm64': 'y'}> +CONFIG_PCI_KEYSTONE_HOST policy<{'arm64': 'y'}> +CONFIG_PCI_KEYSTONE_TRISTATE policy<{'arm64': 'y'}> +CONFIG_PCI_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_PCI_LAYERSCAPE policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_PCI_LAYERSCAPE_EP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_LOCKLESS_CONFIG policy<{'amd64': 'y'}> +CONFIG_PCI_MMCONFIG policy<{'amd64': 'y'}> +CONFIG_PCI_MSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_MSI_ARCH_FALLBACKS policy<{'ppc64el': 'y', 's390x': 'y'}> +CONFIG_PCI_MVEBU policy<{'armhf': 'm'}> +CONFIG_PCI_NPEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCI_P2PDMA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_PASID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PCI_PF_STUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_PRI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PCI_PWRCTRL policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_PWRCTRL_GENERIC policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_PWRCTRL_PWRSEQ policy<{'arm64': 'm'}> +CONFIG_PCI_PWRCTRL_TC9563 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_QUIRKS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_RCAR_GEN2 policy<{'armhf': 'y'}> +CONFIG_PCI_REALLOC_ENABLE_AUTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_SKY1_HOST policy<{'arm64': 'm'}> +CONFIG_PCI_STUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_SW_SWITCHTEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_SYSCALL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_PCI_TEGRA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_TSM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PCI_V3_SEMI policy<{'armhf': 'y'}> +CONFIG_PCI_XEN policy<{'amd64': 'y'}> +CONFIG_PCI_XGENE policy<{'arm64': 'y'}> +CONFIG_PCI_XGENE_MSI policy<{'arm64': 'y'}> +CONFIG_PCMCIA policy<{'amd64': 'm', 'arm64': 'n', 'armhf': 'n', 'ppc64el': '-'}> +CONFIG_PCMCIA_AHA152X policy<{'amd64': 'm'}> +CONFIG_PCMCIA_FDOMAIN policy<{'amd64': 'm'}> +CONFIG_PCMCIA_LOAD_CIS policy<{'amd64': 'y'}> +CONFIG_PCMCIA_PCNET policy<{'amd64': 'm'}> +CONFIG_PCMCIA_QLOGIC policy<{'amd64': 'm'}> +CONFIG_PCMCIA_SYM53C500 policy<{'amd64': 'm'}> +CONFIG_PCMCIA_XIRC2PS policy<{'amd64': 'm'}> +CONFIG_PCMCIA_XIRCOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-'}> +CONFIG_PCNET32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PCPU_DEV_REFCNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCP_BATCH_SCALE_MAX policy<{'amd64': '5', 'arm64': '5', 'armhf': '5', 'ppc64el': '5', 'riscv64': '5', 's390x': '5'}> +CONFIG_PCSPKR_PLATFORM policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_PCS_LYNX policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PCS_MTK_LYNXI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PCS_RZN1_MIIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCS_XPCS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PD6729 policy<{'amd64': 'm'}> +CONFIG_PDC_ADMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PDS_CORE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PDS_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PDS_VFIO_PCI policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PECI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PECI_ASPEED policy<{'armhf': 'm'}> +CONFIG_PECI_CPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PECI_NPCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PERCPU_STATS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PERCPU_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PERF_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PERF_EVENTS_AMD_BRS policy<{'amd64': 'y'}> +CONFIG_PERF_EVENTS_AMD_POWER policy<{'amd64': 'n'}> +CONFIG_PERF_EVENTS_AMD_UNCORE policy<{'amd64': 'm'}> +CONFIG_PERF_EVENTS_INTEL_CSTATE policy<{'amd64': 'm'}> +CONFIG_PERF_EVENTS_INTEL_RAPL policy<{'amd64': 'm'}> +CONFIG_PERF_EVENTS_INTEL_UNCORE policy<{'amd64': 'y'}> +CONFIG_PERF_GUEST_MEDIATED_PMU policy<{'amd64': 'y'}> +CONFIG_PERF_USE_VMALLOC policy<{'armhf': 'y'}> +CONFIG_PERSISTENT_HUGE_ZERO_FOLIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PERSISTENT_KEYRINGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PER_VMA_LOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PER_VMA_LOCK_STATS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PFAULT policy<{'s390x': 'y'}> +CONFIG_PFCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PGTABLE_HAS_HUGE_LEAVES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PGTABLE_LEVELS policy<{'amd64': '5', 'arm64': '4', 'arm64-generic-64k': '3', 'armhf': '3', 'ppc64el': '4', 'riscv64': '5', 's390x': '5'}> +CONFIG_PHANTOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PHONET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PHYLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PHYLIB_LEDS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PHYLINK policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PHYSICAL_ALIGN policy<{'amd64': '0x200000'}> +CONFIG_PHYSICAL_START policy<{'amd64': '0x1000000', 'ppc64el': '0x00000000'}> +CONFIG_PHYS_ADDR_T_64BIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PHY_AIROHA_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_AM654_SERDES policy<{'arm64': 'm'}> +CONFIG_PHY_APPLE_ATC policy<{'arm64': 'm'}> +CONFIG_PHY_BERLIN_SATA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_BERLIN_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_CADENCE_DPHY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_CADENCE_DPHY_RX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_CADENCE_SALVO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_CADENCE_SIERRA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_CADENCE_TORRENT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_CAN_TRANSCEIVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PHY_COMMON_PROPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PHY_CPCAP_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_DM816X_USB policy<{'armhf': 'm'}> +CONFIG_PHY_EXYNOS_DP_VIDEO policy<{'armhf': 'n'}> +CONFIG_PHY_EXYNOS_MIPI_VIDEO policy<{'armhf': 'n'}> +CONFIG_PHY_EXYNOS_PCIE policy<{'armhf': 'n'}> +CONFIG_PHY_FSL_IMX8MQ_USB policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_IMX8M_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_IMX8QM_HSIO policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_LYNX_28G policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY policy<{'arm64': 'm', 'armhf': 'n'}> +CONFIG_PHY_GOOGLE_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_HI3660_USB policy<{'arm64': 'm'}> +CONFIG_PHY_HI3670_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_HI3670_USB policy<{'arm64': 'm'}> +CONFIG_PHY_HI6220_USB policy<{'arm64': 'm'}> +CONFIG_PHY_HISI_INNO_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_HISTB_COMBPHY policy<{'arm64': 'm'}> +CONFIG_PHY_HIX5HD2_SATA policy<{'armhf': 'm'}> +CONFIG_PHY_INTEL_KEEMBAY_EMMC policy<{'arm64': 'm'}> +CONFIG_PHY_INTEL_KEEMBAY_USB policy<{'arm64': 'm'}> +CONFIG_PHY_INTEL_LGM_EMMC policy<{'amd64': 'm'}> +CONFIG_PHY_J721E_WIZ policy<{'arm64': 'm'}> +CONFIG_PHY_LAN966X_SERDES policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_MA35_USB policy<{'arm64': 'n'}> +CONFIG_PHY_MAPPHONE_MDM6600 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_MESON8B_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MESON8_HDMI_TX policy<{'armhf': 'm'}> +CONFIG_PHY_MESON_AXG_MIPI_DPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PHY_MESON_AXG_PCIE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MESON_G12A_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MESON_G12A_USB3_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MESON_GXL_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MIXEL_LVDS_PHY policy<{'arm64': 'm'}> +CONFIG_PHY_MIXEL_MIPI_DPHY policy<{'arm64': 'm'}> +CONFIG_PHY_MMP3_HSIC policy<{'armhf': 'm'}> +CONFIG_PHY_MMP3_USB policy<{'armhf': 'm'}> +CONFIG_PHY_MTK_DP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_MIPI_CSI_0_5 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_TPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_UFS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_XFI_TPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_XSPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_A3700_COMPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_A3700_UTMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_A38X_COMPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_CP110_COMPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_CP110_UTMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_SATA policy<{'armhf': 'y'}> +CONFIG_PHY_NXP_PTN3222 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_OCELOT_SERDES policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_PACKAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PHY_PXA_28NM_HSIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PHY_PXA_28NM_USB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PHY_PXA_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_APQ8064_SATA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_EDP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_EUSB2_REPEATER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_IPQ4019_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_IPQ806X_SATA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_IPQ806X_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_M31_EUSB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_M31_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_MIPI_CSI2 policy<{'arm64': 'm', 'armhf': 'n'}> +CONFIG_PHY_QCOM_PCIE2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_COMBO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_PCIE_8996 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_UFS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_USB_LEGACY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QUSB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_SGMII_ETH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PHY_QCOM_USB_HS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_QCOM_USB_HSIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_QCOM_USB_HS_28NM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_USB_SS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_R8A779F0_ETHERNET_SERDES policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RCAR_GEN2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RCAR_GEN3_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RCAR_GEN3_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RCAR_GEN3_USB3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_DP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_DPHY_RX0 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_EMMC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_TYPEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_USBDP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RTK_RTD_USB2PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RTK_RTD_USB3PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RZ_G3E_USB3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_SAMSUNG_UFS policy<{'armhf': 'n'}> +CONFIG_PHY_SAMSUNG_USB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PHY_SNPS_EUSB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_SOPHGO_CV1800_USB2 policy<{'arm64': 'm'}> +CONFIG_PHY_SPARX5_SERDES policy<{'amd64': '-', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-'}> +CONFIG_PHY_STM32_COMBOPHY policy<{'arm64': 'm'}> +CONFIG_PHY_STM32_USBPHYC policy<{'arm64': 'm'}> +CONFIG_PHY_SUN4I_USB policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PHY_SUN50I_USB3 policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PHY_SUN6I_MIPI_DPHY policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PHY_SUN9I_USB policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PHY_SUNPLUS_USB policy<{'armhf': 'm'}> +CONFIG_PHY_TEGRA194_P2U policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_TEGRA_XUSB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_TI_GMII_SEL policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_PHY_TUSB1210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_XGENE policy<{'arm64': 'y'}> +CONFIG_PHY_XILINX_ZYNQMP policy<{'arm64': 'm'}> +CONFIG_PID_IN_CONTEXTIDR policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_PID_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PINCONF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PINCTRL_AC5 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AIROHA policy<{'arm64': 'm'}> +CONFIG_PINCTRL_ALDERLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_AMD policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_AMDISP policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_PINCTRL_AMLOGIC_A4 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AMLOGIC_C3 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_AMLOGIC_T7 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_APPLE_GPIO policy<{'arm64': 'm'}> +CONFIG_PINCTRL_APQ8064 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_APQ8084 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_ARMADA_370 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ARMADA_375 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ARMADA_37XX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_ARMADA_38X policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ARMADA_39X policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ARMADA_AP806 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_ARMADA_CP110 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_ARMADA_XP policy<{'armhf': 'y'}> +CONFIG_PINCTRL_AS370 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_AS3722 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_ASPEED policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ASPEED_G6 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_AW9523 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_AXP209 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_BAYTRAIL policy<{'amd64': 'y'}> +CONFIG_PINCTRL_BERLIN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_BERLIN_BG2 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_BERLIN_BG2CD policy<{'armhf': 'y'}> +CONFIG_PINCTRL_BERLIN_BG2Q policy<{'armhf': 'y'}> +CONFIG_PINCTRL_BERLIN_BG4CT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_BM1880 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_BROXTON policy<{'amd64': 'm'}> +CONFIG_PINCTRL_CANNONLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_CEDARFORK policy<{'amd64': 'm'}> +CONFIG_PINCTRL_CS42L43 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_CS47L15 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_CS47L35 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_CS47L85 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_CS47L90 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_CS47L92 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_CY8C95X0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_DA9062 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_DENVERTON policy<{'amd64': 'm'}> +CONFIG_PINCTRL_DOVE policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ELIZA policy<{'arm64': 'm'}> +CONFIG_PINCTRL_ELKHARTLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_EMMITSBURG policy<{'amd64': 'm'}> +CONFIG_PINCTRL_EXYNOS policy<{'armhf': 'y'}> +CONFIG_PINCTRL_EXYNOS_ARM policy<{'armhf': 'y'}> +CONFIG_PINCTRL_GEMINILAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_GLYMUR policy<{'arm64': 'm'}> +CONFIG_PINCTRL_HAWI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_ICELAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_IMX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_IMX50 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX51 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX6Q policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX6SL policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX6SLL policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX6SX policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX6UL policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX7D policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX7ULP policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX8DXL policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MM policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MN policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MQ policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8QM policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8QXP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8ULP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_IMX91 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_IMX93 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_IMX_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_IMX_SCU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_INTEL policy<{'amd64': 'y'}> +CONFIG_PINCTRL_INTEL_PLATFORM policy<{'amd64': 'm'}> +CONFIG_PINCTRL_IPQ4019 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_IPQ5018 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ5210 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ5332 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ5424 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ6018 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ8064 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_IPQ8074 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ9574 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_JASPERLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_KAANAPALI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_KEEMBAY policy<{'arm64': 'm'}> +CONFIG_PINCTRL_LAKEFIELD policy<{'amd64': 'm'}> +CONFIG_PINCTRL_LEWISBURG policy<{'amd64': 'm'}> +CONFIG_PINCTRL_LOCHNAGAR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_LPASS_LPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_LYNXPOINT policy<{'amd64': 'm'}> +CONFIG_PINCTRL_MA35 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MA35D1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MADERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_MAX7360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_MAX77620 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_MCP23S08 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PINCTRL_MCP23S08_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_MCP23S08_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_MDM9607 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_MDM9615 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MESON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MESON8 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MESON8B policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MESON8_PMX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MESON_A1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_AXG policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_AXG_PMX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_G12A policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_GXBB policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_GXL policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_S4 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_METEORLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_METEORPOINT policy<{'amd64': 'm'}> +CONFIG_PINCTRL_MICROCHIP_SGPIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_MILOS policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MILOS_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MLXBF3 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MSM8226 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MSM8660 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MSM8909 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MSM8916 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_MSM8917 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_MSM8953 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8960 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MSM8976 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8994 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8996 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8998 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8X74 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MT2701 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MT2712 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6397 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MT6765 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6779 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MT6795 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6797 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6878 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6893 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7622 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7623 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MT7629 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MT7981 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7986 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7988 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8127 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MT8135 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MT8167 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8173 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8183 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8186 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8188 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8189 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8192 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8195 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8196 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8365 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8516 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MTK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MTK_MOORE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MTK_PARIS policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MTK_V2 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MVEBU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_NPCM7XX policy<{'armhf': 'y'}> +CONFIG_PINCTRL_NPCM8XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_OCELOT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_OWL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_PALMAS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_PEF2256 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_PFC_EMEV2 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7740 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7742 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7743 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7744 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7745 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A77470 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A7778 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7779 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7790 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7791 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7792 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7793 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7794 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A77951 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77960 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77961 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77965 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77970 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77980 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77990 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77995 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_SH73A0 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PIC64GX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_POLARFIRE_SOC policy<{'arm64': 'y'}> +CONFIG_PINCTRL_QCM2290 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QCOM_SPMI_PMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_QCOM_SSBI_PMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_QCS404 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QCS615 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QCS8300 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QDF2XXX policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QDU1000 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_RENESAS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_RK805 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_RP1 policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_RTD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_RTD1315E policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_RTD1319D policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_RTD1619B policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_RTD1625 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_RZA1 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_RZA2 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_RZG2L policy<{'arm64': 'y'}> +CONFIG_PINCTRL_RZN1 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_RZT2H policy<{'arm64': 'y'}> +CONFIG_PINCTRL_RZV2M policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S32CC policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S32G2 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S500 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_S700 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S900 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SA8775P policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SAMSUNG policy<{'armhf': 'y'}> +CONFIG_PINCTRL_SAR2130P policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SC7180 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SC7280 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SC7280_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SC8180X policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SC8280XP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SC8280XP_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_SDM660 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDM660_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDM670 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDM670_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDM845 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDX55 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_SDX65 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_SDX75 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SH_PFC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_SH_PFC_GPIO policy<{'armhf': 'y'}> +CONFIG_PINCTRL_SINGLE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_SKY1 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SKY1_BASE policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM4250_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM4450 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6115 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6115_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6125 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6350 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6375 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM7150 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8150 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8250 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8250_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8350 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8450 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8450_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8550 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8550_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8650 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8650_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8750 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SOPHGO_COMMON policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_CV1800B policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_CV1812H policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_CV18XX_OPS policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2000 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2002 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2042 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2042_OPS policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2044 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SPPCTL policy<{'armhf': 'y'}> +CONFIG_PINCTRL_SPRD policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SPRD_SC9860 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STM32 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STM32MP257 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STM32_HDP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STMFX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_SUN20I_D1 policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN4I_A10 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_A100 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_A100_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_A64 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_A64_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_H5 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_H6 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_H616 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_H616_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_H6_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN55I_A523 policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN55I_A523_R policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN5I policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN6I_A31 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN6I_A31_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_A23 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_A23_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_A33 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_A83T policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_A83T_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_H3 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_H3_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_V3S policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN9I_A80 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN9I_A80_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUNRISEPOINT policy<{'amd64': 'm'}> +CONFIG_PINCTRL_SUNXI policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SX150X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_TEGRA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_TEGRA114 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_TEGRA124 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_TEGRA186 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA194 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA20 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_TEGRA210 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA234 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA30 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_TEGRA_XUSB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_TIGERLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_TI_IODELAY policy<{'armhf': 'y'}> +CONFIG_PINCTRL_TMPV7700 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TPS6594 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_UPBOARD policy<{'amd64': 'm'}> +CONFIG_PINCTRL_VF610 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_VISCONTI policy<{'arm64': 'y'}> +CONFIG_PINCTRL_X1E80100 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_ZYNQMP policy<{'arm64': 'm'}> +CONFIG_PING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINMUX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PJ4B_ERRATA_4742 policy<{'armhf': 'y'}> +CONFIG_PKCS7_MESSAGE_PARSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PKCS7_TEST_KEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PKCS7_WAIVE_AUTHATTRS_REJECTION_FOR_MLDSA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PKCS8_PRIVATE_KEY_PARSER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PKEY policy<{'s390x': 'm'}> +CONFIG_PKEY_CCA policy<{'s390x': 'm'}> +CONFIG_PKEY_EP11 policy<{'s390x': 'm'}> +CONFIG_PKEY_PCKMO policy<{'s390x': 'm'}> +CONFIG_PKEY_UV policy<{'s390x': 'm'}> +CONFIG_PL310_ERRATA_588369 policy<{'armhf': 'y'}> +CONFIG_PL310_ERRATA_727915 policy<{'armhf': 'y'}> +CONFIG_PL310_ERRATA_753970 policy<{'armhf': 'y'}> +CONFIG_PL310_ERRATA_769419 policy<{'armhf': 'y'}> +CONFIG_PL320_MBOX policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_PL330_DMA policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_PL353_SMC policy<{'armhf': 'm'}> +CONFIG_PLATFORM_MHU policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PLATFORM_SI4713 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PLAT_ORION policy<{'armhf': 'y'}> +CONFIG_PLAT_PXA policy<{'armhf': 'y'}> +CONFIG_PLAT_SPEAR policy<{'armhf': 'n'}> +CONFIG_PLAT_VERSATILE policy<{'armhf': 'y'}> +CONFIG_PLAYSTATION_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PLDMFW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PLFXLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PLIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PLX_DMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PM8916_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PMBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PMIC_ADP5520 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_PMIC_DA903X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_PMIC_DA9052 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PMIC_OPREGION policy<{'amd64': 'y', 'arm64': 'n', 'riscv64': 'y'}> +CONFIG_PMS7003 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PMU_SYSFS policy<{'ppc64el': 'n'}> +CONFIG_PM_ADVANCED_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_AUTOSLEEP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PM_CLK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_DEVFREQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PM_DEVFREQ_EVENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_GENERIC_DOMAINS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_GENERIC_DOMAINS_OF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_GENERIC_DOMAINS_SLEEP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_NOTIFIER_ERROR_INJECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PM_OPP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_QOS_CPU_SYSTEM_WAKEUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_SLEEP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_SLEEP_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_SLEEP_SMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_SLEEP_SMP_NONZERO_CPU policy<{'ppc64el': 'y'}> +CONFIG_PM_STD_PARTITION policy<{'amd64': '""', 'armhf': '""', 'riscv64': '""'}> +CONFIG_PM_TEST_SUSPEND policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PM_TRACE policy<{'amd64': 'y'}> +CONFIG_PM_TRACE_RTC policy<{'amd64': 'y'}> +CONFIG_PM_USERSPACE_AUTOSLEEP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PM_WAKELOCKS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_WAKELOCKS_GC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_WAKELOCKS_LIMIT policy<{'amd64': '100', 'arm64': '100', 'armhf': '100', 'ppc64el': '100', 'riscv64': '100'}> +CONFIG_PNFS_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PNFS_FILE_LAYOUT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PNFS_FLEXFILE_LAYOUT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PNP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PNPACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PNP_DEBUG_MESSAGES policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_POLARFIRE_SOC_AUTO_UPDATE policy<{'arm64': 'm'}> +CONFIG_POLARFIRE_SOC_IRQ_MUX policy<{'arm64': 'y'}> +CONFIG_POLARFIRE_SOC_MAILBOX policy<{'arm64': 'm'}> +CONFIG_POLARFIRE_SOC_SYSCONS policy<{'arm64': 'y'}> +CONFIG_POLARFIRE_SOC_SYS_CTRL policy<{'arm64': 'm'}> +CONFIG_POLYNOMIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PORTABLE policy<{'riscv64': 'y'}> +CONFIG_PORTWELL_EC policy<{'amd64': 'm'}> +CONFIG_POSIX_AUX_CLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POSIX_CPU_TIMERS_TASK_WORK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POSIX_MQUEUE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POSIX_MQUEUE_SYSCTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POSIX_TIMERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POWER10_CPU policy<{'ppc64el': 'n'}> +CONFIG_POWER7_CPU policy<{'ppc64el': 'n'}> +CONFIG_POWER8_CPU policy<{'ppc64el': 'n'}> +CONFIG_POWER9_CPU policy<{'ppc64el': 'n'}> +CONFIG_POWERCAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_POWERNV_CPUFREQ policy<{'ppc64el': 'y'}> +CONFIG_POWERNV_CPUIDLE policy<{'ppc64el': 'y'}> +CONFIG_POWERNV_OP_PANEL policy<{'ppc64el': 'm'}> +CONFIG_POWERPC64_CPU policy<{'ppc64el': 'y'}> +CONFIG_POWER_MLXBF policy<{'arm64': 'm'}> +CONFIG_POWER_RESET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POWER_RESET_AS3722 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_ATC260X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_POWER_RESET_AXXIA policy<{'armhf': 'y'}> +CONFIG_POWER_RESET_BRCMKONA policy<{'armhf': 'y'}> +CONFIG_POWER_RESET_GPIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_GPIO_RESTART policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_HISI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_POWER_RESET_LINKSTATION policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_POWER_RESET_LTC2952 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_MACSMC policy<{'arm64': 'm'}> +CONFIG_POWER_RESET_MSM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_POWER_RESET_MT6323 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_OCELOT_RESET policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_POWER_RESET_QCOM_PON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_POWER_RESET_QEMU_VIRT_CTRL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_POWER_RESET_QNAP policy<{'armhf': 'n'}> +CONFIG_POWER_RESET_REGULATOR policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_RESTART policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POWER_RESET_RMOBILE policy<{'armhf': 'm'}> +CONFIG_POWER_RESET_SC27XX policy<{'arm64': 'm'}> +CONFIG_POWER_RESET_SYSCON policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_SYSCON_POWEROFF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_TORADEX_EC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_POWER_RESET_TPS65086 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_VERSATILE policy<{'armhf': 'y'}> +CONFIG_POWER_RESET_VEXPRESS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_POWER_RESET_XGENE policy<{'arm64': 'n'}> +CONFIG_POWER_SEQUENCING policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_POWER_SEQUENCING_PCIE_M2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_POWER_SEQUENCING_QCOM_WCN policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_POWER_SUPPLY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_POWER_SUPPLY_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_POWER_SUPPLY_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PPC policy<{'ppc64el': 'y'}> +CONFIG_PPC64 policy<{'ppc64el': 'y'}> +CONFIG_PPC64_BOOT_WRAPPER policy<{'ppc64el': 'y'}> +CONFIG_PPC64_ELF_ABI_V2 policy<{'ppc64el': 'y'}> +CONFIG_PPC64_PROC_SYSTEMCFG policy<{'ppc64el': 'y'}> +CONFIG_PPC64_SUPPORTS_MEMORY_FAILURE policy<{'ppc64el': 'y'}> +CONFIG_PPC_4K_PAGES policy<{'ppc64el': 'n'}> +CONFIG_PPC_64K_PAGES policy<{'ppc64el': 'y'}> +CONFIG_PPC_64S_HASH_MMU policy<{'ppc64el': 'y'}> +CONFIG_PPC_BARRIER_NOSPEC policy<{'ppc64el': 'y'}> +CONFIG_PPC_BOOK3E_64 policy<{'ppc64el': 'n'}> +CONFIG_PPC_BOOK3S policy<{'ppc64el': 'y'}> +CONFIG_PPC_BOOK3S_64 policy<{'ppc64el': 'y'}> +CONFIG_PPC_BOOK3S_IDLE policy<{'ppc64el': 'y'}> +CONFIG_PPC_COPRO_BASE policy<{'ppc64el': 'y'}> +CONFIG_PPC_DAWR policy<{'ppc64el': 'y'}> +CONFIG_PPC_DENORMALISATION policy<{'ppc64el': 'y'}> +CONFIG_PPC_DISABLE_WERROR policy<{'ppc64el': 'n'}> +CONFIG_PPC_DOORBELL policy<{'ppc64el': 'y'}> +CONFIG_PPC_DT_CPU_FTRS policy<{'ppc64el': 'y'}> +CONFIG_PPC_EARLY_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_PPC_EMULATED_STATS policy<{'ppc64el': 'n'}> +CONFIG_PPC_EPAPR_HV_BYTECHAN policy<{'ppc64el': 'n'}> +CONFIG_PPC_FPU policy<{'ppc64el': 'y'}> +CONFIG_PPC_FPU_REGS policy<{'ppc64el': 'y'}> +CONFIG_PPC_FTRACE_OUT_OF_LINE policy<{'ppc64el': 'y'}> +CONFIG_PPC_FTRACE_OUT_OF_LINE_NUM_RESERVE policy<{'ppc64el': '32768'}> +CONFIG_PPC_HASH_MMU_NATIVE policy<{'ppc64el': 'y'}> +CONFIG_PPC_HAS_LBARX_LHARX policy<{'ppc64el': 'y'}> +CONFIG_PPC_HAVE_PMU_SUPPORT policy<{'ppc64el': 'y'}> +CONFIG_PPC_I8259 policy<{'ppc64el': 'y'}> +CONFIG_PPC_ICP_HV policy<{'ppc64el': 'y'}> +CONFIG_PPC_ICP_NATIVE policy<{'ppc64el': 'y'}> +CONFIG_PPC_ICS_NATIVE policy<{'ppc64el': 'y'}> +CONFIG_PPC_ICS_RTAS policy<{'ppc64el': 'y'}> +CONFIG_PPC_INDIRECT_PIO policy<{'ppc64el': 'y'}> +CONFIG_PPC_IRQ_SOFT_MASK_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_PPC_KUAP policy<{'ppc64el': 'y'}> +CONFIG_PPC_KUAP_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_PPC_KUEP policy<{'ppc64el': 'y'}> +CONFIG_PPC_MEMTRACE policy<{'ppc64el': 'y'}> +CONFIG_PPC_MICROWATT policy<{'ppc64el': 'y'}> +CONFIG_PPC_MSI_BITMAP policy<{'ppc64el': 'y'}> +CONFIG_PPC_OF_BOOT_TRAMPOLINE policy<{'ppc64el': 'y'}> +CONFIG_PPC_P7_NAP policy<{'ppc64el': 'y'}> +CONFIG_PPC_PERF_CTRS policy<{'ppc64el': 'y'}> +CONFIG_PPC_PKEY policy<{'ppc64el': 'y'}> +CONFIG_PPC_POWERNV policy<{'ppc64el': 'y'}> +CONFIG_PPC_PROT_SAO_LPAR policy<{'ppc64el': 'n'}> +CONFIG_PPC_PSERIES policy<{'ppc64el': 'y'}> +CONFIG_PPC_QUEUED_SPINLOCKS policy<{'ppc64el': 'n'}> +CONFIG_PPC_RADIX_BROADCAST_TLBIE policy<{'ppc64el': 'y'}> +CONFIG_PPC_RADIX_MMU policy<{'ppc64el': 'y'}> +CONFIG_PPC_RADIX_MMU_DEFAULT policy<{'ppc64el': 'y'}> +CONFIG_PPC_RFI_SRR_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_PPC_RTAS policy<{'ppc64el': 'y'}> +CONFIG_PPC_RTAS_DAEMON policy<{'ppc64el': 'y'}> +CONFIG_PPC_SMLPAR policy<{'ppc64el': 'y'}> +CONFIG_PPC_SMP_MUXED_IPI policy<{'ppc64el': 'y'}> +CONFIG_PPC_SPLPAR policy<{'ppc64el': 'y'}> +CONFIG_PPC_SUBPAGE_PROT policy<{'ppc64el': 'y'}> +CONFIG_PPC_SVM policy<{'ppc64el': 'y'}> +CONFIG_PPC_THP policy<{'ppc64el': 'y'}> +CONFIG_PPC_TRANSACTIONAL_MEM policy<{'ppc64el': 'y'}> +CONFIG_PPC_UDBG_16550 policy<{'ppc64el': 'y'}> +CONFIG_PPC_UV policy<{'ppc64el': 'y'}> +CONFIG_PPC_VAS policy<{'ppc64el': 'y'}> +CONFIG_PPC_WATCHDOG policy<{'ppc64el': 'y'}> +CONFIG_PPC_WERROR policy<{'ppc64el': 'y'}> +CONFIG_PPC_XICS policy<{'ppc64el': 'y'}> +CONFIG_PPC_XIVE policy<{'ppc64el': 'y'}> +CONFIG_PPC_XIVE_NATIVE policy<{'ppc64el': 'y'}> +CONFIG_PPC_XIVE_SPAPR policy<{'ppc64el': 'y'}> +CONFIG_PPDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PPP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PPPOATM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PPPOE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPPOE_HASH_BITS policy<{'amd64': '4', 'arm64': '4', 'armhf': '4', 'ppc64el': '4', 'riscv64': '4'}> +CONFIG_PPPOE_HASH_BITS_1 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PPPOE_HASH_BITS_2 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PPPOE_HASH_BITS_4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PPPOE_HASH_BITS_8 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PPPOL2TP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPP_ASYNC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPP_BSDCOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPP_DEFLATE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPP_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PPP_MPPE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPP_MULTILINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PPP_SYNC_TTY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PPS_CLIENT_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PPS_CLIENT_KTIMER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PPS_CLIENT_LDISC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PPS_CLIENT_PARPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PPS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PPS_GENERATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PPS_GENERATOR_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PPS_GENERATOR_TIO policy<{'amd64': 'm'}> +CONFIG_PPTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PREEMPT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PREEMPTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PREEMPTIRQ_DELAY_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PREEMPT_BUILD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PREEMPT_COUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PREEMPT_LAZY policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PREEMPT_NOTIFIERS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PREEMPT_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_PREEMPT_RT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_PREEMPT_TRACER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PREEMPT_VOLUNTARY policy<{'amd64': '-', 'arm64': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_PREEMPT_VOLUNTARY_BUILD policy<{'armhf': 'y', 'ppc64el': '-', 's390x': '-'}> +CONFIG_PREFIX_SYMBOLS policy<{'amd64': 'y'}> +CONFIG_PRESTERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PRESTERA_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PREVENT_FIRMWARE_BUILD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PRIME_NUMBERS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PRINTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PRINTK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PRINTK_CALLER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PRINTK_EXECUTION_CTX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PRINTK_INDEX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PRINTK_TIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PRINT_STACK_DEPTH policy<{'ppc64el': '64'}> +CONFIG_PROBE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROBE_EVENTS_BTF_ARGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROCESSOR_SELECT policy<{'amd64': 'y'}> +CONFIG_PROC_CHILDREN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_CPU_RESCTRL policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_PROC_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_KCORE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_MEM_ALWAYS_FORCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_MEM_FORCE_PTRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PROC_MEM_NO_FORCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PROC_PAGE_MONITOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_PID_ARCH_STATUS policy<{'amd64': 'y'}> +CONFIG_PROC_SYSCTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_THERMAL_MMIO_RAPL policy<{'amd64': 'm'}> +CONFIG_PROC_VMCORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_VMCORE_DEVICE_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_VMCORE_DEVICE_RAM policy<{'s390x': 'y'}> +CONFIG_PROFILE_ALL_BRANCHES policy<{'riscv64': 'n'}> +CONFIG_PROFILE_ANNOTATED_BRANCHES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PROFILING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROVE_LOCKING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PROVIDE_OHCI1394_DMA_INIT policy<{'amd64': 'n'}> +CONFIG_PRU_REMOTEPROC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PSAMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PSERIES_CPUIDLE policy<{'ppc64el': 'y'}> +CONFIG_PSERIES_ENERGY policy<{'ppc64el': 'm'}> +CONFIG_PSERIES_PLPKS policy<{'ppc64el': 'y'}> +CONFIG_PSERIES_PLPKS_SED policy<{'ppc64el': 'y'}> +CONFIG_PSERIES_WDT policy<{'ppc64el': 'm'}> +CONFIG_PSE_CONTROLLER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_PSE_PD692X0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PSE_REGULATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PSE_SI3474 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PSE_TPS23881 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PSTORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PSTORE_BLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PSTORE_BLK_BLKDEV policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '-'}> +CONFIG_PSTORE_BLK_CONSOLE_SIZE policy<{'armhf': '64'}> +CONFIG_PSTORE_BLK_KMSG_SIZE policy<{'amd64': '64', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64'}> +CONFIG_PSTORE_BLK_MAX_REASON policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2', 's390x': '-'}> +CONFIG_PSTORE_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PSTORE_CONSOLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PSTORE_DEFAULT_KMSG_BYTES policy<{'amd64': '10240', 'arm64': '10240', 'armhf': '10240', 'ppc64el': '10240', 'riscv64': '10240'}> +CONFIG_PSTORE_FTRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PSTORE_PMSG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PSTORE_RAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PSTORE_ZONE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PTDUMP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PTDUMP_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_PTDUMP_STAGE2_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_PTE_MARKER_UFFD_WP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PTP_1588_CLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_PTP_1588_CLOCK_FC3W policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PTP_1588_CLOCK_IDT82P33 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PTP_1588_CLOCK_IDTCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PTP_1588_CLOCK_INES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PTP_1588_CLOCK_KVM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_PTP_1588_CLOCK_MOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PTP_1588_CLOCK_OCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PTP_1588_CLOCK_OPTIONAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_PTP_1588_CLOCK_QORIQ policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_PTP_1588_CLOCK_VMCLOCK policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_PTP_1588_CLOCK_VMW policy<{'amd64': 'm'}> +CONFIG_PTP_DFL_TOD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PTP_NETC_V4_TIMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PTP_S390 policy<{'s390x': 'm'}> +CONFIG_PT_RECLAIM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PUNIT_ATOM_DEBUG policy<{'amd64': 'm'}> +CONFIG_PVH policy<{'amd64': 'y'}> +CONFIG_PVPANIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PVPANIC_MMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PVPANIC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PWC_RZV2M policy<{'arm64': 'y'}> +CONFIG_PWM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PWM_ADP5585 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_AIROHA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_APPLE policy<{'arm64': 'm'}> +CONFIG_PWM_ARGON_FAN_HAT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_ATMEL_HLCDC_PWM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_ATMEL_TCB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_AXI_PWMGEN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_BERLIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_CLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_CRC policy<{'amd64': 'y'}> +CONFIG_PWM_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PWM_DWC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PWM_DWC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_FSL_FTM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_HIBVT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_IMX1 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_IMX27 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_IMX_TPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_IQS620A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_KEEMBAY policy<{'arm64': 'm'}> +CONFIG_PWM_LP3943 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_LPSS policy<{'amd64': 'y'}> +CONFIG_PWM_LPSS_PCI policy<{'amd64': 'y'}> +CONFIG_PWM_LPSS_PLATFORM policy<{'amd64': 'y'}> +CONFIG_PWM_MAX7360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_MC33XS2410 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_MTK_DISP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_NTXEC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_OMAP_DMTIMER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_PCA9685 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PWM_PROVIDE_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PWM_PXA policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_PWM_RENESAS_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_RENESAS_RZG2L_GPT policy<{'arm64': 'm'}> +CONFIG_PWM_RENESAS_RZ_MTU3 policy<{'arm64': 'm'}> +CONFIG_PWM_RENESAS_TPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_SAMSUNG policy<{'armhf': 'n'}> +CONFIG_PWM_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_PWM_SOPHGO_SG2042 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PWM_SPRD policy<{'arm64': 'm'}> +CONFIG_PWM_STM32 policy<{'arm64': 'm'}> +CONFIG_PWM_STM32_LP policy<{'arm64': 'm'}> +CONFIG_PWM_STMPE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PWM_SUN4I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PWM_SUNPLUS policy<{'armhf': 'm'}> +CONFIG_PWM_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_TIECAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_TIEHRPWM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_TWL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PWM_TWL_LED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PWM_VISCONTI policy<{'arm64': 'm'}> +CONFIG_PWM_XILINX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWRSEQ_EMMC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWRSEQ_SD8787 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWRSEQ_SIMPLE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PXA168_ETH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PXA1908_PM_DOMAINS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PXA_DMA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PXA_SSP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QAT_VFIO_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCA7000 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCA7000_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCA7000_UART policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCA807X_PHY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCA808X_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_QCA83XX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_QCM_DISPCC_2290 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCM_GCC_2290 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOMTEE policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_A53PLL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_A7PLL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_AOSS_QMP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_APCS_IPC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_APR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_BAM_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_BAM_DMUX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_CLK_APCC_MSM8996 policy<{'arm64': 'm'}> +CONFIG_QCOM_CLK_APCS_MSM8916 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_CLK_APCS_SDX55 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_QCOM_CLK_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_CLK_RPMH policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_CLK_SMD_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_COINCELL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_COMMAND_DB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_CPR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_CPUCP_MBOX policy<{'arm64': 'm'}> +CONFIG_QCOM_EBI2 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_EMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QCOM_FALKOR_ERRATUM_1003 policy<{'arm64': 'y'}> +CONFIG_QCOM_FALKOR_ERRATUM_1009 policy<{'arm64': 'y'}> +CONFIG_QCOM_FALKOR_ERRATUM_E1041 policy<{'arm64': 'y'}> +CONFIG_QCOM_FASTRPC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_GDSC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_GENI_SE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_GPI_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_GSBI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_HFPLL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_HIDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QCOM_HIDMA_MGMT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QCOM_ICC_BWMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_INLINE_CRYPTO_ENGINE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_IOMMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_IPA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_IPCC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_IRQ_COMBINER policy<{'arm64': 'y'}> +CONFIG_QCOM_KRYO_L2_ACCESSORS policy<{'arm64': 'y'}> +CONFIG_QCOM_L2_PMU policy<{'arm64': 'y'}> +CONFIG_QCOM_L3_PMU policy<{'arm64': 'y'}> +CONFIG_QCOM_LLCC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_LMH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_MDT_LOADER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_MPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_NET_PHYLIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_OCMEM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_PBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_PDC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_PDR_HELPERS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_PDR_MSG policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_PD_MAPPER policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_QCOM_PIL_INFO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_PM8XXX_XOADC policy<{'armhf': 'm'}> +CONFIG_QCOM_PMIC_GLINK policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_PMIC_PDCHARGER_ULOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_PPE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_Q6V5_ADSP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_Q6V5_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_Q6V5_MSS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_Q6V5_PAS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_Q6V5_WCSS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_QMI_HELPERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_QSEECOM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_QSEECOM_UEFISECAPP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_RAMP_CTRL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_RMTFS_MEM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_RPMH policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_RPMHPD policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_RPMPD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_RPM_MASTER_STATS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_RPROC_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SCM policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'm'}> +CONFIG_QCOM_SMD_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SMEM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SMEM_STATE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_SMP2P policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SMSM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SOCINFO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SPEL policy<{'arm64': 'n'}> +CONFIG_QCOM_SPM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_SPMI_ADC5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_SPMI_ADC5_GEN3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_SPMI_ADC_TM5 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SPMI_ADC_TM5_GEN3 policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_QCOM_SPMI_IADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_SPMI_RRADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SPMI_TEMP_ALARM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SPMI_VADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_SSC_BLOCK_BUS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_STATS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SYSMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_TSENS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_TZMEM policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'm'}> +CONFIG_QCOM_TZMEM_MODE_GENERIC policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'y'}> +CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'n'}> +CONFIG_QCOM_UBWC_CONFIG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_VADC_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_WCNSS_CTRL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_WCNSS_PIL policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_QCOM_WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCS_CAMCC_615 policy<{'arm64': 'm'}> +CONFIG_QCS_DISPCC_615 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_QCS_GCC_404 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCS_GCC_615 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_QCS_GCC_8300 policy<{'arm64': 'm'}> +CONFIG_QCS_GPUCC_615 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_QCS_Q6SSTOP_404 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCS_TURING_404 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCS_VIDEOCC_615 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_QDIO policy<{'s390x': 'm'}> +CONFIG_QDU_ECPRICC_1000 policy<{'arm64': 'm'}> +CONFIG_QDU_GCC_1000 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QEDE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QEDF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QEDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QED_FCOE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QED_ISCSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QED_LL2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QED_OOO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QED_RDMA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QED_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QETH policy<{'s390x': 'm'}> +CONFIG_QETH_L2 policy<{'s390x': 'm'}> +CONFIG_QETH_L3 policy<{'s390x': 'm'}> +CONFIG_QE_GPIO policy<{'ppc64el': 'y'}> +CONFIG_QE_TDM policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_QE_USB policy<{'ppc64el': 'y'}> +CONFIG_QFMT_V1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_QFMT_V2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_QLA3XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QLCNIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QLCNIC_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QLCNIC_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QLCNIC_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QNX4FS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_QNX6FS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_QNX6FS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_QORIQ_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_QORIQ_THERMAL policy<{'arm64': 'm'}> +CONFIG_QRTR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_QRTR_MHI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QRTR_SMD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QRTR_TUN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QSEMI_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_QTNFMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QTNFMAC_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QUEUED_RWLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_QUEUED_SPINLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_QUICC_ENGINE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_QUOTA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_QUOTACTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_QUOTA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_QUOTA_NETLINK_INTERFACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_QUOTA_TREE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_R6040 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_R8169 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_R8169_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RADIO_ADAPTERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_MAXIRADIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SAA7706H policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SHARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SHARK2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SI470X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SI4713 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SI476X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_TEA575X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_TEA5764 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_TEF6862 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RAID6_PQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RAID6_PQ_BENCHMARK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RAID_ATTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RAMDAX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RANDOM32_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RANDOMIZE_BASE policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RANDOMIZE_IDENTITY_BASE policy<{'s390x': 'n'}> +CONFIG_RANDOMIZE_KSTACK_OFFSET policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RANDOMIZE_MEMORY policy<{'amd64': 'y'}> +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING policy<{'amd64': '0xa'}> +CONFIG_RANDOMIZE_MODULE_REGION_FULL policy<{'arm64': 'y'}> +CONFIG_RANDOM_KMALLOC_CACHES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RANDSTRUCT_NONE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RAPIDIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_RAPIDIO_CHMAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_CPS_GEN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_CPS_XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_RAPIDIO_DISC_TIMEOUT policy<{'amd64': '30', 'arm64': '30', 'armhf': '30', 'ppc64el': '30', 'riscv64': '30'}> +CONFIG_RAPIDIO_DMA_ENGINE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_RAPIDIO_ENUM_BASIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_MPORT_CDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_RXS_GEN3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_TSI721 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RAS_CEC policy<{'amd64': 'y'}> +CONFIG_RAS_CEC_DEBUG policy<{'amd64': 'n'}> +CONFIG_RAS_FMPM policy<{'amd64': 'm'}> +CONFIG_RATIONAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RAVB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RAVE_SP_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RAVE_SP_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RBTREE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCAR_DMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RCAR_GEN3_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RCAR_GYRO_ADC policy<{'armhf': 'm'}> +CONFIG_RCAR_REMOTEPROC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RCAR_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RCU_CPU_STALL_CPUTIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RCU_CPU_STALL_TIMEOUT policy<{'amd64': '60', 'arm64': '60', 'armhf': '60', 'ppc64el': '60', 'riscv64': '60', 's390x': '60'}> +CONFIG_RCU_EQS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCU_EXPERT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_RCU_NEED_SEGCBLIST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RCU_REF_SCALE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCU_SCALE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCU_STALL_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RCU_TORTURE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCU_TRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RC_ATI_REMOTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RC_DECODERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RC_DEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RC_LOOPBACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RC_MAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RC_XBOX_DVD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RDA_INTC policy<{'armhf': 'y'}> +CONFIG_RDA_TIMER policy<{'armhf': 'y'}> +CONFIG_RDMA_RXE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RDMA_SIW policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RDS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RDS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RDS_RDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RDS_TCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RD_BZIP2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_GZIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_LZ4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_LZMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_XZ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_READABLE_ASM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_READ_ONLY_THP_FOR_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_REALTEK_AUTOPM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REALTEK_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_REALTEK_PHY_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REBOOT_MODE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REDMI_WMI policy<{'amd64': 'm'}> +CONFIG_REED_SOLOMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REED_SOLOMON_DEC16 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REED_SOLOMON_DEC8 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REED_SOLOMON_ENC8 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REED_SOLOMON_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_REGMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_REGMAP_AC97 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGMAP_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_REGMAP_I3C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_REGMAP_MMIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_REGMAP_SCCB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_SLIMBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_SOUNDWIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_SOUNDWIRE_MBQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REGMAP_SPI_AVMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_SPMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_W1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_REGULATOR_88PG86X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_88PM800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_88PM8607 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_88PM886 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_AAT2870 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_ACT8865 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_ACT8945A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_AD5398 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_ADP5055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_ANATOP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_ARIZONA_LDO1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_ARIZONA_MICSUPP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_ARM_SCMI policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_REGULATOR_AS3711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_AS3722 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_ATC260X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_AW37503 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_AXP20X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BCM590XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD71815 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD71828 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD718XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD9571MWV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD957XMUF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD96801 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BQ257XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_CROS_EC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_DA903X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_DA9055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_DA9062 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_DA9063 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_DA9121 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_DA9210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_DA9211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_REGULATOR_DUMMY_CONSUMER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_REGULATOR_FAN53555 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_FAN53880 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_FIXED_VOLTAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_FP9931 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_HI6421 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_HI6421V530 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_HI6421V600 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_HI655X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_ISL6271A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_ISL9305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LM363X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_LOCHNAGAR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_LP3971 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LP3972 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LP872X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LP873X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_LP8755 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LP87565 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_LP8788 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LTC3589 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LTC3676 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX14577 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX1586 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX20086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX20411 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX5970 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77503 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77541 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77620 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77650 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77675 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77686 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77693 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX77802 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77826 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX77838 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77857 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX8649 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8660 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8893 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8907 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX8925 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8952 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8973 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX8997 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8998 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MC13783 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MC13892 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MC13XXX_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MCP16502 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MP5416 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MP8859 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MP886X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MPQ7920 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MT6315 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6316 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6331 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6332 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6357 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6358 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6359 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6363 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6380 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_MT6397 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MTK_DVFSRC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_NETLINK_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REGULATOR_PALMAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PBIAS policy<{'armhf': 'm'}> +CONFIG_REGULATOR_PCA9450 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PCAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PF0900 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PF1550 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PF530X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PF8X00 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PF9453 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PFUZE100 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PV88060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PV88080 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PV88090 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_QCOM_LABIBB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_QCOM_PM8008 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_QCOM_REFGEN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_QCOM_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_QCOM_RPMH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_QCOM_SMD_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_QCOM_SPMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_QCOM_USB_VBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RAA215300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_REGULATOR_RC5T583 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RK808 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RN5T618 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_ROHM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT4801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RT4803 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT4831 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5120 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5133 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5190A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5739 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5759 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT6160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RT6190 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT6245 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RT8092 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RTMV20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RTQ2134 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RTQ2208 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RTQ6752 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RZG2L_VBCTRL policy<{'arm64': 'y'}> +CONFIG_REGULATOR_S2DOS05 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_S2MPA01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_S2MPS11 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_S5M8767 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SC2731 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_SKY81452 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SLG51000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_STM32_BOOSTER policy<{'arm64': 'm'}> +CONFIG_REGULATOR_STM32_PWR policy<{'arm64': 'y'}> +CONFIG_REGULATOR_STM32_VREFBUF policy<{'arm64': 'm'}> +CONFIG_REGULATOR_STPMIC1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SUN20I policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_REGULATOR_SY7636A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SY8106A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SY8824X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SY8827N policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TI_ABB policy<{'armhf': 'y'}> +CONFIG_REGULATOR_TPS51632 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS6105X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS62360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS6286X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS6287X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS65023 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS6507X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS65086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS65090 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS65132 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS65185 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS65218 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS65219 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS6524X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS6586X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS65910 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS65912 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS6594 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS68470 policy<{'amd64': 'm'}> +CONFIG_REGULATOR_USERSPACE_CONSUMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_VCTRL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_VEXPRESS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_VIRTUAL_CONSUMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_VQMMC_IPQ4019 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_WM8350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_WM8400 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_WM8994 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RELAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RELOCATABLE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RELOCATABLE_TEST policy<{'ppc64el': 'n'}> +CONFIG_RELR policy<{'arm64': 'n'}> +CONFIG_REMOTEPROC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_REMOTEPROC_CDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REMOTE_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RENESAS_DMA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RENESAS_ETHER_SWITCH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_GEN4_PTP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_I3C policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_INTC_IRQPIN policy<{'armhf': 'y'}> +CONFIG_RENESAS_IRQC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RENESAS_OSTM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RENESAS_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RENESAS_RPCIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_RZA1_IRQC policy<{'armhf': 'y'}> +CONFIG_RENESAS_RZAWDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_RZG2LWDT policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_RENESAS_RZG2L_IRQC policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_RENESAS_RZN1WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_RZT2H_ICU policy<{'arm64': 'y'}> +CONFIG_RENESAS_RZV2HWDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_RZV2H_ICU policy<{'arm64': 'y'}> +CONFIG_RENESAS_USB_DMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_WWDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESCTRL_FS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_RESCTRL_FS_PSEUDO_LOCK policy<{'amd64': 'y'}> +CONFIG_RESCTRL_RMID_DEPENDS_ON_CLOSID policy<{'arm64': 'y'}> +CONFIG_RESET_A10SR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_ASPEED policy<{'armhf': 'm'}> +CONFIG_RESET_ATTACK_MITIGATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_RESET_BERLIN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_CONTROLLER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_RESET_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RESET_HISI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_IMX7 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_IMX8MP_AUDIOMIX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_IMX_SCU policy<{'arm64': 'm'}> +CONFIG_RESET_MCHP_SPARX5 policy<{'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RESET_MESON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_MESON_AUDIO_ARB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_MESON_AUX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_MESON_COMMON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_NPCM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_NUVOTON_MA35D1 policy<{'arm64': 'y'}> +CONFIG_RESET_POLARFIRE_SOC policy<{'arm64': 'y'}> +CONFIG_RESET_QCOM_AOSS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_QCOM_PDC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_RZG2L_USBPHY_CTRL policy<{'arm64': 'y'}> +CONFIG_RESET_RZV2H_USB2PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_SIMPLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RESET_SKY1 policy<{'arm64': 'y'}> +CONFIG_RESET_SOCFPGA policy<{'armhf': 'y'}> +CONFIG_RESET_SUNPLUS policy<{'armhf': 'y'}> +CONFIG_RESET_SUNXI policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_RESET_TEGRA_BPMP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_TI_SCI policy<{'arm64': 'm'}> +CONFIG_RESET_TI_SYSCON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RESET_TI_TPS380X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RESET_TN48M_CPLD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_RETHOOK policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RETU_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RFD77402 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RFD_FTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RFKILL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_RFKILL_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RFKILL_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RFKILL_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RFS_ACCEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RICHTEK_RTQ6056 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RING_BUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RING_BUFFER_BENCHMARK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RING_BUFFER_STARTUP_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RIONET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RIONET_RX_SIZE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128'}> +CONFIG_RIONET_TX_SIZE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128'}> +CONFIG_RISCV policy<{'riscv64': 'y'}> +CONFIG_RISCV_ALTERNATIVE policy<{'riscv64': 'y'}> +CONFIG_RISCV_APLIC policy<{'riscv64': 'y'}> +CONFIG_RISCV_APLIC_MSI policy<{'riscv64': 'y'}> +CONFIG_RISCV_BOOT_SPINWAIT policy<{'riscv64': 'n'}> +CONFIG_RISCV_COMBO_SPINLOCKS policy<{'riscv64': 'y'}> +CONFIG_RISCV_DMA_NONCOHERENT policy<{'riscv64': 'y'}> +CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS policy<{'riscv64': 'n'}> +CONFIG_RISCV_IMSIC policy<{'riscv64': 'y'}> +CONFIG_RISCV_INTC policy<{'riscv64': 'y'}> +CONFIG_RISCV_IOMMU policy<{'riscv64': 'y'}> +CONFIG_RISCV_IOMMU_PCI policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_C policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_FALLBACK policy<{'riscv64': 'n'}> +CONFIG_RISCV_ISA_SUPM policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_SVNAPOT policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_SVPBMT policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_SVRSW60T59B policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_V policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_VENDOR_EXT policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_VENDOR_EXT_ANDES policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_VENDOR_EXT_MIPS policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_VENDOR_EXT_THEAD policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_V_PREEMPTIVE policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD policy<{'riscv64': '768'}> +CONFIG_RISCV_ISA_XTHEADVECTOR policy<{'riscv64': 'n'}> +CONFIG_RISCV_ISA_ZABHA policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZACAS policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZAWRS policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZBA policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZBB policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZBC policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZBKB policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZICBOM policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZICBOP policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZICBOZ policy<{'riscv64': 'y'}> +CONFIG_RISCV_MISALIGNED policy<{'riscv64': 'y'}> +CONFIG_RISCV_PMU policy<{'riscv64': 'y'}> +CONFIG_RISCV_PMU_LEGACY policy<{'riscv64': 'y'}> +CONFIG_RISCV_PMU_SBI policy<{'riscv64': 'y'}> +CONFIG_RISCV_PROBE_UNALIGNED_ACCESS policy<{'riscv64': 'y'}> +CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS policy<{'riscv64': 'y'}> +CONFIG_RISCV_RPMI_SYSMSI policy<{'riscv64': 'y'}> +CONFIG_RISCV_SBI policy<{'riscv64': 'y'}> +CONFIG_RISCV_SBI_CPUIDLE policy<{'riscv64': 'y'}> +CONFIG_RISCV_SBI_MPXY_MBOX policy<{'riscv64': 'm'}> +CONFIG_RISCV_SBI_V01 policy<{'riscv64': 'n'}> +CONFIG_RISCV_SCALAR_MISALIGNED policy<{'riscv64': 'y'}> +CONFIG_RISCV_TICKET_SPINLOCKS policy<{'riscv64': 'n'}> +CONFIG_RISCV_TIMER policy<{'riscv64': 'y'}> +CONFIG_RISCV_USER_CFI policy<{'riscv64': 'y'}> +CONFIG_RISCV_VECTOR_MISALIGNED policy<{'riscv64': 'y'}> +CONFIG_RMI4_2D_SENSOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RMI4_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RMI4_F03 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F03_SERIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RMI4_F11 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F12 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F1A policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RMI4_F21 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RMI4_F30 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F34 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F3A policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F54 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RMI4_F55 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RMI4_SMB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RMI4_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RMNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RN5T618_ADC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RN5T618_POWER policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RN5T618_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ROCKCHIP_ANALOGIX_DP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_CDN_DP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_DTPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ROCKCHIP_DW_DP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_DW_HDMI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_DW_HDMI_QP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_DW_MIPI_DSI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_DW_MIPI_DSI2 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_ERRATUM_3568002 policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_ERRATUM_3588001 policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_GRF policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_INNO_HDMI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_IODOMAIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ROCKCHIP_IOMMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_LVDS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_MBOX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ROCKCHIP_PM_DOMAINS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_RGB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_RK3066_HDMI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_SARADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ROCKCHIP_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ROCKCHIP_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_VOP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_VOP2 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ROHM_BD79112 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ROHM_BD79124 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ROHM_BM1390 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ROHM_BU27034 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ROMFS_BACKED_BY_BLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ROMFS_BACKED_BY_BOTH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ROMFS_BACKED_BY_MTD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ROMFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ROMFS_ON_BLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RPCSEC_GSS_KRB5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RPMB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RPMSG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_CHAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_CTRL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_MTK_SCP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RPMSG_NS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_QCOM_GLINK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_QCOM_GLINK_RPM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RPMSG_QCOM_GLINK_SMEM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RPMSG_QCOM_SMD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RPMSG_TTY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RPMSG_WWAN_CTRL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPR0521 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RSEQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RSEQ_DEBUG_DEFAULT_ENABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RSEQ_SLICE_EXTENSION policy<{'amd64': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RSEQ_STATS policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RSI_91X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RSI_COEX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RSI_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RSI_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RSI_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RST_RCAR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RT2400PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2500PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2500USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2800PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2800PCI_RT3290 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800PCI_RT33XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800PCI_RT35XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800PCI_RT53XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2800USB_RT33XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB_RT3573 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB_RT35XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB_RT53XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB_RT55XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB_UNKNOWN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2800_LIB_MMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2X00 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2X00_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RT2X00_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2X00_LIB_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2X00_LIB_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RT2X00_LIB_FIRMWARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2X00_LIB_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2X00_LIB_MMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2X00_LIB_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2X00_LIB_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT61PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT73USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTASE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTAS_ERROR_LOGGING policy<{'ppc64el': 'y'}> +CONFIG_RTAS_FLASH policy<{'ppc64el': 'm'}> +CONFIG_RTAS_PROC policy<{'ppc64el': 'y'}> +CONFIG_RTC_CLASS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_88PM80X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_88PM886 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ABB5ZES3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ABEOZ9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ABX80X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_AMLOGIC_A4 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_ARMADA38X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_AS3722 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ASPEED policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_BBNSM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_BD70528 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_BQ32K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_CADENCE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_CV1800 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_RTC_DRV_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DA9055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DA9063 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1286 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1302 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1307 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1307_CENTURY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_DS1343 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1347 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1374 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1374_WDT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_DS1390 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1511 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1553 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1672 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1685 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_DS1685_FAMILY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1689 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_DS17285 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_DS1742 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS17485 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_DS17885 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_DS2404 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS3232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS3232_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_EM3027 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_FM3130 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_FSL_FTM_ALARM policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_FTRTC010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_GENERIC policy<{'ppc64el': 'y'}> +CONFIG_RTC_DRV_GOLDFISH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'y'}> +CONFIG_RTC_DRV_HID_SENSOR_TIME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_HYM8563 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_IMXDI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_IMX_BBM_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_IMX_SC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_ISL12022 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ISL12026 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ISL1208 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_LP8788 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M41T80 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M41T80_WDT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_M41T93 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M41T94 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M48T35 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M48T59 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M48T86 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MA35D1 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MACSMC policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX31335 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX6900 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX6902 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX6916 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX77686 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX8907 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX8925 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX8997 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX8998 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MC13XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MCP795 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MESON policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_MESON_VRTC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_MSC313 policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_MSM6242 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MT2712 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_MT6397 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MT7622 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_MV policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RTC_DRV_MXC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_MXC_V2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_NCT3018Y policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_NTXEC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_NVIDIA_VRS10 policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_RTC_DRV_OMAP policy<{'armhf': 'y'}> +CONFIG_RTC_DRV_OPAL policy<{'ppc64el': 'y'}> +CONFIG_RTC_DRV_OPTEE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_PALMAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF2123 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF2127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF85063 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF8523 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF85363 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF8563 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF8583 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PL030 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_RTC_DRV_PL031 policy<{'arm64': 'm', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_RTC_DRV_PM8XXX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_R7301 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_R9701 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RC5T583 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RC5T619 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RENESAS_RTCA3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_RK808 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RP5C01 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RS5C348 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RS5C372 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RTD119X policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RTC_DRV_RV3028 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RV3029C2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RV3029_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_RV3032 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RV8803 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX4581 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX6110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX8010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX8025 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX8111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX8581 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RZN1 policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_S32G policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_S35390A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_S3C policy<{'armhf': 'n'}> +CONFIG_RTC_DRV_S5M policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_SA1100 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_SC27XX policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_SD2405AL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_SD3078 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_SH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_SNVS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_SSD202D policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_STK17TA8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_STM32 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_SUN6I policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_RTC_DRV_SUNPLUS policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_TI_K3 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_TPS6586X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_TPS65910 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_TPS6594 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_WILCO_EC policy<{'amd64': 'm'}> +CONFIG_RTC_DRV_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_WM8350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_X1205 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_XGENE policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_ZYNQMP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_HCTOSYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_HCTOSYS_DEVICE policy<{'amd64': '"rtc0"', 'arm64': '"rtc0"', 'armhf': '"rtc0"', 'ppc64el': '"rtc0"', 'riscv64': '"rtc0"'}> +CONFIG_RTC_I2C_AND_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_INTF_DEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_INTF_DEV_UIE_EMUL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_INTF_PROC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_INTF_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_LIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_MC146818_LIB policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_RTC_NVMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_SYSTOHC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_SYSTOHC_DEVICE policy<{'amd64': '"rtc0"', 'arm64': '"rtc0"', 'armhf': '"rtc0"', 'ppc64el': '"rtc0"', 'riscv64': '"rtc0"'}> +CONFIG_RTD119X_WATCHDOG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RTK_SYSTIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RTL8180 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8187 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8187_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTL8188EE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192CE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192CU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192C_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192DE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192DU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192D_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192EE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192SE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8723AE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8723BE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8723BS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8723_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8821AE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8XXXU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8XXXU_UNTESTED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTLBTCOEXIST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTLWIFI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTLWIFI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTLWIFI_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTLWIFI_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL_CARDS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTSN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTW88 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8703B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723CS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723DE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723DS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723DU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8812A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8812AU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8814A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8814AE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8814AU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821AU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821CE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821CS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821CU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822BE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822BS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822BU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822CE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822CS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822CU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_88XXA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW88_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW88_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW88_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8851B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8851BE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8851BU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852AE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852AU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852BE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852BT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852BTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852BU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852B_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852CE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852CU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8922A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8922AE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW89_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW89_DEBUGMSG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW89_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT_MUTEXES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUNTIME_KERNEL_TESTING_MENU policy<{'riscv64': 'n'}> +CONFIG_RUNTIME_TESTING_MENU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUSTC_LLVM_MAJOR_VERSION policy<{'amd64': '19', 'arm64': '19', 'armhf': '19', 'ppc64el': '19', 'riscv64': '19', 's390x': '19'}> +CONFIG_RUSTC_LLVM_VERSION policy<{'amd64': '190101', 'arm64': '190101', 'armhf': '190101', 'ppc64el': '190101', 'riscv64': '190101', 's390x': '190101'}> +CONFIG_RUSTC_SUPPORTS_ARM64 policy<{'arm64': 'y'}> +CONFIG_RUSTC_SUPPORTS_RISCV policy<{'riscv64': 'y'}> +CONFIG_RUSTC_VERSION policy<{'amd64': '108200', 'arm64': '108200', 'armhf': '108200', 'ppc64el': '108200', 'riscv64': '108200', 's390x': '108200'}> +CONFIG_RV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RVU_ESWITCH policy<{'arm64': 'm'}> +CONFIG_RV_HA_MONITOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_MON_DEADLINE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_MON_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_MON_MAINTENANCE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_MON_NOMISS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_MON_RTAPP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RV_MON_STALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_MON_WWNR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_PER_TASK_MONITORS policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2', 's390x': '2'}> +CONFIG_RV_REACTORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_REACT_PANIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_REACT_PRINTK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RWSEM_SPIN_ON_OWNER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RXGK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RXKAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RXPERF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RZG2L_ADC policy<{'arm64': 'm'}> +CONFIG_RZG2L_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RZG3E_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RZG3S_THERMAL policy<{'arm64': 'm'}> +CONFIG_RZN1_ADC policy<{'armhf': 'm'}> +CONFIG_RZN1_DMAMUX policy<{'armhf': 'm'}> +CONFIG_RZN1_IRQMUX policy<{'armhf': 'y'}> +CONFIG_RZT2H_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RZ_DMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RZ_MTU3 policy<{'arm64': 'y'}> +CONFIG_RZ_MTU3_CNT policy<{'arm64': 'm'}> +CONFIG_S32G_WDT policy<{'arm64': 'm'}> +CONFIG_S390 policy<{'s390x': 'y'}> +CONFIG_S390_GUEST policy<{'s390x': 'y'}> +CONFIG_S390_HYPFS policy<{'s390x': 'y'}> +CONFIG_S390_HYPFS_FS policy<{'s390x': 'y'}> +CONFIG_S390_IOMMU policy<{'s390x': 'y'}> +CONFIG_S390_PRNG policy<{'s390x': 'm'}> +CONFIG_S390_TAPE policy<{'s390x': 'm'}> +CONFIG_S390_VMUR policy<{'s390x': 'm'}> +CONFIG_S3C2410_WATCHDOG policy<{'armhf': 'n'}> +CONFIG_S5P_DEV_MFC policy<{'armhf': 'y'}> +CONFIG_SAMPLES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SAMPLE_AUXDISPLAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SAMPLE_CONFIGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_FPROBE policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_FTRACE_DIRECT policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_FTRACE_DIRECT_MULTI policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_FTRACE_OPS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_HUNG_TASK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SAMPLE_HW_BREAKPOINT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n'}> +CONFIG_SAMPLE_KDB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SAMPLE_KFIFO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_KOBJECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_KPROBES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_LIVEPATCH policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_QMI_CLIENT policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_SAMPLE_RPMSG_CLIENT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SAMPLE_TRACE_ARRAY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_TRACE_EVENTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_TSM_MR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MBOCHS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MDPY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MTTY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_WATCHDOG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SAMSUNG_GALAXYBOOK policy<{'amd64': 'm'}> +CONFIG_SAMSUNG_LAPTOP policy<{'amd64': 'm'}> +CONFIG_SAMSUNG_MC policy<{'armhf': 'y'}> +CONFIG_SAMSUNG_Q10 policy<{'amd64': 'm'}> +CONFIG_SAR_GCC_2130P policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SAR_GPUCC_2130P policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SATA_ACARD_AHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_AHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_AHCI_SEATTLE policy<{'arm64': 'm'}> +CONFIG_SATA_DWC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_DWC_OLD_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SATA_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SATA_INIC162X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_MOBILE_LPM_POLICY policy<{'amd64': '3', 'arm64': '3', 'armhf': '3', 'ppc64el': '3', 'riscv64': '3'}> +CONFIG_SATA_MV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_NV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_PMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SATA_PROMISE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_QSTOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SATA_SIL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_SIL24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_SIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_SVW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_SX4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_ULI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_VIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_VITESSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_ZPODD policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_SA_CAMCC_8775P policy<{'arm64': 'm'}> +CONFIG_SA_DISPCC_8775P policy<{'arm64': 'm'}> +CONFIG_SA_GCC_8775P policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_SA_GPUCC_8775P policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SA_VIDEOCC_8775P policy<{'arm64': 'm'}> +CONFIG_SBC_EPX_C3_WATCHDOG policy<{'amd64': 'm'}> +CONFIG_SBC_FITPC2_WATCHDOG policy<{'amd64': 'm'}> +CONFIG_SBITMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SBP_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SC1200_WDT policy<{'amd64': 'm'}> +CONFIG_SC27XX_ADC policy<{'arm64': 'm'}> +CONFIG_SC92031 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCA3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCA3300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCD30_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCD30_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCD30_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCD4X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCF_TORTURE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SCHEDSTATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_AUTOGROUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_CLASS_EXT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_CLUSTER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_SCHED_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_SCHED_HRTICK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_HW_PRESSURE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SCHED_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_MC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_MC_PRIO policy<{'amd64': 'y'}> +CONFIG_SCHED_MM_CID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_OMIT_FRAME_POINTER policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_SCHED_PROXY_EXEC policy<{'armhf': 'y'}> +CONFIG_SCHED_SMT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_SCHED_STACK_END_CHECK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_TOPOLOGY policy<{'s390x': 'y'}> +CONFIG_SCHED_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCLP_CONSOLE policy<{'s390x': 'y'}> +CONFIG_SCLP_TTY policy<{'s390x': 'y'}> +CONFIG_SCLP_VT220_CONSOLE policy<{'s390x': 'y'}> +CONFIG_SCLP_VT220_TTY policy<{'s390x': 'y'}> +CONFIG_SCM_BLOCK policy<{'s390x': 'm'}> +CONFIG_SCM_BUS policy<{'s390x': 'y'}> +CONFIG_SCOM_DEBUGFS policy<{'ppc64el': 'y'}> +CONFIG_SCREEN_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_SCSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_3W_9XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_3W_SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_AACRAID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_ACARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_ADVANSYS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_AIC79XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_AIC7XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_AIC94XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_AM53C974 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_ARCMSR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_BFA_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_BNX2X_FCOE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_BNX2_ISCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_BUSLOGIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_CHELSIO_FCOE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_CONSTANTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_CXGB3_ISCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_CXGB4_ISCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_DC395x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_DEBUG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_DH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_DH_ALUA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_DH_EMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_DH_HP_SW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_DH_RDAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_DMX3191D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_EFCT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_ENCLOSURE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_ESAS2R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_FC_ATTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_FDOMAIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_FDOMAIN_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_FLASHPOINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_HISI_SAS policy<{'arm64': 'm'}> +CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE policy<{'arm64': 'n'}> +CONFIG_SCSI_HISI_SAS_PCI policy<{'arm64': 'm'}> +CONFIG_SCSI_HPSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_HPTIOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_IBMVFC policy<{'ppc64el': 'm'}> +CONFIG_SCSI_IBMVFC_TRACE policy<{'ppc64el': 'y'}> +CONFIG_SCSI_IBMVSCSI policy<{'ppc64el': 'm'}> +CONFIG_SCSI_IBMVSCSIS policy<{'ppc64el': 'm'}> +CONFIG_SCSI_IMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_INIA100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_INITIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_IPR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_IPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_ISCI policy<{'amd64': 'm'}> +CONFIG_SCSI_ISCSI_ATTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_IZIP_SLOW_CTR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SCSI_LOGGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_LOWLEVEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_LOWLEVEL_PCMCIA policy<{'amd64': 'y'}> +CONFIG_SCSI_LPFC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_LPFC_DEBUG_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SCSI_MOD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_MPI3MR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_MPT2SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_MPT2SAS_MAX_SGE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128', 's390x': '128'}> +CONFIG_SCSI_MPT3SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_MPT3SAS_MAX_SGE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128', 's390x': '128'}> +CONFIG_SCSI_MVSAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_MVSAS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SCSI_MVSAS_TASKLET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SCSI_MVUMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_MYRB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_MYRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_NETLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_NSP32 policy<{'armhf': 'm'}> +CONFIG_SCSI_PM8001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_PMCRAID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_PPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_PROC_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_QLA_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_QLA_ISCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_QLOGIC_1280 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_SAS_ATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_SAS_ATTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_SAS_HOST_SMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_SAS_LIBSAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_SCAN_ASYNC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_SMARTPQI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_SNIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_SNIC_DEBUG_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SCSI_SPI_ATTRS policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_SRP_ATTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_STEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS policy<{'amd64': '16', 'arm64': '16', 'armhf': '16', 'ppc64el': '16', 'riscv64': '16'}> +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_SCSI_SYM53C8XX_MAX_TAGS policy<{'amd64': '64', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64'}> +CONFIG_SCSI_SYM53C8XX_MMIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_UFSHCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_UFSHCD_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_UFSHCD_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_UFS_AMD_VERSAL2 policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_BSG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_UFS_CDNS_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_UFS_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_UFS_DWC_TC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_UFS_DWC_TC_PLATFORM policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_UFS_EXYNOS policy<{'armhf': 'n'}> +CONFIG_SCSI_UFS_HISI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SCSI_UFS_HWMON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SCSI_UFS_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SCSI_UFS_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SCSI_UFS_RENESAS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SCSI_UFS_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SCSI_UFS_SPRD policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_TI_J721E policy<{'arm64': 'm'}> +CONFIG_SCSI_WD719X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCTP_DBG_OBJCNT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SC_CAMCC_7180 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_CAMCC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_CAMCC_8180X policy<{'arm64': 'm'}> +CONFIG_SC_CAMCC_8280XP policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_DISPCC_7180 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_DISPCC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_DISPCC_8280XP policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_GCC_7180 policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SC_GCC_7280 policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SC_GCC_8180X policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SC_GCC_8280XP policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SC_GPUCC_7180 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_GPUCC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_GPUCC_8280XP policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_LPASSCC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_LPASSCC_8280XP policy<{'arm64': 'm'}> +CONFIG_SC_LPASS_CORECC_7180 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_LPASS_CORECC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_VIDEOCC_7180 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_VIDEOCC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDIO_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SDMA_VERBOSITY policy<{'amd64': 'n'}> +CONFIG_SDM_CAMCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_DISPCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_GCC_660 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_GCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_GPUCC_660 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_GPUCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_LPASSCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_MMCC_660 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_VIDEOCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDP500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SDR_MAX2175 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SDR_PLATFORM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SDX_GCC_55 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_SDX_GCC_65 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_SDX_GCC_75 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SD_ADC_MODULATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SECCOMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECCOMP_CACHE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECCOMP_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECONDARY_TRUSTED_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECRETMEM policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECTION_MISMATCH_WARN_ONLY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITYFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_HASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_DMESG_RESTRICT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_INFINIBAND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_IPE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_LANDLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_LOADPIN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_LOCKDOWN_LSM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_NETWORK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_NETWORK_XFRM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_PATH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SELINUX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SELINUX_AVC_HASH_BITS policy<{'amd64': '9', 'arm64': '9', 'armhf': '9', 'ppc64el': '9', 'riscv64': '9', 's390x': '9'}> +CONFIG_SECURITY_SELINUX_AVC_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SELINUX_BOOTPARAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SECURITY_SELINUX_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_SELINUX_DEVELOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE policy<{'amd64': '256', 'arm64': '256', 'armhf': '256', 'ppc64el': '256', 'riscv64': '256', 's390x': '256'}> +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS policy<{'amd64': '9', 'arm64': '9', 'armhf': '9', 'ppc64el': '9', 'riscv64': '9', 's390x': '9'}> +CONFIG_SECURITY_SMACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SMACK_APPEND_SIGNALS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SMACK_BRINGUP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_SMACK_NETFILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_TOMOYO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER policy<{'amd64': '"/sbin/init"', 'arm64': '"/sbin/init"', 'armhf': '"/sbin/init"', 'ppc64el': '"/sbin/init"', 'riscv64': '"/sbin/init"', 's390x': '"/sbin/init"'}> +CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY policy<{'amd64': '2048', 'arm64': '2048', 'armhf': '2048', 'ppc64el': '2048', 'riscv64': '2048', 's390x': '2048'}> +CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG policy<{'amd64': '1024', 'arm64': '1024', 'armhf': '1024', 'ppc64el': '1024', 'riscv64': '1024', 's390x': '1024'}> +CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_TOMOYO_POLICY_LOADER policy<{'amd64': '"/sbin/tomoyo-init"', 'arm64': '"/sbin/tomoyo-init"', 'armhf': '"/sbin/tomoyo-init"', 'ppc64el': '"/sbin/tomoyo-init"', 'riscv64': '"/sbin/tomoyo-init"', 's390x': '"/sbin/tomoyo-init"'}> +CONFIG_SECURITY_YAMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SEG_LED_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SEL3350_PLATFORM policy<{'amd64': 'm'}> +CONFIG_SELECT_MEMORY_MODEL policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SEN0322 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSEAIR_SUNRISE_CO2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSIRION_SGP30 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSIRION_SGP40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ABITUGURU policy<{'amd64': 'm'}> +CONFIG_SENSORS_ABITUGURU3 policy<{'amd64': 'm'}> +CONFIG_SENSORS_ACBEL_FSG032 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ACPI_POWER policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_AD7314 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_AD7414 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_AD7418 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADC128D818 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADCXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1025 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1026 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1029 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1031 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1177 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1266 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ADM1275 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ADM9240 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADP1050 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ADP1050_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_ADS7828 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADS7871 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7310 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7410 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7411 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7462 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7470 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7475 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7X10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_AHT10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_AMC6821 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_APDS990X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SENSORS_APPLESMC policy<{'amd64': 'm'}> +CONFIG_SENSORS_APS_379 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ARM_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SENSORS_ARM_SCPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SENSORS_AS370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ASB100 policy<{'amd64': 'm'}> +CONFIG_SENSORS_ASC7621 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ASPEED policy<{'armhf': 'm'}> +CONFIG_SENSORS_ASPEED_G6 policy<{'armhf': 'm'}> +CONFIG_SENSORS_ASUS_EC policy<{'amd64': 'm'}> +CONFIG_SENSORS_ASUS_ROG_RYUJIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ASUS_WMI policy<{'amd64': 'm'}> +CONFIG_SENSORS_ATK0110 policy<{'amd64': 'm'}> +CONFIG_SENSORS_ATXP1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_AXI_FAN_CONTROL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_BEL_PFE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_BH1770 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SENSORS_BPA_RS600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_CGBC policy<{'amd64': 'm'}> +CONFIG_SENSORS_CHIPCAP2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_CORETEMP policy<{'amd64': 'm'}> +CONFIG_SENSORS_CORSAIR_CPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_CORSAIR_PSU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SENSORS_CRPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_DA9052_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_DA9055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_DELL_SMM policy<{'amd64': 'm'}> +CONFIG_SENSORS_DELTA_AHE50DC_FAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_DME1737 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_DPS920AB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_DRIVETEMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_DS1621 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_DS620 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_EMC1403 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_EMC2103 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_EMC2305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_EMC6W201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_F71805F policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_F71882FG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_F75375S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_FAM15H_POWER policy<{'amd64': 'm'}> +CONFIG_SENSORS_FSCHMD policy<{'amd64': 'm'}> +CONFIG_SENSORS_FSP_3Y policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_FTSTEUTATES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_G760A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_G762 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_GIGABYTE_WATERFORCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_GL518SM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_GL520SM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_GPD policy<{'amd64': 'm'}> +CONFIG_SENSORS_GPIO_FAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_GSC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_GXP_FAN_CTRL policy<{'armhf': 'm'}> +CONFIG_SENSORS_HAC300S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_HDAPS policy<{'amd64': 'm'}> +CONFIG_SENSORS_HIH6130 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_HMC5843 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_HMC5843_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_HMC5843_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_HP_WMI policy<{'amd64': 'm'}> +CONFIG_SENSORS_HS3001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_HTU31 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_I5500 policy<{'amd64': 'm'}> +CONFIG_SENSORS_I5K_AMB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_IBMAEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IBMPEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IBMPOWERNV policy<{'ppc64el': 'm'}> +CONFIG_SENSORS_IBM_CFFPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IIO_HWMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_INA209 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_INA233 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_INA238 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_INA2XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_INA3221 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_INSPUR_IPSPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_INTEL_M10_BMC_HWMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IR35221 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IR36021 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IR38064 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IR38064_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_IRPS5401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ISL28022 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ISL29018 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ISL29028 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ISL68137 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IT87 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_JC42 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_K10TEMP policy<{'amd64': 'm'}> +CONFIG_SENSORS_K8TEMP policy<{'amd64': 'm'}> +CONFIG_SENSORS_KBATT policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SENSORS_KFAN policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SENSORS_LATTEPANDA_SIGMA_EC policy<{'amd64': 'm'}> +CONFIG_SENSORS_LENOVO_EC policy<{'amd64': 'm'}> +CONFIG_SENSORS_LINEAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LIS3LV02D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LIS3_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SENSORS_LIS3_SPI policy<{'armhf': 'm', 'ppc64el': 'm', 'riscv64': '-', 's390x': '-'}> +CONFIG_SENSORS_LM25066 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LM25066_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_LM3533 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LM63 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM70 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM73 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM75 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM77 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM78 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM80 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM83 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM85 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM87 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM90 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM92 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM93 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM95234 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM95241 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM95245 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LOCHNAGAR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LT3074 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LT3074_REGULATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LT7182S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC2945 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC2947 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC2947_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC2947_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC2978 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC2978_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_LTC2990 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC2991 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC2992 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC3815 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC4151 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4215 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4222 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4245 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4260 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4261 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4282 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC4286 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_MACSMC_HWMON policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX1111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX15301 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX16064 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX16065 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX1619 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX16601 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX1668 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX17616 policy<{'amd64': 'm', 'arm64-generic': 'm', 'arm64-generic-64k': 'n', 'armhf': 'n', 'ppc64el': 'm', 'riscv64': 'n'}> +CONFIG_SENSORS_MAX197 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX20730 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX20751 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX31722 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX31730 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX31760 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX31785 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX31790 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX34440 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX6620 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX6621 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX6639 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX6650 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX6697 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX77705 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX8688 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MC13783_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MC33XS2410 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MC34VR500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MCP3021 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MCP9982 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MENF21BMC_HWMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MLXREG_FAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SENSORS_MP2856 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2869 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2888 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2891 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2925 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP29502 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2975 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2975_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_MP2993 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP5023 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP5920 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP5926 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP5990 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP9941 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP9945 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MPQ7932 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MPQ7932_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_MPQ8785 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MR75203 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NCT6683 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NCT6775 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NCT6775_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NCT6775_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NCT7363 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NCT7802 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NCT7904 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NPCM7XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NTC_THERMISTOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NZXT_KRAKEN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NZXT_KRAKEN3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NZXT_SMART2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_OCC policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_SENSORS_OCC_P8_I2C policy<{'amd64': 'm', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'm', 'riscv64': 'n'}> +CONFIG_SENSORS_OCC_P9_SBE policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'm', 'riscv64': 'n'}> +CONFIG_SENSORS_PC87360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_PC87427 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_PCF8591 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_PECI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PECI_CPUTEMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PECI_DIMMTEMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PIM4328 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PLI1209BC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PLI1209BC_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_PM6764TR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PMBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_POWERZ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_POWR1220 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_PT5161L policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PWM_FAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PXE1610 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_Q54SJ108A2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_QNAP_MCU_HWMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_RM3100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_RM3100_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_RM3100_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_SBTSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SCH5627 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SCH5636 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SCH56XX_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_SG2042_MCU policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SENSORS_SHT15 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SHT21 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SHT3x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SHT4x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SHTC1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SIS5595 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_SENSORS_SMPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_SMSC47B397 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SMSC47M1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SMSC47M192 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SPARX5 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SPD5118 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_SPD5118_DETECT policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_STEF48H28 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_STPDDC60 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_STTS751 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SURFACE_FAN policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SENSORS_SURFACE_TEMP policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SENSORS_SY7636A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_T14S_FAN_CTRL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SENSORS_TC654 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TC74 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TDA38640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TDA38640_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_THMC50 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP103 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP108 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP421 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP464 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TMP513 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TPS23861 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TPS25990 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TPS25990_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_TPS40422 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TPS53679 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TPS546D24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TSC1641 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TSL2550 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SENSORS_TSL2563 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_UCD9000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_UCD9200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_VEXPRESS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SENSORS_VIA686A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_VIA_CPUTEMP policy<{'amd64': 'm'}> +CONFIG_SENSORS_VT1211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_VT8231 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83627EHF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83627HF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83773G policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83781D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83791D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83792D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83793 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83795 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83795_FANCTRL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SENSORS_W83L785TS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83L786NG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_WM8350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_XDP710 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_XDP720 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_XDPE122 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_XDPE122_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_XDPE152 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_XDPE1A2G7B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_XGENE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_YOGAFAN policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ZL6100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_8250 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_16550A_VARIANTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_ASPEED_VUART policy<{'armhf': 'm'}> +CONFIG_SERIAL_8250_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_CS policy<{'amd64': 'm'}> +CONFIG_SERIAL_8250_DETECT_IRQ policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SERIAL_8250_DFL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_SERIAL_8250_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_DWLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_EM policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_SERIAL_8250_EXAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_8250_EXTENDED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_FINTEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_FSL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_SERIAL_8250_KEBA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SERIAL_8250_LPSS policy<{'amd64': 'm'}> +CONFIG_SERIAL_8250_MANY_PORTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_MEN_MCB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_8250_MT6577 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_8250_NI policy<{'amd64': 'm'}> +CONFIG_SERIAL_8250_NR_UARTS policy<{'amd64': '48', 'arm64': '48', 'armhf': '48', 'ppc64el': '48', 'riscv64': '48'}> +CONFIG_SERIAL_8250_OMAP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_8250_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_PCI1XXXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_SERIAL_8250_PCILIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_PERICOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_8250_PNP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_PXA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_8250_RSA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_RT288X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_RUNTIME_UARTS policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32'}> +CONFIG_SERIAL_8250_SHARE_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_TEGRA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_ALTERA_JTAGUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_ALTERA_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_ALTERA_UART_BAUDRATE policy<{'amd64': '115200', 'arm64': '115200', 'armhf': '115200', 'ppc64el': '115200', 'riscv64': '115200'}> +CONFIG_SERIAL_ALTERA_UART_MAXPORTS policy<{'amd64': '4', 'arm64': '4', 'armhf': '4', 'ppc64el': '4', 'riscv64': '4'}> +CONFIG_SERIAL_AMBA_PL010 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_SERIAL_AMBA_PL011 policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_SERIAL_AMBA_PL011_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_ARC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_ARC_NR_PORTS policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_SERIAL_ATMEL policy<{'arm64': 'y'}> +CONFIG_SERIAL_ATMEL_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_ATMEL_PDC policy<{'arm64': 'y'}> +CONFIG_SERIAL_ATMEL_TTYAT policy<{'arm64': 'n'}> +CONFIG_SERIAL_CONEXANT_DIGICOLOR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_SERIAL_CORE_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_EARLYCON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_EARLYCON_RISCV_SBI policy<{'riscv64': 'y'}> +CONFIG_SERIAL_EARLYCON_SEMIHOST policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_FSL_LINFLEXUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_FSL_LPUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_ICOM policy<{'ppc64el': 'm'}> +CONFIG_SERIAL_IMX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_IMX_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_IMX_EARLYCON policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_SERIAL_IPOCTAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_JSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIAL_LANTIQ policy<{'amd64': 'm'}> +CONFIG_SERIAL_LITEUART policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_LITEUART_MAX_PORTS policy<{'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_SERIAL_MAX3100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIAL_MAX310X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_MCTRL_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_MEN_Z135 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_MESON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_MESON_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_MILBEAUT_USIO policy<{'armhf': 'm'}> +CONFIG_SERIAL_MILBEAUT_USIO_PORTS policy<{'armhf': '4'}> +CONFIG_SERIAL_MSM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_MSM_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_MULTI_INSTANTIATE policy<{'amd64': 'm', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_SERIAL_MVEBU_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_MVEBU_UART policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_NONSTANDARD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SERIAL_NUVOTON_MA35D1 policy<{'arm64': 'm'}> +CONFIG_SERIAL_OF_PLATFORM policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_OWL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_OWL_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_PXA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_PXA_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_QCOM_GENI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_QCOM_GENI_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_QCOM_GENI_UART_PORTS policy<{'arm64': '8', 'armhf': '8'}> +CONFIG_SERIAL_QE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_SERIAL_RDA policy<{'armhf': 'y'}> +CONFIG_SERIAL_RDA_CONSOLE policy<{'armhf': 'y'}> +CONFIG_SERIAL_RP2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_RP2_NR_UARTS policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32'}> +CONFIG_SERIAL_RSCI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIAL_SAMSUNG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIAL_SAMSUNG_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_SAMSUNG_UARTS policy<{'arm64': '4', 'armhf': '4'}> +CONFIG_SERIAL_SC16IS7XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_SC16IS7XX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_SC16IS7XX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_SCCNXP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SERIAL_SCCNXP_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_SH_SCI_DMA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_SH_SCI_NR_UARTS policy<{'arm64': '18', 'armhf': '2'}> +CONFIG_SERIAL_SIFIVE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'y'}> +CONFIG_SERIAL_SIFIVE_CONSOLE policy<{'riscv64': 'y'}> +CONFIG_SERIAL_SPRD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIAL_STM32 policy<{'arm64': 'm'}> +CONFIG_SERIAL_STM32_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_ST_ASC policy<{'armhf': 'm'}> +CONFIG_SERIAL_SUNPLUS policy<{'armhf': 'y'}> +CONFIG_SERIAL_SUNPLUS_CONSOLE policy<{'armhf': 'y'}> +CONFIG_SERIAL_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIAL_TEGRA_TCU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_TEGRA_TCU_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_TEGRA_UTC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIAL_TEGRA_UTC_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_UARTLITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SERIAL_UARTLITE_NR_UARTS policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1', 's390x': '1'}> +CONFIG_SERIAL_XILINX_PS_UART policy<{'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SERIO_ALTERA_PS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_AMBAKMI policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_SERIO_APBPS2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIO_ARC_PS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_GPIO_PS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_I8042 policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_SERIO_LIBPS2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIO_NVEC_PS2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIO_OLPC_APSP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIO_PARKBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIO_PCIPS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_PS2MULT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_SERPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_SUN4I_PS2 policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SERIO_XILINX_XPS_PS2 policy<{'ppc64el': 'm'}> +CONFIG_SEV_GUEST policy<{'amd64': 'm'}> +CONFIG_SFC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SFC_FALCON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SFC_FALCON_MTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_MCDI_LOGGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_MCDI_MON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_MTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_SIENA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SFC_SIENA_MCDI_LOGGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_SIENA_MCDI_MON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_SIENA_MTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_SIENA_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SF_PDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SGETMASK_SYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SGI_GRU policy<{'amd64': 'm'}> +CONFIG_SGI_GRU_DEBUG policy<{'amd64': 'n'}> +CONFIG_SGI_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SGI_XP policy<{'amd64': 'm'}> +CONFIG_SGL_ALLOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SG_POOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SG_SPLIT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SHADOW_CALL_STACK policy<{'arm64': 'y'}> +CONFIG_SHMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SHRINKER_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SHUFFLE_PAGE_ALLOCATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SH_ETH policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_SH_TIMER_CMT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SH_TIMER_MTU2 policy<{'armhf': 'y'}> +CONFIG_SH_TIMER_TMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SI1133 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SI1145 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SI7005 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SI7020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SI7210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC policy<{'amd64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC_BATT policy<{'amd64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC_BATT_APOLLOLAKE policy<{'amd64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC_BATT_ELKHARTLAKE policy<{'amd64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC_BATT_F7188X policy<{'amd64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC_WDT policy<{'amd64': 'm'}> +CONFIG_SIFIVE_PLIC policy<{'riscv64': 'y'}> +CONFIG_SIGNALFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SIGNATURE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SIGNED_PE_FILE_VERIFICATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SILICOM_PLATFORM policy<{'amd64': 'm'}> +CONFIG_SIMPLE_RING_BUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SIOX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SIOX_BUS_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SIS190 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SIS900 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SKB_DECRYPTED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SKB_EXTENSIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SKFP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SKGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SKGE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SKGE_GENESIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SKY2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SKY2_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SL28CPLD_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_SLAB_BUCKETS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLAB_FREELIST_HARDENED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLAB_FREELIST_RANDOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLAB_MERGE_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLAB_OBJ_EXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLHC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SLICOSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SLIC_DS26522 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SLIMBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SLIM_QCOM_NGD_CTRL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SLIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SLIP_COMPRESSED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SLIP_MODE_SLIP6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SLIP_SMART policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SLUB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLUB_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLUB_DEBUG_ON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SLUB_STATS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SLUB_TINY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SMARTJOYPLUS_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SMBDIRECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMBFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMB_SERVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SMB_SERVER_KERBEROS5 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SMB_SERVER_SMBDIRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SMC91X policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SMC_HS_CTRL_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SMI240 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMI330 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMI330_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMI330_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SMPRO_ERRMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMPRO_MISC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMP_ON_UP policy<{'armhf': 'y'}> +CONFIG_SMSC37B787_WDT policy<{'amd64': 'm'}> +CONFIG_SMSC911X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SMSC9420 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SMSC_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMSC_SCH311X_WDT policy<{'amd64': 'm'}> +CONFIG_SMSGIUCV policy<{'s390x': 'y'}> +CONFIG_SMSGIUCV_EVENT policy<{'s390x': 'm'}> +CONFIG_SMS_SDIO_DRV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMS_SIANO_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SMS_SIANO_MDTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMS_SIANO_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SMS_USB_DRV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMT_NUM_THREADS_DYNAMIC policy<{'ppc64el': 'y'}> +CONFIG_SM_CAMCC_4450 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_6350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_CAMCC_7150 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8150 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_CAMCC_8450 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_CAMCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_CAMCC_8650 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_MILOS policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_4450 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_6115 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_6125 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_6350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_6375 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_7150 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_8450 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_MILOS policy<{'arm64': 'm'}> +CONFIG_SM_FTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SM_GCC_4450 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_6115 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_6125 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_6350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_6375 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_7150 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8150 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8450 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8650 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_MILOS policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_4450 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_6115 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_6125 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_6350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_6375 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_8150 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8450 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8650 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_MILOS policy<{'arm64': 'm'}> +CONFIG_SM_LPASSCC_6115 policy<{'arm64': 'm'}> +CONFIG_SM_TCSRCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_TCSRCC_8650 policy<{'arm64': 'm'}> +CONFIG_SM_TCSRCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_6350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_7150 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_8150 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_8350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_8450 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_MILOS policy<{'arm64': 'm'}> +CONFIG_SND_AC97_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AC97_POWER_SAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_AC97_POWER_SAVE_DEFAULT policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_SND_AD1889 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ALI5451 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ALOOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ALS300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ALS4000 policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_SND_AMD_ACP_CONFIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AMD_ASOC_ACP63 policy<{'amd64': 'm'}> +CONFIG_SND_AMD_ASOC_ACP70 policy<{'amd64': 'm'}> +CONFIG_SND_AMD_ASOC_REMBRANDT policy<{'amd64': 'm'}> +CONFIG_SND_AMD_ASOC_RENOIR policy<{'amd64': 'm'}> +CONFIG_SND_AMD_SOUNDWIRE_ACPI policy<{'amd64': 'm'}> +CONFIG_SND_ARM policy<{'armhf': 'y'}> +CONFIG_SND_ARMAACI policy<{'armhf': 'm'}> +CONFIG_SND_ASIHPI policy<{'amd64': 'm'}> +CONFIG_SND_ATIIXP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ATIIXP_MODEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AU8810 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AU8820 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AU8830 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AUDIO_GRAPH_CARD policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AUDIO_GRAPH_CARD2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AW2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AZT3328 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_BCD2000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_BCM63XX_I2S_WHISTLER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_BEBOB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_BT87X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_BT87X_OVERCLOCK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_CA0106 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_CMIPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_COMPRESS_ACCEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_COMPRESS_OFFLOAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_CS4281 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_CS46XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_CS46XX_NEW_DSP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_CTL_FAST_LOOKUP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_CTL_INPUT_VALIDATION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_CTL_LED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_CTXFI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DARLA20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DARLA24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_DESIGNWARE_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DESIGNWARE_PCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_DICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DMAENGINE_PCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DMA_SGBUF policy<{'amd64': 'y'}> +CONFIG_SND_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DYNAMIC_MINORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_ECHO3G policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_EMU10K1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_EMU10K1X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_EMU10K1_SEQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ENS1370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ENS1371 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ES1938 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ES1968 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ES1968_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_SND_ES1968_RADIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_SND_FIREFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FIREWIRE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_FIREWIRE_DIGI00X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FIREWIRE_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FIREWIRE_MOTU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FIREWIRE_TASCAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FIREWORKS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FM801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FM801_TEA575X_BOOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_GINA20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_GINA24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_ALIGNED_MMIO policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SND_HDA_CIRRUS_SCODEC policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CIX_IPBLOQ policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC260 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC262 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC268 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC269 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC662 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC680 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC861 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC861VD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC880 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC882 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ANALOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CA0110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CA0132 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CA0132_DSP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_CODEC_CIRRUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CM9825 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CMEDIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CONEXANT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CS420X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CS421X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CS8409 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_ATI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_INTEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_NVIDIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_NVIDIA_MCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_SIMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_TEGRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_REALTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_REALTEK_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_SENARYTECH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_SI3054 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_SIGMATEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_VIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_COMPONENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CTL_DEV_ID policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_HDA_DSP_LOADER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_EXT_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_GENERIC_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_HWDEP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_I915 policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_SND_HDA_INPUT_BEEP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_INPUT_BEEP_MODE policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_SND_HDA_INTEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_HDA_PATCH_LOADER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_PREALLOC_SIZE policy<{'amd64': '0', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64'}> +CONFIG_SND_HDA_SCODEC_COMPONENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L41 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L41_I2C policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L41_SPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L56 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L56_CAL_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_SND_HDA_SCODEC_CS35L56_I2C policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L56_SPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_TAS2781 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_TAS2781_I2C policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_TAS2781_SPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_HDSP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDSPM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HRTIMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HWDEP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_I2S_HI6210_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ICE1712 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ICE1724 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_IMX_SOC policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_SND_INDIGO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INDIGODJ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INDIGODJX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INDIGOIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INDIGOIOX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INTEL8X0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INTEL8X0M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INTEL_BYT_PREFER_SOF policy<{'amd64': 'y'}> +CONFIG_SND_INTEL_DSP_CONFIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INTEL_NHLT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_SND_INTEL_SOUNDWIRE_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_ISIGHT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_JACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_JACK_INPUT_DEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_KIRKWOOD_SOC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_KORG1212 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_LAYLA20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_LAYLA24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_LOLA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_LX6464ES policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MAESTRO3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MAESTRO3_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_SND_MAX_CARDS policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32'}> +CONFIG_SND_MESON_AIU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_FIFO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_FRDDR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_PDM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_SOUND_CARD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_SPDIFIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_SPDIFOUT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_TDMIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_TDMOUT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_TDM_FORMATTER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_TDM_INTERFACE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_TODDR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_CARD_UTILS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_CODEC_GLUE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_G12A_TOACODEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_G12A_TOHDMITX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_GX_SOUND_CARD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MIXART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MIXER_OSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MMP_SOC_SSPA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MONA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MPU401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MPU401_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MTPAV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MTS64 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_NM256 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_OPL3_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_OPL3_LIB_SEQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_OSSEMUL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_OXFW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_OXYGEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_OXYGEN_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_PCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_PCMCIA policy<{'amd64': 'y'}> +CONFIG_SND_PCMTEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_PCM_ELD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_PCM_IEC958 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_PCM_TIMER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_PCSP policy<{'amd64': 'm'}> +CONFIG_SND_PCXHR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_PDAUDIOCF policy<{'amd64': 'm'}> +CONFIG_SND_PORTMAN2X4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_PPC policy<{'ppc64el': 'y'}> +CONFIG_SND_PROC_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_PXA910_SOC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_RAWMIDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_RIPTIDE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_RME32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_RME96 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_RME9652 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SB_COMMON policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_SND_SEQUENCER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQUENCER_OSS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_SEQ_DEVICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_HRTIMER_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SEQ_MIDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_MIDI_EMUL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_MIDI_EVENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_UMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SEQ_UMP_CLIENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_VIRMIDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SERIAL_GENERIC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SERIAL_U16550 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SIMPLE_CARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SIMPLE_CARD_UTILS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AC97_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SOC_AC97_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ACPI_AMD_MATCH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_ACPI_AMD_SDCA_QUIRKS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_ACPI_INTEL_MATCH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_ACPI_INTEL_SDCA_QUIRKS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_ADAU1372 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1372_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1372_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1373 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1701 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1761 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1761_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1761_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU17X1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU7002 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU7118 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU7118_HW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU7118_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU_UTILS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADI_AXI_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADI_AXI_SPDIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4104 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4118 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4375 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4458 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4554 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4613 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4619 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4642 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK5386 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK5558 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ALC5623 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ALC5632 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_AMD_ACP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AMD_ACP3x policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP5x policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP63_TOPLEVEL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP6x policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACPI_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_I2S policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_LEGACY_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_PCI policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_PCM policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_PDM policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AMD_LEGACY_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_LEGACY_SDW_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_MACH_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_PS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_PS_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_RV_RT5682_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_SDW_MACH_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_SOF_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_SOF_SDW_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_SOUNDWIRE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_SOUNDWIRE_LINK_BASELINE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ST_ES8336_MACH policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AMD_VANGOGH_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_YC_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_APPLE_MCA policy<{'arm64': 'm'}> +CONFIG_SND_SOC_APQ8016_SBC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ARIZONA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AUDIO_IIO_AUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW8738 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW87390 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88081 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88166 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88261 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88395 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88395_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88399 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_BD28623 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_BT_SCO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CHV3_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CHV3_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SOC_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CROS_EC_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_CS35L32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L33 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L34 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L35 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L36 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L41 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L41_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L41_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L41_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L45 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L45_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L45_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L56 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_SOC_CS35L56_CAL_PERFORM_CTRL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_SOC_CS35L56_CAL_SET_CTRL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_SOC_CS35L56_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L56_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L56_SHARED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L56_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS40L50 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4234 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4265 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4270 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4271 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4271_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4271_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L42 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L42_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L42_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L43 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L43_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L51 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L51_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L52 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L56 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L73 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L83 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L84 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42XX8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42XX8_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS43130 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4349 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS48L32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS530X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS530X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS530X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS53L30 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS_AMP_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CV1800B_ADC_CODEC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CV1800B_DAC_CODEC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CV1800B_TDM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CX2072X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_DA7213 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_DA7219 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_DAVINCI_MCASP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_DMIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES7134 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES7241 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8316 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8326 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8328 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8328_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8328_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8375 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8389 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES83XX_DSM_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_EUKREA_TLV320 policy<{'armhf': 'm'}> +CONFIG_SND_SOC_FRAMER policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FS210X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_ASOC_CARD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_FSL_ASRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_AUD2HTX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_FSL_AUDMIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_EASRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_ESAI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_MICFIL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_MQS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_RPMSG policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_SAI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_SPDIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_SSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_UTILS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_XCVR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FS_AMP_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SOC_GTM601 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_HDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_HDAC_HDA policy<{'amd64': 'm'}> +CONFIG_SND_SOC_HDMI_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_I2C_AND_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ICS43432 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_IDT821034 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_IMX_AUDIO_RPMSG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_AUDMIX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_AUDMUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_IMX_CARD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_ES8328 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_PCM_DMA policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_SND_SOC_IMX_PCM_FIQ policy<{'armhf': 'y'}> +CONFIG_SND_SOC_IMX_PCM_RPMSG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_RPMSG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_SGTL5000 policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_SND_SOC_INNO_RK3036 policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_SND_SOC_INTEL_AVS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_CARDNAME_OBSOLETE policy<{'amd64': 'n'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_ES8336 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_PCM3168A policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT274 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT286 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT298 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5514 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5640 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5663 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BROADWELL_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH policy<{'amd64': 'n'}> +CONFIG_SND_SOC_INTEL_CATPT policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_HASWELL_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_KEEMBAY policy<{'arm64': 'm'}> +CONFIG_SND_SOC_INTEL_MACH policy<{'amd64': 'y'}> +CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_BOARD_HELPERS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_CIRRUS_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_DA7219_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_NUVOTON_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_REALTEK_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_TI_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SST_TOPLEVEL policy<{'amd64': 'y'}> +CONFIG_SND_SOC_J721E_EVM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LOCHNAGAR_SC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_LPASS_APQ8016 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_CDC_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_CPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_IPQ806X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_MACRO_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_LPASS_PLATFORM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_RX_MACRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_LPASS_SC7180 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_SC7280 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_TX_MACRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_LPASS_VA_MACRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_LPASS_WSA_MACRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX9759 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98088 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98090 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98357A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98363 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98373 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98373_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98373_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98388 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98390 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98396 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98504 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX9860 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX9867 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98927 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MESON_T9015 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MIKROE_PROTO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MSIOF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MSM8916_WCD_ANALOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MSM8996 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT2701 policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_SND_SOC_MT6351 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MT6357 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MT6358 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MT6359 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT6359_ACCDET policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT6660 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MT6797 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT6797_MT6351 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT7986 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT7986_WM8960 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8173 policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_SND_SOC_MT8183 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8183_DA7219_MAX98357A policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8186 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8186_MT6366 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8188 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8188_MT6359 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8189 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8189_NAU8825 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8192 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8195 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8195_MT6359 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8365 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8365_MT6357 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MTK_BTCVSD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8315 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8325 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8540 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8810 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8821 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8822 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8824 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8825 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_NTP8835 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NTP8918 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NTPFW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_OMAP_MCBSP policy<{'armhf': 'm'}> +CONFIG_SND_SOC_PCM1681 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM1754 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM1789 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM1789_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM179X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM179X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM179X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM186X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM186X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM186X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3060_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3060_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3168A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3168A_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3168A_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM5102A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM512x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM512x_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM512x_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM6240 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PEB2466 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PM4125 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PM4125_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QCOM_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QCOM_OFFLOAD_UTILS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QCOM_SDW policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_ADM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_AFE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_AFE_CLOCKS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_AFE_DAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_APM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_APM_DAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_ASM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_ASM_DAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_CORE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_PRM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_ROUTING policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RK3288_HDMI_ANALOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RK3308 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RK3328 policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_SND_SOC_RK3399_GRU_SOUND policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RK817 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RL6231 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RL6347A policy<{'amd64': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_I2S policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_MAX98090 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_PDM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_RT5645 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_SAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_SPDIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT1011 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT1015 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT1015P policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT1017_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT1019 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT1308 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT1308_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT1316_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT1318_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT1320_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT274 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT286 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT298 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT5514 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5514_SPI policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5575 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5575_SPI policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SOC_RT5616 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5631 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5645 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5651 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT5659 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5660 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT5663 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5670 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT5677 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5677_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5682 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5682S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5682_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5682_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT700 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT700_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT711_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT711_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT712_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT715 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT715_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT715_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT721_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT722_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT9120 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT9123 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT9123P policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RTQ9124 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RTQ9128 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT_SDW_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RZ policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SAMSUNG policy<{'armhf': 'n'}> +CONFIG_SND_SOC_SC7180 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SC7280 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SC8280XP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SDCA policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SDCA_CLASS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SDCA_CLASS_FUNCTION policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SDCA_FDL policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SDCA_HID policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SDCA_IRQ policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SDCA_OPTIONAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SDM845 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SDW_MOCKUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SDW_UTILS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SGTL5000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SH4_FSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SI476X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SIGMADSP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SIGMADSP_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SIGMADSP_REGMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SIMPLE_AMPLIFIER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SIMPLE_MUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SM8250 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SMA1303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SMA1307 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SOF policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SND_SOC_SOF_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SOF_ACPI_DEV policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_ACP_PROBES policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_ALDERLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_ACP63 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_ACP70 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_REMBRANDT policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_RENOIR policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE_LINK_BASELINE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_TOPLEVEL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_VANGOGH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_APOLLOLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_BAYTRAIL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_BROADWELL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_CANNONLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_CLIENT policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_COFFEELAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_COMETLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_COMPRESS policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_DEBUG_PROBES policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': '-'}> +CONFIG_SND_SOC_SOF_ELKHARTLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_GEMINILAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA_GENERIC policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA_MLINK policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA_PROBES policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_ICELAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_IMX8 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_IMX9 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_IMX_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_INTEL_APL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_CNL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_ICL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_LNL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_MTL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_NVL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_PTL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_SKL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_TGL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SOF_IPC3 policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_SND_SOC_SOF_IPC4 policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SOF_JASPERLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_KABYLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_LUNARLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_MERRIFIELD policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_METEORLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_MT8186 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_MT8195 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_MTK_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_MTK_TOPLEVEL policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_NOVALAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_OF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SOF_OF_DEV policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_PANTHERLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SOF_PCI_DEV policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SOF_SKYLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_TIGERLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_TOPLEVEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SOC_SOF_XTENSA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SND_SOC_SPDIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SPRD policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SPRD_MCDT policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SRC4XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SRC4XXX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM2305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM2518 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM2602 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM2602_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM2602_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM3515 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM4567 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_STA32X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_STA350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_STI_SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_STM32_DFSDM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STM32_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STM32_SAI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STM32_SPDIFRX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STORM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TAS2552 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2562 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2764 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2770 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2781_COMLIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2781_COMLIB_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2781_FMWLIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2781_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2783_SDW policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SND_SOC_TAS5086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS571X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS5720 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS5805M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS6424 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TDA7419 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA186_ASRC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA186_DSPK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA20_AC97 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA20_DAS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA20_I2S policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA20_SPDIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_ADMAIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_ADX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_AHUB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_AMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_DMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_I2S policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_MIXER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_MVC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_OPE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_SFC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA30_AHUB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA30_I2S policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_ALC5632 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_CPCAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_MACHINE_DRV policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_MAX98088 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_MAX98090 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_RT5631 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_RT5640 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_RT5677 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_SGTL5000 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_TRIMSLICE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_WM8753 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_WM8903 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_WM8962 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_WM9712 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TFA9879 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TFA989X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TI_EDMA_PCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TI_SDMA_PCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TI_UDMA_PCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TLV320ADC3XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320ADCX140 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC23 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC23_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC23_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC31XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC32X4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC32X4_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC32X4_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC3X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC3X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC3X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TOPOLOGY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_SND_SOC_TPA6130A2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TS3A227E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TSCS42XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TSCS454 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_UDA1334 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_UDA1342 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_UDA1380 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD9335 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD934X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD937X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD937X_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD938X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD938X_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD939X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD939X_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD_CLASSH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD_MBHC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM5102 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_WM8510 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8523 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8524 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8580 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8728 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8731 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8731_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8731_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8737 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8741 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8750 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8753 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8770 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8776 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8782 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8804 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8804_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8804_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8903 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8904 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8940 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8960 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8961 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8962 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8974 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8978 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8985 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8994 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_WM8998 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM9712 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_WM_ADSP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM_HUBS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_WSA881X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WSA883X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WSA884X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_X1E80100 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_XILINX_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_XILINX_SPDIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_XTFPGA_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ZL38060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOF_SOF_HDA_SDW_BPT policy<{'amd64': 'm'}> +CONFIG_SND_SONICVIBES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM policy<{'amd64': 'm'}> +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI policy<{'amd64': 'm'}> +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI policy<{'amd64': 'm'}> +CONFIG_SND_SUN4I_CODEC policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SND_SUN4I_I2S policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SND_SUN4I_SPDIF policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SND_SUN50I_CODEC_ANALOG policy<{'arm64': 'm'}> +CONFIG_SND_SUN50I_DMIC policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SND_SUN8I_ADDA_PR_REGMAP policy<{'arm64': 'm'}> +CONFIG_SND_SUN8I_CODEC policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SND_SUN8I_CODEC_ANALOG policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SND_SUPPORT_OLD_API policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SYNTH_EMUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_TEST_COMPONENT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_TIMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_TRIDENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_UMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_UMP_LEGACY_RAWMIDI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_USB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_USB_6FIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_AUDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_AUDIO_MIDI_V2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_USB_AUDIO_QMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_USB_CAIAQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_CAIAQ_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_USB_HIFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_LINE6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_POD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_PODHD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_TONEPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_UA101 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_US122L policy<{'amd64': 'm'}> +CONFIG_SND_USB_US144MKII policy<{'amd64': 'm'}> +CONFIG_SND_USB_USX2Y policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_SND_USB_VARIAX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_UTIMER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_VERBOSE_PROCFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_VIA82XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VIA82XX_MODEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VIRMIDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VIRTUOSO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VMASTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_VX222 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VXPOCKET policy<{'amd64': 'm'}> +CONFIG_SND_VX_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_X86 policy<{'amd64': 'y'}> +CONFIG_SND_XEN_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_SND_YMFPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SNET_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SNI_NETSEC policy<{'arm64': 'm'}> +CONFIG_SOCFPGA_FPGA_BRIDGE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SOCFPGA_SUSPEND policy<{'armhf': 'y'}> +CONFIG_SOCIONEXT_SYNQUACER_PREITS policy<{'arm64': 'y'}> +CONFIG_SOCK_CGROUP_DATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SOCK_RX_QUEUE_MAPPING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SOCK_VALIDATE_XMIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SOC_AM33XX policy<{'armhf': 'n'}> +CONFIG_SOC_AM43XX policy<{'armhf': 'n'}> +CONFIG_SOC_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SOC_DRA7XX policy<{'armhf': 'y'}> +CONFIG_SOC_HAS_OMAP2_SDRC policy<{'armhf': 'y'}> +CONFIG_SOC_HAS_REALTIME_COUNTER policy<{'armhf': 'y'}> +CONFIG_SOC_IMX5 policy<{'armhf': 'y'}> +CONFIG_SOC_IMX50 policy<{'armhf': 'y'}> +CONFIG_SOC_IMX51 policy<{'armhf': 'y'}> +CONFIG_SOC_IMX53 policy<{'armhf': 'n'}> +CONFIG_SOC_IMX6 policy<{'armhf': 'y'}> +CONFIG_SOC_IMX6Q policy<{'armhf': 'y'}> +CONFIG_SOC_IMX6SL policy<{'armhf': 'y'}> +CONFIG_SOC_IMX6SLL policy<{'armhf': 'y'}> +CONFIG_SOC_IMX6SX policy<{'armhf': 'y'}> +CONFIG_SOC_IMX6UL policy<{'armhf': 'y'}> +CONFIG_SOC_IMX7D policy<{'armhf': 'y'}> +CONFIG_SOC_IMX7D_CA7 policy<{'armhf': 'y'}> +CONFIG_SOC_IMX7ULP policy<{'armhf': 'y'}> +CONFIG_SOC_IMX8M policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_SOC_IMX9 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SOC_LS1021A policy<{'armhf': 'n'}> +CONFIG_SOC_OMAP5 policy<{'armhf': 'n'}> +CONFIG_SOC_RENESAS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SOC_SAMSUNG policy<{'armhf': 'y'}> +CONFIG_SOC_SP7021 policy<{'armhf': 'y'}> +CONFIG_SOC_STARFIVE policy<{'riscv64': 'n'}> +CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER policy<{'armhf': 'y'}> +CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER policy<{'armhf': 'y'}> +CONFIG_SOC_TEGRA_CBB policy<{'arm64': 'm'}> +CONFIG_SOC_TEGRA_FLOWCTRL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SOC_TEGRA_FUSE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SOC_TEGRA_PMC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SOC_TEGRA_POWERGATE_BPMP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SOC_TI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SOC_VF610 policy<{'armhf': 'y'}> +CONFIG_SOFTIRQ_ON_OWN_STACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SOFTLOCKUP_DETECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SOFT_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SOFT_WATCHDOG_PRETIMEOUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SOLARIS_X86_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SONYPI_COMPAT policy<{'amd64': 'y'}> +CONFIG_SONY_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SONY_LAPTOP policy<{'amd64': 'm'}> +CONFIG_SOPHGO_CV1800B_ADC policy<{'arm64': 'n', 'riscv64': '-'}> +CONFIG_SOPHGO_CV1800B_DMAMUX policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SOPHGO_CV1800_RTCSYS policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SOPHGO_SG2042_MSI policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_SOPHGO_SG2044_TOPSYS policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SOUNDWIRE_AMD policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SOUNDWIRE_CADENCE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SOUNDWIRE_GENERIC_ALLOCATION policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SOUNDWIRE_INTEL policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SOUNDWIRE_QCOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SOUND_OSS_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SP5100_TCO policy<{'amd64': 'm'}> +CONFIG_SP7021_EMAC policy<{'armhf': 'm'}> +CONFIG_SPAPR_TCE_IOMMU policy<{'ppc64el': 'y'}> +CONFIG_SPARSEMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPARSEMEM_EXTREME policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPARSEMEM_MANUAL policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPARSEMEM_STATIC policy<{'armhf': 'y'}> +CONFIG_SPARSEMEM_VMEMMAP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPARSEMEM_VMEMMAP_ENABLE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPARSEMEM_VMEMMAP_PREINIT policy<{'amd64': 'y'}> +CONFIG_SPARSE_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPARX5_DCB policy<{'arm64': 'y'}> +CONFIG_SPARX5_SWITCH policy<{'amd64': '-', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-'}> +CONFIG_SPEAKUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_ACNTSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_APOLLO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_AUDPTR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_BNS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_DECEXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_DECTLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_LTLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_SOFT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_SPKOUT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_TXPRT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SPI_AIROHA_SNFI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_ALTERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_ALTERA_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_ALTERA_DFL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_AMD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_AMLOGIC_SPIFC_A1 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_AMLOGIC_SPIFC_A4 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_AMLOGIC_SPISG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_APPLE policy<{'arm64': 'm'}> +CONFIG_SPI_ARMADA_3700 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_ASPEED_SMC policy<{'armhf': 'm'}> +CONFIG_SPI_ATMEL policy<{'arm64': 'm'}> +CONFIG_SPI_AX88796C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_AX88796C_COMPRESSION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SPI_AXIADO policy<{'arm64': 'm'}> +CONFIG_SPI_AXI_SPI_ENGINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_BITBANG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_BUTTERFLY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_CADENCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_CADENCE_QUADSPI policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_SPI_CADENCE_XSPI policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_CH341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_CS42L43 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SPI_DESIGNWARE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_DLN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_DW_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_DW_MMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_DW_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_DYNAMIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_FSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_FSL_DSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_FSL_LIB policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_FSL_LPSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_FSL_QUADSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_FSL_SPI policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_GXP policy<{'armhf': 'm'}> +CONFIG_SPI_HISI_KUNPENG policy<{'arm64': 'm'}> +CONFIG_SPI_HISI_SFC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_HISI_SFC_V3XX policy<{'arm64': 'm'}> +CONFIG_SPI_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_INTEL policy<{'amd64': 'm'}> +CONFIG_SPI_INTEL_PCI policy<{'amd64': 'm'}> +CONFIG_SPI_INTEL_PLATFORM policy<{'amd64': 'm'}> +CONFIG_SPI_KSPI2 policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SPI_LANTIQ_SSC policy<{'amd64': 'm'}> +CONFIG_SPI_LJCA policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SPI_LM70_LLP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_LOOPBACK_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_MASTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_MEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_MESON_SPICC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_MESON_SPIFC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_MICROCHIP_CORE_QSPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_MICROCHIP_CORE_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_MT65XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_MTK_NOR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_MTK_SNFI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_MUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_MXIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_NPCM_FIU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_NPCM_PSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_NXP_FLEXSPI policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_SPI_NXP_XSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_OC_TINY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_OFFLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_OFFLOAD_TRIGGER_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_OMAP24XX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SPI_ORION policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_PCI1XXXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_PL022 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_SPI_POLARFIRE_SOC policy<{'arm64': 'm'}> +CONFIG_SPI_PXA2XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_SPI_PXA2XX_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_SPI_QCOM_GENI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_QCOM_QSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_QPIC_SNAND policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_QUP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_ROCKCHIP policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_SPI_ROCKCHIP_SFC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_RPCIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_RSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_RZV2H_RSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_RZV2M_CSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_S3C64XX policy<{'armhf': 'n'}> +CONFIG_SPI_SC18IS602 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_SG2044_NOR policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SPI_SH_HSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_SH_MSIOF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_SIFIVE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_SLAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_SLAVE_MT27XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_SLAVE_SYSTEM_CONTROL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_SLAVE_TIME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_SN_F_OSPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_SPIDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_SPRD policy<{'arm64': 'm'}> +CONFIG_SPI_SPRD_ADI policy<{'arm64': 'm'}> +CONFIG_SPI_STM32 policy<{'arm64': 'm'}> +CONFIG_SPI_STM32_OSPI policy<{'arm64': 'm'}> +CONFIG_SPI_STM32_QSPI policy<{'arm64': 'm'}> +CONFIG_SPI_SUN4I policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SPI_SUN6I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SPI_SUNPLUS_SP7021 policy<{'armhf': 'm'}> +CONFIG_SPI_SYNQUACER policy<{'arm64': 'm'}> +CONFIG_SPI_TEGRA114 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_TEGRA20_SFLASH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_TEGRA20_SLINK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_TEGRA210_QUAD policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_SPI_THUNDERX policy<{'arm64': 'm'}> +CONFIG_SPI_TI_QSPI policy<{'armhf': 'm'}> +CONFIG_SPI_TLE62X0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_WPCM_FIU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_XCOMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_XILINX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_XLP policy<{'arm64': 'm'}> +CONFIG_SPI_ZYNQMP_GQSPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPLIT_PMD_PTLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPLIT_PTE_PTLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SPMI_APPLE policy<{'arm64': 'm'}> +CONFIG_SPMI_HISI3670 policy<{'amd64': '-', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_SPMI_MSM_PMIC_ARB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPMI_MTK_PMIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPMI_PMIC_CLKDIV policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPRD_COMMON_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_DMA policy<{'arm64': 'm'}> +CONFIG_SPRD_IOMMU policy<{'arm64': 'm'}> +CONFIG_SPRD_MBOX policy<{'arm64': 'm'}> +CONFIG_SPRD_SC9860_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_SC9863A_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_THERMAL policy<{'arm64': 'm'}> +CONFIG_SPRD_TIMER policy<{'arm64': 'y'}> +CONFIG_SPRD_UMS512_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_SPS30 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPS30_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPS30_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_COMP_CACHE_FULL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SQUASHFS_DECOMP_MULTI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_DECOMP_SINGLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_EMBEDDED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SQUASHFS_FILE_CACHE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SQUASHFS_FILE_DIRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE policy<{'amd64': '3', 'arm64': '3', 'armhf': '3', 'ppc64el': '3', 'riscv64': '3', 's390x': '3'}> +CONFIG_SQUASHFS_LZ4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_MOUNT_DECOMP_THREADS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_XZ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_ZLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SRAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SRAM_EXEC policy<{'armhf': 'y'}> +CONFIG_SRF04 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SRF08 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SSB_B43_PCI_BRIDGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_BLOCKIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_DRIVER_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_SSB_DRIVER_PCICORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_PCIHOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_SSB_PCIHOST_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_PCMCIAHOST policy<{'amd64': 'n'}> +CONFIG_SSB_PCMCIAHOST_POSSIBLE policy<{'amd64': 'y'}> +CONFIG_SSB_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SSB_SDIOHOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_SDIOHOST_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_SPROM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSFDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SSIF_IPMI_BMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STACKDEPOT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STACKDEPOT_MAX_FRAMES policy<{'amd64': '64', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64', 's390x': '64'}> +CONFIG_STACKPROTECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STACKPROTECTOR_PER_TASK policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_STACKPROTECTOR_STRONG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STACKTRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STACKTRACE_BUILD_ID policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_STACKTRACE_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STACK_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STAGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_STAGING_MEDIA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STAGING_MEDIA_DEPRECATED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_STANDALONE policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STATIC_CALL_SELFTEST policy<{'amd64': 'n'}> +CONFIG_STATIC_KEYS_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_STATIC_USERMODEHELPER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_STE10XP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STEAM_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STK3310 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STK8312 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STK8BA50 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM32MP_EXTI policy<{'arm64': 'm'}> +CONFIG_STM32_ADC policy<{'arm64': 'm'}> +CONFIG_STM32_ADC_CORE policy<{'arm64': 'm'}> +CONFIG_STM32_DAC policy<{'arm64': 'm'}> +CONFIG_STM32_DAC_CORE policy<{'arm64': 'm'}> +CONFIG_STM32_DBG_BUS policy<{'arm64': 'm'}> +CONFIG_STM32_DFSDM_ADC policy<{'arm64': 'm'}> +CONFIG_STM32_DFSDM_CORE policy<{'arm64': 'm'}> +CONFIG_STM32_DMA policy<{'arm64': 'y'}> +CONFIG_STM32_DMA3 policy<{'arm64': 'm'}> +CONFIG_STM32_DMAMUX policy<{'arm64': 'y'}> +CONFIG_STM32_FIREWALL policy<{'arm64': 'y'}> +CONFIG_STM32_FMC2_EBI policy<{'arm64': 'm'}> +CONFIG_STM32_LPTIMER_CNT policy<{'arm64': 'm'}> +CONFIG_STM32_MDMA policy<{'arm64': 'y'}> +CONFIG_STM32_OMM policy<{'arm64': 'm'}> +CONFIG_STM32_RPROC policy<{'arm64': 'm'}> +CONFIG_STM32_TIMER_CNT policy<{'arm64': 'm'}> +CONFIG_STM32_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_STMMAC_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_STMMAC_LIBPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STMMAC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STMMAC_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STMMAC_SELFTESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_STMPE_ADC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STMPE_I2C policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STMPE_SPI policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STMP_DEVICE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_STM_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM_PROTO_BASIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM_PROTO_SYS_T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM_SOURCE_CONSOLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM_SOURCE_FTRACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM_SOURCE_HEARTBEAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STPMIC1_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STREAM_PARSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STRICT_DEVMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STRICT_KERNEL_RWX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STRICT_MM_TYPECHECKS policy<{'s390x': 'y'}> +CONFIG_STRICT_MODULE_RWX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STRICT_SIGALTSTACK_SIZE policy<{'amd64': 'n'}> +CONFIG_STRIP_ASM_SYMS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_STUB_CLK_HI3660 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_STUB_CLK_HI6220 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_STX104 policy<{'amd64': 'm'}> +CONFIG_ST_THERMAL policy<{'arm64': 'm'}> +CONFIG_ST_THERMAL_MEMMAP policy<{'arm64': 'm'}> +CONFIG_ST_UVIS25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ST_UVIS25_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ST_UVIS25_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SUN20I_GPADC policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SUN20I_PPU policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_SUN4I_EMAC policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN4I_GPADC policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN4I_TIMER policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN50I_A100_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_A100_R_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_A64_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_DE2_BUS policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN50I_ERRATUM_UNKNOWN1 policy<{'arm64': 'y'}> +CONFIG_SUN50I_H616_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_H6_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_H6_PRCM_PPU policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SUN50I_H6_R_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_IOMMU policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN55I_A523_CCU policy<{'arm64': 'y'}> +CONFIG_SUN55I_A523_MCU_CCU policy<{'arm64': 'm'}> +CONFIG_SUN55I_A523_R_CCU policy<{'arm64': 'y'}> +CONFIG_SUN55I_PCK600 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SUN6I_MSGBOX policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN6I_RTC_CCU policy<{'arm64': 'm'}> +CONFIG_SUN6I_R_INTC policy<{'arm64': 'y'}> +CONFIG_SUN8I_DE2_CCU policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN8I_H3_CCU policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SUN8I_R_CCU policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SUN8I_THERMAL policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUNDANCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SUNDANCE_MMIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SUNGEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SUNGEM_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SUNPLUS_SP7021_INTC policy<{'armhf': 'y'}> +CONFIG_SUNPLUS_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_SUNRPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SUNRPC_BACKCHANNEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SUNRPC_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SUNRPC_DEBUG_TRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SUNRPC_GSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SUNRPC_SWAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SUNRPC_XPRT_RDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SUNXI_CCU policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUNXI_MBUS policy<{'arm64': 'y'}> +CONFIG_SUNXI_NMI_INTC policy<{'arm64': 'y'}> +CONFIG_SUNXI_RSB policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUNXI_SRAM policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_SUNXI_WATCHDOG policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SURFACE3_WMI policy<{'amd64': 'm'}> +CONFIG_SURFACE_3_POWER_OPREGION policy<{'amd64': 'm', 'arm64': 'n'}> +CONFIG_SURFACE_ACPI_NOTIFY policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_BUS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_SURFACE_AGGREGATOR_CDEV policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_SURFACE_AGGREGATOR_HUB policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_REGISTRY policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_DTX policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_GPE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_HID policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_HID_CORE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_HOTPLUG policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_KBD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_PLATFORMS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_SURFACE_PLATFORM_PROFILE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_PRO3_BUTTON policy<{'amd64': 'm', 'arm64': 'n'}> +CONFIG_SUSPEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SUSPEND_FREEZER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SUSPEND_SKIP_SYNC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SVC_I3C_MASTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SWAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SWIOTLB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SWIOTLB_DYNAMIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SWIOTLB_XEN policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_SWITCHTEC_DMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SWPHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SWP_EMULATE policy<{'armhf': 'y'}> +CONFIG_SW_SYNC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SX9310 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SX9324 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SX9360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SX9500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SXGBE_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SX_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SYMBOLIC_ERRNAME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYNC_FILE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYNTH_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYNTH_EVENT_GEN_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SYN_COOKIES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSCON_REBOOT_MODE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SYSCTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW policy<{'riscv64': 'y'}> +CONFIG_SYSCTL_EXCEPTION_TRACE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSC_R8A7742 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7743 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7745 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A77470 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A7779 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7790 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7791 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7792 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7794 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7795 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77960 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77961 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77965 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77970 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77980 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77990 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77995 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R9A08G045 policy<{'arm64': 'y'}> +CONFIG_SYSC_R9A08G046 policy<{'arm64': 'y'}> +CONFIG_SYSC_RCAR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SYSC_RCAR_GEN4 policy<{'arm64': 'y'}> +CONFIG_SYSC_RMOBILE policy<{'armhf': 'y'}> +CONFIG_SYSC_RZ policy<{'arm64': 'y'}> +CONFIG_SYSFB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSFS_SYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM76_ACPI policy<{'amd64': 'm'}> +CONFIG_SYSTEMPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SYSTEM_BLACKLIST_HASH_LIST policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_SYSTEM_BLACKLIST_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM_DATA_VERIFICATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM_EXTRA_CERTIFICATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE policy<{'amd64': '4096', 'arm64': '4096', 'armhf': '4096', 'ppc64el': '4096', 'riscv64': '4096', 's390x': '4096'}> +CONFIG_SYSTEM_REVOCATION_KEYS policy<{'amd64': '"debian/canonical-revoked-certs.pem"', 'arm64': '"debian/canonical-revoked-certs.pem"', 'armhf': '"debian/canonical-revoked-certs.pem"', 'ppc64el': '"debian/canonical-revoked-certs.pem"', 'riscv64': '"debian/canonical-revoked-certs.pem"', 's390x': '"debian/canonical-revoked-certs.pem"'}> +CONFIG_SYSTEM_REVOCATION_LIST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM_TRUSTED_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM_TRUSTED_KEYS policy<{'amd64': '"debian/canonical-certs.pem"', 'arm64': '"debian/canonical-certs.pem"', 'armhf': '"debian/canonical-certs.pem"', 'ppc64el': '"debian/canonical-certs.pem"', 'riscv64': '"debian/canonical-certs.pem"', 's390x': '"debian/canonical-certs.pem"'}> +CONFIG_SYSV68_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SYSVIPC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSVIPC_COMPAT policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 's390x': '-'}> +CONFIG_SYSVIPC_SYSCTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYS_HYPERVISOR policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_SYS_R9A09G047 policy<{'arm64': 'y'}> +CONFIG_SYS_R9A09G056 policy<{'arm64': 'y'}> +CONFIG_SYS_R9A09G057 policy<{'arm64': 'y'}> +CONFIG_SYS_SUPPORTS_APM_EMULATION policy<{'armhf': 'y'}> +CONFIG_SYS_SUPPORTS_EM_STI policy<{'armhf': 'y'}> +CONFIG_SYS_SUPPORTS_SH_CMT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SYS_SUPPORTS_SH_MTU2 policy<{'armhf': 'y'}> +CONFIG_SYS_SUPPORTS_SH_TMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_T5403 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TABLET_SERIAL_WACOM4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TABLET_USB_ACECAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TABLET_USB_AIPTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TABLET_USB_HANWANG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TABLET_USB_KBTAB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TABLET_USB_PEGASUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TAHVO_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TAHVO_USB_HOST_BY_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TARGET_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TARGET_CPU policy<{'ppc64el': '"power8"'}> +CONFIG_TARGET_CPU_BOOL policy<{'ppc64el': 'y'}> +CONFIG_TASKSTATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASKS_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASKS_RCU_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASKS_RUDE_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASKS_TRACE_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASK_DELAY_ACCT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASK_IO_ACCOUNTING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASK_XACCT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCG_ARM_CRB_FFA policy<{'arm64': 'm'}> +CONFIG_TCG_ATMEL policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TCG_CRB policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_TCG_FTPM_TEE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TCG_IBMVTPM policy<{'ppc64el': 'y'}> +CONFIG_TCG_INFINEON policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_TCG_NSC policy<{'amd64': 'm'}> +CONFIG_TCG_SVSM policy<{'amd64': 'm'}> +CONFIG_TCG_TIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TCG_TIS_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TCG_TIS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_I2C_CR50 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_SPI policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TCG_TIS_SPI_CR50 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TCG_TIS_ST33ZP24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TCG_TIS_ST33ZP24_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_ST33ZP24_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TCG_TIS_SYNQUACER policy<{'arm64': 'm'}> +CONFIG_TCG_TPM2_HMAC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TCG_VTPM_PROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCG_XEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_TCM_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCM_FILEIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCM_IBLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCM_PSCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCM_QLA2XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TCM_QLA2XXX_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_TCM_USER2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_AO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCP_CONG_ADVANCED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCP_CONG_BBR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_BIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_CDG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_CUBIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCP_CONG_DCTCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_HSTCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_HTCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_HYBLA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_ILLINOIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_LP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_NV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_SCALABLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_VEGAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_VENO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_WESTWOOD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_YEAH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_MD5SIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCP_SIGPOOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCS3414 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TCS3472 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TDX_GUEST_DRIVER policy<{'amd64': 'm'}> +CONFIG_TEE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEE_DMABUF_HEAPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEE_STMM_EFI policy<{'arm64-generic': 'n', 'arm64-generic-64k': 'm', 'armhf': 'm'}> +CONFIG_TEGRA124_CLK_EMC policy<{'armhf': 'y'}> +CONFIG_TEGRA124_EMC policy<{'armhf': 'y'}> +CONFIG_TEGRA186_GPC_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEGRA186_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA20_APB_DMA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA20_EMC policy<{'armhf': 'y'}> +CONFIG_TEGRA210_ADMA policy<{'arm64': 'm', 'armhf': 'n'}> +CONFIG_TEGRA210_EMC policy<{'arm64': 'm'}> +CONFIG_TEGRA210_EMC_TABLE policy<{'arm64': 'y'}> +CONFIG_TEGRA241_CMDQV policy<{'arm64': 'y'}> +CONFIG_TEGRA30_EMC policy<{'armhf': 'y'}> +CONFIG_TEGRA30_TSENSOR policy<{'armhf': 'm'}> +CONFIG_TEGRA_ACONNECT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEGRA_AHB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_BPMP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_BPMP_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEGRA_CLK_DFLL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_GMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEGRA_HOST1X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEGRA_HOST1X_CONTEXT_BUS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_HOST1X_FIREWALL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_HSP_MBOX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_IOMMU_SMMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_IVC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_MC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_SOCTHERM policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_TEGRA_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEHUTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TEHUTI_TN40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TELCLOCK policy<{'amd64': 'm'}> +CONFIG_TERANETICS_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TEST_ASYNC_DRIVER_PROBE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_BITMAP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_BITOPS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_BPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TEST_CLOCKSOURCE_WATCHDOG policy<{'amd64': 'n'}> +CONFIG_TEST_DHRY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_DIV64 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_DYNAMIC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_FIRMWARE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_FPU policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_TEST_FREE_PAGES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_HEXDUMP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_HMM policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_IDA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_KALLSYMS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_KEXEC_HANDOVER policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_TEST_KMOD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_KSTRTOX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_LKM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_LOCKUP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_MAPLE_TREE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_MEMCAT_P policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_MEMINIT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_MULDIV64 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_OBJAGG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_OBJPOOL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_PARMAN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TEST_REF_TRACKER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_RHASHTABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_STATIC_KEYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_SYSCTL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_UBSAN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_TEST_UDELAY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_VMALLOC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_WORKQUEUE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_XARRAY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEXTSEARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TEXTSEARCH_BM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TEXTSEARCH_FSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TEXTSEARCH_KMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_THERMAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_THERMAL_CORE_TESTING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_THERMAL_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_THERMAL_EMULATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_GOV_BANG_BANG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_GOV_FAIR_SHARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_GOV_POWER_ALLOCATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_GOV_STEP_WISE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_GOV_USER_SPACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_MMIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_THERMAL_NETLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_OF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_STATISTICS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THINKPAD_ACPI policy<{'amd64': 'm'}> +CONFIG_THINKPAD_ACPI_ALSA_SUPPORT policy<{'amd64': 'y'}> +CONFIG_THINKPAD_ACPI_DEBUG policy<{'amd64': 'n'}> +CONFIG_THINKPAD_ACPI_DEBUGFACILITIES policy<{'amd64': 'y'}> +CONFIG_THINKPAD_ACPI_HOTKEY_POLL policy<{'amd64': 'y'}> +CONFIG_THINKPAD_ACPI_UNSAFE_LEDS policy<{'amd64': 'n'}> +CONFIG_THINKPAD_ACPI_VIDEO policy<{'amd64': 'y'}> +CONFIG_THINKPAD_LMI policy<{'amd64': 'm'}> +CONFIG_THP_SWAP policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_THREAD_INFO_IN_TASK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_THREAD_SHIFT policy<{'ppc64el': '14'}> +CONFIG_THREAD_SIZE_ORDER policy<{'riscv64': '2'}> +CONFIG_THRUSTMASTER_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THUMB2_KERNEL policy<{'armhf': 'n'}> +CONFIG_THUNDERX2_PMU policy<{'arm64': 'm'}> +CONFIG_THUNDER_NIC_BGX policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_THUNDER_NIC_PF policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_THUNDER_NIC_RGX policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_THUNDER_NIC_VF policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TICK_CPU_ACCOUNTING policy<{'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_TICK_ONESHOT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIFM_7XX1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TIFM_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TIGON3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TIGON3_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TIMERFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIMER_ACPI policy<{'arm64': 'y'}> +CONFIG_TIMER_IMX_SYS_CTR policy<{'arm64': 'y'}> +CONFIG_TIMER_OF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_TIMER_PROBE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_TIME_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIME_NS_VDSO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TINYDRM_HX8357D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_ILI9163 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TINYDRM_ILI9225 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_ILI9341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_ILI9486 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_MI0283QT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_REPAPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_SHARP_MEMORY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TIPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TIPC_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIPC_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TIPC_MEDIA_IB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIPC_MEDIA_UDP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TI_ADC081C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC0832 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC084S021 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC108S102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC12138 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC128S052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC161S626 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS1015 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS1018 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS1100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS1119 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS124S08 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS1298 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS131E08 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS131M02 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS7138 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS7924 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS7950 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS8344 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS8688 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_AM335X_ADC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_TI_AM65_CPSW_QOS policy<{'arm64': 'y'}> +CONFIG_TI_CPPI41 policy<{'armhf': 'm'}> +CONFIG_TI_CPSW policy<{'armhf': 'y'}> +CONFIG_TI_CPSW_PHY_SEL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_TI_CPSW_SWITCHDEV policy<{'armhf': 'm'}> +CONFIG_TI_CPTS policy<{'armhf': 'y'}> +CONFIG_TI_DAC082S085 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_DAC5571 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_DAC7311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_DAC7612 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_DAVINCI_MDIO policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TI_DMA_CROSSBAR policy<{'armhf': 'y'}> +CONFIG_TI_ECAP_CAPTURE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TI_EDMA policy<{'armhf': 'y'}> +CONFIG_TI_EMIF policy<{'armhf': 'm'}> +CONFIG_TI_EQEP policy<{'arm64': 'm'}> +CONFIG_TI_FPC202 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TI_ICSSG_PRUETH policy<{'arm64': 'm'}> +CONFIG_TI_ICSSG_PRUETH_SR1 policy<{'arm64': 'm'}> +CONFIG_TI_ICSS_IEP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TI_K3_AM65_CPSW_NUSS policy<{'arm64': 'm'}> +CONFIG_TI_K3_AM65_CPSW_SWITCHDEV policy<{'arm64': 'y'}> +CONFIG_TI_K3_AM65_CPTS policy<{'arm64': 'm'}> +CONFIG_TI_K3_CPPI_DESC_POOL policy<{'arm64': 'm'}> +CONFIG_TI_K3_DSP_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_TI_K3_M4_REMOTEPROC policy<{'arm64': 'n', 'armhf': '-'}> +CONFIG_TI_K3_PSIL policy<{'arm64': 'y'}> +CONFIG_TI_K3_R5_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_TI_K3_RINGACC policy<{'arm64': 'y'}> +CONFIG_TI_K3_SOCINFO policy<{'arm64': 'y'}> +CONFIG_TI_K3_UDMA policy<{'arm64': 'y'}> +CONFIG_TI_K3_UDMA_GLUE_LAYER policy<{'arm64': 'y'}> +CONFIG_TI_LMP92064 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_MESSAGE_MANAGER policy<{'arm64': 'y'}> +CONFIG_TI_PIPE3 policy<{'armhf': 'm'}> +CONFIG_TI_PRUETH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TI_PRUSS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TI_PRUSS_INTC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TI_PWMSS policy<{'armhf': 'y'}> +CONFIG_TI_SCI_CLK policy<{'arm64': 'm'}> +CONFIG_TI_SCI_CLK_PROBE_FROM_FW policy<{'arm64': 'n'}> +CONFIG_TI_SCI_INTA_IRQCHIP policy<{'arm64': 'y'}> +CONFIG_TI_SCI_INTA_MSI_DOMAIN policy<{'arm64': 'y'}> +CONFIG_TI_SCI_INTR_IRQCHIP policy<{'arm64': 'y'}> +CONFIG_TI_SCI_PM_DOMAINS policy<{'arm64': 'm'}> +CONFIG_TI_SCI_PROTOCOL policy<{'arm64': 'y'}> +CONFIG_TI_SOC_THERMAL policy<{'arm64': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_TI_SYSC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TI_SYSCON_CLK policy<{'arm64': 'y'}> +CONFIG_TI_TLC4541 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_TMAG5273 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_TSC2046 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TLS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TLS_DEVICE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TLS_TOE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TMP006 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TMP007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TMP117 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TMPFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TMPFS_INODE64 policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TMPFS_QUOTA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TMPFS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TN3215 policy<{'s390x': 'y'}> +CONFIG_TN3215_CONSOLE policy<{'s390x': 'y'}> +CONFIG_TN3270 policy<{'s390x': 'y'}> +CONFIG_TN3270_CONSOLE policy<{'s390x': 'y'}> +CONFIG_TN3270_FS policy<{'s390x': 'm'}> +CONFIG_TOOLCHAIN_DEFAULT_CPU policy<{'ppc64el': 'n'}> +CONFIG_TOOLCHAIN_HAS_V policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_VECTOR_CRYPTO policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZABHA policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZACAS policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZBA policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZBB policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZBC policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZBKB policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI policy<{'riscv64': 'y'}> +CONFIG_TOOLS_SUPPORT_RELR policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_TOPSTAR_LAPTOP policy<{'amd64': 'm'}> +CONFIG_TOSHIBA_BT_RFKILL policy<{'amd64': 'm'}> +CONFIG_TOSHIBA_HAPS policy<{'amd64': 'm'}> +CONFIG_TOSHIBA_WMI policy<{'amd64': 'n'}> +CONFIG_TOUCHSCREEN_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_AD7877 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_AD7879 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_AD7879_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_AD7879_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_ADS7846 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_AR1021_I2C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_ATMEL_MXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_AUO_PIXCIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_BU21013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_BU21029 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_COLIBRI_VF50 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_CY8CTMA140 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_CY8CTMG110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_CYTTSP5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_CYTTSP_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_CYTTSP_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_CYTTSP_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_DA9034 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_DMI policy<{'amd64': 'y'}> +CONFIG_TOUCHSCREEN_DYNAPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_EDT_FT5X06 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_EETI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_EGALAX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_EGALAX_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_EKTF2127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ELO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_EXC3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_FUJITSU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_GOODIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_GUNZE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_HAMPSHIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_HIDEEP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_HIMAX_HX83112B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_HIMAX_HX852X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_HYCON_HY46XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_HYNITRON_CST816X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_ILI210X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ILITEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_IMAGIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_IMX6UL_TSC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_INEXIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_IQS5XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_IQS7211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_MAX11801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_MC13783 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_MELFAS_MIP4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_MMS114 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_MSG2638 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_MTOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_PCAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_PENMOUNT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_PIXCIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_RM_TS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ROHM_BU21023 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_S6SY761 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_SILEAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_SIS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ST1232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_STMFTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_STMPE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_SUN4I policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_TOUCHSCREEN_SUR40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_SURFACE3_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_SX8654 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TI_AM335X_TSC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_TOUCHSCREEN_TOUCHIT213 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TOUCHRIGHT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TOUCHWIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TPS6507X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TS4800 policy<{'armhf': 'm'}> +CONFIG_TOUCHSCREEN_TSC2004 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TSC2005 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TSC2007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TSC2007_IIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_TSC200X_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_TSC_SERIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_USB_3M policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_COMPOSITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_USB_DMC_TSC10 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_E2I policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_EASYTOUCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_EGALAX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ELO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ETURBO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_GOTOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_GUNZE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_IDEALTEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_IRTOUCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ITM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_JASTEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_NEXIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_PANJIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ZYTRONIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_WACOM_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_WACOM_W8001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_WDT87XX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_WM9705 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_WM9712 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_WM9713 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_WM97XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_ZET6223 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ZFORCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ZINITIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TPL0102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TPS6105X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TPS65010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TPS6507X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TPS6594_ESM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TPS6594_PFSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TPS68470_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_TQMX86_WDT policy<{'amd64': 'm'}> +CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACEPOINTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACEPOINT_BENCHMARK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRACER_MAX_TRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACER_SNAPSHOT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRACE_CLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACE_EVAL_MAP_FILE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRACE_EVENT_INJECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACE_GPU_MEM policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_TRACE_IRQFLAGS_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACE_MMIO_ACCESS policy<{'arm64': 'y', 's390x': 'y'}> +CONFIG_TRACE_REMOTE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACE_REMOTE_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TRACE_SYSCALL_BUF_SIZE_DEFAULT policy<{'amd64': '63', 'arm64': '63', 'armhf': '63', 'ppc64el': '63', 'riscv64': '63', 's390x': '63'}> +CONFIG_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACING_MAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACING_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_NEVER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_ADVISE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_ALWAYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_NEVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_WITHIN_SIZE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_ADVISE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_ALWAYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_NEVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_WITHIN_SIZE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANS_TABLE policy<{'arm64': 'y'}> +CONFIG_TREE_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TREE_SRCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRIM_UNUSED_KSYMS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRUSTED_FOUNDATIONS policy<{'armhf': 'y'}> +CONFIG_TRUSTED_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRUSTED_KEYS_PKWM policy<{'ppc64el': 'y'}> +CONFIG_TRUSTED_KEYS_TPM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TS4800_IRQ policy<{'armhf': 'm'}> +CONFIG_TS4800_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_TSL2583 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TSL2591 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TSL2772 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TSL4531 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TSM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TSM_GUEST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TSM_MEASUREMENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TSM_REPORTS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_TSNEP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TSNEP_SELFTESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TSYS01 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TSYS02D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TTPCI_EEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TTY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TTY_PRINTK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_TTY_PRINTK_LEVEL policy<{'amd64': '6', 'arm64': '6', 'armhf': '6', 'ppc64el': '6', 'riscv64': '6'}> +CONFIG_TULIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TULIP_MMIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_TULIP_MWI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_TULIP_NAPI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_TUN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TUNE_CPU policy<{'ppc64el': '"-mtune=power10"'}> +CONFIG_TUNE_DEFAULT policy<{'s390x': 'n'}> +CONFIG_TUNE_GENERIC policy<{'riscv64': 'y'}> +CONFIG_TUNE_Z10 policy<{'s390x': 'n'}> +CONFIG_TUNE_Z13 policy<{'s390x': 'n'}> +CONFIG_TUNE_Z14 policy<{'s390x': 'n'}> +CONFIG_TUNE_Z15 policy<{'s390x': 'n'}> +CONFIG_TUNE_Z17 policy<{'s390x': 'n'}> +CONFIG_TUNE_Z196 policy<{'s390x': 'n'}> +CONFIG_TUNE_ZEC12 policy<{'s390x': 'n'}> +CONFIG_TUN_VNET_CROSS_LE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TURRIS_MOX_RWTM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TURRIS_MOX_RWTM_KEYCTL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TURRIS_OMNIA_MCU policy<{'armhf': 'm'}> +CONFIG_TURRIS_OMNIA_MCU_GPIO policy<{'armhf': 'y'}> +CONFIG_TURRIS_OMNIA_MCU_KEYCTL policy<{'armhf': 'y'}> +CONFIG_TURRIS_OMNIA_MCU_SYSOFF_WAKEUP policy<{'armhf': 'y'}> +CONFIG_TURRIS_OMNIA_MCU_TRNG policy<{'armhf': 'y'}> +CONFIG_TURRIS_OMNIA_MCU_WATCHDOG policy<{'armhf': 'y'}> +CONFIG_TURRIS_SIGNING_KEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TUXEDO_NB04_WMI_AB policy<{'amd64': 'm'}> +CONFIG_TWL4030_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_TWL4030_MADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TWL4030_POWER policy<{'armhf': 'y'}> +CONFIG_TWL4030_USB policy<{'armhf': 'm'}> +CONFIG_TWL4030_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TWL6030_GPADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TWL6030_USB policy<{'armhf': 'm'}> +CONFIG_TWL6040_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_TXGBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TXGBEVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TYPEC_ANX7411 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_DP_ALTMODE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_FUSB302 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_HD3SS3220 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MT6360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_FSA4480 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_GPIO_SBU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_INTEL_PMC policy<{'amd64': 'm'}> +CONFIG_TYPEC_MUX_IT5205 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_NB7VPQ904M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_PI3USB30532 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_PS883X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_PTN36502 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_TUSB1046 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_WCD939X_USBSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_NVIDIA_ALTMODE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_QCOM_PMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TYPEC_RT1711H policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_RT1719 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_STUSB160X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TBT_ALTMODE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TCPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TCPCI_MAXIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TCPCI_MT6370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TCPM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TPS6598X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_UCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_WCOVE policy<{'amd64': 'm'}> +CONFIG_TYPEC_WUSB3801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPHOON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_UACCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UACCESS_WITH_MEMCPY policy<{'armhf': 'n'}> +CONFIG_UBIFS_ATIME_SUPPORT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_UBIFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UBIFS_FS_ADVANCED_COMPR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_UBIFS_FS_AUTHENTICATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBIFS_FS_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBIFS_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBIFS_FS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBIFS_FS_ZLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBIFS_FS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBSAN_ALIGNMENT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_UBSAN_BOOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_UBSAN_BOUNDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_UBSAN_BOUNDS_STRICT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_UBSAN_DIV_ZERO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_UBSAN_ENUM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_UBSAN_KVM_EL2 policy<{'arm64': 'n'}> +CONFIG_UBSAN_SHIFT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_UBSAN_TRAP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_UBSAN_UNREACHABLE policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_UCC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_UCC_FAST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_UCC_SLOW policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_UCLAMP_BUCKETS_COUNT policy<{'amd64': '5', 'arm64': '5', 'armhf': '5', 'ppc64el': '5', 'riscv64': '5'}> +CONFIG_UCLAMP_TASK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UCLAMP_TASK_GROUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UCS2_STRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_UCSI_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_UCSI_CCG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UCSI_HUAWEI_GAOKUN policy<{'arm64': 'm'}> +CONFIG_UCSI_LENOVO_YOGA_C630 policy<{'arm64-generic': 'm'}> +CONFIG_UCSI_PMIC_GLINK policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UCSI_STM32G0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UDF_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_UDMABUF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UEFI_CPER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_UEFI_CPER_ARM policy<{'arm64': 'y'}> +CONFIG_UEFI_CPER_X86 policy<{'amd64': 'y'}> +CONFIG_UEVENT_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UEVENT_HELPER_PATH policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_UFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_UFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UFS_FS_WRITE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_UHID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_UID16 policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 's390x': '-'}> +CONFIG_UIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_UIO_AEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_CIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_DFL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UIO_DMEM_GENIRQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_FSL_ELBC_GPCM policy<{'ppc64el': 'm'}> +CONFIG_UIO_FSL_ELBC_GPCM_NETX5152 policy<{'ppc64el': 'n'}> +CONFIG_UIO_HV_GENERIC policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_UIO_MF624 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_NETX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_PCI_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_PCI_GENERIC_SVA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_UIO_PDRV_GENIRQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_SERCOS3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ULI526X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ULTRIX_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_UNACCEPTED_MEMORY policy<{'amd64': 'y'}> +CONFIG_UNCOMPRESS_INCLUDE policy<{'armhf': '"debug/uncompress.h"'}> +CONFIG_UNICODE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UNINLINE_SPIN_UNLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UNION_FIND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UNIWILL_LAPTOP policy<{'amd64': 'm'}> +CONFIG_UNIX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UNIX98_PTYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UNIXWARE_DISKLABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_UNIX_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_UNMAP_KERNEL_AT_EL0 policy<{'arm64': 'y'}> +CONFIG_UNWINDER_ARM policy<{'armhf': 'n'}> +CONFIG_UNWINDER_ORC policy<{'amd64': 'n'}> +CONFIG_UNWIND_USER policy<{'amd64': 'y'}> +CONFIG_UPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UPROBE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_US5182D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_USB4_DEBUGFS_WRITE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB4_DMA_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB4_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USBIP_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USBIP_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USBIP_HOST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USBIP_VHCI_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USBIP_VHCI_HC_PORTS policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8'}> +CONFIG_USBIP_VHCI_NR_HCS policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_USBIP_VUDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USBPCWATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ACM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ADUTUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_AIRSPY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_ALI_M5632 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_AMD5536UDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_AN2720 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ANNOUNCE_NEW_DEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_APPLEDISPLAY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ARCH_HAS_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ARMLINUX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ASPEED_UDC policy<{'armhf': 'm'}> +CONFIG_USB_ASPEED_VHUB policy<{'armhf': 'm'}> +CONFIG_USB_ATM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_AUDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_AUTOSUSPEND_DELAY policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2'}> +CONFIG_USB_BDC_UDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_BELKIN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_C67X00_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CATC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDC_COMPOSITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDC_PHONET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDNS2_UDC policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDNS3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDNS3_GADGET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CDNS3_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CDNS3_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_CDNS3_PCI_WRAP policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDNS3_TI policy<{'arm64': 'm'}> +CONFIG_USB_CDNSP_GADGET policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_USB_CDNSP_HOST policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_USB_CDNSP_PCI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDNS_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CDNS_SUPPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CHAOSKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CHIPIDEA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CHIPIDEA_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CHIPIDEA_IMX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_MSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_NPCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_TEGRA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_UDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CONFIGFS_ACM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_ECM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_ECM_SUBSET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_EEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_HID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_LB_SS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_MIDI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_MIDI2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_PRINTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_TCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_UAC1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_UAC2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_UVC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_MASS_STORAGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_NCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_OBEX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_PHONET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_RNDIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_SERIAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONN_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CXACRU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CYPRESS_CY7C63 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CYTHERM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_USB_DEFAULT_PERSIST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_DSBR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_DUMMY_HCD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_DWC2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_DWC2_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_DWC2_DUAL_ROLE policy<{'armhf': 'n'}> +CONFIG_USB_DWC2_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_DWC2_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_DWC2_PERIPHERAL policy<{'armhf': 'n'}> +CONFIG_USB_DWC2_TRACK_MISSED_SOFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_DWC3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_DWC3_AM62 policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_APPLE policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_DUAL_ROLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_DWC3_EXYNOS policy<{'armhf': 'n'}> +CONFIG_USB_DWC3_GADGET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_DWC3_GENERIC_PLAT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_DWC3_GOOGLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_DWC3_HAPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_DWC3_HOST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_DWC3_IMX policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_IMX8MP policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_KEYSTONE policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_MESON_G12A policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_DWC3_OF_SIMPLE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_DWC3_OMAP policy<{'armhf': 'm'}> +CONFIG_USB_DWC3_PCI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_USB_DWC3_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_DWC3_RTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_DWC3_ULPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_DWC3_XILINX policy<{'arm64': 'm'}> +CONFIG_USB_DYNAMIC_MINORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EG20T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_EHCI_EXYNOS policy<{'armhf': 'n'}> +CONFIG_USB_EHCI_FSL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_EHCI_HCD_NPCM7XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_EHCI_HCD_OMAP policy<{'armhf': 'm'}> +CONFIG_USB_EHCI_HCD_ORION policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_USB_EHCI_HCD_PPC_OF policy<{'ppc64el': 'y'}> +CONFIG_USB_EHCI_MV policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_EHCI_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EHCI_ROOT_HUB_TT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EHCI_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_EHCI_TT_NEWSCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EHSET_TEST_FIXTURE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_EMI26 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_EMI62 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_EPSON2888 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_ETH_EEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ETH_RNDIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_EZUSB_FX2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_FEW_INIT_RETRIES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_FHCI_HCD policy<{'ppc64el': 'm'}> +CONFIG_USB_FUNCTIONFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_FUNCTIONFS_ETH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_FUNCTIONFS_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_FUNCTIONFS_RNDIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_F_ACM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_ECM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_EEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_MASS_STORAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_MIDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_MIDI2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_NCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_OBEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_PHONET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_PRINTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_RNDIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_SS_LB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_SUBSET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_TCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_UAC1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_UAC1_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_UAC2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_UVC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GADGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_GADGETFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GADGET_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_GADGET_DEBUG_FILES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_GADGET_DEBUG_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2'}> +CONFIG_USB_GADGET_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GADGET_VBUS_DRAW policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2'}> +CONFIG_USB_GADGET_XILINX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GL860 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GOKU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GPIO_VBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_GR_UDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_BENQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_CONEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_CPIA1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_DTCS033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_ETOMS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_FINEPIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_JEILINJ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_JL2005BCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_KINECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_KONICA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_MARS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_MR97310A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_NW80X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_OV519 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_OV534 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_OV534_9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_PAC207 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_PAC7302 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_PAC7311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SE401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SN9C2028 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SN9C20X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SONIXB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SONIXJ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA1528 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA505 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA506 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA508 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA561 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SQ905 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SQ905C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SQ930X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_STK014 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_STK1135 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_STV0680 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SUNPLUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_T613 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_TOPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_TOUPTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_TV8532 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_VC032X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_VICAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_XIRLINK_CIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_ZC3XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_ACM_MS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_DBGP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_DBGP_PRINTK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_G_DBGP_SERIAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_G_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_MULTI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_G_NCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_NOKIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_PRINTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_WEBCAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_HACKRF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_HCD_TEST_MODE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_HIDDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_HSIC_USB3503 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_HSIC_USB4604 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_HSO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_HUB_USB251XB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_IDMOUSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_IOWARRIOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_IPHETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_ISIGHTFW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ISP116X_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ISP1301 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ISP1760 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ISP1760_DUAL_ROLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ISP1760_GADGET_ROLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_ISP1760_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ISP1760_HOST_ROLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_ISP1761_UDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_KAWETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_KBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_KC2190 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_KEENE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_LAN78XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_LCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_LD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_LEDS_TRIGGER_USBPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_LED_TRIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_LEGOTOWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_LGM_PHY policy<{'amd64': 'm'}> +CONFIG_USB_LIBCOMPOSITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_LINK_LAYER_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_LJCA policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_USB_M5602 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MA901 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MASS_STORAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MAX3420_UDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MAX3421_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MDC800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MICROTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MIDI_GADGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MOUSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MR800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MSI2500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MTU3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_MTU3_DEBUG policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_USB_MTU3_DUAL_ROLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_USB_MTU3_GADGET policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_USB_MTU3_HOST policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_USB_MUSB_DSPS policy<{'armhf': 'm'}> +CONFIG_USB_MUSB_DUAL_ROLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_MUSB_GADGET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_MUSB_HOST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_MUSB_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_MUSB_OMAP2PLUS policy<{'armhf': 'm'}> +CONFIG_USB_MUSB_SUNXI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_USB_MUSB_TUSB6010 policy<{'armhf': 'm'}> +CONFIG_USB_MXS_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_USB_NET2280 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_AQC111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_AX88179_178A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_AX8817X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDCETHER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDC_EEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDC_MBIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDC_NCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDC_SUBSET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDC_SUBSET_ENABLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CH9200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CX82310_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_DM9601 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_DRIVERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_NET_GL620A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_HUAWEI_CDC_NCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_INT51X1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_KALMIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_MCS7830 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_NET1080 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_PLUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_QMI_WWAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_RNDIS_HOST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_SMSC75XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_SMSC95XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_SR9700 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_SR9800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_ZAURUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_OHCI_EXYNOS policy<{'armhf': 'n'}> +CONFIG_USB_OHCI_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_OHCI_HCD_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_OHCI_HCD_PLATFORM policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_OHCI_HCD_PPC_OF_BE policy<{'ppc64el': 'n'}> +CONFIG_USB_OHCI_HCD_PPC_OF_LE policy<{'ppc64el': 'n'}> +CONFIG_USB_OHCI_LITTLE_ENDIAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USB_ONBOARD_DEV policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_ONBOARD_DEV_USB5744 policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_OTG_FSM policy<{'riscv64': 'm'}> +CONFIG_USB_OTG_PRODUCTLIST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_OXU210HP_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_PCI_AMD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_PEGASUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_PHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_PRINTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_PULSE8_CEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_PWC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_PWC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_PWC_INPUT_EVDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_PXA27X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_QCOM_EUD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_R8A66597 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_R8A66597_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_RAINSHADOW_CEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_RAREMONO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_RAW_GADGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_RENESAS_USB3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_RENESAS_USBF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_RENESAS_USBHS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_RENESAS_USBHS_HCD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_RENESAS_USBHS_UDC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_ROLES_INTEL_XHCI policy<{'amd64': 'm'}> +CONFIG_USB_ROLE_SWITCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_RTL8150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_RTL8152 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_RTL8153_ECM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_RZV2M_USB3DRD policy<{'arm64': 'm'}> +CONFIG_USB_S2255 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_SERIAL_AIRCABLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_ARK3116 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_BELKIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_CH341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_CP210X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_CYBERJACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_CYPRESS_M8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_DIGI_ACCELEPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_EDGEPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_EDGEPORT_TI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_EMPEG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_F81232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_F8153X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_FTDI_SIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_GARMIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_SERIAL_IPAQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_IPW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_IR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_IUU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_KEYSPAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_KEYSPAN_PDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_KLSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_KOBIL_SCT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_MCT_U232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_METRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_MOS7715_PARPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_SERIAL_MOS7720 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_MOS7840 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_MXUPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_NAVMAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_OMNINET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_OPTICON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_OPTION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_OTI6858 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_PL2303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_QCAUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_QT2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_QUALCOMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SAFE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SAFE_PADDED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_SERIAL_SIERRAWIRELESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SIMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SPCP8X5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SSU100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SYMBOL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_TI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_UPD78F0730 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_VISOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_WHITEHEAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_WISHBONE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_WWAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_XR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_XSENS_MT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SEVSEG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_SI470X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SI4713 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SIERRA_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SISUSBVGA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_SL811_CS policy<{'amd64': 'm'}> +CONFIG_USB_SL811_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_SL811_HCD_ISO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_SNP_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SNP_UDC_PLAT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SPEEDTOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_STORAGE_ALAUDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_CYPRESS_ATACB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_DATAFAB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_STORAGE_ENE_UB6250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_FREECOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_ISD200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_JUMPSHOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_KARMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_ONETOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_REALTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_SDDR09 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_SDDR55 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_USBAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STV06XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_USB_TEGRA_PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_TEGRA_XUDC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_TMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_TRANCEVIBRATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_UAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_UEAGLEATM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_UHCI_ASPEED policy<{'armhf': 'y'}> +CONFIG_USB_UHCI_PLATFORM policy<{'armhf': 'y'}> +CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC policy<{'armhf': 'y'}> +CONFIG_USB_ULPI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_USB_ULPI_BUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ULPI_VIEWPORT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_USB_USBIO policy<{'amd64': 'm', 'arm64': '-', 'riscv64': '-'}> +CONFIG_USB_USBNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_USS720 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_U_AUDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_U_ETHER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_U_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_VIDEO_CLASS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_VL600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_WDM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_XEN_HCD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_USB_XHCI_HISTB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_XHCI_MTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_XHCI_MVEBU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_XHCI_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_XHCI_PCI_RENESAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_XHCI_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_XHCI_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_XHCI_RZV2M policy<{'arm64': 'y'}> +CONFIG_USB_XHCI_SIDEBAND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_XHCI_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_XUSBATM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_YUREX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ZERO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_ZERO_HNPTEST policy<{'riscv64': 'n'}> +CONFIG_USERFAULTFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USERIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USER_DECRYPTED_DATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USER_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USER_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USER_RETURN_NOTIFIER policy<{'amd64': 'y'}> +CONFIG_USER_STACKTRACE_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USE_OF policy<{'armhf': 'y'}> +CONFIG_USE_PERCPU_NUMA_NODE_ID policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USE_X86_SEG_SUPPORT policy<{'amd64': 'y'}> +CONFIG_UTS_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UVC_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UV_MMTIMER policy<{'amd64': 'm'}> +CONFIG_UV_SYSFS policy<{'amd64': 'm'}> +CONFIG_U_SERIAL_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_V4L2_ASYNC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_CCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_CCI_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_FLASH_LED_CLASS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_FWNODE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_H264 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_V4L2_ISP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_V4L2_JPEG_HELPER policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_V4L2_MEM2MEM_DEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_VP9 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_V4L_MEM2MEM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_V4L_PLATFORM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_V4L_TEST_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VALIDATE_FS_PARSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VBOXGUEST policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_VBOXSF_FS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_VCAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VCNL3020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VCNL4000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VCNL4035 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VCPU_STALL_DETECTOR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_VDPA_SIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VDPA_SIM_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VDPA_SIM_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VDPA_USER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VDSO policy<{'armhf': 'y'}> +CONFIG_VDSO_GETRANDOM policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VEML3235 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VEML6030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VEML6040 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VEML6046X00 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VEML6070 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VEML6075 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VEXPRESS_CONFIG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VF610_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VF610_DAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VFIO_AMBA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VFIO_AP policy<{'s390x': 'm'}> +CONFIG_VFIO_CCW policy<{'s390x': 'm'}> +CONFIG_VFIO_CDX policy<{'arm64': 'm'}> +CONFIG_VFIO_CONTAINER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFIO_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_VFIO_DEVICE_CDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_VFIO_FSL_MC policy<{'arm64': 'm'}> +CONFIG_VFIO_GROUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFIO_IOMMU_SPAPR_TCE policy<{'ppc64el': 'm'}> +CONFIG_VFIO_IOMMU_TYPE1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 's390x': 'm'}> +CONFIG_VFIO_MDEV policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': 'm'}> +CONFIG_VFIO_NOIOMMU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFIO_PCI_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VFIO_PCI_DMABUF policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFIO_PCI_IGD policy<{'amd64': 'y'}> +CONFIG_VFIO_PCI_INTX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VFIO_PCI_VGA policy<{'amd64': 'y'}> +CONFIG_VFIO_PLATFORM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VFIO_PLATFORM_AMDXGBE_RESET policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VFIO_PLATFORM_BASE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VFIO_VIRQFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFP policy<{'armhf': 'y'}> +CONFIG_VFPv3 policy<{'armhf': 'y'}> +CONFIG_VF_USE_ARM_GLOBAL_TIMER policy<{'armhf': 'y'}> +CONFIG_VF_USE_PIT_TIMER policy<{'armhf': 'n'}> +CONFIG_VGASTATE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VGA_ARB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VGA_ARB_MAX_GPUS policy<{'amd64': '16', 'arm64': '16', 'armhf': '16', 'ppc64el': '16', 'riscv64': '16'}> +CONFIG_VGA_CONSOLE policy<{'amd64': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VGA_SWITCHEROO policy<{'amd64': 'y'}> +CONFIG_VHOST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VHOST_CROSS_ENDIAN_LEGACY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VHOST_IOTLB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VHOST_MENU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VHOST_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VHOST_RING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VHOST_SCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VHOST_TASK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VHOST_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VHOST_VSOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIA_RHINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VIA_RHINE_MMIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIA_VELOCITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VIA_WDT policy<{'amd64': 'm'}> +CONFIG_VIDEO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIDEOBUF2_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_DMA_CONTIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_DMA_SG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_DVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_MEMOPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_V4L2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_VMALLOC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOMODE_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_AD5820 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADP1653 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7170 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7175 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7180 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7183 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7343 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7393 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV748X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7511 policy<{'amd64': 'm'}> +CONFIG_VIDEO_ADV7511_CEC policy<{'amd64': 'n'}> +CONFIG_VIDEO_ADV7604 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7604_CEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_ADV7842 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7842_CEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_ADV_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_VIDEO_AK7375 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_AK881X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ALLEGRO_DVT policy<{'arm64': 'm'}> +CONFIG_VIDEO_ALVIUM_CSI2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_AMD_ISP4_CAPTURE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'n'}> +CONFIG_VIDEO_AMPHION_VPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_APTINA_PLL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_AR0521 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ASPEED policy<{'amd64': '-', 'arm64': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VIDEO_AU0828 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_AU0828_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_AU0828_V4L2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_BT819 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_BT848 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_BT856 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_BT866 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_C3_ISP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_C3_MIPI_ADAPTER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_C3_MIPI_CSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_CADENCE_CSI2RX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CADENCE_CSI2TX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CAFE_CCIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CAMERA_LENS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_CAMERA_SENSOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_CCS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CCS_PLL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_COBALT policy<{'amd64': 'm'}> +CONFIG_VIDEO_CODA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_CS3308 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CS5345 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CS53L32A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX18 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX18_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX231XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX231XX_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX231XX_DVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX231XX_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_CX2341X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX23885 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX25821 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX25821_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX25840 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88_BLACKBIRD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88_DVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88_ENABLE_VP3054 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_CX88_MPEG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88_VP3054 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DS90UB913 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DS90UB953 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DS90UB960 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DT3155 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DW100 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_DW9714 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DW9719 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DW9768 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DW9807_VCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DW_MIPI_CSI2RX policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VIDEO_E5010_JPEG_ENC policy<{'amd64': '-', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VIDEO_EM28XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_EM28XX_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_EM28XX_DVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_EM28XX_RC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_EM28XX_V4L2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ET8EK8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_FB_IVTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_FB_IVTV_FORCE_PAT policy<{'amd64': 'y'}> +CONFIG_VIDEO_FIXED_MINOR_RANGES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_VIDEO_GC0308 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GC0310 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GC05A2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GC08A3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GC2145 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GO7007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GO7007_LOADER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GO7007_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GO7007_USB_S2250_BOARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GS1662 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HANTRO policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_VIDEO_HANTRO_HEVC_RFC policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_VIDEO_HANTRO_IMX8M policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VIDEO_HANTRO_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VIDEO_HANTRO_STM32MP25 policy<{'arm64': 'y'}> +CONFIG_VIDEO_HANTRO_SUNXI policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_VIDEO_HDPVR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HEXIUM_GEMINI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HEXIUM_ORION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HI556 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HI846 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HI847 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX208 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX214 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX219 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX258 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX274 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX283 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX290 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX296 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX319 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX334 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX335 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX355 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX412 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX415 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX7_CSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX8_ISI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX8_ISI_M2M policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VIDEO_IMX8_JPEG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX_MEDIA policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_VIDEO_IMX_MIPI_CSIS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX_PXP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX_VDOA policy<{'armhf': 'm'}> +CONFIG_VIDEO_INTEL_IPU6 policy<{'amd64': 'm'}> +CONFIG_VIDEO_INTEL_IPU7 policy<{'amd64': 'm'}> +CONFIG_VIDEO_IPU3_CIO2 policy<{'amd64': 'm'}> +CONFIG_VIDEO_IPU3_IMGU policy<{'amd64': 'm'}> +CONFIG_VIDEO_IR_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ISL7998X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IVTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IVTV_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_KS0127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_LM3560 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_LM3646 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_LT6911UXE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_M52790 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MALI_C55 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_MAX9271_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MAX9286 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MAX96712 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MAX96714 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MAX96717 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MEDIATEK_JPEG policy<{'arm64': 'm'}> +CONFIG_VIDEO_MEDIATEK_MDP policy<{'arm64': 'm'}> +CONFIG_VIDEO_MEDIATEK_MDP3 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MEDIATEK_VCODEC policy<{'arm64': 'm'}> +CONFIG_VIDEO_MEDIATEK_VCODEC_SCP policy<{'arm64': 'y'}> +CONFIG_VIDEO_MEDIATEK_VCODEC_VPU policy<{'arm64': 'y'}> +CONFIG_VIDEO_MEDIATEK_VPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_MEM2MEM_DEINTERLACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MESON_GE2D policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_MESON_VDEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_MGB4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ML86V7667 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MMP_CAMERA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_MSP3400 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9M001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9M111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9M114 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9P031 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9T112 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9V011 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9V032 policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9V111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MUX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MXB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_NPCM_VCD_ECE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_OG01A1B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OG0VE1B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OS05B10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV01A10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV02A10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV02C10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV02E10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV08D10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV08X40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV13858 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV13B10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2659 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2680 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2685 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2732 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2735 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2740 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV4689 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5640 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5645 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5647 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5648 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5670 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5675 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5693 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5695 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV6211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV64A40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV7251 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV7640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV7670 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV772X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV7740 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV8856 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV8858 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV8865 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV9282 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV9640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV9650 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV9734 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_PCI_SKELETON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_VIDEO_PVRUSB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_PVRUSB2_DEBUGIFC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_VIDEO_PVRUSB2_DVB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_PVRUSB2_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_QCOM_CAMSS policy<{'arm64': 'm'}> +CONFIG_VIDEO_QCOM_IRIS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_QCOM_VENUS policy<{'arm64': 'm'}> +CONFIG_VIDEO_RCAR_CSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RCAR_DRIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RCAR_ISP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RCAR_VIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RDACM20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_RDACM21 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_RENESAS_CEU policy<{'armhf': 'm'}> +CONFIG_VIDEO_RENESAS_FCP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RENESAS_FDP1 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RENESAS_JPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RENESAS_VSP1 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RJ54N1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ROCKCHIP_CIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_ROCKCHIP_ISP1 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_ROCKCHIP_RGA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_ROCKCHIP_VDEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RP1_CFE policy<{'amd64': 'n', 'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_VIDEO_RZG2L_CRU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RZG2L_CSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RZV2H_IVC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_S5C73M3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_S5K3M5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_S5K5BAF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_S5K6A3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_S5KJN1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA6588 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA6752HS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA711X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7134 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7134_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7134_DVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7134_GO7007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7134_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_SAA7146 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7146_VV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7164 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA717X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7185 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS policy<{'armhf': 'n'}> +CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC policy<{'armhf': 'n'}> +CONFIG_VIDEO_SAMSUNG_S5P_G2D policy<{'armhf': 'n'}> +CONFIG_VIDEO_SAMSUNG_S5P_JPEG policy<{'armhf': 'n'}> +CONFIG_VIDEO_SAMSUNG_S5P_MFC policy<{'armhf': 'n'}> +CONFIG_VIDEO_SOLO6X10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'n', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SONY_BTF_MPX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_STK1160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_STM32_CSI policy<{'arm64': 'm'}> +CONFIG_VIDEO_STM32_DCMI policy<{'arm64': 'm'}> +CONFIG_VIDEO_STM32_DCMIPP policy<{'arm64': 'm'}> +CONFIG_VIDEO_STM32_DMA2D policy<{'arm64': 'm'}> +CONFIG_VIDEO_ST_MIPID02 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SUN4I_CSI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SUN6I_CSI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SUN6I_ISP policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_VIDEO_SUN6I_MIPI_CSI2 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_VIDEO_SUN8I_DEINTERLACE policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SUN8I_ROTATE policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SUNXI policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SUNXI_CEDRUS policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SYNOPSYS_HDMIRX policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SYNOPSYS_HDMIRX_LOAD_DEFAULT_EDID policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VIDEO_T4KA3 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TC358743 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TC358743_CEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_TC358746 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TDA1997X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TDA7432 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TDA9840 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TEA6415C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TEA6420 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_TEGRA_TPG policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_VIDEO_TEGRA_VDE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_THP7312 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_THS7303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_THS8200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TI_CAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_TI_CAL_MC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VIDEO_TI_CSC policy<{'armhf': 'm'}> +CONFIG_VIDEO_TI_J721E_CSI2RX policy<{'arm64': 'm'}> +CONFIG_VIDEO_TI_SC policy<{'armhf': 'm'}> +CONFIG_VIDEO_TI_VIP policy<{'armhf': 'm'}> +CONFIG_VIDEO_TI_VPDMA policy<{'armhf': 'm'}> +CONFIG_VIDEO_TI_VPE policy<{'armhf': 'm'}> +CONFIG_VIDEO_TI_VPE_DEBUG policy<{'armhf': 'n'}> +CONFIG_VIDEO_TLV320AIC23B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TUNER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TVAUDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TVEEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TVP514X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TVP5150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TVP7002 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW2804 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW5864 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW68 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW686X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW9900 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW9903 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW9906 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW9910 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_UDA1342 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_UPD64031A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_UPD64083 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_USBTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_V4L2_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_V4L2_SUBDEV_API policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_V4L2_TPG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VD55G1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VD56G3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VGXY61 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VIA_CAMERA policy<{'amd64': 'm'}> +CONFIG_VIDEO_VICODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VIM2M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VISL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VIVID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VIVID_CEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_VIVID_MAX_DEVS policy<{'amd64': '64', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64'}> +CONFIG_VIDEO_VIVID_OSD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_VP27SMPX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VPX3220 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_WAVE_VPU policy<{'arm64': 'm'}> +CONFIG_VIDEO_WM8739 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_WM8775 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_XILINX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_XILINX_CSI2RXSS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_XILINX_TPG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_XILINX_VTC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ZORAN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_VIPERBOARD_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIRTIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_ANCHOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_BALLOON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_VIRTIO_DMA_SHARED_BUFFER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_INPUT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_IOMMU policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_VIRTIO_MEM policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_MENU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIRTIO_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_PCI_ADMIN_LEGACY policy<{'amd64': 'y'}> +CONFIG_VIRTIO_PCI_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_PCI_LIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_PCI_LIB_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_PMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VIRTIO_RTC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_RTC_ARM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VIRTIO_RTC_CLASS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIRTIO_RTC_PTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIRTIO_VFIO_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_VIRTIO_VFIO_PCI_ADMIN_LEGACY policy<{'amd64': 'y'}> +CONFIG_VIRTIO_VSOCKETS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_VSOCKETS_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTUALIZATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRT_CPU_ACCOUNTING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRT_CPU_ACCOUNTING_GEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIRT_CPU_ACCOUNTING_NATIVE policy<{'ppc64el': 'n', 's390x': 'y'}> +CONFIG_VIRT_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRT_WIFI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIRT_XFER_TO_GUEST_WORK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VISCONTI_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_VISL_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_VITESSE_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VL53L0X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VL53L1X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VL6180 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VLAN_8021Q policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VLAN_8021Q_GVRP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VLAN_8021Q_MVRP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VMAP_PFN policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y', 's390x': '-'}> +CONFIG_VMAP_STACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VMCORE_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VMCP policy<{'s390x': 'y'}> +CONFIG_VMCP_CMA_SIZE policy<{'s390x': '4'}> +CONFIG_VMD policy<{'amd64': 'm'}> +CONFIG_VME_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_VME_FAKE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VME_TSI148 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VME_USER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VMGENID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VMLINUX_MAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VMLOGRDR policy<{'s390x': 'm'}> +CONFIG_VMSPLIT_1G policy<{'armhf': 'n'}> +CONFIG_VMSPLIT_2G policy<{'armhf': 'n'}> +CONFIG_VMSPLIT_3G policy<{'armhf': 'y'}> +CONFIG_VMWARE_BALLOON policy<{'amd64': 'm'}> +CONFIG_VMWARE_PVSCSI policy<{'amd64': 'm'}> +CONFIG_VMWARE_VMCI policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_VMWARE_VMCI_VSOCKETS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_VMXNET3 policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_VM_EVENT_COUNTERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VORTEX policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VPA_PMU policy<{'ppc64el': 'm'}> +CONFIG_VP_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VSOCKETS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VSOCKETS_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VSOCKETS_LOOPBACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VSOCKMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VSX policy<{'ppc64el': 'y'}> +CONFIG_VT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VT_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VT_CONSOLE_SLEEP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VT_HW_CONSOLE_BINDING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VXFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_VXLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VZ89X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_W1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_W1_CON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_W1_MASTER_AMD_AXI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_W1_MASTER_DS2482 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_MASTER_DS2490 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_MASTER_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_MASTER_MATROX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_MASTER_MXC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_W1_MASTER_SGI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_MASTER_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_W1_SLAVE_DS2405 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2406 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2408 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2408_READBACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_W1_SLAVE_DS2413 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2423 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2430 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2431 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2433 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2433_CRC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2438 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS250X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2781 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2805 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS28E04 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS28E17 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_SMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_THERM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W83627HF_WDT policy<{'amd64': 'm'}> +CONFIG_W83877F_WDT policy<{'amd64': 'm'}> +CONFIG_W83977F_WDT policy<{'amd64': 'm'}> +CONFIG_WAFER_WDT policy<{'amd64': 'm'}> +CONFIG_WAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_WANT_COMPAT_NETLINK_MESSAGES policy<{'amd64': 'y'}> +CONFIG_WANT_DEV_COREDUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WANXL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WATCHDOG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WATCHDOG_NOWAYOUT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WATCHDOG_OPEN_TIMEOUT policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_WATCHDOG_RTAS policy<{'ppc64el': 'm'}> +CONFIG_WATCHDOG_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCH_QUEUE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WCN36XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WCN36XX_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_WDAT_WDT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_WDTPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WERROR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WEXT_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WEXT_PRIV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WEXT_PROC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WFX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WIL6210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WIL6210_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WIL6210_ISR_COR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WIL6210_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WILC1000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WILC1000_HW_OOB_INTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WILC1000_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WILC1000_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WILCO_EC policy<{'amd64': 'm'}> +CONFIG_WILCO_EC_DEBUGFS policy<{'amd64': 'm'}> +CONFIG_WILCO_EC_EVENTS policy<{'amd64': 'm'}> +CONFIG_WILCO_EC_TELEMETRY policy<{'amd64': 'm'}> +CONFIG_WINBOND_840 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WINDFARM policy<{'ppc64el': 'm'}> +CONFIG_WINMATE_FM07_KEYS policy<{'amd64': 'm'}> +CONFIG_WIREGUARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_WIREGUARD_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WIRELESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WIRELESS_EXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WIRELESS_HOTKEY policy<{'amd64': 'm'}> +CONFIG_WIZNET_BUS_ANY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WIZNET_BUS_DIRECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_WIZNET_BUS_INDIRECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_WIZNET_W5100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WIZNET_W5100_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WIZNET_W5300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WL1251 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WL1251_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WL1251_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WL12XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WL18XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WLAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_ADMTEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_ATH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_ATMEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_BROADCOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_INTEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_INTERSIL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_MARVELL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_MEDIATEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_MICROCHIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_PURELIFI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_QUANTENNA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_RALINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_REALTEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_RSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_SILABS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_ST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_TI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_ZYDAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLCORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WLCORE_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WLCORE_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WM831X_BACKUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WM831X_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WM831X_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WM8350_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WM8350_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WMI_BMOF policy<{'amd64': 'm'}> +CONFIG_WPCM450_SOC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_WQ_CPU_INTENSIVE_REPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WQ_POWER_EFFICIENT_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WQ_WATCHDOG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WWAN_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WWAN_HWSIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WW_MUTEX_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_X25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_X86 policy<{'amd64': 'y'}> +CONFIG_X86_16BIT policy<{'amd64': 'y'}> +CONFIG_X86_64 policy<{'amd64': 'y'}> +CONFIG_X86_64_ACPI_NUMA policy<{'amd64': 'y'}> +CONFIG_X86_ACPI_CPUFREQ_CPB policy<{'amd64': 'y'}> +CONFIG_X86_AMD_FREQ_SENSITIVITY policy<{'amd64': 'm'}> +CONFIG_X86_AMD_PLATFORM_DEVICE policy<{'amd64': 'y'}> +CONFIG_X86_AMD_PSTATE policy<{'amd64': 'y'}> +CONFIG_X86_AMD_PSTATE_DEFAULT_MODE policy<{'amd64': '3'}> +CONFIG_X86_AMD_PSTATE_UT policy<{'amd64': 'n'}> +CONFIG_X86_ANDROID_TABLETS policy<{'amd64': 'm'}> +CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK policy<{'amd64': 'y'}> +CONFIG_X86_BUS_LOCK_DETECT policy<{'amd64': 'y'}> +CONFIG_X86_CET policy<{'amd64': 'y'}> +CONFIG_X86_CHECK_BIOS_CORRUPTION policy<{'amd64': 'y'}> +CONFIG_X86_CMOV policy<{'amd64': 'y'}> +CONFIG_X86_CPA_STATISTICS policy<{'amd64': 'n'}> +CONFIG_X86_CPUID policy<{'amd64': 'm'}> +CONFIG_X86_CPU_RESCTRL policy<{'amd64': 'y'}> +CONFIG_X86_CX8 policy<{'amd64': 'y'}> +CONFIG_X86_DEBUGCTLMSR policy<{'amd64': 'y'}> +CONFIG_X86_DEBUG_FPU policy<{'amd64': 'y'}> +CONFIG_X86_DECODER_SELFTEST policy<{'amd64': 'n'}> +CONFIG_X86_DIRECT_GBPAGES policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_CENTAUR_MCR policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_CYRIX_ARR policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_IBT policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_K6_MTRR policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_LAM policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_VME policy<{'amd64': 'y'}> +CONFIG_X86_ESPFIX64 policy<{'amd64': 'y'}> +CONFIG_X86_EXTENDED_PLATFORM policy<{'amd64': 'y'}> +CONFIG_X86_FRED policy<{'amd64': 'y'}> +CONFIG_X86_GOLDFISH policy<{'amd64': 'n'}> +CONFIG_X86_HAVE_PAE policy<{'amd64': 'y'}> +CONFIG_X86_HV_CALLBACK_VECTOR policy<{'amd64': 'y'}> +CONFIG_X86_INTEL_LPSS policy<{'amd64': 'y'}> +CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS policy<{'amd64': 'y'}> +CONFIG_X86_INTEL_MID policy<{'amd64': 'n'}> +CONFIG_X86_INTEL_PSTATE policy<{'amd64': 'y'}> +CONFIG_X86_INTEL_TSX_MODE_AUTO policy<{'amd64': 'n'}> +CONFIG_X86_INTEL_TSX_MODE_OFF policy<{'amd64': 'y'}> +CONFIG_X86_INTEL_TSX_MODE_ON policy<{'amd64': 'n'}> +CONFIG_X86_INTERNODE_CACHE_SHIFT policy<{'amd64': '6'}> +CONFIG_X86_IOPL_IOPERM policy<{'amd64': 'y'}> +CONFIG_X86_IO_APIC policy<{'amd64': 'y'}> +CONFIG_X86_L1_CACHE_SHIFT policy<{'amd64': '6'}> +CONFIG_X86_LOCAL_APIC policy<{'amd64': 'y'}> +CONFIG_X86_MCE policy<{'amd64': 'y'}> +CONFIG_X86_MCELOG_LEGACY policy<{'amd64': 'y'}> +CONFIG_X86_MCE_AMD policy<{'amd64': 'y'}> +CONFIG_X86_MCE_INJECT policy<{'amd64': 'm'}> +CONFIG_X86_MCE_INTEL policy<{'amd64': 'y'}> +CONFIG_X86_MCE_THRESHOLD policy<{'amd64': 'y'}> +CONFIG_X86_MEM_ENCRYPT policy<{'amd64': 'y'}> +CONFIG_X86_MINIMUM_CPU_FAMILY policy<{'amd64': '64'}> +CONFIG_X86_MPPARSE policy<{'amd64': 'y'}> +CONFIG_X86_MSR policy<{'amd64': 'm'}> +CONFIG_X86_NEED_RELOCS policy<{'amd64': 'y'}> +CONFIG_X86_NUMACHIP policy<{'amd64': 'y'}> +CONFIG_X86_P4_CLOCKMOD policy<{'amd64': 'm'}> +CONFIG_X86_PAT policy<{'amd64': 'y'}> +CONFIG_X86_PKG_TEMP_THERMAL policy<{'amd64': 'm'}> +CONFIG_X86_PLATFORM_DEVICES policy<{'amd64': 'y'}> +CONFIG_X86_PLATFORM_DRIVERS_DELL policy<{'amd64': 'y'}> +CONFIG_X86_PLATFORM_DRIVERS_HP policy<{'amd64': 'y'}> +CONFIG_X86_PLATFORM_DRIVERS_UNIWILL policy<{'amd64': 'y'}> +CONFIG_X86_PMEM_LEGACY policy<{'amd64': 'y'}> +CONFIG_X86_PMEM_LEGACY_DEVICE policy<{'amd64': 'y'}> +CONFIG_X86_PM_TIMER policy<{'amd64': 'y'}> +CONFIG_X86_POSTED_MSI policy<{'amd64': 'n'}> +CONFIG_X86_REQUIRED_FEATURE_ALWAYS policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_CMOV policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_CPUID policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_CX8 policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_FPU policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_FXSR policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_LM policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_MSR policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_NOPL policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_PAE policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_XMM policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_XMM2 policy<{'amd64': 'y'}> +CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS policy<{'amd64': 'y'}> +CONFIG_X86_SGX policy<{'amd64': 'y'}> +CONFIG_X86_SGX_KVM policy<{'amd64': 'y'}> +CONFIG_X86_SPEEDSTEP_LIB policy<{'amd64': 'm'}> +CONFIG_X86_SUPPORTS_MEMORY_FAILURE policy<{'amd64': 'y'}> +CONFIG_X86_THERMAL_VECTOR policy<{'amd64': 'y'}> +CONFIG_X86_TSC policy<{'amd64': 'y'}> +CONFIG_X86_UMIP policy<{'amd64': 'y'}> +CONFIG_X86_USER_SHADOW_STACK policy<{'amd64': 'y'}> +CONFIG_X86_VERBOSE_BOOTUP policy<{'amd64': 'n'}> +CONFIG_X86_VMX_FEATURE_NAMES policy<{'amd64': 'y'}> +CONFIG_X86_VSMP policy<{'amd64': 'n'}> +CONFIG_X86_VSYSCALL_EMULATION policy<{'amd64': 'y'}> +CONFIG_X86_X2APIC policy<{'amd64': 'y'}> +CONFIG_X9250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XARRAY_MULTI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XDP_SOCKETS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XDP_SOCKETS_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n'}> +CONFIG_XENFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_ACPI policy<{'amd64': 'y'}> +CONFIG_XEN_AUTO_XLATE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_BACKEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_BALLOON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_BALLOON_MEMORY_HOTPLUG policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_BLKDEV_BACKEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_COMPAT_XENFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_DEBUG_FS policy<{'amd64': 'n'}> +CONFIG_XEN_DEV_EVTCHN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_DOM0 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_EFI policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_FBDEV_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_FRONT_PGDIR_SHBUF policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_XEN_GNTDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_GNTDEV_DMABUF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_GRANT_DEV_ALLOC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_GRANT_DMA_ALLOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_GRANT_DMA_IOMMU policy<{'arm64': 'y'}> +CONFIG_XEN_GRANT_DMA_OPS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_HAVE_PVMMU policy<{'amd64': 'y'}> +CONFIG_XEN_HAVE_VPMU policy<{'amd64': 'y'}> +CONFIG_XEN_MCE_LOG policy<{'amd64': 'y'}> +CONFIG_XEN_MEMORY_HOTPLUG_LIMIT policy<{'amd64': '512'}> +CONFIG_XEN_NETDEV_BACKEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_PCIDEV_BACKEND policy<{'amd64': 'm'}> +CONFIG_XEN_PCIDEV_FRONTEND policy<{'amd64': 'm'}> +CONFIG_XEN_PCIDEV_STUB policy<{'arm64': 'm'}> +CONFIG_XEN_PCI_STUB policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_PRIVCMD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_XEN_PRIVCMD_EVENTFD policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_PV policy<{'amd64': 'y'}> +CONFIG_XEN_PVCALLS_BACKEND policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-'}> +CONFIG_XEN_PVCALLS_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_PVH policy<{'amd64': 'y'}> +CONFIG_XEN_PVHVM policy<{'amd64': 'y'}> +CONFIG_XEN_PVHVM_GUEST policy<{'amd64': 'y'}> +CONFIG_XEN_PVHVM_SMP policy<{'amd64': 'y'}> +CONFIG_XEN_PV_DOM0 policy<{'amd64': 'y'}> +CONFIG_XEN_PV_MSR_SAFE policy<{'amd64': 'y'}> +CONFIG_XEN_PV_SMP policy<{'amd64': 'y'}> +CONFIG_XEN_SCRUB_PAGES_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_SCSI_BACKEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_SCSI_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_SYMS policy<{'amd64': 'y'}> +CONFIG_XEN_SYS_HYPERVISOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_UNPOPULATED_ALLOC policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_VIRTIO policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_VIRTIO_FORCE_GRANT policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_XEN_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_XENBUS_FRONTEND policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XE_VFIO_PCI policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_XFRM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFRM_AH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_ALGO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_ESP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_ESPINTCP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFRM_INTERFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_IPCOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_IPTFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_MIGRATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_XFRM_OFFLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFRM_STATISTICS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFRM_SUB_POLICY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_XFRM_USER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_USER_COMPAT policy<{'amd64': 'm'}> +CONFIG_XFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_XFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFS_ONLINE_SCRUB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_XFS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFS_QUOTA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFS_RT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFS_SUPPORT_ASCII_CI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFS_SUPPORT_V4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFS_WARN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_XGENE_DMA policy<{'arm64': 'm'}> +CONFIG_XGENE_PMU policy<{'arm64': 'y'}> +CONFIG_XGENE_SLIMPRO_MBOX policy<{'arm64': 'm'}> +CONFIG_XIAOMI_WMI policy<{'amd64': 'm'}> +CONFIG_XILINX_AMS policy<{'arm64': 'm'}> +CONFIG_XILINX_AXI_EMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_XILINX_DMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILINX_EMACLITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XILINX_GMII2RGMII policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XILINX_INTC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_XILINX_LL_TEMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XILINX_PR_DECOUPLER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILINX_SDFEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XILINX_VCU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_XILINX_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XILINX_WINDOW_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_XILINX_XADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILINX_XDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILINX_ZYNQMP_DMA policy<{'arm64': 'm'}> +CONFIG_XILINX_ZYNQMP_DPDMA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILLYBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XILLYBUS_CLASS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILLYBUS_OF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILLYBUS_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILLYUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_XIL_AXIS_FIFO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XLNX_EVENT_MANAGER policy<{'arm64': 'y'}> +CONFIG_XLNX_R5_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_XMON policy<{'ppc64el': 'y'}> +CONFIG_XMON_DEFAULT policy<{'ppc64el': 'n'}> +CONFIG_XMON_DEFAULT_RO_MODE policy<{'ppc64el': 'y'}> +CONFIG_XMON_DISASSEMBLY policy<{'ppc64el': 'y'}> +CONFIG_XOR_BLOCKS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XOR_BLOCKS_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XPOWER_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_XPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XXHASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC_ARM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_XZ_DEC_ARM64 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC_ARMTHUMB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_XZ_DEC_BCJ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC_MICROLZMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC_POWERPC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_XZ_DEC_RISCV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC_SPARC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_XZ_DEC_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XZ_DEC_X86 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_YAMAHA_YAS530 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_YENTA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-'}> +CONFIG_YENTA_ENE_TUNE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_YENTA_O2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_YENTA_RICOH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_YENTA_TI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_YENTA_TOSHIBA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_YOGABOOK policy<{'amd64': 'm'}> +CONFIG_YT2_1380 policy<{'amd64': 'm'}> +CONFIG_ZBOOT_ROM_BSS policy<{'armhf': '0x0'}> +CONFIG_ZBOOT_ROM_TEXT policy<{'armhf': '0x0'}> +CONFIG_ZCRYPT policy<{'s390x': 'm'}> +CONFIG_ZD1211RW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZD1211RW_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ZEROPLUS_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ZERO_CALL_USED_REGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZFCP policy<{'s390x': 'm'}> +CONFIG_ZIIRAVE_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ZISOFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZL3073X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ZL3073X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ZL3073X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZLIB_DEFLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZLIB_INFLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZONEFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ZONE_DEVICE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZONE_DMA32 policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ZOPT2201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZPA2326 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZPA2326_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZPA2326_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZRAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ZRAM_BACKEND_842 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_BACKEND_DEFLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_BACKEND_LZ4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_BACKEND_LZ4HC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_BACKEND_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_BACKEND_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_DEF_COMP policy<{'amd64': '"lzo-rle"', 'arm64': '"lzo-rle"', 'armhf': '"lzo-rle"', 'ppc64el': '"lzo-rle"', 'riscv64': '"lzo-rle"', 's390x': '"lzo-rle"'}> +CONFIG_ZRAM_DEF_COMP_842 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_DEF_COMP_DEFLATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZ4 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZ4HC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZORLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_DEF_COMP_ZSTD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_MEMORY_TRACKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_MULTI_COMP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_TRACK_ENTRY_ACTIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_WRITEBACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSMALLOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSMALLOC_CHAIN_SIZE policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8', 's390x': '8'}> +CONFIG_ZSMALLOC_STAT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSTD_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSTD_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSTD_DECOMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSWAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT policy<{'amd64': '"lzo"', 'arm64': '"lzo"', 'armhf': '"lzo"', 'ppc64el': '"lzo"', 'riscv64': '"lzo"', 's390x': '"lzo"'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_DEFAULT_ON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_SHRINKER_DEFAULT_ON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZYNQMP_FIRMWARE policy<{'arm64': 'y'}> +CONFIG_ZYNQMP_FIRMWARE_DEBUG policy<{'arm64': 'n'}> +CONFIG_ZYNQMP_IPI_MBOX policy<{'arm64': 'y'}> +CONFIG_ZYNQMP_PM_DOMAINS policy<{'arm64': 'y'}> +CONFIG_ZYNQMP_POWER policy<{'arm64': 'y'}> diff --git a/debian.master/control.d/flavour-control.stub b/debian.master/control.d/flavour-control.stub new file mode 100644 index 00000000000000..9fc2050223a6ce --- /dev/null +++ b/debian.master/control.d/flavour-control.stub @@ -0,0 +1,88 @@ +# Items that get replaced: +# FLAVOUR +# ARCH +# SUPPORTED +# TARGET +# BOOTLOADER +# =PROVIDES= +# =DEPENDS= +# +# Items marked with =FOO= are optional +# +# This file describes the template for packages that are created for each flavour +# in debian/control.d/vars.* +# +# This file gets edited in a couple of places. See the debian/control.stub rule in +# debian/rules. PGGVER, ABINUM, and SRCPKGNAME are all converted in the +# process of creating debian/control. +# +# The flavour specific strings (ARCH, etc) are converted using values from the various +# flavour files in debian/control.d/vars.* +# +# XXX: Leave the blank line before the first package!! + +Package: linux-modules-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, =DEPENDS=wireless-regdb +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel modules for version PKGVER + Contains the corresponding System.map file, the modules built by the + packager, and scripts that try to ensure that the system is not left in an + unbootable state after an update. + . + Supports SUPPORTED processors. + . + TARGET + . + You likely do not want to install this package directly. Instead, install + the linux-FLAVOUR meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-headers-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-headers-PKGVER-ABINUM, ${shlibs:Depends} +Provides: linux-headers, linux-headers-3.0 +Description: Linux kernel headers for version PKGVER + This package provides kernel header files for version PKGVER. + . + This is for sites that want the latest kernel headers. Please read + /usr/share/doc/linux-headers-PKGVER-ABINUM/debian.README.gz for details. + +Package: linux-lib-rust-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: amd64 +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Rust library files related to Linux kernel version PKGVER + This package provides kernel library files for version PKGVER, that allow to + compile out-of-tree kernel modules written in Rust. + +Package: linux-tools-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-tools-PKGVER-ABINUM +Description: Linux kernel version specific tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools (such as x86_energy_perf_policy) for + version PKGVER-ABINUM. + +Package: linux-cloud-tools-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-cloud-tools-PKGVER-ABINUM +Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools for cloud for version PKGVER-ABINUM. + diff --git a/debian.master/control.d/flavour-signed-control.stub b/debian.master/control.d/flavour-signed-control.stub new file mode 100644 index 00000000000000..b059c7aeceedd1 --- /dev/null +++ b/debian.master/control.d/flavour-signed-control.stub @@ -0,0 +1,38 @@ +Package: linux-image=SIGN-ME-PKG=-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Provides: linux-image, fuse-module, =PROVIDES=${linux:rprovides} +Depends: ${misc:Depends}, ${shlibs:Depends}, kmod, linux-base (>= 4.5ubuntu1~16.04.1), linux-modules-PKGVER-ABINUM-FLAVOUR +Recommends: BOOTLOADER, dracut | linux-initramfs-tool +Breaks: flash-kernel (<< 3.90ubuntu2) [arm64 armhf], s390-tools (<< 2.3.0-0ubuntu3) [s390x] +Conflicts: linux-image=SIGN-PEER-PKG=-PKGVER-ABINUM-FLAVOUR +Suggests: bpftool, linux-perf, SRCPKGNAME-tools, linux-headers-PKGVER-ABINUM-FLAVOUR +Description: Linux kernel image for version PKGVER + This package contains the=SIGN-ME-TXT= Linux kernel image for version PKGVER. + . + Supports SUPPORTED processors. + . + TARGET + . + You likely do not want to install this package directly. Instead, install + the linux-FLAVOUR meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-image=SIGN-ME-PKG=-PKGVER-ABINUM-FLAVOUR-dbgsym +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends} +Provides: linux-debug +Description: Linux kernel debug image for version PKGVER + This package provides the=SIGN-ME-TXT= kernel debug image for version PKGVER. + . + This is for sites that wish to debug the kernel. + . + The kernel image contained in this package is NOT meant to boot from. It + is uncompressed, and unstripped. This package also includes the + unstripped modules. + diff --git a/debian.master/control.d/vars.generic b/debian.master/control.d/vars.generic new file mode 100644 index 00000000000000..3fd9beb0a77666 --- /dev/null +++ b/debian.master/control.d/vars.generic @@ -0,0 +1,5 @@ +arch="amd64 armhf arm64 ppc64el s390x" +supported="Generic" +target="Geared toward desktop and server systems." +bootloader="grub-pc [amd64] | grub-efi-amd64 [amd64] | grub-efi-ia32 [amd64] | grub [amd64] | lilo [amd64] | flash-kernel [armhf arm64] | grub-efi-arm64 [arm64] | grub-efi-arm [armhf] | grub-ieee1275 [ppc64el]" +provides="kvm-api-4, redhat-cluster-modules, ivtv-modules, virtualbox-guest-modules [amd64]" diff --git a/debian.master/control.d/vars.generic-64k b/debian.master/control.d/vars.generic-64k new file mode 100644 index 00000000000000..cd772b42f9d7e3 --- /dev/null +++ b/debian.master/control.d/vars.generic-64k @@ -0,0 +1,5 @@ +arch="arm64" +supported="Generic 64K pages" +target="Geared toward desktop and server systems." +bootloader="grub-efi-arm64 [arm64] | flash-kernel [arm64]" +provides="kvm-api-4, redhat-cluster-modules, ivtv-modules" diff --git a/debian.master/control.stub.in b/debian.master/control.stub.in new file mode 100644 index 00000000000000..9938932c94fb17 --- /dev/null +++ b/debian.master/control.stub.in @@ -0,0 +1,103 @@ +Source: SRCPKGNAME +Section: devel +Priority: optional +Maintainer: Ubuntu Kernel Team +Rules-Requires-Root: no +Standards-Version: 3.9.4.0 +Build-Depends: + autoconf , + automake , + bc , + bindgen:native [amd64 arm64 armhf ppc64el riscv64 s390x], + bison , + clang-21:native [amd64 arm64 armhf ppc64el riscv64 s390x], + cpio, + curl , + debhelper-compat (= 10), + default-jdk-headless:native , + dkms , + flex , + gawk , + java-common , + kmod , + libaudit-dev , + libbpf-dev , + libcap-dev , + libdebuginfod-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libdw-dev , + libelf-dev , + libiberty-dev , + libllvm21 , + liblzma-dev , + libnewt-dev , + libnl-3-dev, + libnl-genl-3-dev, + libnuma-dev [amd64 arm64 ppc64el s390x] , + libpci-dev , + libssl-dev , + libstd-rustc-dev [amd64 arm64 armhf ppc64el riscv64 s390x], + libstdc++-dev, + libtool , + libtraceevent-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libtracefs-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libudev-dev , + libunwind8-dev [amd64 arm64 armhf ppc64el] , + llvm-21-tools:native , + makedumpfile:native [amd64] , + openssl , + pahole (>= 1.29-2ubuntu2) [amd64 arm64 armhf ppc64el s390x riscv64] | dwarves (>= 1.21) [amd64 arm64 armhf ppc64el s390x riscv64] , + pkg-config , + python3:native , + python3-dev:native , + libpython3-dev , + python3-setuptools, + rsync [!i386] , + rust-src:native [amd64 arm64 armhf ppc64el riscv64 s390x], + rustc:native (>= 1.82) [amd64 arm64 armhf ppc64el riscv64 s390x], + rustfmt:native [amd64 arm64 armhf ppc64el riscv64 s390x], + uuid-dev , + zstd , + bpftool:native [amd64 arm64 armhf ppc64el riscv64 s390x] , +Build-Depends-Indep: + asciidoc , + bzip2 , + python3-docutils , + sharutils , + xmlto , +Vcs-Git: git://git.launchpad.net/~ubuntu-kernel/ubuntu/+source/linux/+git/=SERIES= +XS-Testsuite: autopkgtest + +Package: SRCPKGNAME-headers-PKGVER-ABINUM +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Header files related to Linux kernel version PKGVER + This package provides kernel header files for version PKGVER, for sites + that want the latest kernel headers. Please read + /usr/share/doc/SRCPKGNAME-headers-PKGVER-ABINUM/debian.README.gz for details + +Package: SRCPKGNAME-tools-PKGVER-ABINUM +Build-Profiles: +Architecture: amd64 armhf arm64 ppc64el s390x +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-tools-common +Description: Linux kernel version specific tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools (such as perf and x86_energy_perf_policy) for + version PKGVER-ABINUM. + You probably want to install linux-tools-PKGVER-ABINUM-. + +Package: SRCPKGNAME-cloud-tools-PKGVER-ABINUM +Build-Profiles: +Architecture: amd64 armhf +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-cloud-tools-common +Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools for cloud tools for version PKGVER-ABINUM. + You probably want to install linux-cloud-tools-PKGVER-ABINUM-. diff --git a/debian.master/dkms-versions b/debian.master/dkms-versions new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/debian.master/modprobe.d/common.conf b/debian.master/modprobe.d/common.conf new file mode 100644 index 00000000000000..e0fbbd6e060d43 --- /dev/null +++ b/debian.master/modprobe.d/common.conf @@ -0,0 +1,3 @@ +# LP:1434842 -- disable OSS drivers by default to allow pulseaudio to emulate +blacklist snd-mixer-oss +blacklist snd-pcm-oss diff --git a/debian.master/reconstruct b/debian.master/reconstruct new file mode 100755 index 00000000000000..039e4d0069c5c2 --- /dev/null +++ b/debian.master/reconstruct @@ -0,0 +1,2 @@ +#!/bin/sh +exit 0 diff --git a/debian.master/rules.d/amd64.mk b/debian.master/rules.d/amd64.mk new file mode 100644 index 00000000000000..4e4d608185a323 --- /dev/null +++ b/debian.master/rules.d/amd64.mk @@ -0,0 +1,20 @@ +build_arch = x86 +defconfig = defconfig +flavours = generic +build_image = bzImage +kernel_file = arch/$(build_arch)/boot/bzImage +install_file = vmlinuz +vdso = vdso_install +no_dumpfile = true +uefi_signed = true +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_x86 = true +do_tools_hyperv = true +do_tools_rtla = true +do_tools_acpidbg = true +do_lib_rust = true diff --git a/debian.master/rules.d/arm64.mk b/debian.master/rules.d/arm64.mk new file mode 100644 index 00000000000000..ad6fbd06ab703b --- /dev/null +++ b/debian.master/rules.d/arm64.mk @@ -0,0 +1,20 @@ +build_arch = arm64 +defconfig = defconfig +flavours = generic generic-64k +build_image = vmlinuz.efi +kernel_file = arch/$(build_arch)/boot/vmlinuz.efi +install_file = vmlinuz +no_dumpfile = true +uefi_signed = true + +vdso = vdso_install + +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_rtla = true + +do_dtbs = true diff --git a/debian.master/rules.d/armhf.mk b/debian.master/rules.d/armhf.mk new file mode 100644 index 00000000000000..492b11501cda9f --- /dev/null +++ b/debian.master/rules.d/armhf.mk @@ -0,0 +1,18 @@ +build_arch = arm +defconfig = defconfig +flavours = generic +build_image = zImage +kernel_file = arch/$(build_arch)/boot/zImage +install_file = vmlinuz +no_dumpfile = true + +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = false +do_tools_perf_jvmti = false +do_tools_perf_python = false +do_tools_bpftool = true +do_tools_bpftool_stub = true +do_tools_rtla = true + +do_dtbs = true diff --git a/debian.master/rules.d/hooks.mk b/debian.master/rules.d/hooks.mk new file mode 100644 index 00000000000000..37be6fdc0308ef --- /dev/null +++ b/debian.master/rules.d/hooks.mk @@ -0,0 +1,2 @@ +# Mainline Build. +do_mainline_build=true diff --git a/debian.master/rules.d/i386.mk b/debian.master/rules.d/i386.mk new file mode 100644 index 00000000000000..f8e5e503d54d45 --- /dev/null +++ b/debian.master/rules.d/i386.mk @@ -0,0 +1,12 @@ +build_arch = i386 +defconfig = defconfig +flavours = generic +build_image = bzImage +kernel_file = arch/$(build_arch)/boot/bzImage +install_file = vmlinuz +vdso = vdso_install +no_dumpfile = true +do_flavour_image_package = false +do_tools = false +do_flavour_header_package = false +do_common_headers_indep = false diff --git a/debian.master/rules.d/ppc64el.mk b/debian.master/rules.d/ppc64el.mk new file mode 100644 index 00000000000000..0888b6d3f1f52c --- /dev/null +++ b/debian.master/rules.d/ppc64el.mk @@ -0,0 +1,15 @@ +build_arch = powerpc +defconfig = pseries_le_defconfig +flavours = generic +build_image = vmlinux.strip +kernel_file = arch/powerpc/boot/vmlinux.strip +install_file = vmlinux +no_dumpfile = true +opal_signed = false +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_rtla = true diff --git a/debian.master/rules.d/riscv64.mk b/debian.master/rules.d/riscv64.mk new file mode 100644 index 00000000000000..d1fe692fc27690 --- /dev/null +++ b/debian.master/rules.d/riscv64.mk @@ -0,0 +1,21 @@ +build_arch = riscv +defconfig = defconfig +flavours = generic +build_image = Image +kernel_file = arch/$(build_arch)/boot/Image +install_file = vmlinuz + +vdso = vdso_install +no_dumpfile = true + +do_flavour_image_package = false +do_tools = true +do_flavour_header_package = false +do_common_headers_indep = false +do_tools_usbip = false +do_tools_cpupower = false +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_dtbs = false diff --git a/debian.master/rules.d/s390x.mk b/debian.master/rules.d/s390x.mk new file mode 100644 index 00000000000000..f4712e4e45f155 --- /dev/null +++ b/debian.master/rules.d/s390x.mk @@ -0,0 +1,18 @@ +build_arch = s390 +defconfig = defconfig +flavours = generic +build_image = bzImage +kernel_file = arch/$(build_arch)/boot/bzImage +install_file = vmlinuz + +vdso = vdso_install +no_dumpfile = true + +sipl_signed = true +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_rtla = false diff --git a/debian.master/tracking-bug b/debian.master/tracking-bug new file mode 100644 index 00000000000000..3252f5cc921156 --- /dev/null +++ b/debian.master/tracking-bug @@ -0,0 +1 @@ +2154256 d2026.05.25-1 diff --git a/debian.master/upstream-realtime b/debian.master/upstream-realtime new file mode 100644 index 00000000000000..96fce91a41c8f3 --- /dev/null +++ b/debian.master/upstream-realtime @@ -0,0 +1,3 @@ +# The following upstream releases have been ported: +[upstream-realtime] + linux-7.0.y-rt = 7.0-rc1-rt1 diff --git a/debian.master/upstream-stable b/debian.master/upstream-stable new file mode 100644 index 00000000000000..30e10948e88f96 --- /dev/null +++ b/debian.master/upstream-stable @@ -0,0 +1,3 @@ +# The following upstream stable releases have been ported: +[upstream-stable] + linux-6.17.y = v6.17.1 diff --git a/debian.master/variants b/debian.master/variants new file mode 100644 index 00000000000000..2dfa9251bb212d --- /dev/null +++ b/debian.master/variants @@ -0,0 +1,4 @@ +-7.1 +-- +-hwe-26.04 +-hwe-26.04-edge diff --git a/debian.qcom-x1e/changelog b/debian.qcom-x1e/changelog new file mode 100644 index 00000000000000..3334e35ca34de7 --- /dev/null +++ b/debian.qcom-x1e/changelog @@ -0,0 +1,8461 @@ +linux-qcom-x1e (7.2.0-jg-0sp11v19) resolute; urgency=medium + + * Add the Phase 84 IPTS IRQ-cadence path. When paired with the Phase 83 + minimal initialization, consume exactly one successful runtime header/body + response per level-low IRQ, matching the generic Linux HID-over-SPI + runtime contract without the Windows-only header/body delay. + * Keep the Phase 84 IRQ masked while synchronous initialization and + recovery own the transport, then enable it only after input mode is ready. + Require the validated empty-read quiesce and host-fault recovery guards; + leave feature exchanges and the load-time fallback falling-edge drain loop + unchanged. + * Promote the complete Phase 84 profile to the driver default after live X1E + validation of pressure, two-axis tilt, the barrel button, exact level-low + IRQ/report accounting, and a clean error/reset window. Retain all four + read-only module parameters as load-time fallbacks, without a global + modprobe configuration that could affect an older fallback kernel. + * Promote X1P/LCD (0x0c80) as a supported target of the same Phase 84 + default. Descriptor validation, product-preserving HIDRAW registration, + panel-provided metadata, DFT relay, and the level-low Denali wiring are + shared with X1E. Keep the qualification boundary explicit: the live result + is X1E-only, and X1P pen, forced recovery, and suspend/resume validation + remain pending. + + -- Leon Silcott Sun, 30 Aug 2026 01:47:29 +0100 + +linux-qcom-x1e (7.2.0-jg-0sp11v18) resolute; urgency=medium + + * Add an opt-in IPTS minimal-init profile for Surface Pro 11 pen reset + isolation. After the proven SET_FEATURE 0x05 mode command, bypass the + private GET/SET 0x70, short report 0x09, and SET_FEATURE 0x56 tail so the + panel activation matches the request set used by the working generic + HID-over-SPI plus iptsd stack. + * Keep the experiment behind the read-only ipts_minimal_init parameter, + require the HIDRAW bridge, reject Windows-parity initialization, and expose + the active profile in behavior statistics. Retain the v17 HID transport + lifetime fix and leave the existing initialization path as the default. + + -- Leon Silcott Sat, 29 Aug 2026 23:36:14 +0100 + +linux-qcom-x1e (7.2.0-jg-0sp11v17) resolute; urgency=medium + + * Fix the MSHW0485 HIDRAW bridge transport-private-data lifetime exposed by + immediate udev feature-report probes. Keep the parent touchscreen state in + hid_device.driver_data instead of the HID client driver's drvdata slot, and + reject callbacks without valid transport state rather than dereferencing a + NULL parent. + * Retain the v16 pen bridge and userspace iptsd contract. Clean-boot target + validation, transport fault recovery, and suspend/resume remain release + gates. + + -- Leon Silcott Sat, 29 Aug 2026 21:41:51 +0100 + +linux-qcom-x1e (7.2.0-jg-0sp11v16) resolute; urgency=medium + + * Surface Pro 11 pen part 2: expose the validated MSHW0485 native report + descriptor through a private-group, HIDRAW-only sibling device for + userspace DFT stylus processing. Preserve the existing kernel-owned panel + mode and direct multitouch path. + * Relay only core DFT reports 0x0b, 0x0c, 0x0d, and 0x1a. Keep report 0x07 + and privacy-sensitive report 0x6e on the diagnostic /dev/g6ts-heat ABI. + * Proxy and cache feature report 0x06 metadata, acknowledge iptsd report + 0x05 mode writes locally, and recreate HIDRAW through a deferred, + generation-aware lifecycle that avoids the transport/hidraw lock order. + Quiesce and remove the child before parent suspend, and bound registration + retries so transient allocation failures do not strand the generation. + * Enable CONFIG_TOUCHSCREEN_MSHW0485 in ubuntu_x1e_defconfig and require HID + plus HIDRAW for the driver. Build and static verification pass; target + hardware and suspend/resume qualification remain release gates. + + -- Leon Silcott Sat, 29 Aug 2026 19:17:07 +0100 + +linux-qcom-x1e (7.2.0-jg-0sp11v14) resolute; urgency=medium + + * Surface Pro 11 v14: enable the runtime-validated Sony IMX681 front camera + with a standalone driver and complete 3840x2640 RAW10 mode tables at + approximately 30 fps. Retain Denali's proven CCI address 0x10 and expose + one 1.203 GHz V4L2 link frequency, representing 2.406 Gsymbol/s on the + wire. + * Add the exact X1E80100 trio-0, 2.406-Gsymbol/s C-PHY profile and its + observed reset, toggle, common, analogue, IRQ-clear, and shutdown + lifecycle. Reject unvalidated C-PHY rates and topologies before receiver + power or register programming while preserving the generic D-PHY path. + * Complete CAMSS C-PHY routing through CSIPHY2, CSID0, and VFE0 RDI0, with + link-derived CSID clock votes, the matched CSID680 receiver configuration, + keep-all RDI handling, and VFE680 MIPI RAW mode. Propagate stream failures, + unwind partial starts, and shut down the receiver before its clocks and + supplies. + * Wire the Denali sensor with MCLK4, reset and power rails, user-facing + orientation, and the V4L2-managed privacy LED. Preserve Bayer order across + flip controls; expose grouped frame-length, 24-bit 0x0229 exposure, and + analogue/digital gain controls; and enable CONFIG_VIDEO_IMX681=m in the + ARM64 package policy. + * Preserve matched-stack provenance from turbineBMW repository b1f5237957b9 + and camera bundle 675d89b381d8: sensor 00cece0b87c4, Denali wiring + 8915ca862de4, X1E C-PHY/CSID plumbing b1eae4e60169, and observed receiver + sequence 8c1731648d04. + [karsies-wq https://github.com/karsies-wq] + [geocausa https://github.com/geocausa] + [turbineBMW https://github.com/turbineBMW] + + -- Leon Silcott Sat, 29 Aug 2026 08:59:29 +0100 + +linux-qcom-x1e (7.2.0-jg-0sp11v13) resolute; urgency=medium + + * Surface Pro 11 v13: add experimental camera receiver groundwork: + disable unconfigured CSID680 RDI crop/drop, select MIPI RAW mode for + VFE680 RDI, and guard CCS tiny floating-point limits against oversized + shifts. No camera sensors are enabled yet. + * Surface Pro 11 v13: enable the Sony IMX681 C-PHY front camera with + model-scoped CCS IMX681 support, the x1e80100 C-PHY receive path, + CAMSS C-PHY routing and receiver crop, Denali camera device-tree + nodes, and the privacy indicator + [karsies-wq https://github.com/karsies-wq] + + -- Leon Silcott Thu, 27 Aug 2026 16:05:30 +0100 + +linux-qcom-x1e (7.2.0-jg-0sp11v12) resolute; urgency=medium + + * Surface Pro 11 v12: adopt geocausa mic implementation (0072 VA DMIC + Windows divider + 0078 share VA DMIC clock with TX capture), drop our + VA DMIC DAPM-supply approach, retain TX capture DAI + micbias + 4.8 MHz + [geocausa https://github.com/geocausa] + + -- Leon Silcott Wed, 26 Aug 2026 18:30:00 +0100 + +linux-qcom-x1e (7.2.0-jg-0sp11v11) resolute; urgency=medium + + * Surface Pro 11 v11: support X1P MSHW0485 touchscreen product ID + (0x0c80) alongside the X1E (0x0c83); descriptor validation now + accepts both + * Surface Pro 11 v11: skip the SAM battery provider on Denali; + Qualcomm battmgr is the authoritative battery source there + + -- Justin White Mon, 24 Aug 2026 15:50:00 -0500 + +linux-qcom-x1e (7.2.0-jg-0sp11v10) resolute; urgency=medium + + * Surface Pro 11 v10: port geocausa Golden v33 TOP_CFG1 physical VI + parity (https://github.com/geocausa/SP11X1e-audio) on top of v9: + materialize WSA macro TOP_CFG1=0x03 after each enabled VI pair on + Denali [geocausa https://github.com/geocausa] + + -- Leon Silcott Mon, 24 Aug 2026 00:00:00 +0100 + +linux-qcom-x1e (7.2.0-jg-0sp11v9) resolute; urgency=medium + + * Surface Pro 11 v9: port geocausa SP11 Golden v32 audio parity + (https://github.com/geocausa/SP11X1e-audio): protected AudioReach + pull-mode graph, WSA VI feedback + CPS feedback transport, + Windows-ordered calibration/volume/mute semantics, WSA8845 + lifecycle fixes, SoundWire transport parity, 4.8 MHz DMIC clock + [geocausa https://github.com/geocausa] + + -- Leon Silcott Sun, 23 Aug 2026 00:00:00 +0100 + +linux-qcom-x1e (7.2.0-jg-0sp11v8) resolute; urgency=medium + + * Surface Pro 11 v8: platform_profile framework works without ACPI + (module-local kobject fallback), enabling power-profiles-daemon on + the DT-only SP11. + + -- Leon Silcott Sun, 23 Aug 2026 00:00:00 +0100 + +linux-qcom-x1e (7.2.0-jg-0sp11v7) resolute; urgency=medium + + * Surface Pro 11 v7: non-rc 7.2.0 integration line. + + -- Leon Silcott Tue, 18 Aug 2026 00:00:00 +0100 + +linux-qcom-x1e (7.2-rc6-jg-0sp11v6) resolute; urgency=medium + + * Surface Pro 11 v6: wsa884x 2S supply + PA fault recovery + 4-ohm profile. + + -- Leon Silcott Mon, 17 Aug 2026 00:00:00 +0100 + +linux-qcom-x1e (7.2.0-jg-0) resolute; urgency=medium + + * phy: snps-eusb2: delay clk defaults until after power-up + * usb: dwc3-qcom: delay clk defaults until after power-up + * arm64: dts: qcom: x1p42100-ideapad-slim5x-oled: specify usb2-only clock for usb_1_ss2 + * arm64: dts: qcom: hamoa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies [Manivannan Sadhasivam ] + * arm64: dts: qcom: introduce Purwa variant of the Ideacentre Mini 01q8x10 + * arm64: dts: qcom: x1p42100-ideapad-slim5x-lcd: sync with working oled variant + * arm64: dts: qcom: x1p42100-ideapad-5-2in1: sync with working slim5x + * arm64: dts: qcom: x1p42100-thinkbook-16: sync with working slim5x + * rebase the whole stack to 7.2.0 + * arm64: dts: qcom: x126100-lenovo-ideapad-slim3: amend numbering of eUSB2 repeaters + * arm64: dts: qcom: x126100-lenovo-ideapad-slim3: introduce PWM backlight + * HACK: add "lenovo,thinkpad-t14s" as compatible to ensure install on Ubuntu Concept ISO + * arm64: dts: qcom: purwa-lenovo-ideacentre-mini-x: correct the firmware path and names + * arm64: dts: qcom: x1-el2: disable default iris node + * arm64: dts: qcom: lenovo-ideacentre-mini-01q8x10: disable Iris + * arm64: dts: qcom: x1p42100-ideapad-5-2in1: disable Iris + * arm64: dts: qcom: purwa-lenovo-ideacentre-mini-x: correct makefile + * arm64: dts: qcom: purwa-lenovo-ideacentre-mini-x: refine sound setup + + -- Jens Glathe Mon, 17 Aug 2026 20:16:16 +0200 + +linux-qcom-x1e (7.2-rc6-jg-0) resolute; urgency=medium + + * rebased the whole stack to v7.2-rc6 + * driver core: platform: / drm/msm: dp: Delay applying clock defaults whole seriws [https://lore.kernel.org/all/20250814-platform-delay-clk-defaults-v1-0-4aae5b33512f@linaro.org/] + + -- Jens Glathe Fri, 09 Aug 2026 10:20:00 +0200 + +linux-qcom-x1e (7.2-rc5-jg-0) resolute; urgency=medium + + * rebased the whole stack to v7.2-rc5 + * arm64: qcom: x1p-lenovo-laptops: adjust eUSB2 retimers, HDMI bridge + * drm/msm/dpu,dp,dsi: Drop sneaky dev_pm_opp_set_rate(0) whole series [https://lore.kernel.org/all/20260728-topic-dpu_power-v1-0-e7783b859a70@oss.qualcomm.com/] + * drm/msm/dp: use direct SDP flush for PSR [Lars Karlslund <8929787+lkarlslund@users.noreply.github.com>] + * drm/msm: Attach a driver to GMU whole series [https://lore.kernel.org/all/20260513-gmu-sync-state-fix-v1-0-6e33e6aa9b4f@oss.qualcomm.com/] + + -- Jens Glathe Thu, 30 Jul 2026 18:30:54 +0200 + +linux-qcom-x1e (7.2-rc4-jg-0) resolute; urgency=medium + + * rebased the whole stack to v7.2-rc4 + * kernel: amend strncpy() use with strscpy() + * apparmor: fix changed aa_audit_file() API call + * media: qcom: iris: fix variable mismatch + * media: venus: guard SC8280XP resources when Iris is enabled + * ubuntu: igh-ecat: replace strncpy() with strscpy() + * Ubuntu: fix ukify paths + + -- Jens Glathe Wed, 22 Jul 2026 12:14:24 +0200 + +linux-qcom-x1e (7.1.3-jg-2) resolute; urgency=medium + + * drm/msm/dpu: change BSOD colour for buffer underflow [Stephan Gerhold ] + * arm64: dts: qcom: x1: disable ps883x USB4 capapility (whole series) [https://lore.kernel.org/all/20260718-ps883x-disable-usb4-v1-0-cec86d0b909e@oldschoolsolutions.biz/] + * arm64: dts: qcom: x1-acer-swift-go-14: correct zap-shader file name + + -- Jens Glathe Sun, 19 Jul 2026 11:15:17 +0200 + +linux-qcom-x1e (7.1.3-jg-1) resolute; urgency=medium + + * removed mismatched camera-related patches from Bryan O'Donoghue + * arm64: dts: qcom: x1p42100-dell-latitude-5455: add Dell 5455 model + * arm64: dts: qcom: x1-asus-zenbook-a14: add dp sound DAIs + + -- Jens Glathe Fri, 10 Jul 2026 06:59:09 +0200 + +linux-qcom-x1e (7.1.3-jg-0) resolute; urgency=medium + + * new stack, based on: + - updated sre/thinkpad-t14s-x1e + - Ubuntu-Mainline daily config + - jg/ubuntu-qcom-x1e-oldconfig-7.1.y + + -- Jens Glathe Wed, 08 Jul 2026 16:40:57 +0200 + +linux-qcom-x1e (7.1.2-jg-3) resolute; urgency=medium + + * arm64: dts: qcom: x1p42100-ideapad-5-oled: adjust max-brightness usage + * arm64: dts: qcom: x1-lenovo-ideapad-slim3: disable EC node + + -- Jens Glathe Mon, 06 Jul 2026 21:57:15 +0200 + +linux-qcom-x1e (7.1.2-jg-2) resolute; urgency=medium + + * arm64: dts: qcom: x1-asus-vivobook-s15: add displayport DAIs + + -- Jens Glathe Mon, 06 Jul 2026 19:30:01 +0200 + +linux-qcom-x1e (7.1.2-jg-1) resolute; urgency=medium + + * usb: typec: ps883x: Return -EOPNOTSUPP for USB4 when qcom,disable-usb4 is set + * usb: typec: mux: ps883x: add a delay after writing config regs + * arm64: dts: qcom: x1-lenovo-thinkpad-t14s: disable ps883x USB4 capapility + * arm64: dts: qcom: x1e80100-dell-inspiron-14-plus-7441: hack the backlight + + -- Jens Glathe Sat, 04 Jul 2026 09:12:44 +0200 + +linux-qcom-x1e (7.1.2-jg-0) resolute; urgency=medium + + * rebased the whole stack to v7.1.2 + * arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: add Displayport DAIs + * drm/msm/dpu: Reassert core clock rate on runtime resume [Xilin Wu ] + + -- Jens Glathe Sun, 28 Jun 2026 19:33:51 +0200 + +linux-qcom-x1e (7.1.1-jg-1) resolute; urgency=medium + + * arm64: dts: qcom: x1p42100-hp-omnibook-5: DT for HP OmniBook 5 laptop [Jay Sim ] + * arm64: dts: qcom: x1p42100-ideapad-slim5x: Fix display brightness regression [olav-st ] + * drivers/platform: lenovo-t14s-ec: Add hwmon support for temperatures and fan speed [Daniel Lezcano ] + * arm64: dts: qcom: x1p42100-hp-omnibook-5: remove max-brightness value + + -- Jens Glathe Fri, 26 Jun 2026 16:34:27 +0200 + +linux-qcom-x1e (7.1.1-jg-0) resolute; urgency=medium + + * rebased the whole stack to v7.1.1 + + -- Jens Glathe Sun, 21 Jun 2026 11:41:34 +0200 + +linux-qcom-x1e (7.1-jg-1) resolute; urgency=medium + + * arm64: dts: qcom: x1-lenovo-ideapad-slim3: fix formatting + * arm64: dts: qcom: x1-lenovo-ideapad-5-2in1: set camera regulator to always on + * arm64: dts: qcom: x1-lenovo-ideapad-5-2in1: switch mic setup to T14s mapping (2 dmics + * drm/msm/dpu: Update catalog for X1E80100 display support [William Larson ] + * powercap: qcom: Add SPEL powercap driver [Manaf Meethalavalappu Pallikunhi ] + * arm64: dts: qcom: x1-lenovo-ideapad-slim5x: disable displayport-2-dai-link + + -- Jens Glathe Sun, 21 Jun 2026 08:33:05 +0200 + +linux-qcom-x1e (7.1-jg-0) resolute; urgency=medium + + * rebased the whole stack to v7.1 + + -- Jens Glathe Sun, 14 Jun 2026 20:53:54 +0200 + +linux-qcom-x1e (7.1-rc7-jg-0) resolute; urgency=medium + + * rebased the whole stack to v7.1-rc7 + * arm64: dts: qcom: x1-lenovo-ideapad-slim5x: re-configure backlight + + -- Jens Glathe Sun, 14 Jun 2026 19:49:07 +0200 + +linux-qcom-x1e (7.1-rc6-jg-3) resolute; urgency=medium + + * arm64: dts: qcom: x1-thinkbook-16: Keep PTN3222 supplies in retention during deep suspend + * arm64: dts: qcom: x1-lenovo-ideapad-5: Keep PTN3222 supplies in retention during deep suspend + + -- Jens Glathe Fri, 12 Jun 2026 20:32:59 +0200 + +linux-qcom-x1e (7.1-rc6-jg-2) resolute; urgency=medium + + * clk: implement sync_state support [Brian Masney ] - whole series https://lore.kernel.org/all/20260603-clk-sync-state-v1-0-457120eed200@redhat.com/ + * update config/annotations with android binder + + -- Jens Glathe Fri, 05 Jun 2026 18:10:00 +0200 + +linux-qcom-x1e (7.1-rc6-jg-1) resolute; urgency=medium + + * hid: Pen battery quirk for Surface Pro 12in [Harrison Vanderbyl ] + * arm64: dts: qcom: Add Microsoft Surface Pro 12in [Harrison Vanderbyl ] + * arm64: dts: qcom: x1p42100-microsoft-sp12in: remove previous sp12 dts + + -- Jens Glathe Thu, 04 Jun 2026 17:44:31 +0200 + +linux-qcom-x1e (7.1-rc6-jg-0) resolute; urgency=medium + + * rebased the whole stack to v7.1-rc6 + * drm/msm/dp: add missing drm_edid_connector_update() before add_modes on cached EDID + + -- Jens Glathe Tue, 02 Jun 2026 22:16:25 +0200 + +linux-qcom-x1e (7.1-rc5-jg-0) resolute; urgency=medium + + * rebased the whole stack to v7.1-rc5 + * arm64: dts: qcom: x1-asus-vivobook-s15: add 4-speaker 3-dp sound nodes + * arm64: dts: qcom: sc8280xp-blackrock: correct usb phy power supply + * arm64: dts: qcom: x1p4-asus-vivobook-s15: disable Iris + * arm64: dts: qcom: hamoa: Drop cluster_cl5 idle state from CPU clusters + * Revert "usb: typec: mux: avoid duplicated mux switches" + * drm/msm: force mode_changed when gamma_lut changes [Stephan Gerhold ] + * drm/msm/dpu: skip resource reallocation on color_mgmt_changed only [Stephan Gerhold ] + * usb: typec: ps883x: fix DP_STATE_D handling [Stephan Gerhold ] + * drm/msm/dp: add EDID re-read retry in msm_dp_panel_get_modes() + * kbuild: dtbinst: mark __dtbs_install as .NOTPARALLEL to avoid install -D race + * arm64: dts: qcom: idepad-slim3x: update pcie nodes to 7.0 syntax + * arm64: dts: qcom: x1p42100-lenovo-thinkbook-16: align eUSB2 repeaters + + -- Jens Glathe Mon, 01 Jun 2026 08:51:59 +0200 + +linux-qcom-x1e (7.1-rc4-jg-0) resolute; urgency=medium + + * rebased the whole stack to v7.1-rc4 + * arm64: dts: qcom: x1e001-devkit-jg: add variant from 6.19.y + + -- Jens Glathe Mon, 18 May 2026 19:39:08 +0200 + +linux-qcom-x1e (7.1-rc3-jg-2) resolute; urgency=medium + + * ASoC: qcom: q6asm-dai: fix error handling [Srinivas Kandagatla ] + * drm/msm/dp: Do not fail audio prepare when DP is inactive [Xilin Wu ] + * arm64: dts: qcom: idepad-slim5x: update from working ip5 2in1 + * arm64: dts: qcom: idepad-5-2in1: enable hdmi, fp-reader, dp sound + * arm64: dts: qcom: sc8280xp: correct usb phy power supply [Pengyu Luo ] + + -- Jens Glathe Mon, 18 May 2026 11:46:20 +0200 + +linux-qcom-x1e (7.1-rc3-jg-1) resolute; urgency=medium + + * arm64: dts: qcom: x1p42100-ideapad-slim5x: Fix display brightness regression [olav-st ] + * debian/rules: limit target dtbs_install to -j1 + * ASoC: qcom: q6apm-dai: Allocate an extra page for PCM buffers [Srinivas Kandagatla ] + * arm64: dts: qcom: x1: Add x1-el2-pas.dtso for PAS-managed remoteproc + * arm64: dts: qcom: idepad-5-2in1: remove backlight gpio + + -- Jens Glathe Thu, 14 May 2026 15:15:00 +0200 + +linux-qcom-x1e (7.1-rc3-jg-0) resolute; urgency=medium + + * complete rebuild onto v7.1-rc3 + * base: torvalds v7.1-rc + * add: sre branch for t14s on 7.0 + * add: qcom-x1e-7.0 + * add: jg/ubuntu-qcom-x1e + + -- Jens Glathe Mon, 11 May 2026 17:14:01 +0200 + +linux-qcom-x1e (7.0.0-22.22) questing; urgency=medium + + * x1e80100-lenovo-yoga-slim7x: fix RGB cam supply voltage fix + + -- Tobias Heider Tue, 24 Mar 2026 22:39:22 +0100 + +linux-qcom-x1e (7.0.0-20.20) questing; urgency=medium + + * Revert gpi-dma commit in sc8280x + + -- Tobias Heider Mon, 23 Mar 2026 19:44:55 +0100 + +linux-qcom-x1e (7.0.0-17.17) questing; urgency=medium + + * x1e80100-lenovo-yoga-slim7x: fix RGB cam supply voltage + + -- Tobias Heider Fri, 20 Mar 2026 23:49:55 +0100 + +linux-qcom-x1e (7.0.0-16.16) questing; urgency=medium + + * Rebase onto Ubuntu-7.0.0-10.10 + + -- Tobias Heider Fri, 20 Mar 2026 15:24:06 +0100 + +linux-qcom-x1e (7.0.0-15.15) questing; urgency=medium + + [ Jens Glathe ] + * firmware: qcom: scm: allow QSEECOM on ASUS Vivobook X1P42100 variant + + -- Tobias Heider Fri, 20 Mar 2026 11:43:40 +0100 + +linux-qcom-x1e (7.0.0-14.14) questing; urgency=medium + + * PCIe fix for all remaning DTBs: + - https://lore.kernel.org/linux-arm-msm/20260313094618.1361418-1-ziyue.zhang@oss.qualcomm.com/ + + -- Tobias Heider Thu, 19 Mar 2026 14:26:33 +0100 + +linux-qcom-x1e (7.0.0-13.13) questing; urgency=medium + + * Add x1p42100-hp-elitebook-6-g1q + * Add x1p42100-asus-vivobook-s15 + + -- Tobias Heider Wed, 18 Mar 2026 12:03:32 +0100 + +linux-qcom-x1e (7.0.0-12.12) questing; urgency=medium + + * Rebase qcom-x1e onto 7.0 + + -- Tobias Heider Tue, 17 Mar 2026 01:29:53 +0100 + +linux (7.0.0-7.7) resolute; urgency=medium + + * resolute/linux: 7.0.0-7.7 -proposed tracker (LP: #2143974) + + * unconfined profile denies userns_create for chromium based processes + (LP: #1990064) + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * Jellyfin Desktop Flatpak doesn't work with the current AppArmor profile + (LP: #2142956) + - SAUCE: apparmor5.0.0 [29/29]: apparmor: fix fine grained inet mediation + sock_file_perm + + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor5.0.0 [28/29]: apparmor: fix aa_label_sk_perm to check + for RULE_MEDIATES_NET + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/29]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [2/29]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [3/29]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [4/29]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [5/29]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [6/29]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [7/29]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [8/29]: apparmor: lift compatibility check out of + profile_af_perm + - SAUCE: apparmor5.0.0 [9/29]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [10/29]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [12/29]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [13/29]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [14/29]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [15/29]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [16/29]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [19/29]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [20/29]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [21/29]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [22/29]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [23/29]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [24/29]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [25/29]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [26/29]: apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [27/29]: apparmor: prevent profile->disconnected + double free in aa_free_profile + + * update apparmor and LSM stacking patch set (LP: #2028253) // Installation + of AppArmor on a 6.14 kernel produces error message "Illegal number: yes" + (LP: #2102680) + - SAUCE: apparmor5.0.0 [17/29]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [18/29]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [11/29]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + + * NPU utilization on amdxdna is missing (LP: #2143243) + - SAUCE: accel/amdxdna: Add IOCTL to retrieve realtime NPU power estimate + - SAUCE: accel/amdxdna: Support sensors for column utilization + - SAUCE: accel/amdxdna: Import AMD_PMF namespace + + * Adopting dark mode by default for OLED panel (LP: #2143203) + - SAUCE: drm/connector: Add a new 'panel_type' property + - SAUCE: drm/amd/display: Attach OLED property to eDP panels + + * Support AMD Image Signal Processing (ISP) unit V4.0 (LP: #2110092) + - SAUCE: media: platform: amd: Introduce amd isp4 capture driver + - SAUCE: media: platform: amd: low level support for isp4 firmware + - SAUCE: media: platform: amd: Add isp4 fw and hw interface + - SAUCE: media: platform: amd: isp4 subdev and firmware loading handling + added + - SAUCE: media: platform: amd: isp4 video node and buffers handling added + - SAUCE: Documentation: add documentation of AMD isp 4 driver + - SAUCE: media: platform: amd: isp4 debug fs logging and more descriptive + errors + - [Config] Enable VIDEO_AMD_ISP4_CAPTURE + + * Miscellaneous Ubuntu changes + - [Config] temporarily disable OBJTOOL_WERROR + + -- Paolo Pisati Thu, 12 Mar 2026 10:49:34 +0100 + +linux (7.0.0-6.6) resolute; urgency=medium + + * resolute/linux: 7.0.0-6.6 -proposed tracker (LP: #2143745) + + * Miscellaneous Ubuntu changes + - [Packaging] drop unstable suffix + + -- Paolo Pisati Mon, 09 Mar 2026 17:20:26 +0100 + +linux (7.0.0-5.5) resolute; urgency=medium + + * resolute/linux-unstable: 7.0.0-5.5 -proposed tracker (LP: #2143700) + + * Resolute real-time patchset: 7.0-rc1-rt1 (LP: #2143181) + - SAUCE: Reapply "serial: 8250: Switch to nbcon console" + - SAUCE: Reapply "serial: 8250: Revert "drop lockdep annotation from + serial8250_clear_IER()"" + - SAUCE: drm/i915: Use preempt_disable/enable_rt() where recommended + - SAUCE: drm/i915: Don't disable interrupts on PREEMPT_RT during atomic + updates + - SAUCE: drm/i915: Disable tracing points on PREEMPT_RT + - SAUCE: drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + + spin_lock() + - SAUCE: drm/i915: Drop the irqs_disabled() check + - SAUCE: drm/i915/guc: Consider also RCU depth in busy loop. + - SAUCE: drm/i915: Consider RCU read section as atomic. + - SAUCE: Revert "drm/i915: Depend on !PREEMPT_RT." + - SAUCE: sysfs: Add /sys/kernel/realtime entry + - Real-time patchset 7.0-rc1-rt1 + + * Miscellaneous Ubuntu changes + - [Config] rust toolchain version update + + -- Paolo Pisati Mon, 09 Mar 2026 08:10:31 +0100 + +linux-unstable (7.0.0-4.4) resolute; urgency=medium + + * resolute/linux-unstable: 7.0.0-4.4 -proposed tracker (LP: #2143123) + + * efi: Fix swapped arguments to bsearch() in efi_status_to_*() SAUCE patch + (LP: #2141276) + - SAUCE efi: Fix swapped arguments to bsearch() in efi_status_to_*() + + * Plucky preinstalled server fails to boot on rb3gen2 (LP: #2106681) // + Questing preinstalled server fails to boot on sa8775p boards + (LP: #2121347) + - [Config] move more qcom interconnect/pinctrl/gcc options to builtin + + * linux-tools: consider linking perf against LLVM (LP: #2138328) + - [Packaging] Add llvm-21-dev to build-depends for perf + + * Miscellaneous Ubuntu changes + - [Packaging] Add intel-speed-select to linux-tools + - [Packaging] remove stale debian/dkms-versions + - [Packaging] remove stale debian/dkms-versions scripting + + -- Paolo Pisati Wed, 04 Mar 2026 13:59:02 +0100 + +linux-unstable (7.0.0-3.3) resolute; urgency=medium + + * resolute/linux-unstable: 7.0.0-3.3 -proposed tracker (LP: #2143020) + + * Miscellaneous Ubuntu changes + - [Config] updateconfig after rebase to v7.0-rc2 + - [Config] switch to PREEMPT_LAZY + + -- Paolo Pisati Mon, 02 Mar 2026 09:26:45 +0100 + +linux-unstable (7.0.0-2.2) resolute; urgency=medium + + * resolute/linux-unstable: 7.0.0-2.2 -proposed tracker (LP: #2142764) + + -- Paolo Pisati Fri, 27 Feb 2026 10:25:35 +0100 + +linux-unstable (7.0.0-1.1) resolute; urgency=medium + + * resolute/linux-unstable: 7.0.0-1.1 -proposed tracker (LP: #2142402) + + * Miscellaneous Ubuntu changes + - [packaging] rename to linux-unstable + - [Config] updateconfig after rebase to v7.0-rc1 + - Update Changes.md + - [Packaging] add libbpf-dev to Build-Depends + - [Config] disable AMD_ISP4, FTBFS + - [Packaging] debian.master/dkms-versions -- temporarily remove zfs FTBFS + - [Packaging] debian.master/dkms-versions -- temporarily remove evdi FTBFS + - [Config] updateconfig after rebase to v7.0-rc1 + - [Config] update toolchain version + + -- Paolo Pisati Mon, 23 Feb 2026 08:32:17 +0100 + +linux-unstable (6.19.0-6.6) resolute; urgency=medium + + * resolute/linux: 6.19.0-6.6 -proposed tracker (LP: #2142114) + + * Resolute update: v6.19.2 upstream stable release (LP: #2142112) + - Revert "driver core: enforce device_lock for driver_match_device()" + - Linux 6.19.2 + + * Resolute update: v6.19.1 upstream stable release (LP: #2142111) + - io_uring/io-wq: add exit-on-idle state + - io_uring: allow io-wq workers to exit when unused + - smb: client: split cached_fid bitfields to avoid shared-byte RMW races + - ksmbd: fix infinite loop caused by next_smb2_rcv_hdr_off reset in error + paths + - ksmbd: add chann_lock to protect ksmbd_chann_list xarray + - smb: server: fix leak of active_num_conn in ksmbd_tcp_new_connection() + - smb: smbdirect: introduce smbdirect_socket.recv_io.credits.available + - smb: smbdirect: introduce smbdirect_socket.send_io.bcredits.* + - smb: server: make use of smbdirect_socket.recv_io.credits.available + - smb: server: let recv_done() queue a refill when the peer is low on + credits + - smb: server: make use of smbdirect_socket.send_io.bcredits + - smb: server: fix last send credit problem causing disconnects + - smb: server: let send_done handle a completion without IB_SEND_SIGNALED + - smb: client: make use of smbdirect_socket.recv_io.credits.available + - smb: client: let recv_done() queue a refill when the peer is low on + credits + - smb: client: let smbd_post_send() make use of request->wr + - smb: client: remove pointless sc->recv_io.credits.count rollback + - smb: client: remove pointless sc->send_io.pending handling in + smbd_post_send_iter() + - smb: client: port and use the wait_for_credits logic used by server + - smb: client: split out smbd_ib_post_send() + - smb: client: introduce and use smbd_{alloc, free}_send_io() + - smb: client: use smbdirect_send_batch processing + - smb: client: make use of smbdirect_socket.send_io.bcredits + - smb: client: fix last send credit problem causing disconnects + - smb: client: let smbd_post_send_negotiate_req() use smbd_post_send() + - smb: client: let send_done handle a completion without IB_SEND_SIGNALED + - driver core: enforce device_lock for driver_match_device() + - Bluetooth: btusb: Add USB ID 7392:e611 for Edimax EW-7611UXB + - ALSA: hda/conexant: Add quirk for HP ZBook Studio G4 + - crypto: iaa - Fix out-of-bounds index in find_empty_iaa_compression_mode + - crypto: octeontx - Fix length check to avoid truncation in + ucode_load_store + - crypto: omap - Allocate OMAP_CRYPTO_FORCE_COPY scatterlists correctly + - crypto: virtio - Add spinlock protection with virtqueue notification + - crypto: virtio - Remove duplicated virtqueue_kick in + virtio_crypto_skcipher_crypt_req + - nilfs2: Fix potential block overflow that cause system hang + - hfs: ensure sb->s_fs_info is always cleaned up + - wifi: rtw88: Fix alignment fault in rtw_core_enable_beacon() + - scsi: qla2xxx: Validate sp before freeing associated memory + - scsi: qla2xxx: Allow recovery for tape devices + - scsi: qla2xxx: Delay module unload while fabric scan in progress + - scsi: qla2xxx: Free sp in error path to fix system crash + - scsi: qla2xxx: Query FW again before proceeding with login + - sched/mmcid: Don't assume CID is CPU owned on mode switch + - bus: fsl-mc: fix use-after-free in driver_override_show() + - erofs: fix UAF issue for file-backed mounts w/ directio option + - xfs: fix UAF in xchk_btree_check_block_owner + - drm/exynos: vidi: use ctx->lock to protect struct vidi_context member + variables related to memory alloc/free + - PCI: endpoint: Avoid creating sub-groups asynchronously + - wifi: rtl8xxxu: fix slab-out-of-bounds in rtl8xxxu_sta_add + - Linux 6.19.1 + + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor: fix aa_label_sk_perm to check for RULE_MEDIATES_NET + + -- Timo Aaltonen Wed, 18 Feb 2026 14:31:48 +0200 + +linux (6.19.0-5.5) resolute; urgency=medium + + * resolute/linux: 6.19.0-5.5 -proposed tracker (LP: #2141736) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2026.02.09) + + * Blacklisted sbsa_gwdt module makes machines reboot (LP: #2138924) + - [Packaging] fix watchdog blacklist exceptions adding kmod extension + + * Miscellaneous Ubuntu changes + - [Packaging] debian/scripts/dkms-build--nvidia-N -- fix module.lds option + - [Packaging] fix a typo in Ubuntu.md + - [Config] updateconfig after rebase to v6.19-rc8 + - [Packaging] Drop changelog entries older than noble + + -- Timo Aaltonen Fri, 13 Feb 2026 19:04:04 +0200 + +linux (6.19.0-3.3) resolute; urgency=medium + + * resolute/linux: 6.19.0-3.3 -proposed tracker (LP: #2138935) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2026.01.12) + - [Packaging] update variants + + * [26.04] Please test secureboot and lock-down with 6.18 kernel (s390x) on + Resolute Raccoon (LP: #2131805) + - SAUCE: s390/boot/vmlinux.lds.S: Ensure bzImage ends with SecureBoot + trailer + + * unconfined profile denies userns_create for chromium based processes + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * update apparmor and LSM stacking patch set + - SAUCE: apparmor5.0.0 [1/53]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [2/53]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [3/53]: Stacking: Audit: Call only the first of the + audit rule hooks + - SAUCE: apparmor5.0.0 [4/53]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [5/53]: apparmor-next 7.0: apparmor: replace + sprintf with snprintf in aa_new_learning_profile + - SAUCE: apparmor5.0.0 [6/53]: apparmor-next 7.0: apparmor: Replace + sprintf/strcpy with scnprintf/strscpy in aa_policy_init + - SAUCE: apparmor5.0.0 [7/53]: apparmor-next 7.0: apparmor: Replace + deprecated strcpy in d_namespace_path + - SAUCE: apparmor5.0.0 [8/53]: apparmor-next 7.0: apparmor: fix NULL + pointer dereference in __unix_needs_revalidation + - SAUCE: apparmor5.0.0 [9/53]: apparmor-next 7.0: apparmor: fix NULL sock + in aa_sock_file_perm + - SAUCE: apparmor5.0.0 [10/53]: apparmor-next 7.0: apparmor: Replace + deprecated strcpy with memcpy in gen_symlink_name + - SAUCE: apparmor5.0.0 [11/53]: apparmor-next 7.0: AppArmor: Allow + apparmor to handle unaligned dfa tables + - SAUCE: apparmor5.0.0 [12/53]: apparmor-next 7.0: apparmor: Fix & + Optimize table creation from possibly unaligned memory + - SAUCE: apparmor5.0.0 [13/53]: apparmor-next 7.0: apparmor: make str + table more generic and be able to have multiple entries + - SAUCE: apparmor5.0.0 [14/53]: apparmor-next 7.0: apparmor: add support + loading per permission tagging + - SAUCE: apparmor5.0.0 [15/53]: apparmor-next 7.0: aoparmor: userns: Add + support for execpath in userns + - SAUCE: apparmor5.0.0 [16/53]: apparmor-next 7.0: apparmor: fix boolean + argument in apparmor_mmap_file + - SAUCE: apparmor5.0.0 [17/53]: apparmor-next 7.0: apparmor: drop + in_atomic flag in common_mmap, and common_file_perm + - SAUCE: apparmor5.0.0 [18/53]: apparmor-next 7.0: apparmor: account for + in_atomic removal in common_file_perm + - SAUCE: apparmor5.0.0 [19/53]: apparmor-next 7.0: apparmor: return + -ENOMEM in unpack_perms_table upon alloc failure + - SAUCE: apparmor5.0.0 [20/53]: apparmor-next 7.0: apparmor: guard against + free routines being called with a NULL + - SAUCE: apparmor5.0.0 [21/53]: apparmor-next 7.0: apparmor: move check + for aa_null file to cover all cases + - SAUCE: apparmor5.0.0 [22/53]: apparmor-next 7.0: apparmor: fix label and + profile debug macros + - SAUCE: apparmor5.0.0 [23/53]: apparmor-next 7.0: apparmor: + refactor/cleanup cred helper fns. + - SAUCE: apparmor5.0.0 [24/53]: apparmor-next 7.0: apparmor: fix rlimit + for posix cpu timers + - SAUCE: apparmor5.0.0 [25/53]: apparmor-next 7.0: apparmor: fix fast path + cache check for unix sockets + - SAUCE: apparmor5.0.0 [26/53]: apparmor-next 7.0: apparmor: remove + apply_modes_to_perms from label_match + - SAUCE: apparmor5.0.0 [27/53]: apparmor-next 7.0: apparmor: make + label_match return a consistent value + - SAUCE: apparmor5.0.0 [28/53]: apparmor-next 7.0: apparmor: split + xxx_in_ns into its two separate semantic use cases + - SAUCE: apparmor5.0.0 [29/53]: apparmor-next 7.0: apparmor: avoid per-cpu + hold underflow in aa_get_buffer + - SAUCE: apparmor5.0.0 [30/53]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [31/53]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [32/53]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [33/53]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [34/53]: apparmor: lift compatibility check out of + profile_af_perm + - SAUCE: apparmor5.0.0 [35/53]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [36/53]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [37/53]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + - SAUCE: apparmor5.0.0 [38/53]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [39/53]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [40/53]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [41/53]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [42/53]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [43/53]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [44/53]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + - SAUCE: apparmor5.0.0 [45/53]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [46/53]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [47/53]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [48/53]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [49/53]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [50/53]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [51/53]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [52/53]: apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [53/53]: apparmor: prevent profile->disconnected + double free in aa_free_profile + + * Blacklisted sbsa_gwdt module makes machines reboot (LP: #2138924) + - [Packaging] remove sbsa_gwdt from watchdog blacklist + + * Integrate IgH EtherCAT master (LP: #2138621) + - SAUCE: ubuntu/igh-ecat: Import IgH EtherCAT master + - SAUCE: igh-ecat: Plug IgH EtherCAT master into Kbuild + - SAUCE: igh-ecat: Fix build failure with kernel 6.19 + - [Config] Enable IgH EtherCAT master + + * TBT call trace while connecting TBT4 monitor on TBT5 port (LP: #2137613) + - SAUCE: thunderbolt: log path activation failures without WARN backtraces + + * Boot up hang with ucsi call trace while plug power cord or device on tbt5 + port (LP: #2127764) + - SAUCE: usb: typec: ucsi: Fix workqueue destruction race during connector + cleanup + + * Ease the sysfs call trace which comes from ucsi firmware issue + (LP: #2127960) + - usb: typec: ucsi: Detect and skip duplicate altmodes from buggy firmware + - usb: typec: ucsi: Add duplicate detection to nvidia registration path + - usb: typec: ucsi: yoga_c630: Remove redundant duplicate altmode handling + + * Enable RTL ASPM for more new Dell platforms (LP: #2133144) + - SAUCE: r8169: Add more Dell platforms to enable ASPM + + * Enable RTL ASPM for new Dell platforms (LP: #2121200) + - SAUCE: r8169: enable ASPM on all new Dell platforms + + * Miscellaneous Ubuntu changes + - [Packaging] Bump clang build-dep to match the current default. + - [Config] updateconfig after rebase to v6.19-rc6 + - [Packaging] update Ubuntu.md + + -- Timo Aaltonen Fri, 23 Jan 2026 17:50:01 +0200 + +linux-unstable (6.19.0-1.1) resolute; urgency=medium + + * resolute/linux-unstable: 6.19.0-1.1 -proposed tracker (LP: #2138287) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.10.20) + - [Packaging] update variants + + * Miscellaneous Ubuntu changes + - SAUCE: (lockdown) efi,lockdown: fix kernel lockdown on Secure Boot + - [Config] updateconfigs following v6.19-rc4 rebase + - SAUCE: aaeon: The modules need to import ASUS_WMI now + - Update Changes.md + - SAUCE: arm64: dts: qcom: x1-acer-swift-14: Fix includes + - [Packaging] Drop failing dkms packages + + -- Timo Aaltonen Tue, 13 Jan 2026 15:36:30 +0200 + +linux-unstable (6.19.0-0.0) resolute; urgency=medium + + * Dummy entry. + + -- Timo Aaltonen Wed, 17 Dec 2025 14:08:41 +0200 + +linux-unstable (6.18.0-6.6) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-6.6 -proposed tracker (LP: #2133502) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.10.20) + + * Miscellaneous Ubuntu changes + - Update dropped.txt + - [Packaging] debian.master/dkms-versions: Drop failing dkms packages + - rename dropped.txt to Changes.md + + -- Paolo Pisati Mon, 01 Dec 2025 14:52:34 +0100 + +linux-unstable (6.18.0-5.5) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-5.5 -proposed tracker (LP: #2131673) + + * Re-enable INTEL_SKL_INT3472 for kernels >= 6.16 for Intel IPU camera + (LP: #2128792) + - Revert "UBUNTU: [Config] FTBFS: disable INTEL_SKL_INT3472" + - Revert "UBUNTU: SAUCE: platform/x86: int3472: Add handshake GPIO + function" + + * i40e driver is triggering VF resets on every link state change + (LP: #2130552) + - i40e: avoid redundant VF link state updates + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.18-rc6 rebase + + -- Paolo Pisati Tue, 18 Nov 2025 11:23:48 +0100 + +linux-unstable (6.18.0-4.4) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-4.4 -proposed tracker (LP: #2131211) + + * CAP_PERFMON insufficient to get perf data (LP: #2131046) + - SAUCE: perf/core: Allow CAP_PERFMON for paranoid level 4 + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.18-rc5 rebase + + -- Paolo Pisati Thu, 13 Nov 2025 12:55:49 +0100 + +linux-unstable (6.18.0-3.3) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-3.3 -proposed tracker (LP: #2129919) + + * [26.04 FEAT] Set Architecture Level (ALS) to z15 (LP: #2126577) + - [Config] Raise the architectural level set for s390x to z15 + + * Miscellaneous Ubuntu changes + - [Config]: Enable CONFIG_CRYPTO_BENCHMARK + - [Config] updateconfigs after v6.18-rc3 rebase + + -- Paolo Pisati Mon, 27 Oct 2025 11:07:35 +0100 + +linux-unstable (6.18.0-2.2) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-2.2 -proposed tracker (LP: #2129552) + + * Miscellaneous Ubuntu changes + - [Config] update rustc version + + -- Paolo Pisati Wed, 22 Oct 2025 15:42:17 +0200 + +linux-unstable (6.18.0-1.1) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-1.1 -proposed tracker (LP: #2129038) + + * Packaging resync (LP: #1786013) + - [Packaging] update Ubuntu.md + + * Miscellaneous Ubuntu changes + - [Packaging] Rename to linux-unstable and move to 6.18 + - [Config] updateconfigs following v6.18-rc1 rebase + - [Config] apparmor: remove SECURITY_APPARMOR_RESTRICT_USERNS + - [Packaging] debian.master/dkms-versions: Drop failing dkms packages + - [Config] updateconfigs following v6.18-rc2 rebase + - move to resolute + + * Miscellaneous upstream changes + - Revert "audit: fix skb leak when audit rate limit is exceeded" + - Revert "audit: init ab->skb_list earlier in audit_buffer_alloc()" + - Revert "audit: add record for multiple object contexts" + - Revert "audit: add record for multiple task security contexts" + - Revert "lsm: security_lsmblob_to_secctx module selection" + - audit: fix skb leak when audit rate limit is exceeded + + -- Paolo Pisati Tue, 21 Oct 2025 16:26:01 +0200 + +linux-unstable (6.18.0-0.0) resolute; urgency=medium + + * questing/linux: 6.17.0-6.6 -proposed tracker (LP: #2126040) + + * Questing update: v6.17.1 upstream stable release (LP: #2126948) + - blk-mq: fix blk_mq_tags double free while nr_requests grown + - gcc-plugins: Remove TODO_verify_il for GCC >= 16 + - scsi: target: target_core_configfs: Add length check to avoid buffer + overflow + - ALSA: usb-audio: fix race condition to UAF in snd_usbmidi_free + - wifi: rtw89: fix use-after-free in rtw89_core_tx_kick_off_and_wait() + - media: b2c2: Fix use-after-free causing by irq_check_work in + flexcop_pci_remove + - media: i2c: tc358743: Fix use-after-free bugs caused by orphan timer in + probe + - media: tuner: xc5000: Fix use-after-free in xc5000_release + - media: rc: fix races with imon_disconnect() + - media: uvcvideo: Mark invalid entities with id UVC_INVALID_ENTITY_ID + - mm: swap: check for stable address space before operating on the VMA + - wifi: ath11k: fix NULL dereference in ath11k_qmi_m3_load() + - media: iris: Fix memory leak by freeing untracked persist buffer + - media: stm32-csi: Fix dereference before NULL check + - ASoC: qcom: audioreach: fix potential null pointer dereference + - Linux 6.17.1 + + * RISC-V kernel config is out of sync with other archs (LP: #1981437) + - [Config] riscv64: Update EFI_SBAT_FILE + - [Config] riscv64: Enable EFI_ZBOOT + - [Config] riscv64: Disable support for non-RVA23 SoCs + - [Config] riscv64: Disable RISCV_ISA_FALLBACK + - [Config] riscv64: Sync config with other architectures + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs after rebase to 6.17 + + -- Timo Aaltonen Tue, 07 Oct 2025 14:15:18 +0300 + +linux (6.17.0-5.5) questing; urgency=medium + + * questing/linux: 6.17.0-5.5 -proposed tracker (LP: #2125319) + + * Packaging resync (LP: #1786013) + - [Packaging] resync git-ubuntu-log + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.09.22) + + * [SRU] Failed to create source package: Unmet build dependencies: + bpftool:native (LP: #2122310) + - [Packaging] fix build profile spec for bpftool + + * UBUNTU: fan: fail to check kmalloc() return could cause a NULL pointer + dereference (LP: #2125053) + - SAUCE: fan: vxlan: check memory allocation for map + + * iproute2 breaking netplan DEP-8 tests in Questing, unexpected "fan-map" in + JSON output (LP: #2124257) + - SAUCE: fan: don't enforce a specific enum value for IFLA_VXLAN_FAN_MAP + + * memory leaks when configuring a small rate limit in audit (LP: #2122554) + - SAUCE: audit: fix skb leak when audit rate limit is exceeded + + * Support AMD Image Signal Processing (ISP) unit V4.0 (LP: #2110092) + - SAUCE: media: platform: amd: Introduce amd isp4 capture driver + - SAUCE: media: platform: amd: low level support for isp4 firmware + - SAUCE: media: platform: amd: Add isp4 fw and hw interface + - SAUCE: media: platform: amd: isp4 subdev and firmware loading handling + added + - SAUCE: media: platform: amd: isp4 video node and buffers handling added + - SAUCE: media: platform: amd: isp4 debug fs logging and more descriptive + errors + - SAUCE: Documentation: add documentation of AMD isp 4 driver + - [Config] Enable AMD_ISP4 + + * 25.10 Snapdragon X Elite: Sync concept kernel changes (LP: #2121477) + - phy: qcom: qmp-combo: Rename 'mode' to 'phy_mode' + - phy: qcom: qmp-combo: store DP phy power state + - phy: qcom: qmp-combo: introduce QMPPHY_MODE + - phy: qcom: qmp-combo: register a typec mux to change the QMPPHY_MODE + - arm64: dts: qcom: x1e80100-crd: Add USB multiport fingerprint reader + - dt-bindings: arm: qcom: Add Dell Latitude 7455 + - dt-bindings: display: panel: samsung,atna40cu11: document ATNA40CU11 + - dt-bindings: display: panel: samsung,atna40ct06: document ATNA40CT06 + - drm/panel-edp: Add BOE NV140WUM-N64 + - arm64: dts: qcom: x1-crd: Enable HBR3 on external DPs + - SAUCE: drm/dp: drm_edp_backlight_set_level: do not always send 3-byte + commands + - SAUCE: drm/edp-panel: Add touchscreen panel used by Lenovo X13s + - SAUCE: net: qrtr: mhi: synchronize qrtr and mhi preparation + - SAUCE: arm64: dts: qcom: x1e78100-t14s-oled: add eDP panel + - SAUCE: wip: arm64: dts: qcom: x1e80100-crd: Add WiFi/BT pwrseq + - SAUCE: wip: arm64: dts: qcom: x1e78100-t14s: enable bluetooth + - SAUCE: drm/dp: clamp PWM bit count to advertised MIN and MAX + capabilities + - SAUCE: arm64: dts: qcom: x1e80100-pmics: Disable pm8010 by default + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: Add Left/Right + Speakers and Tweeter + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: enable MICs LDO + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: Mark audio channels + as left-right swapped + - SAUCE: arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13: Set up 4-lane DP + - SAUCE: dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document default + phy mode + - SAUCE: phy: qcom: qmp-combo: get default qmpphy_mode from DT + - SAUCE: arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: add HDMI nodes + - SAUCE: dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Reference usb- + switch.yaml to allow mode-switch + - SAUCE: dt-bindings: arm: qcom: Add Asus Zenbook A14 UX3407QA LCD/OLED + variants + - SAUCE: arm64: dts: qcom: Rework X1-based Asus Zenbook A14's displays + - SAUCE: arm64: dts: qcom: x1e80100-asus-zenbook-a14: Enable WiFi, + Bluetooth + - SAUCE: arm64: dts: qcom: Add support for Dell Inspiron 7441 / Latitude + 7455 + - SAUCE: firmware: qcom: scm: Allow QSEECOM on Dell Inspiron 7441 / + Latitude 7455 + - SAUCE: dt-bindings: arm: qcom: Add Acer Swift 14 AI + - SAUCE: arm64: dts: qcom: x1-acer-swift-14: Add support for Acer Swift 14 + - SAUCE: arm64: dts: qcom: x1e80100: allow mode-switch events to reach the + QMP Combo PHYs + - SAUCE: arm64: dts: qcom: x1e80100: move dp0/1/2 data-lanes to SoC dtsi + - SAUCE: arm64: dts: qcom: x1e80100: Set up 4-lane DP + - SAUCE: arm64: dts: qcom: x1e80100: move remaining dp0/1/2 data-lanes to + SoC dtsi + - Revert "UBUNTU: SAUCE: Change: cracking sound fix" + + * UBSAN: shift-out-of-bounds in drivers/edac/skx_common.c:452:16 + (LP: #2119713) + - EDAC/i10nm: Skip DIMM enumeration on a disabled memory controller + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs for v6.17-rc6 rebase + + -- Timo Aaltonen Mon, 22 Sep 2025 10:33:58 +0300 + +linux (6.17.0-4.4) questing; urgency=medium + + * questing/linux: 6.17.0-4.4 -proposed tracker (LP: #2122321) + + * [SRU] Do not instantiate SPD5118 sensors on i801 SMBus controllers + (LP: #2114963) + - SAUCE: i2c: i801: Do not instantiate spd5118 under SPD Write Disable + + * initramfs-tools: autopkgtest fails on arm64 with Possible missing firmware + /lib/firmware/apple/dfrmtfw-*.bin for built-in driver apple_z2 + (LP: #2115758) + - [Config] Set TOUCHSCREEN_APPLE_Z2=m (arm64) + + * Support TDX host in questing (LP: #2121873) + - SAUCE: x86/kexec: Consolidate relocate_kernel() function parameters + - SAUCE: x86/sme: Use percpu boolean to control WBINVD during kexec + - SAUCE: x86/virt/tdx: Mark memory cache state incoherent when making + SEAMCALL + - SAUCE: x86/kexec: Disable kexec/kdump on platforms with TDX partial + write erratum + - SAUCE: x86/virt/tdx: Remove the !KEXEC_CORE dependency + - SAUCE: x86/virt/tdx: Update the kexec section in the TDX documentation + - SAUCE: KVM: TDX: Explicitly do WBINVD when no more TDX SEAMCALLs + - [Config] enable TDX host support + + * minimal kernel lacks modules for blk disk in arm64 openstack environments + where config_drive is required (LP: #2118499) + - [Config] Enable SYM53C8XX_2 on arm64 + + * Miscellaneous Ubuntu changes + - [Config] Re-enable Rust support, and make sure it doesn't get disabled + by accident + - [Config] updateconfigs for v6.17-rc5 rebase + + -- Timo Aaltonen Mon, 08 Sep 2025 17:10:38 +0300 + +linux (6.17.0-3.3) questing; urgency=medium + + * questing/linux: 6.17.0-3.3 -proposed tracker (LP: #2121512) + + * Enable Xilinx PS UART configs (LP: #2121337) + - [Config] Enable Xilinx PS UART configs + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.08.25) + + * Plucky/Questing fails to boot on (older) Macs (LP: #2105402) + - SAUCE: hack: efi/libstub: enable t14s boot failure hack only on arm64 + + * Miscellaneous Ubuntu changes + - [Packaging] Fix linux-modules Description, add dependency on wireless- + regdb from old -extra + - [Packaging] Fix arch list for bpftool build-dep + + -- Timo Aaltonen Thu, 28 Aug 2025 10:37:03 +0300 + +linux (6.17.0-2.2) questing; urgency=medium + + * questing/linux: 6.17.0-2.2 -proposed tracker (LP: #2121374) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.08.25) + + * enable Mediatek media platform drivers on arm64 (LP: #2116138) + - [Config] enable mediatek media platform drivers + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/38]: Stacking: Audit: Create audit_stamp + structure + - SAUCE: apparmor5.0.0 [2/38]: Stacking: Audit: Allow multiple records in + an audit_buffer + - SAUCE: apparmor5.0.0 [3/38]: Stacking: LSM: security_lsmblob_to_secctx + module selection + - SAUCE: apparmor5.0.0 [4/38]: Stacking: Audit: Add record for multiple + task security contexts + - SAUCE: apparmor5.0.0 [5/38]: Stacking: Audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor5.0.0 [6/38]: Stacking: Audit: Add record for multiple + object contexts + - SAUCE: apparmor5.0.0 [7/38]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [8/38]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [9/38]: Stacking: Audit: Call only the first of the + audit rule hooks + - SAUCE: apparmor5.0.0 [10/38]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [11/38]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [12/38]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [13/38]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [14/38]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [15/38]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [16/38]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [18/38]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [19/38]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [20/38]: aoparmor: userns: Add support for execpath + in userns + - SAUCE: apparmor5.0.0 [21/38]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [22/38]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [23/38]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [26/38]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [27/38]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [28/38]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [29/38]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [30/38]: apparmor: add AA_DEBUG_PROFILE to have + debug on profiles with flag set + - SAUCE: apparmor5.0.0 [31/38]: apparmor: make str table more generic and + be able to have multiple entries + - SAUCE: apparmor5.0.0 [32/38]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [33/38]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [34/38]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [35/38]: UBUNTU: SAUCE: apparmor5.0.0 [35/38]: + apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [36/38]: apparmor: mmap_file() doesn't need to be + called atomically + - SAUCE: apparmor5.0.0 [37/38]: apparmor: guard against free routines + being called with a NULL + - SAUCE: apparmor5.0.0 [38/38]: apparmor: prevent profile->disconnected + double free in aa_free_profile + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * Installation of AppArmor on a 6.14 kernel produces error message "Illegal + number: yes" (LP: #2102680) + - SAUCE: apparmor5.0.0 [24/38]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [25/38]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [17/38]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + + * nvme no longer detected on boot after upgrade to 6.8.0-60 (LP: #2111521) + - SAUCE: PCI: Disable RRS polling for Intel SSDPE2KX020T8 nvme + + * Miscellaneous Ubuntu changes + - [Packaging] Use host bpftool if doing cross-compiling + - [Packaging] Rename to linux + - [Packaging] d/t/ubuntu-regression-suite: use https to clone + - [Packaging] d/t/control: add snapd and fuse-overlayfs dependencies + - [Packaging] Drop/update some dkms packages. + + -- Timo Aaltonen Tue, 26 Aug 2025 17:15:12 +0300 + +linux-unstable (6.17.0-1.1) questing; urgency=medium + + * questing/linux-unstable: 6.17.0-1.1 -proposed tracker (LP: #2121054) + + * Enable CONFIG_IPV6_OPTIMISTIC_DAD (LP: #1728366) + - [Config] Enable CONFIG_IPV6_OPTIMISTIC_DAD + + * No IP Address assigned after hot-plugging Ethernet cable on HP Platform + (LP: #2115393) + - Revert "e1000e: change k1 configuration on MTP and later platforms" + + * sources list generation using dwarfdump takes up to 0.5hr in build process + (LP: #2104911) + - [Packaging] Don't generate list of source files + + * Miscellaneous Ubuntu changes + - [Config] updateconfig following rebase to v6.17-rc2 + - [Packaging] Renane to linux-unstable + - SAUCE: gpio: aaeon: use new GPIO line value setter callbacks + - [Packaging] debian.master/dkms-versions: Drop failing dkms packages + - [Packaging] Don't suggest linux-modules-extra + + -- Timo Aaltonen Thu, 21 Aug 2025 11:22:12 +0300 + +linux-unstable (6.17.0-0.0) questing; urgency=medium + + * dummy entry + + -- Timo Aaltonen Mon, 18 Aug 2025 18:27:35 +0300 + +linux (6.16.0-16.16) questing; urgency=medium + + * questing/linux: 6.16.0-16.16 -proposed tracker (LP: #2120720) + + -- Paolo Pisati Sat, 16 Aug 2025 17:31:00 +0200 + +linux (6.16.0-14.14) questing; urgency=medium + + * questing/linux: 6.16.0-14.14 -proposed tracker (LP: #2120657) + + * BPF header file in wrong location (LP: #2118965) + - [Packaging] Install bpf header to correct location + + * enlarge the number of the serial port for sh-sci serial driver + (LP: #2116140) + - [Config] enlarge CONFIG_SERIAL_SH_SCI_NR_UARTS + + * Ubuntu 24.04+ arm64: screen resolution fixed to 1024x768 with last kernel + update (LP: #2115068) + - [Config] Replace FB_HYPERV with DRM_HYPERV + + * Miscellaneous Ubuntu changes + - [Packaging] move to unversioned gcc by default + - [Config] bump toolchain version to gcc-15 + + -- Paolo Pisati Fri, 15 Aug 2025 08:24:39 +0200 + +linux (6.16.0-13.13) questing; urgency=medium + + * questing/linux: 6.16.0-13.13 -proposed tracker (LP: #2119951) + + * Miscellaneous Ubuntu changes + - [Packaging] debian.master/dkms-versions -- remove ipu6 since it's + upstream + + -- Paolo Pisati Thu, 07 Aug 2025 16:32:32 +0200 + +linux (6.16.0-12.12) questing; urgency=medium + + * questing/linux: 6.16.0-12.12 -proposed tracker (LP: #2119711) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.07.28) + - [Packaging] resync git-ubuntu-log + - [Packaging] update variants + - [Packaging] update annotations scripts + + -- Paolo Pisati Thu, 07 Aug 2025 09:59:27 +0200 + +linux (6.16.0-11.11) questing; urgency=medium + + * questing/linux: 6.16.0-11.11 -proposed tracker (LP: #2119360) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/93]: Stacking: Audit: Create audit_stamp + structure + - SAUCE: apparmor5.0.0 [2/93]: Stacking: Audit: Allow multiple records in + an audit_buffer + - SAUCE: apparmor5.0.0 [3/93]: Stacking: LSM: security_lsmblob_to_secctx + module selection + - SAUCE: apparmor5.0.0 [4/93]: Stacking: Audit: Add record for multiple + task security contexts + - SAUCE: apparmor5.0.0 [5/93]: Stacking: Audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor5.0.0 [6/93]: Stacking: Audit: Add record for multiple + object contexts + - SAUCE: apparmor5.0.0 [7/93]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [8/93]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [9/93]: Stacking: Audit: Call only the first of the + audit rule hooks + - SAUCE: apparmor5.0.0 [10/93]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [11/93]: 6.17 apparmor-next: apparmor: Use + str_yes_no() helper function + - SAUCE: apparmor5.0.0 [12/93]: 6.17 apparmor-next: apparmor: Improve + debug print infrastructure + - SAUCE: apparmor5.0.0 [13/93]: 6.17 apparmor-next: apparmor: cleanup: + attachment perm lookup to use lookup_perms() + - SAUCE: apparmor5.0.0 [14/93]: 6.17 apparmor-next: apparmor: remove + redundant unconfined check. + - SAUCE: apparmor5.0.0 [15/93]: 6.17 apparmor-next: apparmor: switch + signal mediation to use RULE_MEDIATES + - SAUCE: apparmor5.0.0 [16/93]: 6.17 apparmor-next: apparmor: ensure + labels with more than one entry have correct flags + - SAUCE: apparmor5.0.0 [17/93]: 6.17 apparmor-next: apparmor: remove + explicit restriction that unconfined cannot use change_hat + - SAUCE: apparmor5.0.0 [18/93]: 6.17 apparmor-next: apparmor: cleanup: + refactor file_perm() to doc semantics of some checks + - SAUCE: apparmor5.0.0 [19/93]: 6.17 apparmor-next: apparmor: carry + mediation check on label + - SAUCE: apparmor5.0.0 [20/93]: 6.17 apparmor-next: apparmor: add + additional flags to extended permission. + - SAUCE: apparmor5.0.0 [21/93]: 6.17 apparmor-next: apparmor: add support + for profiles to define the kill signal + - SAUCE: apparmor5.0.0 [22/93]: 6.17 apparmor-next: apparmor: fix + x_table_lookup when stacking is not the first entry + - SAUCE: apparmor5.0.0 [23/93]: 6.17 apparmor-next: apparmor: add ability + to mediate caps with policy state machine + - SAUCE: apparmor5.0.0 [24/93]: 6.17 apparmor-next: apparmor: remove + af_select macro + - SAUCE: apparmor5.0.0 [25/93]: 6.17 apparmor-next: apparmor: lift kernel + socket check out of critical section + - SAUCE: apparmor5.0.0 [26/93]: 6.17 apparmor-next: apparmor: in + preparation for finer networking rules rework match_prot + - SAUCE: apparmor5.0.0 [27/93]: 6.17 apparmor-next: apparmor: add fine + grained af_unix mediation + - SAUCE: apparmor5.0.0 [28/93]: 6.17 apparmor-next: apparmor: gate make + fine grained unix mediation behind v9 abi + - SAUCE: apparmor5.0.0 [29/93]: 6.17 apparmor-next: apparmor: fix dbus + permission queries to v9 ABI + - SAUCE: apparmor5.0.0 [30/93]: 6.17 apparmor-next: apparmor: Fix checking + address of an array in accum_label_info() + - SAUCE: apparmor5.0.0 [31/93]: 6.17 apparmor-next: apparmor: Modify + mismatched function name + - SAUCE: apparmor5.0.0 [32/93]: 6.17 apparmor-next: apparmor: Modify + mismatched function name + - SAUCE: apparmor5.0.0 [33/93]: 6.17 apparmor-next: apparmor: fix typos + and spelling errors + - SAUCE: apparmor5.0.0 [34/93]: 6.17 apparmor-next: apparmor: use the + condition in AA_BUG_FMT even with debug disabled + - SAUCE: apparmor5.0.0 [35/93]: 6.17 apparmor-next: apparmor: Remove + unused variable 'sock' in __file_sock_perm() + - SAUCE: apparmor5.0.0 [68/93]: Revert "6.17 apparmor-next: apparmor: fix + dbus permission queries to v9 ABI" + - SAUCE: apparmor5.0.0 [69/93]: Revert "6.17 apparmor-next: apparmor: gate + make fine grained unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [70/93]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [71/93]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [72/93]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [73/93]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [75/93]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [76/93]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [80/93]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [83/93]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [84/93]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [85/93]: apparmor: prompt: enable userspace upcall + for mediation + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * Installation of AppArmor on a 6.14 kernel produces error message "Illegal + number: yes" (LP: #2102680) + - SAUCE: apparmor5.0.0 [81/93]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [82/93]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [74/93]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor5.0.0 [36/93]: 6.17 apparmor-next: security/apparmor: use + kfree_sensitive() in unpack_secmark() + - SAUCE: apparmor5.0.0 [37/93]: 6.17 apparmor-next: apparmor: Fix + incorrect profile->signal range check + - SAUCE: apparmor5.0.0 [38/93]: 6.17 apparmor-next: apparmor: fix some + kernel-doc issues in header files + - SAUCE: apparmor5.0.0 [39/93]: 6.17 apparmor-next: apparmor: ensure + WB_HISTORY_SIZE value is a power of 2 + - SAUCE: apparmor5.0.0 [40/93]: 6.17 apparmor-next: apparmor: fix loop + detection used in conflicting attachment resolution + - SAUCE: apparmor5.0.0 [41/93]: 6.17 apparmor-next: apparmor: make all + generated string array headers const char *const + - SAUCE: apparmor5.0.0 [42/93]: 6.17 apparmor-next: apparmor: force audit + on unconfined exec if info is set by find_attach + - SAUCE: apparmor5.0.0 [43/93]: 6.17 apparmor-next: apparmor: move the + "conflicting profile attachments" infostr to a const declaration + - SAUCE: apparmor5.0.0 [44/93]: 6.17 apparmor-next: apparmor: include + conflicting attachment info for confined ix/ux fallback + - SAUCE: apparmor5.0.0 [45/93]: 6.17 apparmor-next: apparmor: force + auditing of conflicting attachment execs from confined + - SAUCE: apparmor5.0.0 [46/93]: 6.17 apparmor-next: apparmor: make + debug_values_table static + - SAUCE: apparmor5.0.0 [47/93]: 6.17 apparmor-next: apparmor: Document + that label must be last member in struct aa_profile + - SAUCE: apparmor5.0.0 [48/93]: 6.17 apparmor-next: apparmor: mitigate + parser generating large xtables + - SAUCE: apparmor5.0.0 [49/93]: 6.17 apparmor-next: apparmor: make + __begin_current_label_crit_section() indicate whether put is needed + - SAUCE: apparmor5.0.0 [50/93]: 6.17 apparmor-next: apparmor: update + kernel doc comments for xxx_label_crit_section + - SAUCE: apparmor5.0.0 [51/93]: 6.17 apparmor-next: apparmor: Remove use + of the double lock + - SAUCE: apparmor5.0.0 [52/93]: 6.17 apparmor-next: apparmor: fix af_unix + auditing to include all address information + - SAUCE: apparmor5.0.0 [53/93]: 6.17 apparmor-next: apparmor: fix + AA_DEBUG_LABEL() + - SAUCE: apparmor5.0.0 [54/93]: 6.17 apparmor-next: apparmor: fix + regression in fs based unix sockets when using old abi + - SAUCE: apparmor5.0.0 [55/93]: 6.17 apparmor-next: apparmor: make sure + unix socket labeling is correctly updated. + - SAUCE: apparmor5.0.0 [56/93]: 6.17 apparmor-next: apparmor: shift ouid + when mediating hard links in userns + - SAUCE: apparmor5.0.0 [57/93]: 6.17 apparmor-next: apparmor: shift uid + when mediating af_unix in userns + - SAUCE: apparmor5.0.0 [58/93]: 6.17 apparmor-next: apparmor: Fix 8-byte + alignment for initial dfa blob streams + - SAUCE: apparmor5.0.0 [59/93]: 6.17 apparmor-next: apparmor: Fix + unaligned memory accesses in KUnit test + - SAUCE: apparmor5.0.0 [60/93]: 6.17 apparmor-next: apparmor: fix kernel + doc warnings for kernel test robot + - SAUCE: apparmor5.0.0 [61/93]: 6.17 apparmor-next: apparmor: remove + redundant perms.allow MAY_EXEC bitflag set + - SAUCE: apparmor5.0.0 [62/93]: 6.17 apparmor-next: apparmor: fix + documentation mismatches in val_mask_to_str and socket functions + - SAUCE: apparmor5.0.0 [63/93]: 6.17 apparmor-next: apparmor: transition + from a list of rules to a vector of rules + - SAUCE: apparmor5.0.0 [64/93]: 6.17 apparmor-next: apparmor: fix: accept2 + being specifie even when permission table is presnt + - SAUCE: apparmor5.0.0 [65/93]: 6.17 apparmor-next: apparmor: Remove the + unused variable rules + - SAUCE: apparmor5.0.0 [66/93]: 6.17 apparmor-next: apparmor: fix test + error: WARNING in apparmor_unix_stream_connect + - SAUCE: apparmor5.0.0 [67/93]: 6.17 apparmor-next: apparmor: fix + Regression on linux-next (next-20250721) + - SAUCE: apparmor5.0.0 [77/93]: aoparmor: userns: Add support for execpath + in userns + - SAUCE: apparmor5.0.0 [78/93]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [79/93]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [86/93]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [87/93]: apparmor: add AA_DEBUG_PROFILE to have + debug on profiles with flag set + - SAUCE: apparmor5.0.0 [88/93]: apparmor: make str table more generic and + be able to have multiple entries + - SAUCE: apparmor5.0.0 [89/93]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [90/93]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [91/93]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [92/93]: UBUNTU: SAUCE: apparmor5.0.0 [92/93]: + apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [93/93]: apparmor: mmap_file() doesn't need to be + called atomically + + -- Paolo Pisati Sat, 02 Aug 2025 11:25:12 +0200 + +linux (6.16.0-10.10) questing; urgency=medium + + * questing/linux: 6.16.0-10.10 -proposed tracker (LP: #2118882) + + * Miscellaneous Ubuntu changes + - Update dropped.txt + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] disable signing for s390x" + + -- Paolo Pisati Mon, 28 Jul 2025 08:23:12 +0200 + +linux (6.16.0-9.9) questing; urgency=medium + + * questing/linux: 6.16.0-9.9 -proposed tracker (LP: #2117331) + + -- Paolo Pisati Mon, 21 Jul 2025 09:06:33 +0200 + +linux (6.16.0-8.8) questing; urgency=medium + + * questing/linux: 6.16.0-8.8 -proposed tracker (LP: #2117156) + + * Miscellaneous Ubuntu changes + - [Packaging] rename to linux + - [Packaging] disable signing for s390x + + -- Paolo Pisati Thu, 17 Jul 2025 15:11:36 +0200 + +linux-unstable (6.16.0-7.7) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-7.7 -proposed tracker (LP: #2116881) + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.16-rc6 rebase + + -- Paolo Pisati Tue, 15 Jul 2025 09:13:15 +0200 + +linux-unstable (6.16.0-6.6) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-6.6 -proposed tracker (LP: #2116265) + + * [UBUNTU 25.04] lszcrypt output shows no cards because ap module has to be + loaded manually (LP: #2116061) + - [Config] s390: Build ap driver into the kernel + + * Miscellaneous Ubuntu changes + - [Packaging] debian.master/control.stub.in: fix dpkg-checkbuilddeps + - [Config] RUSTC_VERSION = 108501 + + -- Paolo Pisati Sun, 13 Jul 2025 10:16:39 +0200 + +linux-unstable (6.16.0-5.5) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-5.5 -proposed tracker (LP: #2115966) + + * Miscellaneous Ubuntu changes + - [Packaging] debian.master/control.stub.in: prepare for cross-compiling + - [Packaging] debian/rules.d/0-common-vars.mk: avoid infinite loop + - [Packaging] debian/rules.d/0-common-vars.mk: use native GCC + - [Packaging] debian/rules.d/0-common-vars.mk: enable linux-tools cross- + compilation + - [Packaging] debian/rules.d/0-common-vars.mk: fix linux-tools cross-build + - [Config] updateconfigs following v6.16-rc5 rebase + + -- Paolo Pisati Tue, 08 Jul 2025 15:09:17 +0200 + +linux-unstable (6.16.0-4.4) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-4.4 -proposed tracker (LP: #2115628) + + -- Paolo Pisati Mon, 30 Jun 2025 13:34:49 +0200 + +linux-unstable (6.16.0-3.3) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-3.3 -proposed tracker (LP: #2115254) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.06.03) + + * arm64: kernel image cannot be booted in UEFI despite EFI stub and ZBOOT + (LP: #2098111) + - [Packaging] Install compressed vmlinuz.efi on arm64 + + * Creating a VXLAN interface with a Fan mapping causes a NULL pointer + dereference caught by ubuntu_fan_smoke_test:sut-scan (LP: #2113992) + - SAUCE: fan: vxlan: parse fan-map from IFLA_VXLAN_FAN_MAP attribute ID + + * Dell AIO backlight is not working, dell_uart_backlight module is missing + (LP: #2083800) + - [Config] enable CONFIG_DELL_UART_BACKLIGHT + + * Miscellaneous Ubuntu changes + - [Packaging] Update debian/signature-inclusion + + -- Paolo Pisati Wed, 25 Jun 2025 13:07:01 +0200 + +linux-unstable (6.16.0-2.2) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-2.2 -proposed tracker (LP: #2114841) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.06.03) + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.16-rc2 + + -- Paolo Pisati Wed, 18 Jun 2025 15:33:41 +0200 + +linux-unstable (6.16.0-1.1) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-1.1 -proposed tracker (LP: #2114165) + + * Support Sony IMX471 camera sensor for Intel IPU7 platforms (LP: #2107320) + - SAUCE: media: ipu-bridge: Support imx471 sensor + + * Rotate the Canonical Livepatch key (LP: #2111244) + - [config] prepare for Canonical Livepatch key rotation + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.05.26) + + * Miscellaneous Ubuntu changes + - Update dropped.txt + - Update dropped.txt wrt v6.16-rc1 rebase + - [Config] updateconfigs following v6.16-rc1 + - [Config] FTBFS: disable INTEL_SKL_INT3472 + - SAUCE: binder: turn into module - lock_vma_under_rcu() + - [Packaging] debian.master/dkms-versions -- temporarily remove zfs FTBFS + - [Packaging] debian.master/dkms-versions -- temporarily remove + v4l2loopback FTBFS + + -- Paolo Pisati Thu, 12 Jun 2025 12:58:18 +0200 + +linux-unstable (6.15.0-2.2) questing; urgency=medium + + * questing/linux-unstable: 6.15.0-2.2 -proposed tracker (LP: #2111721) + + * Miscellaneous Ubuntu changes + - [Config] Updateconfigs for v6.15-rc7 rebase + + -- Paolo Pisati Mon, 26 May 2025 15:24:31 +0200 + +linux-unstable (6.15.0-1.1) questing; urgency=medium + + * questing/linux-unstable: 6.15.0-1.1 -proposed tracker (LP: #2110148) + + * Drop support for modules-extra (LP: #2042831) + - [Packaging] Drop support for modules-extra + + * Miscellaneous Ubuntu changes + - [Packaging] Rename to linux-unstable, bump version + - [Packaging] Re-enable tools build on cross-builds + - [Packaging] debian.master/dkms-versions -- temporarily remove all dkms + - [Packaging] Introduce do_sources_list build flag + - [Config] Updateconfigs for v6.15-rc5 rebase + - SAUCE: Revert "gcc-15: acpi: sprinkle random '__nonstring' crumbles around" + + -- Timo Aaltonen Thu, 08 May 2025 22:29:23 +0300 + +linux-unstable (6.15.0-0.0) questing; urgency=medium + + * Dummy entry + + -- Timo Aaltonen Wed, 07 May 2025 18:41:33 +0300 + +linux (6.14.0-17.17) plucky; urgency=medium + + * plucky/linux: 6.14.0-17.17 -proposed tracker (LP: #2109741) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/2025.04.14) + + * Plucky update: v6.14.4 upstream stable release (LP: #2109367) + - scsi: hisi_sas: Enable force phy when SATA disk directly connected + - wifi: at76c50x: fix use after free access in at76_disconnect + - wifi: mac80211: Update skb's control block key in ieee80211_tx_dequeue() + - wifi: mac80211: Purge vif txq in ieee80211_do_stop() + - wifi: brcmfmac: fix memory leak in brcmf_get_module_param + - wifi: wl1251: fix memory leak in wl1251_tx_work + - scsi: iscsi: Fix missing scsi_host_put() in error path + - scsi: smartpqi: Use is_kdump_kernel() to check for kdump + - md/raid10: fix missing discard IO accounting + - md/md-bitmap: fix stats collection for external bitmaps + - ASoC: dwc: always enable/disable i2s irqs + - ASoC: Intel: avs: Fix null-ptr-deref in avs_component_probe() + - crypto: tegra - Fix IV usage for AES ECB + - ovl: remove unused forward declaration + - RDMA/bnxt_re: Fix budget handling of notification queue + - RDMA/usnic: Fix passing zero to PTR_ERR in usnic_ib_pci_probe() + - RDMA/hns: Fix wrong maximum DMA segment size + - ALSA: hda/cirrus_scodec_test: Don't select dependencies + - ALSA: hda/realtek - Fixed ASUS platform headset Mic issue + - ASoC: cs42l43: Reset clamp override on jack removal + - RDMA/core: Silence oversized kvmalloc() warning + - firmware: cs_dsp: test_bin_error: Fix uninitialized data used as fw version + - Bluetooth: hci_event: Fix sending MGMT_EV_DEVICE_FOUND for invalid address + - Bluetooth: btrtl: Prevent potential NULL dereference + - Bluetooth: qca: fix NV variant for one of WCN3950 SoCs + - Bluetooth: l2cap: Check encryption key size on incoming connection + - RDMA/bnxt_re: Remove unusable nq variable + - ipv6: add exception routes to GC list in rt6_insert_exception + - xen: fix multicall debug feature + - mlxbf-bootctl: use sysfs_emit_at() in secure_boot_fuse_state_show() + - wifi: iwlwifi: pcie: set state to no-FW before reset handshake + - Revert "wifi: mac80211: Update skb's control block key in + ieee80211_tx_dequeue()" + - igc: fix PTM cycle trigger logic + - igc: increase wait time before retrying PTM + - igc: move ktime snapshot into PTM retry loop + - igc: handle the IGC_PTP_ENABLED flag correctly + - igc: cleanup PTP module if probe fails + - igc: add lock preventing multiple simultaneous PTM transactions + - perf tools: Remove evsel__handle_error_quirks() + - dt-bindings: soc: fsl: fsl,ls1028a-reset: Fix maintainer entry + - smc: Fix lockdep false-positive for IPPROTO_SMC. + - test suite: use %zu to print size_t + - selftests: mincore: fix tmpfs mincore test failure + - pds_core: fix memory leak in pdsc_debugfs_add_qcq() + - ethtool: cmis_cdb: use correct rpl size in ethtool_cmis_module_poll() + - net: mctp: Set SOCK_RCU_FREE + - net: hibmcge: fix incorrect pause frame statistics issue + - net: hibmcge: fix incorrect multicast filtering issue + - net: hibmcge: fix wrong mtu log issue + - net: hibmcge: fix not restore rx pause mac addr after reset issue + - block: fix resource leak in blk_register_queue() error path + - netlink: specs: ovs_vport: align with C codegen capabilities + - net: openvswitch: fix nested key length validation in the set() action + - can: rockchip_canfd: fix broken quirks checks + - net: ngbe: fix memory leak in ngbe_probe() error path + - octeontx2-pf: handle otx2_mbox_get_rsp errors + - net: ethernet: ti: am65-cpsw: fix port_np reference counting + - eth: bnxt: fix missing ring index trim on error path + - loop: aio inherit the ioprio of original request + - loop: stop using vfs_iter_{read,write} for buffered I/O + - nvmet: pci-epf: always fully initialize completion entries + - nvmet: pci-epf: clear CC and CSTS when disabling the controller + - ata: libata-sata: Save all fields from sense data descriptor + - cxgb4: fix memory leak in cxgb4_init_ethtool_filters() error path + - netlink: specs: rt-link: add an attr layer around alt-ifname + - netlink: specs: rtnetlink: attribute naming corrections + - netlink: specs: rt-link: adjust mctp attribute naming + - netlink: specs: rt-neigh: prefix struct nfmsg members with ndm + - net: b53: enable BPDU reception for management port + - net: bridge: switchdev: do not notify new brentries as changed + - net: txgbe: fix memory leak in txgbe_probe() error path + - net: dsa: mv88e6xxx: avoid unregistering devlink regions which were never + registered + - net: dsa: mv88e6xxx: fix -ENOENT when deleting VLANs and MST is unsupported + - net: dsa: clean up FDB, MDB, VLAN entries on unbind + - net: dsa: free routing table on probe failure + - net: dsa: avoid refcount warnings when ds->ops->tag_8021q_vlan_del() fails + - ptp: ocp: fix start time alignment in ptp_ocp_signal_set + - netfilter: conntrack: fix erronous removal of offload bit + - net: ti: icss-iep: Add pwidth configuration for perout signal + - net: ti: icss-iep: Add phase offset configuration for perout signal + - net: ti: icss-iep: Fix possible NULL pointer dereference for perout request + - net: ethernet: mtk_eth_soc: reapply mdc divider on reset + - net: ethernet: mtk_eth_soc: correct the max weight of the queue limit for + 100Mbps + - net: ethernet: mtk_eth_soc: revise QDMA packet scheduler settings + - riscv: Use kvmalloc_array on relocation_hashtable + - riscv: Properly export reserved regions in /proc/iomem + - riscv: module: Fix out-of-bounds relocation access + - riscv: module: Allocate PLT entries for R_RISCV_PLT32 + - kunit: qemu_configs: SH: Respect kunit cmdline + - thermal: intel: int340x: Fix Panther Lake DLVR support + - riscv: KGDB: Do not inline arch_kgdb_breakpoint() + - riscv: KGDB: Remove ".option norvc/.option rvc" for kgdb_compiled_break + - cpufreq/sched: Fix the usage of CPUFREQ_NEED_UPDATE_LIMITS + - objtool/rust: add one more `noreturn` Rust function for Rust 1.86.0 + - rust: helpers: Remove volatile qualifier from io helpers + - rust: kasan/kbuild: fix missing flags on first build + - rust: disable `clippy::needless_continue` + - rust: kbuild: Don't export __pfx symbols + - rust: kbuild: use `pound` to support GNU Make < 4.3 + - writeback: fix false warning in inode_to_wb() + - Revert "PCI: Avoid reset when disabled via sysfs" + - ASoC: fsl: fsl_qmc_audio: Reset audio data pointers on TRIGGER_START event + - ASoC: codecs:lpass-wsa-macro: Fix vi feedback rate + - ASoC: codecs:lpass-wsa-macro: Fix logic of enabling vi channels + - ASoC: Intel: sof_sdw: Add quirk for Asus Zenbook S16 + - ASoC: qcom: Fix sc7280 lpass potential buffer overflow + - accel/ivpu: Fix the NPU's DPU frequency calculation + - alloc_tag: handle incomplete bulk allocations in vm_module_tags_populate + - asus-laptop: Fix an uninitialized variable + - block: integrity: Do not call set_page_dirty_lock() + - drm/v3d: Fix Indirect Dispatch configuration for V3D 7.1.6 and later + - drm/msm/dpu: Fix error pointers in dpu_plane_virtual_atomic_check + - drm/msm/dpu: drop rogue intr_tear_rd_ptr values + - dma-buf/sw_sync: Decrement refcount on error in sw_sync_ioctl_get_deadline() + - nfs: add missing selections of CONFIG_CRC32 + - nfsd: decrease sc_count directly if fail to queue dl_recall + - i2c: atr: Fix wrong include + - eventpoll: abstract out ep_try_send_events() helper + - eventpoll: Set epoll timeout if it's in the future + - ftrace: fix incorrect hash size in register_ftrace_direct() + - drm/msm/a6xx+: Don't let IB_SIZE overflow + - Bluetooth: l2cap: Process valid commands in too long frame + - Bluetooth: vhci: Avoid needless snprintf() calls + - btrfs: ioctl: don't free iov when btrfs_encoded_read() returns -EAGAIN + - btrfs: correctly escape subvol in btrfs_show_options() + - cpufreq/sched: Explicitly synchronize limits_changed flag handling + - crypto: caam/qi - Fix drv_ctx refcount bug + - hfs/hfsplus: fix slab-out-of-bounds in hfs_bnode_read_key + - i2c: cros-ec-tunnel: defer probe if parent EC is not present + - isofs: Prevent the use of too small fid + - lib/iov_iter: fix to increase non slab folio refcount + - loop: properly send KOBJ_CHANGED uevent for disk device + - loop: LOOP_SET_FD: send uevents for partitions + - mm/compaction: fix bug in hugetlb handling pathway + - mm/gup: fix wrongly calculated returned value in fault_in_safe_writeable() + - mm: fix filemap_get_folios_contig returning batches of identical folios + - mm: fix apply_to_existing_page_range() + - ovl: don't allow datadir only + - ksmbd: Fix dangling pointer in krb_authenticate + - ksmbd: fix use-after-free in __smb2_lease_break_noti() + - ksmbd: fix use-after-free in smb_break_all_levII_oplock() + - ksmbd: Prevent integer overflow in calculation of deadtime + - ksmbd: fix the warning from __kernel_write_iter + - Revert "smb: client: Fix netns refcount imbalance causing leaks and use- + after-free" + - Revert "smb: client: fix TCP timers deadlock after rmmod" + - riscv: Avoid fortify warning in syscall_get_arguments() + - selftests/mm: generate a temporary mountpoint for cgroup filesystem + - slab: ensure slab->obj_exts is clear in a newly allocated slab page + - smb3 client: fix open hardlink on deferred close file error + - string: Add load_unaligned_zeropad() code path to sized_strscpy() + - tracing: Fix filter string testing + - virtiofs: add filesystem context source name check + - x86/microcode/AMD: Extend the SHA check to Zen5, block loading of any + unreleased standalone Zen5 microcode patches + - x86/cpu/amd: Fix workaround for erratum 1054 + - x86/boot/sev: Avoid shared GHCB page for early memory acceptance + - scsi: megaraid_sas: Block zero-length ATA VPD inquiry + - scsi: ufs: exynos: Move UFS shareability value to drvdata + - scsi: ufs: exynos: Disable iocc if dma-coherent property isn't set + - scsi: ufs: exynos: Ensure consistent phy reference counts + - RDMA/cma: Fix workqueue crash in cma_netevent_work_handler + - RAS/AMD/ATL: Include row[13] bit in row retirement + - RAS/AMD/FMPM: Get masked address + - platform/x86: amd: pmf: Fix STT limits + - perf/x86/intel: Allow to update user space GPRs from PEBS records + - perf/x86/intel/uncore: Fix the scale of IIO free running counters on SNR + - perf/x86/intel/uncore: Fix the scale of IIO free running counters on ICX + - perf/x86/intel/uncore: Fix the scale of IIO free running counters on SPR + - drm/repaper: fix integer overflows in repeat functions + - drm/ast: Fix ast_dp connection status + - drm/msm/dsi: Add check for devm_kstrdup() + - drm/msm/a6xx: Fix stale rpmh votes from GPU + - drm/amdgpu: Prefer shadow rom when available + - drm/amd/display: prevent hang on link training fail + - drm/amd: Handle being compiled without SI or CIK support better + - drm/amd/display: Actually do immediate vblank disable + - drm/amd/display: Increase vblank offdelay for PSR panels + - drm/amd/pm: Prevent division by zero + - drm/amd/pm/powerplay: Prevent division by zero + - drm/amd/pm: Add zero RPM enabled OD setting support for SMU14.0.2 + - drm/amd/pm/smu11: Prevent division by zero + - drm/amd/pm/powerplay/hwmgr/smu7_thermal: Prevent division by zero + - drm/amd/pm/swsmu/smu13/smu_v13_0: Prevent division by zero + - drm/amd/pm/powerplay/hwmgr/vega20_thermal: Prevent division by zero + - drm/amdgpu/mes12: optimize MES pipe FW version fetching + - drm/i915/vrr: Add vrr.vsync_{start, end} in vrr_params_changed + - drm/xe: Use local fence in error path of xe_migrate_clear + - drm/virtio: Don't attach GEM to a non-created context in gem_object_open() + - drm/amd/display: Add HP Elitebook 645 to the quirk list for eDP on DP1 + - drm/amd/display: Protect FPU in dml2_validate()/dml21_validate() + - drm/amd/display: Protect FPU in dml21_copy() + - drm/amdgpu/mes11: optimize MES pipe FW version fetching + - drm/amdgpu/dma_buf: fix page_link check + - drm/nouveau: prime: fix ttm_bo_delayed_delete oops + - drm/imagination: fix firmware memory leaks + - drm/imagination: take paired job reference + - drm/virtio: Fix missed dmabuf unpinning in error path of prepare_fb() + - drm/sti: remove duplicate object names + - drm/i915: Fix scanline_offset for LNL+ and BMG+ + - drm/xe: Fix an out-of-bounds shift when invalidating TLB + - Revert "UBUNTU: SAUCE: drm/xe/bmg: Add one additional PCI ID" + - drm/xe/bmg: Add one additional PCI ID + - drm/i915/gvt: fix unterminated-string-initialization warning + - drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC + - drm/i915/dp: Reject HBR3 when sink doesn't support TPS4 + - drm/amdgpu: immediately use GTT for new allocations + - drm/amd/display: Do not enable Replay and PSR while VRR is on in + amdgpu_dm_commit_planes() + - drm/amd/display: Protect FPU in dml2_init()/dml21_init() + - drm/amd/display: Add HP Probook 445 and 465 to the quirk list for eDP on DP1 + - drm/xe/dma_buf: stop relying on placement in unmap + - drm/xe/userptr: fix notifier vs folio deadlock + - drm/xe: Set LRC addresses before guc load + - drm/i915/display: Add macro for checking 3 DSC engines + - drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slices + - drm/amd/display/dml2: use vzalloc rather than kzalloc + - drm/amdgpu: fix warning of drm_mm_clean + - drm/mgag200: Fix value in register + - io_uring: don't post tag CQEs on file/buffer registration failure + - arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 + - arm64/sysreg: Add register fields for HDFGRTR2_EL2 + - arm64/sysreg: Add register fields for HDFGWTR2_EL2 + - arm64/sysreg: Add register fields for HFGITR2_EL2 + - arm64/sysreg: Add register fields for HFGRTR2_EL2 + - arm64/sysreg: Add register fields for HFGWTR2_EL2 + - arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 + - cpufreq: Reference count policy in cpufreq_update_limits() + - scripts: generate_rust_analyzer: Add ffi crate + - platform/x86: alienware-wmi-wmax: Add G-Mode support to Alienware m16 R1 + - platform/x86: alienware-wmi-wmax: Extend support to more laptops + - platform/x86: msi-wmi-platform: Rename "data" variable + - platform/x86: msi-wmi-platform: Workaround a ACPI firmware bug + - drm/amd/display: Temporarily disable hostvm on DCN31 + - nvmet-fc: Remove unused functions + - mm/vma: add give_up_on_oom option on modify/merge, use in uffd release + - Revert "wifi: ath12k: Fix invalid entry fetch in ath12k_dp_mon_srng_process" + - MIPS: dec: Declare which_prom() as static + - MIPS: cevt-ds1287: Add missing ds1287.h include + - MIPS: ds1287: Match ds1287_set_base_clock() function types + - wifi: ath12k: Fix invalid entry fetch in ath12k_dp_mon_srng_process + - Linux 6.14.4 + + * Plucky update: v6.14.3 upstream stable release (LP: #2108854) + - ASoC: Intel: adl: add 2xrt1316 audio configuration + - cgroup/cpuset: Fix incorrect isolated_cpus update in + update_parent_effective_cpumask() + - cgroup/cpuset: Fix error handling in remote_partition_disable() + - cgroup/cpuset: Fix race between newly created partition and dying one + - tracing: fprobe: Cleanup fprobe hash when module unloading + - gpiolib: of: Fix the choice for Ingenic NAND quirk + - selftests/futex: futex_waitv wouldblock test should fail + - ublk: fix handling recovery & reissue in ublk_abort_queue() + - drm/virtio: Fix flickering issue seen with imported dmabufs + - drm/i915: Disable RPG during live selftest + - x86/acpi: Don't limit CPUs to 1 for Xen PV guests due to disabled ACPI + - net: ethtool: fix ethtool_ringparam_get_cfg() returns a hds_thresh value + always as 0. + - drm/xe/hw_engine: define sysfs_ops on all directories + - drm/xe: Restore EIO errno return when GuC PC start fails + - ata: pata_pxa: Fix potential NULL pointer dereference in pxa_ata_probe() + - objtool: Fix INSN_CONTEXT_SWITCH handling in validate_unret() + - tipc: fix memory leak in tipc_link_xmit + - codel: remove sch->q.qlen check before qdisc_tree_reduce_backlog() + - net: tls: explicitly disallow disconnect + - octeontx2-pf: qos: fix VF root node parent queue index + - tc: Ensure we have enough buffer space when sending filter netlink + notifications + - net: ethtool: Don't call .cleanup_data when prepare_data fails + - drm/tests: modeset: Fix drm_display_mode memory leak + - drm/tests: helpers: Create kunit helper to destroy a drm_display_mode + - drm/tests: cmdline: Fix drm_display_mode memory leak + - drm/tests: modes: Fix drm_display_mode memory leak + - drm/tests: probe-helper: Fix drm_display_mode memory leak + - net: libwx: handle page_pool_dev_alloc_pages error + - cifs: Fix support for WSL-style symlinks + - ata: sata_sx4: Add error handling in pdc20621_i2c_read() + - drm/i915/huc: Fix fence not released on early probe errors + - s390/cpumf: Fix double free on error in cpumf_pmu_event_init() + - nvmet-fcloop: swap list_add_tail arguments + - net_sched: sch_sfq: use a temporary work area for validating configuration + - net_sched: sch_sfq: move the limit validation + - x86/cpu: Avoid running off the end of an AMD erratum table + - smb: client: fix UAF in decryption with multichannel + - net: phy: move phy_link_change() prior to mdio_bus_phy_may_suspend() + - net: phy: allow MDIO bus PM ops to start/stop state machine for phylink- + controlled PHY + - ipv6: Align behavior across nexthops during path selection + - net: ppp: Add bound checking for skb data on ppp_sync_txmung + - nft_set_pipapo: fix incorrect avx2 match of 5th field octet + - ethtool: cmis_cdb: Fix incorrect read / write length extension + - iommu/exynos: Fix suspend/resume with IDENTITY domain + - iommu/mediatek: Fix NULL pointer deference in mtk_iommu_device_group + - net: libwx: Fix the wrong Rx descriptor field + - perf/core: Simplify the perf_event_alloc() error path + - perf: Fix hang while freeing sigtrap event + - fs: consistently deref the files table with rcu_dereference_raw() + - umount: Allow superblock owners to force umount + - srcu: Force synchronization for srcu_get_delay() + - pm: cpupower: bench: Prevent NULL dereference on malloc failure + - irqchip/gic-v3: Add Rockchip 3568002 erratum workaround + - [Config] updateconfigs for ROCKCHIP_ERRATUM_3568002 + - x86/mm: Clear _PAGE_DIRTY for kernel mappings when we clear _PAGE_RW + - x86/percpu: Disable named address spaces for UBSAN_BOOL with KASAN for GCC < + 14.2 + - x86/ia32: Leave NULL selector values 0~3 unchanged + - x86/cpu: Don't clear X86_FEATURE_LAHF_LM flag in init_amd_k8() on AMD when + running in a virtual machine + - perf: arm_pmu: Don't disable counter in armpmu_add() + - perf/dwc_pcie: fix some unreleased resources + - perf/dwc_pcie: fix duplicate pci_dev devices + - PM: hibernate: Avoid deadlock in hibernate_compressor_param_set() + - Flush console log from kernel_power_off() + - cpufreq/amd-pstate: Invalidate cppc_req_cached during suspend + - arm64: cputype: Add QCOM_CPU_PART_KRYO_3XX_GOLD + - xen/mcelog: Add __nonstring annotations for unterminated strings + - zstd: Increase DYNAMIC_BMI2 GCC version cutoff from 4.8 to 11.0 to work + around compiler segfault + - tracing: Disable branch profiling in noinstr code + - platform/chrome: cros_ec_lpc: Match on Framework ACPI device + - ASoC: SOF: topology: Use krealloc_array() to replace krealloc() + - HID: pidff: Convert infinite length from Linux API to PID standard + - HID: pidff: Do not send effect envelope if it's empty + - HID: pidff: Add MISSING_DELAY quirk and its detection + - HID: pidff: Add MISSING_PBO quirk and its detection + - HID: pidff: Add PERMISSIVE_CONTROL quirk + - HID: pidff: Add hid_pidff_init_with_quirks and export as GPL symbol + - HID: pidff: Add FIX_WHEEL_DIRECTION quirk + - HID: Add hid-universal-pidff driver and supported device ids + - [Config] enable new hid-universal-pidff driver module + - HID: pidff: Add PERIODIC_SINE_ONLY quirk + - HID: pidff: Fix null pointer dereference in pidff_find_fields + - ASoC: amd: ps: use macro for ACP6.3 pci revision id + - ASoC: amd: amd_sdw: Add quirks for Dell SKU's + - ALSA: hda: intel: Fix Optimus when GPU has no sound + - ALSA: hda: intel: Add Lenovo IdeaPad Z570 to probe denylist + - ASoC: fsl_audmix: register card device depends on 'dais' property + - media: uvcvideo: Add quirk for Actions UVC05 + - HID: lenovo: Fix to ensure the data as __le32 instead of u32 + - media: s5p-mfc: Corrected NV12M/NV21M plane-sizes + - mmc: dw_mmc: add a quirk for accessing 64-bit FIFOs in two halves + - ALSA: usb-audio: Fix CME quirk for UF series keyboards + - ASoC: amd: Add DMI quirk for ACP6X mic support + - ALSA: hda/realtek: fix micmute LEDs on HP Laptops with ALC3315 + - ALSA: hda/realtek: fix micmute LEDs on HP Laptops with ALC3247 + - ASoC: amd: yc: update quirk data for new Lenovo model + - platform/x86: x86-android-tablets: Add select POWER_SUPPLY to Kconfig + - wifi: ath9k: use unsigned long for activity check timestamp + - wifi: ath11k: Fix DMA buffer allocation to resolve SWIOTLB issues + - wifi: ath11k: fix memory leak in ath11k_xxx_remove() + - wifi: ath12k: fix memory leak in ath12k_pci_remove() + - wifi: ath12k: Fix invalid entry fetch in ath12k_dp_mon_srng_process + - wifi: ath12k: Avoid memory leak while enabling statistics + - ata: libata-core: Add 'external' to the libata.force kernel parameter + - scsi: mpi3mr: Avoid reply queue full condition + - scsi: mpi3mr: Synchronous access b/w reset and tm thread for reply queue + - net: page_pool: don't cast mp param to devmem + - f2fs: don't retry IO for corrupted data scenario + - wifi: mac80211: add strict mode disabling workarounds + - wifi: mac80211: ensure sdata->work is canceled before initialized. + - scsi: target: spc: Fix RSOC parameter data header size + - net: usb: asix_devices: add FiberGecko DeviceID + - page_pool: avoid infinite loop to schedule delayed worker + - can: flexcan: Add quirk to handle separate interrupt lines for mailboxes + - can: flexcan: add NXP S32G2/S32G3 SoC support + - jfs: Fix uninit-value access of imap allocated in the diMount() function + - fs/jfs: cast inactags to s64 to prevent potential overflow + - fs/jfs: Prevent integer overflow in AG size calculation + - jfs: Prevent copying of nlink with value 0 from disk inode + - jfs: add sanity check for agwidth in dbMount + - wifi: rtw88: Add support for Mercusys MA30N and D-Link DWA-T185 rev. A1 + - ata: libata-eh: Do not use ATAPI DMA for a device limited to PIO mode + - net: sfp: add quirk for 2.5G OEM BX SFP + - wifi: ath12k: Fix invalid data access in ath12k_dp_rx_h_undecap_nwifi + - f2fs: fix to avoid out-of-bounds access in f2fs_truncate_inode_blocks() + - net: sfp: add quirk for FS SFP-10GM-T copper SFP+ module + - ahci: add PCI ID for Marvell 88SE9215 SATA Controller + - ext4: protect ext4_release_dquot against freezing + - Revert "f2fs: rebuild nat_bits during umount" + - wifi: mac80211: fix userspace_selectors corruption + - ext4: ignore xattrs past end + - cdc_ether|r8152: ThinkPad Hybrid USB-C/A Dock quirk + - scsi: st: Fix array overflow in st_setup() + - ahci: Marvell 88SE9215 controllers prefer DMA for ATAPI + - btrfs: harden block_group::bg_list against list_del() races + - wifi: mt76: mt76x2u: add TP-Link TL-WDN6200 ID to device table + - net: vlan: don't propagate flags on open + - tracing: fix return value in __ftrace_event_enable_disable for + TRACE_REG_UNREGISTER + - Bluetooth: btusb: Add new VID/PID for WCN785x + - Bluetooth: btintel_pcie: Add device id of Whale Peak + - Bluetooth: btusb: Add 13 USB device IDs for Qualcomm WCN785x + - Bluetooth: hci_uart: fix race during initialization + - Bluetooth: btusb: Add 2 HWIDs for MT7922 + - Bluetooth: hci_qca: use the power sequencer for wcn6750 + - Bluetooth: qca: simplify WCN399x NVM loading + - Bluetooth: qca: add WCN3950 support + - drm: allow encoder mode_set even when connectors change for crtc + - drm/virtio: Set missing bo->attached flag + - drm/rockchip: Don't change hdmi reference clock rate + - drm/xe/ptl: Update the PTL pci id table + - drm/xe/pf: Don't send BEGIN_ID if VF has no context/doorbells + - drm/xe/vf: Don't try to trigger a full GT reset if VF + - drm/amd/display: Update Cursor request mode to the beginning prefetch always + - drm/amd/display: Guard Possible Null Pointer Dereference + - drm/amd/display: add workaround flag to link to force FFE preset + - drm/amdgpu: Unlocked unmap only clear page table leaves + - drm: panel-orientation-quirks: Add support for AYANEO 2S + - drm: panel-orientation-quirks: Add quirks for AYA NEO Flip DS and KB + - drm: panel-orientation-quirks: Add quirk for AYA NEO Slide + - drm: panel-orientation-quirks: Add new quirk for GPD Win 2 + - drm: panel-orientation-quirks: Add quirk for OneXPlayer Mini (Intel) + - drm/debugfs: fix printk format for bridge index + - drm/bridge: panel: forbid initializing a panel with unknown connector type + - drm/amd/display: Update FIXED_VS Link Rate Toggle Workaround Usage + - drm/amd/display: stop DML2 from removing pipes based on planes + - drivers: base: devres: Allow to release group on device release + - drm/amdkfd: clamp queue size to minimum + - drm/amdkfd: Fix mode1 reset crash issue + - drm/amdkfd: Fix pqm_destroy_queue race with GPU reset + - drm/amdkfd: debugfs hang_hws skip GPU with MES + - drm/xe/xelp: Move Wa_16011163337 from tunings to workarounds + - drm/mediatek: mtk_dpi: Move the input_2p_en bit to platform data + - drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off + - drm/rockchip: stop passing non struct drm_device to drm_err() and friends + - PCI: Add Rockchip Vendor ID + - drm/amdgpu: handle amdgpu_cgs_create_device() errors in + amd_powerplay_create() + - drm/amd/display: Prevent VStartup Overflow + - PCI: Enable Configuration RRS SV early + - drm/amdgpu: Fix the race condition for draining retry fault + - PCI: Check BAR index for validity + - PCI: vmd: Make vmd_dev::cfg_lock a raw_spinlock_t type + - drm/amdgpu: grab an additional reference on the gang fence v2 + - fbdev: omapfb: Add 'plane' value check + - tracing: probe-events: Log error for exceeding the number of arguments + - tracing: probe-events: Add comments about entry data storing code + - ktest: Fix Test Failures Due to Missing LOG_FILE Directories + - tpm, tpm_tis: Workaround failed command reception on Infineon devices + - tpm: End any active auth session before shutdown + - pwm: mediatek: Prevent divide-by-zero in pwm_mediatek_config() + - pwm: rcar: Improve register calculation + - pwm: fsl-ftm: Handle clk_get_rate() returning 0 + - pwm: stm32: Search an appropriate duty_cycle if period cannot be modified + - erofs: set error to bio if file-backed IO fails + - bpf: support SKF_NET_OFF and SKF_LL_OFF on skb frags + - ext4: don't treat fhandle lookup of ea_inode as FS corruption + - s390/pci: Fix s390_mmio_read/write syscall page fault handling + - HID: pidff: Clamp PERIODIC effect period to device's logical range + - HID: pidff: Stop all effects before enabling actuators + - HID: pidff: Completely rework and fix pidff_reset function + - HID: pidff: Simplify pidff_upload_effect function + - HID: pidff: Define values used in pidff_find_special_fields + - HID: pidff: Rescale time values to match field units + - HID: pidff: Factor out code for setting gain + - HID: pidff: Move all hid-pidff definitions to a dedicated header + - HID: pidff: Simplify pidff_rescale_signed + - HID: pidff: Use macros instead of hardcoded min/max values for shorts + - HID: pidff: Factor out pool report fetch and remove excess declaration + - HID: pidff: Make sure to fetch pool before checking SIMULTANEOUS_MAX + - HID: hid-universal-pidff: Add Asetek wheelbases support + - HID: pidff: Comment and code style update + - HID: pidff: Support device error response from PID_BLOCK_LOAD + - HID: pidff: Remove redundant call to pidff_find_special_keys + - HID: pidff: Rename two functions to align them with naming convention + - HID: pidff: Clamp effect playback LOOP_COUNT value + - HID: pidff: Compute INFINITE value instead of using hardcoded 0xffff + - HID: pidff: Fix 90 degrees direction name North -> East + - HID: pidff: Fix set_device_control() + - auxdisplay: hd44780: Fix an API misuse in hd44780.c + - dt-bindings: media: st,stmipid02: correct lane-polarities maxItems + - media: mediatek: vcodec: Fix a resource leak related to the scp device in FW + initialization + - media: mtk-vcodec: venc: avoid -Wenum-compare-conditional warning + - media: uapi: rkisp1-config: Fix typo in extensible params example + - media: mgb4: Fix CMT registers update logic + - media: i2c: adv748x: Fix test pattern selection mask + - media: mgb4: Fix switched CMT frequency range "magic values" sets + - media: intel/ipu6: set the dev_parent of video device to pdev + - media: venus: hfi: add a check to handle OOB in sfr region + - media: venus: hfi: add check to handle incorrect queue size + - media: vim2m: print device name after registering device + - media: siano: Fix error handling in smsdvb_module_init() + - media: rockchip: rga: fix rga offset lookup + - xenfs/xensyms: respect hypervisor's "next" indication + - KVM: arm64: PMU: Set raw values from user to PM{C,I}NTEN{SET,CLR}, + PMOVS{SET,CLR} + - arm64: cputype: Add MIDR_CORTEX_A76AE + - arm64: errata: Add QCOM_KRYO_4XX_GOLD to the spectre_bhb_k24_list + - arm64: errata: Assume that unknown CPUs _are_ vulnerable to Spectre BHB + - arm64: errata: Add KRYO 2XX/3XX/4XX silver cores to Spectre BHB safe list + - KVM: arm64: Tear down vGIC on failed vCPU creation + - KVM: arm64: Set HCR_EL2.TID1 unconditionally + - spi: cadence-qspi: Fix probe on AM62A LP SK + - mtd: rawnand: brcmnand: fix PM resume warning + - tpm, tpm_tis: Fix timeout handling when waiting for TPM status + - accel/ivpu: Fix PM related deadlocks in MS IOCTLs + - media: ov08x40: Properly turn sensor on/off when runtime-suspended + - media: streamzap: prevent processing IR data on URB failure + - media: hi556: Fix memory leak (on error) in hi556_check_hwcfg() + - media: visl: Fix ERANGE error when setting enum controls + - media: platform: stm32: Add check for clk_enable() + - media: xilinx-tpg: fix double put in xtpg_parse_of() + - media: imx219: Adjust PLL settings based on the number of MIPI lanes + - media: v4l2-dv-timings: prevent possible overflow in v4l2_detect_gtf() + - Revert "media: imx214: Fix the error handling in imx214_probe()" + - media: i2c: ccs: Set the device's runtime PM status correctly in remove + - media: i2c: ccs: Set the device's runtime PM status correctly in probe + - media: i2c: ov7251: Set enable GPIO low in probe + - media: i2c: ov7251: Introduce 1 ms delay between regulators and en GPIO + - media: nuvoton: Fix reference handling of ece_node + - media: nuvoton: Fix reference handling of ece_pdev + - media: venus: hfi_parser: add check to avoid out of bound access + - media: venus: hfi_parser: refactor hfi packet parsing logic + - media: i2c: imx319: Rectify runtime PM handling probe and remove + - media: i2c: imx219: Rectify runtime PM handling in probe and remove + - media: i2c: imx214: Rectify probe error handling related to runtime PM + - media: chips-media: wave5: Fix gray color on screen + - media: chips-media: wave5: Avoid race condition in the interrupt handler + - media: chips-media: wave5: Fix a hang after seeking + - media: chips-media: wave5: Fix timeout while testing 10bit hevc fluster + - irqchip/renesas-rzv2h: Fix wrong variable usage in rzv2h_tint_set_type() + - mptcp: sockopt: fix getting IPV6_V6ONLY + - mptcp: sockopt: fix getting freebind & transparent + - block: make sure ->nr_integrity_segments is cloned in blk_rq_prep_clone + - mtd: Add check for devm_kcalloc() + - net: dsa: mv88e6xxx: workaround RGMII transmit delay erratum for 6320 family + - net: dsa: mv88e6xxx: fix internal PHYs for 6320 family + - mtd: Replace kcalloc() with devm_kcalloc() + - clocksource/drivers/stm32-lptimer: Use wakeup capable instead of init wakeup + - Revert "wifi: mt76: mt7925: Update mt7925_mcu_uni_[tx,rx]_ba for MLO" + - wifi: mt76: Add check for devm_kstrdup() + - wifi: mt76: mt792x: re-register CHANCTX_STA_CSA only for the mt7921 series + - wifi: mac80211: fix integer overflow in hwmp_route_info_get() + - wifi: mt76: mt7925: ensure wow pattern command align fw format + - wifi: mt76: mt7925: fix country count limitation for CLC + - wifi: mt76: mt7925: fix the wrong link_idx when a p2p_device is present + - wifi: mt76: mt7925: fix the wrong simultaneous cap for MLO + - wifi: mt76: mt7925: adjust rm BSS flow to prevent next connection failure + - wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd + - wifi: mt76: mt7925: update the power-saving flow + - scsi: lpfc: Restore clearing of NLP_UNREG_INP in ndlp->nlp_flag + - net: stmmac: Fix accessing freed irq affinity_hint + - io_uring/net: fix accept multishot handling + - io_uring/net: fix io_req_post_cqe abuse by send bundle + - io_uring/kbuf: reject zero sized provided buffers + - ASoC: codecs: wcd937x: fix a potential memory leak in + wcd937x_soc_codec_probe() + - ASoC: q6apm: add q6apm_get_hw_pointer helper + - ASoC: q6apm-dai: schedule all available frames to avoid dsp under-runs + - ASoC: q6apm-dai: make use of q6apm_get_hw_pointer + - ASoC: qdsp6: q6apm-dai: set 10 ms period and buffer alignment. + - ASoC: qdsp6: q6apm-dai: fix capture pipeline overruns. + - ASoC: qdsp6: q6asm-dai: fix q6asm_dai_compr_set_params error path + - ALSA: hda/realtek: Enable Mute LED on HP OMEN 16 Laptop xd000xx + - accel/ivpu: Fix warning in ivpu_ipc_send_receive_internal() + - accel/ivpu: Fix deadlock in ivpu_ms_cleanup() + - arm/crc-t10dif: fix use of out-of-scope array in crc_t10dif_arch() + - arm64/crc-t10dif: fix use of out-of-scope array in crc_t10dif_arch() + - bus: mhi: host: Fix race between unprepare and queue_buf + - ext4: fix off-by-one error in do_split + - f2fs: fix the missing write pointer correction + - f2fs: fix to avoid atomicity corruption of atomic file + - vdpa/mlx5: Fix oversized null mkey longer than 32bit + - udf: Fix inode_getblk() return value + - tpm: do not start chip while suspended + - svcrdma: do not unregister device for listeners + - soc: samsung: exynos-chipid: Add NULL pointer check in exynos_chipid_probe() + - smb311 client: fix missing tcon check when mounting with linux/posix + extensions + - ima: limit the number of open-writers integrity violations + - ima: limit the number of ToMToU integrity violations + - igc: Fix XSK queue NAPI ID mapping + - i3c: master: svc: Use readsb helper for reading MDB + - i3c: Add NULL pointer check in i3c_master_queue_ibi() + - jbd2: remove wrong sb->s_sequence check + - kbuild: exclude .rodata.(cst|str)* when building ranges + - kbuild: Add '-fno-builtin-wcslen' + - leds: rgb: leds-qcom-lpg: Fix pwm resolution max for Hi-Res PWMs + - leds: rgb: leds-qcom-lpg: Fix calculation of best period Hi-Res PWMs + - mfd: ene-kb3930: Fix a potential NULL pointer dereference + - mailbox: tegra-hsp: Define dimensioning masks in SoC data + - locking/lockdep: Decrease nr_unused_locks if lock unused in zap_class() + - lib: scatterlist: fix sg_split_phys to preserve original scatterlist offsets + - mptcp: fix NULL pointer in can_accept_new_subflow + - mptcp: only inc MPJoinAckHMacFailure for HMAC failures + - mtd: inftlcore: Add error check for inftl_read_oob() + - mtd: rawnand: Add status chack in r852_ready() + - mtd: spinand: Fix build with gcc < 7.5 + - arm64: mops: Do not dereference src reg for a set operation + - arm64: tegra: Remove the Orin NX/Nano suspend key + - arm64: mm: Correct the update of max_pfn + - arm64: dts: ti: k3-j784s4-j742s2-main-common: Correct the GICD size + - arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks + - arm64: dts: mediatek: mt8188: Assign apll1 clock as parent to avoid hang + - arm64: dts: mediatek: mt8173: Fix disp-pwm compatible string + - arm64: dts: exynos: gs101: disable pinctrl_gsacore node + - backlight: led_bl: Hold led_access lock when calling led_sysfs_disable() + - btrfs: fix non-empty delayed iputs list on unmount due to compressed write + workers + - btrfs: tests: fix chunk map leak after failure to add it to the tree + - btrfs: zoned: fix zone activation with missing devices + - btrfs: zoned: fix zone finishing with missing devices + - iommufd: Fix uninitialized rc in iommufd_access_rw() + - iommu/tegra241-cmdqv: Fix warnings due to dmam_free_coherent() + - iommu/vt-d: Put IRTE back into posted MSI mode if vCPU posting is disabled + - iommu/vt-d: Don't clobber posted vCPU IRTE when host IRQ affinity changes + - iommu/vt-d: Fix possible circular locking dependency + - iommu/vt-d: Wire up irq_ack() to irq_move_irq() for posted MSIs + - sparc/mm: disable preemption in lazy mmu mode + - sparc/mm: avoid calling arch_enter/leave_lazy_mmu() in set_ptes + - net: Fix null-ptr-deref by sock_lock_init_class_and_name() and rmmod. + - mm/damon/ops: have damon_get_folio return folio even for tail pages + - mm/damon: avoid applying DAMOS action to same entity multiple times + - mm/rmap: reject hugetlb folios in folio_make_device_exclusive() + - mm: make page_mapped_in_vma() hugetlb walk aware + - mm: fix lazy mmu docs and usage + - mm/mremap: correctly handle partial mremap() of VMA starting at 0 + - mm: add missing release barrier on PGDAT_RECLAIM_LOCKED unlock + - mm/userfaultfd: fix release hang over concurrent GUP + - mm/hwpoison: do not send SIGBUS to processes with recovered clean pages + - mm/hugetlb: move hugetlb_sysctl_init() to the __init section + - mm/hwpoison: introduce folio_contain_hwpoisoned_page() helper + - sctp: detect and prevent references to a freed transport in sendmsg + - x86/xen: fix balloon target initialization for PVH dom0 + - uprobes: Avoid false-positive lockdep splat on CONFIG_PREEMPT_RT=y in the + ri_timer() uprobe timer callback, use raw_write_seqcount_*() + - tracing: fprobe: Fix to lock module while registering fprobe + - tracing: fprobe events: Fix possible UAF on modules + - tracing: Do not add length to print format in synthetic events + - thermal/drivers/rockchip: Add missing rk3328 mapping entry + - CIFS: Propagate min offload along with other parameters from primary to + secondary channels. + - cifs: avoid NULL pointer dereference in dbg call + - cifs: fix integer overflow in match_server() + - cifs: Ensure that all non-client-specific reparse points are processed by + the server + - clk: renesas: r9a07g043: Fix HP clock source for RZ/Five + - clk: qcom: clk-branch: Fix invert halt status bit check for votable clocks + - clk: qcom: gdsc: Release pm subdomains in reverse add order + - clk: qcom: gdsc: Capture pm_genpd_add_subdomain result code + - clk: qcom: gdsc: Set retain_ff before moving to HW CTRL + - crypto: ccp - Fix check for the primary ASP device + - crypto: ccp - Fix uAPI definitions of PSP errors + - dlm: fix error if inactive rsb is not hashed + - dlm: fix error if active rsb is not hashed + - dm-ebs: fix prefetch-vs-suspend race + - dm-integrity: set ti->error on memory allocation failure + - dm-integrity: fix non-constant-time tag verification + - dm-verity: fix prefetch-vs-suspend race + - dt-bindings: coresight: qcom,coresight-tpda: Fix too many 'reg' + - dt-bindings: coresight: qcom,coresight-tpdm: Fix too many 'reg' + - firmware: cs_dsp: test_control_parse: null-terminate test strings + - ftrace: Add cond_resched() to ftrace_graph_set_hash() + - ftrace: Properly merge notrace hashes + - fuse: {io-uring} Fix a possible req cancellation race + - gpio: mpc8xxx: Fix wakeup source leaks on device unbind + - gpio: tegra186: fix resource handling in ACPI probe path + - gpio: zynq: Fix wakeup source leaks on device unbind + - gve: handle overflow when reporting TX consumed descriptors + - KVM: Allow building irqbypass.ko as as module when kvm.ko is a module + - [Config] updateconfigs for HAVE_KVM_IRQ_BYPASS + - KVM: x86: Explicitly zero-initialize on-stack CPUID unions + - KVM: x86: Acquire SRCU in KVM_GET_MP_STATE to protect guest memory accesses + - landlock: Move code to ease future backports + - landlock: Add the errata interface + - landlock: Add erratum for TCP fix + - landlock: Always allow signals between threads of the same process + - landlock: Prepare to add second errata + - selftests/landlock: Split signal_scoping_threads tests + - selftests/landlock: Add a new test for setuid() + - misc: pci_endpoint_test: Avoid issue of interrupts remaining after + request_irq error + - misc: pci_endpoint_test: Fix displaying 'irq_type' after 'request_irq' error + - misc: pci_endpoint_test: Fix 'irq_type' to convey the correct type + - net: mana: Switch to page pool for jumbo frames + - ntb: use 64-bit arithmetic for the MSI doorbell mask + - of/irq: Fix device node refcount leakage in API of_irq_parse_one() + - of/irq: Fix device node refcount leakage in API of_irq_parse_raw() + - of/irq: Fix device node refcount leakages in of_irq_count() + - of/irq: Fix device node refcount leakage in API irq_of_parse_and_map() + - of/irq: Fix device node refcount leakages in of_irq_init() + - PCI: brcmstb: Fix missing of_node_put() in brcm_pcie_probe() + - PCI: j721e: Fix the value of .linkdown_irq_regfield for J784S4 + - PCI: layerscape: Fix arg_count to syscon_regmap_lookup_by_phandle_args() + - PCI: pciehp: Avoid unnecessary device replacement check + - PCI: Fix reference leak in pci_alloc_child_bus() + - PCI: Fix reference leak in pci_register_host_bridge() + - PCI: Fix wrong length of devres array + - phy: freescale: imx8m-pcie: assert phy reset and perst in power off + - pinctrl: qcom: Clear latched interrupt status when changing IRQ type + - pinctrl: samsung: add support for eint_fltcon_offset + - ring-buffer: Use flush_kernel_vmap_range() over flush_dcache_folio() + - s390/pci: Fix zpci_bus_is_isolated_vf() for non-VFs + - s390/virtio_ccw: Don't allocate/assign airqs for non-existing queues + - s390: Fix linker error when -no-pie option is unavailable + - sched_ext: create_dsq: Return -EEXIST on duplicate request + - selftests: mptcp: close fd_in before returning in main_loop + - selftests: mptcp: fix incorrect fd checks in main_loop + - spi: fsl-qspi: use devm function instead of driver remove + - spi: fsl-qspi: Fix double cleanup in probe error path + - thermal/drivers/mediatek/lvts: Disable monitor mode during suspend + - thermal/drivers/mediatek/lvts: Disable Stage 3 thermal threshold + - wifi: ath11k: update channel list in worker when wait flag is set + - arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists + - iommufd: Make attach_handle generic than fault specific + - iommufd: Fail replace if device has not been attached + - x86/e820: Fix handling of subpage regions when calculating nosave ranges in + e820__register_nosave_regions() + - Bluetooth: hci_uart: Fix another race during initialization + - Linux 6.14.3 + + * Plucky update: v6.14.3 upstream stable release (LP: #2108854) // + CVE-2025-37838 + - HSI: ssi_protocol: Fix use after free vulnerability in ssi_protocol Driver + Due to Race Condition + + * Introduce configfs-based interface for gpio-aggregator (LP: #2103496) + - SAUCE: gpio: aggregator: fix "_sysfs" prefix check in + gpio_aggregator_make_group() + - SAUCE: gpio: aggregator: Fix gpio_aggregator_line_alloc() checking + - SAUCE: gpio: aggregator: Return an error if there are no GPIOs in + gpio_aggregator_parse() + - SAUCE: gpio: aggregator: Fix error code in gpio_aggregator_activate() + - SAUCE: gpio: aggregator: Fix leak in gpio_aggregator_parse() + - SAUCE: selftests: gpio: gpio-aggregator: add a test case for _sysfs prefix + reservation + + * [SRU] Fix screen flickering in inverted display mode (LP: #2103617) + - drm/xe/display: Fix fbdev GGTT mapping handling. + + * System could not hit hardware sleep state with specific panel with AMD + KRK/STX under DC mode (LP: #2103480) + - drm/amd/display: Add and use new dm_prepare_suspend() callback + + * WARNING: CPU: 18 PID: 3683 at arch/powerpc/kvm/../../../virt/kvm/vfio.c Call + Traces seen when pci device is detached from the kvm guest (LP: #2104893) + - KVM: PPC: Enable CAP_SPAPR_TCE_VFIO on pSeries KVM guests + + * [SRU] Enable speaker/mic mute LEDs on Lenovo ideapad and thinkbook + (LP: #2106449) + - platform/x86:lenovo-wmi-hotkey-utilities.c: Support for mic and audio mute + LEDs + - [Config] Enable Lenovo wmi hotkey driver + + * OLED panel screen backlight brightness does not change with brightness + hotkey(F6&F7 Key) (LP: #2097818) + - drm/dp: Add eDP 1.5 bit definition + - drm/dp: Increase eDP display control capability size + - drm/i915/backlight: Use proper interface based on eDP version + - drm/i915/backlight: Check Luminance based brightness control for VESA + - drm/i915/backlight: Modify function to get VESA brightness in Nits + - drm/i915/backlight: Add function to change brightness in nits for VESA + - drm/i915/backlight: Setup nits based luminance via VESA + - drm/i915/backlight: Enable nits based luminance + + * Plucky update: v6.14.2 upstream stable release (LP: #2107212) + - fs: support O_PATH fds with FSCONFIG_SET_FD + - watch_queue: fix pipe accounting mismatch + - x86/mm/pat: cpa-test: fix length for CPA_ARRAY test + - m68k: sun3: Use str_read_write() helper in mmu_emu_handle_fault() + - m68k: sun3: Fix DEBUG_MMU_EMU build + - cpufreq: scpi: compare kHz instead of Hz + - seccomp: fix the __secure_computing() stub for !HAVE_ARCH_SECCOMP_FILTER + - smack: dont compile ipv6 code unless ipv6 is configured + - smack: ipv4/ipv6: tcp/dccp/sctp: fix incorrect child socket label + - sched: Cancel the slice protection of the idle entity + - sched/eevdf: Force propagating min_slice of cfs_rq when {en,de}queue tasks + - cpufreq: governor: Fix negative 'idle_time' handling in dbs_update() + - EDAC/igen6: Fix the flood of invalid error reports + - EDAC/{skx_common,i10nm}: Fix some missing error reports on Emerald Rapids + - x86/vdso: Fix latent bug in vclock_pages calculation + - x86/fpu: Fix guest FPU state buffer allocation size + - cpufreq/amd-pstate: Modify the min_perf calculation in adjust_perf callback + - cpufreq/amd-pstate: Pass min/max_limit_perf as min/max_perf to + amd_pstate_update + - cpufreq/amd-pstate: Convert all perf values to u8 + - cpufreq/amd-pstate: Add missing NULL ptr check in amd_pstate_update + - x86/fpu: Avoid copying dynamic FP state from init_task in + arch_dup_task_struct() + - rseq: Update kernel fields in lockstep with CONFIG_DEBUG_RSEQ=y + - x86/platform: Only allow CONFIG_EISA for 32-bit + - [Config] updateconfigs for HAVE_EISA + - x86/sev: Add missing RIP_REL_REF() invocations during sme_enable() + - lockdep/mm: Fix might_fault() lockdep check of current->mm->mmap_lock + - PM: sleep: Adjust check before setting power.must_resume + - cpufreq: tegra194: Allow building for Tegra234 + - RISC-V: KVM: Disable the kernel perf counter during configure + - kunit/stackinit: Use fill byte different from Clang i386 pattern + - watchdog/hardlockup/perf: Fix perf_event memory leak + - x86/split_lock: Fix the delayed detection logic + - selinux: Chain up tool resolving errors in install_policy.sh + - EDAC/ie31200: Fix the size of EDAC_MC_LAYER_CHIP_SELECT layer + - EDAC/ie31200: Fix the DIMM size mask for several SoCs + - EDAC/ie31200: Fix the error path order of ie31200_init() + - dma: Fix encryption bit clearing for dma_to_phys + - dma: Introduce generic dma_addr_*crypted helpers + - arm64: realm: Use aliased addresses for device DMA to shared buffers + - x86/resctrl: Fix allocation of cleanest CLOSID on platforms with no monitors + - cpuidle: Init cpuidle only for present CPUs + - thermal: int340x: Add NULL check for adev + - PM: sleep: Fix handling devices with direct_complete set on errors + - lockdep: Don't disable interrupts on RT in disable_irq_nosync_lockdep.*() + - cpufreq: Init cpufreq only for present CPUs + - perf/ring_buffer: Allow the EPOLLRDNORM flag for poll + - perf: Save PMU specific data in task_struct + - perf: Supply task information to sched_task() + - perf/x86/lbr: Fix shorter LBRs call stacks for the system-wide mode + - sched/deadline: Ignore special tasks when rebuilding domains + - sched/topology: Wrappers for sched_domains_mutex + - sched/deadline: Generalize unique visiting of root domains + - sched/deadline: Rebuild root domain accounting after every update + - x86/traps: Make exc_double_fault() consistently noreturn + - x86/fpu/xstate: Fix inconsistencies in guest FPU xfeatures + - x86/entry: Add __init to ia32_emulation_override_cmdline() + - RISC-V: KVM: Teardown riscv specific bits after kvm_exit + - regulator: pca9450: Fix enable register for LDO5 + - auxdisplay: MAX6959 should select BITREVERSE + - media: verisilicon: HEVC: Initialize start_bit field + - media: platform: allgro-dvt: unregister v4l2_device on the error path + - auxdisplay: panel: Fix an API misuse in panel.c + - platform/x86: lenovo-yoga-tab2-pro-1380-fastcharger: Make symbol static + - platform/x86: dell-uart-backlight: Make dell_uart_bl_serdev_driver static + - platform/x86: dell-ddv: Fix temperature calculation + - ASoC: cs35l41: check the return value from spi_setup() + - ASoC: amd: acp: Fix for enabling DMIC on acp platforms via _DSD entry + - HID: remove superfluous (and wrong) Makefile entry for + CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER + - ASoC: simple-card-utils: Don't use __free(device_node) at + graph_util_parse_dai() + - dt-bindings: vendor-prefixes: add GOcontroll + - ALSA: hda/realtek: Always honor no_shutup_pins + - ASoC: tegra: Use non-atomic timeout for ADX status register + - ASoC: ti: j721e-evm: Fix clock configuration for ti,j7200-cpb-audio + compatible + - ALSA: usb-audio: separate DJM-A9 cap lvl options + - ALSA: timer: Don't take register_mutex with copy_from/to_user() + - ALSA: hda/realtek: Fix built-in mic assignment on ASUS VivoBook X515UA + - wifi: rtw89: Correct immediate cfg_len calculation for scan_offload_be + - wifi: ath12k: fix skb_ext_desc leak in ath12k_dp_tx() error path + - wifi: ath12k: encode max Tx power in scan channel list command + - wifi: ath12k: Fix pdev lookup in WBM error processing + - wifi: ath9k: do not submit zero bytes to the entropy pool + - wifi: ath11k: fix wrong overriding for VHT Beamformee STS Capability + - arm64: dts: mediatek: mt8173-elm: Drop pmic's #address-cells and #size-cells + - arm64: dts: mediatek: mt8173: Fix some node names + - wifi: ath11k: update channel list in reg notifier instead reg worker + - ARM: dts: omap4-panda-a4: Add missing model and compatible properties + - f2fs: quota: fix to avoid warning in dquot_writeback_dquots() + - dlm: prevent NPD when writing a positive value to event_done + - wifi: ath11k: fix RCU stall while reaping monitor destination ring + - wifi: ath11k: add srng->lock for ath11k_hal_srng_* in monitor mode + - wifi: ath12k: Fix locking in "QMI firmware ready" error paths + - f2fs: fix to avoid panic once fallocation fails for pinfile + - scsi: mpt3sas: Reduce log level of ignore_delay_remove message to KERN_INFO + - md: ensure resync is prioritized over recovery + - md/raid1: fix memory leak in raid1_run() if no active rdev + - coredump: Fixes core_pipe_limit sysctl proc_handler + - io_uring/io-wq: eliminate redundant io_work_get_acct() calls + - io_uring/io-wq: cache work->flags in variable + - io_uring/io-wq: do not use bogus hash value + - io_uring: check for iowq alloc_workqueue failure + - io_uring/net: improve recv bundles + - firmware: arm_ffa: Refactor addition of partition information into XArray + - firmware: arm_ffa: Unregister the FF-A devices when cleaning up the + partitions + - arm64: dts: mediatek: mt6359: fix dtbs_check error for audio-codec + - scsi: mpi3mr: Fix locking in an error path + - scsi: mpt3sas: Fix a locking bug in an error path + - can: rockchip_canfd: rkcanfd_chip_fifo_setup(): remove duplicated setup of + RX FIFO + - jfs: reject on-disk inodes of an unsupported type + - jfs: add check read-only before txBeginAnon() call + - jfs: add check read-only before truncation in jfs_truncate_nolock() + - wifi: ath12k: Add missing htt_metadata flag in ath12k_dp_tx() + - wifi: rtw89: rtw8852b{t}: fix TSSI debug timestamps + - xfrm: delay initialization of offload path till its actually requested + - iommu/io-pgtable-dart: Only set subpage protection disable for DART 1 + - firmware: arm_ffa: Explicitly cast return value from FFA_VERSION before + comparison + - firmware: arm_ffa: Explicitly cast return value from NOTIFICATION_INFO_GET + - arm64: dts: renesas: r8a774c0: Re-add voltages to OPP table + - arm64: dts: renesas: r8a77990: Re-add voltages to OPP table + - firmware: arm_ffa: Skip the first/partition ID when parsing vCPU list + - arm64: dts: ti: k3-j722s-evm: Fix USB2.0_MUX_SEL to select Type-C + - wifi: ath12k: use link specific bss_conf as well in + ath12k_mac_vif_cache_flush() + - arm64: dts: imx8mp-skov: correct PMIC board limits + - arm64: dts: imx8mp-skov: operate CPU at 850 mV by default + - arm64: dts: mediatek: mt8390-genio-700-evk: Move common parts to dtsi + - arm64: dts: mediatek: mt8390-genio-common: Fix duplicated regulator name + - wifi: ath11k: Clear affinity hint before calling ath11k_pcic_free_irq() in + error path + - wifi: ath12k: Clear affinity hint before calling ath12k_pci_free_irq() in + error path + - f2fs: fix to set .discard_granularity correctly + - f2fs: add check for deleted inode + - arm64: dts: ti: k3-am62-verdin-dahlia: add Microphone Jack to sound card + - f2fs: fix potential deadloop in prepare_compress_overwrite() + - f2fs: fix to call f2fs_recover_quota_end() correctly + - md: fix mddev uaf while iterating all_mddevs list + - md/raid1,raid10: don't ignore IO flags + - md/md-bitmap: fix wrong bitmap_limit for clustermd when write sb + - tracing: Fix DECLARE_TRACE_CONDITION + - tools/rv: Keep user LDFLAGS in build + - arm64: dts: ti: k3-am62p: Enable AUDIO_REFCLKx + - arm64: dts: ti: k3-am62p: fix pinctrl settings + - arm64: dts: ti: k3-j722s: fix pinctrl settings + - wifi: rtw89: fw: correct debug message format in + rtw89_build_txpwr_trk_tbl_from_elm() + - wifi: rtw89: pci: correct ISR RDU bit for 8922AE + - blk-throttle: fix lower bps rate by throtl_trim_slice() + - soc: mediatek: mtk-mmsys: Fix MT8188 VDO1 DPI1 output selection + - soc: mediatek: mt8167-mmsys: Fix missing regval in all entries + - soc: mediatek: mt8365-mmsys: Fix routing table masks and values + - md/raid10: wait barrier before returning discard request with REQ_NOWAIT + - block: ensure correct integrity capability propagation in stacked devices + - block: Correctly initialize BLK_INTEGRITY_NOGENERATE and + BLK_INTEGRITY_NOVERIFY + - badblocks: Fix error shitf ops + - badblocks: factor out a helper try_adjacent_combine + - badblocks: attempt to merge adjacent badblocks during ack_all_badblocks + - badblocks: return error directly when setting badblocks exceeds 512 + - badblocks: return error if any badblock set fails + - badblocks: fix the using of MAX_BADBLOCKS + - badblocks: fix merge issue when new badblocks align with pre+1 + - badblocks: fix missing bad blocks on retry in _badblocks_check() + - badblocks: return boolean from badblocks_set() and badblocks_clear() + - badblocks: use sector_t instead of int to avoid truncation of badblocks + length + - firmware: arm_scmi: use ioread64() instead of ioread64_hi_lo() + - net: airoha: Fix lan4 support in airoha_qdma_get_gdm_port() + - iommu/amd: Fix header file + - iommu/vt-d: Fix system hang on reboot -f + - memory: mtk-smi: Add ostd setting for mt8192 + - gfs2: minor evict fix + - gfs2: skip if we cannot defer delete + - ARM: dts: imx6ul-tqma6ul1: Change include order to disable fec2 node + - arm64: dts: imx8mp: add AUDIO_AXI_CLK_ROOT to AUDIOMIX block + - arm64: dts: imx8mp: change AUDIO_AXI_CLK_ROOT freq. to 800MHz + - f2fs: fix to avoid accessing uninitialized curseg + - iommu: Handle race with default domain setup + - wifi: mac80211: remove SSID from ML reconf + - f2fs: fix to avoid running out of free segments + - block: fix adding folio to bio + - ext4: fix potential null dereference in ext4 kunit test + - ext4: convert EXT4_FLAGS_* defines to enum + - ext4: add EXT4_FLAGS_EMERGENCY_RO bit + - ext4: correct behavior under errors=remount-ro mode + - ext4: show 'emergency_ro' when EXT4_FLAGS_EMERGENCY_RO is set + - arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory + - arm64: dts: rockchip: Remove bluetooth node from rock-3a + - bus: qcom-ssc-block-bus: Remove some duplicated iounmap() calls + - bus: qcom-ssc-block-bus: Fix the error handling path of + qcom_ssc_block_bus_probe() + - arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max + - arm64: dts: rockchip: Fix PWM pinctrl names + - arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0 + - erofs: allow 16-byte volume name again + - ext4: add missing brelse() for bh2 in ext4_dx_add_entry() + - ext4: verify fast symlink length + - f2fs: fix missing discard for active segments + - scsi: hisi_sas: Fixed failure to issue vendor specific commands + - scsi: target: tcm_loop: Fix wrong abort tag + - ext4: introduce ITAIL helper + - ext4: fix out-of-bound read in ext4_xattr_inode_dec_ref_all() + - ext4: goto right label 'out_mmap_sem' in ext4_setattr() + - jbd2: fix off-by-one while erasing journal + - ata: libata: Fix NCQ Non-Data log not supported print + - wifi: nl80211: store chandef on the correct link when starting CAC + - wifi: mac80211: check basic rates validity in sta_link_apply_parameters + - wifi: cfg80211: init wiphy_work before allocating rfkill fails + - wifi: mwifiex: Fix premature release of RF calibration data. + - wifi: mwifiex: Fix RF calibration data download from file + - ice: health.c: fix compilation on gcc 7.5 + - ice: ensure periodic output start time is in the future + - ice: fix reservation of resources for RDMA when disabled + - virtchnl: make proto and filter action count unsigned + - ice: stop truncating queue ids when checking + - ice: validate queue quanta parameters to prevent OOB access + - ice: fix input validation for virtchnl BW + - ice: fix using untrusted value of pkt_len in ice_vc_fdir_parse_raw() + - idpf: check error for register_netdev() on init + - btrfs: get used bytes while holding lock at btrfs_reclaim_bgs_work() + - btrfs: fix reclaimed bytes accounting after automatic block group reclaim + - btrfs: fix block group refcount race in btrfs_create_pending_block_groups() + - btrfs: don't clobber ret in btrfs_validate_super() + - wifi: mt76: mt7915: fix possible integer overflows in + mt7915_muru_stats_show() + - igb: reject invalid external timestamp requests for 82580-based HW + - renesas: reject PTP_STRICT_FLAGS as unsupported + - net: lan743x: reject unsupported external timestamp requests + - broadcom: fix supported flag check in periodic output function + - ptp: ocp: reject unsupported periodic output flags + - nvmet: pci-epf: Always configure BAR0 as 64-bit + - jbd2: add a missing data flush during file and fs synchronization + - ext4: define ext4_journal_destroy wrapper + - ext4: avoid journaling sb update on error if journal is destroying + - eth: bnxt: fix out-of-range access of vnic_info array + - net: Remove RTNL dance for SIOCBRADDIF and SIOCBRDELIF. + - netfilter: nfnetlink_queue: Initialize ctx to avoid memory allocation error + - netfilter: nf_tables: Only use nf_skip_indirect_calls() when + MITIGATION_RETPOLINE + - ax25: Remove broken autobind + - net/mlx5e: Fix ethtool -N flow-type ip4 to RSS context + - bnxt_en: Mask the bd_cnt field in the TX BD properly + - bnxt_en: Linearize TX SKB if the fragments exceed the max + - net: dsa: mv88e6xxx: fix atu_move_port_mask for 6341 family + - net: dsa: mv88e6xxx: enable PVT for 6321 switch + - net: dsa: mv88e6xxx: enable .port_set_policy() for 6320 family + - net: dsa: mv88e6xxx: fix VTU methods for 6320 family + - net: dsa: mv88e6xxx: enable STU methods for 6320 family + - mlxsw: spectrum_acl_bloom_filter: Workaround for some LLVM versions + - net: dsa: sja1105: fix displaced ethtool statistics counters + - net: dsa: sja1105: reject other RX filters than + HWTSTAMP_FILTER_PTP_V2_L2_EVENT + - net: dsa: sja1105: fix kasan out-of-bounds warning in + sja1105_table_delete_entry() + - net/mlx5: LAG, reload representors on LAG creation failure + - net/mlx5: Start health poll after enable hca + - vmxnet3: unregister xdp rxq info in the reset path + - bonding: check xdp prog when set bond mode + - ibmvnic: Use kernel helpers for hex dumps + - net: fix NULL pointer dereference in l3mdev_l3_rcv + - virtio_net: Fix endian with virtio_net_ctrl_rss + - Bluetooth: Add quirk for broken READ_VOICE_SETTING + - Bluetooth: Add quirk for broken READ_PAGE_SCAN_TYPE + - Bluetooth: btusb: Fix regression in the initialization of fake Bluetooth + controllers + - Bluetooth: hci_core: Enable buffer flow control for SCO/eSCO + - Bluetooth: HCI: Add definition of hci_rp_remote_name_req_cancel + - rwonce: handle KCSAN like KASAN in read_word_at_a_time() + - net: dsa: microchip: fix DCB apptrust configuration on KSZ88x3 + - Bluetooth: btnxpuart: Fix kernel panic during FW release + - Bluetooth: hci_event: Fix handling of HCI_EV_LE_DIRECT_ADV_REPORT + - net: Fix the devmem sock opts and msgs for parisc + - net: libwx: fix Tx descriptor content for some tunnel packets + - net: libwx: fix Tx L4 checksum + - rwonce: fix crash by removing READ_ONCE() for unaligned read + - drm/bridge: ti-sn65dsi86: Fix multiple instances + - drm/ssd130x: Set SPI .id_table to prevent an SPI core warning + - accel/amdxdna: Return error when setting clock failed for npu1 + - drm/panthor: Fix a race between the reset and suspend path + - drm/ssd130x: fix ssd132x encoding + - drm/ssd130x: ensure ssd132x pitch is correct + - drm/dp_mst: Fix drm RAD print + - drm/bridge: it6505: fix HDCP V match check is not performed correctly + - drm/panthor: Fix race condition when gathering fdinfo group samples + - drm: xlnx: zynqmp: Fix max dma segment size + - drm: xlnx: zynqmp_dpsub: Add NULL check in zynqmp_audio_init + - drm: zynqmp_dp: Fix a deadlock in zynqmp_dp_ignore_hpd_set() + - drm/vkms: Fix use after free and double free on init error + - gpu: cdns-mhdp8546: fix call balance of mhdp->clk handling routines + - drm/amdgpu: refine smu send msg debug log format + - drm/amdgpu/umsch: remove vpe test from umsch + - drm/amdgpu/umsch: declare umsch firmware + - drm/amdgpu/umsch: fix ucode check + - drm/amdgpu/vcn5.0.1: use correct dpm helper + - PCI: Use downstream bridges for distributing resources + - PCI: Remove add_align overwrite unrelated to size0 + - PCI: Simplify size1 assignment logic + - PCI: Allow relaxed bridge window tail sizing for optional resources + - drm/mediatek: mtk_hdmi: Unregister audio platform device on failure + - drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member + - drm/amdgpu: Replace Mutex with Spinlock for RLCG register access to avoid + Priority Inversion in SRIOV + - PCI/ASPM: Fix link state exit during switch upstream function removal + - drm/panel: ilitek-ili9882t: fix GPIO name in error message + - PCI/ACS: Fix 'pci=config_acs=' parameter + - drm/amd/display: fix an indent issue in DML21 + - drm/msm/dpu: don't use active in atomic_check() + - drm/msm/dsi/phy: Program clock inverters in correct register + - drm/msm/dsi: Use existing per-interface slice count in DSC timing + - drm/msm/dsi: Set PHY usescase (and mode) before registering DSI host + - drm/msm/dpu: Fall back to a single DSC encoder (1:1:1) on small SoCs + - drm/msm/dpu: Remove arbitrary limit of 1 interface in DSC topology + - drm/msm/gem: Fix error code msm_parse_deps() + - drm/amdkfd: Fix Circular Locking Dependency in + 'svm_range_cpu_invalidate_pagetables' + - PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC + - PCI: cadence-ep: Fix the driver to send MSG TLP for INTx without data + payload + - PCI: brcmstb: Set generation limit before PCIe link up + - PCI: brcmstb: Use internal register to change link capability + - PCI: brcmstb: Fix error path after a call to regulator_bulk_get() + - PCI: brcmstb: Fix potential premature regulator disabling + - selftests/pcie_bwctrl: Add 'set_pcie_speed.sh' to TEST_PROGS + - PCI/portdrv: Only disable pciehp interrupts early when needed + - PCI: Avoid reset when disabled via sysfs + - drm/msm/dpu: move needs_cdm setting to dpu_encoder_get_topology() + - drm/msm/dpu: simplify dpu_encoder_get_topology() interface + - drm/msm/dpu: don't set crtc_state->mode_changed from atomic_check() + - drm/panthor: Update CS_STATUS_ defines to correct values + - drm/file: Add fdinfo helper for printing regions with prefix + - drm/panthor: Expose size of driver internal BO's over fdinfo + - drm/panthor: Replace sleep locks with spinlocks in fdinfo path + - drm/panthor: Avoid sleep locking in the internal BO size path + - drm/panthor: Clean up FW version information display + - drm/amd/display: fix type mismatch in CalculateDynamicMetadataParameters() + - drm/msm/a6xx: Fix a6xx indexed-regs in devcoreduump + - powerpc/perf: Fix ref-counting on the PMU 'vpa_pmu' + - misc: pci_endpoint_test: Fix pci_endpoint_test_bars_read_bar() error + handling + - misc: pci_endpoint_test: Handle BAR sizes larger than INT_MAX + - PCI: endpoint: pci-epf-test: Handle endianness properly + - crypto: powerpc: Mark ghashp8-ppc.o as an OBJECT_FILES_NON_STANDARD + - powerpc/kexec: fix physical address calculation in clear_utlb_entry() + - PCI: Remove stray put_device() in pci_register_host_bridge() + - PCI: xilinx-cpm: Fix IRQ domain leak in error path of probe + - drm/mediatek: Fix config_updating flag never false when no mbox channel + - drm/mediatek: dp: drm_err => dev_err in HPD path to avoid NULL ptr + - drm/mediatek: dsi: fix error codes in mtk_dsi_host_transfer() + - drm/amd/display: avoid NPD when ASIC does not support DMUB + - PCI: dwc: ep: Return -ENOMEM for allocation failures + - PCI: histb: Fix an error handling path in histb_pcie_probe() + - PCI: Fix BAR resizing when VF BARs are assigned + - drm/amdgpu/mes: optimize compute loop handling + - drm/amdgpu/mes: enable compute pipes across all MEC + - PCI: pciehp: Don't enable HPIE when resuming in poll mode + - PCI/bwctrl: Fix pcie_bwctrl_select_speed() return type + - io_uring/net: only import send_zc buffer once + - PCI: Fix NULL dereference in SR-IOV VF creation error path + - io_uring: use lockless_cq flag in io_req_complete_post() + - io_uring: fix retry handling off iowq + - fbdev: au1100fb: Move a variable assignment behind a null pointer check + - dummycon: fix default rows/cols + - mdacon: rework dependency list + - fbdev: sm501fb: Add some geometry checks. + - crypto: iaa - Test the correct request flag + - crypto: qat - set parity error mask for qat_420xx + - crypto: tegra - Use separate buffer for setkey + - crypto: tegra - Do not use fixed size buffers + - crypto: tegra - check return value for hash do_one_req + - crypto: tegra - Transfer HASH init function to crypto engine + - crypto: tegra - Fix HASH intermediate result handling + - crypto: bpf - Add MODULE_DESCRIPTION for skcipher + - crypto: tegra - Use HMAC fallback when keyslots are full + - clk: amlogic: gxbb: drop incorrect flag on 32k clock + - crypto: hisilicon/sec2 - fix for aead authsize alignment + - crypto: hisilicon/sec2 - fix for sec spec check + - RDMA/mlx5: Fix page_size variable overflow + - remoteproc: core: Clear table_sz when rproc_shutdown + - of: property: Increase NR_FWNODE_REFERENCE_ARGS + - pinctrl: renesas: rzg2l: Suppress binding attributes + - remoteproc: qcom_q6v5_pas: Make single-PD handling more robust + - libbpf: Fix hypothetical STT_SECTION extern NULL deref case + - drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock + - selftests/bpf: Fix string read in strncmp benchmark + - x86/mm/pat: Fix VM_PAT handling when fork() fails in copy_page_range() + - clk: renesas: r8a08g045: Check the source of the CPU PLL settings + - remoteproc: qcom: pas: add minidump_id to SC7280 WPSS + - clk: samsung: Fix UBSAN panic in samsung_clk_init() + - pinctrl: nuvoton: npcm8xx: Fix error handling in npcm8xx_gpio_fw() + - crypto: tegra - Fix CMAC intermediate result handling + - clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock + - selftests/bpf: Fix runqslower cross-endian build + - s390: Remove ioremap_wt() and pgprot_writethrough() + - RDMA/mana_ib: Ensure variable err is initialized + - crypto: tegra - Set IV to NULL explicitly for AES ECB + - remoteproc: qcom_q6v5_pas: Use resource with CX PD for MSM8226 + - crypto: tegra - finalize crypto req on error + - crypto: tegra - Reserve keyslots to allocate dynamically + - bpf: Use preempt_count() directly in bpf_send_signal_common() + - lib: 842: Improve error handling in sw842_compress() + - pinctrl: renesas: rza2: Fix missing of_node_put() call + - pinctrl: renesas: rzg2l: Fix missing of_node_put() call + - RDMA/mlx5: Fix MR cache initialization error flow + - selftests/bpf: Fix freplace_link segfault in tailcalls prog test + - clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parent + - RDMA/core: Don't expose hw_counters outside of init net namespace + - RDMA/mlx5: Fix calculation of total invalidated pages + - RDMA/erdma: Prevent use-after-free in erdma_accept_newconn() + - remoteproc: qcom_q6v5_mss: Handle platforms with one power domain + - power: supply: bq27xxx_battery: do not update cached flags prematurely + - leds: st1202: Check for error code from devm_mutex_init() call + - crypto: api - Fix larval relookup type and mask + - IB/mad: Check available slots before posting receive WRs + - pinctrl: tegra: Set SFIO mode to Mux Register + - clk: amlogic: g12b: fix cluster A parent data + - clk: amlogic: gxbb: drop non existing 32k clock parent + - selftests/bpf: Select NUMA_NO_NODE to create map + - rust: fix signature of rust_fmt_argument + - crypto: tegra - Fix format specifier in tegra_sha_prep_cmd() + - libbpf: Add namespace for errstr making it libbpf_errstr + - clk: mmp: Fix NULL vs IS_ERR() check + - pinctrl: npcm8xx: Fix incorrect struct npcm8xx_pincfg assignment + - samples/bpf: Fix broken vmlinux path for VMLINUX_BTF + - crypto: qat - remove access to parity register for QAT GEN4 + - clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parents + - clk: amlogic: g12a: fix mmc A peripheral clock + - pinctrl: bcm2835: don't -EINVAL on alternate funcs from get_direction() + - x86/entry: Fix ORC unwinder for PUSH_REGS with save_ret=1 + - power: supply: max77693: Fix wrong conversion of charge input threshold + value + - crypto: api - Call crypto_alg_put in crypto_unregister_alg + - clk: stm32f4: fix an uninitialized variable + - crypto: nx - Fix uninitialised hv_nxc on error + - clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable() + - bpf: Fix array bounds error with may_goto + - RDMA/mlx5: Fix mlx5_poll_one() cur_qp update flow + - pinctrl: renesas: rzv2m: Fix missing of_node_put() call + - clk: qcom: ipq5424: fix software and hardware flow control error of UART + - mfd: sm501: Switch to BIT() to mitigate integer overflows + - leds: Fix LED_OFF brightness race + - x86/dumpstack: Fix inaccurate unwinding from exception stacks due to + misplaced assignment + - RDMA/core: Fix use-after-free when rename device name + - crypto: hisilicon/sec2 - fix for aead auth key length + - pinctrl: intel: Fix wrong bypass assignment in intel_pinctrl_probe_pwm() + - clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock + - libbpf: Fix accessing BTF.ext core_relo header + - perf stat: Fix find_stat for mixed legacy/non-legacy events + - perf: Always feature test reallocarray + - w1: fix NULL pointer dereference in probe + - staging: gpib: Add missing interface entry point + - staging: gpib: Fix pr_err format warning + - usb: typec: thunderbolt: Fix loops that iterate TYPEC_PLUG_SOP_P and + TYPEC_PLUG_SOP_PP + - usb: typec: thunderbolt: Remove IS_ERR check for plug + - iio: dac: adi-axi-dac: modify stream enable + - perf test: Fix Hwmon PMU test endianess issue + - perf stat: Don't merge counters purely on name + - fs/ntfs3: Factor out ntfs_{create/remove}_procdir() + - fs/ntfs3: Factor out ntfs_{create/remove}_proc_root() + - fs/ntfs3: Fix 'proc_info_root' leak when init ntfs failed + - fs/ntfs3: Update inode->i_mapping->a_ops on compression state + - iio: light: veml6030: extend regmap to support regfields + - iio: gts-helper: export iio_gts_get_total_gain() + - iio: light: veml6030: fix scale to conform to ABI + - iio: adc: ad7124: Micro-optimize channel disabling + - iio: adc: ad7124: Really disable all channels at probe time + - phy: phy-rockchip-samsung-hdptx: Don't use dt aliases to determine phy-id + - perf tools: Add skip check in tool_pmu__event_to_str() + - isofs: fix KMSAN uninit-value bug in do_isofs_readdir() + - perf tests: Fix Tool PMU test segfault + - soundwire: slave: fix an OF node reference leak in soundwire slave device + - staging: gpib: Fix cb7210 pcmcia Oops + - perf report: Switch data file correctly in TUI + - perf report: Fix input reload/switch with symbol sort key + - greybus: gb-beagleplay: Add error handling for gb_greybus_init + - coresight: catu: Fix number of pages while using 64k pages + - vhost-scsi: Fix handling of multiple calls to vhost_scsi_set_endpoint + - coresight-etm4x: add isb() before reading the TRCSTATR + - perf pmus: Restructure pmu_read_sysfs to scan fewer PMUs + - perf pmu: Dynamically allocate tool PMU + - perf pmu: Don't double count common sysfs and json events + - tools/x86: Fix linux/unaligned.h include path in lib/insn.c + - perf build: Fix in-tree build due to symbolic link + - ucsi_ccg: Don't show failed to get FW build information error + - iio: accel: mma8452: Ensure error return on failure to matching oversampling + ratio + - iio: accel: msa311: Fix failure to release runtime pm if direct mode claim + fails. + - iio: backend: make sure to NULL terminate stack buffer + - iio: core: Rework claim and release of direct mode to work with sparse. + - iio: adc: ad7173: Grab direct mode for calibration + - iio: adc: ad7192: Grab direct mode for calibration + - perf arm-spe: Fix load-store operation checking + - perf bench: Fix perf bench syscall loop count + - perf machine: Fixup kernel maps ends after adding extra maps + - usb: xhci: correct debug message page size calculation + - fs/ntfs3: Fix a couple integer overflows on 32bit systems + - fs/ntfs3: Prevent integer overflow in hdr_first_de() + - perf test: Add timeout to datasym workload + - perf tests: Fix data symbol test with LTO builds + - NFSD: Fix callback decoder status codes + - soundwire: take in count the bandwidth of a prepared stream + - dmaengine: fsl-edma: cleanup chan after dma_async_device_unregister + - dmaengine: fsl-edma: free irq correctly in remove path + - dmaengine: ae4dma: Use the MSI count and its corresponding IRQ number + - dmaengine: ptdma: Utilize the AE4DMA engine's multi-queue functionality + - iio: adc: ad_sigma_delta: Disable channel after calibration + - iio: adc: ad4130: Fix comparison of channel setups + - iio: adc: ad7124: Fix comparison of channel configs + - iio: adc: ad7173: Fix comparison of channel configs + - iio: adc: ad7768-1: set MOSI idle state to prevent accidental reset + - iio: light: Add check for array bounds in veml6075_read_int_time_ms + - perf debug: Avoid stack overflow in recursive error message + - perf evlist: Add success path to evlist__create_syswide_maps + - perf evsel: tp_format accessing improvements + - perf x86/topdown: Fix topdown leader sampling test error on hybrid + - perf units: Fix insufficient array space + - perf test stat_all_pmu.sh: Correctly check 'perf stat' result + - kernel/events/uprobes: handle device-exclusive entries correctly in + __replace_page() + - kexec: initialize ELF lowest address to ULONG_MAX + - ocfs2: validate l_tree_depth to avoid out-of-bounds access + - reboot: replace __hw_protection_shutdown bool action parameter with an enum + - reboot: reboot, not shutdown, on hw_protection_reboot timeout + - arch/powerpc: drop GENERIC_PTDUMP from mpc885_ads_defconfig + - writeback: let trace_balance_dirty_pages() take struct dtc as parameter + - writeback: fix calculations in trace_balance_dirty_pages() for cgwb + - scripts/gdb/linux/symbols.py: address changes to module_sect_attrs + - NFSv4: Don't trigger uneccessary scans for return-on-close delegations + - NFSv4: Avoid unnecessary scans of filesystems for returning delegations + - NFSv4: Avoid unnecessary scans of filesystems for expired delegations + - NFSv4: Avoid unnecessary scans of filesystems for delayed delegations + - NFS: fix open_owner_id_maxsz and related fields. + - fuse: fix dax truncate/punch_hole fault path + - selftests/mm/cow: fix the incorrect error handling + - um: Pass the correct Rust target and options with gcc + - um: remove copy_from_kernel_nofault_allowed + - um: hostfs: avoid issues on inode number reuse by host + - i3c: master: svc: Fix missing the IBI rules + - perf python: Fixup description of sample.id event member + - perf python: Decrement the refcount of just created event on failure + - perf python: Don't keep a raw_data pointer to consumed ring buffer space + - perf python: Check if there is space to copy all the event + - perf dso: fix dso__is_kallsyms() check + - perf: intel-tpebs: Fix incorrect usage of zfree() + - perf pmu: Handle memory failure in tool_pmu__new() + - staging: rtl8723bs: select CONFIG_CRYPTO_LIB_AES + - staging: vchiq_arm: Register debugfs after cdev + - staging: vchiq_arm: Fix possible NPR of keep-alive thread + - staging: vchiq_arm: Stop kthreads if vchiq cdev register fails + - tty: n_tty: use uint for space returned by tty_write_room() + - perf vendor events arm64 AmpereOneX: Fix frontend_bound calculation + - fs/procfs: fix the comment above proc_pid_wchan() + - perf tools: Fix is_compat_mode build break in ppc64 + - perf tools: annotate asm_pure_loop.S + - perf bpf-filter: Fix a parsing error with comma + - objtool: Handle various symbol types of rodata + - objtool: Handle different entry size of rodata + - objtool: Handle PC relative relocation type + - objtool: Fix detection of consecutive jump tables on Clang 20 + - thermal: core: Remove duplicate struct declaration + - objtool, spi: amd: Fix out-of-bounds stack access in amd_set_spi_freq() + - objtool, nvmet: Fix out-of-bounds stack access in nvmet_ctrl_state_show() + - objtool, media: dib8000: Prevent divide-by-zero in dib8000_set_dds() + - NFS: Shut down the nfs_client only after all the superblocks + - smb: client: Fix netns refcount imbalance causing leaks and use-after-free + - exfat: fix the infinite loop in exfat_find_last_cluster() + - exfat: fix missing shutdown check + - rtnetlink: Allocate vfinfo size for VF GUIDs when supported + - rndis_host: Flag RNDIS modems as WWAN devices + - ksmbd: use aead_request_free to match aead_request_alloc + - ksmbd: fix multichannel connection failure + - ksmbd: fix r_count dec/increment mismatch + - net/mlx5e: SHAMPO, Make reserved size independent of page size + - ring-buffer: Fix bytes_dropped calculation issue + - objtool: Fix segfault in ignore_unreachable_insn() + - LoongArch: Fix help text of CMDLINE_EXTEND in Kconfig + - LoongArch: Fix device node refcount leak in fdt_cpu_clk_init() + - LoongArch: Rework the arch_kgdb_breakpoint() implementation + - ACPI: processor: idle: Return an error if both P_LVL{2,3} idle states are + invalid + - net: phy: broadcom: Correct BCM5221 PHY model detection + - octeontx2-af: Fix mbox INTR handler when num VFs > 64 + - octeontx2-af: Free NIX_AF_INT_VEC_GEN irq + - objtool: Fix verbose disassembly if CROSS_COMPILE isn't set + - sched/smt: Always inline sched_smt_active() + - context_tracking: Always inline ct_{nmi,irq}_{enter,exit}() + - rcu-tasks: Always inline rcu_irq_work_resched() + - objtool/loongarch: Add unwind hints in prepare_frametrace() + - nfs: Add missing release on error in nfs_lock_and_join_requests() + - rtc: renesas-rtca3: Disable interrupts only if the RTC is enabled + - spufs: fix a leak on spufs_new_file() failure + - spufs: fix gang directory lifetimes + - spufs: fix a leak in spufs_create_context() + - fs/9p: fix NULL pointer dereference on mkdir + - riscv: ftrace: Add parentheses in macro definitions of make_call_t0 and + make_call_ra + - riscv: Fix the __riscv_copy_vec_words_unaligned implementation + - riscv: Fix missing __free_pages() in check_vector_unaligned_access() + - riscv: fgraph: Select HAVE_FUNCTION_GRAPH_TRACER depends on + HAVE_DYNAMIC_FTRACE_WITH_ARGS + - ntb_hw_switchtec: Fix shift-out-of-bounds in switchtec_ntb_mw_set_trans + - ntb: intel: Fix using link status DB's + - riscv: fgraph: Fix stack layout to match __arch_ftrace_regs argument of + ftrace_return_to_handler + - riscv: Annotate unaligned access init functions + - riscv: Fix riscv_online_cpu_vec + - riscv: Fix check_unaligned_access_all_cpus + - riscv: Change check_unaligned_access_speed_all_cpus to void + - riscv: Fix set up of cpu hotplug callbacks + - riscv: Fix set up of vector cpu hotplug callback + - firmware: cs_dsp: Ensure cs_dsp_load[_coeff]() returns 0 on success + - ALSA: hda/realtek: Fix built-in mic breakage on ASUS VivoBook X515JA + - RISC-V: errata: Use medany for relocatable builds + - x86/uaccess: Improve performance by aligning writes to 8 bytes in + copy_user_generic(), on non-FSRM/ERMS CPUs + - ublk: make sure ubq->canceling is set when queue is frozen + - s390/entry: Fix setting _CIF_MCCK_GUEST with lowcore relocation + - ASoC: codecs: rt5665: Fix some error handling paths in rt5665_probe() + - spi: cadence: Fix out-of-bounds array access in cdns_mrvl_xspi_setup_clock() + - riscv: Fix hugetlb retrieval of number of ptes in case of !present pte + - riscv/kexec_file: Handle R_RISCV_64 in purgatory relocator + - riscv/purgatory: 4B align purgatory_start + - nvme/ioctl: don't warn on vectorized uring_cmd with fixed buffer + - nvme-pci: skip nvme_write_sq_db on empty rqlist + - ASoC: imx-card: Add NULL check in imx_card_probe() + - spi: bcm2835: Do not call gpiod_put() on invalid descriptor + - ALSA: hda/realtek: Fix built-in mic on another ASUS VivoBook model + - spi: bcm2835: Restore native CS probing when pinctrl-bcm2835 is absent + - xsk: Add launch time hardware offload support to XDP Tx metadata + - igc: Refactor empty frame insertion for launch time support + - igc: Add launch time support to XDP ZC + - igc: Fix TX drops in XDP ZC + - e1000e: change k1 configuration on MTP and later platforms + - ixgbe: fix media type detection for E610 device + - idpf: fix adapter NULL pointer dereference on reboot + - netfilter: nft_set_hash: GC reaps elements with conncount for dynamic sets + only + - netfilter: nf_tables: don't unregister hook when table is dormant + - netlabel: Fix NULL pointer exception caused by CALIPSO on IPv4 sockets + - net_sched: skbprio: Remove overly strict queue assertions + - sctp: add mutual exclusion in proc_sctp_do_udp_port() + - net: airoha: Fix qid report in airoha_tc_get_htb_get_leaf_queue() + - net: airoha: Fix ETS priomap validation + - net: mvpp2: Prevent parser TCAM memory corruption + - rtnetlink: Use register_pernet_subsys() in rtnl_net_debug_init(). + - udp: Fix multiple wraparounds of sk->sk_rmem_alloc. + - udp: Fix memory accounting leak. + - vsock: avoid timeout during connect() if the socket is closing + - tunnels: Accept PACKET_HOST in skb_tunnel_check_pmtu(). + - xsk: Fix __xsk_generic_xmit() error code when cq is full + - net: decrease cached dst counters in dst_release + - netfilter: nft_tunnel: fix geneve_opt type confusion addition + - sfc: rip out MDIO support + - sfc: fix NULL dereferences in ef100_process_design_param() + - ipv6: fix omitted netlink attributes when using RTEXT_FILTER_SKIP_STATS + - net: dsa: mv88e6xxx: propperly shutdown PPU re-enable timer on destroy + - net: fix geneve_opt length integer overflow + - ipv6: Start path selection from the first nexthop + - ipv6: Do not consider link down nexthops in path selection + - arcnet: Add NULL check in com20020pci_probe() + - net: ibmveth: make veth_pool_store stop hanging + - netlink: specs: rt_route: pull the ifa- prefix out of the names + - tools/power turbostat: Allow Zero return value for some RAPL registers + - kbuild: deb-pkg: don't set KBUILD_BUILD_VERSION unconditionally + - drm/xe: Fix unmet direct dependencies warning + - drm/amdgpu/gfx11: fix num_mec + - drm/amdgpu/gfx12: fix num_mec + - perf/core: Fix child_total_time_enabled accounting bug at task exit + - tools/power turbostat: report CoreThr per measurement interval + - tools/power turbostat: Restore GFX sysfs fflush() call + - staging: gpib: ni_usb console messaging cleanup + - staging: gpib: Fix Oops after disconnect in ni_usb + - staging: gpib: agilent usb console messaging cleanup + - staging: gpib: Fix Oops after disconnect in agilent usb + - tty: serial: fsl_lpuart: Use u32 and u8 for register variables + - tty: serial: fsl_lpuart: use port struct directly to simply code + - tty: serial: fsl_lpuart: Fix unused variable 'sport' build warning + - tty: serial: lpuart: only disable CTS instead of overwriting the whole + UARTMODIR register + - usbnet:fix NPE during rx_complete + - rust: Fix enabling Rust and building with GCC for LoongArch + - LoongArch: Increase ARCH_DMA_MINALIGN up to 16 + - LoongArch: Increase MAX_IO_PICS up to 8 + - LoongArch: BPF: Fix off-by-one error in build_prologue() + - LoongArch: BPF: Don't override subprog's return value + - LoongArch: BPF: Use move_addr() for BPF_PSEUDO_FUNC + - x86/hyperv: Fix check of return value from snp_set_vmsa() + - KVM: x86: block KVM_CAP_SYNC_REGS if guest state is protected + - x86/microcode/AMD: Fix __apply_microcode_amd()'s return value + - x86/mce: use is_copy_from_user() to determine copy-from-user context + - x86/paravirt: Move halt paravirt calls under CONFIG_PARAVIRT + - x86/tdx: Fix arch_safe_halt() execution for TDX VMs + - ACPI: x86: Extend Lenovo Yoga Tab 3 quirk with skip GPIO event-handlers + - platform/x86: thinkpad_acpi: disable ACPI fan access for T495* and E560 + - platform/x86: ISST: Correct command storage data length + - ntb_perf: Delete duplicate dmaengine_unmap_put() call in perf_copy_chunk() + - perf/x86/intel: Apply static call for drain_pebs + - perf/x86/intel: Avoid disable PMU if !cpuc->enabled in sample read + - uprobes/x86: Harden uretprobe syscall trampoline check + - bcachefs: bch2_ioctl_subvolume_destroy() fixes + - x86/Kconfig: Add cmpxchg8b support back to Geode CPUs + - x86/tsc: Always save/restore TSC sched_clock() on suspend/resume + - x86/mm: Fix flush_tlb_range() when used for zapping normal PMDs + - ACPI: platform-profile: Fix CFI violation when accessing sysfs files + - wifi: mt76: mt7925: remove unused acpi function for clc + - acpi: nfit: fix narrowing conversion in acpi_nfit_ctl + - ACPI: resource: Skip IRQ override on ASUS Vivobook 14 X1404VAP + - ACPI: video: Handle fetching EDID as ACPI_TYPE_PACKAGE + - ARM: 9443/1: Require linker to support KEEP within OVERLAY for DCE + - [Config] updateconfigs for LD_CAN_USE_KEEP_IN_OVERLAY + - ARM: 9444/1: add KEEP() keyword to ARM_VECTORS + - media: omap3isp: Handle ARM dma_iommu_mapping + - Remove unnecessary firmware version check for gc v9_4_2 + - mmc: omap: Fix memory leak in mmc_omap_new_slot + - mmc: sdhci-pxav3: set NEED_RSP_BUSY capability + - mmc: sdhci-omap: Disable MMC_CAP_AGGRESSIVE_PM for eMMC/SD + - KVM: SVM: Don't change target vCPU state on AP Creation VMGEXIT error + - ksmbd: add bounds check for durable handle context + - ksmbd: add bounds check for create lease context + - ksmbd: fix use-after-free in ksmbd_sessions_deregister() + - ksmbd: fix session use-after-free in multichannel connection + - ksmbd: fix overflow in dacloffset bounds check + - ksmbd: validate zero num_subauth before sub_auth is accessed + - ksmbd: fix null pointer dereference in alloc_preauth_hash() + - exfat: fix random stack corruption after get_block + - exfat: fix potential wrong error return from get_block + - tracing: Fix use-after-free in print_graph_function_flags during tracer + switching + - tracing: Ensure module defining synth event cannot be unloaded while tracing + - tracing: Fix synth event printk format for str fields + - tracing/osnoise: Fix possible recursive locking for cpus_read_lock() + - tracing: Verify event formats that have "%*p.." + - mm/gup: reject FOLL_SPLIT_PMD with hugetlb VMAs + - arm64: Don't call NULL in do_compat_alignment_fixup() + - wifi: mt76: mt7921: fix kernel panic due to null pointer dereference + - ext4: don't over-report free space or inodes in statvfs + - ext4: fix OOB read when checking dotdot dir + - PCI/bwctrl: Fix NULL pointer dereference on bus number exhaustion + - jfs: fix slab-out-of-bounds read in ea_get() + - jfs: add index corruption check to DT_GETPAGE() + - mm: zswap: fix crypto_free_acomp() deadlock in zswap_cpu_comp_dead() + - exec: fix the racy usage of fs_struct->in_exec + - media: vimc: skip .s_stream() for stopped entities + - media: streamzap: fix race between device disconnection and urb callback + - nfsd: don't ignore the return code of svc_proc_register() + - nfsd: allow SC_STATUS_FREEABLE when searching via nfs4_lookup_stateid() + - nfsd: put dl_stid if fail to queue dl_recall + - NFSD: Add a Kconfig setting to enable delegated timestamps + - [Config] disable new feature NFSD_V4_DELEG_TIMESTAMPS + - nfsd: fix management of listener transports + - NFSD: nfsd_unlink() clobbers non-zero status returned from + fh_fill_pre_attrs() + - NFSD: Never return NFS4ERR_FILE_OPEN when removing a directory + - NFSD: Skip sending CB_RECALL_ANY when the backchannel isn't up + - perf pmu: Rename name matching for no suffix or wildcard variants + - include/{topology,cpuset}: Move dl_rebuild_rd_accounting to cpuset.h + - tracing: Do not use PERF enums when perf is not defined + - ASoC: mediatek: mt6359: Fix DT parse error due to wrong child node name + - Linux 6.14.2 + + * Plucky update: v6.14.1 upstream stable release (LP: #2106661) + - ALSA: usb-audio: Add quirk for Plantronics headsets to fix control names + - HID: hid-plantronics: Add mic mute mapping and generalize quirks + - atm: Fix NULL pointer dereference + - cgroup/rstat: Fix forceidle time in cpu.stat + - netfilter: socket: Lookup orig tuple for IPv6 SNAT + - ALSA: hda/realtek: Support mute LED on HP Laptop 15s-du3xxx + - ALSA: hda/realtek: Bass speaker fixup for ASUS UM5606KA + - counter: stm32-lptimer-cnt: fix error handling when enabling + - counter: microchip-tcb-capture: Fix undefined counter channel state on probe + - tty: serial: 8250: Add some more device IDs + - tty: serial: 8250: Add Brainboxes XC devices + - tty: serial: fsl_lpuart: disable transmitter before changing RS485 related + registers + - net: usb: qmi_wwan: add Telit Cinterion FN990B composition + - net: usb: qmi_wwan: add Telit Cinterion FE990B composition + - net: usb: usbnet: restore usb%d name exception for local mac addresses + - usb: xhci: Don't skip on Stopped - Length Invalid + - usb: xhci: Apply the link chain quirk on NEC isoc endpoints + - memstick: rtsx_usb_ms: Fix slab-use-after-free in rtsx_usb_ms_drv_remove + - perf tools: Fix up some comments and code to properly use the event_source + bus + - serial: stm32: do not deassert RS485 RTS GPIO prematurely + - serial: 8250_dma: terminate correct DMA in tx_dma_flush() + - Linux 6.14.1 + + * Null pointer dereference in gVNIC driver (LP: #2106281) + - gve: unlink old napi only if page pool exists + + * Miscellaneous upstream changes + - Revert "net: stmmac: dwmac-socfpga: Set RX watchdog interrupt as broken" + - Revert "drm: fsl-dcu: enable PIXCLK on LS1021A" + - Revert "m68k: mvme147: Reinstate early console" + - Revert "MAINTAINERS: appoint myself the XFS maintainer for 6.12 LTS" + + -- Mehmet Basaran Thu, 01 May 2025 10:39:35 +0300 + +linux (6.14.0-15.15) plucky; urgency=medium + + * plucky/linux: 6.14.0-15.15 -proposed tracker (LP: #2106239) + + * Enabling GENDWARFKSYMS breaks loading modules (LP: #2103771) + - [Packaging] Bump pahole build-dep + + * BMG: support additional PCI ID (LP: #2105768) + - SAUCE: drm/xe/bmg: Add one additional PCI ID + + * Missing bpftool binary on riscv64 (LP: #2106091) + - [Packaging] Build bpftool and linux-perf on riscv64 + - [Packaging] Allow binary-debs target without enabling + do_flavour_image_package + - [Packaging] Fix bpftool, linux-perf packaging in binary-perarch + + -- Paolo Pisati Sun, 06 Apr 2025 14:36:36 +0200 + +linux (6.14.0-14.14) plucky; urgency=medium + + * plucky/linux: 6.14.0-14.14 -proposed tracker (LP: #2106234) + + * Expose IFLA_VXLAN_FAN_MAP version via sysctl/proc (LP: #2106115) + - SAUCE: fan: expose IFLA_VXLAN_FAN_MAP version via sysctl/proc + + * not able to install a Power9 bare metal with Ubuntu 25.04 Plucky + (LP: #2104297) + - SAUCE: powerpc64/ftrace: fix module loading without patchable function + entries + + * bluetooth/detect-output failed due to the lack of USB device id in btusb.c + (LP: #2094969) + - SAUCE: Bluetooth: btusb: Add new VID/PID 0489/e14e for MT7925 + + * Don't suggests fdutils package anymore (LP: #2104355) + - [Packaging] Drop fdutils from linux-image Suggests + + * Miscellaneous Ubuntu changes + - [Packaging] Add bpftool, linux-perf to linux-image Suggests + + -- Paolo Pisati Fri, 04 Apr 2025 15:12:05 +0200 + +linux (6.14.0-13.13) plucky; urgency=medium + + * plucky/linux: 6.14.0-13.13 -proposed tracker (LP: #2104293) + + * Miscellaneous Ubuntu changes + - [Packaging] Fix invoking of control-create + + -- Paolo Pisati Wed, 26 Mar 2025 20:26:51 +0100 + +linux (6.14.0-12.12) plucky; urgency=medium + + * plucky/linux: 6.14.0-12.12 -proposed tracker (LP: #2104021) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.03.24) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.03.24) + + * Disconnected paths for mqueues show a TODO in the kernel logs (LP: #2102237) + - SAUCE: apparmor4.0.0 [58/53]: apparmor: add mediation of disconnected paths + in mqueues + + * Installation of AppArmor on a 6.14 kernel produces error message "Illegal + number: yes" (LP: #2102680) + - SAUCE: apparmor4.0.0 [56/53]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor4.0.0 [57/53]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT for + userns and io_uring sysctls + + * QRT AppArmorUnixDomainConnect test failures on Plucky 6.14 kernel + (LP: #2103460) + - SAUCE: apparmor4.0.0 [54/53]: AppArmor: Fix af_unix backwards compat + - SAUCE: apparmor4.0.0 [55/53]: apparmor: Fix inet mediation + + * Mouse cursor flashes using the 'xe' DRM driver (LP: #2103981) + - drm/xe/display: Re-use display vmas when possible + + * Snapdragon X Elite: Sync concept kernel changes (LP: #2100858) + - SAUCE: drm/msm/dp: Fix support of LTTPR handling + - SAUCE: drm/msm/dp: Introduce link training per-segment for LTTPRs + - SAUCE: wifi: ath12k: fix ring-buffer corruption + - SAUCE: wifi: ath11k: fix ring-buffer corruption + - SAUCE: arm64: dts: qcom: x1e80100-hp-omnibook-x14: Enable SMB2360 0 and 1 + - SAUCE: Revert "usb: typec: ps883x: fix missing accessibility check" + + * drm/xe: improve behavior under memory pressure (LP: #2102659) + - drm/xe: Reject BO eviction if BO is bound to current VM + + * Introduce configfs-based interface for gpio-aggregator (LP: #2103496) + - gpio: introduce utilities for synchronous fake device creation + - gpio: sim: convert to use dev-sync-probe utilities + - gpio: virtuser: convert to use dev-sync-probe utilities + - [Config] updateconfigs for DEV_SYNC_PROBE + - SAUCE: gpio: aggregator: reorder functions to prepare for configfs + introduction + - SAUCE: gpio: aggregator: add aggr_alloc()/aggr_free() + - SAUCE: gpio: aggregator: introduce basic configfs interface + - SAUCE: gpio: aggregator: rename 'name' to 'key' in aggr_parse() + - SAUCE: gpio: aggregator: expose aggregator created via legacy sysfs to + configfs + - SAUCE: gpio: aggregator: cancel deferred probe for devices created via + configfs + - SAUCE: Documentation: gpio: document configfs interface for gpio-aggregator + - SAUCE: selftests: gpio: add test cases for gpio-aggregator + + * python perf module missing in plucky's kernel (LP: #2103653) + - [Packaging] linux-perf: Fix python perf library location + + * Miscellaneous Ubuntu changes + - [packaging] mv debian.master/copyright debian + - [Config] Disable CONFIG_MODULE_COMPRESS_ALL + - Revert "SAUCE: Support but do not require compressed modules" + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Config] Revert back to GENKSYMS on amd64/arm64 too, drop + rust support" + + -- Paolo Pisati Wed, 26 Mar 2025 10:50:08 +0100 + +linux (6.14.0-11.11) plucky; urgency=medium + + * plucky/linux: 6.14.0-11.11 -proposed tracker (LP: #2103404) + + * Snapdragon X Elite: Sync concept kernel changes (LP: #2100858) + - firmware: qcom: uefisecapp: fix efivars registration race + - soc: qcom: pdr: Fix the potential deadlock + - clk: qcom: gcc-x1e80100: Unregister GCC_GPU_CFG_AHB_CLK/GCC_DISP_XO_CLK + - arm64: dts: qcom: x1e80100: Set CPU interconnect paths as ACTIVE_ONLY + - dt-bindings: usb: Add Parade PS8830 Type-C retimer bindings + - usb: typec: Add support for Parade PS8830 Type-C Retimer + - usb: typec: ps883x: fix probe error handling + - usb: typec: ps883x: fix registration race + - usb: typec: ps883x: fix missing accessibility check + - usb: typec: ps883x: fix configuration error handling + - drm/dp: Add helper to set LTTPRs in transparent mode + - drm/msm/dp: Add support for LTTPR handling + - arm64: dts: qcom: x1e80100: Add the watchdog device + - arm64: dts: qcom: x1e80100: Mark usb_2 as dma-coherent + - arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets + - arm64: dts: qcom: Commonize X1 CRD DTSI + - arm64: dts: qcom: Add X1P42100 SoC and CRD + - arm64: dts: qcom: x1e80100: Fix video thermal zone + - arm64: dts: qcom: x1e80100: Apply consistent critical thermal shutdown + - arm64: dts: qcom: x1e80100: Add GPU cooling + - arm64: dts: qcom: x1e80100: Drop unused passive thermal trip points for CPU + - arm64: dts: qcom: x1e80100-dell-xps13-9345: Enable external DP support + - arm64: dts: qcom: x1e001de-devkit: Enable HBR3 on external DPs + - arm64: dts: qcom: x1e80100-hp-x14: Enable HBR3 on external DPs + - arm64: dts: qcom: x1e80100-qcp: Enable HBR3 on external DPs + - drm/edp-panel: Add panel used by T14s Gen6 Snapdragon + - arm64: dts: qcom: x1e80100-slim7x: Drop incorrect qcom,ath12k-calibration- + variant + - SAUCE: arm64: dts: qcom: x1e80100-crd: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e78100-t14s: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e001de-devkit: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: mark l12b and l15b + always-on + - SAUCE: arm64: dts: qcom: x1e80100-hp-x14: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e80100-yoga-slim7x: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e80100-qcp: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e78100-t14s: fix missing HID supplies + - SAUCE: arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes + - SAUCE: arm64: dts: qcom: x1e80100: Enable cpufreq + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Describe the Parade PS8830 retimers + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Enable external DisplayPort support + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Enable HBR3 on external DPs + - SAUCE: arm64: dts: qcom: x1e78100-t14s: enable bluetooth + - SAUCE: Add Bluetooth support for the Lenovo Yoga Slim 7x + - SAUCE: dt-bindings: platform: Add bindings for Lenovo Yoga Slim 7x EC + - SAUCE: platform: arm64: Add driver for Lenovo Yoga Slim 7x's EC + - SAUCE: arm64: dts: qcom: Add EC to Lenovo Yoga Slim 7x + - SAUCE: arm64: dts: qcom: x1e80100-vivobook-s15: Add bluetooth + - SAUCE: arm64: dts: qcom: x1e80100-vivobook-s15: Enable USB-A ports + - SAUCE: arm64: dts: qcom: x1e80100-vivobook-s15: Enable micro-sd card reader + - SAUCE: arm64: dts: qcom: x1p64100-acer-swift-sf14-11 dt for Acer Swift 14 + SF14-11 (touchpad fix) + - SAUCE: dt-bindings: arm: qcom: Add Acer Swift 14 AI + - SAUCE: arm64: dts: qcom: x1e80100-acer-swift-sf14-11: Enable HBR3 on + external DPs + - SAUCE: firmware: qcom: scm: Allow QSEECOM on Acer Swift 14 models + - SAUCE: arm64: dts: qcom: x1e001de-devkit: Set ps8830 reset-gpios active low + - SAUCE: Change: cracking sound fix + - SAUCE: rtc: pm8xxx: add support for uefi offset + - SAUCE: rtc: pm8xxx: mitigate flash wear + - SAUCE: arm64: dts: qcom: sc8280xp-x13s: switch to uefi rtc offset + - SAUCE: dt-bindings: rtc: qcom-pm8xxx: document qcom,no-alarm flag + - SAUCE: rtc: pm8xxx: implement qcom,no-alarm flag for non-HLOS owned alarm + - SAUCE: arm64: dts: qcom: x1e80100: enable rtc + - SAUCE: arm64: dts: qcom: x1e80100-microsoft-romulus: Enable external DP + support + - SAUCE: arm64: dts: qcom: x1e80100-asus-vivobook: Introduce retimers, + external DP + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps-9345: Add WiFi/BT pwrseq + - SAUCE: arm64: dts: qcom: x1e78100-t14s: Add display brightness control + support + - SAUCE: hack: efi/libstub: mitigate t14s exit_boot_services() failure + - [Config] Enable X Elite modules on arm64 + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.14-rc7 rebase + + -- Paolo Pisati Mon, 17 Mar 2025 11:29:48 +0100 + +linux (6.14.0-10.10) plucky; urgency=medium + + * plucky/linux: 6.14.0-10.10 -proposed tracker (LP: #2102106) + + * Miscellaneous Ubuntu changes + - [Config] Revert back to GENKSYMS on amd64/arm64 too, drop rust support + + -- Paolo Pisati Wed, 12 Mar 2025 15:20:52 +0100 + +linux (6.14.0-9.9) plucky; urgency=medium + + * plucky/linux: 6.14.0-9.9 -proposed tracker (LP: #2101943) + + * Miscellaneous Ubuntu changes + - [Config] Revert back to GENKSYMS on non-rust-enabled archs + + -- Paolo Pisati Tue, 11 Mar 2025 12:38:22 +0100 + +linux (6.14.0-8.8) plucky; urgency=medium + + * plucky/linux: 6.14.0-8.8 -proposed tracker (LP: #2101833) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.02.26) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.03.10) + + * wdat_wdt.ko should be pulled in by linux-image-virtual (LP: #2098554) + - [Packaging]: wdat_wdt.ko is moved from "linux-modules-extra-*-generic" to + "linux-modules-*-generic" + + * Add additional PCI ids for BMG support (LP: #2098969) + - drm/xe/bmg: Add new PCI IDs + + * Provide linux-perf package (LP: #1613393) + - [Packaging] Split linux-perf from linux-tools-common + + * linux-tools-common: bpftool wrapper causes build failure for xdp-tools + (LP: #2007308) + - [Packaging] bpftool: move to separate unversioned and unflavored binary + package + + * Miscellaneous Ubuntu changes + - [Packaging] templates/image.postrm.in: Add modules.weakdep to the remove- + list + - [Config] Re-enable rust support, switch from genksyms to gendwarfksyms + - [packaging] check-in copyright directly in debian/ + - [Packaging] remove intermediate $(DEBIAN)/control.stub + - [Config] updateconfigs following v6.14-rc6 rebase + + -- Paolo Pisati Mon, 10 Mar 2025 16:46:27 +0100 + +linux (6.14.0-7.7) plucky; urgency=medium + + * plucky/linux: 6.14.0-7.7 -proposed tracker (LP: #2100581) + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] Sync riscv64.mk with linux-riscv tree" + + -- Paolo Pisati Fri, 28 Feb 2025 10:46:05 +0100 + +linux (6.14.0-6.6) plucky; urgency=medium + + * plucky/linux: 6.14.0-6.6 -proposed tracker (LP: #2100481) + + * Miscellaneous Ubuntu changes + - [Packaging] riscv64.mk: fix a typo + - [Packaging] enable signing for s390x + - [Packaging] riscv64.mk: disable building as part of linux-generic + + -- Paolo Pisati Fri, 28 Feb 2025 09:44:27 +0100 + +linux (6.14.0-5.5) plucky; urgency=medium + + * plucky/linux: 6.14.0-5.5 -proposed tracker (LP: #2100254) + + * Miscellaneous Ubuntu changes + - [Packaging] Sync riscv64.mk with linux-riscv tree + - [Packaging] clean up the distclean rule + - [Config] updateconfigs following v6.14-rc4 rebase + + -- Paolo Pisati Wed, 26 Feb 2025 11:23:13 +0100 + +linux (6.14.0-4.4) plucky; urgency=medium + + * plucky/linux: 6.14.0-4.4 -proposed tracker (LP: #2098875) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.02.11) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [1/53]: Stacking: Audit: Create audit_stamp structure + - SAUCE: apparmor4.0.0 [2/53]: Stacking: Audit: Allow multiple records in an + audit_buffer + - SAUCE: apparmor4.0.0 [3/53]: Stacking: LSM: security_lsmblob_to_secctx + module selection + - SAUCE: apparmor4.0.0 [4/53]: Stacking: Audit: Add record for multiple task + security contexts + - SAUCE: apparmor4.0.0 [5/53]: Stacking: Audit: multiple subject lsm values + for netlabel + - SAUCE: apparmor4.0.0 [6/53]: Stacking: Audit: Add record for multiple object + contexts + - SAUCE: apparmor4.0.0 [7/53]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor4.0.0 [8/53]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [9/53]: Stacking: Audit: Call only the first of the + audit rule hooks + - SAUCE: apparmor4.0.0 [10/53]: Stacking: AppArmor: Remove the exclusive flag + - SAUCE: apparmor4.0.0 [11/53]: 6.15 apparmor-next: apparmor: Use str_yes_no() + helper function + - SAUCE: apparmor4.0.0 [12/53]: 6.15 apparmor-next: apparmor: Improve debug + print infrastructure + - SAUCE: apparmor4.0.0 [13/53]: 6.15 apparmor-next: apparmor: cleanup: + attachment perm lookup to use lookup_perms() + - SAUCE: apparmor4.0.0 [14/53]: 6.15 apparmor-next: apparmor: remove redundant + unconfined check. + - SAUCE: apparmor4.0.0 [15/53]: 6.15 apparmor-next: apparmor: switch signal + mediation to use RULE_MEDIATES + - SAUCE: apparmor4.0.0 [16/53]: 6.15 apparmor-next: apparmor: ensure labels + with more than one entry have correct flags + - SAUCE: apparmor4.0.0 [17/53]: 6.15 apparmor-next: apparmor: remove explicit + restriction that unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [18/53]: 6.15 apparmor-next: apparmor: cleanup: + refactor file_perm() to doc semantics of some checks + - SAUCE: apparmor4.0.0 [19/53]: 6.15 apparmor-next: apparmor: carry mediation + check on label + - SAUCE: apparmor4.0.0 [20/53]: 6.15 apparmor-next: apparmor: add additional + flags to extended permission. + - SAUCE: apparmor4.0.0 [21/53]: 6.15 apparmor-next: apparmor: add support for + profiles to define the kill signal + - SAUCE: apparmor4.0.0 [22/53]: 6.15 apparmor-next: apparmor: fix + x_table_lookup when stacking is not the first entry + - SAUCE: apparmor4.0.0 [23/53]: 6.15 apparmor-next: apparmor: add ability to + mediate caps with policy state machine + - SAUCE: apparmor4.0.0 [24/53]: 6.15 apparmor-next: apparmor: remove af_select + macro + - SAUCE: apparmor4.0.0 [25/53]: 6.15 apparmor-next: apparmor: lift kernel + socket check out of critical section + - SAUCE: apparmor4.0.0 [26/53]: 6.15 apparmor-next: apparmor: in preparation + for finer networking rules rework match_prot + - SAUCE: apparmor4.0.0 [27/53]: 6.15 apparmor-next: apparmor: add fine grained + af_unix mediation + - SAUCE: apparmor4.0.0 [28/53]: 6.15 apparmor-next: apparmor: gate make fine + grained unix mediation behind v9 abi + - SAUCE: apparmor4.0.0 [29/53]: 6.15 apparmor-next: apparmor: fix dbus + permission queries to v9 ABI + - SAUCE: apparmor4.0.0 [30/53]: 6.15 apparmor-next: apparmor: Fix checking + address of an array in accum_label_info() + - SAUCE: apparmor4.0.0 [31/53]: 6.15 apparmor-next: apparmor: Modify + mismatched function name + - SAUCE: apparmor4.0.0 [32/53]: 6.15 apparmor-next: apparmor: Modify + mismatched function name + - SAUCE: apparmor4.0.0 [33/53]: 6.15 apparmor-next: apparmor: fix typos and + spelling errors + - SAUCE: apparmor4.0.0 [34/53]: 6.15 apparmor-next: apparmor: use the + condition in AA_BUG_FMT even with debug disabled + - SAUCE: apparmor4.0.0 [35/53]: 6.15 apparmor-next: apparmor: Remove unused + variable 'sock' in __file_sock_perm() + - SAUCE: apparmor4.0.0 [36/53]: Revert "6.15 apparmor-next: apparmor: fix dbus + permission queries to v9 ABI" + - SAUCE: apparmor4.0.0 [37/53]: Revert "6.15 apparmor-next: apparmor: gate + make fine grained unix mediation behind v9 abi" + - SAUCE: apparmor4.0.0 [38/53]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [39/53]: apparmor: make debug_values_table static + - SAUCE: apparmor4.0.0 [40/53]: apparmor: Document that label must be last + member in struct aa_profile + - SAUCE: apparmor4.0.0 [41/53]: apparmor: transition from a list of rules to a + vector of rules + - SAUCE: apparmor4.0.0 [42/53]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [43/53]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [44/53]: add unprivileged user ns mediation + - SAUCE: apparmor4.0.0 [45/53]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [47/53]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [48/53]: apparmor: allow profile to be transitioned + when a userns is created + - SAUCE: apparmor4.0.0 [49/53]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [51/53]: apparmor: add fine grained ipv4/ipv6 mediation + - SAUCE: apparmor4.0.0 [52/53]: add io_uring mediation + - SAUCE: apparmor4.0.0 [53/53]: enable userspace upcall for mediation + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [46/53]: userns - make it so special unconfined + profiles can mediate user namespaces + + * Miscellaneous Ubuntu changes + - [Packaging] disable signing for ppc64el + - [Packaging] disable signing for s390x + - [packaging] rename to linux + - [Config] update RUSTC version + - [packaging] remove $(wildcard $(DEBIAN)/control.d/*) dependency + - [packaging] avoid piping control-create for error detection + - [packaging] split flavour-control.stub + - [packaging] generate debian/control with correct signed/unsigned + - [packaging] remove DESC and =HUMAN= substitution + - [Packaging] remove unnecessary dependency on control.stub + - [Packaging] add .gitignore and clean more files + - SAUCE: apparmor4.0.0 [50/53]: apparmor: audit mqueue-via-path access as + getattr instead of unlink + - [Packaging] debian.master/dkms-versions -- remove ipu6-drivers, + ipu7-drivers, backport-iwlwifi-dkms and mofed-modules-24.10 FTBFS + + -- Paolo Pisati Thu, 20 Feb 2025 14:20:53 +0100 + +linux-unstable (6.14.0-3.3) plucky; urgency=medium + + * plucky/linux-unstable: 6.14.0-3.3 -proposed tracker (LP: #2098836) + + * RISC-V kernel config is out of sync with other archs (LP: #1981437) + - [Config] riscv64: Sync config with other architectures + + * Miscellaneous Ubuntu changes + - SAUCE: platform/x86: int3472: fixup s/polarity/gpio_flags/ + - [Config] riscv64: Disable CONFIG_ARCH_RENESAS + - [Config] riscv64: Disable Andes vendor extensions + - [Config] riscv64: Set CONFIG_MMC_SPI=m like other architectures + - [Config] riscv64: Enable Svpbmt support + - [Config] riscv64: Disable kernel compression + - [packaging] enable ppc64el signing + - [Config] updateconfigs + + -- Paolo Pisati Wed, 19 Feb 2025 16:38:27 +0100 + +linux-unstable (6.14.0-2.2) plucky; urgency=medium + + * plucky/linux-unstable: 6.14.0-2.2 -proposed tracker (LP: #2097828) + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.14-rc2 rebase + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] Build all packages for linux-unstable" + + -- Paolo Pisati Tue, 11 Feb 2025 10:11:13 +0100 + +linux-unstable (6.14.0-1.1) plucky; urgency=medium + + * [25.04 FEAT] In-kernel crypto support MSA 11 HMAC (LP: #2096812) + - [Config] Change CONFIG_CRYPTO_HMAC_S390 to m for s390x + + * Miscellaneous Ubuntu changes + - Update dropped.txt (MODVERSION patches for Rust) + - [Config] updateconfigs following v6.14-rc1 rebase + - SAUCE: binder: turn into module - list_lru_add()/list_lru_del() + - SAUCE: binder: turn into module - lock_vma_under_rcu() + - [Config] temporarily disable DRM_HISI_HIBMC, FTBFS + - dkms: remove zfs, FTBFS + - [Config] armhf: disable TEGRA210_ADMA, FTBFS + + -- Paolo Pisati Fri, 07 Feb 2025 09:41:02 +0100 + +linux-unstable (6.13.0-2.2) plucky; urgency=medium + + * plucky/linux-unstable: 6.13.0-2.2 -proposed tracker (LP: #2096822) + + * Failed to probe for OVTI02C1: chip id mismatch: 560243!=0 (LP: #2090932) + - SAUCE: ACPI: scan: Update HID for new platform + + * Miscellaneous Ubuntu changes + - [Packaging]: Fix linux-bpf-dev build error for non-main kernels + - [Packaging] perf: enable debuginfod support + - [Config] toolchain version update + + -- Timo Aaltonen Tue, 28 Jan 2025 11:15:49 +0200 + +linux-unstable (6.13.0-1.1) plucky; urgency=medium + + * plucky/linux-unstable: 6.13.0-1.1 -proposed tracker (LP: #2096776) + + * Miscellaneous Ubuntu changes + - [Packaging] Rename to linux-unstable, bump version + - [Config] updateconfigs following v6.13 rebase + - [Config] toolchain version update + + -- Timo Aaltonen Mon, 27 Jan 2025 17:54:43 +0200 + +linux-unstable (6.13.0-0.0) plucky; urgency=medium + + * Dummy entry. + + -- Timo Aaltonen Mon, 20 Jan 2025 13:35:31 +0200 + +linux (6.12.0-10.10) plucky; urgency=medium + + * plucky/linux: 6.12.0-10.10 -proposed tracker (LP: #2092288) + + * Miscellaneous Ubuntu changes + - [Config] toolchain version update + - [Packaging] Update to clang-19 and newer rustc + - [Config] Re-enable rust support + + -- Paolo Pisati Sun, 29 Dec 2024 11:25:01 +0100 + +linux (6.12.0-9.9) plucky; urgency=medium + + * plucky/linux: 6.12.0-9.9 -proposed tracker (LP: #2092219) + + * Miscellaneous Ubuntu changes + - [Packaging] rules: Fix raw_kernelversion + + -- Paolo Pisati Fri, 20 Dec 2024 10:17:18 +0100 + +linux (6.12.0-8.8) plucky; urgency=medium + + * plucky/linux: 6.12.0-8.8 -proposed tracker (LP: #2092077) + + * Intel AX211 wireless module [8086:7740] subsys [8086:4090] wrongly + recognized as BE201 (LP: #2091546) + - SAUCE: wifi: iwlwifi: fix CRF name for Bz + + * When /dev/vmbus/hv_kvp is not present, disable hv-kvp-daemon (LP: #2091744) + - [Packaging] disable hv-kvp-daemon if needed + + * Miscellaneous Ubuntu changes + - [Packaging] linux-bpf-dev: Restructure packaging + - [Packaging] linux-bpf-dev: Skip packaging for additional kernel flavors + - [Packaging] rules: Convert install-arch-headers to a stamped target + - [Packaging] rules: Fold config check into stamp-prepare-% target + - [Packaging] rules: Fold module signature check into stamp-install-% target + - [Packaging] rules: Remove inclusion of 4-checks.mk + - [Packaging] rules: Remove build tests + - [Packaging] rules: Clean up install-perarch target + - [Packaging] rules: Move the ABI build directory to debian/build + - [Packaging] rules: Introduce global abi_dir variable + - [Packaging] rules: Introduce global build_dir variable + - [Packaging] rules: Remove target_flavour variable + - [Packaging] rules: Remove unused confdir variables + - [Packaging] rules: Remove undefined variables prev_{abinum, revisions} + - [Packaging] rules: Remove explicit kernel compression + - [Packaging] rules: Remove ship_extras_package feature + - [Packaging] rules: Remove stamps/stamp-prepare-indep target + - [Packaging] rules: Explicitly set do_*tools* variables to false + - [Packaging] rules: Wrap do_linux_tools around bpftool install/usage + + -- Paolo Pisati Thu, 19 Dec 2024 15:10:50 +0100 + +linux (6.12.0-7.7) plucky; urgency=medium + + * plucky/linux: 6.12.0-7.7 -proposed tracker (LP: #2091852) + + * Miscellaneous Ubuntu changes + - remove the AA stack + + * Remove the entire AA stack (FTBFS) + + -- Paolo Pisati Wed, 18 Dec 2024 14:55:25 +0100 + +linux (6.12.0-6.6) plucky; urgency=medium + + * plucky/linux: 6.12.0-6.6 -proposed tracker (LP: #2091721) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [29/84]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [30/84]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [31/84]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [32/84]: af_unix mediation + - SAUCE: apparmor4.0.0 [33/84]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [35/84]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [36/84]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [37/84]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [38/84]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [39/84]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [40/84]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [41/84]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [42/84]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [43/84]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [44/84]: prompt - fix caching + - SAUCE: apparmor4.0.0 [45/84]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [46/84]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [47/84]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [48/84]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [49/84]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [50/84]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [65/93] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [55/84]: add io_uring mediation + - SAUCE: apparmor4.0.0 [56/84]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [57/84]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [58/84]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [59/84]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [60/84]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [61/84]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [62/84]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [63/84]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [64/84]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [65/84]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [66/84]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [67/84]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [68/84]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [69/84]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [70/84]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [71/84]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [72/84]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [73/84]: fixup notify + - SAUCE: apparmor4.0.0 [74/84]: apparmor: add fine grained ipv4/ipv6 mediation + - SAUCE: apparmor4.0.0 [75/84]: apparmor: disable tailglob responses for now + - SAUCE: apparmor4.0.0 [76/84]: apparmor: Fix notify build warnings + - SAUCE: apparmor4.0.0 [77/84]: fix reserved mem for when we save ipv6 + addresses + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * linux-gcp 6.8.0-1005.5 (+ others) Noble kernel regression with new apparmor + profiles/features (LP: #2061851) + - SAUCE: apparmor4.0.0 [78/84]: fix address mapping for recvfrom + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [52/84]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [53/84]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [54/84]: userns - make it so special unconfined + profiles can mediate user namespaces + + * Miscellaneous Ubuntu changes + - [packaging] rename to linux + - SAUCE: apparmor4.0.0 [1/84]: LSM: Add the lsm_prop data structure. + - SAUCE: apparmor4.0.0 [2/84]: LSM: Use lsm_prop in security_audit_rule_match + - SAUCE: apparmor4.0.0 [3/84]: LSM: Add lsmprop_to_secctx hook + - SAUCE: apparmor4.0.0 [4/84]: Audit: maintain an lsm_prop in audit_context + - SAUCE: apparmor4.0.0 [5/84]: LSM: Use lsm_prop in security_ipc_getsecid + - SAUCE: apparmor4.0.0 [6/84]: Audit: Update shutdown LSM data + - SAUCE: apparmor4.0.0 [7/84]: LSM: Use lsm_prop in security_current_getsecid + - SAUCE: apparmor4.0.0 [8/84]: LSM: Use lsm_prop in security_inode_getsecid + - SAUCE: apparmor4.0.0 [9/84]: Audit: use an lsm_prop in audit_names + - SAUCE: apparmor4.0.0 [10/84]: LSM: Create new security_cred_getlsmprop LSM + hook + - SAUCE: apparmor4.0.0 [11/84]: Audit: Change context data from secid to + lsm_prop + - SAUCE: apparmor4.0.0 [12/84]: Use lsm_prop for audit data + - SAUCE: apparmor4.0.0 [13/84]: LSM: Remove lsm_prop scaffolding + - SAUCE: apparmor4.0.0 [14/84]: LSM: Ensure the correct LSM context releaser + - SAUCE: apparmor4.0.0 [15/84]: LSM: Replace context+len with lsm_context + - SAUCE: apparmor4.0.0 [16/84]: LSM: Use lsm_context in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [17/84]: LSM: lsm_context in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [18/84]: LSM: secctx provider check on release + - SAUCE: apparmor4.0.0 [19/84]: LSM: Use lsm_context in + security_inode_notifysecctx + - SAUCE: apparmor4.0.0 [20/84]: Audit: Create audit_stamp structure + - SAUCE: apparmor4.0.0 [21/84]: Audit: Allow multiple records in an + audit_buffer + - SAUCE: apparmor4.0.0 [22/84]: LSM: security_lsmblob_to_secctx module + selection + - SAUCE: apparmor4.0.0 [23/84]: Audit: Add record for multiple task security + contexts + - SAUCE: apparmor4.0.0 [24/84]: Audit: multiple subject lsm values for + netlabel + - SAUCE: apparmor4.0.0 [25/84]: Audit: Add record for multiple object contexts + - SAUCE: apparmor4.0.0 [26/84]: LSM: Single calls in secid hooks + - SAUCE: apparmor4.0.0 [27/84]: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [28/84]: AppArmor: Remove the exclusive flag + - SAUCE: apparmor4.0.0 [34/84]: fixup inode_set_attr + - SAUCE: apparmor4.0.0 [79/84]: apparmor: add support for 2^24 states to the + dfa state machine. + - SAUCE: apparmor4.0.0 [80/84]: apparmor: advertise to userspace support of + user upcall for file rules. + - SAUCE: apparmor4.0.0 [81/84]: apparmor: allocate xmatch for nullpdf inside + aa_alloc_null + - SAUCE: apparmor4.0.0 [82/84]: apparmor: properly handle cx/px lookup failure + for complain + - SAUCE: apparmor4.0.0 [83/84]: apparmor: fix prompt failing during large down + loads + - SAUCE: apparmor4.0.0 [84/84]: apparmor: fix allow field in notification + + -- Paolo Pisati Fri, 13 Dec 2024 16:35:21 +0100 + +linux (6.12.0-5.5) plucky; urgency=medium + + * plucky/linux-unstable: 6.12.0-5.5 -proposed tracker (LP: #2091628) + + * Plucky update: v6.12.4 upstream stable release (LP: #2091627) + - xfs: remove unknown compat feature check in superblock write validation + - quota: flush quota_release_work upon quota writeback + - btrfs: drop unused parameter file_offset from + btrfs_encoded_read_regular_fill_pages() + - btrfs: change btrfs_encoded_read() so that reading of extent is done by + caller + - btrfs: move priv off stack in btrfs_encoded_read_regular_fill_pages() + - btrfs: fix use-after-free in btrfs_encoded_read_endio() + - btrfs: don't loop for nowait writes when checking for cross references + - btrfs: add a sanity check for btrfs root in btrfs_search_slot() + - btrfs: ref-verify: fix use-after-free after invalid ref action + - iommu/tegra241-cmdqv: Fix unused variable warning + - netkit: Add option for scrubbing skb meta data + - md/raid5: Wait sync io to finish before changing group cnt + - md/md-bitmap: Add missing destroy_work_on_stack() + - arm64: dts: allwinner: pinephone: Add mount matrix to accelerometer + - arm64: dts: mediatek: mt8186-corsola: Fix GPU supply coupling max-spread + - arm64: dts: freescale: imx8mm-verdin: Fix SD regulator startup delay + - arm64: dts: ti: k3-am62-verdin: Fix SD regulator startup delay + - arm64: dts: mediatek: mt8186-corsola: Fix IT6505 reset line polarity + - media: qcom: camss: fix error path on configuration of power domains + - media: amphion: Set video drvdata before register video device + - media: imx-jpeg: Set video drvdata before register video device + - media: mtk-jpeg: Fix null-ptr-deref during unload module + - media: i2c: dw9768: Fix pm_runtime_set_suspended() with runtime pm enabled + - arm64: dts: freescale: imx8mp-verdin: Fix SD regulator startup delay + - media: i2c: tc358743: Fix crash in the probe error path when using polling + - media: imx-jpeg: Ensure power suppliers be suspended before detach them + - media: platform: rga: fix 32-bit DMA limitation + - media: verisilicon: av1: Fix reference video buffer pointer assignment + - media: ts2020: fix null-ptr-deref in ts2020_probe() + - media: platform: exynos4-is: Fix an OF node reference leak in + fimc_md_is_isp_available + - efi/libstub: Free correct pointer on failure + - net: phy: dp83869: fix status reporting for 1000base-x autonegotiation + - media: amphion: Fix pm_runtime_set_suspended() with runtime pm enabled + - media: venus: Fix pm_runtime_set_suspended() with runtime pm enabled + - media: gspca: ov534-ov772x: Fix off-by-one error in set_frame_rate() + - media: ov08x40: Fix burst write sequence + - media: platform: allegro-dvt: Fix possible memory leak in + allocate_buffers_internal() + - media: uvcvideo: Stop stream during unregister + - media: uvcvideo: Require entities to have a non-zero unique ID + - tracing: Fix function timing profiler to initialize hashtable + - kunit: Fix potential null dereference in kunit_device_driver_test() + - kunit: string-stream: Fix a UAF bug in kunit_init_suite() + - ovl: Filter invalid inodes with missing lookup function + - maple_tree: refine mas_store_root() on storing NULL + - ftrace: Fix regression with module command in stack_trace_filter + - vmstat: call fold_vm_zone_numa_events() before show per zone NUMA event + - zram: clear IDLE flag after recompression + - iommu/io-pgtable-arm: Fix stage-2 map/unmap for concatenated tables + - iommu/arm-smmu: Defer probe of clients after smmu device bound + - leds: lp55xx: Remove redundant test for invalid channel number + - mm/damon/vaddr: fix issue in damon_va_evenly_split_region() + - powerpc/vdso: Drop -mstack-protector-guard flags in 32-bit files with clang + - cpufreq: scmi: Fix cleanup path when boost enablement fails + - clk: qcom: gcc-qcs404: fix initial rate of GPLL3 + - ad7780: fix division by zero in ad7780_write_raw() + - nvmem: core: Check read_only flag for force_ro in bin_attr_nvmem_write() + - driver core: fw_devlink: Stop trying to optimize cycle detection logic + - spmi: pmic-arb: fix return path in for_each_available_child_of_node() + - ARM: 9429/1: ioremap: Sync PGDs for VMALLOC shadow + - s390/entry: Mark IRQ entries to fix stack depot warnings + - ARM: 9430/1: entry: Do a dummy read from VMAP shadow + - ARM: 9431/1: mm: Pair atomic_set_release() with _read_acquire() + - net: stmmac: set initial EEE policy configuration + - vfio/qat: fix overflow check in qat_vf_resume_write() + - PCI: qcom: Disable ASPM L0s for X1E80100 + - perf jevents: fix breakage when do perf stat on system metric + - remoteproc: qcom_q6v5_pas: disable auto boot for wpss + - PCI: imx6: Fix suspend/resume support on i.MX6QDL + - mm/slub: Avoid list corruption when removing a slab from the full list + - f2fs: fix to drop all discards after creating snapshot on lvm device + - ceph: extract entity name from device id + - ceph: pass cred pointer to ceph_mds_auth_match() + - ceph: fix cred leak in ceph_mds_check_access() + - mtd: spinand: winbond: Fix 512GW and 02JW OOB layout + - mtd: spinand: winbond: Fix 512GW, 01GW, 01JW and 02JW ECC information + - util_macros.h: fix/rework find_closest() macros + - s390/stacktrace: Use break instead of return statement + - scsi: ufs: exynos: Add check inside exynos_ufs_config_smu() + - scsi: ufs: exynos: Fix hibern8 notify callbacks + - i3c: master: svc: Fix pm_runtime_set_suspended() with runtime pm enabled + - i3c: master: Fix miss free init_dyn_addr at i3c_master_put_i3c_addrs() + - i3c: master: svc: fix possible assignment of the same address to two devices + - i3c: master: svc: Modify enabled_events bit 7:0 to act as IBI enable counter + - PCI: keystone: Set mode as Root Complex for "ti,keystone-pcie" compatible + - PCI: keystone: Add link up check to ks_pcie_other_map_bus() + - PCI: endpoint: Fix PCI domain ID release in pci_epc_destroy() + - PCI: endpoint: Clear secondary (not primary) EPC in pci_epc_remove_epf() + - slab: Fix too strict alignment check in create_cache() + - fs/proc/kcore.c: Clear ret value in read_kcore_iter after successful + iov_iter_zero + - thermal: int3400: Fix reading of current_uuid for active policy + - leds: flash: mt6360: Fix device_for_each_child_node() refcounting in error + paths + - ovl: properly handle large files in ovl_security_fileattr + - mm/vmalloc: combine all TLB flush operations of KASAN shadow virtual address + into one operation + - dm: Fix typo in error message + - dm thin: Add missing destroy_work_on_stack() + - PCI: dwc: ep: Fix advertised resizable BAR size regression + - PCI: of_property: Assign PCI instead of CPU bus address to dynamic PCI nodes + - PCI: rockchip-ep: Fix address translation unit programming + - nfsd: make sure exp active before svc_export_show + - nfsd: fix nfs4_openowner leak when concurrent nfsd4_open occur + - iio: accel: kx022a: Fix raw read format + - iio: invensense: fix multiple odr switch when FIFO is off + - iio: Fix fwnode_handle in __fwnode_iio_channel_get_by_name() + - iio: adc: ad7923: Fix buffer overflow for tx_buf and ring_xfer + - iio: gts: fix infinite loop for gain_to_scaletables() + - powerpc: Fix stack protector Kconfig test for clang + - powerpc: Adjust adding stack protector flags to KBUILD_CLAGS for clang + - binder: fix node UAF in binder_add_freeze_work() + - binder: fix OOB in binder_add_freeze_work() + - binder: fix freeze UAF in binder_release_work() + - binder: fix BINDER_WORK_FROZEN_BINDER debug logs + - binder: fix BINDER_WORK_CLEAR_FREEZE_NOTIFICATION debug logs + - binder: allow freeze notification for dead nodes + - binder: fix memleak of proc->delivered_freeze + - binder: add delivered_freeze to debugfs output + - dt-bindings: net: fec: add pps channel property + - net: fec: refactor PPS channel configuration + - net: fec: make PPS channel configurable + - drm/panic: Fix uninitialized spinlock acquisition with CONFIG_DRM_PANIC=n + - drm/sti: avoid potential dereference of error pointers in + sti_hqvdp_atomic_check + - drm/sti: avoid potential dereference of error pointers in + sti_gdp_atomic_check + - drm: panel: jd9365da-h3: Remove unused num_init_cmds structure member + - drm/sti: avoid potential dereference of error pointers + - drm/fbdev-dma: Select FB_DEFERRED_IO + - drm/mediatek: Fix child node refcount handling in early exit + - drm/bridge: it6505: Fix inverted reset polarity + - drm/etnaviv: flush shader L1 cache after user commandstream + - drm: xlnx: zynqmp_dpsub: fix hotplug detection + - drm/xe/xe_guc_ads: save/restore OA registers and allowlist regs + - drm/xe/migrate: fix pat index usage + - Revert "drm/radeon: Delay Connector detecting when HPD singals is unstable" + - drm/xe/migrate: use XE_BO_FLAG_PAGETABLE + - drm/xe/guc_submit: fix race around suspend_pending + - drm/amdkfd: Use the correct wptr size + - drm/amdgpu/pm: add gen5 display to the user on smu v14.0.2/3 + - drm/amd: Add some missing straps from NBIO 7.11.0 + - drm/amdgpu: fix usage slab after free + - drm/amd/pm: skip setting the power source on smu v14.0.2/3 + - drm/amd: Fix initialization mistake for NBIO 7.11 devices + - drm/amd/pm: update current_socclk and current_uclk in gpu_metrics on smu + v13.0.7 + - drm/amd/pm: disable pcie speed switching on Intel platform for smu v14.0.2/3 + - drm/amd/pm: Remove arcturus min power limit + - drm/amd/display: Fix handling of plane refcount + - drm/amd/display: update pipe selection policy to check head pipe + - drm/amd/display: Remove PIPE_DTO_SRC_SEL programming from set_dtbclk_dto + - posix-timers: Target group sigqueue to current task only if not exiting + - Revert "drm/xe/xe_guc_ads: save/restore OA registers and allowlist regs" + - Linux 6.12.4 + + * Plucky update: v6.12.3 upstream stable release (LP: #2091626) + - sched: Initialize idle tasks only once + - Linux 6.12.3 + + * Plucky update: v6.12.2 upstream stable release (LP: #2091625) + - MAINTAINERS: appoint myself the XFS maintainer for 6.12 LTS + - drm/amd/display: Skip Invalid Streams from DSC Policy + - drm/amd/display: Fix incorrect DSC recompute trigger + - s390/facilities: Fix warning about shadow of global variable + - s390/virtio_ccw: Fix dma_parm pointer not set up + - efs: fix the efs new mount api implementation + - arm64: probes: Disable kprobes/uprobes on MOPS instructions + - kselftest/arm64: hwcap: fix f8dp2 cpuinfo name + - kselftest/arm64: mte: fix printf type warnings about __u64 + - kselftest/arm64: mte: fix printf type warnings about longs + - block/fs: Pass an iocb to generic_atomic_write_valid() + - fs/block: Check for IOCB_DIRECT in generic_atomic_write_valid() + - s390/cio: Do not unregister the subchannel based on DNV + - s390/pageattr: Implement missing kernel_page_present() + - x86/pvh: Call C code via the kernel virtual mapping + - brd: defer automatic disk creation until module initialization succeeds + - ext4: avoid remount errors with 'abort' mount option + - mips: asm: fix warning when disabling MIPS_FP_SUPPORT + - s390/cpum_sf: Fix and protect memory allocation of SDBs with mutex + - initramfs: avoid filename buffer overrun + - arm64: Expose ID_AA64ISAR1_EL1.XS to sanitised feature consumers + - kselftest/arm64: Fix encoding for SVE B16B16 test + - nvme-pci: fix freeing of the HMB descriptor table + - m68k: mvme147: Fix SCSI controller IRQ numbers + - m68k: mvme147: Reinstate early console + - arm64: fix .data.rel.ro size assertion when CONFIG_LTO_CLANG + - acpi/arm64: Adjust error handling procedure in gtdt_parse_timer_block() + - loop: fix type of block size + - cachefiles: Fix incorrect length return value in + cachefiles_ondemand_fd_write_iter() + - cachefiles: Fix missing pos updates in cachefiles_ondemand_fd_write_iter() + - cachefiles: Fix NULL pointer dereference in object->file + - netfs/fscache: Add a memory barrier for FSCACHE_VOLUME_CREATING + - block: take chunk_sectors into account in bio_split_write_zeroes + - block: fix bio_split_rw_at to take zone_write_granularity into account + - s390/syscalls: Avoid creation of arch/arch/ directory + - hfsplus: don't query the device logical block size multiple times + - ext4: fix race in buffer_head read fault injection + - nvme-pci: reverse request order in nvme_queue_rqs + - virtio_blk: reverse request order in virtio_queue_rqs + - crypto: mxs-dcp - Fix AES-CBC with hardware-bound keys + - crypto: caam - Fix the pointer passed to caam_qi_shutdown() + - crypto: qat - remove check after debugfs_create_dir() + - crypto: qat/qat_420xx - fix off by one in uof_get_name() + - crypto: qat/qat_4xxx - fix off by one in uof_get_name() + - firmware: google: Unregister driver_info on failure + - EDAC/bluefield: Fix potential integer overflow + - crypto: qat - remove faulty arbiter config reset + - thermal: core: Initialize thermal zones before registering them + - thermal: core: Rearrange PM notification code + - thermal: core: Represent suspend-related thermal zone flags as bits + - thermal: core: Mark thermal zones as initializing to start with + - thermal: core: Fix race between zone registration and system suspend + - EDAC/fsl_ddr: Fix bad bit shift operations + - EDAC/skx_common: Differentiate memory error sources + - EDAC/{skx_common,i10nm}: Fix incorrect far-memory error source indicator + - crypto: pcrypt - Call crypto layer directly when padata_do_parallel() return + -EBUSY + - crypto: cavium - Fix the if condition to exit loop after timeout + - cpufreq/amd-pstate: Don't update CPPC request in + amd_pstate_cpu_boost_update() + - amd-pstate: Set min_perf to nominal_perf for active mode performance gov + - crypto: hisilicon/qm - disable same error report before resetting + - EDAC/igen6: Avoid segmentation fault on module unload + - crypto: qat - Fix missing destroy_workqueue in adf_init_aer() + - crypto: inside-secure - Fix the return value of safexcel_xcbcmac_cra_init() + - sched/cpufreq: Ensure sd is rebuilt for EAS check + - doc: rcu: update printed dynticks counter bits + - rcu/srcutiny: don't return before reenabling preemption + - rcu/kvfree: Fix data-race in __mod_timer / kvfree_call_rcu + - rcu/nocb: Fix missed RCU barrier on deoffloading + - hwmon: (pmbus/core) clear faults after setting smbalert mask + - hwmon: (nct6775-core) Fix overflows seen when writing limit attributes + - ACPI: CPPC: Fix _CPC register setting issue + - thermal: testing: Use DEFINE_FREE() and __free() to simplify code + - thermal: testing: Initialize some variables annoteded with _free() + - crypto: caam - add error check to caam_rsa_set_priv_key_form + - crypto: bcm - add error check in the ahash_hmac_init function + - crypto: cavium - Fix an error handling path in cpt_ucode_load_fw() + - rcuscale: Do a proper cleanup if kfree_scale_init() fails + - tools/lib/thermal: Make more generic the command encoding function + - thermal/lib: Fix memory leak on error in thermal_genl_auto() + - x86/unwind/orc: Fix unwind for newly forked tasks + - Revert "scripts/faddr2line: Check only two symbols when calculating symbol + size" + - cleanup: Remove address space of returned pointer + - time: Partially revert cleanup on msecs_to_jiffies() documentation + - time: Fix references to _msecs_to_jiffies() handling of values + - timers: Add missing READ_ONCE() in __run_timer_base() + - locking/atomic/x86: Use ALT_OUTPUT_SP() for __alternative_atomic64() + - locking/atomic/x86: Use ALT_OUTPUT_SP() for __arch_{,try_}cmpxchg64_emu() + - kcsan, seqlock: Support seqcount_latch_t + - kcsan, seqlock: Fix incorrect assumption in read_seqbegin() + - sched/ext: Remove sched_fork() hack + - locking/rt: Add sparse annotation PREEMPT_RT's sleeping locks. + - rust: helpers: Avoid raw_spin_lock initialization for PREEMPT_RT + - clocksource/drivers:sp804: Make user selectable + - clocksource/drivers/timer-ti-dm: Fix child node refcount handling + - irqchip/riscv-aplic: Prevent crash when MSI domain is missing + - regulator: qcom-smd: make smd_vreg_rpm static + - spi: spi-fsl-lpspi: Use IRQF_NO_AUTOEN flag in request_irq() + - arm64: dts: qcom: qcs6390-rb3gen2: use modem.mbn for modem DSP + - ARM: dts: renesas: genmai: Fix partition size for QSPI NOR Flash + - drivers: soc: xilinx: add the missing kfree in xlnx_add_cb_for_suspend() + - microblaze: Export xmb_manager functions + - arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power domain + - arm64: dts: mediatek: mt8395-genio-1200-evk: Fix dtbs_check error for phy + - arm64: dts: mt8195: Fix dtbs_check error for mutex node + - arm64: dts: mt8195: Fix dtbs_check error for infracfg_ao node + - arm64: dts: mediatek: mt8183-kukui: Disable DPI display interface + - arm64: dts: mt8183: Add port node to dpi node + - soc: ti: smartreflex: Use IRQF_NO_AUTOEN flag in request_irq() + - soc: qcom: geni-se: fix array underflow in geni_se_clk_tbl_get() + - arm64: dts: qcom: sm6350: Fix GPU frequencies missing on some speedbins + - arm64: dts: qcom: sda660-ifc6560: fix l10a voltage ranges + - ARM: dts: microchip: sam9x60: Add missing property atmel,usart-mode + - mmc: mmc_spi: drop buggy snprintf() + - scripts/kernel-doc: Do not track section counter across processed files + - arm64: dts: qcom: x1e80100-slim7x: Drop orientation-switch from USB SS[0-1] + QMP PHYs + - arm64: dts: qcom: x1e80100-vivobook-s15: Drop orientation-switch from USB + SS[0-1] QMP PHYs + - openrisc: Implement fixmap to fix earlycon + - efi/libstub: fix efi_parse_options() ignoring the default command line + - tpm: fix signed/unsigned bug when checking event logs + - media: i2c: max96717: clean up on error in max96717_subdev_init() + - media: i2c: vgxy61: Fix an error handling path in vgxy61_detect() + - media: i2c: ds90ub960: Fix missing return check on ub960_rxport_read call + - arm64: dts: mt8183: krane: Fix the address of eeprom at i2c4 + - arm64: dts: mt8183: kukui: Fix the address of eeprom at i2c4 + - arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region + - kernel-doc: allow object-like macros in ReST output + - arm64: dts: ti: k3-am62x-phyboard-lyra: Drop unnecessary McASP AFIFOs + - gpio: sloppy-logic-analyzer remove reference to rcu_momentary_dyntick_idle() + - arm64: dts: mediatek: mt8173-elm-hana: Add vdd-supply to second source + trackpad + - arm64: dts: mediatek: mt8188: Fix USB3 PHY port default status + - arm64: dts: mediatek: mt8195-cherry: Use correct audio codec DAI + - Revert "cgroup: Fix memory leak caused by missing cgroup_bpf_offline" + - cgroup/bpf: only cgroup v2 can be attached by bpf programs + - regulator: rk808: Restrict DVS GPIOs to the RK808 variant only + - power: sequencing: make the QCom PMU pwrseq driver depend on CONFIG_OF + - arm64: tegra: p2180: Add mandatory compatible for WiFi node + - arm64: dts: rockchip: Remove 'enable-active-low' from two boards + - arm64: dts: mt8183: fennel: add i2c2's i2c-scl-internal-delay-ns + - arm64: dts: mt8183: burnet: add i2c2's i2c-scl-internal-delay-ns + - arm64: dts: mt8183: cozmo: add i2c2's i2c-scl-internal-delay-ns + - arm64: dts: mt8183: Damu: add i2c2's i2c-scl-internal-delay-ns + - pwm: imx27: Workaround of the pwm output bug when decrease the duty cycle + - ARM: dts: cubieboard4: Fix DCDC5 regulator constraints + - arm64: dts: ti: k3-j7200: Fix register map for main domain pmx + - arm64: dts: ti: k3-j7200: Fix clock ids for MCSPI instances + - arm64: dts: ti: k3-j721e: Fix clock IDs for MCSPI instances + - arm64: dts: ti: k3-j721s2: Fix clock IDs for MCSPI instances + - watchdog: Add HAS_IOPORT dependency for SBC8360 and SBC7240 + - arm64: dts: qcom: x1e80100: Update C4/C5 residency/exit numbers + - dt-bindings: cache: qcom,llcc: Fix X1E80100 reg entries + - of/fdt: add dt_phys arg to early_init_dt_scan and early_init_dt_verify + - pmdomain: ti-sci: Add missing of_node_put() for args.np + - spi: tegra210-quad: Avoid shift-out-of-bounds + - spi: zynqmp-gqspi: Undo runtime PM changes at driver exit time​ + - regmap: irq: Set lockdep class for hierarchical IRQ domains + - arm64: dts: renesas: hihope: Drop #sound-dai-cells + - arm64: dts: imx8mn-tqma8mqnl-mba8mx-usbot: fix coexistence of output-low and + output-high in GPIO + - arm64: dts: mediatek: mt6358: fix dtbs_check error + - arm64: dts: mediatek: mt8183-kukui-jacuzzi: Fix DP bridge supply names + - arm64: dts: mediatek: mt8183-kukui-jacuzzi: Add supplies for fixed + regulators + - selftests/resctrl: Print accurate buffer size as part of MBM results + - selftests/resctrl: Fix memory overflow due to unhandled wraparound + - selftests/resctrl: Protect against array overrun during iMC config parsing + - firmware: arm_scpi: Check the DVFS OPP count returned by the firmware + - media: ipu6: Fix DMA and physical address debugging messages for 32-bit + - media: ipu6: not override the dma_ops of device in driver + - media: ipu6: remove architecture DMA ops dependency in Kconfig + - pwm: Assume a disabled PWM to emit a constant inactive output + - media: atomisp: Add check for rgby_data memory allocation failure + - arm64: dts: rockchip: correct analog audio name on Indiedroid Nova + - sched_ext: scx_bpf_dispatch_from_dsq_set_*() are allowed from unlocked + context + - HID: hyperv: streamline driver probe to avoid devres issues + - platform/x86: asus-wmi: Fix inconsistent use of thermal policies + - platform/x86/intel/pmt: allow user offset for PMT callbacks + - platform/x86: panasonic-laptop: Return errno correctly in show callback + - drm/imagination: Convert to use time_before macro + - drm/imagination: Use pvr_vm_context_get() + - drm/mm: Mark drm_mm_interval_tree*() functions with __maybe_unused + - drm/vc4: hvs: Don't write gamma luts on 2711 + - drm/vc4: hdmi: Avoid hang with debug registers when suspended + - drm/vc4: hvs: Fix dlist debug not resetting the next entry pointer + - drm/vc4: hvs: Remove incorrect limit from hvs_dlist debugfs function + - drm/vc4: hvs: Correct logic on stopping an HVS channel + - wifi: ath9k: add range check for conn_rsp_epid in htc_connect_service() + - drm/omap: Fix possible NULL dereference + - drm/omap: Fix locking in omap_gem_new_dmabuf() + - drm/v3d: Appease lockdep while updating GPU stats + - wifi: p54: Use IRQF_NO_AUTOEN flag in request_irq() + - wifi: mwifiex: Use IRQF_NO_AUTOEN flag in request_irq() + - udmabuf: change folios array from kmalloc to kvmalloc + - udmabuf: fix vmap_udmabuf error page set + - drm/imx/dcss: Use IRQF_NO_AUTOEN flag in request_irq() + - drm/imx/ipuv3: Use IRQF_NO_AUTOEN flag in request_irq() + - drm/panel: nt35510: Make new commands optional + - drm/v3d: Address race-condition in MMU flush + - drm/v3d: Flush the MMU before we supply more memory to the binner + - drm/amdgpu: Fix JPEG v4.0.3 register write + - wifi: ath10k: fix invalid VHT parameters in supported_vht_mcs_rate_nss1 + - wifi: ath10k: fix invalid VHT parameters in supported_vht_mcs_rate_nss2 + - wifi: ath12k: Skip Rx TID cleanup for self peer + - dt-bindings: vendor-prefixes: Add NeoFidelity, Inc + - ASoC: fsl_micfil: fix regmap_write_bits usage + - ASoC: dt-bindings: mt6359: Update generic node name and dmic-mode + - drm/amdgpu/gfx9: Add Cleaner Shader Deinitialization in gfx_v9_0 Module + - ASoC: fsl-asoc-card: Add missing handling of {hp,mic}-dt-gpios + - drm/bridge: anx7625: Drop EDID cache on bridge power off + - drm/bridge: it6505: Drop EDID cache on bridge power off + - libbpf: Fix expected_attach_type set handling in program load callback + - libbpf: Fix output .symtab byte-order during linking + - selftests/bpf: Fix uprobe_multi compilation error + - dlm: fix swapped args sb_flags vs sb_status + - wifi: rtl8xxxu: Perform update_beacon_work when beaconing is enabled + - ASoC: amd: acp: fix for inconsistent indenting + - ASoC: amd: acp: fix for cpu dai index logic + - drm/amd/display: fix a memleak issue when driver is removed + - wifi: ath12k: fix use-after-free in ath12k_dp_cc_cleanup() + - wifi: ath12k: fix one more memcpy size error + - libbpf: Add missing per-arch include path + - selftests: bpf: Add missing per-arch include path + - bpf: Fix the xdp_adjust_tail sample prog issue + - selftests/bpf: Fix backtrace printing for selftests crashes + - wifi: ath11k: Fix CE offset address calculation for WCN6750 in SSR + - selftests/bpf: add missing header include for htons + - wifi: cfg80211: check radio iface combination for multi radio per wiphy + - ice: consistently use q_idx in ice_vc_cfg_qs_msg() + - drm/vc4: hdmi: Increase audio MAI fifo dreq threshold + - drm/vc4: Introduce generation number enum + - drm/vc4: Match drm_dev_enter and exit calls in vc4_hvs_lut_load + - drm/vc4: Match drm_dev_enter and exit calls in vc4_hvs_atomic_flush + - drm/vc4: Correct generation check in vc4_hvs_lut_load + - libbpf: fix sym_is_subprog() logic for weak global subprogs + - accel/ivpu: Prevent recovery invocation during probe and resume + - ASoC: rt722-sdca: Remove logically deadcode in rt722-sdca.c + - libbpf: never interpret subprogs in .text as entry programs + - netdevsim: copy addresses for both in and out paths + - drm/bridge: tc358767: Fix link properties discovery + - drm/panic: Select ZLIB_DEFLATE for DRM_PANIC_SCREEN_QR_CODE + - selftests/bpf: Fix msg_verify_data in test_sockmap + - selftests/bpf: Fix txmsg_redir of test_txmsg_pull in test_sockmap + - wifi: mwifiex: add missing locking for cfg80211 calls + - wifi: wilc1000: Set MAC after operation mode + - wifi: mwifiex: Fix memcpy() field-spanning write warning in + mwifiex_config_scan() + - drm: fsl-dcu: enable PIXCLK on LS1021A + - drm: panel: nv3052c: correct spi_device_id for RG35XX panel + - drm/msm/dpu: on SDM845 move DSPP_3 to LM_5 block + - drm/msm/dpu: drop LM_3 / LM_4 on SDM845 + - drm/msm/dpu: drop LM_3 / LM_4 on MSM8998 + - octeontx2-pf: handle otx2_mbox_get_rsp errors in otx2_common.c + - octeontx2-pf: handle otx2_mbox_get_rsp errors in otx2_ethtool.c + - octeontx2-pf: handle otx2_mbox_get_rsp errors in otx2_flows.c + - octeontx2-pf: handle otx2_mbox_get_rsp errors in cn10k.c + - octeontx2-pf: handle otx2_mbox_get_rsp errors in otx2_dmac_flt.c + - octeontx2-pf: handle otx2_mbox_get_rsp errors in otx2_dcbnl.c + - selftests/bpf: fix test_spin_lock_fail.c's global vars usage + - libbpf: move global data mmap()'ing into bpf_object__load() + - wifi: rtw89: rename rtw89_vif to rtw89_vif_link ahead for MLO + - wifi: rtw89: rename rtw89_sta to rtw89_sta_link ahead for MLO + - wifi: rtw89: read bss_conf corresponding to the link + - wifi: rtw89: read link_sta corresponding to the link + - wifi: rtw89: refactor VIF related func ahead for MLO + - wifi: rtw89: refactor STA related func ahead for MLO + - wifi: rtw89: tweak driver architecture for impending MLO support + - wifi: rtw89: Fix TX fail with A2DP after scanning + - wifi: rtw89: unlock on error path in rtw89_ops_unassign_vif_chanctx() + - drm/panfrost: Remove unused id_mask from struct panfrost_model + - bpf, arm64: Remove garbage frame for struct_ops trampoline + - drm/msm/adreno: Use IRQF_NO_AUTOEN flag in request_irq() + - drm/msm/gpu: Check the status of registration to PM QoS + - drm/xe/hdcp: Fix gsc structure check in fw check status + - drm/etnaviv: Request pages from DMA32 zone on addressing_limited + - drm/etnaviv: hold GPU lock across perfmon sampling + - drm/amd/display: Increase idle worker HPD detection time + - drm/amd/display: Reduce HPD Detection Interval for IPS + - drm/nouveau/gr/gf100: Fix missing unlock in gf100_gr_chan_new() + - drm: zynqmp_kms: Unplug DRM device before removal + - drm: xlnx: zynqmp_disp: layer may be null while releasing + - wifi: wfx: Fix error handling in wfx_core_init() + - wifi: cw1200: Fix potential NULL dereference + - drm/msm/dpu: cast crtc_clk calculation to u64 in _dpu_core_perf_calc_clk() + - bpf, bpftool: Fix incorrect disasm pc + - bpf: Tighten tail call checks for lingering locks, RCU, preempt_disable + - drm/vkms: Drop unnecessary call to drm_crtc_cleanup() + - drm/amdgpu: Fix the memory allocation issue in + amdgpu_discovery_get_nps_info() + - drm/amdkfd: Use dynamic allocation for CU occupancy array in + 'kfd_get_cu_occupancy()' + - bpf: Mark raw_tp arguments with PTR_MAYBE_NULL + - drm: use ATOMIC64_INIT() for atomic64_t + - netfilter: nf_tables: avoid false-positive lockdep splat on rule deletion + - netfilter: nf_tables: must hold rcu read lock while iterating expression + type list + - netfilter: nf_tables: must hold rcu read lock while iterating object type + list + - netlink: typographical error in nlmsg_type constants definition + - wifi: rtw89: coex: check NULL return of kmalloc in btc_fw_set_monreg() + - drm/panfrost: Add missing OPP table refcnt decremental + - drm/panthor: introduce job cycle and timestamp accounting + - drm/panthor: record current and maximum device clock frequencies + - drm/panthor: Fix OPP refcnt leaks in devfreq initialisation + - isofs: avoid memory leak in iocharset + - selftests/bpf: Add txmsg_pass to pull/push/pop in test_sockmap + - selftests/bpf: Fix SENDPAGE data logic in test_sockmap + - selftests/bpf: Fix total_bytes in msg_loop_rx in test_sockmap + - selftests/bpf: Add push/pop checking for msg_verify_data in test_sockmap + - bpf, sockmap: Several fixes to bpf_msg_push_data + - bpf, sockmap: Several fixes to bpf_msg_pop_data + - bpf, sockmap: Fix sk_msg_reset_curr + - ipv6: release nexthop on device removal + - selftests: net: really check for bg process completion + - wifi: cfg80211: Remove the Medium Synchronization Delay validity check + - wifi: iwlwifi: allow fast resume on ax200 + - wifi: iwlwifi: mvm: tell iwlmei when we finished suspending + - drm/amdgpu: fix ACA bank count boundary check error + - drm/amdgpu: Fix map/unmap queue logic + - drm/amdkfd: Fix wrong usage of INIT_WORK() + - bpf: Allow return values 0 and 1 for kprobe session + - bpf: Force uprobe bpf program to always return 0 + - selftests/bpf: skip the timer_lockup test for single-CPU nodes + - ipv6: Fix soft lockups in fib6_select_path under high next hop churn + - net: rfkill: gpio: Add check for clk_enable() + - Revert "wifi: iwlegacy: do not skip frames with bad FCS" + - bpf: Use function pointers count as struct_ops links count + - bpf: Add kernel symbol for struct_ops trampoline + - ALSA: usx2y: Use snd_card_free_when_closed() at disconnection + - ALSA: us122l: Use snd_card_free_when_closed() at disconnection + - ALSA: caiaq: Use snd_card_free_when_closed() at disconnection + - ALSA: 6fire: Release resources at card release + - i2c: dev: Fix memory leak when underlying adapter does not support I2C + - selftests: netfilter: Fix missing return values in conntrack_dump_flush + - Bluetooth: btintel_pcie: Add handshake between driver and firmware + - Bluetooth: btintel: Do no pass vendor events to stack + - Bluetooth: btmtk: adjust the position to init iso data anchor + - Bluetooth: btbcm: fix missing of_node_put() in btbcm_get_board_name() + - Bluetooth: ISO: Use kref to track lifetime of iso_conn + - Bluetooth: ISO: Do not emit LE PA Create Sync if previous is pending + - Bluetooth: ISO: Do not emit LE BIG Create Sync if previous is pending + - Bluetooth: ISO: Send BIG Create Sync via hci_sync + - Bluetooth: fix use-after-free in device_for_each_child() + - xsk: Free skb when TX metadata options are invalid + - erofs: fix file-backed mounts over FUSE + - erofs: fix blksize < PAGE_SIZE for file-backed mounts + - erofs: handle NONHEAD !delta[1] lclusters gracefully + - dlm: fix dlm_recover_members refcount on error + - eth: fbnic: don't disable the PCI device twice + - net: txgbe: remove GPIO interrupt controller + - net: txgbe: fix null pointer to pcs + - netpoll: Use rcu_access_pointer() in netpoll_poll_lock + - wireguard: selftests: load nf_conntrack if not present + - bpf: fix recursive lock when verdict program return SK_PASS + - unicode: Fix utf8_load() error path + - cppc_cpufreq: Use desired perf if feedback ctrs are 0 or unchanged + - RDMA/core: Provide rdma_user_mmap_disassociate() to disassociate mmap pages + - RDMA/hns: Disassociate mmap pages for all uctx when HW is being reset + - pinctrl: renesas: rzg2l: Fix missing return in rzg2l_pinctrl_register() + - clk: mediatek: drop two dead config options + - trace/trace_event_perf: remove duplicate samples on the first tracepoint + event + - pinctrl: zynqmp: drop excess struct member description + - pinctrl: renesas: Select PINCTRL_RZG2L for RZ/V2H(P) SoC + - clk: qcom: videocc-sm8550: depend on either gcc-sm8550 or gcc-sm8650 + - iommu/s390: Implement blocking domain + - scsi: hisi_sas: Enable all PHYs that are not disabled by user during + controller reset + - powerpc/vdso: Flag VDSO64 entry points as functions + - mfd: tps65010: Use IRQF_NO_AUTOEN flag in request_irq() to fix race + - mfd: da9052-spi: Change read-mask to write-mask + - mfd: intel_soc_pmic_bxtwc: Use IRQ domain for USB Type-C device + - mfd: intel_soc_pmic_bxtwc: Use IRQ domain for TMU device + - mfd: intel_soc_pmic_bxtwc: Use IRQ domain for PMIC devices + - mfd: intel_soc_pmic_bxtwc: Fix IRQ domain names duplication + - cpufreq: loongson2: Unregister platform_driver on failure + - powerpc/fadump: Refactor and prepare fadump_cma_init for late init + - powerpc/fadump: Move fadump_cma_init to setup_arch() after initmem_init() + - mtd: hyperbus: rpc-if: Add missing MODULE_DEVICE_TABLE + - mtd: rawnand: atmel: Fix possible memory leak + - clk: Allow kunit tests to run without OF_OVERLAY enabled + - powerpc/mm/fault: Fix kfence page fault reporting + - iommu/tegra241-cmdqv: Staticize cmdqv_debugfs_dir + - clk: sophgo: avoid integer overflow in sg2042_pll_recalc_rate() + - mtd: spi-nor: spansion: Use nor->addr_nbytes in octal DTR mode in + RD_ANY_REG_OP + - powerpc/pseries: Fix dtl_access_lock to be a rw_semaphore + - cpufreq: CPPC: Fix possible null-ptr-deref for cpufreq_cpu_get_raw() + - cpufreq: CPPC: Fix possible null-ptr-deref for cppc_get_cpu_cost() + - iommu/amd/pgtbl_v2: Take protection domain lock before invalidating TLB + - RDMA/hns: Fix an AEQE overflow error caused by untimely update of eq_db_ci + - RDMA/hns: Fix flush cqe error when racing with destroy qp + - RDMA/hns: Modify debugfs name + - RDMA/hns: Use dev_* printings in hem code instead of ibdev_* + - RDMA/hns: Fix cpu stuck caused by printings during reset + - RDMA/rxe: Fix the qp flush warnings in req + - RDMA/bnxt_re: Check cqe flags to know imm_data vs inv_irkey + - clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset + - clk: renesas: rzg2l: Fix FOUTPOSTDIV clk + - RDMA/rxe: Set queue pair cur_qp_state when being queried + - RDMA/mlx5: Call dev_put() after the blocking notifier + - RDMA/core: Implement RoCE GID port rescan and export delete function + - RDMA/mlx5: Ensure active slave attachment to the bond IB device + - RISC-V: KVM: Fix APLIC in_clrip and clripnum write emulation + - riscv: kvm: Fix out-of-bounds array access + - clk: imx: lpcg-scu: SW workaround for errata (e10858) + - clk: imx: fracn-gppll: correct PLL initialization flow + - clk: imx: fracn-gppll: fix pll power up + - clk: imx: clk-scu: fix clk enable state save and restore + - clk: imx: imx8-acm: Fix return value check in + clk_imx_acm_attach_pm_domains() + - iommu/vt-d: Fix checks and print in dmar_fault_dump_ptes() + - iommu/vt-d: Fix checks and print in pgtable_walk() + - checkpatch: always parse orig_commit in fixes tag + - mfd: rt5033: Fix missing regmap_del_irq_chip() + - leds: max5970: Fix unreleased fwnode_handle in probe function + - leds: ktd2692: Set missing timing properties + - fs/proc/kcore.c: fix coccinelle reported ERROR instances + - scsi: target: Fix incorrect function name in pscsi_create_type_disk() + - scsi: bfa: Fix use-after-free in bfad_im_module_exit() + - scsi: fusion: Remove unused variable 'rc' + - scsi: qedf: Fix a possible memory leak in qedf_alloc_and_init_sb() + - scsi: qedi: Fix a possible memory leak in qedi_alloc_and_init_sb() + - scsi: sg: Enable runtime power management + - x86/tdx: Introduce wrappers to read and write TD metadata + - x86/tdx: Rename tdx_parse_tdinfo() to tdx_setup() + - x86/tdx: Dynamically disable SEPT violations from causing #VEs + - powerpc/fadump: allocate memory for additional parameters early + - fadump: reserve param area if below boot_mem_top + - RDMA/hns: Fix out-of-order issue of requester when setting FENCE + - RDMA/hns: Fix NULL pointer derefernce in hns_roce_map_mr_sg() + - cpufreq: loongson3: Check for error code from devm_mutex_init() call + - cpufreq: CPPC: Fix wrong return value in cppc_get_cpu_cost() + - cpufreq: CPPC: Fix wrong return value in cppc_get_cpu_power() + - kasan: move checks to do_strncpy_from_user + - kunit: skb: use "gfp" variable instead of hardcoding GFP_KERNEL + - ocfs2: fix uninitialized value in ocfs2_file_read_iter() + - zram: ZRAM_DEF_COMP should depend on ZRAM + - iommu/tegra241-cmdqv: Fix alignment failure at max_n_shift + - dax: delete a stale directory pmem + - KVM: PPC: Book3S HV: Stop using vc->dpdes for nested KVM guests + - KVM: PPC: Book3S HV: Avoid returning to nested hypervisor on pending + doorbells + - powerpc/sstep: make emulate_vsx_load and emulate_vsx_store static + - RDMA/hns: Fix different dgids mapping to the same dip_idx + - KVM: PPC: Book3S HV: Fix kmv -> kvm typo + - powerpc/kexec: Fix return of uninitialized variable + - fbdev: sh7760fb: Fix a possible memory leak in sh7760fb_alloc_mem() + - RDMA/mlx5: Move events notifier registration to be after device registration + - clk: clk-apple-nco: Add NULL check in applnco_probe + - clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883 + - clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs + - clk: en7523: remove REG_PCIE*_{MEM,MEM_MASK} configuration + - clk: en7523: move clock_register in hw_init callback + - clk: en7523: introduce chip_scu regmap + - clk: en7523: fix estimation of fixed rate for EN7581 + - dt-bindings: clock: axi-clkgen: include AXI clk + - clk: clk-axi-clkgen: make sure to enable the AXI bus clock + - zram: permit only one post-processing operation at a time + - zram: fix NULL pointer in comp_algorithm_show() + - RDMA/bnxt_re: Correct the sequence of device suspend + - arm64: dts: qcom: sc8180x: Add a SoC-specific compatible to cpufreq-hw + - pinctrl: k210: Undef K210_PC_DEFAULT + - rtla/timerlat: Do not set params->user_workload with -U + - smb: cached directories can be more than root file handle + - mailbox: mtk-cmdq: fix wrong use of sizeof in cmdq_get_clocks() + - mailbox: arm_mhuv2: clean up loop in get_irq_chan_comb() + - x86: fix off-by-one in access_ok() + - perf cs-etm: Don't flush when packet_queue fills up + - gfs2: Rename GLF_VERIFY_EVICT to GLF_VERIFY_DELETE + - gfs2: Allow immediate GLF_VERIFY_DELETE work + - gfs2: Fix unlinked inode cleanup + - perf mem: Fix printing PERF_MEM_LVLNUM_{L2_MHB|MSC} + - dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only + - PCI: Fix reset_method_store() memory leak + - perf jevents: Don't stop at the first matched pmu when searching a events + table + - perf stat: Close cork_fd when create_perf_stat_counter() failed + - perf stat: Fix affinity memory leaks on error path + - perf trace: Keep exited threads for summary + - perf test attr: Add back missing topdown events + - rust: rbtree: fix `SAFETY` comments that should be `# Safety` sections + - f2fs: compress: fix inconsistent update of i_blocks in + release_compress_blocks and reserve_compress_blocks + - f2fs: fix null-ptr-deref in f2fs_submit_page_bio() + - mailbox, remoteproc: k3-m4+: fix compile testing + - f2fs: fix to account dirty data in __get_secs_required() + - perf dso: Fix symtab_type for kmod compression + - perf disasm: Fix capstone memory leak + - perf probe: Fix libdw memory leak + - perf probe: Correct demangled symbols in C++ program + - rust: kernel: fix THIS_MODULE header path in ThisModule doc comment + - rust: macros: fix documentation of the paste! macro + - PCI: cpqphp: Fix PCIBIOS_* return value confusion + - rust: block: fix formatting of `kernel::block::mq::request` module + - perf disasm: Use disasm_line__free() to properly free disasm_line + - perf disasm: Fix not cleaning up disasm_line in symbol__disassemble_raw() + - virtiofs: use pages instead of pointer for kernel direct IO + - perf ftrace latency: Fix unit on histogram first entry when using --use-nsec + - i3c: master: Remove i3c_dev_disable_ibi_locked(olddev) on device hotjoin + - f2fs: fix the wrong f2fs_bug_on condition in f2fs_do_replace_block + - f2fs: check curseg->inited before write_sum_page in change_curseg + - f2fs: Fix not used variable 'index' + - f2fs: fix to avoid potential deadlock in f2fs_record_stop_reason() + - f2fs: fix to avoid use GC_AT when setting gc_mode as GC_URGENT_LOW or + GC_URGENT_MID + - PCI: qcom: Enable MSI interrupts together with Link up if 'Global IRQ' is + supported + - PCI: qcom-ep: Move controller cleanups to qcom_pcie_perst_deassert() + - PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert() + - PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds + - perf build: Add missing cflags when building with custom libtraceevent + - f2fs: fix race in concurrent f2fs_stop_gc_thread + - f2fs: fix to map blocks correctly for direct write + - f2fs: fix to avoid forcing direct write to use buffered IO on inline_data + inode + - perf trace: avoid garbage when not printing a trace event's arguments + - m68k: mcfgpio: Fix incorrect register offset for CONFIG_M5441x + - m68k: coldfire/device.c: only build FEC when HW macros are defined + - svcrdma: Address an integer overflow + - nfsd: drop inode parameter from nfsd4_change_attribute() + - perf list: Fix topic and pmu_name argument order + - perf trace: Fix tracing itself, creating feedback loops + - perf trace: Do not lose last events in a race + - perf trace: Avoid garbage when not printing a syscall's arguments + - remoteproc: qcom: pas: Remove subdevs on the error path of adsp_probe() + - remoteproc: qcom: adsp: Remove subdevs on the error path of adsp_probe() + - remoteproc: qcom: pas: add minidump_id to SM8350 resources + - rpmsg: glink: use only lower 16-bits of param2 for CMD_OPEN name length + - remoteproc: qcom_q6v5_mss: Re-order writes to the IMEM region + - PCI: endpoint: epf-mhi: Avoid NULL dereference if DT lacks 'mmio' + - NFSD: Prevent NULL dereference in nfsd4_process_cb_update() + - NFSD: Cap the number of bytes copied by nfs4_reset_recoverydir() + - nfsd: release svc_expkey/svc_export with rcu_work + - svcrdma: fix miss destroy percpu_counter in svc_rdma_proc_init() + - NFSD: Fix nfsd4_shutdown_copy() + - nfs_common: must not hold RCU while calling nfsd_file_put_local + - f2fs: fix to do cast in F2FS_{BLK_TO_BYTES, BTYES_TO_BLK} to avoid overflow + - perf bpf-filter: Return -ENOMEM directly when pfi allocation fails + - hwmon: (tps23861) Fix reporting of negative temperatures + - hwmon: (aquacomputer_d5next) Fix length of speed_input array + - phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in + airoha_pcie_phy_init_clk_out() + - phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in + airoha_pcie_phy_init_csr_2l() + - phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in + airoha_pcie_phy_init_ssc_jcpll() + - phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions + - vdpa/mlx5: Fix suboptimal range on iotlb iteration + - vfio/mlx5: Fix an unwind issue in mlx5vf_add_migration_pages() + - vfio/mlx5: Fix unwind flows in mlx5vf_pci_save/resume_device_data() + - selftests/mount_setattr: Fix failures on 64K PAGE_SIZE kernels + - gpio: zevio: Add missed label initialisation + - vfio/pci: Properly hide first-in-list PCIe extended capability + - fs_parser: update mount_api doc to match function signature + - LoongArch: Fix build failure with GCC 15 (-std=gnu23) + - LoongArch: BPF: Sign-extend return values + - power: supply: core: Remove might_sleep() from power_supply_put() + - power: supply: bq27xxx: Fix registers of bq27426 + - power: supply: rt9471: Fix wrong WDT function regfield declaration + - power: supply: rt9471: Use IC status regfield to report real charger status + - fs/ntfs3: Equivalent transition from page to folio + - power: reset: ep93xx: add AUXILIARY_BUS dependency + - net: usb: lan78xx: Fix double free issue with interrupt buffer allocation + - net: usb: lan78xx: Fix memory leak on device unplug by freeing PHY device + - tg3: Set coherent DMA mask bits to 31 for BCM57766 chipsets + - net: usb: lan78xx: Fix refcounting and autosuspend on invalid WoL + configuration + - net: microchip: vcap: Add typegroup table terminators in kunit tests + - netlink: fix false positive warning in extack during dumps + - exfat: fix file being changed by unaligned direct write + - net/l2tp: fix warning in l2tp_exit_net found by syzbot + - s390/iucv: MSG_PEEK causes memory leak in iucv_sock_destruct() + - rtase: Refactor the rtase_check_mac_version_valid() function + - rtase: Correct the speed for RTL907XD-V1 + - rtase: Corrects error handling of the rtase_check_mac_version_valid() + - net/ipv6: delete temporary address if mngtmpaddr is removed or unmanaged + - net: mdio-ipq4019: add missing error check + - marvell: pxa168_eth: fix call balance of pep->clk handling routines + - net: stmmac: dwmac-socfpga: Set RX watchdog interrupt as broken + - octeontx2-af: RPM: Fix mismatch in lmac type + - octeontx2-af: RPM: Fix low network performance + - octeontx2-af: RPM: fix stale RSFEC counters + - octeontx2-af: RPM: fix stale FCFEC counters + - octeontx2-af: Quiesce traffic before NIX block reset + - spi: atmel-quadspi: Fix register name in verbose logging function + - net: hsr: fix hsr_init_sk() vs network/transport headers. + - bnxt_en: Reserve rings after PCIe AER recovery if NIC interface is down + - bnxt_en: Set backplane link modes correctly for ethtool + - bnxt_en: Fix queue start to update vnic RSS table + - bnxt_en: Fix receive ring space parameters when XDP is active + - bnxt_en: Refactor bnxt_ptp_init() + - bnxt_en: Unregister PTP during PCI shutdown and suspend + - Bluetooth: MGMT: Fix slab-use-after-free Read in set_powered_sync + - Bluetooth: MGMT: Fix possible deadlocks + - llc: Improve setsockopt() handling of malformed user input + - rxrpc: Improve setsockopt() handling of malformed user input + - tcp: Fix use-after-free of nreq in reqsk_timer_handler(). + - ip6mr: fix tables suspicious RCU usage + - ipmr: fix tables suspicious RCU usage + - iio: light: al3010: Fix an error handling path in al3010_probe() + - usb: using mutex lock and supporting O_NONBLOCK flag in iowarrior_read() + - usb: yurex: make waiting on yurex_write interruptible + - USB: chaoskey: fail open after removal + - USB: chaoskey: Fix possible deadlock chaoskey_list_lock + - misc: apds990x: Fix missing pm_runtime_disable() + - devres: Fix page faults when tracing devres from unloaded modules + - usb: gadget: uvc: wake pump everytime we update the free list + - interconnect: qcom: icc-rpmh: probe defer incase of missing QoS clock + dependency + - iio: backend: fix wrong pointer passed to IS_ERR() + - iio: adc: ad4000: fix reading unsigned data + - iio: adc: ad4000: Check for error code from devm_mutex_init() call + - iio: adc: pac1921: Check for error code from devm_mutex_init() call + - iio: accel: adxl380: fix raw sample read + - phy: realtek: usb: fix NULL deref in rtk_usb2phy_probe + - phy: realtek: usb: fix NULL deref in rtk_usb3phy_probe + - counter: stm32-timer-cnt: Add check for clk_enable() + - counter: ti-ecap-capture: Add check for clk_enable() + - bus: mhi: host: Switch trace_mhi_gen_tre fields to native endian + - usb: typec: fix potential array underflow in ucsi_ccg_sync_control() + - firmware_loader: Fix possible resource leak in fw_log_firmware_info() + - ALSA: hda/realtek: Update ALC256 depop procedure + - drm/radeon: Fix spurious unplug event on radeon HDMI + - drm/amd/display: Fix null check for pipe_ctx->plane_state in + dcn20_program_pipe + - drm/amd/display: Fix null check for pipe_ctx->plane_state in hwss_setup_dpp + - ASoC: imx-audmix: Add NULL check in imx_audmix_probe + - drm/xe/ufence: Wake up waiters after setting ufence->signalled + - apparmor: fix 'Do simple duplicate message elimination' + - ALSA: core: Fix possible NULL dereference caused by kunit_kzalloc() + - ASoC: amd: yc: Fix for enabling DMIC on acp6x via _DSD entry + - ASoC: mediatek: Check num_codecs is not zero to avoid panic during probe + - s390/pci: Fix potential double remove of hotplug slot + - f2fs: fix fiemap failure issue when page size is 16KB + - net_sched: sch_fq: don't follow the fast path if Tx is behind now + - xen: Fix the issue of resource not being properly released in + xenbus_dev_probe() + - ALSA: usb-audio: Fix potential out-of-bound accesses for Extigy and Mbox + devices + - ALSA: usb-audio: Fix out of bounds reads when finding clock sources + - usb: ehci-spear: fix call balance of sehci clk handling routines + - usb: typec: ucsi: glink: fix off-by-one in connector_status + - xfs: fix simplify extent lookup in xfs_can_free_eofblocks + - ext4: supress data-race warnings in ext4_free_inodes_{count,set}() + - ext4: fix FS_IOC_GETFSMAP handling + - MAINTAINERS: update location of media main tree + - docs: media: update location of the media patches + - jfs: xattr: check invalid xattr size more strictly + - ASoC: amd: yc: Add a quirk for microfone on Lenovo ThinkPad P14s Gen 5 + 21MES00B00 + - ASoC: codecs: Fix atomicity violation in snd_soc_component_get_drvdata() + - ASoC: da7213: Populate max_register to regmap_config + - perf/x86/intel/pt: Fix buffer full but size is 0 case + - crypto: x86/aegis128 - access 32-bit arguments as 32-bit + - KVM: x86: switch hugepage recovery thread to vhost_task + - KVM: x86/mmu: Skip the "try unsync" path iff the old SPTE was a leaf SPTE + - KVM: x86: add back X86_LOCAL_APIC dependency + - KVM: x86: Break CONFIG_KVM_X86's direct dependency on KVM_INTEL || KVM_AMD + - powerpc/pseries: Fix KVM guest detection for disabling hardlockup detector + - KVM: arm64: vgic-v3: Sanitise guest writes to GICR_INVLPIR + - KVM: arm64: Ignore PMCNTENSET_EL0 while checking for overflow status + - Revert "KVM: VMX: Move LOAD_IA32_PERF_GLOBAL_CTRL errata handling out of + setup_vmcs_config()" + - KVM: arm64: Don't retire aborted MMIO instruction + - KVM: arm64: vgic-its: Clear ITE when DISCARD frees an ITE + - KVM: arm64: Get rid of userspace_irqchip_in_use + - KVM: arm64: vgic-its: Add a data length check in vgic_its_save_* + - KVM: arm64: vgic-its: Clear DTE when MAPD unmaps a device + - Compiler Attributes: disable __counted_by for clang < 19.1.3 + - PCI: Fix use-after-free of slot->bus on hot remove + - LoongArch: Explicitly specify code model in Makefile + - clk: clk-loongson2: Fix memory corruption bug in struct + loongson2_clk_provider + - clk: clk-loongson2: Fix potential buffer overflow in flexible-array member + access + - fsnotify: fix sending inotify event with unexpected filename + - fsnotify: Fix ordering of iput() and watched_objects decrement + - comedi: Flush partial mappings in error case + - apparmor: test: Fix memory leak for aa_unpack_strdup() + - iio: dac: adi-axi-dac: fix wrong register bitfield + - tty: ldsic: fix tty_ldisc_autoload sysctl's proc_handler + - locking/lockdep: Avoid creating new name string literals in + lockdep_set_subclass() + - tools/nolibc: s390: include std.h + - fcntl: make F_DUPFD_QUERY associative + - pinctrl: qcom: spmi: fix debugfs drive strength + - dt-bindings: pinctrl: samsung: Fix interrupt constraint for variants with + fallbacks + - dt-bindings: iio: dac: ad3552r: fix maximum spi speed + - exfat: fix uninit-value in __exfat_get_dentry_set + - exfat: fix out-of-bounds access of directory entries + - xhci: Fix control transfer error on Etron xHCI host + - xhci: Combine two if statements for Etron xHCI host + - xhci: Don't perform Soft Retry for Etron xHCI host + - xhci: Don't issue Reset Device command to Etron xHCI host + - Bluetooth: Fix type of len in rfcomm_sock_getsockopt{,_old}() + - usb: xhci: Limit Stop Endpoint retries + - usb: xhci: Fix TD invalidation under pending Set TR Dequeue + - usb: xhci: Avoid queuing redundant Stop Endpoint commands + - ARM: dts: omap36xx: declare 1GHz OPP as turbo again + - wifi: ath12k: fix warning when unbinding + - wifi: rtlwifi: Drastically reduce the attempts to read efuse in case of + failures + - wifi: nl80211: fix bounds checker error in nl80211_parse_sched_scan + - wifi: ath12k: fix crash when unbinding + - wifi: brcmfmac: release 'root' node in all execution paths + - Revert "fs: don't block i_writecount during exec" + - Revert "f2fs: remove unreachable lazytime mount option parsing" + - Revert "usb: gadget: composite: fix OS descriptors w_value logic" + - serial: sh-sci: Clean sci_ports[0] after at earlycon exit + - Revert "serial: sh-sci: Clean sci_ports[0] after at earlycon exit" + - io_uring: fix corner case forgetting to vunmap + - io_uring: check for overflows in io_pin_pages + - blk-settings: round down io_opt to physical_block_size + - gpio: exar: set value when external pull-up or pull-down is present + - netfilter: ipset: add missing range check in bitmap_ip_uadt + - spi: Fix acpi deferred irq probe + - mtd: spi-nor: core: replace dummy buswidth from addr to data + - cpufreq: mediatek-hw: Fix wrong return value in mtk_cpufreq_get_cpu_power() + - cifs: support mounting with alternate password to allow password rotation + - parisc/ftrace: Fix function graph tracing disablement + - RISC-V: Scalar unaligned access emulated on hotplug CPUs + - RISC-V: Check scalar unaligned access on all CPUs + - ksmbd: fix use-after-free in SMB request handling + - smb: client: fix NULL ptr deref in crypto_aead_setkey() + - platform/chrome: cros_ec_typec: fix missing fwnode reference decrement + - irqchip/irq-mvebu-sei: Move misplaced select() callback to SEI CP domain + - x86/CPU/AMD: Terminate the erratum_1386_microcode array + - ubi: wl: Put source PEB into correct list if trying locking LEB failed + - um: ubd: Do not use drvdata in release + - um: net: Do not use drvdata in release + - dt-bindings: serial: rs485: Fix rs485-rts-delay property + - serial: 8250_fintek: Add support for F81216E + - serial: 8250: omap: Move pm_runtime_get_sync + - serial: amba-pl011: Fix RX stall when DMA is used + - serial: amba-pl011: fix build regression + - Revert "block, bfq: merge bfq_release_process_ref() into + bfq_put_cooperator()" + - mtd: ubi: fix unreleased fwnode_handle in find_volume_fwnode() + - block: Prevent potential deadlock in blk_revalidate_disk_zones() + - um: vector: Do not use drvdata in release + - sh: cpuinfo: Fix a warning for CONFIG_CPUMASK_OFFSTACK + - iio: gts: Fix uninitialized symbol 'ret' + - ublk: fix ublk_ch_mmap() for 64K page size + - arm64: tls: Fix context-switching of tpidrro_el0 when kpti is enabled + - block: fix missing dispatching request when queue is started or unquiesced + - block: fix ordering between checking QUEUE_FLAG_QUIESCED request adding + - block: fix ordering between checking BLK_MQ_S_STOPPED request adding + - blk-mq: Make blk_mq_quiesce_tagset() hold the tag list mutex less long + - gve: Flow steering trigger reset only for timeout error + - HID: wacom: Interpret tilt data from Intuos Pro BT as signed values + - i40e: Fix handling changed priv flags + - media: wl128x: Fix atomicity violation in fmc_send_cmd() + - media: intel/ipu6: do not handle interrupts when device is disabled + - arm64: dts: mediatek: mt8186-corsola-voltorb: Merge speaker codec nodes + - netdev-genl: Hold rcu_read_lock in napi_get + - soc: fsl: cpm1: qmc: Set the ret error code on platform_get_irq() failure + - soc: fsl: rcpm: fix missing of_node_put() in copy_ippdexpcr1_setting() + - media: v4l2-core: v4l2-dv-timings: check cvt/gtf result + - x86/mm: Carve out INVLPG inline asm for use by others + - x86/microcode/AMD: Flush patch buffer mapping after application + - ALSA: rawmidi: Fix kvfree() call in spinlock + - ALSA: ump: Fix evaluation of MIDI 1.0 FB info + - ALSA: pcm: Add sanity NULL check for the default mmap fault handler + - ALSA: hda/realtek: Update ALC225 depop procedure + - ALSA: hda/realtek: Enable speaker pins for Medion E15443 platform + - ALSA: hda/realtek: Set PCBeep to default value for ALC274 + - ALSA: hda/realtek: Fix Internal Speaker and Mic boost of Infinix Y4 Max + - ALSA: hda/realtek: fix mute/micmute LEDs don't work for EliteBook X G1i + - ALSA: hda/realtek: Apply quirk for Medion E15433 + - fs/smb/client: implement chmod() for SMB3 POSIX Extensions + - smb: client: fix use-after-free of signing key + - smb3: request handle caching when caching directories + - smb: client: handle max length for SMB symlinks + - smb: Don't leak cfid when reconnect races with open_cached_dir + - smb: prevent use-after-free due to open_cached_dir error paths + - smb: During unmount, ensure all cached dir instances drop their dentry + - usb: misc: ljca: set small runtime autosuspend delay + - usb: misc: ljca: move usb_autopm_put_interface() after wait for response + - usb: dwc3: ep0: Don't clear ep0 DWC3_EP_TRANSFER_STARTED + - usb: musb: Fix hardware lockup on first Rx endpoint request + - usb: dwc3: gadget: Add missing check for single port RAM in TxFIFO resizing + logic + - usb: dwc3: gadget: Fix checking for number of TRBs left + - usb: dwc3: gadget: Fix looping of queued SG entries + - staging: vchiq_arm: Fix missing refcount decrement in error path for fw_node + - counter: stm32-timer-cnt: fix device_node handling in probe_encoder() + - ublk: fix error code for unsupported command + - lib: string_helpers: silence snprintf() output truncation warning + - f2fs: fix to do sanity check on node blkaddr in truncate_node() + - ipc: fix memleak if msg_init_ns failed in create_ipc_ns + - Input: cs40l50 - fix wrong usage of INIT_WORK() + - NFSD: Prevent a potential integer overflow + - SUNRPC: make sure cache entry active before cache_show + - um: Fix potential integer overflow during physmem setup + - um: Fix the return value of elf_core_copy_task_fpregs + - kfifo: don't include dma-mapping.h in kfifo.h + - um: ubd: Initialize ubd's disk pointer in ubd_add + - um: Always dump trace for specified task in show_stack + - NFSv4.0: Fix a use-after-free problem in the asynchronous open() + - nfs/localio: must clear res.replen in nfs_local_read_done + - rtc: st-lpc: Use IRQF_NO_AUTOEN flag in request_irq() + - rtc: abx80x: Fix WDT bit position of the status register + - rtc: check if __rtc_read_time was successful in rtc_timer_do_work() + - ubi: fastmap: wl: Schedule fm_work if wear-leveling pool is empty + - ubifs: Correct the total block count by deducting journal reservation + - ubi: fastmap: Fix duplicate slab cache names while attaching + - ubifs: authentication: Fix use-after-free in ubifs_tnc_end_commit + - jffs2: fix use of uninitialized variable + - hostfs: Fix the NULL vs IS_ERR() bug for __filemap_get_folio() + - net/9p/usbg: fix handling of the failed kzalloc() memory allocation + - rtc: rzn1: fix BCD to rtc_time conversion errors + - Revert "nfs: don't reuse partially completed requests in + nfs_lock_and_join_requests" + - nvme/multipath: Fix RCU list traversal to use SRCU primitive + - blk-mq: add non_owner variant of start_freeze/unfreeze queue APIs + - block: model freeze & enter queue as lock for supporting lockdep + - block: fix uaf for flush rq while iterating tags + - block: return unsigned int from bdev_io_min + - nvme-fabrics: fix kernel crash while shutting down controller + - 9p/xen: fix init sequence + - 9p/xen: fix release of IRQ + - perf/arm-smmuv3: Fix lockdep assert in ->event_init() + - perf/arm-cmn: Ensure port and device id bits are set properly + - smb: client: disable directory caching when dir_cache_timeout is zero + - x86/Documentation: Update algo in init_size description of boot protocol + - cifs: Fix parsing native symlinks relative to the export + - cifs: Fix parsing reparse point with native symlink in SMB1 non-UNICODE + session + - rtc: ab-eoz9: don't fail temperature reads on undervoltage notification + - Rename .data.unlikely to .data..unlikely + - Rename .data.once to .data..once to fix resetting WARN*_ONCE + - kbuild: deb-pkg: Don't fail if modules.order is missing + - smb: Initialize cfid->tcon before performing network ops + - block: Don't allow an atomic write be truncated in blkdev_write_iter() + - modpost: remove incorrect code in do_eisa_entry() + - cifs: during remount, make sure passwords are in sync + - cifs: unlock on error in smb3_reconfigure() + - nfs: ignore SB_RDONLY when mounting nfs + - sunrpc: clear XPRT_SOCK_UPD_TIMEOUT when reset transport + - SUNRPC: timeout and cancel TLS handshake with -ETIMEDOUT + - sunrpc: fix one UAF issue caused by sunrpc kernel tcp socket + - nfs/blocklayout: Don't attempt unregister for invalid block device + - nfs/blocklayout: Limit repeat device registration on failure + - block, bfq: fix bfqq uaf in bfq_limit_depth() + - brd: decrease the number of allocated pages which discarded + - sh: intc: Fix use-after-free bug in register_intc_controller() + - tools/power turbostat: Fix trailing '\n' parsing + - tools/power turbostat: Fix child's argument forwarding + - block: always verify unfreeze lock on the owner task + - block: don't verify IO lock for freeze/unfreeze in elevator_init_mq() + - Linux 6.12.2 + + * Plucky update: v6.12.1 upstream stable release (LP: #2091624) + - hv_sock: Initializing vsk->trans to NULL to prevent a dangling pointer + - media: uvcvideo: Skip parsing frames of type UVC_VS_UNDEFINED in + uvc_parse_format + - mm/mmap: fix __mmap_region() error handling in rare merge failure case + - Linux 6.12.1 + + * Fix compile warnings (LP: #2089676) + - SAUCE: Revert "UBUNTU: SAUCE: (no-up) Allow filtering of cpufreq drivers" + - SAUCE: r8169: Fix compile warning + + * Intel Be201 Bluetooth hardware error 0x0f on Arrow Lake (LP: #2088151) + - Bluetooth: btintel: Add DSBR support for BlazarIW, BlazarU and GaP + + * python perf module missing in realtime kernel (LP: #2089411) + - [Packaging] linux-tools: Link directories rather than individual files + - [Packaging] linux-tools: Fix python perf library packaging + + * Miscellaneous Ubuntu changes + - [Packaging] Fix source file collection + - [Packaging] Build all packages for linux-unstable + - [Packaging] linux-lib-rust: Fix incorrect package name + - [Packaging] linux-tools: Put libperf-jvmti.so into lib/ + - [Packaging] linux-bpf-dev: Restructure packaging + - [Packaging] linux-bpf-dev: Skip packaging for additional kernel flavors + - [Config] updateconfigs following v6.12.2 stable import + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] linux-bpf-dev: Skip packaging for additional + kernel flavors" + - Revert "UBUNTU: [Packaging] linux-bpf-dev: Restructure packaging" + + -- Paolo Pisati Thu, 12 Dec 2024 17:17:27 +0100 + +linux-unstable (6.12.0-4.4) plucky; urgency=medium + + * plucky/linux-unstable: 6.12.0-4.4 -proposed tracker (LP: #2089753) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.11.12) + + * Random flickering with Intel i915 (Comet Lake and Kaby Lake) on Linux 6.8+ + (LP: #2086587) + - SAUCE: iommu/intel: disable DMAR for KBL and CML integrated gfx + + * Miscellaneous Ubuntu changes + - [Packaging] avoid arch-specific certificate creation + + * Miscellaneous upstream changes + - Revert "lsm: remove LSM_COUNT and LSM_CONFIG_COUNT" + - Revert "lsm: replace indirect LSM hook calls with static calls" + - Revert "init/main.c: Initialize early LSMs after arch code, static keys and + calls." + + -- Paolo Pisati Wed, 27 Nov 2024 11:50:01 +0100 + +linux-unstable (6.12.0-3.3) plucky; urgency=medium + + * plucky/linux-unstable: 6.12.0-3.3 -proposed tracker (LP: #2088427) + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.12 rebase + + -- Paolo Pisati Mon, 18 Nov 2024 09:57:30 +0100 + +linux-unstable (6.12.0-2.2) plucky; urgency=medium + + * plucky/linux-unstable: 6.12.0-2.2 -proposed tracker (LP: #2088046) + + * Miscellaneous Ubuntu changes + - debian.master/dkms-versions: temporarily remove dkmses + + -- Paolo Pisati Wed, 13 Nov 2024 10:59:36 +0100 + +linux-unstable (6.12.0-1.1) plucky; urgency=medium + + * plucky/linux-unstable: 6.12.0-1.1 -proposed tracker (LP: #2087956) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.11.12) + + * OVTI08F4:00: number of CSI2 data lanes 2 is not supported (LP: #2084059) + - SAUCE: media: ipu-bridge: Add support for additional link frequencies + + * [Oracular] Allow overriding Rust tools (LP: #2084693) + - [Packaging] Allow rust overrides + + * Support ov05c10 camera sensor in Intel ipu-bridge (LP: #2081866) + - SAUCE: media: Support ov05c10 camera sensor + + * Lack of UART boot output on rb3gen2 even with earlycon (LP: #2083559) + - [Config] move qcom clk and serial options as builtin + + * Missing Bluetooth device IDs for new Mediatek MT7920/MT7925 (LP: #2078878) + - SAUCE: Bluetooth: btusb: Add USB HW IDs for MT7920/MT7925 + + * Support Qualcomm WCN7851 Dual Bluetooth Adapter 0489:E0F3 (LP: #2081796) + - SAUCE: Bluetooth: btusb: Add one more ID 0x0489:0xe0f3 for Qualcomm WCN785x + + * re-enable Ubuntu FAN in the Noble kernel (LP: #2064508) + - SAUCE: fan: add VXLAN implementation + - SAUCE: fan: Fix NULL pointer dereference + - SAUCE: fan: support vxlan strict length validation + + * update for V3 kernel bits and improved multiple fan slice support + (LP: #1470091) // re-enable Ubuntu FAN in the Noble kernel (LP: #2064508) + - SAUCE: fan: tunnel multiple mapping mode (v3) + + * Miscellaneous Ubuntu changes + - [packaging] move to v6.12 and rename to linux-unstable + - [Config] Update annotations after rebase to v6.12-rc4 + - [Packaging] use DEB_ prefix for some variables + - debian.master/dkms-versions: temporarily remove most dkms packages + - [Packaging] Sort build dependencies alphabetically + - [Packaging] Add list of used source files to buildinfo package + - [Packaging] replace $(DROOT) with debian + - [Config] updateconfigs following v6.12-rc7 rebase + - [packaging] garbage collect some invalid/unnecessary flags + + -- Paolo Pisati Tue, 12 Nov 2024 14:56:47 +0100 + +linux-unstable (6.12.0-0.0) plucky; urgency=medium + + * Dummy entry. + + -- Timo Aaltonen Thu, 03 Oct 2024 15:00:32 +0300 + +linux (6.11.0-8.8) oracular; urgency=medium + + * oracular/linux: 6.11.0-8.8 -proposed tracker (LP: #2080825) + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.08.12) + + * [SRU] Disable CONFIG_TCG_TPM2_HMAC to avoid performance loss after v6.10 + (LP: #2080322) + - [Config] disable CONFIG_TCG_TPM2_HMAC by default + + * Integrated Sensor Hub (ISH) support for Intel Lunar Lake platform + (LP: #2071698) + - Documentation: hid: intel-ish-hid: Add vendor custom firmware loading + - HID: intel-ish-hid: Use CPU generation string in driver_data + - hid: intel-ish-hid: Add support for vendor customized firmware loading + + * Miscellaneous Ubuntu changes + - [Packaging] Purge obsolete upstart files + - [Packaging] tools/hv: don't build/install hv_fcopy_uio_daemon on arm64 + - [Config] Update toolchain versions + - SAUCE: rust: Fix rustc source path for the new rustc packaging + - [Packaging] Don't force bindgen version + - [Config] Re-enable rust support for amd64 + + -- Timo Aaltonen Mon, 16 Sep 2024 15:04:18 +0300 + +linux (6.11.0-7.7) oracular; urgency=medium + + * oracular/linux: 6.11.0-7.7 -proposed tracker (LP: #2079949) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [1/99]: LSM: Infrastructure management of the sock + security + - SAUCE: apparmor4.0.0 [2/99]: LSM: Add the lsmblob data structure. + - SAUCE: apparmor4.0.0 [3/99]: LSM: Use lsmblob in security_audit_rule_match + - SAUCE: apparmor4.0.0 [4/99]: LSM: Call only one hook for audit rules + - SAUCE: apparmor4.0.0 [5/99]: LSM: Add lsmblob_to_secctx hook + - SAUCE: apparmor4.0.0 [6/99]: Audit: maintain an lsmblob in audit_context + - SAUCE: apparmor4.0.0 [7/99]: LSM: Use lsmblob in security_ipc_getsecid + - SAUCE: apparmor4.0.0 [8/99]: Audit: Update shutdown LSM data + - SAUCE: apparmor4.0.0 [9/99]: LSM: Use lsmblob in security_current_getsecid + - SAUCE: apparmor4.0.0 [10/99]: LSM: Use lsmblob in security_inode_getsecid + - SAUCE: apparmor4.0.0 [11/99]: Audit: use an lsmblob in audit_names + - SAUCE: apparmor4.0.0 [12/99]: LSM: Create new security_cred_getlsmblob LSM + hook + - SAUCE: apparmor4.0.0 [13/99]: Audit: Change context data from secid to + lsmblob + - SAUCE: apparmor4.0.0 [14/99]: Netlabel: Use lsmblob for audit data + - SAUCE: apparmor4.0.0 [15/99]: LSM: Ensure the correct LSM context releaser + - SAUCE: apparmor4.0.0 [16/99]: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [17/99]: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [18/99]: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [19/99]: LSM: lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [20/99]: LSM: security_lsmblob_to_secctx module + selection + - SAUCE: apparmor4.0.0 [21/99]: Audit: Create audit_stamp structure + - SAUCE: apparmor4.0.0 [22/99]: Audit: Allow multiple records in an + audit_buffer + - SAUCE: apparmor4.0.0 [23/99]: Audit: Add record for multiple task security + contexts + - SAUCE: apparmor4.0.0 [24/99]: audit: multiple subject lsm values for + netlabel + - SAUCE: apparmor4.0.0 [25/99]: Audit: Add record for multiple object contexts + - SAUCE: apparmor4.0.0 [26/99]: LSM: Remove unused lsmcontext_init() + - SAUCE: apparmor4.0.0 [27/99]: LSM: Improve logic in security_getprocattr + - SAUCE: apparmor4.0.0 [28/99]: LSM: secctx provider check on release + - SAUCE: apparmor4.0.0 [29/99]: LSM: Single calls in socket_getpeersec hooks + - SAUCE: apparmor4.0.0 [30/99]: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [31/99]: LSM: Identify which LSM handles the context + string + - SAUCE: apparmor4.0.0 [32/99]: AppArmor: Remove the exclusive flag + - SAUCE: apparmor4.0.0 [33/99]: LSM: Add mount opts blob size tracking + - SAUCE: apparmor4.0.0 [34/99]: LSM: allocate mnt_opts blobs instead of module + specific data + - SAUCE: apparmor4.0.0 [35/99]: LSM: Infrastructure management of the key + security blob + - SAUCE: apparmor4.0.0 [36/99]: LSM: Infrastructure management of the mnt_opts + security blob + - SAUCE: apparmor4.0.0 [37/99]: LSM: Remove lsmblob scaffolding + - SAUCE: apparmor4.0.0 [38/99]: LSM: Allow reservation of netlabel + - SAUCE: apparmor4.0.0 [39/99]: LSM: restrict security_cred_getsecid() to a + single LSM + - SAUCE: apparmor4.0.0 [40/99]: Smack: Remove LSM_FLAG_EXCLUSIVE + - SAUCE: apparmor4.0.0 [41/99]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [41/99]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [42/99]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [43/99]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [44/99]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [45/99]: af_unix mediation + - SAUCE: apparmor4.0.0 [46/99]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [47/99] fixup inode_set_attr + - SAUCE: apparmor4.0.0 [48/99]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [49/99]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [50/99]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [51/99]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [52/99]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [53/99]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [54/99]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [55/99]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [56/99]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [57/99]: prompt - fix caching + - SAUCE: apparmor4.0.0 [58/99]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [59/99]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [60/99]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [61/99]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [62/99]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [63/99]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [64/93] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [65/99]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [66/99]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [67/99]: userns - make it so special unconfined + profiles can mediate user namespaces + - SAUCE: apparmor4.0.0 [68/99]: add io_uring mediation + - SAUCE: apparmor4.0.0 [69/99]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [70/99]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [71/99]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [72/99]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [73/99]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [74/99]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [75/99]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [76/99]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [77/99]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [78/99]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [79/99]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [80/99]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [81/99]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [82/99]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [83/99]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [84/99]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [85/99]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [86/99]: fixup notify + - SAUCE: apparmor4.0.0 [87/99]: apparmor: add fine grained ipv4/ipv6 mediation + - SAUCE: apparmor4.0.0 [88/99]: apparmor: disable tailglob responses for now + - SAUCE: apparmor4.0.0 [89/99]: apparmor: Fix notify build warnings + - SAUCE: apparmor4.0.0 [90/99]: fix reserved mem for when we save ipv6 + addresses + - SAUCE: apparmor4.0.0 [91/99]: fix address mapping for recvfrom + - SAUCE: apparmor4.0.0 [92/99]: apparmor: add support for 2^24 states to the + dfa state machine. + - SAUCE: apparmor4.0.0 [93/99]: apparmor: advertise to userspace support of + user upcall for file rules. + - SAUCE: apparmor4.0.0 [94/99]: apparmor: allocate xmatch for nullpdf inside + aa_alloc_null + - SAUCE: apparmor4.0.0 [95/99]: apparmor: properly handle cx/px lookup failure + for complain + - SAUCE: apparmor4.0.0 [96/99]: apparmor: fix prompt failing during large down + loads + - SAUCE: apparmor4.0.0 [97/99]: apparmor: fix allow field in notification + - SAUCE: apparmor4.0.0 [98/99]: fix build error with !CONFIG_SECURITY + - SAUCE: apparmor4.0.0 [99/99]: fix build error with in nfs4xdr + + * Intel Lunar Lake / Battlemage enablement (LP: #2076209) + - drm/xe/lnl: Drop force_probe requirement + - drm/xe: Support 'nomodeset' kernel command-line option + - drm/i915/display: Plane capability for 64k phys alignment + - drm/xe: Align all VRAM scanout buffers to 64k physical pages when needed. + - drm/xe: Use separate rpm lockdep map for non-d3cold-capable devices + - drm/xe: Fix NPD in ggtt_node_remove() + - drm/xe/bmg: Drop force_probe requirement + - drm/xe/gsc: Fix FW status if the firmware is already loaded + - drm/xe/gsc: Track the platform in the compatibility version + - drm/xe/gsc: Wedge the device if the GSCCS reset fails + - drm/i915/bios: Update new entries in VBT BDB block definitions + - drm/xe/hwmon: Treat hwmon as a per-device concept + - drm/xe: s/xe_tile_migrate_engine/xe_tile_migrate_exec_queue + - drm/xe: Add xe_vm_pgtable_update_op to xe_vma_ops + - drm/xe: Add xe_exec_queue_last_fence_test_dep + - drm/xe: Add timeout to preempt fences + - drm/xe: Convert multiple bind ops into single job + - drm/xe: Update VM trace events + - drm/xe: Update PT layer with better error handling + - drm/xe: Add VM bind IOCTL error injection + - dma-buf: Split out dma fence array create into alloc and arm functions + - drm/xe: Invalidate media_gt TLBs in PT code + - drm/i915/display: Fix BMG CCS modifiers + - drm/xe: Use xe_pm_runtime_get in xe_bo_move() if reclaim-safe. + - drm/xe: Remove extra dma_fence_put on xe_sync_entry_add_deps failure + + * [24.10 FEAT] [KRN1911] Vertical CPU Polarization Support Stage 2 + (LP: #2072760) + - s390/wti: Introduce infrastructure for warning track interrupt + - s390/wti: Prepare graceful CPU pre-emption on wti reception + - s390/wti: Add wti accounting for missed grace periods + - s390/wti: Add debugfs file to display missed grace periods per cpu + - s390/topology: Add sysctl handler for polarization + - s390/topology: Add config option to switch to vertical during boot + - s390/smp: Add cpu capacities + - s390/hiperdispatch: Introduce hiperdispatch + - s390/hiperdispatch: Add steal time averaging + - s390/hiperdispatch: Add trace events + - s390/hiperdispatch: Add hiperdispatch sysctl interface + - s390/hiperdispatch: Add hiperdispatch debug attributes + - s390/hiperdispatch: Add hiperdispatch debug counters + - [Config] Initial set of new options HIPERDISPATCH_ON and + SCHED_TOPOLOGY_VERTICAL to yes for s390x + + * Remove non-LPAE kernel flavor (LP: #2025265) + - [Packaging] Drop control.d/vars.generic-lpae + + * generate and ship vmlinux.h to allow packages to build BPF CO-RE + (LP: #2050083) + - [Packaging] Don't call dh_all on linux-bpf-dev unless on master kernel + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.11-rc7 rebase + + -- Timo Aaltonen Mon, 09 Sep 2024 13:38:09 +0300 + +linux (6.11.0-6.6) oracular; urgency=medium + + * oracular/linux: 6.11.0-6.6 -proposed tracker (LP: #2077949) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.08.12) + - [Packaging] update Ubuntu.md + + * Pull in latest X13s commits (LP: #2078929) + - arm64: dts: qcom: sc8280xp-x13s: disable PCIe perst pull downs + - arm64: dts: qcom: sc8280xp-x13s: clean up PCIe2a pinctrl node + - media: qcom: camss: Remove use_count guard in stop_streaming + - media: qcom: camss: Fix ordering of pm_runtime_enable + - arm64: dts: qcom: sc8280xp-x13s: Enable RGB sensor + - wifi: ath11k: fix NULL pointer dereference in ath11k_mac_get_eirp_power() + - Revert "wifi: ath11k: restore country code during resume" + - Revert "wifi: ath11k: support hibernation" + - SAUCE: media: ov5675: Fix power on/off delay timings + - SAUCE: media: dt-bindings: Document SC8280XP/SM8350 Venus + - SAUCE: media: venus: core: Remove trailing commas from of match entries + - SAUCE: media: venus: hfi_venus: Support only updating certain bits with + presets + - SAUCE: media: platform: venus: Add optional LLCC path + - SAUCE: media: venus: core: Add SM8350 resource struct + - SAUCE: media: venus: core: Add SC8280XP resource struct + - SAUCE: arm64: dts: qcom: sc8280xp: Add Venus + - SAUCE: arm64: dts: qcom: sc8280xp-x13s: Enable Venus + - SAUCE: phy: qcom-qmp-combo: drop regulator loads + - SAUCE: phy: qcom-edp: drop regulator loads + - SAUCE: i2c: qcom-cci: Stop complaining about DT set clock rate + - SAUCE: clk: qcom: gcc-sc8280xp: don't use parking clk_ops for QUPs + + * Intel Lunar Lake / Battlemage enablement (LP: #2076209) + - drm/i915: Skip programming FIA link enable bits for MTL+ + - drm/i915: disable fbc due to Wa_16023588340 + - drm/xe/xe2lpm: Extend Wa_16021639441 + - drm/i915/display: Cache adpative sync caps to use it later + - drm/xe: Generate oob before compiling anything + - drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock + - drm/xe/gsc: add Battlemage support + - drm/xe/migrate: Handle clear ccs logic for xe2 dgfx + - drm/xe/migrate: Add helper function to program identity map + - drm/xe/xe2: Introduce identity map for compressed pat for vram + - drm/xe/xe_migrate: Handle migration logic for xe2+ dgfx + - drm/xe/fbdev: Limit the usage of stolen for LNL+ + - drm/xe/uapi: Expose SIMD16 EU mask in topology query + - drm/xe: Fix warning on unreachable statement + - drm/i915/hdcp: Add encoder check in intel_hdcp_get_capability + - drm/i915/hdcp: Add encoder check in hdcp2_get_capability + - drm/xe/hdcp: Check GSC structure validity + - drm/i915/dp: Clear VSC SDP during post ddi disable routine + - drm/xe/huc: Define HuC binary for LNL + - drm/xe/gsc: Define GSC binary for LNL + - drm/xe/huc: Define HuC binary for BMG + - drm/xe/xe2hpg: Introduce performance tuning changes for Xe2_HPG + - drm/i915/display/dp: Compute AS SDP when vrr is also enabled + - drm/xe: Move and export xe_hw_engine lookup. + - drm/xe/xe2: Enable Priority Mem Read + - drm/xe/xe2: Introduce performance changes + - drm/xe/xe2: Add performance turning changes + - drm/xe/guc: Bump minimum required GuC version to v70.29.2 + - drm/xe/guc: Define GuC version v70.29.2 for BMG + - drm/xe/guc: Enable w/a 14022293748 and 22019794406 + - drm/xe: Move enable host l2 VRAM post MCR init + - drm/xe: Write all slices if its mcr register + - drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register + - drm/i915/pps: Disable DPLS_GATING around pps sequence + - drm/xe: fix engine_class bounds check again + - drm/xe/uc: Use managed bo for HuC and GSC objects + - drm/xe: Use reserved copy engine for user binds on faulting devices + - drm/xe/display: Match i915 driver suspend/resume sequences better + - drm/i915: move rawclk from runtime to display runtime info + - drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO() + - drm/i915/psr: Prevent Panel Replay if CRC calculation is enabled + - drm/i915/display: Don't enable decompression on Xe2 with Tile4 + - drm/fourcc: define Intel Xe2 related tile4 ccs modifiers + - drm/i915/display: allow creation of Xe2 ccs framebuffers + - drm/xe/display: fix compat IS_DISPLAY_STEP() range end + - drm/xe/display: remove intel_display_step_name() to simplify + - drm/xe/display: remove the unused compat HAS_GMD_ID() + - drm/xe/step: define more steppings E-J + - drm/i915/display: rename IS_DISPLAY_IP_RANGE() to IS_DISPLAY_VER_FULL() + - drm/i915/display: rename IS_DISPLAY_IP_STEP() to IS_DISPLAY_VER_STEP() + - drm/i915/display: identify display steppings in display probe + - drm/i915/display: switch to display detected steppings + - drm/i915: remove display stepping handling + - drm/xe: remove display stepping handling + - drm/xe: Removed unused xe_ggtt_printk + - drm/xe: Introduce GGTT documentation + - drm/xe: Remove unnecessary drm_mm.h includes + - drm/{i915, xe}: Avoid direct inspection of dpt_vma from outside dpt + - drm/xe: Encapsulate drm_mm_node inside xe_ggtt_node + - drm/xe: Rename xe_ggtt_node related functions + - drm/xe: Limit drm_mm_node_allocated access to xe_ggtt_node + - drm/xe: Introduce xe_ggtt_largest_hole + - drm/xe: Introduce xe_ggtt_print_holes + - drm/xe: Refactor xe_ggtt balloon functions to make the node clear + - drm/xe: Make xe_ggtt_node struct independent + - drm/xe: Fix missing runtime outer protection for ggtt_remove_node + - drm/xe: Move ggtt_fini to devm managed + - drm/xe: Set firmware state to loadable before registering guc_fini_hw + - drm/xe: Drop warn on xe_guc_pc_gucrc_disable in guc pc fini + - drm/xe: Move hw_engine_fini to devm managed + - drm/xe: Update xe_sa to use xe_managed_bo_create_pin_map + - drm/xe: Suspend/resume user access only during system s/r + - drm/xe: Handle polling only for system s/r in xe_display_pm_suspend/resume() + - drm/xe/display: handle HPD polling in display runtime suspend/resume + - drm/xe: Fix total initialization in xe_ggtt_print_holes() + + * Missing device ID for amd_atl for AMD platforms Kraken and Strix-Halo + (LP: #2077922) + - x86/amd_nb: Add new PCI IDs for AMD family 1Ah model 60h + - x86/amd_nb: Add new PCI IDs for AMD family 1Ah model 60h-70h + + * generate and ship vmlinux.h to allow packages to build BPF CO-RE + (LP: #2050083) + - [Packaging] add linux-bpf-dev package + - [Packaging] do not attempt to generate BTF header on armhf + + * Fix ethernet performance on JSL and EHL (LP: #2077858) + - intel_idle: Disable promotion to C1E on Jasper Lake and Elkhart Lake + + * Regression: unable to reach low idle states on Tiger Lake (LP: #2072679) + - SAUCE: PCI: ASPM: Allow OS to configure ASPM where BIOS is incapable of + - SAUCE: PCI: vmd: Let OS control ASPM for devices under VMD domain + + * Random flickering with Intel i915 (Gen9 GPUs in 6th-8th gen CPUs) on Linux + 6.8 (LP: #2062951) + - SAUCE: iommu/intel: disable DMAR for SKL integrated gfx + + * Make linux-tools-common Provide linux-cpupower (LP: #1960841) + - [Packaging] Add linux-cpupower to linux-tools-common Provides + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor4.0.0: fix build error with !CONFIG_SECURITY + - [Config] updateconfigs following v6.11-rc6 rebase + - SAUCE: apparmor4.0.0: fix build after rebase to v6.11-rc6 + - [Packaging] perf: reenable libtraceevent + + -- Timo Aaltonen Wed, 04 Sep 2024 17:12:57 +0300 + +linux (6.11.0-5.5) oracular; urgency=medium + + * oracular/linux: 6.11.0-5.5 -proposed tracker (LP: #2077454) + + * GDS force mitigation re-enabled in 6.10 (and 6.11) causing crashes + (LP: #2077145) + - [Config] Force disable CONFIG_MITIGATION_GDS_FORCE again + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.11-rc5 rebase + + -- Timo Aaltonen Mon, 26 Aug 2024 17:11:19 +0300 + +linux (6.11.0-4.4) oracular; urgency=medium + + * oracular/linux: 6.11.0-4.4 -proposed tracker (LP: #2077394) + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + + * Miscellaneous Ubuntu changes + - [Config] Disable CONFIG_DRM_I915_REPLAY_GPU_HANGS_API + - [Packaging] carry ELF_PACKAGE_METADATA into relinking + - [Packaging] Rename to linux + + -- Timo Aaltonen Tue, 20 Aug 2024 12:07:08 +0300 + +linux (6.11.0-3.3) oracular; urgency=medium + + * dummy entry + + -- Timo Aaltonen Tue, 20 Aug 2024 10:30:29 +0300 + +linux-unstable (6.11.0-3.3) oracular; urgency=medium + + * oracular/linux-unstable: 6.11.0-3.3 -proposed tracker (LP: #2077292) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.08.12) + + * Disable PCI_DYNAMIC_OF_NODES in Ubuntu (LP: #2074376) + - [Config] Disable PCI_DYNAMIC_OF_NODES + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.11-rc3 rebase + + -- Timo Aaltonen Mon, 19 Aug 2024 11:49:32 +0300 + +linux-unstable (6.11.0-2.2) oracular; urgency=medium + + * oracular/linux-unstable: 6.11.0-2.2 -proposed tracker (LP: #2076564) + + * please help enable more EROFS compression algorithms (LP: #2074049) + - [Config] enable LZMA and ZSTD file compressions in EROFS + + * Enable CONFIG_EXFAT_FS in s390x too (LP: #2076428) + - [Config] Enable EXFAT_FS on s390x too + + * Miscellaneous Ubuntu changes + - [Packaging] Disable tools/perf on armhf (FTBFS) + - [Config] toolchain version update + + * Miscellaneous Ubuntu changes + - UBUNTU: Rebase on v6.11-rc3 + + -- Timo Aaltonen Mon, 12 Aug 2024 14:07:05 +0300 + +linux-unstable (6.11.0-1.1) oracular; urgency=medium + + * oracular/linux-unstable: 6.11.0-1.1 -proposed tracker (LP: #2076116) + + * Miscellaneous Ubuntu changes + - [packaging] move to v6.11 and rename to linux-unstable + - [Config] updateconfigs following v6.11-rc2 rebase + - SAUCE: hwmon: Fix aaeon driver for 6.11. + - debian.master/dkms-versions: temporarily remove all dkms + + -- Timo Aaltonen Mon, 05 Aug 2024 20:10:11 +0300 + +linux-unstable (6.11.0-0.0) oracular; urgency=medium + + * Dummy entry. + + -- Timo Aaltonen Wed, 31 Jul 2024 16:41:50 +0300 + +linux (6.10.0-18.18) oracular; urgency=medium + + * oracular/linux: 6.10.0-18.18 -proposed tracker (LP: #2073754) + + * net:fib_rule_tests.sh in ubuntu_kselftests_net fails on Noble (LP: #2066332) + - Revert "UBUNTU: SAUCE: selftests: net: fix "from" match test in + fib_rule_tests.sh" + + * Pull-request to address TPM bypass issue (LP: #2037688) + - [Config]: Configure TPM drivers as builtins for arm64 in annotations + + * kdump doesn't work with UEFI secure boot and kernel lockdown enabled on + ARM64 (LP: #2033007) + - [Config]: Enable CONFIG_KEXEC_IMAGE_VERIFY_SIG on arm64 + + * Miscellaneous Ubuntu changes + - SAUCE: s390/setup: Fix __pa/__va for modules under non-GPL licenses + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] debian.master/dkms-versions -- disable zfs for + s390x" + + -- Paolo Pisati Mon, 22 Jul 2024 13:43:47 +0200 + +linux (6.10.0-17.17) oracular; urgency=medium + + * oracular/linux: 6.10.0-17.17 -proposed tracker (LP: #2073091) + + * Miscellaneous Ubuntu changes + - rebase on v6.10 + + -- Paolo Pisati Mon, 15 Jul 2024 10:29:49 +0200 + +linux (6.10.0-16.16) oracular; urgency=medium + + * oracular/linux: 6.10.0-16.16 -proposed tracker (LP: #2072507) + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc7 + + -- Paolo Pisati Mon, 08 Jul 2024 17:52:01 +0200 + +linux (6.10.0-15.15) oracular; urgency=medium + + * oracular/linux: 6.10.0-15.15 -proposed tracker (LP: #2071915) + + * [UBUNTU 24.04] IOMMU DMA mode changed in kernel config causes massive + throughput degradation for PCI-related network workloads (LP: #2071471) + - [Config] Set IOMMU_DEFAULT_DMA_STRICT=n and IOMMU_DEFAULT_DMA_LAZY=yes for + s390x + + * Miscellaneous Ubuntu changes + - rename to linux + + -- Paolo Pisati Thu, 04 Jul 2024 12:12:06 +0200 + +linux-unstable (6.10.0-14.14) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-14.14 -proposed tracker (LP: #2071786) + + * zfs-dkms FTBFS on Linux 6.10/s390x (LP: #2071774) + - [Packaging] debian.master/dkms-versions -- disable zfs for s390x + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.06.11) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [42/92]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [42/92]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [43/92]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [44/92]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [45/92]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [46/92]: af_unix mediation + - SAUCE: apparmor4.0.0 [47/92]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [49/92]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [50/92]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [51/92]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [52/92]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [53/92]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [54/92]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [55/92]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [56/92]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [57/92]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [58/92]: prompt - fix caching + - SAUCE: apparmor4.0.0 [59/92]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [60/92]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [61/92]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [62/92]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [63/92]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [64/92]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [65/93] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [69/92]: add io_uring mediation + - SAUCE: apparmor4.0.0 [70/92]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [71/92]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [72/92]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [73/92]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [74/92]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [75/92]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [76/92]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [77/92]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [78/92]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [79/92]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [80/92]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [81/92]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [82/92]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [83/92]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [84/92]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [85/92]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [86/92]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [87/92]: fixup notify + - SAUCE: apparmor4.0.0 [88/92]: apparmor: add fine grained ipv4/ipv6 mediation + - SAUCE: apparmor4.0.0 [89/92]: apparmor: disable tailglob responses for now + - SAUCE: apparmor4.0.0 [90/92]: apparmor: Fix notify build warnings + - SAUCE: apparmor4.0.0 [91/92]: fix reserved mem for when we save ipv6 + addresses + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * linux-gcp 6.8.0-1005.5 (+ others) Noble kernel regression with new apparmor + profiles/features (LP: #2061851) + - SAUCE: apparmor4.0.0 [92/92]: fix address mapping for recvfrom + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [66/92]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [67/92]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [68/92]: userns - make it so special unconfined + profiles can mediate user namespaces + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor4.0.0 [1/92]: LSM: Infrastructure management of the sock + security + - SAUCE: apparmor4.0.0 [2/92]: LSM: Add the lsmblob data structure. + - SAUCE: apparmor4.0.0 [3/92]: LSM: Use lsmblob in security_audit_rule_match + - SAUCE: apparmor4.0.0 [4/92]: LSM: Call only one hook for audit rules + - SAUCE: apparmor4.0.0 [5/92]: LSM: Add lsmblob_to_secctx hook + - SAUCE: apparmor4.0.0 [6/92]: Audit: maintain an lsmblob in audit_context + - SAUCE: apparmor4.0.0 [7/92]: LSM: Use lsmblob in security_ipc_getsecid + - SAUCE: apparmor4.0.0 [8/92]: Audit: Update shutdown LSM data + - SAUCE: apparmor4.0.0 [9/92]: LSM: Use lsmblob in security_current_getsecid + - SAUCE: apparmor4.0.0 [10/92]: LSM: Use lsmblob in security_inode_getsecid + - SAUCE: apparmor4.0.0 [11/92]: Audit: use an lsmblob in audit_names + - SAUCE: apparmor4.0.0 [12/92]: LSM: Create new security_cred_getlsmblob LSM + hook + - SAUCE: apparmor4.0.0 [13/92]: Audit: Change context data from secid to + lsmblob + - SAUCE: apparmor4.0.0 [14/92]: Netlabel: Use lsmblob for audit data + - SAUCE: apparmor4.0.0 [15/92]: LSM: Ensure the correct LSM context releaser + - SAUCE: apparmor4.0.0 [16/92]: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [17/92]: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [18/92]: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [19/92]: LSM: lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [20/92]: LSM: security_lsmblob_to_secctx module + selection + - SAUCE: apparmor4.0.0 [21/92]: Audit: Create audit_stamp structure + - SAUCE: apparmor4.0.0 [22/92]: Audit: Allow multiple records in an + audit_buffer + - SAUCE: apparmor4.0.0 [23/92]: Audit: Add record for multiple task security + contexts + - SAUCE: apparmor4.0.0 [24/92]: audit: multiple subject lsm values for + netlabel + - SAUCE: apparmor4.0.0 [25/92]: Audit: Add record for multiple object contexts + - SAUCE: apparmor4.0.0 [26/92]: LSM: Remove unused lsmcontext_init() + - SAUCE: apparmor4.0.0 [27/92]: LSM: Improve logic in security_getprocattr + - SAUCE: apparmor4.0.0 [28/92]: LSM: secctx provider check on release + - SAUCE: apparmor4.0.0 [29/92]: LSM: Single calls in socket_getpeersec hooks + - SAUCE: apparmor4.0.0 [30/92]: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [31/92]: LSM: Identify which LSM handles the context + string + - SAUCE: apparmor4.0.0 [32/92]: AppArmor: Remove the exclusive flag + - SAUCE: apparmor4.0.0 [33/92]: LSM: Add mount opts blob size tracking + - SAUCE: apparmor4.0.0 [34/92]: LSM: allocate mnt_opts blobs instead of module + specific data + - SAUCE: apparmor4.0.0 [35/92]: LSM: Infrastructure management of the key + security blob + - SAUCE: apparmor4.0.0 [36/92]: LSM: Infrastructure management of the mnt_opts + security blob + - SAUCE: apparmor4.0.0 [37/92]: LSM: Remove lsmblob scaffolding + - SAUCE: apparmor4.0.0 [38/92]: LSM: Allow reservation of netlabel + - SAUCE: apparmor4.0.0 [39/92]: LSM: Correct handling of ENOSYS in + inode_setxattr + - SAUCE: apparmor4.0.0 [40/92]: LSM: restrict security_cred_getsecid() to a + single LSM + - SAUCE: apparmor4.0.0 [41/92]: Smack: Remove LSM_FLAG_EXCLUSIVE + + * Miscellaneous upstream changes + - fixup inode_set_attr + + -- Paolo Pisati Wed, 03 Jul 2024 11:23:40 +0200 + +linux-unstable (6.10.0-13.13) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-13.13 -proposed tracker (LP: #2071598) + + * Miscellaneous Ubuntu changes + - zfs FTBFS on s390x - temporarily disable it + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc6 + + -- Paolo Pisati Mon, 01 Jul 2024 11:57:44 +0200 + +linux-unstable (6.10.0-12.12) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-12.12 -proposed tracker (LP: #2071461) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.06.11) + + * noble:linux: ADT ubuntu-regression-suite misses fakeroot dependency + (LP: #2070042) + - [DEP-8] Add missing fakeroot dependency + + * Add Real-time Linux Analysis tool (rtla) to linux-tools (LP: #2059080) + - [Packaging] add Real-time Linux Analysis tool (rtla) to linux-tools + - [Packaging] update dependencies for rtla + + * failed to enable IPU6 camera sensor on kernel >= 6.8: ivsc_ace + intel_vsc-5db76cf6-0a68-4ed6-9b78-0361635e2447: switch camera to host + failed: -110 (LP: #2067364) + - SAUCE: media: ivsc: csi: don't count privacy on as error + - SAUCE: media: ivsc: csi: add separate lock for v4l2 control handler + - SAUCE: media: ivsc: csi: remove privacy status in struct mei_csi + - SAUCE: mei: vsc: Enhance IVSC chipset stability during warm reboot + - SAUCE: mei: vsc: Enhance SPI transfer of IVSC rom + - SAUCE: mei: vsc: Utilize the appropriate byte order swap function + - SAUCE: mei: vsc: Prevent timeout error with added delay post-firmware + download + + * Miscellaneous Ubuntu changes + - SAUCE: nvme-tcp: Do not terminate commands when in RESETTING + - SAUCE: nvme-tcp: make 'err_work' a delayed work + - SAUCE: nvme-tcp: delay error recovery until the next KATO interval + - SAUCE: nvme-tcp: add recovery_delay to sysfs + - [Packaging] rtla: workaround the empty LD variable + - [Packaging] Check do_lib_rust before linking Rust lib files + - [Config] toolchain version update + + -- Paolo Pisati Fri, 28 Jun 2024 15:37:27 +0200 + +linux-unstable (6.10.0-11.11) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-11.11 -proposed tracker (LP: #2070368) + + * Provide python perf module (LP: #2051560) + - [Packaging] enable perf python module + - [Packaging] provide a wrapper module for python-perf + + * Miscellaneous Ubuntu changes + - [Config] toolchain version update + - [Packaging] Fix python3-setuptools build-dep for tools/perf + + -- Paolo Pisati Tue, 25 Jun 2024 14:53:52 +0200 + +linux-unstable (6.10.0-10.10) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-10.10 -proposed tracker (LP: #2070030) + + * Miscellaneous Ubuntu changes + - [Config] arm64: disable RELR + - [Config] updateconfigs following v6.10-rc5 rebase + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc5 + + -- Paolo Pisati Mon, 24 Jun 2024 10:57:14 +0200 + +linux-unstable (6.10.0-7.7) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-7.7 -proposed tracker (LP: #2069713) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.06.11) + + * Miscellaneous Ubuntu changes + - SAUCE: Revert "mm: remove follow_pfn" + - [Packaging] debian.master/dkms-versions -- remove zfs-linux + + -- Paolo Pisati Tue, 18 Jun 2024 12:13:02 +0200 + +linux-unstable (6.10.0-6.6) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-6.6 -proposed tracker (LP: #2069590) + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc4 + - [Config] updateconfigs following v6.10-rc4 rebase + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc4 + + -- Paolo Pisati Mon, 17 Jun 2024 11:02:49 +0200 + +linux-unstable (6.10.0-5.5) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-5.5 -proposed tracker (LP: #2069031) + + * Miscellaneous Ubuntu changes + - [packaging] remove the kernel configuration for perf + - [Packaging] dkms-build: Support DEB822 sources + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc3 + + -- Paolo Pisati Tue, 11 Jun 2024 12:42:10 +0200 + +linux-unstable (6.10.0-4.4) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-4.4 -proposed tracker (LP: #2067887) + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc2 + + -- Paolo Pisati Mon, 03 Jun 2024 11:52:09 +0200 + +linux-unstable (6.10.0-3.3) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-3.3 -proposed tracker (LP: #2067718) + + * Miscellaneous Ubuntu changes + - SAUCE: [packaging] `make scripts_gdb` target is broken upstream, to avoid a + FTBFS, do not try to install GDB_SCRIPTS + + -- Paolo Pisati Fri, 31 May 2024 13:17:14 +0200 + +linux-unstable (6.10.0-2.2) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-2.2 -proposed tracker (LP: #2067473) + + * Miscellaneous Ubuntu changes + - SAUCE: update hv_fcopy_daemon target to hv_fcopy_uio_daemon (following + upstream rename) + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] update dependencies for rtla" + - Revert "UBUNTU: [Packaging] add Real-time Linux Analysis tool (rtla) to + linux-tools" + - Revert "UBUNTU: [Packaging] provide a wrapper module for python-perf" + - Revert "UBUNTU: [Packaging] enable perf python module" + + -- Paolo Pisati Wed, 29 May 2024 14:08:53 +0200 + +linux-unstable (6.10.0-1.1) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-1.1 -proposed tracker (LP: #2067390) + + * Miscellaneous Ubuntu changes + - [packaging] move to v6.10 and rename to linux-unstable + - [Config] updateconfigs following v6.10-rc1 rebase + - SAUCE: (lockdown) security: use default hook return value + - debian.master/dkms-versions: temporarily remove all dkms + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc1 + + -- Paolo Pisati Tue, 28 May 2024 17:57:38 +0200 + +linux-unstable (6.10.0-0.0) oracular; urgency=medium + + * noble/linux: 6.8.0-34.34 -proposed tracker (LP: #2065167) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/2024.04.29) + + -- Roxana Nicolescu Wed, 08 May 2024 13:14:41 +0200 + +linux (6.8.0-32.32) noble; urgency=medium + + * noble/linux: 6.8.0-32.32 -proposed tracker (LP: #2064344) + + * Packaging resync (LP: #1786013) + - [Packaging] drop getabis data + - [Packaging] update variants + - [Packaging] update annotations scripts + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/2024.04.29) + + * Enable Nezha board (LP: #1975592) + - [Config] Enable CONFIG_REGULATOR_FIXED_VOLTAGE on riscv64 + + * Enable Nezha board (LP: #1975592) // Enable StarFive VisionFive 2 board + (LP: #2013232) + - [Config] Enable CONFIG_SERIAL_8250_DW on riscv64 + + * RISC-V kernel config is out of sync with other archs (LP: #1981437) + - [Config] Sync riscv64 config with other architectures + + * obsolete out-of-tree ivsc dkms in favor of in-tree one (LP: #2061747) + - ACPI: scan: Defer enumeration of devices with a _DEP pointing to IVSC device + - Revert "mei: vsc: Call wake_up() in the threaded IRQ handler" + - mei: vsc: Unregister interrupt handler for system suspend + - media: ipu-bridge: Add ov01a10 in Dell XPS 9315 + - SAUCE: media: ipu-bridge: Support more sensors + + * Fix after-suspend-mediacard/sdhc-insert test failed (LP: #2042500) + - PCI/ASPM: Move pci_configure_ltr() to aspm.c + - PCI/ASPM: Always build aspm.c + - PCI/ASPM: Move pci_save_ltr_state() to aspm.c + - PCI/ASPM: Save L1 PM Substates Capability for suspend/resume + - PCI/ASPM: Call pci_save_ltr_state() from pci_save_pcie_state() + - PCI/ASPM: Disable L1 before configuring L1 Substates + - PCI/ASPM: Update save_state when configuration changes + + * RTL8852BE fw security fail then lost WIFI function during suspend/resume + cycle (LP: #2063096) + - wifi: rtw89: download firmware with five times retry + + * intel_rapl_common: Add support for ARL and LNL (LP: #2061953) + - powercap: intel_rapl: Add support for Lunar Lake-M paltform + - powercap: intel_rapl: Add support for Arrow Lake + + * Kernel panic during checkbox stress_ng_test on Grace running noble 6.8 + (arm64+largemem) kernel (LP: #2058557) + - aio: Fix null ptr deref in aio_complete() wakeup + + * Avoid creating non-working backlight sysfs knob from ASUS board + (LP: #2060422) + - platform/x86: asus-wmi: Consider device is absent when the read is ~0 + + * Include cifs.ko in linux-modules package (LP: #2042546) + - [Packaging] Replace fs/cifs with fs/smb/client in inclusion list + + * Add Real-time Linux Analysis tool (rtla) to linux-tools (LP: #2059080) + - SAUCE: rtla: fix deb build + - [Packaging] add Real-time Linux Analysis tool (rtla) to linux-tools + - [Packaging] update dependencies for rtla + + * Noble update: v6.8.4 upstream stable release (LP: #2060533) + - Revert "workqueue: Shorten events_freezable_power_efficient name" + - Revert "workqueue: Don't call cpumask_test_cpu() with -1 CPU in + wq_update_node_max_active()" + - Revert "workqueue: Implement system-wide nr_active enforcement for unbound + workqueues" + - Revert "workqueue: Introduce struct wq_node_nr_active" + - Revert "workqueue: RCU protect wq->dfl_pwq and implement accessors for it" + - Revert "workqueue: Make wq_adjust_max_active() round-robin pwqs while + activating" + - Revert "workqueue: Move nr_active handling into helpers" + - Revert "workqueue: Replace pwq_activate_inactive_work() with + [__]pwq_activate_work()" + - Revert "workqueue: Factor out pwq_is_empty()" + - Revert "workqueue: Move pwq->max_active to wq->max_active" + - Revert "workqueue.c: Increase workqueue name length" + - Linux 6.8.4 + + * Noble update: v6.8.3 upstream stable release (LP: #2060531) + - drm/vmwgfx: Unmap the surface before resetting it on a plane state + - wifi: brcmfmac: Fix use-after-free bug in brcmf_cfg80211_detach + - wifi: brcmfmac: avoid invalid list operation when vendor attach fails + - media: staging: ipu3-imgu: Set fields before media_entity_pads_init() + - arm64: dts: qcom: sc7280: Add additional MSI interrupts + - remoteproc: virtio: Fix wdg cannot recovery remote processor + - clk: qcom: gcc-sdm845: Add soft dependency on rpmhpd + - smack: Set SMACK64TRANSMUTE only for dirs in smack_inode_setxattr() + - smack: Handle SMACK64TRANSMUTE in smack_inode_setsecurity() + - arm: dts: marvell: Fix maxium->maxim typo in brownstone dts + - drm/vmwgfx: Fix possible null pointer derefence with invalid contexts + - arm64: dts: qcom: sm8450-hdk: correct AMIC4 and AMIC5 microphones + - serial: max310x: fix NULL pointer dereference in I2C instantiation + - drm/vmwgfx: Fix the lifetime of the bo cursor memory + - pci_iounmap(): Fix MMIO mapping leak + - media: xc4000: Fix atomicity violation in xc4000_get_frequency + - media: mc: Add local pad to pipeline regardless of the link state + - media: mc: Fix flags handling when creating pad links + - media: nxp: imx8-isi: Check whether crossbar pad is non-NULL before access + - media: mc: Add num_links flag to media_pad + - media: mc: Rename pad variable to clarify intent + - media: mc: Expand MUST_CONNECT flag to always require an enabled link + - media: nxp: imx8-isi: Mark all crossbar sink pads as MUST_CONNECT + - md: use RCU lock to protect traversal in md_spares_need_change() + - KVM: Always flush async #PF workqueue when vCPU is being destroyed + - arm64: dts: qcom: sm8550-qrd: correct WCD9385 TX port mapping + - arm64: dts: qcom: sm8550-mtp: correct WCD9385 TX port mapping + - cpufreq: amd-pstate: Fix min_perf assignment in amd_pstate_adjust_perf() + - thermal/intel: Fix intel_tcc_get_temp() to support negative CPU temperature + - powercap: intel_rapl: Fix a NULL pointer dereference + - powercap: intel_rapl: Fix locking in TPMI RAPL + - powercap: intel_rapl_tpmi: Fix a register bug + - powercap: intel_rapl_tpmi: Fix System Domain probing + - powerpc/smp: Adjust nr_cpu_ids to cover all threads of a core + - powerpc/smp: Increase nr_cpu_ids to include the boot CPU + - sparc64: NMI watchdog: fix return value of __setup handler + - sparc: vDSO: fix return value of __setup handler + - selftests/mqueue: Set timeout to 180 seconds + - pinctrl: qcom: sm8650-lpass-lpi: correct Kconfig name + - ext4: correct best extent lstart adjustment logic + - drm/amdgpu/display: Address kdoc for 'is_psr_su' in 'fill_dc_dirty_rects' + - block: Clear zone limits for a non-zoned stacked queue + - kasan/test: avoid gcc warning for intentional overflow + - bounds: support non-power-of-two CONFIG_NR_CPUS + - fat: fix uninitialized field in nostale filehandles + - fuse: fix VM_MAYSHARE and direct_io_allow_mmap + - mfd: twl: Select MFD_CORE + - ubifs: Set page uptodate in the correct place + - ubi: Check for too small LEB size in VTBL code + - ubi: correct the calculation of fastmap size + - ubifs: ubifs_symlink: Fix memleak of inode->i_link in error path + - mtd: rawnand: meson: fix scrambling mode value in command macro + - md/md-bitmap: fix incorrect usage for sb_index + - x86/nmi: Fix the inverse "in NMI handler" check + - parisc/unaligned: Rewrite 64-bit inline assembly of emulate_ldd() + - parisc: Avoid clobbering the C/B bits in the PSW with tophys and tovirt + macros + - parisc: Fix ip_fast_csum + - parisc: Fix csum_ipv6_magic on 32-bit systems + - parisc: Fix csum_ipv6_magic on 64-bit systems + - parisc: Strip upper 32 bit of sum in csum_ipv6_magic for 64-bit builds + - md/raid5: fix atomicity violation in raid5_cache_count + - iio: adc: rockchip_saradc: fix bitmask for channels on SARADCv2 + - iio: adc: rockchip_saradc: use mask for write_enable bitfield + - docs: Restore "smart quotes" for quotes + - cpufreq: Limit resolving a frequency to policy min/max + - PM: suspend: Set mem_sleep_current during kernel command line setup + - vfio/pds: Always clear the save/restore FDs on reset + - clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays + - clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays + - clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays + - clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays + - clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays + - clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays + - clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays + - usb: xhci: Add error handling in xhci_map_urb_for_dma + - powerpc/fsl: Fix mfpmr build errors with newer binutils + - USB: serial: ftdi_sio: add support for GMC Z216C Adapter IR-USB + - USB: serial: add device ID for VeriFone adapter + - USB: serial: cp210x: add ID for MGP Instruments PDS100 + - wifi: mac80211: track capability/opmode NSS separately + - USB: serial: option: add MeiG Smart SLM320 product + - KVM: x86/xen: inject vCPU upcall vector when local APIC is enabled + - USB: serial: cp210x: add pid/vid for TDK NC0110013M and MM0110113M + - PM: sleep: wakeirq: fix wake irq warning in system suspend + - mmc: tmio: avoid concurrent runs of mmc_request_done() + - fuse: replace remaining make_bad_inode() with fuse_make_bad() + - fuse: fix root lookup with nonzero generation + - fuse: don't unhash root + - usb: typec: ucsi: Clean up UCSI_CABLE_PROP macros + - usb: dwc3-am62: fix module unload/reload behavior + - usb: dwc3-am62: Disable wakeup at remove + - serial: core: only stop transmit when HW fifo is empty + - serial: Lock console when calling into driver before registration + - btrfs: qgroup: always free reserved space for extent records + - btrfs: fix off-by-one chunk length calculation at contains_pending_extent() + - wifi: rtw88: Add missing VID/PIDs for 8811CU and 8821CU + - docs: Makefile: Add dependency to $(YNL_INDEX) for targets other than + htmldocs + - PCI/PM: Drain runtime-idle callbacks before driver removal + - PCI/DPC: Quirk PIO log size for Intel Raptor Lake Root Ports + - Revert "Revert "md/raid5: Wait for MD_SB_CHANGE_PENDING in raid5d"" + - md: don't clear MD_RECOVERY_FROZEN for new dm-raid until resume + - md: export helpers to stop sync_thread + - md: export helper md_is_rdwr() + - md: add a new helper reshape_interrupted() + - dm-raid: really frozen sync_thread during suspend + - md/dm-raid: don't call md_reap_sync_thread() directly + - dm-raid: add a new helper prepare_suspend() in md_personality + - dm-raid456, md/raid456: fix a deadlock for dm-raid456 while io concurrent + with reshape + - dm-raid: fix lockdep waring in "pers->hot_add_disk" + - powerpc: xor_vmx: Add '-mhard-float' to CFLAGS + - mac802154: fix llsec key resources release in mac802154_llsec_key_del + - mm: swap: fix race between free_swap_and_cache() and swapoff() + - mmc: core: Fix switch on gp3 partition + - Bluetooth: btnxpuart: Fix btnxpuart_close + - leds: trigger: netdev: Fix kernel panic on interface rename trig notify + - drm/etnaviv: Restore some id values + - landlock: Warn once if a Landlock action is requested while disabled + - io_uring: fix mshot read defer taskrun cqe posting + - hwmon: (amc6821) add of_match table + - io_uring: fix io_queue_proc modifying req->flags + - ext4: fix corruption during on-line resize + - nvmem: meson-efuse: fix function pointer type mismatch + - slimbus: core: Remove usage of the deprecated ida_simple_xx() API + - phy: tegra: xusb: Add API to retrieve the port number of phy + - usb: gadget: tegra-xudc: Fix USB3 PHY retrieval logic + - speakup: Fix 8bit characters from direct synth + - debugfs: fix wait/cancellation handling during remove + - PCI/AER: Block runtime suspend when handling errors + - io_uring/net: correctly handle multishot recvmsg retry setup + - io_uring: fix mshot io-wq checks + - PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p + - sparc32: Fix parport build with sparc32 + - nfs: fix UAF in direct writes + - NFS: Read unlock folio on nfs_page_create_from_folio() error + - kbuild: Move -Wenum-{compare-conditional,enum-conversion} into W=1 + - PCI: qcom: Enable BDF to SID translation properly + - PCI: dwc: endpoint: Fix advertised resizable BAR size + - PCI: hv: Fix ring buffer size calculation + - cifs: prevent updating file size from server if we have a read/write lease + - cifs: allow changing password during remount + - thermal/drivers/mediatek: Fix control buffer enablement on MT7896 + - vfio/pci: Disable auto-enable of exclusive INTx IRQ + - vfio/pci: Lock external INTx masking ops + - vfio/platform: Disable virqfds on cleanup + - vfio/platform: Create persistent IRQ handlers + - vfio/fsl-mc: Block calling interrupt handler without trigger + - tpm,tpm_tis: Avoid warning splat at shutdown + - ksmbd: replace generic_fillattr with vfs_getattr + - ksmbd: retrieve number of blocks using vfs_getattr in + set_file_allocation_info + - platform/x86/intel/tpmi: Change vsec offset to u64 + - io_uring/rw: return IOU_ISSUE_SKIP_COMPLETE for multishot retry + - io_uring: clean rings on NO_MMAP alloc fail + - ring-buffer: Do not set shortest_full when full target is hit + - ring-buffer: Fix full_waiters_pending in poll + - ring-buffer: Use wait_event_interruptible() in ring_buffer_wait() + - tracing/ring-buffer: Fix wait_on_pipe() race + - dlm: fix user space lkb refcounting + - soc: fsl: qbman: Always disable interrupts when taking cgr_lock + - soc: fsl: qbman: Use raw spinlock for cgr_lock + - s390/zcrypt: fix reference counting on zcrypt card objects + - drm/probe-helper: warn about negative .get_modes() + - drm/panel: do not return negative error codes from drm_panel_get_modes() + - drm/exynos: do not return negative values from .get_modes() + - drm/imx/ipuv3: do not return negative values from .get_modes() + - drm/vc4: hdmi: do not return negative values from .get_modes() + - clocksource/drivers/timer-riscv: Clear timer interrupt on timer + initialization + - memtest: use {READ,WRITE}_ONCE in memory scanning + - Revert "block/mq-deadline: use correct way to throttling write requests" + - lsm: use 32-bit compatible data types in LSM syscalls + - lsm: handle the NULL buffer case in lsm_fill_user_ctx() + - f2fs: mark inode dirty for FI_ATOMIC_COMMITTED flag + - f2fs: truncate page cache before clearing flags when aborting atomic write + - nilfs2: fix failure to detect DAT corruption in btree and direct mappings + - nilfs2: prevent kernel bug at submit_bh_wbc() + - cifs: make sure server interfaces are requested only for SMB3+ + - cifs: reduce warning log level for server not advertising interfaces + - cifs: open_cached_dir(): add FILE_READ_EA to desired access + - mtd: rawnand: Fix and simplify again the continuous read derivations + - mtd: rawnand: Add a helper for calculating a page index + - mtd: rawnand: Ensure all continuous terms are always in sync + - mtd: rawnand: Constrain even more when continuous reads are enabled + - cpufreq: dt: always allocate zeroed cpumask + - io_uring/futex: always remove futex entry for cancel all + - io_uring/waitid: always remove waitid entry for cancel all + - x86/CPU/AMD: Update the Zenbleed microcode revisions + - ksmbd: fix slab-out-of-bounds in smb_strndup_from_utf16() + - net: esp: fix bad handling of pages from page_pool + - NFSD: Fix nfsd_clid_class use of __string_len() macro + - drm/i915: Add missing ; to __assign_str() macros in tracepoint code + - net: hns3: tracing: fix hclgevf trace event strings + - cxl/trace: Properly initialize cxl_poison region name + - ksmbd: fix potencial out-of-bounds when buffer offset is invalid + - virtio: reenable config if freezing device failed + - LoongArch: Change __my_cpu_offset definition to avoid mis-optimization + - LoongArch: Define the __io_aw() hook as mmiowb() + - LoongArch/crypto: Clean up useless assignment operations + - wireguard: netlink: check for dangling peer via is_dead instead of empty + list + - wireguard: netlink: access device through ctx instead of peer + - wireguard: selftests: set RISCV_ISA_FALLBACK on riscv{32,64} + - ahci: asm1064: asm1166: don't limit reported ports + - drm/amd/display: Change default size for dummy plane in DML2 + - drm/amdgpu: amdgpu_ttm_gart_bind set gtt bound flag + - drm/amdgpu/pm: Fix NULL pointer dereference when get power limit + - drm/amdgpu/pm: Check the validity of overdiver power limit + - drm/amd/display: Override min required DCFCLK in dml1_validate + - drm/amd/display: Allow dirty rects to be sent to dmub when abm is active + - drm/amd/display: Init DPPCLK from SMU on dcn32 + - drm/amd/display: Update odm when ODM combine is changed on an otg master + pipe with no plane + - drm/amd/display: Fix idle check for shared firmware state + - drm/amd/display: Amend coasting vtotal for replay low hz + - drm/amd/display: Lock all enabled otg pipes even with no planes + - drm/amd/display: Implement wait_for_odm_update_pending_complete + - drm/amd/display: Return the correct HDCP error code + - drm/amd/display: Add a dc_state NULL check in dc_state_release + - drm/amd/display: Fix noise issue on HDMI AV mute + - dm snapshot: fix lockup in dm_exception_table_exit + - x86/pm: Work around false positive kmemleak report in msr_build_context() + - wifi: brcmfmac: add per-vendor feature detection callback + - wifi: brcmfmac: cfg80211: Use WSEC to set SAE password + - wifi: brcmfmac: Demote vendor-specific attach/detach messages to info + - drm/ttm: Make sure the mapped tt pages are decrypted when needed + - drm/amd/display: Unify optimize_required flags and VRR adjustments + - drm/amd/display: Add more checks for exiting idle in DC + - btrfs: add set_folio_extent_mapped() helper + - btrfs: replace sb::s_blocksize by fs_info::sectorsize + - btrfs: add helpers to get inode from page/folio pointers + - btrfs: add helpers to get fs_info from page/folio pointers + - btrfs: add helper to get fs_info from struct inode pointer + - btrfs: qgroup: validate btrfs_qgroup_inherit parameter + - vfio: Introduce interface to flush virqfd inject workqueue + - vfio/pci: Create persistent INTx handler + - drm/bridge: add ->edid_read hook and drm_bridge_edid_read() + - drm/bridge: lt8912b: use drm_bridge_edid_read() + - drm/bridge: lt8912b: clear the EDID property on failures + - drm/bridge: lt8912b: do not return negative values from .get_modes() + - drm/amd/display: Remove pixle rate limit for subvp + - drm/amd/display: Revert Remove pixle rate limit for subvp + - workqueue: Shorten events_freezable_power_efficient name + - drm/amd/display: Use freesync when `DRM_EDID_FEATURE_CONTINUOUS_FREQ` found + - netfilter: nf_tables: reject constant set with timeout + - Revert "crypto: pkcs7 - remove sha1 support" + - x86/efistub: Call mixed mode boot services on the firmware's stack + - ASoC: amd: yc: Revert "Fix non-functional mic on Lenovo 21J2" + - ASoC: amd: yc: Revert "add new YC platform variant (0x63) support" + - Fix memory leak in posix_clock_open() + - wifi: rtw88: 8821cu: Fix connection failure + - x86/Kconfig: Remove CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT + - x86/sev: Fix position dependent variable references in startup code + - clocksource/drivers/arm_global_timer: Fix maximum prescaler value + - ARM: 9352/1: iwmmxt: Remove support for PJ4/PJ4B cores + - ARM: 9359/1: flush: check if the folio is reserved for no-mapping addresses + - entry: Respect changes to system call number by trace_sys_enter() + - swiotlb: Fix double-allocation of slots due to broken alignment handling + - swiotlb: Honour dma_alloc_coherent() alignment in swiotlb_alloc() + - swiotlb: Fix alignment checks when both allocation and DMA masks are present + - iommu/dma: Force swiotlb_max_mapping_size on an untrusted device + - printk: Update @console_may_schedule in console_trylock_spinning() + - irqchip/renesas-rzg2l: Flush posted write in irq_eoi() + - irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi() + - irqchip/renesas-rzg2l: Rename rzg2l_irq_eoi() + - irqchip/renesas-rzg2l: Prevent spurious interrupts when setting trigger type + - kprobes/x86: Use copy_from_kernel_nofault() to read from unsafe address + - efi/libstub: fix efi_random_alloc() to allocate memory at alloc_min or + higher address + - x86/mpparse: Register APIC address only once + - x86/fpu: Keep xfd_state in sync with MSR_IA32_XFD + - efi: fix panic in kdump kernel + - pwm: img: fix pwm clock lookup + - selftests/mm: Fix build with _FORTIFY_SOURCE + - btrfs: handle errors returned from unpin_extent_cache() + - btrfs: fix warning messages not printing interval at unpin_extent_range() + - btrfs: do not skip re-registration for the mounted device + - mfd: intel-lpss: Switch to generalized quirk table + - mfd: intel-lpss: Introduce QUIRK_CLOCK_DIVIDER_UNITY for XPS 9530 + - drm/i915: Replace a memset() with zero initialization + - drm/i915: Try to preserve the current shared_dpll for fastset on type-c + ports + - drm/i915: Include the PLL name in the debug messages + - drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs + - crypto: iaa - Fix nr_cpus < nr_iaa case + - drm/amd/display: Prevent crash when disable stream + - ALSA: hda/tas2781: remove digital gain kcontrol + - ALSA: hda/tas2781: add locks to kcontrols + - mm: zswap: fix writeback shinker GFP_NOIO/GFP_NOFS recursion + - init: open /initrd.image with O_LARGEFILE + - x86/efistub: Add missing boot_params for mixed mode compat entry + - efi/libstub: Cast away type warning in use of max() + - x86/efistub: Reinstate soft limit for initrd loading + - prctl: generalize PR_SET_MDWE support check to be per-arch + - ARM: prctl: reject PR_SET_MDWE on pre-ARMv6 + - tmpfs: fix race on handling dquot rbtree + - btrfs: validate device maj:min during open + - btrfs: fix race in read_extent_buffer_pages() + - btrfs: zoned: don't skip block groups with 100% zone unusable + - btrfs: zoned: use zone aware sb location for scrub + - btrfs: zoned: fix use-after-free in do_zone_finish() + - wifi: mac80211: check/clear fast rx for non-4addr sta VLAN changes + - wifi: cfg80211: add a flag to disable wireless extensions + - wifi: iwlwifi: mvm: disable MLO for the time being + - wifi: iwlwifi: fw: don't always use FW dump trig + - wifi: iwlwifi: mvm: handle debugfs names more carefully + - Revert "drm/amd/display: Fix sending VSC (+ colorimetry) packets for DP/eDP + displays without PSR" + - fbdev: Select I/O-memory framebuffer ops for SBus + - exec: Fix NOMMU linux_binprm::exec in transfer_args_to_stack() + - hexagon: vmlinux.lds.S: handle attributes section + - mm: cachestat: fix two shmem bugs + - selftests/mm: sigbus-wp test requires UFFD_FEATURE_WP_HUGETLBFS_SHMEM + - selftests/mm: fix ARM related issue with fork after pthread_create + - mmc: sdhci-omap: re-tuning is needed after a pm transition to support emmc + HS200 mode + - mmc: core: Initialize mmc_blk_ioc_data + - mmc: core: Avoid negative index with array access + - sdhci-of-dwcmshc: disable PM runtime in dwcmshc_remove() + - block: Do not force full zone append completion in req_bio_endio() + - thermal: devfreq_cooling: Fix perf state when calculate dfc res_util + - Revert "thermal: core: Don't update trip points inside the hysteresis range" + - nouveau/dmem: handle kcalloc() allocation failure + - net: ll_temac: platform_get_resource replaced by wrong function + - net: wan: framer: Add missing static inline qualifiers + - net: phy: qcom: at803x: fix kernel panic with at8031_probe + - drm/xe/query: fix gt_id bounds check + - drm/dp: Fix divide-by-zero regression on DP MST unplug with nouveau + - drm/vmwgfx: Create debugfs ttm_resource_manager entry only if needed + - drm/amdkfd: fix TLB flush after unmap for GFX9.4.2 + - drm/amdgpu: fix deadlock while reading mqd from debugfs + - drm/amd/display: Remove MPC rate control logic from DCN30 and above + - drm/amd/display: Set DCN351 BB and IP the same as DCN35 + - drm/i915/hwmon: Fix locking inversion in sysfs getter + - drm/i915/vma: Fix UAF on destroy against retire race + - drm/i915/bios: Tolerate devdata==NULL in + intel_bios_encoder_supports_dp_dual_mode() + - drm/i915/vrr: Generate VRR "safe window" for DSB + - drm/i915/dsi: Go back to the previous INIT_OTP/DISPLAY_ON order, mostly + - drm/i915/dsb: Fix DSB vblank waits when using VRR + - drm/i915: Do not match JSL in ehl_combo_pll_div_frac_wa_needed() + - drm/i915: Pre-populate the cursor physical dma address + - drm/i915/gt: Reset queue_priority_hint on parking + - drm/amd/display: Fix bounds check for dcn35 DcfClocks + - Bluetooth: hci_sync: Fix not checking error on hci_cmd_sync_cancel_sync + - mtd: spinand: Add support for 5-byte IDs + - Revert "usb: phy: generic: Get the vbus supply" + - usb: cdc-wdm: close race between read and workqueue + - usb: misc: ljca: Fix double free in error handling path + - USB: UAS: return ENODEV when submit urbs fail with device not attached + - vfio/pds: Make sure migration file isn't accessed after reset + - ring-buffer: Make wake once of ring_buffer_wait() more robust + - btrfs: fix extent map leak in unexpected scenario at unpin_extent_cache() + - ALSA: sh: aica: reorder cleanup operations to avoid UAF bugs + - scsi: ufs: qcom: Provide default cycles_in_1us value + - scsi: sd: Fix TCG OPAL unlock on system resume + - scsi: core: Fix unremoved procfs host directory regression + - staging: vc04_services: changen strncpy() to strscpy_pad() + - staging: vc04_services: fix information leak in create_component() + - genirq: Introduce IRQF_COND_ONESHOT and use it in pinctrl-amd + - usb: dwc3: Properly set system wakeup + - USB: core: Fix deadlock in usb_deauthorize_interface() + - USB: core: Add hub_get() and hub_put() routines + - USB: core: Fix deadlock in port "disable" sysfs attribute + - usb: dwc2: host: Fix remote wakeup from hibernation + - usb: dwc2: host: Fix hibernation flow + - usb: dwc2: host: Fix ISOC flow in DDMA mode + - usb: dwc2: gadget: Fix exiting from clock gating + - usb: dwc2: gadget: LPM flow fix + - usb: udc: remove warning when queue disabled ep + - usb: typec: ucsi: Fix race between typec_switch and role_switch + - usb: typec: tcpm: fix double-free issue in tcpm_port_unregister_pd() + - usb: typec: tcpm: Correct port source pdo array in pd_set callback + - usb: typec: tcpm: Update PD of Type-C port upon pd_set + - usb: typec: Return size of buffer if pd_set operation succeeds + - usb: typec: ucsi: Clear EVENT_PENDING under PPM lock + - usb: typec: ucsi: Ack unsupported commands + - usb: typec: ucsi_acpi: Refactor and fix DELL quirk + - usb: typec: ucsi: Clear UCSI_CCI_RESET_COMPLETE before reset + - scsi: qla2xxx: Prevent command send on chip reset + - scsi: qla2xxx: Fix N2N stuck connection + - scsi: qla2xxx: Split FCE|EFT trace control + - scsi: qla2xxx: Update manufacturer detail + - scsi: qla2xxx: NVME|FCP prefer flag not being honored + - scsi: qla2xxx: Fix command flush on cable pull + - scsi: qla2xxx: Fix double free of the ha->vp_map pointer + - scsi: qla2xxx: Fix double free of fcport + - scsi: qla2xxx: Change debug message during driver unload + - scsi: qla2xxx: Delay I/O Abort on PCI error + - x86/bugs: Fix the SRSO mitigation on Zen3/4 + - crash: use macro to add crashk_res into iomem early for specific arch + - drm/amd/display: fix IPX enablement + - x86/bugs: Use fixed addressing for VERW operand + - Revert "x86/bugs: Use fixed addressing for VERW operand" + - usb: dwc3: pci: Drop duplicate ID + - scsi: lpfc: Correct size for cmdwqe/rspwqe for memset() + - scsi: lpfc: Correct size for wqe for memset() + - scsi: libsas: Add a helper sas_get_sas_addr_and_dev_type() + - scsi: libsas: Fix disk not being scanned in after being removed + - perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and + later + - x86/sev: Skip ROM range scans and validation for SEV-SNP guests + - tools/resolve_btfids: fix build with musl libc + - drm/amdgpu: fix use-after-free bug + - drm/sched: fix null-ptr-deref in init entity + - Linux 6.8.3 + - [Config] updateconfigs following v6.8.3 import + + * Noble update: v6.8.3 upstream stable release (LP: #2060531) // + [Ubuntu-24.04] Hugepage memory is not getting released even after destroying + the guest! (LP: #2062556) + - block: Fix page refcounts for unaligned buffers in __bio_release_pages() + + * [SPR][EMR][GNR] TDX: efi: TD Measurement support for kernel cmdline/initrd + sections from EFI stub (LP: #2060130) + - efi/libstub: Use TPM event typedefs from the TCG PC Client spec + - efi/tpm: Use symbolic GUID name from spec for final events table + - efi/libstub: Add Confidential Computing (CC) measurement typedefs + - efi/libstub: Measure into CC protocol if TCG2 protocol is absent + - efi/libstub: Add get_event_log() support for CC platforms + - x86/efistub: Remap kernel text read-only before dropping NX attribute + + * Fix acpi_power_meter accessing IPMI region before it's ready (LP: #2059263) + - ACPI: IPMI: Add helper to wait for when SMI is selected + - hwmon: (acpi_power_meter) Ensure IPMI space handler is ready on Dell systems + + * Drop fips-checks script from trees (LP: #2055083) + - [Packaging] Remove fips-checks script + + * alsa/realtek: adjust max output valume for headphone on 2 LG machines + (LP: #2058573) + - ALSA: hda/realtek: fix the hp playback volume issue for LG machines + + * Noble update: v6.8.2 upstream stable release (LP: #2060097) + - do_sys_name_to_handle(): use kzalloc() to fix kernel-infoleak + - workqueue.c: Increase workqueue name length + - workqueue: Move pwq->max_active to wq->max_active + - workqueue: Factor out pwq_is_empty() + - workqueue: Replace pwq_activate_inactive_work() with [__]pwq_activate_work() + - workqueue: Move nr_active handling into helpers + - workqueue: Make wq_adjust_max_active() round-robin pwqs while activating + - workqueue: RCU protect wq->dfl_pwq and implement accessors for it + - workqueue: Introduce struct wq_node_nr_active + - workqueue: Implement system-wide nr_active enforcement for unbound + workqueues + - workqueue: Don't call cpumask_test_cpu() with -1 CPU in + wq_update_node_max_active() + - iomap: clear the per-folio dirty bits on all writeback failures + - fs: Fix rw_hint validation + - io_uring: remove looping around handling traditional task_work + - io_uring: remove unconditional looping in local task_work handling + - s390/dasd: Use dev_*() for device log messages + - s390/dasd: fix double module refcount decrement + - fs/hfsplus: use better @opf description + - md: fix kmemleak of rdev->serial + - rcu/exp: Fix RCU expedited parallel grace period kworker allocation failure + recovery + - rcu/exp: Handle RCU expedited grace period kworker allocation failure + - fs/select: rework stack allocation hack for clang + - block: fix deadlock between bd_link_disk_holder and partition scan + - md: Don't clear MD_CLOSING when the raid is about to stop + - kunit: Setup DMA masks on the kunit device + - ovl: Always reject mounting over case-insensitive directories + - kunit: test: Log the correct filter string in executor_test + - lib/cmdline: Fix an invalid format specifier in an assertion msg + - lib: memcpy_kunit: Fix an invalid format specifier in an assertion msg + - time: test: Fix incorrect format specifier + - rtc: test: Fix invalid format specifier. + - net: test: Fix printf format specifier in skb_segment kunit test + - drm/xe/tests: Fix printf format specifiers in xe_migrate test + - drm: tests: Fix invalid printf format specifiers in KUnit tests + - md/raid1: factor out helpers to add rdev to conf + - md/raid1: record nonrot rdevs while adding/removing rdevs to conf + - md/raid1: fix choose next idle in read_balance() + - io_uring/net: unify how recvmsg and sendmsg copy in the msghdr + - io_uring/net: move receive multishot out of the generic msghdr path + - io_uring/net: fix overflow check in io_recvmsg_mshot_prep() + - nvme: host: fix double-free of struct nvme_id_ns in ns_update_nuse() + - aoe: fix the potential use-after-free problem in aoecmd_cfg_pkts + - x86/mm: Ensure input to pfn_to_kaddr() is treated as a 64-bit type + - x86/resctrl: Remove hard-coded memory bandwidth limit + - x86/resctrl: Read supported bandwidth sources from CPUID + - x86/resctrl: Implement new mba_MBps throttling heuristic + - x86/sme: Fix memory encryption setting if enabled by default and not + overridden + - timekeeping: Fix cross-timestamp interpolation on counter wrap + - timekeeping: Fix cross-timestamp interpolation corner case decision + - timekeeping: Fix cross-timestamp interpolation for non-x86 + - x86/asm: Remove the __iomem annotation of movdir64b()'s dst argument + - sched/fair: Take the scheduling domain into account in select_idle_smt() + - sched/fair: Take the scheduling domain into account in select_idle_core() + - wifi: ath10k: fix NULL pointer dereference in + ath10k_wmi_tlv_op_pull_mgmt_tx_compl_ev() + - wifi: b43: Stop/wake correct queue in DMA Tx path when QoS is disabled + - wifi: b43: Stop/wake correct queue in PIO Tx path when QoS is disabled + - wifi: b43: Stop correct queue in DMA worker when QoS is disabled + - wifi: b43: Disable QoS for bcm4331 + - wifi: wilc1000: fix declarations ordering + - wifi: wilc1000: fix RCU usage in connect path + - wifi: ath11k: add support to select 6 GHz regulatory type + - wifi: ath11k: store cur_regulatory_info for each radio + - wifi: ath11k: fix a possible dead lock caused by ab->base_lock + - wifi: rtl8xxxu: add cancel_work_sync() for c2hcmd_work + - wifi: wilc1000: do not realloc workqueue everytime an interface is added + - wifi: wilc1000: fix multi-vif management when deleting a vif + - wifi: mwifiex: debugfs: Drop unnecessary error check for + debugfs_create_dir() + - ARM: dts: renesas: r8a73a4: Fix external clocks and clock rate + - arm64: dts: qcom: x1e80100: drop qcom,drv-count + - arm64: dts: qcom: sc8180x: Hook up VDD_CX as GCC parent domain + - arm64: dts: qcom: sc8180x: Fix up big CPU idle state entry latency + - arm64: dts: qcom: sc8180x: Add missing CPU off state + - arm64: dts: qcom: sc8180x: Fix eDP PHY power-domains + - arm64: dts: qcom: sc8180x: Don't hold MDP core clock at FMAX + - arm64: dts: qcom: sc8180x: Require LOW_SVS vote for MMCX if DISPCC is on + - arm64: dts: qcom: sc8180x: Add missing CPU<->MDP_CFG path + - arm64: dts: qcom: sc8180x: Shrink aoss_qmp register space size + - cpufreq: brcmstb-avs-cpufreq: add check for cpufreq_cpu_get's return value + - cpufreq: mediatek-hw: Wait for CPU supplies before probing + - sock_diag: annotate data-races around sock_diag_handlers[family] + - inet_diag: annotate data-races around inet_diag_table[] + - bpftool: Silence build warning about calloc() + - selftests/bpf: Fix potential premature unload in bpf_testmod + - libbpf: Apply map_set_def_max_entries() for inner_maps on creation + - selftest/bpf: Add map_in_maps with BPF_MAP_TYPE_PERF_EVENT_ARRAY values + - bpftool: Fix wrong free call in do_show_link + - wifi: ath12k: Fix issues in channel list update + - selftests/bpf: Fix the flaky tc_redirect_dtime test + - selftests/bpf: Wait for the netstamp_needed_key static key to be turned on + - wifi: cfg80211: add RNR with reporting AP information + - wifi: mac80211: use deflink and fix typo in link ID check + - wifi: iwlwifi: change link id in time event to s8 + - af_unix: Annotate data-race of gc_in_progress in wait_for_unix_gc(). + - arm64: dts: qcom: sm8450: Add missing interconnects to serial + - soc: qcom: socinfo: rename PM2250 to PM4125 + - arm64: dts: qcom: sc7280: Add static properties to cryptobam + - arm64: dts: qcom: qcm6490-fairphone-fp5: Add missing reserved-memory + - arm64: dts: qcom: sdm845-oneplus-common: improve DAI node naming + - arm64: dts: qcom: rename PM2250 to PM4125 + - cpufreq: mediatek-hw: Don't error out if supply is not found + - libbpf: Fix faccessat() usage on Android + - libbpf: fix __arg_ctx type enforcement for perf_event programs + - pmdomain: qcom: rpmhpd: Drop SA8540P gfx.lvl + - arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc + - arm64: dts: renesas: r8a779g0: Restore sort order + - arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2 + - selftests/bpf: Disable IPv6 for lwt_redirect test + - arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on OSM-S i.MX8MM + - arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on SL/BL i.MX8MM + - arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL + OSM-S board + - arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL + board + - arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL + OSM-S board + - arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL + board + - arm64: dts: imx8mm-kontron: Fix interrupt for RTC on OSM-S i.MX8MM module + - arm64: dts: imx8qm: Align edma3 power-domains resources indentation + - arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers + - libbpf: Add missing LIBBPF_API annotation to libbpf_set_memlock_rlim API + - wifi: ath9k: delay all of ath9k_wmi_event_tasklet() until init is complete + - wifi: ath11k: change to move WMI_VDEV_PARAM_SET_HEMU_MODE before + WMI_PEER_ASSOC_CMDID + - wifi: ath12k: fix fetching MCBC flag for QCN9274 + - wifi: iwlwifi: mvm: report beacon protection failures + - wifi: iwlwifi: dbg-tlv: ensure NUL termination + - wifi: iwlwifi: acpi: fix WPFC reading + - wifi: iwlwifi: mvm: initialize rates in FW earlier + - wifi: iwlwifi: fix EWRD table validity check + - wifi: iwlwifi: mvm: d3: fix IPN byte order + - wifi: iwlwifi: always have 'uats_enabled' + - wifi: iwlwifi: mvm: fix the TLC command after ADD_STA + - wifi: iwlwifi: read BIOS PNVM only for non-Intel SKU + - gpio: vf610: allow disabling the vf610 driver + - selftests/bpf: trace_helpers.c: do not use poisoned type + - bpf: make sure scalar args don't accept __arg_nonnull tag + - bpf: don't emit warnings intended for global subprogs for static subprogs + - arm64: dts: imx8mm-venice-gw71xx: fix USB OTG VBUS + - pwm: atmel-hlcdc: Fix clock imbalance related to suspend support + - net: blackhole_dev: fix build warning for ethh set but not used + - spi: consolidate setting message->spi + - spi: move split xfers for CS_WORD emulation + - arm64: dts: ti: k3-am62p5-sk: Enable CPSW MDIO node + - arm64: dts: ti: k3-j721s2: Fix power domain for VTM node + - arm64: dts: ti: k3-j784s4: Fix power domain for VTM node + - wifi: ath11k: initialize rx_mcs_80 and rx_mcs_160 before use + - wifi: libertas: fix some memleaks in lbs_allocate_cmd_buffer() + - arm64: dts: ti: k3-am69-sk: remove assigned-clock-parents for unused VP + - libbpf: fix return value for PERF_EVENT __arg_ctx type fix up check + - arm64: dts: ti: k3-am62p-mcu/wakeup: Disable MCU and wakeup R5FSS nodes + - arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J + - libbpf: Use OPTS_SET() macro in bpf_xdp_query() + - wifi: wfx: fix memory leak when starting AP + - arm64: dts: qcom: qcm2290: declare VLS CLAMP register for USB3 PHY + - arm64: dts: qcom: sm6115: declare VLS CLAMP register for USB3 PHY + - arm64: dts: qcom: sm8650: Fix UFS PHY clocks + - wifi: ath12k: fix incorrect logic of calculating vdev_stats_id + - printk: nbcon: Relocate 32bit seq macros + - printk: ringbuffer: Do not skip non-finalized records with prb_next_seq() + - printk: Wait for all reserved records with pr_flush() + - printk: Add this_cpu_in_panic() + - printk: ringbuffer: Cleanup reader terminology + - printk: ringbuffer: Skip non-finalized records in panic + - printk: Disable passing console lock owner completely during panic() + - pwm: sti: Fix capture for st,pwm-num-chan < st,capture-num-chan + - tools/resolve_btfids: Refactor set sorting with types from btf_ids.h + - tools/resolve_btfids: Fix cross-compilation to non-host endianness + - wifi: iwlwifi: support EHT for WH + - wifi: iwlwifi: properly check if link is active + - wifi: iwlwifi: mvm: fix erroneous queue index mask + - wifi: iwlwifi: mvm: don't set the MFP flag for the GTK + - wifi: iwlwifi: mvm: don't set replay counters to 0xff + - s390/pai: fix attr_event_free upper limit for pai device drivers + - s390/vdso: drop '-fPIC' from LDFLAGS + - arm64: dts: qcom: qcm6490-idp: Correct the voltage setting for vph_pwr + - arm64: dts: qcom: qcs6490-rb3gen2: Correct the voltage setting for vph_pwr + - selftests: forwarding: Add missing config entries + - selftests: forwarding: Add missing multicast routing config entries + - arm64: dts: qcom: sm6115: drop pipe clock selection + - ipv6: mcast: remove one synchronize_net() barrier in ipv6_mc_down() + - arm64: dts: mt8183: Move CrosEC base detection node to kukui-based DTs + - arm64: dts: mediatek: mt7986: fix reference to PWM in fan node + - arm64: dts: mediatek: mt7986: drop crypto's unneeded/invalid clock name + - arm64: dts: mediatek: mt7986: fix SPI bus width properties + - arm64: dts: mediatek: mt7986: fix SPI nodename + - arm64: dts: mediatek: mt7986: drop "#clock-cells" from PWM + - arm64: dts: mediatek: mt7986: add "#reset-cells" to infracfg + - arm64: dts: mediatek: mt8192-asurada: Remove CrosEC base detection node + - arm64: dts: mediatek: mt8192: fix vencoder clock name + - arm64: dts: mediatek: mt8186: fix VENC power domain clocks + - arm64: dts: mediatek: mt7622: add missing "device_type" to memory nodes + - can: m_can: Start/Cancel polling timer together with interrupts + - wifi: iwlwifi: mvm: Fix the listener MAC filter flags + - bpf: Mark bpf_spin_{lock,unlock}() helpers with notrace correctly + - arm64: dts: qcom: sdm845: Use the Low Power Island CX/MX for SLPI + - soc: qcom: llcc: Check return value on Broadcast_OR reg read + - ARM: dts: qcom: msm8974: correct qfprom node size + - arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domains + - arm64: dts: mediatek: mt8186: Add missing xhci clock to usb controllers + - arm64: dts: ti: am65x: Fix dtbs_install for Rocktech OLDI overlay + - cpufreq: qcom-hw: add CONFIG_COMMON_CLK dependency + - wifi: wilc1000: prevent use-after-free on vif when cleaning up all + interfaces + - pwm: dwc: use pm_sleep_ptr() macro + - arm64: dts: ti: k3-am69-sk: fix PMIC interrupt number + - arm64: dts: ti: k3-j721e-sk: fix PMIC interrupt number + - arm64: dts: ti: k3-am62-main: disable usb lpm + - ACPI: processor_idle: Fix memory leak in acpi_processor_power_exit() + - bus: tegra-aconnect: Update dependency to ARCH_TEGRA + - iommu/amd: Mark interrupt as managed + - wifi: brcmsmac: avoid function pointer casts + - arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios + - arm64: dts: qcom: sm8150: correct PCIe wake-gpios + - powercap: dtpm_cpu: Fix error check against freq_qos_add_request() + - net: ena: Remove ena_select_queue + - arm64: dts: ti: k3-j7200-common-proc-board: Modify Pinmux for wkup_uart0 and + mcu_uart0 + - arm64: dts: ti: k3-j7200-common-proc-board: Remove clock-frequency from + mcu_uart0 + - arm64: dts: ti: k3-j721s2-common-proc-board: Remove Pinmux for CTS and RTS + in wkup_uart0 + - arm64: dts: ti: k3-j784s4-evm: Remove Pinmux for CTS and RTS in wkup_uart0 + - arm64: dts: ti: k3-am64-main: Fix ITAP/OTAP values for MMC + - arm64: dts: mt8195-cherry-tomato: change watchdog reset boot flow + - arm64: dts: ti: Add common1 register space for AM65x SoC + - arm64: dts: ti: Add common1 register space for AM62x SoC + - firmware: arm_scmi: Fix double free in SMC transport cleanup path + - wifi: cfg80211: set correct param change count in ML element + - arm64: dts: ti: k3-j721e: Fix mux-reg-masks in hbmc_mux + - arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl + - arm64: dts: ti: k3-am62p: Fix memory ranges for DMSS + - wifi: wilc1000: revert reset line logic flip + - ARM: dts: arm: realview: Fix development chip ROM compatible value + - memory: tegra: Correct DLA client names + - wifi: mt76: mt7996: fix fw loading timeout + - wifi: mt76: mt7925: fix connect to 80211b mode fail in 2Ghz band + - wifi: mt76: mt7925: fix SAP no beacon issue in 5Ghz and 6Ghz band + - wifi: mt76: mt7925: fix mcu query command fail + - wifi: mt76: mt7925: fix wmm queue mapping + - wifi: mt76: mt7925: fix fw download fail + - wifi: mt76: mt7925: fix WoW failed in encrypted mode + - wifi: mt76: mt7925: fix the wrong header translation config + - wifi: mt76: mt7925: add flow to avoid chip bt function fail + - wifi: mt76: mt7925: add support to set ifs time by mcu command + - wifi: mt76: mt7925: update PCIe DMA settings + - wifi: mt76: mt7996: check txs format before getting skb by pid + - wifi: mt76: mt7996: fix TWT issues + - wifi: mt76: mt7996: fix incorrect interpretation of EHT MCS caps + - wifi: mt76: mt7996: fix HE beamformer phy cap for station vif + - wifi: mt76: mt7996: fix efuse reading issue + - wifi: mt76: mt7996: fix HIF_TXD_V2_1 value + - wifi: mt76: mt792x: fix ethtool warning + - wifi: mt76: mt7921e: fix use-after-free in free_irq() + - wifi: mt76: mt7925e: fix use-after-free in free_irq() + - wifi: mt76: mt7921: fix incorrect type conversion for CLC command + - wifi: mt76: mt792x: fix a potential loading failure of the 6Ghz channel + config from ACPI + - wifi: mt76: fix the issue of missing txpwr settings from ch153 to ch177 + - arm64: dts: renesas: rzg2l: Add missing interrupts to IRQC nodes + - arm64: dts: renesas: r9a08g045: Add missing interrupts to IRQC node + - arm64: dts: renesas: rzg3s-smarc-som: Guard Ethernet IRQ GPIO hogs + - arm64: dts: renesas: r8a779a0: Correct avb[01] reg sizes + - arm64: dts: renesas: r8a779g0: Correct avb[01] reg sizes + - net: mctp: copy skb ext data when fragmenting + - pstore: inode: Only d_invalidate() is needed + - arm64: dts: allwinner: h6: Add RX DMA channel for SPDIF + - ARM: dts: imx6dl-yapp4: Fix typo in the QCA switch register address + - ARM: dts: imx6dl-yapp4: Move the internal switch PHYs under the switch node + - arm64: dts: imx8mp: Set SPI NOR to max 40 MHz on Data Modul i.MX8M Plus eDM + SBC + - arm64: dts: imx8mp-evk: Fix hdmi@3d node + - regulator: userspace-consumer: add module device table + - gpiolib: Pass consumer device through to core in + devm_fwnode_gpiod_get_index() + - arm64: dts: marvell: reorder crypto interrupts on Armada SoCs + - ACPI: resource: Do IRQ override on Lunnen Ground laptops + - ACPI: resource: Add MAIBENBEN X577 to irq1_edge_low_force_override + - ACPI: scan: Fix device check notification handling + - arm64: dts: rockchip: add missing interrupt-names for rk356x vdpu + - arm64: dts: rockchip: fix reset-names for rk356x i2s2 controller + - arm64: dts: rockchip: drop rockchip,trcm-sync-tx-only from rk3588 i2s + - objtool: Fix UNWIND_HINT_{SAVE,RESTORE} across basic blocks + - x86, relocs: Ignore relocations in .notes section + - SUNRPC: fix a memleak in gss_import_v2_context + - SUNRPC: fix some memleaks in gssx_dec_option_array + - arm64: dts: qcom: sm8550: Fix SPMI channels size + - arm64: dts: qcom: sm8650: Fix SPMI channels size + - mmc: wmt-sdmmc: remove an incorrect release_mem_region() call in the .remove + function + - ACPI: CPPC: enable AMD CPPC V2 support for family 17h processors + - btrfs: fix race when detecting delalloc ranges during fiemap + - wifi: rtw88: 8821cu: Fix firmware upload fail + - wifi: rtw88: 8821c: Fix beacon loss and disconnect + - wifi: rtw88: 8821c: Fix false alarm count + - wifi: brcm80211: handle pmk_op allocation failure + - riscv: dts: starfive: jh7100: fix root clock names + - PCI: Make pci_dev_is_disconnected() helper public for other drivers + - iommu/vt-d: Don't issue ATS Invalidation request when device is disconnected + - iommu/vt-d: Use rbtree to track iommu probed devices + - iommu/vt-d: Improve ITE fault handling if target device isn't present + - iommu/vt-d: Use device rbtree in iopf reporting path + - iommu: Add static iommu_ops->release_domain + - iommu/vt-d: Fix NULL domain on device release + - igc: Fix missing time sync events + - igb: Fix missing time sync events + - ice: fix stats being updated by way too large values + - Bluetooth: Remove HCI_POWER_OFF_TIMEOUT + - Bluetooth: mgmt: Remove leftover queuing of power_off work + - Bluetooth: Remove superfluous call to hci_conn_check_pending() + - Bluetooth: Remove BT_HS + - Bluetooth: hci_event: Fix not indicating new connection for BIG Sync + - Bluetooth: hci_qca: don't use IS_ERR_OR_NULL() with gpiod_get_optional() + - Bluetooth: hci_core: Cancel request on command timeout + - Bluetooth: hci_sync: Fix overwriting request callback + - Bluetooth: hci_h5: Add ability to allocate memory for private data + - Bluetooth: btrtl: fix out of bounds memory access + - Bluetooth: hci_core: Fix possible buffer overflow + - Bluetooth: msft: Fix memory leak + - Bluetooth: btusb: Fix memory leak + - Bluetooth: af_bluetooth: Fix deadlock + - Bluetooth: fix use-after-free in accessing skb after sending it + - sr9800: Add check for usbnet_get_endpoints + - s390/cache: prevent rebuild of shared_cpu_list + - bpf: Fix DEVMAP_HASH overflow check on 32-bit arches + - bpf: Fix hashtab overflow check on 32-bit arches + - bpf: Fix stackmap overflow check on 32-bit arches + - net: dsa: microchip: make sure drive strength configuration is not lost by + soft reset + - dpll: spec: use proper enum for pin capabilities attribute + - iommu: Fix compilation without CONFIG_IOMMU_INTEL + - ipv6: fib6_rules: flush route cache when rule is changed + - net: ip_tunnel: make sure to pull inner header in ip_tunnel_rcv() + - octeontx2-af: Fix devlink params + - net: phy: fix phy_get_internal_delay accessing an empty array + - dpll: fix dpll_xa_ref_*_del() for multiple registrations + - net: hns3: fix wrong judgment condition issue + - net: hns3: fix kernel crash when 1588 is received on HIP08 devices + - net: hns3: fix port duplex configure error in IMP reset + - Bluetooth: Fix eir name length + - net: phy: dp83822: Fix RGMII TX delay configuration + - erofs: fix lockdep false positives on initializing erofs_pseudo_mnt + - OPP: debugfs: Fix warning around icc_get_name() + - tcp: fix incorrect parameter validation in the do_tcp_getsockopt() function + - ipmr: fix incorrect parameter validation in the ip_mroute_getsockopt() + function + - l2tp: fix incorrect parameter validation in the pppol2tp_getsockopt() + function + - udp: fix incorrect parameter validation in the udp_lib_getsockopt() function + - net: kcm: fix incorrect parameter validation in the kcm_getsockopt) function + - net/x25: fix incorrect parameter validation in the x25_getsockopt() function + - devlink: Fix length of eswitch inline-mode + - r8152: fix unknown device for choose_configuration + - nfp: flower: handle acti_netdevs allocation failure + - bpf: hardcode BPF_PROG_PACK_SIZE to 2MB * num_possible_nodes() + - dm raid: fix false positive for requeue needed during reshape + - dm: call the resume method on internal suspend + - fbdev/simplefb: change loglevel when the power domains cannot be parsed + - drm/tegra: dsi: Add missing check for of_find_device_by_node + - drm/tegra: dpaux: Fix PM disable depth imbalance in tegra_dpaux_probe + - drm/tegra: dsi: Fix some error handling paths in tegra_dsi_probe() + - drm/tegra: dsi: Fix missing pm_runtime_disable() in the error handling path + of tegra_dsi_probe() + - drm/tegra: hdmi: Fix some error handling paths in tegra_hdmi_probe() + - drm/tegra: rgb: Fix some error handling paths in tegra_dc_rgb_probe() + - drm/tegra: rgb: Fix missing clk_put() in the error handling paths of + tegra_dc_rgb_probe() + - drm/tegra: output: Fix missing i2c_put_adapter() in the error handling paths + of tegra_output_probe() + - drm/rockchip: inno_hdmi: Fix video timing + - drm: Don't treat 0 as -1 in drm_fixp2int_ceil + - drm/vkms: Avoid reading beyond LUT array + - drm/vmwgfx: fix a memleak in vmw_gmrid_man_get_node + - drm/rockchip: lvds: do not overwrite error code + - drm/rockchip: lvds: do not print scary message when probing defer + - drm/panel-edp: use put_sync in unprepare + - drm/lima: fix a memleak in lima_heap_alloc + - ASoC: amd: acp: Add missing error handling in sof-mach + - ASoC: SOF: amd: Fix memory leak in amd_sof_acp_probe() + - ASoC: SOF: core: Skip firmware test for custom loaders + - ASoC: SOF: amd: Compute file paths on firmware load + - soundwire: stream: add missing const to Documentation + - dmaengine: tegra210-adma: Update dependency to ARCH_TEGRA + - media: tc358743: register v4l2 async device only after successful setup + - media: cadence: csi2rx: use match fwnode for media link + - PCI/DPC: Print all TLP Prefixes, not just the first + - perf record: Fix possible incorrect free in record__switch_output() + - perf record: Check conflict between '--timestamp-filename' option and pipe + mode before recording + - HID: lenovo: Add middleclick_workaround sysfs knob for cptkbd + - drm/amd/display: Fix a potential buffer overflow in 'dp_dsc_clock_en_read()' + - perf pmu: Treat the msr pmu as software + - crypto: qat - avoid memcpy() overflow warning + - ALSA: hda: cs35l41: Set Channel Index correctly when system is missing _DSD + - drm/amd/display: Fix potential NULL pointer dereferences in + 'dcn10_set_output_transfer_func()' + - ASoC: sh: rz-ssi: Fix error message print + - drm/vmwgfx: Fix vmw_du_get_cursor_mob fencing of newly-created MOBs + - clk: renesas: r8a779g0: Fix PCIe clock name + - pinctrl: renesas: rzg2l: Fix locking in rzg2l_dt_subnode_to_map() + - pinctrl: renesas: r8a779g0: Add missing SCIF_CLK2 pin group/function + - clk: samsung: exynos850: Propagate SPI IPCLK rate change + - media: v4l2: cci: print leading 0 on error + - perf evsel: Fix duplicate initialization of data->id in + evsel__parse_sample() + - perf bpf: Clean up the generated/copied vmlinux.h + - clk: meson: Add missing clocks to axg_clk_regmaps + - media: em28xx: annotate unchecked call to media_device_register() + - media: v4l2-tpg: fix some memleaks in tpg_alloc + - media: v4l2-mem2mem: fix a memleak in v4l2_m2m_register_entity + - media: dt-bindings: techwell,tw9900: Fix port schema ref + - mtd: spinand: esmt: Extend IDs to 5 bytes + - media: edia: dvbdev: fix a use-after-free + - pinctrl: mediatek: Drop bogus slew rate register range for MT8186 + - pinctrl: mediatek: Drop bogus slew rate register range for MT8192 + - drm/amdgpu: Fix potential out-of-bounds access in + 'amdgpu_discovery_reg_base_init()' + - clk: qcom: reset: Commonize the de/assert functions + - clk: qcom: reset: Ensure write completion on reset de/assertion + - quota: Fix potential NULL pointer dereference + - quota: Fix rcu annotations of inode dquot pointers + - quota: Properly annotate i_dquot arrays with __rcu + - ASoC: Intel: ssp-common: Add stub for sof_ssp_get_codec_name + - PCI/P2PDMA: Fix a sleeping issue in a RCU read section + - PCI: switchtec: Fix an error handling path in switchtec_pci_probe() + - crypto: xilinx - call finalize with bh disabled + - drivers/ps3: select VIDEO to provide cmdline functions + - perf thread_map: Free strlist on normal path in thread_map__new_by_tid_str() + - perf srcline: Add missed addr2line closes + - dt-bindings: msm: qcom, mdss: Include ommited fam-b compatible + - drm/msm/dpu: fix the programming of INTF_CFG2_DATA_HCTL_EN + - drm/msm/dpu: Only enable DSC_MODE_MULTIPLEX if dsc_merge is enabled + - drm/radeon/ni: Fix wrong firmware size logging in ni_init_microcode() + - drm/amd/display: fix NULL checks for adev->dm.dc in amdgpu_dm_fini() + - clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks + - clk: renesas: r8a779f0: Correct PFC/GPIO parent clock + - clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 + mux + - ALSA: seq: fix function cast warnings + - perf expr: Fix "has_event" function for metric style events + - perf stat: Avoid metric-only segv + - perf metric: Don't remove scale from counts + - ASoC: meson: aiu: fix function pointer type mismatch + - ASoC: meson: t9015: fix function pointer type mismatch + - powerpc: Force inlining of arch_vmap_p{u/m}d_supported() + - ASoC: SOF: Add some bounds checking to firmware data + - drm: ci: use clk_ignore_unused for apq8016 + - NTB: fix possible name leak in ntb_register_device() + - media: cedrus: h265: Fix configuring bitstream size + - media: sun8i-di: Fix coefficient writes + - media: sun8i-di: Fix power on/off sequences + - media: sun8i-di: Fix chroma difference threshold + - staging: media: starfive: Set 16 bpp for capture_raw device + - media: imx: csc/scaler: fix v4l2_ctrl_handler memory leak + - media: go7007: add check of return value of go7007_read_addr() + - media: pvrusb2: remove redundant NULL check + - media: videobuf2: Add missing doc comment for waiting_in_dqbuf + - media: pvrusb2: fix pvr2_stream_callback casts + - clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times + - drm/amd/display: Add 'replay' NULL check in 'edp_set_replay_allow_active()' + - drm/panel: boe-tv101wum-nl6: make use of prepare_prev_first + - drm/msm/dpu: finalise global state object + - drm/mediatek: dsi: Fix DSI RGB666 formats and definitions + - PCI: Mark 3ware-9650SE Root Port Extended Tags as broken + - drm/bridge: adv7511: fix crash on irq during probe + - pinctrl: renesas: Allow the compiler to optimize away sh_pfc_pm + - clk: hisilicon: hi3519: Release the correct number of gates in + hi3519_clk_unregister() + - clk: hisilicon: hi3559a: Fix an erroneous devm_kfree() + - clk: mediatek: mt8135: Fix an error handling path in + clk_mt8135_apmixed_probe() + - clk: mediatek: mt7622-apmixedsys: Fix an error handling path in + clk_mt8135_apmixed_probe() + - clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF + - clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical + - drm/tegra: put drm_gem_object ref on error in tegra_fb_create + - tty: mips_ejtag_fdc: Fix passing incompatible pointer type warning + - media: ivsc: csi: Swap SINK and SOURCE pads + - media: i2c: imx290: Fix IMX920 typo + - mfd: syscon: Call of_node_put() only when of_parse_phandle() takes a ref + - mfd: altera-sysmgr: Call of_node_put() only when of_parse_phandle() takes a + ref + - perf print-events: make is_event_supported() more robust + - crypto: arm/sha - fix function cast warnings + - crypto: ccp - Avoid discarding errors in psp_send_platform_access_msg() + - crypto: qat - remove unused macros in qat_comp_alg.c + - crypto: qat - removed unused macro in adf_cnv_dbgfs.c + - crypto: qat - avoid division by zero + - crypto: qat - remove double initialization of value + - crypto: qat - fix ring to service map for dcc in 4xxx + - crypto: qat - fix ring to service map for dcc in 420xx + - crypto: jitter - fix CRYPTO_JITTERENTROPY help text + - drm/tidss: Fix initial plane zpos values + - drm/tidss: Fix sync-lost issue with two displays + - clk: imx: imx8mp: Fix SAI_MCLK_SEL definition + - mtd: maps: physmap-core: fix flash size larger than 32-bit + - mtd: rawnand: lpc32xx_mlc: fix irq handler prototype + - mtd: rawnand: brcmnand: exec_op helper functions return type fixes + - ASoC: meson: axg-tdm-interface: fix mclk setup without mclk-fs + - ASoC: meson: axg-tdm-interface: add frame rate constraint + - drm/msm/a6xx: specify UBWC config for sc7180 + - drm/msm/a7xx: Fix LLC typo + - dt-bindings: arm-smmu: fix SM8[45]50 GPU SMMU if condition + - perf pmu: Fix a potential memory leak in perf_pmu__lookup() + - HID: amd_sfh: Update HPD sensor structure elements + - HID: amd_sfh: Avoid disabling the interrupt + - drm/amdgpu: Fix missing break in ATOM_ARG_IMM Case of atom_get_src_int() + - media: pvrusb2: fix uaf in pvr2_context_set_notify + - media: dvb-frontends: avoid stack overflow warnings with clang + - media: go7007: fix a memleak in go7007_load_encoder + - media: ttpci: fix two memleaks in budget_av_attach + - media: mediatek: vcodec: avoid -Wcast-function-type-strict warning + - arm64: ftrace: Don't forbid CALL_OPS+CC_OPTIMIZE_FOR_SIZE with Clang + - drm/tests: helpers: Include missing drm_drv header + - drm/amd/pm: Fix esm reg mask use to get pcie speed + - gpio: nomadik: fix offset bug in nmk_pmx_set() + - drm/mediatek: Fix a null pointer crash in mtk_drm_crtc_finish_page_flip + - mfd: cs42l43: Fix wrong register defaults + - powerpc/32: fix ADB_CUDA kconfig warning + - powerpc/pseries: Fix potential memleak in papr_get_attr() + - powerpc/hv-gpci: Fix the H_GET_PERF_COUNTER_INFO hcall return value checks + - clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk' + - clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk' + - clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset + - perf vendor events amd: Fix Zen 4 cache latency events + - drm/msm/dpu: allow certain formats for CDM for DP + - drm/msm/dpu: add division of drm_display_mode's hskew parameter + - media: usbtv: Remove useless locks in usbtv_video_free() + - drm/xe: Fix ref counting leak on page fault + - drm/xe: Replace 'grouped target' in Makefile with pattern rule + - lib/stackdepot: fix first entry having a 0-handle + - lib/stackdepot: off by one in depot_fetch_stack() + - modules: wait do_free_init correctly + - mfd: cs42l43: Fix wrong GPIO_FN_SEL and SPI_CLK_CONFIG1 defaults + - power: supply: mm8013: fix "not charging" detection + - powerpc/embedded6xx: Fix no previous prototype for avr_uart_send() etc. + - powerpc/4xx: Fix warp_gpio_leds build failure + - RISC-V: KVM: Forward SEED CSR access to user space + - leds: aw2013: Unlock mutex before destroying it + - leds: sgm3140: Add missing timer cleanup and flash gpio control + - backlight: hx8357: Fix potential NULL pointer dereference + - backlight: ktz8866: Correct the check for of_property_read_u32 + - backlight: lm3630a: Initialize backlight_properties on init + - backlight: lm3630a: Don't set bl->props.brightness in get_brightness + - backlight: da9052: Fully initialize backlight_properties during probe + - backlight: lm3639: Fully initialize backlight_properties during probe + - backlight: lp8788: Fully initialize backlight_properties during probe + - sparc32: Use generic cmpdi2/ucmpdi2 variants + - mtd: maps: sun_uflash: Declare uflash_devinit static + - sparc32: Do not select GENERIC_ISA_DMA + - sparc32: Fix section mismatch in leon_pci_grpci + - clk: Fix clk_core_get NULL dereference + - clk: zynq: Prevent null pointer dereference caused by kmalloc failure + - PCI: brcmstb: Fix broken brcm_pcie_mdio_write() polling + - cifs: Fix writeback data corruption + - ALSA: hda/realtek: fix ALC285 issues on HP Envy x360 laptops + - ALSA: hda/tas2781: use dev_dbg in system_resume + - ALSA: hda/tas2781: add lock to system_suspend + - ALSA: hda/tas2781: do not reset cur_* values in runtime_suspend + - ALSA: hda/tas2781: do not call pm_runtime_force_* in system_resume/suspend + - ALSA: hda/tas2781: restore power state after system_resume + - ALSA: scarlett2: Fix Scarlett 4th Gen 4i4 low-voltage detection + - ALSA: scarlett2: Fix Scarlett 4th Gen autogain status values + - ALSA: scarlett2: Fix Scarlett 4th Gen input gain range + - ALSA: scarlett2: Fix Scarlett 4th Gen input gain range again + - mips: cm: Convert __mips_cm_l2sync_phys_base() to weak function + - platform/x86/intel/pmc/lnl: Remove SSRAM support + - platform/x86/intel/pmc/arl: Put GNA device in D3 + - platform/x86/amd/pmf: Do not use readl() for policy buffer access + - ALSA: usb-audio: Stop parsing channels bits when all channels are found. + - phy: qcom: qmp-usb: split USB-C PHY driver + - phy: qcom: qmp-usbc: add support for the Type-C handling + - phy: qcom: qmp-usbc: handle CLAMP register in a correct way + - scsi: hisi_sas: Fix a deadlock issue related to automatic dump + - RDMA/irdma: Remove duplicate assignment + - RDMA/srpt: Do not register event handler until srpt device is fully setup + - f2fs: compress: fix to guarantee persisting compressed blocks by CP + - f2fs: compress: fix to cover normal cluster write with cp_rwsem + - f2fs: compress: fix to check unreleased compressed cluster + - f2fs: compress: fix to avoid inconsistence bewteen i_blocks and dnode + - f2fs: fix to remove unnecessary f2fs_bug_on() to avoid panic + - f2fs: zone: fix to wait completion of last bio in zone correctly + - f2fs: fix NULL pointer dereference in f2fs_submit_page_write() + - f2fs: compress: fix to cover f2fs_disable_compressed_file() w/ i_sem + - f2fs: fix to avoid potential panic during recovery + - scsi: csiostor: Avoid function pointer casts + - i3c: dw: Disable IBI IRQ depends on hot-join and SIR enabling + - RDMA/hns: Fix mis-modifying default congestion control algorithm + - RDMA/device: Fix a race between mad_client and cm_client init + - RDMA/rtrs-clt: Check strnlen return len in sysfs mpath_policy_store() + - scsi: bfa: Fix function pointer type mismatch for hcb_qe->cbfn + - f2fs: fix to create selinux label during whiteout initialization + - f2fs: compress: fix to check zstd compress level correctly in mount option + - net: sunrpc: Fix an off by one in rpc_sockaddr2uaddr() + - NFSv4.2: fix nfs4_listxattr kernel BUG at mm/usercopy.c:102 + - NFSv4.2: fix listxattr maximum XDR buffer size + - f2fs: compress: fix to check compress flag w/ .i_sem lock + - f2fs: check number of blocks in a current section + - watchdog: starfive: Check pm_runtime_enabled() before decrementing usage + counter + - watchdog: stm32_iwdg: initialize default timeout + - f2fs: fix to use correct segment type in f2fs_allocate_data_block() + - f2fs: ro: compress: fix to avoid caching unaligned extent + - RDMA/mana_ib: Fix bug in creation of dma regions + - RDMA/mana_ib: Introduce mdev_to_gc helper function + - RDMA/mana_ib: Introduce mana_ib_get_netdev helper function + - RDMA/mana_ib: Introduce mana_ib_install_cq_cb helper function + - RDMA/mana_ib: Use virtual address in dma regions for MRs + - Input: iqs7222 - add support for IQS7222D v1.1 and v1.2 + - NFS: Fix nfs_netfs_issue_read() xarray locking for writeback interrupt + - NFS: Fix an off by one in root_nfs_cat() + - NFSv4.1/pnfs: fix NFS with TLS in pnfs + - ACPI: HMAT: Remove register of memory node for generic target + - f2fs: compress: relocate some judgments in f2fs_reserve_compress_blocks + - f2fs: compress: fix reserve_cblocks counting error when out of space + - f2fs: fix to truncate meta inode pages forcely + - f2fs: zone: fix to remove pow2 check condition for zoned block device + - cxl: Fix the incorrect assignment of SSLBIS entry pointer initial location + - perf/x86/amd/core: Avoid register reset when CPU is dead + - afs: Revert "afs: Hide silly-rename files from userspace" + - afs: Don't cache preferred address + - afs: Fix occasional rmdir-then-VNOVNODE with generic/011 + - f2fs: fix to avoid use-after-free issue in f2fs_filemap_fault + - nfs: fix panic when nfs4_ff_layout_prepare_ds() fails + - ovl: relax WARN_ON in ovl_verify_area() + - io_uring/net: correct the type of variable + - remoteproc: stm32: Fix incorrect type in assignment for va + - remoteproc: stm32: Fix incorrect type assignment returned by + stm32_rproc_get_loaded_rsc_tablef + - iio: pressure: mprls0025pa fix off-by-one enum + - usb: phy: generic: Get the vbus supply + - tty: vt: fix 20 vs 0x20 typo in EScsiignore + - serial: max310x: fix syntax error in IRQ error message + - tty: serial: samsung: fix tx_empty() to return TIOCSER_TEMT + - arm64: dts: broadcom: bcmbca: bcm4908: drop invalid switch cells + - coresight: Fix issue where a source device's helpers aren't disabled + - coresight: etm4x: Set skip_power_up in etm4_init_arch_data function + - xhci: Add interrupt pending autoclear flag to each interrupter + - xhci: make isoc_bei_interval variable interrupter specific. + - xhci: remove unnecessary event_ring_deq parameter from xhci_handle_event() + - xhci: update event ring dequeue pointer position to controller correctly + - coccinelle: device_attr_show: Remove useless expression STR + - kconfig: fix infinite loop when expanding a macro at the end of file + - iio: gts-helper: Fix division loop + - bus: mhi: ep: check the correct variable in mhi_ep_register_controller() + - hwtracing: hisi_ptt: Move type check to the beginning of + hisi_ptt_pmu_event_init() + - rtc: mt6397: select IRQ_DOMAIN instead of depending on it + - rtc: max31335: fix interrupt status reg + - serial: 8250_exar: Don't remove GPIO device on suspend + - staging: greybus: fix get_channel_from_mode() failure path + - mei: vsc: Call wake_up() in the threaded IRQ handler + - mei: vsc: Don't use sleeping condition in wait_event_timeout() + - usb: gadget: net2272: Use irqflags in the call to net2272_probe_fin + - char: xilinx_hwicap: Fix NULL vs IS_ERR() bug + - x86/hyperv: Use per cpu initial stack for vtl context + - ASoC: tlv320adc3xxx: Don't strip remove function when driver is builtin + - thermal/drivers/mediatek/lvts_thermal: Fix a memory leak in an error + handling path + - thermal/drivers/qoriq: Fix getting tmu range + - io_uring: don't save/restore iowait state + - spi: lpspi: Avoid potential use-after-free in probe() + - spi: Restore delays for non-GPIO chip select + - ASoC: rockchip: i2s-tdm: Fix inaccurate sampling rates + - nouveau: reset the bo resource bus info after an eviction + - tcp: Fix NEW_SYN_RECV handling in inet_twsk_purge() + - rds: tcp: Fix use-after-free of net in reqsk_timer_handler(). + - octeontx2-af: Use matching wake_up API variant in CGX command interface + - s390/vtime: fix average steal time calculation + - net/sched: taprio: proper TCA_TAPRIO_TC_ENTRY_INDEX check + - devlink: Fix devlink parallel commands processing + - riscv: Only check online cpus for emulated accesses + - soc: fsl: dpio: fix kcalloc() argument order + - cpufreq: Fix per-policy boost behavior on SoCs using cpufreq_boost_set_sw() + - io_uring: Fix release of pinned pages when __io_uaddr_map fails + - tcp: Fix refcnt handling in __inet_hash_connect(). + - vmxnet3: Fix missing reserved tailroom + - hsr: Fix uninit-value access in hsr_get_node() + - net: txgbe: fix clk_name exceed MAX_DEV_ID limits + - spi: spi-mem: add statistics support to ->exec_op() calls + - spi: Fix error code checking in spi_mem_exec_op() + - nvme: fix reconnection fail due to reserved tag allocation + - drm/xe: Invalidate userptr VMA on page pin fault + - drm/xe: Skip VMAs pin when requesting signal to the last XE_EXEC + - net: mediatek: mtk_eth_soc: clear MAC_MCR_FORCE_LINK only when MAC is up + - net: ethernet: mtk_eth_soc: fix PPE hanging issue + - io_uring: fix poll_remove stalled req completion + - ASoC: SOF: amd: Move signed_fw_image to struct acp_quirk_entry + - ASoC: SOF: amd: Skip IRAM/DRAM size modification for Steam Deck OLED + - riscv: Fix compilation error with FAST_GUP and rv32 + - xen/evtchn: avoid WARN() when unbinding an event channel + - xen/events: increment refcnt only if event channel is refcounted + - packet: annotate data-races around ignore_outgoing + - xfrm: Allow UDP encapsulation only in offload modes + - net: veth: do not manipulate GRO when using XDP + - net: dsa: mt7530: prevent possible incorrect XTAL frequency selection + - spi: spi-imx: fix off-by-one in mx51 CPU mode burst length + - drm: Fix drm_fixp2int_round() making it add 0.5 + - virtio: uapi: Drop __packed attribute in linux/virtio_pci.h + - vdpa_sim: reset must not run + - vdpa/mlx5: Allow CVQ size changes + - virtio: packed: fix unmap leak for indirect desc table + - net: move dev->state into net_device_read_txrx group + - wireguard: receive: annotate data-race around receiving_counter.counter + - rds: introduce acquire/release ordering in acquire/release_in_xmit() + - hsr: Handle failures in module init + - ipv4: raw: Fix sending packets from raw sockets via IPsec tunnels + - nouveau/gsp: don't check devinit disable on GSP. + - ceph: stop copying to iter at EOF on sync reads + - net: phy: fix phy_read_poll_timeout argument type in genphy_loopback + - dm-integrity: fix a memory leak when rechecking the data + - net/bnx2x: Prevent access to a freed page in page_pool + - devlink: fix port new reply cmd type + - octeontx2: Detect the mbox up or down message via register + - octeontx2-pf: Wait till detach_resources msg is complete + - octeontx2-pf: Use default max_active works instead of one + - octeontx2-pf: Send UP messages to VF only when VF is up. + - octeontx2-af: Use separate handlers for interrupts + - drm/amdgpu: add MMHUB 3.3.1 support + - drm/amdgpu: fix mmhub client id out-of-bounds access + - drm/amdgpu: drop setting buffer funcs in sdma442 + - netfilter: nft_set_pipapo: release elements in clone only from destroy path + - netfilter: nf_tables: do not compare internal table flags on updates + - rcu: add a helper to report consolidated flavor QS + - net: report RCU QS on threaded NAPI repolling + - bpf: report RCU QS in cpumap kthread + - net: dsa: mt7530: fix link-local frames that ingress vlan filtering ports + - net: dsa: mt7530: fix handling of all link-local frames + - netfilter: nf_tables: Fix a memory leak in nf_tables_updchain + - spi: spi-mt65xx: Fix NULL pointer access in interrupt handler + - selftests: forwarding: Fix ping failure due to short timeout + - dm io: Support IO priority + - dm-integrity: align the outgoing bio in integrity_recheck + - x86/efistub: Clear decompressor BSS in native EFI entrypoint + - x86/efistub: Don't clear BSS twice in mixed mode + - printk: Adjust mapping for 32bit seq macros + - printk: Use prb_first_seq() as base for 32bit seq macros + - Linux 6.8.2 + - [Config] updateconfig following v6.8.2 import + + * Provide python perf module (LP: #2051560) + - [Packaging] enable perf python module + - [Packaging] provide a wrapper module for python-perf + + * To support AMD Adaptive Backlight Management (ABM) for power profiles daemon + >= 2.0 (LP: #2056716) + - drm/amd/display: add panel_power_savings sysfs entry to eDP connectors + - drm/amdgpu: respect the abmlevel module parameter value if it is set + + * Miscellaneous Ubuntu changes + - [Config] Disable StarFive JH7100 support + - [Config] Disable Renesas RZ/Five support + - [Config] Disable BINFMT_FLAT for riscv64 + + -- Roxana Nicolescu Wed, 01 May 2024 16:02:05 +0200 + +linux (6.8.0-31.31) noble; urgency=medium + + * noble/linux: 6.8.0-31.31 -proposed tracker (LP: #2062933) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.04.04) + + -- Andrea Righi Fri, 19 Apr 2024 23:46:38 +0200 + +linux (6.8.0-30.30) noble; urgency=medium + + * noble/linux: 6.8.0-30.30 -proposed tracker (LP: #2061893) + + * System unstable, kernel ring buffer flooded with "BUG: Bad page state in + process swapper/0" (LP: #2056706) + - xen-netfront: Add missing skb_mark_for_recycle + + -- Andrea Righi Tue, 16 Apr 2024 21:17:11 +0200 + +linux (6.8.0-29.29) noble; urgency=medium + + * noble/linux: 6.8.0-29.29 -proposed tracker (LP: #2061888) + + * [24.04 FEAT] [SEC2353] zcrypt: extend error recovery to deal with device + scans (LP: #2050019) + - s390/zcrypt: harmonize debug feature calls and defines + - s390/zcrypt: introduce dynamic debugging for AP and zcrypt code + - s390/pkey: harmonize pkey s390 debug feature calls + - s390/pkey: introduce dynamic debugging for pkey + - s390/ap: add debug possibility for AP messages + - s390/zcrypt: add debug possibility for CCA and EP11 messages + - s390/ap: rearm APQNs bindings complete completion + - s390/ap: clarify AP scan bus related functions and variables + - s390/ap: rework ap_scan_bus() to return true on config change + - s390/ap: introduce mutex to lock the AP bus scan + - s390/zcrypt: introduce retries on in-kernel send CPRB functions + - s390/zcrypt: improve zcrypt retry behavior + - s390/pkey: improve pkey retry behavior + + * [24.04 FEAT] Memory hotplug vmem pages (s390x) (LP: #2051835) + - mm/memory_hotplug: introduce MEM_PREPARE_ONLINE/MEM_FINISH_OFFLINE notifiers + - s390/mm: allocate vmemmap pages from self-contained memory range + - s390/sclp: remove unhandled memory notifier type + - s390/mm: implement MEM_PREPARE_ONLINE/MEM_FINISH_OFFLINE notifiers + - s390: enable MHP_MEMMAP_ON_MEMORY + - [Config] enable CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE and + CONFIG_MHP_MEMMAP_ON_MEMORY for s390x + + -- Paolo Pisati Tue, 16 Apr 2024 20:32:09 +0200 + +linux (6.8.0-28.28) noble; urgency=medium + + * noble/linux: 6.8.0-28.28 -proposed tracker (LP: #2061867) + + * linux-gcp 6.8.0-1005.5 (+ others) Noble kernel regression iwth new apparmor + profiles/features (LP: #2061851) + - SAUCE: apparmor4.0.0 [92/90]: fix address mapping for recvfrom + + -- Paolo Pisati Tue, 16 Apr 2024 18:29:17 +0200 + +linux (6.8.0-25.25) noble; urgency=medium + + * noble/linux: 6.8.0-25.25 -proposed tracker (LP: #2061083) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.04.04) + + * Apply mitigations for the native BHI hardware vulnerabilty (LP: #2060909) + - x86/cpufeatures: Add new word for scattered features + - x86/bugs: Change commas to semicolons in 'spectre_v2' sysfs file + - x86/syscall: Don't force use of indirect calls for system calls + - x86/bhi: Add support for clearing branch history at syscall entry + - x86/bhi: Define SPEC_CTRL_BHI_DIS_S + - x86/bhi: Enumerate Branch History Injection (BHI) bug + - x86/bhi: Add BHI mitigation knob + - x86/bhi: Mitigate KVM by default + - KVM: x86: Add BHI_NO + - x86: set SPECTRE_BHI_ON as default + - [Config] enable spectre_bhi=auto by default + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [01/90]: LSM stacking v39: integrity: disassociate + ima_filter_rule from security_audit_rule + - SAUCE: apparmor4.0.0 [02/90]: LSM stacking v39: SM: Infrastructure + management of the sock security + - SAUCE: apparmor4.0.0 [03/90]: LSM stacking v39: LSM: Add the lsmblob data + structure. + - SAUCE: apparmor4.0.0 [04/90]: LSM stacking v39: IMA: avoid label collisions + with stacked LSMs + - SAUCE: apparmor4.0.0 [05/90]: LSM stacking v39: LSM: Use lsmblob in + security_audit_rule_match + - SAUCE: apparmor4.0.0 [06/90]: LSM stacking v39: LSM: Add lsmblob_to_secctx + hook + - SAUCE: apparmor4.0.0 [07/90]: LSM stacking v39: Audit: maintain an lsmblob + in audit_context + - SAUCE: apparmor4.0.0 [08/90]: LSM stacking v39: LSM: Use lsmblob in + security_ipc_getsecid + - SAUCE: apparmor4.0.0 [09/90]: LSM stacking v39: Audit: Update shutdown LSM + data + - SAUCE: apparmor4.0.0 [10/90]: LSM stacking v39: LSM: Use lsmblob in + security_current_getsecid + - SAUCE: apparmor4.0.0 [11/90]: LSM stacking v39: LSM: Use lsmblob in + security_inode_getsecid + - SAUCE: apparmor4.0.0 [12/90]: LSM stacking v39: Audit: use an lsmblob in + audit_names + - SAUCE: apparmor4.0.0 [13/90]: LSM stacking v39: LSM: Create new + security_cred_getlsmblob LSM hook + - SAUCE: apparmor4.0.0 [14/90]: LSM stacking v39: Audit: Change context data + from secid to lsmblob + - SAUCE: apparmor4.0.0 [15/90]: LSM stacking v39: Netlabel: Use lsmblob for + audit data + - SAUCE: apparmor4.0.0 [16/90]: LSM stacking v39: LSM: Ensure the correct LSM + context releaser + - SAUCE: apparmor4.0.0 [17/90]: LSM stacking v39: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [18/90]: LSM stacking v39: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [19/90]: LSM stacking v39: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [20/90]: LSM stacking v39: LSM: Use lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [21/90]: LSM stacking v39: LSM: + security_lsmblob_to_secctx module selection + - SAUCE: apparmor4.0.0 [22/90]: LSM stacking v39: Audit: Create audit_stamp + structure + - SAUCE: apparmor4.0.0 [23/90]: LSM stacking v39: Audit: Allow multiple + records in an audit_buffer + - SAUCE: apparmor4.0.0 [24/90]: LSM stacking v39: Audit: Add record for + multiple task security contexts + - SAUCE: apparmor4.0.0 [25/90]: LSM stacking v39: audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor4.0.0 [26/90]: LSM stacking v39: Audit: Add record for + multiple object contexts + - SAUCE: apparmor4.0.0 [27/90]: LSM stacking v39: LSM: Remove unused + lsmcontext_init() + - SAUCE: apparmor4.0.0 [28/90]: LSM stacking v39: LSM: Improve logic in + security_getprocattr + - SAUCE: apparmor4.0.0 [29/90]: LSM stacking v39: LSM: secctx provider check + on release + - SAUCE: apparmor4.0.0 [31/90]: LSM stacking v39: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [32/90]: LSM stacking v39: LSM: Identify which LSM + handles the context string + - SAUCE: apparmor4.0.0 [33/90]: LSM stacking v39: AppArmor: Remove the + exclusive flag + - SAUCE: apparmor4.0.0 [34/90]: LSM stacking v39: LSM: Add mount opts blob + size tracking + - SAUCE: apparmor4.0.0 [35/90]: LSM stacking v39: LSM: allocate mnt_opts blobs + instead of module specific data + - SAUCE: apparmor4.0.0 [36/90]: LSM stacking v39: LSM: Infrastructure + management of the key security blob + - SAUCE: apparmor4.0.0 [37/90]: LSM stacking v39: LSM: Infrastructure + management of the mnt_opts security blob + - SAUCE: apparmor4.0.0 [38/90]: LSM stacking v39: LSM: Correct handling of + ENOSYS in inode_setxattr + - SAUCE: apparmor4.0.0 [39/90]: LSM stacking v39: LSM: Remove lsmblob + scaffolding + - SAUCE: apparmor4.0.0 [40/90]: LSM stacking v39: LSM: Allow reservation of + netlabel + - SAUCE: apparmor4.0.0 [41/90]: LSM stacking v39: LSM: restrict + security_cred_getsecid() to a single LSM + - SAUCE: apparmor4.0.0 [42/90]: LSM stacking v39: Smack: Remove + LSM_FLAG_EXCLUSIVE + - SAUCE: apparmor4.0.0 [43/90]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [12/95]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [44/90]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [45/90]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [46/90]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [47/90]: af_unix mediation + - SAUCE: apparmor4.0.0 [48/90]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [49/90]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [50/90]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [51/90]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [52/90]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [53/90]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [54/90]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [55/90]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [56/90]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [57/90]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [58/90]: prompt - fix caching + - SAUCE: apparmor4.0.0 [59/90]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [60/90]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [61/90]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [62/90]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [63/90]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [64/90]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [65/90] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [69/90]: add io_uring mediation + - SAUCE: apparmor4.0.0 [70/90]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [71/90]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [72/90]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [73/90]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [74/90]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [75/90]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [76/90]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [77/90]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [78/90]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [79/90]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [80/90]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [81/90]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [82/90]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [83/90]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [84/90]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [85/90]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [86/90]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [87/90]: fixup notify + - SAUCE: apparmor4.0.0 [88/90]: apparmor: add fine grained ipv4/ipv6 mediation + - SAUCE: apparmor4.0.0 [89/90]:apparmor: disable tailglob responses for now + - SAUCE: apparmor4.0.0 [90/90]: apparmor: Fix notify build warnings + - SAUCE: apparmor4.0.0: fix reserved mem for when we save ipv6 addresses + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [66/90]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [67/90]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [68/90]: userns - make it so special unconfined + profiles can mediate user namespaces + + * [MTL] x86: Fix Cache info sysfs is not populated (LP: #2049793) + - SAUCE: cacheinfo: Check for null last-level cache info + - SAUCE: cacheinfo: Allocate memory for memory if not done from the primary + CPU + - SAUCE: x86/cacheinfo: Delete global num_cache_leaves + - SAUCE: x86/cacheinfo: Clean out init_cache_level() + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor4.0.0: LSM stacking v39: fix build error with + CONFIG_SECURITY=n + - [Config] toolchain version update + + -- Paolo Pisati Fri, 12 Apr 2024 10:42:33 +0200 + +linux (6.8.0-22.22) noble; urgency=medium + + * noble/linux: 6.8.0-22.22 -proposed tracker (LP: #2060238) + + -- Andrea Righi Thu, 04 Apr 2024 23:00:49 +0200 + +linux (6.8.0-21.21) noble; urgency=medium + + * noble/linux: 6.8.0-21.21 -proposed tracker (LP: #2060225) + + * Miscellaneous Ubuntu changes + - [Config] update toolchain version in annotations + + -- Andrea Righi Thu, 04 Apr 2024 22:20:27 +0200 + +linux (6.8.0-20.20) noble; urgency=medium + + * noble/linux: 6.8.0-20.20 -proposed tracker (LP: #2058221) + + * Noble update: v6.8.1 upstream stable release (LP: #2058224) + - x86/mmio: Disable KVM mitigation when X86_FEATURE_CLEAR_CPU_BUF is set + - Documentation/hw-vuln: Add documentation for RFDS + - x86/rfds: Mitigate Register File Data Sampling (RFDS) + - KVM/x86: Export RFDS_NO and RFDS_CLEAR to guests + - Linux 6.8.1 + + * Autopkgtest failures on amd64 (LP: #2048768) + - [Packaging] update to clang-18 + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor4.0.0: LSM stacking v39: fix build error with + CONFIG_SECURITY=n + - [Config] amd64: MITIGATION_RFDS=y + + -- Paolo Pisati Mon, 18 Mar 2024 11:08:14 +0100 + +linux (6.8.0-19.19) noble; urgency=medium + + * noble/linux: 6.8.0-19.19 -proposed tracker (LP: #2057910) + + * Miscellaneous Ubuntu changes + - [Packaging] re-introduce linux-doc as an empty package + + -- Paolo Pisati Thu, 14 Mar 2024 14:36:14 +0100 + +linux (6.8.0-18.18) noble; urgency=medium + + * noble/linux: 6.8.0-18.18 -proposed tracker (LP: #2057456) + + * Miscellaneous Ubuntu changes + - [Packaging] drop dependency on libclang-17 + + -- Paolo Pisati Tue, 12 Mar 2024 14:44:13 +0100 + +linux (6.8.0-17.17) noble; urgency=medium + + * noble/linux: 6.8.0-17.17 -proposed tracker (LP: #2056745) + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] Add debian/control sanity check" + + -- Paolo Pisati Mon, 11 Mar 2024 12:46:38 +0100 + +linux (6.8.0-16.16) noble; urgency=medium + + * noble/linux: 6.8.0-16.16 -proposed tracker (LP: #2056738) + + * left-over ceph debugging printks (LP: #2056616) + - Revert "UBUNTU: SAUCE: ceph: make sure all the files successfully put before + unmounting" + + * qat: Improve error recovery flows (LP: #2056354) + - crypto: qat - add heartbeat error simulator + - crypto: qat - disable arbitration before reset + - crypto: qat - update PFVF protocol for recovery + - crypto: qat - re-enable sriov after pf reset + - crypto: qat - add fatal error notification + - crypto: qat - add auto reset on error + - crypto: qat - limit heartbeat notifications + - crypto: qat - improve aer error reset handling + - crypto: qat - change SLAs cleanup flow at shutdown + - crypto: qat - resolve race condition during AER recovery + - Documentation: qat: fix auto_reset section + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [01/87]: LSM stacking v39: integrity: disassociate + ima_filter_rule from security_audit_rule + - SAUCE: apparmor4.0.0 [02/87]: LSM stacking v39: SM: Infrastructure + management of the sock security + - SAUCE: apparmor4.0.0 [03/87]: LSM stacking v39: LSM: Add the lsmblob data + structure. + - SAUCE: apparmor4.0.0 [04/87]: LSM stacking v39: IMA: avoid label collisions + with stacked LSMs + - SAUCE: apparmor4.0.0 [05/87]: LSM stacking v39: LSM: Use lsmblob in + security_audit_rule_match + - SAUCE: apparmor4.0.0 [06/87]: LSM stacking v39: LSM: Add lsmblob_to_secctx + hook + - SAUCE: apparmor4.0.0 [07/87]: LSM stacking v39: Audit: maintain an lsmblob + in audit_context + - SAUCE: apparmor4.0.0 [08/87]: LSM stacking v39: LSM: Use lsmblob in + security_ipc_getsecid + - SAUCE: apparmor4.0.0 [09/87]: LSM stacking v39: Audit: Update shutdown LSM + data + - SAUCE: apparmor4.0.0 [10/87]: LSM stacking v39: LSM: Use lsmblob in + security_current_getsecid + - SAUCE: apparmor4.0.0 [11/87]: LSM stacking v39: LSM: Use lsmblob in + security_inode_getsecid + - SAUCE: apparmor4.0.0 [12/87]: LSM stacking v39: Audit: use an lsmblob in + audit_names + - SAUCE: apparmor4.0.0 [13/87]: LSM stacking v39: LSM: Create new + security_cred_getlsmblob LSM hook + - SAUCE: apparmor4.0.0 [14/87]: LSM stacking v39: Audit: Change context data + from secid to lsmblob + - SAUCE: apparmor4.0.0 [15/87]: LSM stacking v39: Netlabel: Use lsmblob for + audit data + - SAUCE: apparmor4.0.0 [16/87]: LSM stacking v39: LSM: Ensure the correct LSM + context releaser + - SAUCE: apparmor4.0.0 [17/87]: LSM stacking v39: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [18/87]: LSM stacking v39: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [19/87]: LSM stacking v39: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [20/87]: LSM stacking v39: LSM: Use lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [21/87]: LSM stacking v39: LSM: + security_lsmblob_to_secctx module selection + - SAUCE: apparmor4.0.0 [22/87]: LSM stacking v39: Audit: Create audit_stamp + structure + - SAUCE: apparmor4.0.0 [23/87]: LSM stacking v39: Audit: Allow multiple + records in an audit_buffer + - SAUCE: apparmor4.0.0 [24/87]: LSM stacking v39: Audit: Add record for + multiple task security contexts + - SAUCE: apparmor4.0.0 [25/87]: LSM stacking v39: audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor4.0.0 [26/87]: LSM stacking v39: Audit: Add record for + multiple object contexts + - SAUCE: apparmor4.0.0 [27/87]: LSM stacking v39: LSM: Remove unused + lsmcontext_init() + - SAUCE: apparmor4.0.0 [28/87]: LSM stacking v39: LSM: Improve logic in + security_getprocattr + - SAUCE: apparmor4.0.0 [29/87]: LSM stacking v39: LSM: secctx provider check + on release + - SAUCE: apparmor4.0.0 [31/87]: LSM stacking v39: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [32/87]: LSM stacking v39: LSM: Identify which LSM + handles the context string + - SAUCE: apparmor4.0.0 [33/87]: LSM stacking v39: AppArmor: Remove the + exclusive flag + - SAUCE: apparmor4.0.0 [34/87]: LSM stacking v39: LSM: Add mount opts blob + size tracking + - SAUCE: apparmor4.0.0 [35/87]: LSM stacking v39: LSM: allocate mnt_opts blobs + instead of module specific data + - SAUCE: apparmor4.0.0 [36/87]: LSM stacking v39: LSM: Infrastructure + management of the key security blob + - SAUCE: apparmor4.0.0 [37/87]: LSM stacking v39: LSM: Infrastructure + management of the mnt_opts security blob + - SAUCE: apparmor4.0.0 [38/87]: LSM stacking v39: LSM: Correct handling of + ENOSYS in inode_setxattr + - SAUCE: apparmor4.0.0 [39/87]: LSM stacking v39: LSM: Remove lsmblob + scaffolding + - SAUCE: apparmor4.0.0 [40/87]: LSM stacking v39: LSM: Allow reservation of + netlabel + - SAUCE: apparmor4.0.0 [41/87]: LSM stacking v39: LSM: restrict + security_cred_getsecid() to a single LSM + - SAUCE: apparmor4.0.0 [42/87]: LSM stacking v39: Smack: Remove + LSM_FLAG_EXCLUSIVE + - SAUCE: apparmor4.0.0 [43/87]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [12/95]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [44/87]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [45/87]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [46/87]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [47/87]: af_unix mediation + - SAUCE: apparmor4.0.0 [48/87]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [49/87]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [50/87]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [51/87]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [52/87]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [53/87]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [54/87]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [55/87]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [56/87]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [57/87]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [58/87]: prompt - fix caching + - SAUCE: apparmor4.0.0 [59/87]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [60/87]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [61/87]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [62/87]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [63/87]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [64/87]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [65/87] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [69/87]: add io_uring mediation + - SAUCE: apparmor4.0.0 [70/87]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [71/87]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [72/87]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [73/87]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [74/87]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [75/87]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [76/87]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [77/87]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [78/87]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [79/87]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [80/87]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [81/87]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [82/87]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [83/87]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [84/87]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [85/87]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [86/87]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [87/87]: fixup notify + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [66/87]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [67/87]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [68/87]: userns - make it so special unconfined + profiles can mediate user namespaces + + * Enable lowlatency settings in the generic kernel (LP: #2051342) + - [Config] enable low-latency settings + + * hwmon: (coretemp) Fix core count limitation (LP: #2056126) + - hwmon: (coretemp) Introduce enum for attr index + - hwmon: (coretemp) Remove unnecessary dependency of array index + - hwmon: (coretemp) Replace sensor_device_attribute with device_attribute + - hwmon: (coretemp) Remove redundant pdata->cpu_map[] + - hwmon: (coretemp) Abstract core_temp helpers + - hwmon: (coretemp) Split package temp_data and core temp_data + - hwmon: (coretemp) Remove redundant temp_data->is_pkg_data + - hwmon: (coretemp) Use dynamic allocated memory for core temp_data + + * Miscellaneous Ubuntu changes + - [Config] Disable CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION + - [Packaging] remove debian/scripts/misc/arch-has-odm-enabled.sh + - rebase on v6.8 + - [Config] toolchain version update + + * Miscellaneous upstream changes + - crypto: qat - add fatal error notify method + + * Rebase on v6.8 + + -- Paolo Pisati Mon, 11 Mar 2024 10:14:10 +0100 + +linux (6.8.0-15.15) noble; urgency=medium + + * noble/linux: 6.8.0-15.15 -proposed tracker (LP: #2055871) + + * Miscellaneous Ubuntu changes + - rebase on v6.8-rc7 + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] Transition laptop-23.10 to generic" + + * Rebase on v6.8-rc7 + + -- Paolo Pisati Mon, 04 Mar 2024 11:50:51 +0100 + +linux (6.8.0-14.14) noble; urgency=medium + + * noble/linux: 6.8.0-14.14 -proposed tracker (LP: #2055551) + + * Please change CONFIG_CONSOLE_LOGLEVEL_QUIET to 3 (LP: #2049390) + - [Config] reduce verbosity when booting in quiet mode + + * linux: please move erofs.ko (CONFIG_EROFS for EROFS support) from linux- + modules-extra to linux-modules (LP: #2054809) + - UBUNTU [Packaging]: Include erofs in linux-modules instead of linux-modules- + extra + + * linux: please move dmi-sysfs.ko (CONFIG_DMI_SYSFS for SMBIOS support) from + linux-modules-extra to linux-modules (LP: #2045561) + - [Packaging] Move dmi-sysfs.ko into linux-modules + + * Enable CONFIG_INTEL_IOMMU_DEFAULT_ON and + CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON (LP: #1951440) + - [Config] enable Intel DMA remapping by default + + * disable Intel DMA remapping by default (LP: #1971699) + - [Config] update tracking bug for CONFIG_INTEL_IOMMU_DEFAULT_ON + + * Packaging resync (LP: #1786013) + - debian.master/dkms-versions -- update from kernel-versions + (main/d2024.02.29) + + * Miscellaneous Ubuntu changes + - SAUCE: modpost: Replace 0-length array with flex-array member + - [packaging] do not include debian/ directory in a binary package + - [packaging] remove debian/stamps/keep-dir + + -- Paolo Pisati Fri, 01 Mar 2024 11:45:12 +0100 + +linux (6.8.0-13.13) noble; urgency=medium + + * noble/linux: 6.8.0-13.13 -proposed tracker (LP: #2055421) + + * Packaging resync (LP: #1786013) + - debian.master/dkms-versions -- update from kernel-versions + (main/d2024.02.29) + + * Miscellaneous Ubuntu changes + - rebase on v6.8-rc6 + - [Config] updateconfifs following v6.8-rc6 rebase + + * Rebase on v6.8-rc6 + + -- Paolo Pisati Thu, 29 Feb 2024 15:02:24 +0100 + +linux (6.8.0-12.12) noble; urgency=medium + + * linux-tools-common: man page of usbip[d] is misplaced (LP: #2054094) + - [Packaging] rules: Put usbip manpages in the correct directory + + * Validate connection interval to pass Bluetooth Test Suite (LP: #2052005) + - Bluetooth: Enforce validation on max value of connection interval + + * Turning COMPAT_32BIT_TIME off on s390x (LP: #2038583) + - [Config] Turn off 31-bit COMPAT on s390x + + * Don't produce linux-source binary package (LP: #2043994) + - [Packaging] Add debian/control sanity check + + * Don't produce linux-*-source- package (LP: #2052439) + - [Packaging] Move linux-source package stub to debian/control.d + - [Packaging] Build linux-source package only for the main kernel + + * Don't produce linux-*-cloud-tools-common, linux-*-tools-common and + linux-*-tools-host binary packages (LP: #2048183) + - [Packaging] Move indep tools package stubs to debian/control.d + - [Packaging] Build indep tools packages only for the main kernel + + * Enable CONFIG_INTEL_IOMMU_DEFAULT_ON and + CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON (LP: #1951440) + - [Config] enable Intel DMA remapping by default + + * disable Intel DMA remapping by default (LP: #1971699) + - [Config] update tracking bug for CONFIG_INTEL_IOMMU_DEFAULT_ON + + * Miscellaneous Ubuntu changes + - [Packaging] Transition laptop-23.10 to generic + + -- Paolo Pisati Thu, 22 Feb 2024 14:31:00 +0100 + +linux (6.8.0-11.11) noble; urgency=medium + + * noble/linux: 6.8.0-11.11 -proposed tracker (LP: #2053094) + + * Miscellaneous Ubuntu changes + - [Packaging] riscv64: disable building unnecessary binary debs + + -- Paolo Pisati Wed, 14 Feb 2024 00:04:31 +0100 + +linux (6.8.0-10.10) noble; urgency=medium + + * noble/linux: 6.8.0-10.10 -proposed tracker (LP: #2053015) + + * Miscellaneous Ubuntu changes + - [Packaging] add Rust build-deps for riscv64 + + * Miscellaneous upstream changes + - Revert "Revert "UBUNTU: [Packaging] temporarily disable Rust dependencies on + riscv64"" + + -- Paolo Pisati Tue, 13 Feb 2024 13:23:47 +0100 + +linux (6.8.0-9.9) noble; urgency=medium + + * noble/linux: 6.8.0-9.9 -proposed tracker (LP: #2052945) + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] temporarily disable Rust dependencies on + riscv64" + + -- Paolo Pisati Mon, 12 Feb 2024 15:49:20 +0100 + +linux (6.8.0-8.8) noble; urgency=medium + + * noble/linux: 6.8.0-8.8 -proposed tracker (LP: #2052918) + + * Miscellaneous Ubuntu changes + - [Packaging] riscv64: enable linux-libc-dev build + - v6.8-rc4 rebase + + * Rebase on v6.8-rc4 + + -- Paolo Pisati Mon, 12 Feb 2024 10:13:34 +0100 + +linux (6.8.0-7.7) noble; urgency=medium + + * noble/linux: 6.8.0-7.7 -proposed tracker (LP: #2052691) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [01/87]: LSM stacking v39: integrity: disassociate + ima_filter_rule from security_audit_rule + - SAUCE: apparmor4.0.0 [02/87]: LSM stacking v39: SM: Infrastructure + management of the sock security + - SAUCE: apparmor4.0.0 [03/87]: LSM stacking v39: LSM: Add the lsmblob data + structure. + - SAUCE: apparmor4.0.0 [04/87]: LSM stacking v39: IMA: avoid label collisions + with stacked LSMs + - SAUCE: apparmor4.0.0 [05/87]: LSM stacking v39: LSM: Use lsmblob in + security_audit_rule_match + - SAUCE: apparmor4.0.0 [06/87]: LSM stacking v39: LSM: Add lsmblob_to_secctx + hook + - SAUCE: apparmor4.0.0 [07/87]: LSM stacking v39: Audit: maintain an lsmblob + in audit_context + - SAUCE: apparmor4.0.0 [08/87]: LSM stacking v39: LSM: Use lsmblob in + security_ipc_getsecid + - SAUCE: apparmor4.0.0 [09/87]: LSM stacking v39: Audit: Update shutdown LSM + data + - SAUCE: apparmor4.0.0 [10/87]: LSM stacking v39: LSM: Use lsmblob in + security_current_getsecid + - SAUCE: apparmor4.0.0 [11/87]: LSM stacking v39: LSM: Use lsmblob in + security_inode_getsecid + - SAUCE: apparmor4.0.0 [12/87]: LSM stacking v39: Audit: use an lsmblob in + audit_names + - SAUCE: apparmor4.0.0 [13/87]: LSM stacking v39: LSM: Create new + security_cred_getlsmblob LSM hook + - SAUCE: apparmor4.0.0 [14/87]: LSM stacking v39: Audit: Change context data + from secid to lsmblob + - SAUCE: apparmor4.0.0 [15/87]: LSM stacking v39: Netlabel: Use lsmblob for + audit data + - SAUCE: apparmor4.0.0 [16/87]: LSM stacking v39: LSM: Ensure the correct LSM + context releaser + - SAUCE: apparmor4.0.0 [17/87]: LSM stacking v39: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [18/87]: LSM stacking v39: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [19/87]: LSM stacking v39: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [20/87]: LSM stacking v39: LSM: Use lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [21/87]: LSM stacking v39: LSM: + security_lsmblob_to_secctx module selection + - SAUCE: apparmor4.0.0 [22/87]: LSM stacking v39: Audit: Create audit_stamp + structure + - SAUCE: apparmor4.0.0 [23/87]: LSM stacking v39: Audit: Allow multiple + records in an audit_buffer + - SAUCE: apparmor4.0.0 [24/87]: LSM stacking v39: Audit: Add record for + multiple task security contexts + - SAUCE: apparmor4.0.0 [25/87]: LSM stacking v39: audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor4.0.0 [26/87]: LSM stacking v39: Audit: Add record for + multiple object contexts + - SAUCE: apparmor4.0.0 [27/87]: LSM stacking v39: LSM: Remove unused + lsmcontext_init() + - SAUCE: apparmor4.0.0 [28/87]: LSM stacking v39: LSM: Improve logic in + security_getprocattr + - SAUCE: apparmor4.0.0 [29/87]: LSM stacking v39: LSM: secctx provider check + on release + - SAUCE: apparmor4.0.0 [31/87]: LSM stacking v39: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [32/87]: LSM stacking v39: LSM: Identify which LSM + handles the context string + - SAUCE: apparmor4.0.0 [33/87]: LSM stacking v39: AppArmor: Remove the + exclusive flag + - SAUCE: apparmor4.0.0 [34/87]: LSM stacking v39: LSM: Add mount opts blob + size tracking + - SAUCE: apparmor4.0.0 [35/87]: LSM stacking v39: LSM: allocate mnt_opts blobs + instead of module specific data + - SAUCE: apparmor4.0.0 [36/87]: LSM stacking v39: LSM: Infrastructure + management of the key security blob + - SAUCE: apparmor4.0.0 [37/87]: LSM stacking v39: LSM: Infrastructure + management of the mnt_opts security blob + - SAUCE: apparmor4.0.0 [38/87]: LSM stacking v39: LSM: Correct handling of + ENOSYS in inode_setxattr + - SAUCE: apparmor4.0.0 [39/87]: LSM stacking v39: LSM: Remove lsmblob + scaffolding + - SAUCE: apparmor4.0.0 [40/87]: LSM stacking v39: LSM: Allow reservation of + netlabel + - SAUCE: apparmor4.0.0 [41/87]: LSM stacking v39: LSM: restrict + security_cred_getsecid() to a single LSM + - SAUCE: apparmor4.0.0 [42/87]: LSM stacking v39: Smack: Remove + LSM_FLAG_EXCLUSIVE + - SAUCE: apparmor4.0.0 [43/87]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [12/95]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [44/87]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [45/87]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [46/87]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [47/87]: af_unix mediation + - SAUCE: apparmor4.0.0 [48/87]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [49/87]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [50/87]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [51/87]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [52/87]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [53/87]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [54/87]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [55/87]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [56/87]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [57/87]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [58/87]: prompt - fix caching + - SAUCE: apparmor4.0.0 [59/87]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [60/87]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [61/87]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [62/87]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [63/87]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [64/87]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [65/87] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [69/87]: add io_uring mediation + - SAUCE: apparmor4.0.0 [70/87]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [71/87]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [72/87]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [73/87]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [74/87]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [75/87]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [76/87]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [77/87]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [78/87]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [79/87]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [80/87]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [81/87]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [82/87]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [83/87]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [84/87]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [85/87]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [86/87]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [87/87]: fixup notify + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [66/87]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [67/87]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [68/87]: userns - make it so special unconfined + profiles can mediate user namespaces + + -- Paolo Pisati Thu, 08 Feb 2024 12:05:44 +0100 + +linux (6.8.0-6.6) noble; urgency=medium + + * noble/linux: 6.8.0-6.6 -proposed tracker (LP: #2052592) + + * Packaging resync (LP: #1786013) + - debian.master/dkms-versions -- update from kernel-versions + (main/d2024.02.07) + - [Packaging] update variants + + * FIPS kernels should default to fips mode (LP: #2049082) + - SAUCE: Enable fips mode by default, in FIPS kernels only + + * Fix snapcraftyaml.yaml for jammy:linux-raspi (LP: #2051468) + - [Packaging] Remove old snapcraft.yaml + + * Azure: Fix regression introduced in LP: #2045069 (LP: #2052453) + - hv_netvsc: Register VF in netvsc_probe if NET_DEVICE_REGISTER missed + + * Miscellaneous Ubuntu changes + - [Packaging] Remove in-tree abi checks + - [Packaging] drop abi files with clean + - [Packaging] Remove do_full_source variable (fixup) + - [Packaging] Remove update-dkms-versions and move dkms-versions + - [Config] updateconfigs following v6.8-rc3 rebase + - [packaging] rename to linux + - [packaging] rebase on v6.8-rc3 + - [packaging] disable signing for ppc64el + + * Rebase on v6.8-rc3 + + -- Paolo Pisati Wed, 07 Feb 2024 15:13:52 +0100 + +linux (6.8.0-5.5) noble; urgency=medium + + * noble/linux-unstable: 6.8.0-5.5 -proposed tracker (LP: #2052136) + + * Miscellaneous upstream changes + - Revert "mm/sparsemem: fix race in accessing memory_section->usage" + + -- Paolo Pisati Fri, 02 Feb 2024 12:59:09 +0100 + +linux-unstable (6.8.0-4.4) noble; urgency=medium + + * noble/linux-unstable: 6.8.0-4.4 -proposed tracker (LP: #2051502) + + * Migrate from fbdev drivers to simpledrm and DRM fbdev emulation layer + (LP: #1965303) + - [Config] enable simpledrm and DRM fbdev emulation layer + + * Miscellaneous Ubuntu changes + - [Config] toolchain update + + * Miscellaneous upstream changes + - rust: upgrade to Rust 1.75.0 + + -- Paolo Pisati Mon, 29 Jan 2024 14:49:49 +0100 + +linux-unstable (6.8.0-3.3) noble; urgency=medium + + * noble/linux-unstable: 6.8.0-3.3 -proposed tracker (LP: #2051488) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [43/87]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [12/95]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [44/87]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [45/87]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [46/87]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [47/87]: af_unix mediation + - SAUCE: apparmor4.0.0 [48/87]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [49/87]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [50/87]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [51/87]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [52/87]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [53/87]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [54/87]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [55/87]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [56/87]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [57/87]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [58/87]: prompt - fix caching + - SAUCE: apparmor4.0.0 [59/87]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [60/87]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [61/87]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [62/87]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [63/87]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [64/87]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [69/87]: add io_uring mediation + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * apparmor restricts read access of user namespace mediation sysctls to root + (LP: #2040194) + - SAUCE: apparmor4.0.0 [73/87]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + + * AppArmor spams kernel log with assert when auditing (LP: #2040192) + - SAUCE: apparmor4.0.0 [72/87]: apparmor: fix request field from a prompt + reply that denies all access + + * apparmor notification files verification (LP: #2040250) + - SAUCE: apparmor4.0.0 [71/87]: apparmor: fix notification header size + + * apparmor oops when racing to retrieve a notification (LP: #2040245) + - SAUCE: apparmor4.0.0 [70/87]: apparmor: fix oops when racing to retrieve + notification + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [66/87]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [67/87]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [68/87]: userns - make it so special unconfined + profiles can mediate user namespaces + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor4.0.0 [01/87]: LSM stacking v39: integrity: disassociate + ima_filter_rule from security_audit_rule + - SAUCE: apparmor4.0.0 [02/87]: LSM stacking v39: SM: Infrastructure + management of the sock security + - SAUCE: apparmor4.0.0 [03/87]: LSM stacking v39: LSM: Add the lsmblob data + structure. + - SAUCE: apparmor4.0.0 [04/87]: LSM stacking v39: IMA: avoid label collisions + with stacked LSMs + - SAUCE: apparmor4.0.0 [05/87]: LSM stacking v39: LSM: Use lsmblob in + security_audit_rule_match + - SAUCE: apparmor4.0.0 [06/87]: LSM stacking v39: LSM: Add lsmblob_to_secctx + hook + - SAUCE: apparmor4.0.0 [07/87]: LSM stacking v39: Audit: maintain an lsmblob + in audit_context + - SAUCE: apparmor4.0.0 [08/87]: LSM stacking v39: LSM: Use lsmblob in + security_ipc_getsecid + - SAUCE: apparmor4.0.0 [09/87]: LSM stacking v39: Audit: Update shutdown LSM + data + - SAUCE: apparmor4.0.0 [10/87]: LSM stacking v39: LSM: Use lsmblob in + security_current_getsecid + - SAUCE: apparmor4.0.0 [11/87]: LSM stacking v39: LSM: Use lsmblob in + security_inode_getsecid + - SAUCE: apparmor4.0.0 [12/87]: LSM stacking v39: Audit: use an lsmblob in + audit_names + - SAUCE: apparmor4.0.0 [13/87]: LSM stacking v39: LSM: Create new + security_cred_getlsmblob LSM hook + - SAUCE: apparmor4.0.0 [14/87]: LSM stacking v39: Audit: Change context data + from secid to lsmblob + - SAUCE: apparmor4.0.0 [15/87]: LSM stacking v39: Netlabel: Use lsmblob for + audit data + - SAUCE: apparmor4.0.0 [16/87]: LSM stacking v39: LSM: Ensure the correct LSM + context releaser + - SAUCE: apparmor4.0.0 [17/87]: LSM stacking v39: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [18/87]: LSM stacking v39: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [19/87]: LSM stacking v39: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [20/87]: LSM stacking v39: LSM: Use lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [21/87]: LSM stacking v39: LSM: + security_lsmblob_to_secctx module selection + - SAUCE: apparmor4.0.0 [22/87]: LSM stacking v39: Audit: Create audit_stamp + structure + - SAUCE: apparmor4.0.0 [23/87]: LSM stacking v39: Audit: Allow multiple + records in an audit_buffer + - SAUCE: apparmor4.0.0 [24/87]: LSM stacking v39: Audit: Add record for + multiple task security contexts + - SAUCE: apparmor4.0.0 [25/87]: LSM stacking v39: audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor4.0.0 [26/87]: LSM stacking v39: Audit: Add record for + multiple object contexts + - SAUCE: apparmor4.0.0 [27/87]: LSM stacking v39: LSM: Remove unused + lsmcontext_init() + - SAUCE: apparmor4.0.0 [28/87]: LSM stacking v39: LSM: Improve logic in + security_getprocattr + - SAUCE: apparmor4.0.0 [29/87]: LSM stacking v39: LSM: secctx provider check + on release + - SAUCE: apparmor4.0.0 [30/87]: LSM stacking v39: LSM: Single calls in + socket_getpeersec hooks + - SAUCE: apparmor4.0.0 [31/87]: LSM stacking v39: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [32/87]: LSM stacking v39: LSM: Identify which LSM + handles the context string + - SAUCE: apparmor4.0.0 [33/87]: LSM stacking v39: AppArmor: Remove the + exclusive flag + - SAUCE: apparmor4.0.0 [34/87]: LSM stacking v39: LSM: Add mount opts blob + size tracking + - SAUCE: apparmor4.0.0 [35/87]: LSM stacking v39: LSM: allocate mnt_opts blobs + instead of module specific data + - SAUCE: apparmor4.0.0 [36/87]: LSM stacking v39: LSM: Infrastructure + management of the key security blob + - SAUCE: apparmor4.0.0 [37/87]: LSM stacking v39: LSM: Infrastructure + management of the mnt_opts security blob + - SAUCE: apparmor4.0.0 [38/87]: LSM stacking v39: LSM: Correct handling of + ENOSYS in inode_setxattr + - SAUCE: apparmor4.0.0 [39/87]: LSM stacking v39: LSM: Remove lsmblob + scaffolding + - SAUCE: apparmor4.0.0 [40/87]: LSM stacking v39: LSM: Allow reservation of + netlabel + - SAUCE: apparmor4.0.0 [41/87]: LSM stacking v39: LSM: restrict + security_cred_getsecid() to a single LSM + - SAUCE: apparmor4.0.0 [42/87]: LSM stacking v39: Smack: Remove + LSM_FLAG_EXCLUSIVE + - SAUCE: apparmor4.0.0 [65/87] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [74/87]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [75/87]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [76/87]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [77/87]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [78/87]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [79/87]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [80/87]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [81/87]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [82/87]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [83/87]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [84/87]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [85/87]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [86/87]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [87/87]: fixup notify + - [Config] updateconfigs following v6.8-rc2 rebase + + -- Paolo Pisati Mon, 29 Jan 2024 08:59:32 +0100 + +linux-unstable (6.8.0-2.2) noble; urgency=medium + + * noble/linux-unstable: 6.8.0-2.2 -proposed tracker (LP: #2051110) + + * Miscellaneous Ubuntu changes + - [Config] toolchain update + - [Config] enable Rust + + -- Paolo Pisati Wed, 24 Jan 2024 13:10:07 +0100 + +linux-unstable (6.8.0-1.1) noble; urgency=medium + + * noble/linux-unstable: 6.8.0-1.1 -proposed tracker (LP: #2051102) + + * Miscellaneous Ubuntu changes + - [packaging] move to v6.8-rc1 + - [Config] updateconfigs following v6.8-rc1 rebase + - SAUCE: export file_close_fd() instead of close_fd_get_file() + - SAUCE: cpufreq: s/strlcpy/strscpy/ + - debian/dkms-versions -- temporarily disable zfs dkms + - debian/dkms-versions -- temporarily disable ipu6 and isvsc dkms + - debian/dkms-versions -- temporarily disable v4l2loopback + + -- Paolo Pisati Wed, 24 Jan 2024 10:48:37 +0100 + +linux-unstable (6.8.0-0.0) noble; urgency=medium + + * Empty entry. + + -- Paolo Pisati Tue, 23 Jan 2024 11:36:40 +0100 diff --git a/debian.qcom-x1e/config/README.rst b/debian.qcom-x1e/config/README.rst new file mode 100644 index 00000000000000..751ce7f3b284d4 --- /dev/null +++ b/debian.qcom-x1e/config/README.rst @@ -0,0 +1,185 @@ +================== +Config Annotations +================== + +:Author: Andrea Righi + +Overview +======== + +Each Ubuntu kernel needs to maintain its own .config for each supported +architecture and each flavour. + +Every time a new patch is applied or a kernel is rebased on top of a new +one, we need to update the .config's accordingly (config options can be +added, removed and also renamed). + +So, we need to make sure that some critical config options are always +matching the desired value in order to have a functional kernel. + +State of the art +================ + +At the moment configs are maintained as a set of Kconfig chunks (inside +`debian./config/`): a global one, plus per-arch / per-flavour +chunks. + +In addition to that, we need to maintain also a file called +'annotations'; the purpose of this file is to make sure that some +critical config options are not silently removed or changed when the +real .config is re-generated (for example after a rebase or after +applying a new set of patches). + +The main problem with this approach is that, often, we have duplicate +information that is stored both in the Kconfig chunks *and* in the +annotations files and, at the same time, the whole .config's information +is distributed between Kconfig chunks and annotations, making it hard to +maintain, review and manage in general. + +Proposed solution +================= + +The proposed solution is to store all the config information into the +"annotations" format and get rid of the config chunks (basically the +real .config's can be produced "compiling" annotations). + +Implementation +============== + +To help the management of the annotations an helper script is provided +(`debian/scripts/misc/annotations`): + +``` +usage: annotations [-h] [--version] [--file FILE] [--arch ARCH] [--flavour FLAVOUR] [--config CONFIG] + (--query | --export | --import FILE | --update FILE | --check FILE) + +Manage Ubuntu kernel .config and annotations + +options: + -h, --help show this help message and exit + --version, -v show program's version number and exit + --file FILE, -f FILE Pass annotations or .config file to be parsed + --arch ARCH, -a ARCH Select architecture + --flavour FLAVOUR, -l FLAVOUR + Select flavour (default is "generic") + --config CONFIG, -c CONFIG + Select a specific config option + +Action: + --query, -q Query annotations + --export, -e Convert annotations to .config format + --import FILE, -i FILE + Import a full .config for a specific arch and flavour into annotations + --update FILE, -u FILE + Import a partial .config into annotations (only resync configs specified in FILE) + --check FILE, -k FILE + Validate kernel .config with annotations +``` + +This script allows to query config settings (per arch/flavour/config), +export them into the Kconfig format (generating the real .config files) +and check if the final .config matches the rules defined in the +annotations. + +Examples (annotations is defined as an alias to `debian/scripts/annotations`): + + - Show settings for `CONFIG_DEBUG_INFO_BTF` for master kernel across all the + supported architectures and flavours: + +``` +$ annotations --query --config CONFIG_DEBUG_INFO_BTF +{ + "policy": { + "amd64": "y", + "arm64": "y", + "armhf": "n", + "ppc64el": "y", + "riscv64": "y", + "s390x": "y" + }, + "note": "'Needs newer pahole for armhf'" +} +``` + + - Dump kernel .config for arm64 and flavour generic-64k: + +``` +$ annotations --arch arm64 --flavour generic-64k --export +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_COMPAT=y +... +``` + + - Update annotations file with a new kernel .config for amd64 flavour + generic: + +``` +$ annotations --arch amd64 --flavour generic --import build/.config +``` + +Moreover, an additional kernelconfig commands are provided +(via debian/rules targets): + - `migrateconfigs`: automatically merge all the previous configs into + annotations (local changes still need to be committed) + +Annotations headers +=================== + +The main annotations file should contain a header to define the architectures +and flavours that are supported. + +Here is the format of the header for the generic kernel: +``` +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 armhf ppc64el riscv64 s390x +# FLAVOUR: amd64-generic arm64-generic arm64-generic-64k armhf-generic armhf-generic-lpae ppc64el-generic riscv64-generic s390x-generic + +``` + +Example header of a derivative (linux-aws): +``` +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 +# FLAVOUR: amd64-aws arm64-aws +# FLAVOUR_DEP: {'amd64-aws': 'amd64-generic', 'arm64-aws': 'arm64-generic'} + +include "../../debian.master/config/annotations" + +# Below you can define only the specific linux-aws configs that differ from linux generic + +``` + +Pros and Cons +============= + + Pros: + - avoid duplicate information in .config's and annotations + - allow to easily define groups of config settings (for a specific + environment or feature, such as annotations.clouds, annotations.ubuntu, + annotations.snapd, etc.) + - config options are more accessible, easy to change and review + - we can easily document how config options are managed (and external + contributors won't be discouraged anymore when they need to to change a + config option) + + Cons: + - potential regressions: the new tool/scripts can have potential bugs, + so we could experience regressions due to some missed config changes + - kernel team need to understand the new process (even if everything + is transparent, kernel cranking process is the same, there might be + corner cases that need to be addressed and resolved manually) + +TODO +==== + + - Migrate all flavour and arch definitions into annotations (rather + than having this information defined in multiple places inside + debian/scripts); right now this information is "partially" migrated, + meaning that we need to define arches and flavours in the headers + section of annotations (so that the annotations tool can figure out + the list of supported arches and flavours), but arches and flavours + are still defined elsewhere, ideally we would like to have arches and + flavours defined only in one place: annotations. diff --git a/debian.qcom-x1e/config/annotations b/debian.qcom-x1e/config/annotations new file mode 100644 index 00000000000000..d7bd6b656785ef --- /dev/null +++ b/debian.qcom-x1e/config/annotations @@ -0,0 +1,13609 @@ +# Menu: HEADER +# FORMAT: 4 +# ARCH: arm64 +# FLAVOUR: arm64-qcom-x1e + +CONFIG_ACCESSIBILITY policy<{'arm64': 'y'}> +CONFIG_ACCESSIBILITY note<'LP: #1967702'> + +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE policy<{'arm64': 'y'}> +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE note<'LP: #2051835'> + +CONFIG_ARCH_MMAP_RND_BITS policy<{'arm64': '18'}> +CONFIG_ARCH_MMAP_RND_BITS note<'LP: #1983357'> + +CONFIG_ARCH_MMAP_RND_COMPAT_BITS policy<{'arm64': '16'}> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS note<'LP: #1983357'> + +CONFIG_ARCH_ROCKCHIP policy<{'arm64': 'y'}> +CONFIG_ARCH_ROCKCHIP note<'LP: #1825222'> + +CONFIG_ARM64_ERRATUM_843419 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_843419 note<'LP: #1647793'> + +CONFIG_ARM64_ERRATUM_858921 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_858921 note<'LP: #1675509'> + +CONFIG_ARMV8_DEPRECATED policy<{'arm64': 'y'}> +CONFIG_ARMV8_DEPRECATED note<'LP: #1545542'> + +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT note<'LP: #1845820'> + +CONFIG_ASYMMETRIC_KEY_TYPE policy<{'arm64': 'y'}> +CONFIG_ASYMMETRIC_KEY_TYPE note<'module signing'> + +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE policy<{'arm64': 'y'}> +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE note<'module signing'> + +CONFIG_ATA_PIIX policy<{'arm64': 'm'}> +CONFIG_ATA_PIIX note<'LP: #1627324'> + +CONFIG_BINFMT_SCRIPT policy<{'arm64': 'y'}> +CONFIG_BINFMT_SCRIPT note<'required if init is a shell script such as in initramfs-tools'> + +CONFIG_BLK_DEV_DM policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_DM note<'LP: #560717'> + +CONFIG_BLK_DEV_NVME policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_NVME note<'LP: #1759893'> + +CONFIG_BLK_DEV_RAM policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_RAM note<'LP: #1593293'> + +CONFIG_BLK_DEV_RAM_SIZE policy<{'arm64': '65536'}> +CONFIG_BLK_DEV_RAM_SIZE note<'Ramdisk size should be a minimum of 64M'> + +CONFIG_BLK_DEV_SD policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_SD note<'LP: #1627330'> + +CONFIG_BLK_DEV_SR policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_SR note<'LP: #1627330'> + +CONFIG_BLK_DEV_THROTTLING policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_THROTTLING note<'CGROUP disk consumption control'> + +CONFIG_BPF_UNPRIV_DEFAULT_OFF policy<{'arm64': 'y'}> +CONFIG_BPF_UNPRIV_DEFAULT_OFF note<'security reason'> + +CONFIG_CHR_DEV_SG policy<{'arm64': 'y'}> +CONFIG_CHR_DEV_SG note<'not autoloadable'> + +CONFIG_CMA policy<{'arm64': 'y'}> +CONFIG_CMA note<'LP: #1803206'> + +CONFIG_CMA_SIZE_MBYTES policy<{'arm64': '32'}> +CONFIG_CMA_SIZE_MBYTES note<'LP: #1823753'> + +CONFIG_CONSOLE_LOGLEVEL_QUIET policy<{'arm64': '3'}> +CONFIG_CONSOLE_LOGLEVEL_QUIET note<'LP: #2049390'> + +CONFIG_CP15_BARRIER_EMULATION policy<{'arm64': 'y'}> +CONFIG_CP15_BARRIER_EMULATION note<'LP: #1545542'> + +CONFIG_CPUFREQ_DT policy<{'arm64': 'y'}> +CONFIG_CPUFREQ_DT note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_CONSERVATIVE policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_GOV_CONSERVATIVE note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_ONDEMAND policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_GOV_ONDEMAND note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_PERFORMANCE policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_GOV_PERFORMANCE note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_POWERSAVE policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_GOV_POWERSAVE note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_USERSPACE policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_GOV_USERSPACE note<'not autoloadable'> + +CONFIG_CPU_FREQ_STAT policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_STAT note<'dependancy of boot essential'> + +CONFIG_CRASH_DUMP policy<{'arm64': 'y'}> +CONFIG_CRASH_DUMP note<'LP: #1363180'> + +CONFIG_CRYPTO_SHA512 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_SHA512 note<'module signing'> + +CONFIG_DEBUG_FS policy<{'arm64': 'y'}> +CONFIG_DEBUG_FS note<'required debug option'> + +CONFIG_DEBUG_KERNEL policy<{'arm64': 'y'}> +CONFIG_DEBUG_KERNEL note<'required debug option'> + +CONFIG_DEFAULT_MMAP_MIN_ADDR policy<{'arm64': '32768'}> +CONFIG_DEFAULT_MMAP_MIN_ADDR note<'LP: #1531327'> + +CONFIG_DEVTMPFS policy<{'arm64': 'y'}> +CONFIG_DEVTMPFS note<'upstart requirement'> + +CONFIG_DEVTMPFS_MOUNT policy<{'arm64': 'y'}> +CONFIG_DEVTMPFS_MOUNT note<'upstart requirement'> + +CONFIG_DMA_CMA policy<{'arm64': 'y'}> +CONFIG_DMA_CMA note<'LP: #1803206'> + +CONFIG_DRM policy<{'arm64': 'y'}> +CONFIG_DRM note<'LP: #1965303'> + +CONFIG_DRM_HISI_HIBMC policy<{'arm64': 'm'}> +CONFIG_DRM_HISI_HIBMC note<'LP: #1762940'> + +CONFIG_DRM_MGAG200 policy<{'arm64': 'm'}> +CONFIG_DRM_MGAG200 note<'LP: #1693337'> + +CONFIG_DRM_SIMPLEDRM policy<{'arm64': 'y'}> +CONFIG_DRM_SIMPLEDRM note<'LP: #1965303'> + +CONFIG_DVB_DUMMY_FE policy<{'arm64': 'm'}> +CONFIG_DVB_DUMMY_FE note<'expert use only'> + +CONFIG_ECRYPT_FS policy<{'arm64': 'y'}> +CONFIG_ECRYPT_FS note<'not autoloadable'> + +CONFIG_EFIVAR_FS policy<{'arm64': 'y'}> +CONFIG_EFIVAR_FS note<'needed for variable EFI update'> + +CONFIG_EFI_ZBOOT policy<{'arm64': 'y'}> +CONFIG_EFI_ZBOOT note<'LP: #2002226'> + +CONFIG_EVM policy<{'arm64': 'y'}> +CONFIG_EVM note<'LP: #1643652'> + +CONFIG_EVM_ATTR_FSUUID policy<{'arm64': 'y'}> +CONFIG_EVM_ATTR_FSUUID note<'LP: #1643652'> + +CONFIG_FHANDLE policy<{'arm64': 'y'}> +CONFIG_FHANDLE note<'LP: #1412543'> + +CONFIG_FUSE_FS policy<{'arm64': 'y'}> +CONFIG_FUSE_FS note<'not autoloadable'> + +CONFIG_GPIO_CDEV_V1 policy<{'arm64': 'y'}> +CONFIG_GPIO_CDEV_V1 note<'LP: #1953613'> + +CONFIG_HOTPLUG_PCI_PCIE policy<{'arm64': 'y'}> +CONFIG_HOTPLUG_PCI_PCIE note<'LP: #1374440'> + +CONFIG_HOTPLUG_PCI_SHPC policy<{'arm64': 'y'}> +CONFIG_HOTPLUG_PCI_SHPC note<'LP: #1374440'> + +CONFIG_HZ_1000 policy<{'arm64': 'y'}> +CONFIG_HZ_1000 note<'LP: #2051342'> + +CONFIG_I2C_CHARDEV policy<{'arm64': 'y'}> +CONFIG_I2C_CHARDEV note<'LP: #1417032'> + +CONFIG_IDLE_PAGE_TRACKING policy<{'arm64': 'y'}> +CONFIG_IDLE_PAGE_TRACKING note<'is there a cost associated with this?'> + +CONFIG_IMA policy<{'arm64': 'y'}> +CONFIG_IMA note<'LP: #1643652'> + +CONFIG_IMA_APPRAISE policy<{'arm64': 'y'}> +CONFIG_IMA_APPRAISE note<'LP: #1643652'> + +CONFIG_IMA_DEFAULT_HASH_SHA256 policy<{'arm64': 'y'}> +CONFIG_IMA_DEFAULT_HASH_SHA256 note<'LP: #2041735'> + +CONFIG_IMA_KEXEC policy<{'arm64': 'y'}> +CONFIG_IMA_KEXEC note<'LP: #1643652'> + +CONFIG_INPUT_UINPUT policy<{'arm64': 'y'}> +CONFIG_INPUT_UINPUT note<'LP: #584812'> + +CONFIG_IOMMU_DEFAULT_DMA_STRICT policy<{'arm64': 'y'}> +CONFIG_IOMMU_DEFAULT_DMA_STRICT note<'LP: #2071471'> + +CONFIG_IPV6 policy<{'arm64': 'y'}> +CONFIG_IPV6 note<'if this is a module we get a module load for every ipv6 packet'> + +CONFIG_KVM policy<{'arm64': 'y'}> +CONFIG_KVM note<'LP: #1532886'> + +CONFIG_LATENCYTOP policy<{'arm64': 'y'}> +CONFIG_LATENCYTOP note<'LP: #2051342'> + +CONFIG_LRU_GEN policy<{'arm64': 'y'}> +CONFIG_LRU_GEN note<'{Enable multi-gen LRU by default - LP: #2023629}'> + +CONFIG_LRU_GEN_ENABLED policy<{'arm64': 'y'}> +CONFIG_LRU_GEN_ENABLED note<'{Enable multi-gen LRU by default - LP: #2023629}'> + +CONFIG_MFD_SM501 policy<{'arm64': 'm'}> +CONFIG_MFD_SM501 note<'boot essential on OMAP4'> + +CONFIG_MFD_TPS65217 policy<{'arm64': 'm'}> +CONFIG_MFD_TPS65217 note<'boot essential on AM335x'> + +CONFIG_MMC_BLOCK policy<{'arm64': 'y'}> +CONFIG_MMC_BLOCK note<'boot essential on armhf/arm64'> + +CONFIG_MMC_SDHCI policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI note<'installation essential on omap/highbank'> + +CONFIG_MMC_SDHCI_PLTFM policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_PLTFM note<'boot essential on highbank'> + +CONFIG_MODULE_COMPRESS_ZSTD policy<{'arm64': 'y'}> +CONFIG_MODULE_COMPRESS_ZSTD note<'LP: #2028568'> + +CONFIG_MODVERSIONS policy<{'arm64': 'y'}> +CONFIG_MODVERSIONS note<'required as we have a livepatch/drivers modules signing key'> + +CONFIG_MTD policy<{'arm64': 'm'}> +CONFIG_MTD note<'boot essential on arm'> + +CONFIG_MTD_BLOCK policy<{'arm64': 'm'}> +CONFIG_MTD_BLOCK note<'boot essential on arm'> + +CONFIG_MTD_OF_PARTS policy<{'arm64': 'm'}> +CONFIG_MTD_OF_PARTS note<'boot essential on arm'> + +CONFIG_MTD_RAW_NAND policy<{'arm64': 'm'}> +CONFIG_MTD_RAW_NAND note<'boot essential on arm'> + +CONFIG_NETWORK_PHY_TIMESTAMPING policy<{'arm64': 'y'}> +CONFIG_NETWORK_PHY_TIMESTAMPING note<'LP: #1785816'> + +CONFIG_NET_9P policy<{'arm64': 'm'}> +CONFIG_NET_9P note<'LP: #1557994'> + +CONFIG_NET_DROP_MONITOR policy<{'arm64': 'y'}> +CONFIG_NET_DROP_MONITOR note<'LP: #1660634'> + +CONFIG_NET_SWITCHDEV policy<{'arm64': 'y'}> +CONFIG_NET_SWITCHDEV note<'updated to y for s390x starting with focal'> + +CONFIG_NET_VENDOR_EMULEX policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_EMULEX note<'LP: #1543165'> + +CONFIG_NLS policy<{'arm64': 'y'}> +CONFIG_NLS note<'dependancy of boot essential'> + +CONFIG_NOP_USB_XCEIV policy<{'arm64': 'm'}> +CONFIG_NOP_USB_XCEIV note<'boot essential on omap/highbank'> + +CONFIG_NO_HZ_FULL policy<{'arm64': 'y'}> +CONFIG_NO_HZ_FULL note<'LP: #2051342'> + +CONFIG_NR_CPUS policy<{'arm64': '512'}> +CONFIG_NR_CPUS note<'LP: #2042897 (arm64), LP: #1967889 (riscv64), LP: #1864198 (s390x)'> + +CONFIG_NUMA policy<{'arm64': 'y'}> +CONFIG_NUMA note<'LP: #1557690'> + +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED policy<{'arm64': 'y'}> +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED note<'LP: #1557690'> + +CONFIG_NVMEM policy<{'arm64': 'y'}> +CONFIG_NVMEM note<'LP: #1543165'> + +CONFIG_N_GSM policy<{'arm64': 'm'}> +CONFIG_N_GSM note<'LP: #1404670'> + +CONFIG_OSNOISE_TRACER policy<{'arm64': 'y'}> +CONFIG_OSNOISE_TRACER note<'This enables the osnoise tracer for the kernel. LP: #2018591'> + +CONFIG_PAGE_POISONING policy<{'arm64': 'y'}> +CONFIG_PAGE_POISONING note<'LP: #1783651'> + +CONFIG_PCIEASPM_DEFAULT policy<{'arm64': 'y'}> +CONFIG_PCIEASPM_DEFAULT note<'LP: #1398544'> + +CONFIG_PCIEPORTBUS policy<{'arm64': 'y'}> +CONFIG_PCIEPORTBUS note<'LP: #1665404'> + +CONFIG_PCI_MESON policy<{'arm64': 'm'}> +CONFIG_PCI_MESON note<'LP: #2007745'> + +CONFIG_PM policy<{'arm64': 'y'}> +CONFIG_PM note<'LP: #1867753'> + +CONFIG_PREEMPT_DYNAMIC policy<{'arm64': 'y'}> +CONFIG_PREEMPT_DYNAMIC note<'LP: #2051342'> + +CONFIG_QCOM_QDF2400_ERRATUM_0065 policy<{'arm64': 'y'}> +CONFIG_QCOM_QDF2400_ERRATUM_0065 note<'LP: #1672486'> + +CONFIG_RCU_LAZY policy<{'arm64': 'y'}> +CONFIG_RCU_LAZY note<'LP: #2051342'> + +CONFIG_RCU_LAZY_DEFAULT_OFF policy<{'arm64': 'y'}> +CONFIG_RCU_LAZY_DEFAULT_OFF note<'LP: #2051342'> + +CONFIG_RCU_NOCB_CPU policy<{'arm64': 'y'}> +CONFIG_RCU_NOCB_CPU note<'LP: #2051342'> + +CONFIG_REGULATOR_FIXED_VOLTAGE policy<{'arm64': 'm'}> +CONFIG_REGULATOR_FIXED_VOLTAGE note<'boot essential on arm and the Allwinner D1 RISC-V SoC'> + +CONFIG_REGULATOR_TPS65217 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS65217 note<'boot essential on AM335x'> + +CONFIG_SATA_AHCI_PLATFORM policy<{'arm64': 'm'}> +CONFIG_SATA_AHCI_PLATFORM note<'boot essential on highbank'> + +CONFIG_SCSI_VIRTIO policy<{'arm64': 'y'}> +CONFIG_SCSI_VIRTIO note<'enable initrdless boot in VMs for ease of use, cloud-kernel parity and disaster recovery, LP: #1685291'> + +CONFIG_SECURITY_SAFESETID policy<{'arm64': 'y'}> +CONFIG_SECURITY_SAFESETID note<'LP: #1845391'> + +CONFIG_SERIAL_8250_DW policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_DW note<'several RISC-V boards needs this for console output'> + +CONFIG_SERIAL_DEV_BUS policy<{'arm64': 'y'}> +CONFIG_SERIAL_DEV_BUS note<'LP: #1739939'> + +CONFIG_SERIAL_DEV_CTRL_TTYPORT policy<{'arm64': 'y'}> +CONFIG_SERIAL_DEV_CTRL_TTYPORT note<'LP: #1739939'> + +CONFIG_SETEND_EMULATION policy<{'arm64': 'y'}> +CONFIG_SETEND_EMULATION note<'LP: #1545542'> + +CONFIG_SND policy<{'arm64': 'm'}> +CONFIG_SND note<'not autoloadable on omap'> + +CONFIG_SND_SOC policy<{'arm64': 'm'}> +CONFIG_SND_SOC note<'not autoloadable on omap'> + +CONFIG_SOUND policy<{'arm64': 'm'}> +CONFIG_SOUND note<'not autoloadable on omap'> + +CONFIG_SOUNDWIRE policy<{'arm64': 'm'}> +CONFIG_SOUNDWIRE note<'LP: #1855685'> + +CONFIG_SQUASHFS policy<{'arm64': 'y'}> +CONFIG_SQUASHFS note<'LP: #1593134'> + +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU note<'LP: #1980861'> + +CONFIG_SWP_EMULATION policy<{'arm64': 'y'}> +CONFIG_SWP_EMULATION note<'LP: #1545542'> + +CONFIG_TCG_TIS_I2C_ATMEL policy<{'arm64': 'm'}> +CONFIG_TCG_TIS_I2C_ATMEL note<'LP: #1643652'> + +CONFIG_TCG_TIS_I2C_INFINEON policy<{'arm64': 'm'}> +CONFIG_TCG_TIS_I2C_INFINEON note<'LP: #1643652'> + +CONFIG_TCG_TIS_I2C_NUVOTON policy<{'arm64': 'm'}> +CONFIG_TCG_TIS_I2C_NUVOTON note<'LP: #1643652'> + +CONFIG_TCG_TPM policy<{'arm64': 'y'}> +CONFIG_TCG_TPM note<'needed for early validation'> + +CONFIG_TIMERLAT_TRACER policy<{'arm64': 'y'}> +CONFIG_TIMERLAT_TRACER note<'This enables the osnoise tracer for the kernel. LP: #2018591'> + +CONFIG_TMPFS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_TMPFS_POSIX_ACL note<'some /dev nodes require POSIX ACLs, like /dev/dsp'> + +CONFIG_TOUCHSCREEN_ELAN policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ELAN note<'LP: #1630238'> + +CONFIG_UBSAN policy<{'arm64': 'y'}> +CONFIG_UBSAN note<'LP: #1942215'> + +CONFIG_USB_EHCI_HCD policy<{'arm64': 'y'}> +CONFIG_USB_EHCI_HCD note<'ensures USB 2.0/1.1 probe ordering'> + +CONFIG_USB_EHCI_HCD_PLATFORM policy<{'arm64': 'm'}> +CONFIG_USB_EHCI_HCD_PLATFORM note<'Dont use the generic ehci/ohci code on omap, it doesnt work'> + +CONFIG_USB_MUSB_HDRC policy<{'arm64': 'm'}> +CONFIG_USB_MUSB_HDRC note<'not autoloadable on omap'> + +CONFIG_USB_SERIAL_DEBUG policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_DEBUG note<'not actually debug'> + +CONFIG_USB_UHCI_HCD policy<{'arm64': 'y'}> +CONFIG_USB_UHCI_HCD note<'ensures USB 2.0/1.1 probe ordering'> + +CONFIG_USB_XHCI_DBGCAP policy<{'arm64': 'y'}> +CONFIG_USB_XHCI_DBGCAP note<'LP: #1730832'> + +CONFIG_USB_XHCI_HCD policy<{'arm64': 'y'}> +CONFIG_USB_XHCI_HCD note<'ensures USB 2.0/1.1 probe ordering'> + +CONFIG_VFAT_FS policy<{'arm64': 'y'}> +CONFIG_VFAT_FS note<'needed on arm to ensure we can write the kernel when replacing'> + +CONFIG_VFIO policy<{'arm64': 'm'}> +CONFIG_VFIO note<'LP: #1636733'> + +CONFIG_VFIO_PCI policy<{'arm64': 'm'}> +CONFIG_VFIO_PCI note<'LP: #1636733'> + +CONFIG_VIDEO_VIMC policy<{'arm64': 'm'}> +CONFIG_VIDEO_VIMC note<'LP: #1831482'> + +CONFIG_VIRTIO_BLK policy<{'arm64': 'y'}> +CONFIG_VIRTIO_BLK note<'LP: #2030745'> + +CONFIG_VIRTIO_MMIO policy<{'arm64': 'y'}> +CONFIG_VIRTIO_MMIO note<'LP: #1557689'> + +CONFIG_VIRTIO_NET policy<{'arm64': 'y'}> +CONFIG_VIRTIO_NET note<'KVM paravirt support -- cloud-init currently racy with this as a module (LP: #2036968)'> + +CONFIG_WWAN policy<{'arm64': 'm'}> +CONFIG_WWAN note<'LP: #2033406'> + +CONFIG_X509_CERTIFICATE_PARSER policy<{'arm64': 'y'}> +CONFIG_X509_CERTIFICATE_PARSER note<'module signing'> + +CONFIG_XEN_BLKDEV_FRONTEND policy<{'arm64': 'y'}> +CONFIG_XEN_BLKDEV_FRONTEND note<'not autoloadable -- XEN paravirt support'> + +CONFIG_XEN_NETDEV_FRONTEND policy<{'arm64': 'y'}> +CONFIG_XEN_NETDEV_FRONTEND note<'not autoloadable -- XEN paravirt support'> + +CONFIG_XZ_DEC policy<{'arm64': 'y'}> +CONFIG_XZ_DEC note<'boot essential -- initramfs decompressor'> + +CONFIG_ZONE_DMA policy<{'arm64': 'y'}> +CONFIG_ZONE_DMA note<'LP: #1628523'> + + +# ---- Annotations without notes ---- + +CONFIG_64BIT policy<{'arm64': 'y'}> +CONFIG_6LOWPAN policy<{'arm64': 'm'}> +CONFIG_6LOWPAN_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST policy<{'arm64': 'n'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG policy<{'arm64': 'n'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP policy<{'arm64': 'n'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE policy<{'arm64': 'n'}> +CONFIG_6LOWPAN_GHC_ICMPV6 policy<{'arm64': 'n'}> +CONFIG_6LOWPAN_GHC_UDP policy<{'arm64': 'n'}> +CONFIG_6LOWPAN_NHC policy<{'arm64': 'm'}> +CONFIG_6LOWPAN_NHC_DEST policy<{'arm64': 'm'}> +CONFIG_6LOWPAN_NHC_FRAGMENT policy<{'arm64': 'm'}> +CONFIG_6LOWPAN_NHC_HOP policy<{'arm64': 'm'}> +CONFIG_6LOWPAN_NHC_IPV6 policy<{'arm64': 'm'}> +CONFIG_6LOWPAN_NHC_MOBILITY policy<{'arm64': 'm'}> +CONFIG_6LOWPAN_NHC_ROUTING policy<{'arm64': 'm'}> +CONFIG_6LOWPAN_NHC_UDP policy<{'arm64': 'm'}> +CONFIG_8139CP policy<{'arm64': 'm'}> +CONFIG_8139TOO policy<{'arm64': 'm'}> +CONFIG_8139TOO_8129 policy<{'arm64': 'y'}> +CONFIG_8139TOO_PIO policy<{'arm64': 'y'}> +CONFIG_8139TOO_TUNE_TWISTER policy<{'arm64': 'n'}> +CONFIG_8139_OLD_RX_RESET policy<{'arm64': 'n'}> +CONFIG_842_COMPRESS policy<{'arm64': 'm'}> +CONFIG_842_DECOMPRESS policy<{'arm64': 'm'}> +CONFIG_88PM886_GPADC policy<{'arm64': 'm'}> +CONFIG_9P_FS policy<{'arm64': 'm'}> +CONFIG_9P_FSCACHE policy<{'arm64': 'y'}> +CONFIG_9P_FS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_9P_FS_SECURITY policy<{'arm64': 'y'}> +CONFIG_A11Y_BRAILLE_CONSOLE policy<{'arm64': 'n'}> +CONFIG_A64FX_DIAG policy<{'arm64': 'y'}> +CONFIG_ABP060MG policy<{'arm64': 'm'}> +CONFIG_ABP2030PA_I2C policy<{'arm64': 'n'}> +CONFIG_ABP2030PA_SPI policy<{'arm64': 'n'}> +CONFIG_AC97_BUS policy<{'arm64': 'm'}> +CONFIG_ACORN_PARTITION policy<{'arm64': 'n'}> +CONFIG_ACPI policy<{'arm64': 'y'}> +CONFIG_ACPI_AC policy<{'arm64': 'y'}> +CONFIG_ACPI_AGDI policy<{'arm64': 'y'}> +CONFIG_ACPI_ALS policy<{'arm64': 'm'}> +CONFIG_ACPI_APEI policy<{'arm64': 'y'}> +CONFIG_ACPI_APEI_EINJ policy<{'arm64': 'm'}> +CONFIG_ACPI_APEI_EINJ_CXL policy<{'arm64': 'y'}> +CONFIG_ACPI_APEI_ERST_DEBUG policy<{'arm64': 'n'}> +CONFIG_ACPI_APEI_GHES policy<{'arm64': 'y'}> +CONFIG_ACPI_APEI_GHES_NVIDIA policy<{'arm64': 'n'}> +CONFIG_ACPI_APEI_MEMORY_FAILURE policy<{'arm64': 'y'}> +CONFIG_ACPI_APEI_PCIEAER policy<{'arm64': 'y'}> +CONFIG_ACPI_APEI_SEA policy<{'arm64': 'y'}> +CONFIG_ACPI_APMT policy<{'arm64': 'y'}> +CONFIG_ACPI_BATTERY policy<{'arm64': 'y'}> +CONFIG_ACPI_BGRT policy<{'arm64': 'y'}> +CONFIG_ACPI_BUTTON policy<{'arm64': 'y'}> +CONFIG_ACPI_CCA_REQUIRED policy<{'arm64': 'y'}> +CONFIG_ACPI_CONFIGFS policy<{'arm64': 'm'}> +CONFIG_ACPI_CONTAINER policy<{'arm64': 'y'}> +CONFIG_ACPI_CPPC_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ACPI_CPPC_CPUFREQ_FIE policy<{'arm64': 'y'}> +CONFIG_ACPI_CPPC_LIB policy<{'arm64': 'y'}> +CONFIG_ACPI_DEBUG policy<{'arm64': 'n'}> +CONFIG_ACPI_DEBUGGER policy<{'arm64': 'n'}> +CONFIG_ACPI_DOCK policy<{'arm64': 'y'}> +CONFIG_ACPI_EC policy<{'arm64': 'n'}> +CONFIG_ACPI_FAN policy<{'arm64': 'y'}> +CONFIG_ACPI_FFH policy<{'arm64': 'y'}> +CONFIG_ACPI_FPDT policy<{'arm64': 'y'}> +CONFIG_ACPI_GENERIC_GSI policy<{'arm64': 'y'}> +CONFIG_ACPI_GTDT policy<{'arm64': 'y'}> +CONFIG_ACPI_HED policy<{'arm64': 'y'}> +CONFIG_ACPI_HMAT policy<{'arm64': 'y'}> +CONFIG_ACPI_HOTPLUG_CPU policy<{'arm64': 'y'}> +CONFIG_ACPI_HOTPLUG_MEMORY policy<{'arm64': 'y'}> +CONFIG_ACPI_I2C_OPREGION policy<{'arm64': 'y'}> +CONFIG_ACPI_IORT policy<{'arm64': 'y'}> +CONFIG_ACPI_IPMI policy<{'arm64': 'm'}> +CONFIG_ACPI_MCFG policy<{'arm64': 'y'}> +CONFIG_ACPI_MDIO policy<{'arm64': 'y'}> +CONFIG_ACPI_NFIT policy<{'arm64': 'm'}> +CONFIG_ACPI_NHLT policy<{'arm64': 'y'}> +CONFIG_ACPI_NUMA policy<{'arm64': 'y'}> +CONFIG_ACPI_PCC policy<{'arm64': 'y'}> +CONFIG_ACPI_PCI_SLOT policy<{'arm64': 'y'}> +CONFIG_ACPI_PFRUT policy<{'arm64': 'm'}> +CONFIG_ACPI_PLATFORM_PROFILE policy<{'arm64': 'm'}> +CONFIG_ACPI_PPTT policy<{'arm64': 'y'}> +CONFIG_ACPI_PRMT policy<{'arm64': 'y'}> +CONFIG_ACPI_PROCESSOR policy<{'arm64': 'y'}> +CONFIG_ACPI_PROCESSOR_IDLE policy<{'arm64': 'y'}> +CONFIG_ACPI_REDUCED_HARDWARE_ONLY policy<{'arm64': 'y'}> +CONFIG_ACPI_SPCR_TABLE policy<{'arm64': 'y'}> +CONFIG_ACPI_TABLE_LIB policy<{'arm64': 'y'}> +CONFIG_ACPI_TABLE_UPGRADE policy<{'arm64': 'y'}> +CONFIG_ACPI_TAD policy<{'arm64': 'm'}> +CONFIG_ACPI_THERMAL policy<{'arm64': 'y'}> +CONFIG_ACPI_THERMAL_LIB policy<{'arm64': 'y'}> +CONFIG_ACPI_VIDEO policy<{'arm64': 'm'}> +CONFIG_ACPI_VIOT policy<{'arm64': 'y'}> +CONFIG_ACPI_WATCHDOG policy<{'arm64': 'y'}> +CONFIG_AD2S1200 policy<{'arm64': 'm'}> +CONFIG_AD2S1210 policy<{'arm64': 'm'}> +CONFIG_AD2S90 policy<{'arm64': 'm'}> +CONFIG_AD3530R policy<{'arm64': 'm'}> +CONFIG_AD3552R policy<{'arm64': 'm'}> +CONFIG_AD3552R_HS policy<{'arm64': 'm'}> +CONFIG_AD3552R_LIB policy<{'arm64': 'm'}> +CONFIG_AD4000 policy<{'arm64': 'm'}> +CONFIG_AD4030 policy<{'arm64': 'm'}> +CONFIG_AD4062 policy<{'arm64': 'n'}> +CONFIG_AD4080 policy<{'arm64': 'n'}> +CONFIG_AD4130 policy<{'arm64': 'm'}> +CONFIG_AD4134 policy<{'arm64': 'n'}> +CONFIG_AD4170_4 policy<{'arm64': 'n'}> +CONFIG_AD4691 policy<{'arm64': 'n'}> +CONFIG_AD4695 policy<{'arm64': 'm'}> +CONFIG_AD4851 policy<{'arm64': 'm'}> +CONFIG_AD5064 policy<{'arm64': 'm'}> +CONFIG_AD5110 policy<{'arm64': 'm'}> +CONFIG_AD525X_DPOT policy<{'arm64': 'm'}> +CONFIG_AD525X_DPOT_I2C policy<{'arm64': 'm'}> +CONFIG_AD525X_DPOT_SPI policy<{'arm64': 'm'}> +CONFIG_AD5272 policy<{'arm64': 'm'}> +CONFIG_AD5360 policy<{'arm64': 'm'}> +CONFIG_AD5380 policy<{'arm64': 'm'}> +CONFIG_AD5421 policy<{'arm64': 'm'}> +CONFIG_AD5446_I2C policy<{'arm64': 'n'}> +CONFIG_AD5446_SPI policy<{'arm64': 'n'}> +CONFIG_AD5449 policy<{'arm64': 'm'}> +CONFIG_AD5504 policy<{'arm64': 'm'}> +CONFIG_AD5592R policy<{'arm64': 'm'}> +CONFIG_AD5592R_BASE policy<{'arm64': 'm'}> +CONFIG_AD5593R policy<{'arm64': 'm'}> +CONFIG_AD5624R_SPI policy<{'arm64': 'm'}> +CONFIG_AD5686 policy<{'arm64': 'm'}> +CONFIG_AD5686_SPI policy<{'arm64': 'm'}> +CONFIG_AD5696_I2C policy<{'arm64': 'm'}> +CONFIG_AD5706R policy<{'arm64': 'n'}> +CONFIG_AD5755 policy<{'arm64': 'm'}> +CONFIG_AD5758 policy<{'arm64': 'm'}> +CONFIG_AD5761 policy<{'arm64': 'm'}> +CONFIG_AD5764 policy<{'arm64': 'm'}> +CONFIG_AD5766 policy<{'arm64': 'm'}> +CONFIG_AD5770R policy<{'arm64': 'm'}> +CONFIG_AD5791 policy<{'arm64': 'm'}> +CONFIG_AD5933 policy<{'arm64': 'm'}> +CONFIG_AD7091R policy<{'arm64': 'm'}> +CONFIG_AD7091R5 policy<{'arm64': 'm'}> +CONFIG_AD7091R8 policy<{'arm64': 'm'}> +CONFIG_AD7124 policy<{'arm64': 'm'}> +CONFIG_AD7150 policy<{'arm64': 'm'}> +CONFIG_AD7173 policy<{'arm64': 'm'}> +CONFIG_AD7191 policy<{'arm64': 'm'}> +CONFIG_AD7192 policy<{'arm64': 'm'}> +CONFIG_AD7266 policy<{'arm64': 'm'}> +CONFIG_AD7280 policy<{'arm64': 'm'}> +CONFIG_AD7291 policy<{'arm64': 'm'}> +CONFIG_AD7292 policy<{'arm64': 'm'}> +CONFIG_AD7293 policy<{'arm64': 'm'}> +CONFIG_AD7298 policy<{'arm64': 'm'}> +CONFIG_AD7303 policy<{'arm64': 'm'}> +CONFIG_AD7380 policy<{'arm64': 'm'}> +CONFIG_AD7405 policy<{'arm64': 'n'}> +CONFIG_AD74115 policy<{'arm64': 'm'}> +CONFIG_AD74413R policy<{'arm64': 'm'}> +CONFIG_AD7476 policy<{'arm64': 'm'}> +CONFIG_AD7606 policy<{'arm64': 'm'}> +CONFIG_AD7606_IFACE_PARALLEL policy<{'arm64': 'm'}> +CONFIG_AD7606_IFACE_SPI policy<{'arm64': 'm'}> +CONFIG_AD7625 policy<{'arm64': 'm'}> +CONFIG_AD7746 policy<{'arm64': 'm'}> +CONFIG_AD7766 policy<{'arm64': 'm'}> +CONFIG_AD7768_1 policy<{'arm64': 'm'}> +CONFIG_AD7779 policy<{'arm64': 'm'}> +CONFIG_AD7780 policy<{'arm64': 'm'}> +CONFIG_AD7791 policy<{'arm64': 'm'}> +CONFIG_AD7793 policy<{'arm64': 'm'}> +CONFIG_AD7816 policy<{'arm64': 'm'}> +CONFIG_AD7887 policy<{'arm64': 'm'}> +CONFIG_AD7923 policy<{'arm64': 'm'}> +CONFIG_AD7944 policy<{'arm64': 'm'}> +CONFIG_AD7949 policy<{'arm64': 'm'}> +CONFIG_AD799X policy<{'arm64': 'm'}> +CONFIG_AD8366 policy<{'arm64': 'm'}> +CONFIG_AD8460 policy<{'arm64': 'm'}> +CONFIG_AD8801 policy<{'arm64': 'm'}> +CONFIG_AD9467 policy<{'arm64': 'm'}> +CONFIG_AD9523 policy<{'arm64': 'm'}> +CONFIG_AD9739A policy<{'arm64': 'm'}> +CONFIG_AD9832 policy<{'arm64': 'm'}> +CONFIG_AD9834 policy<{'arm64': 'm'}> +CONFIG_ADA4250 policy<{'arm64': 'm'}> +CONFIG_ADAPTEC_STARFIRE policy<{'arm64': 'm'}> +CONFIG_ADC_BATTERY_HELPER policy<{'arm64': 'm'}> +CONFIG_ADE9000 policy<{'arm64': 'n'}> +CONFIG_ADF4350 policy<{'arm64': 'm'}> +CONFIG_ADF4371 policy<{'arm64': 'm'}> +CONFIG_ADF4377 policy<{'arm64': 'm'}> +CONFIG_ADFS_FS policy<{'arm64': 'm'}> +CONFIG_ADFS_FS_RW policy<{'arm64': 'n'}> +CONFIG_ADIN1100_PHY policy<{'arm64': 'm'}> +CONFIG_ADIN1110 policy<{'arm64': 'm'}> +CONFIG_ADIN_PHY policy<{'arm64': 'm'}> +CONFIG_ADIS16080 policy<{'arm64': 'm'}> +CONFIG_ADIS16130 policy<{'arm64': 'm'}> +CONFIG_ADIS16136 policy<{'arm64': 'm'}> +CONFIG_ADIS16201 policy<{'arm64': 'm'}> +CONFIG_ADIS16203 policy<{'arm64': 'm'}> +CONFIG_ADIS16209 policy<{'arm64': 'm'}> +CONFIG_ADIS16260 policy<{'arm64': 'm'}> +CONFIG_ADIS16400 policy<{'arm64': 'm'}> +CONFIG_ADIS16460 policy<{'arm64': 'm'}> +CONFIG_ADIS16475 policy<{'arm64': 'm'}> +CONFIG_ADIS16480 policy<{'arm64': 'm'}> +CONFIG_ADIS16550 policy<{'arm64': 'n'}> +CONFIG_ADI_AXI_ADC policy<{'arm64': 'm'}> +CONFIG_ADI_AXI_DAC policy<{'arm64': 'm'}> +CONFIG_ADI_I3C_MASTER policy<{'arm64': 'n'}> +CONFIG_ADJD_S311 policy<{'arm64': 'm'}> +CONFIG_ADL8113 policy<{'arm64': 'n'}> +CONFIG_ADM8211 policy<{'arm64': 'm'}> +CONFIG_ADMFM2000 policy<{'arm64': 'm'}> +CONFIG_ADMV1013 policy<{'arm64': 'm'}> +CONFIG_ADMV1014 policy<{'arm64': 'm'}> +CONFIG_ADMV4420 policy<{'arm64': 'm'}> +CONFIG_ADMV8818 policy<{'arm64': 'm'}> +CONFIG_ADP810 policy<{'arm64': 'n'}> +CONFIG_ADRF6780 policy<{'arm64': 'm'}> +CONFIG_ADT7316 policy<{'arm64': 'm'}> +CONFIG_ADT7316_I2C policy<{'arm64': 'm'}> +CONFIG_ADT7316_SPI policy<{'arm64': 'm'}> +CONFIG_ADUX1020 policy<{'arm64': 'm'}> +CONFIG_ADVISE_SYSCALLS policy<{'arm64': 'y'}> +CONFIG_ADXL313 policy<{'arm64': 'm'}> +CONFIG_ADXL313_I2C policy<{'arm64': 'm'}> +CONFIG_ADXL313_SPI policy<{'arm64': 'm'}> +CONFIG_ADXL345_I2C policy<{'arm64': 'n'}> +CONFIG_ADXL345_SPI policy<{'arm64': 'n'}> +CONFIG_ADXL355 policy<{'arm64': 'm'}> +CONFIG_ADXL355_I2C policy<{'arm64': 'm'}> +CONFIG_ADXL355_SPI policy<{'arm64': 'm'}> +CONFIG_ADXL367 policy<{'arm64': 'm'}> +CONFIG_ADXL367_I2C policy<{'arm64': 'm'}> +CONFIG_ADXL367_SPI policy<{'arm64': 'm'}> +CONFIG_ADXL372 policy<{'arm64': 'm'}> +CONFIG_ADXL372_I2C policy<{'arm64': 'm'}> +CONFIG_ADXL372_SPI policy<{'arm64': 'm'}> +CONFIG_ADXL380 policy<{'arm64': 'm'}> +CONFIG_ADXL380_I2C policy<{'arm64': 'm'}> +CONFIG_ADXL380_SPI policy<{'arm64': 'm'}> +CONFIG_ADXRS290 policy<{'arm64': 'm'}> +CONFIG_ADXRS450 policy<{'arm64': 'm'}> +CONFIG_AD_SIGMA_DELTA policy<{'arm64': 'm'}> +CONFIG_AF8133J policy<{'arm64': 'm'}> +CONFIG_AFE4403 policy<{'arm64': 'm'}> +CONFIG_AFE4404 policy<{'arm64': 'm'}> +CONFIG_AFFS_FS policy<{'arm64': 'm'}> +CONFIG_AFS_DEBUG policy<{'arm64': 'n'}> +CONFIG_AFS_DEBUG_CURSOR policy<{'arm64': 'n'}> +CONFIG_AFS_FS policy<{'arm64': 'm'}> +CONFIG_AFS_FSCACHE policy<{'arm64': 'y'}> +CONFIG_AF_KCM policy<{'arm64': 'm'}> +CONFIG_AF_RXRPC policy<{'arm64': 'm'}> +CONFIG_AF_RXRPC_DEBUG policy<{'arm64': 'n'}> +CONFIG_AF_RXRPC_INJECT_LOSS policy<{'arm64': 'n'}> +CONFIG_AF_RXRPC_INJECT_RX_DELAY policy<{'arm64': 'n'}> +CONFIG_AF_RXRPC_IPV6 policy<{'arm64': 'y'}> +CONFIG_AF_UNIX_OOB policy<{'arm64': 'y'}> +CONFIG_AHCI_CEVA policy<{'arm64': 'm'}> +CONFIG_AHCI_DWC policy<{'arm64': 'm'}> +CONFIG_AHCI_IMX policy<{'arm64': 'y'}> +CONFIG_AHCI_MTK policy<{'arm64': 'm'}> +CONFIG_AHCI_MVEBU policy<{'arm64': 'm'}> +CONFIG_AHCI_QORIQ policy<{'arm64': 'm'}> +CONFIG_AHCI_SUNXI policy<{'arm64': 'n'}> +CONFIG_AHCI_TEGRA policy<{'arm64': 'm'}> +CONFIG_AHCI_XGENE policy<{'arm64': 'm'}> +CONFIG_AIC79XX_CMDS_PER_DEVICE policy<{'arm64': '32'}> +CONFIG_AIC79XX_DEBUG_ENABLE policy<{'arm64': 'y'}> +CONFIG_AIC79XX_DEBUG_MASK policy<{'arm64': '0'}> +CONFIG_AIC79XX_REG_PRETTY_PRINT policy<{'arm64': 'y'}> +CONFIG_AIC79XX_RESET_DELAY_MS policy<{'arm64': '5000'}> +CONFIG_AIC7XXX_CMDS_PER_DEVICE policy<{'arm64': '8'}> +CONFIG_AIC7XXX_DEBUG_ENABLE policy<{'arm64': 'y'}> +CONFIG_AIC7XXX_DEBUG_MASK policy<{'arm64': '0'}> +CONFIG_AIC7XXX_REG_PRETTY_PRINT policy<{'arm64': 'y'}> +CONFIG_AIC7XXX_RESET_DELAY_MS policy<{'arm64': '5000'}> +CONFIG_AIC94XX_DEBUG policy<{'arm64': 'y'}> +CONFIG_AIO policy<{'arm64': 'y'}> +CONFIG_AIROHA_CPU_PM_DOMAIN policy<{'arm64': 'y'}> +CONFIG_AIROHA_THERMAL policy<{'arm64': 'n'}> +CONFIG_AIROHA_WATCHDOG policy<{'arm64': 'n'}> +CONFIG_AIR_AN8801_PHY policy<{'arm64': 'n'}> +CONFIG_AIR_EN8811H_PHY policy<{'arm64': 'm'}> +CONFIG_AIR_NET_PHYLIB policy<{'arm64': 'm'}> +CONFIG_AIX_PARTITION policy<{'arm64': 'y'}> +CONFIG_AK09911 policy<{'arm64': 'm'}> +CONFIG_AK8974 policy<{'arm64': 'm'}> +CONFIG_AK8975 policy<{'arm64': 'm'}> +CONFIG_AL3000A policy<{'arm64': 'n'}> +CONFIG_AL3010 policy<{'arm64': 'm'}> +CONFIG_AL3320A policy<{'arm64': 'm'}> +CONFIG_ALIBABA_EEA policy<{'arm64': 'n'}> +CONFIG_ALIBABA_UNCORE_DRW_PMU policy<{'arm64': 'm'}> +CONFIG_ALIM7101_WDT policy<{'arm64': 'm'}> +CONFIG_ALLOW_DEV_COREDUMP policy<{'arm64': 'y'}> +CONFIG_ALS31300 policy<{'arm64': 'm'}> +CONFIG_ALTERA_FREEZE_BRIDGE policy<{'arm64': 'm'}> +CONFIG_ALTERA_MBOX policy<{'arm64': 'm'}> +CONFIG_ALTERA_MSGDMA policy<{'arm64': 'm'}> +CONFIG_ALTERA_PR_IP_CORE policy<{'arm64': 'm'}> +CONFIG_ALTERA_PR_IP_CORE_PLAT policy<{'arm64': 'm'}> +CONFIG_ALTERA_STAPL policy<{'arm64': 'm'}> +CONFIG_ALTERA_TSE policy<{'arm64': 'm'}> +CONFIG_ALX policy<{'arm64': 'm'}> +CONFIG_AL_FIC policy<{'arm64': 'y'}> +CONFIG_AM2315 policy<{'arm64': 'm'}> +CONFIG_AMBA_PL08X policy<{'arm64': 'y'}> +CONFIG_AMD8111_ETH policy<{'arm64': 'm'}> +CONFIG_AMD_PHY policy<{'arm64': 'm'}> +CONFIG_AMD_QDMA policy<{'arm64': 'n'}> +CONFIG_AMD_SBRMI_I2C policy<{'arm64': 'n'}> +CONFIG_AMD_XGBE policy<{'arm64': 'm'}> +CONFIG_AMD_XGBE_DCB policy<{'arm64': 'y'}> +CONFIG_AMIGA_PARTITION policy<{'arm64': 'y'}> +CONFIG_AMLOGIC_THERMAL policy<{'arm64': 'm'}> +CONFIG_AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU policy<{'arm64': 'm'}> +CONFIG_AMPERE_ERRATUM_AC03_CPU_38 policy<{'arm64': 'y'}> +CONFIG_AMPERE_ERRATUM_AC04_CPU_23 policy<{'arm64': 'y'}> +CONFIG_AMT policy<{'arm64': 'm'}> +CONFIG_ANDROID_BINDERFS policy<{'arm64': 'm'}> +CONFIG_ANDROID_BINDER_DEVICES policy<{'arm64': '"binder,hwbinder,vndbinder"'}> +CONFIG_ANDROID_BINDER_IPC policy<{'arm64': 'm'}> +CONFIG_ANON_VMA_NAME policy<{'arm64': 'y'}> +CONFIG_AOSONG_AGS02MA policy<{'arm64': 'm'}> +CONFIG_APDS9160 policy<{'arm64': 'm'}> +CONFIG_APDS9300 policy<{'arm64': 'm'}> +CONFIG_APDS9306 policy<{'arm64': 'm'}> +CONFIG_APDS9802ALS policy<{'arm64': 'm'}> +CONFIG_APDS9960 policy<{'arm64': 'm'}> +CONFIG_APDS9999 policy<{'arm64': 'n'}> +CONFIG_APERTURE_HELPERS policy<{'arm64': 'y'}> +CONFIG_APPLE_ADMAC policy<{'arm64': 'm'}> +CONFIG_APPLE_AIC policy<{'arm64': 'y'}> +CONFIG_APPLE_DART policy<{'arm64': 'm'}> +CONFIG_APPLE_M1_CPU_PMU policy<{'arm64': 'y'}> +CONFIG_APPLE_MAILBOX policy<{'arm64': 'm'}> +CONFIG_APPLE_MFI_FASTCHARGE policy<{'arm64': 'm'}> +CONFIG_APPLE_PMGR_PWRSTATE policy<{'arm64': 'y'}> +CONFIG_APPLE_RTKIT policy<{'arm64': 'm'}> +CONFIG_APPLE_SART policy<{'arm64': 'm'}> +CONFIG_APPLE_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_AQTION policy<{'arm64': 'm'}> +CONFIG_AQUANTIA_PHY policy<{'arm64': 'm'}> +CONFIG_AR5523 policy<{'arm64': 'm'}> +CONFIG_ARCH_ACTIONS policy<{'arm64': 'y'}> +CONFIG_ARCH_AIROHA policy<{'arm64': 'y'}> +CONFIG_ARCH_ALPINE policy<{'arm64': 'n'}> +CONFIG_ARCH_APPLE policy<{'arm64': 'y'}> +CONFIG_ARCH_ASPEED policy<{'arm64': 'n'}> +CONFIG_ARCH_AXIADO policy<{'arm64': 'n'}> +CONFIG_ARCH_BCM policy<{'arm64': 'n'}> +CONFIG_ARCH_BERLIN policy<{'arm64': 'y'}> +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS policy<{'arm64': 'y'}> +CONFIG_ARCH_BINFMT_ELF_STATE policy<{'arm64': 'y'}> +CONFIG_ARCH_BITMAIN policy<{'arm64': 'y'}> +CONFIG_ARCH_BLAIZE policy<{'arm64': 'n'}> +CONFIG_ARCH_BST policy<{'arm64': 'n'}> +CONFIG_ARCH_CIX policy<{'arm64': 'n'}> +CONFIG_ARCH_DEFAULT_CRASH_DUMP policy<{'arm64': 'y'}> +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG policy<{'arm64': 'y'}> +CONFIG_ARCH_DMA_ADDR_T_64BIT policy<{'arm64': 'y'}> +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION policy<{'arm64': 'y'}> +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG policy<{'arm64': 'y'}> +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK policy<{'arm64': 'y'}> +CONFIG_ARCH_ENABLE_THP_MIGRATION policy<{'arm64': 'y'}> +CONFIG_ARCH_EXYNOS policy<{'arm64': 'n'}> +CONFIG_ARCH_FORCE_MAX_ORDER policy<{'arm64': '13'}> +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_BATCHED_DMA_SYNC policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_CACHE_LINE_SIZE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_CC_PLATFORM policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_DEBUG_VIRTUAL policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_DEBUG_WX policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_DMA_OPS policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_DMA_PREP_COHERENT policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_ELF_RANDOMIZE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_FAST_MULTIPLIER policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_FORTIFY_SOURCE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_GIGANTIC_PAGE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_HW_PTE_YOUNG policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_KCOV policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_KEEPINITRD policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_LAZY_MMU_MODE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_MEM_ENCRYPT policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_PKEYS policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_PMEM_API policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_PREEMPT_LAZY policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_PTDUMP policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_PTE_SPECIAL policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_RELR policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_RESET_CONTROLLER policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_SETUP_DMA_OPS policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_SET_DIRECT_MAP policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_SET_MEMORY policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_STRICT_MODULE_RWX policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_SUBPAGE_FAULTS policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_SYSCALL_WRAPPER policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_TICK_BROADCAST policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_UBSAN policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_USER_SHADOW_STACK policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_ZONE_DMA_SET policy<{'arm64': 'y'}> +CONFIG_ARCH_HAVE_ELF_PROT policy<{'arm64': 'y'}> +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG policy<{'arm64': 'y'}> +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS policy<{'arm64': 'y'}> +CONFIG_ARCH_HIBERNATION_POSSIBLE policy<{'arm64': 'y'}> +CONFIG_ARCH_HISI policy<{'arm64': 'y'}> +CONFIG_ARCH_INTEL_SOCFPGA policy<{'arm64': 'y'}> +CONFIG_ARCH_K3 policy<{'arm64': 'y'}> +CONFIG_ARCH_KEEMBAY policy<{'arm64': 'y'}> +CONFIG_ARCH_KEEP_MEMBLOCK policy<{'arm64': 'y'}> +CONFIG_ARCH_LAN969X policy<{'arm64': 'n'}> +CONFIG_ARCH_LAYERSCAPE policy<{'arm64': 'y'}> +CONFIG_ARCH_LG1K policy<{'arm64': 'y'}> +CONFIG_ARCH_MA35 policy<{'arm64': 'y'}> +CONFIG_ARCH_MEDIATEK policy<{'arm64': 'y'}> +CONFIG_ARCH_MESON policy<{'arm64': 'y'}> +CONFIG_ARCH_MICROCHIP policy<{'arm64': 'y'}> +CONFIG_ARCH_MMAP_RND_BITS_MAX policy<{'arm64': '33'}> +CONFIG_ARCH_MMAP_RND_BITS_MIN policy<{'arm64': '18'}> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX policy<{'arm64': '16'}> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN policy<{'arm64': '11'}> +CONFIG_ARCH_MMP policy<{'arm64': 'n'}> +CONFIG_ARCH_MVEBU policy<{'arm64': 'y'}> +CONFIG_ARCH_MXC policy<{'arm64': 'y'}> +CONFIG_ARCH_NPCM policy<{'arm64': 'y'}> +CONFIG_ARCH_NXP policy<{'arm64': 'y'}> +CONFIG_ARCH_PENSANDO policy<{'arm64': 'y'}> +CONFIG_ARCH_PKEY_BITS policy<{'arm64': '3'}> +CONFIG_ARCH_PROC_KCORE_TEXT policy<{'arm64': 'y'}> +CONFIG_ARCH_QCOM policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77951 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77960 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77961 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77965 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77970 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77980 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77990 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77995 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A78000 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A07G043 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A07G044 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A07G054 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A08G045 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A08G046 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G011 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G047 policy<{'arm64': 'n'}> +CONFIG_ARCH_R9A09G056 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G057 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G077 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G087 policy<{'arm64': 'y'}> +CONFIG_ARCH_RCAR_GEN3 policy<{'arm64': 'y'}> +CONFIG_ARCH_RCAR_GEN4 policy<{'arm64': 'y'}> +CONFIG_ARCH_RCAR_GEN5 policy<{'arm64': 'y'}> +CONFIG_ARCH_REALTEK policy<{'arm64': 'y'}> +CONFIG_ARCH_RENESAS policy<{'arm64': 'y'}> +CONFIG_ARCH_RZG2L policy<{'arm64': 'y'}> +CONFIG_ARCH_S32 policy<{'arm64': 'y'}> +CONFIG_ARCH_SEATTLE policy<{'arm64': 'y'}> +CONFIG_ARCH_SELECTS_KEXEC_FILE policy<{'arm64': 'y'}> +CONFIG_ARCH_SOPHGO policy<{'arm64': 'n'}> +CONFIG_ARCH_SPARSEMEM_ENABLE policy<{'arm64': 'y'}> +CONFIG_ARCH_SPARX5 policy<{'arm64': 'y'}> +CONFIG_ARCH_SPRD policy<{'arm64': 'y'}> +CONFIG_ARCH_STACKWALK policy<{'arm64': 'y'}> +CONFIG_ARCH_STM32 policy<{'arm64': 'y'}> +CONFIG_ARCH_SUNXI policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_ACPI policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_CFI policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_CRASH_DUMP policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_HUGETLBFS policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_INT128 policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_FILE policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_HANDOVER policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_SIG policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_LTO_CLANG policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_PMD_PFNMAP policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_RT policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_SCHED_CLUSTER policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_SCHED_MC policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_SCHED_SMT policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_UPROBES policy<{'arm64': 'y'}> +CONFIG_ARCH_SUSPEND_POSSIBLE policy<{'arm64': 'y'}> +CONFIG_ARCH_SYNQUACER policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_132_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_186_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_194_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_210_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_234_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_238_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_241_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_264_SOC policy<{'arm64': 'n'}> +CONFIG_ARCH_THUNDER policy<{'arm64': 'y'}> +CONFIG_ARCH_THUNDER2 policy<{'arm64': 'y'}> +CONFIG_ARCH_UNIPHIER policy<{'arm64': 'n'}> +CONFIG_ARCH_USES_HIGH_VMA_FLAGS policy<{'arm64': 'y'}> +CONFIG_ARCH_USES_PG_ARCH_2 policy<{'arm64': 'y'}> +CONFIG_ARCH_USES_PG_ARCH_3 policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_CMPXCHG_LOCKREF policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_GNU_PROPERTY policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_MEMREMAP_PROT policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_MEMTEST policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_QUEUED_RWLOCKS policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_QUEUED_SPINLOCKS policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_SYM_ANNOTATIONS policy<{'arm64': 'y'}> +CONFIG_ARCH_VEXPRESS policy<{'arm64': 'y'}> +CONFIG_ARCH_VISCONTI policy<{'arm64': 'y'}> +CONFIG_ARCH_WANTS_EXECMEM_LATE policy<{'arm64': 'y'}> +CONFIG_ARCH_WANTS_NO_INSTR policy<{'arm64': 'y'}> +CONFIG_ARCH_WANTS_THP_SWAP policy<{'arm64': 'y'}> +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH policy<{'arm64': 'y'}> +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION policy<{'arm64': 'y'}> +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT policy<{'arm64': 'y'}> +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT policy<{'arm64': 'y'}> +CONFIG_ARCH_WANT_FRAME_POINTERS policy<{'arm64': 'y'}> +CONFIG_ARCH_WANT_HUGE_PMD_SHARE policy<{'arm64': 'y'}> +CONFIG_ARCH_WANT_LD_ORPHAN_WARN policy<{'arm64': 'y'}> +CONFIG_ARCH_WANT_PMD_MKWRITE policy<{'arm64': 'y'}> +CONFIG_ARCH_XGENE policy<{'arm64': 'y'}> +CONFIG_ARCH_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_ARCNET policy<{'arm64': 'm'}> +CONFIG_ARCNET_1051 policy<{'arm64': 'm'}> +CONFIG_ARCNET_1201 policy<{'arm64': 'm'}> +CONFIG_ARCNET_CAP policy<{'arm64': 'm'}> +CONFIG_ARCNET_COM20020 policy<{'arm64': 'm'}> +CONFIG_ARCNET_COM20020_PCI policy<{'arm64': 'm'}> +CONFIG_ARCNET_RAW policy<{'arm64': 'm'}> +CONFIG_ARC_EMAC_CORE policy<{'arm64': 'm'}> +CONFIG_ARM64 policy<{'arm64': 'y'}> +CONFIG_ARM64_16K_PAGES policy<{'arm64': 'n'}> +CONFIG_ARM64_4K_PAGES policy<{'arm64': 'y'}> +CONFIG_ARM64_64K_PAGES policy<{'arm64': 'n'}> +CONFIG_ARM64_ACPI_PARKING_PROTOCOL policy<{'arm64': 'y'}> +CONFIG_ARM64_AMU_EXTN policy<{'arm64': 'y'}> +CONFIG_ARM64_AS_HAS_MTE policy<{'arm64': 'y'}> +CONFIG_ARM64_BRBE policy<{'arm64': 'y'}> +CONFIG_ARM64_BTI policy<{'arm64': 'y'}> +CONFIG_ARM64_CNP policy<{'arm64': 'y'}> +CONFIG_ARM64_CONTPTE policy<{'arm64': 'y'}> +CONFIG_ARM64_CONT_PMD_SHIFT policy<{'arm64': '4'}> +CONFIG_ARM64_CONT_PTE_SHIFT policy<{'arm64': '4'}> +CONFIG_ARM64_DEBUG_PRIORITY_MASKING policy<{'arm64': 'n'}> +CONFIG_ARM64_E0PD policy<{'arm64': 'y'}> +CONFIG_ARM64_EPAN policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1024718 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1165522 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1286807 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1319367 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1418040 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1463225 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1508412 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1530923 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1542419 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1742098 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2051678 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2054223 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2067961 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2077057 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2441007 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2441009 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2457168 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2645198 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2658417 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2966298 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_3117295 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_3194386 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_4118414 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_4193714 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_4311569 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_819472 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_824069 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_826319 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_827319 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_832075 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_834220 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_845719 policy<{'arm64': 'y'}> +CONFIG_ARM64_FORCE_52BIT policy<{'arm64': 'n'}> +CONFIG_ARM64_GCS policy<{'arm64': 'y'}> +CONFIG_ARM64_HAFT policy<{'arm64': 'y'}> +CONFIG_ARM64_HW_AFDBM policy<{'arm64': 'y'}> +CONFIG_ARM64_LPA2 policy<{'arm64': 'y'}> +CONFIG_ARM64_LSUI policy<{'arm64': 'y'}> +CONFIG_ARM64_MPAM policy<{'arm64': 'n'}> +CONFIG_ARM64_MTE policy<{'arm64': 'y'}> +CONFIG_ARM64_PA_BITS policy<{'arm64': '52'}> +CONFIG_ARM64_PA_BITS_52 policy<{'arm64': 'y'}> +CONFIG_ARM64_PLATFORM_DEVICES policy<{'arm64': 'y'}> +CONFIG_ARM64_PMEM policy<{'arm64': 'y'}> +CONFIG_ARM64_POE policy<{'arm64': 'y'}> +CONFIG_ARM64_PSEUDO_NMI policy<{'arm64': 'y'}> +CONFIG_ARM64_PTR_AUTH policy<{'arm64': 'y'}> +CONFIG_ARM64_PTR_AUTH_KERNEL policy<{'arm64': 'y'}> +CONFIG_ARM64_RAS_EXTN policy<{'arm64': 'y'}> +CONFIG_ARM64_RELOC_TEST policy<{'arm64': 'n'}> +CONFIG_ARM64_SME policy<{'arm64': 'y'}> +CONFIG_ARM64_SVE policy<{'arm64': 'y'}> +CONFIG_ARM64_SW_TTBR0_PAN policy<{'arm64': 'y'}> +CONFIG_ARM64_TAGGED_ADDR_ABI policy<{'arm64': 'y'}> +CONFIG_ARM64_TLB_RANGE policy<{'arm64': 'y'}> +CONFIG_ARM64_VA_BITS policy<{'arm64': '52'}> +CONFIG_ARM64_VA_BITS_39 policy<{'arm64': 'n'}> +CONFIG_ARM64_VA_BITS_48 policy<{'arm64': 'n'}> +CONFIG_ARM64_VA_BITS_52 policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_DISABLE_CNP policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE policy<{'arm64': 'y'}> +CONFIG_ARMADA_37XX_CLK policy<{'arm64': 'y'}> +CONFIG_ARMADA_37XX_RWTM_MBOX policy<{'arm64': 'm'}> +CONFIG_ARMADA_37XX_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_ARMADA_AP806_SYSCON policy<{'arm64': 'y'}> +CONFIG_ARMADA_AP_CPU_CLK policy<{'arm64': 'y'}> +CONFIG_ARMADA_AP_CP_HELPER policy<{'arm64': 'y'}> +CONFIG_ARMADA_CP110_SYSCON policy<{'arm64': 'y'}> +CONFIG_ARMADA_THERMAL policy<{'arm64': 'y'}> +CONFIG_ARM_AIROHA_SOC_CPUFREQ policy<{'arm64': 'y'}> +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM policy<{'arm64': 'm'}> +CONFIG_ARM_AMBA policy<{'arm64': 'y'}> +CONFIG_ARM_APPLE_SOC_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_ARCH_TIMER policy<{'arm64': 'y'}> +CONFIG_ARM_ARCH_TIMER_EVTSTREAM policy<{'arm64': 'y'}> +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND policy<{'arm64': 'y'}> +CONFIG_ARM_ARMADA_37XX_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_ARMADA_8K_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_CCA_GUEST policy<{'arm64': 'n'}> +CONFIG_ARM_CCI policy<{'arm64': 'y'}> +CONFIG_ARM_CCI400_COMMON policy<{'arm64': 'y'}> +CONFIG_ARM_CCI400_PMU policy<{'arm64': 'y'}> +CONFIG_ARM_CCI5xx_PMU policy<{'arm64': 'y'}> +CONFIG_ARM_CCI_PMU policy<{'arm64': 'y'}> +CONFIG_ARM_CCN policy<{'arm64': 'y'}> +CONFIG_ARM_CMN policy<{'arm64': 'm'}> +CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_DMA350 policy<{'arm64': 'n'}> +CONFIG_ARM_DMC620_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_DSU_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_FFA_SMCCC policy<{'arm64': 'y'}> +CONFIG_ARM_FFA_TRANSPORT policy<{'arm64': 'm'}> +CONFIG_ARM_GIC policy<{'arm64': 'y'}> +CONFIG_ARM_GIC_ITS_PARENT policy<{'arm64': 'y'}> +CONFIG_ARM_GIC_MAX_NR policy<{'arm64': '1'}> +CONFIG_ARM_GIC_PM policy<{'arm64': 'y'}> +CONFIG_ARM_GIC_V2M policy<{'arm64': 'y'}> +CONFIG_ARM_GIC_V3 policy<{'arm64': 'y'}> +CONFIG_ARM_GIC_V3_ITS policy<{'arm64': 'y'}> +CONFIG_ARM_GIC_V5 policy<{'arm64': 'y'}> +CONFIG_ARM_HISI_UNCORE_DEVFREQ policy<{'arm64': 'n'}> +CONFIG_ARM_IMX6Q_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_IMX8M_DDRC_DEVFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_IMX_BUS_DEVFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_IMX_CPUFREQ_DT policy<{'arm64': 'm'}> +CONFIG_ARM_MEDIATEK_CCI_DEVFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_MEDIATEK_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_MEDIATEK_CPUFREQ_HW policy<{'arm64': 'm'}> +CONFIG_ARM_MHU policy<{'arm64': 'm'}> +CONFIG_ARM_MHU_V2 policy<{'arm64': 'm'}> +CONFIG_ARM_MHU_V3 policy<{'arm64': 'm'}> +CONFIG_ARM_NI policy<{'arm64': 'n'}> +CONFIG_ARM_PKVM_GUEST policy<{'arm64': 'n'}> +CONFIG_ARM_PL172_MPMC policy<{'arm64': 'm'}> +CONFIG_ARM_PMU policy<{'arm64': 'y'}> +CONFIG_ARM_PMUV3 policy<{'arm64': 'y'}> +CONFIG_ARM_PMU_ACPI policy<{'arm64': 'y'}> +CONFIG_ARM_PSCI_CHECKER policy<{'arm64': 'n'}> +CONFIG_ARM_PSCI_CPUIDLE policy<{'arm64': 'y'}> +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN policy<{'arm64': 'y'}> +CONFIG_ARM_PSCI_FW policy<{'arm64': 'y'}> +CONFIG_ARM_QCOM_CPUFREQ_HW policy<{'arm64': 'm'}> +CONFIG_ARM_QCOM_CPUFREQ_NVMEM policy<{'arm64': 'm'}> +CONFIG_ARM_RK3399_DMC_DEVFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_SBSA_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_ARM_SCMI_CPUFREQ policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_DEBUG_COUNTERS policy<{'arm64': 'n'}> +CONFIG_ARM_SCMI_HAVE_MSG policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_HAVE_SHMEM policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_HAVE_TRANSPORT policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_NEED_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_PERF_DOMAIN policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_POWERCAP policy<{'arm64': 'm'}> +CONFIG_ARM_SCMI_POWER_CONTROL policy<{'arm64': 'm'}> +CONFIG_ARM_SCMI_POWER_DOMAIN policy<{'arm64': 'm'}> +CONFIG_ARM_SCMI_PROTOCOL policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_QUIRKS policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_RAW_MODE_SUPPORT policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_RAW_MODE_SUPPORT_COEX policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_MAILBOX policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_OPTEE policy<{'arm64': 'm'}> +CONFIG_ARM_SCMI_TRANSPORT_SMC policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE policy<{'arm64': 'y'}> +CONFIG_ARM_SCPI_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_SCPI_POWER_DOMAIN policy<{'arm64': 'm'}> +CONFIG_ARM_SCPI_PROTOCOL policy<{'arm64': 'm'}> +CONFIG_ARM_SDE_INTERFACE policy<{'arm64': 'y'}> +CONFIG_ARM_SMCCC_SOC_ID policy<{'arm64': 'y'}> +CONFIG_ARM_SMC_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_ARM_SMMU policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS policy<{'arm64': 'n'}> +CONFIG_ARM_SMMU_MMU_500_CPRE_ERRATA policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_QCOM policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_QCOM_DEBUG policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_V3 policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_V3_IOMMUFD policy<{'arm64': 'n'}> +CONFIG_ARM_SMMU_V3_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_SMMU_V3_SVA policy<{'arm64': 'y'}> +CONFIG_ARM_SP805_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_ARM_SPE_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_TEGRA124_CPUFREQ policy<{'arm64': 'y'}> +CONFIG_ARM_TEGRA186_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_TEGRA194_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_TEGRA20_CPUFREQ policy<{'arm64': 'y'}> +CONFIG_ARM_TEGRA_DEVFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_TIMER_SP804 policy<{'arm64': 'y'}> +CONFIG_ARM_TI_CPUFREQ policy<{'arm64': 'y'}> +CONFIG_ARM_TSTEE policy<{'arm64': 'm'}> +CONFIG_AS21XXX_PHY policy<{'arm64': 'n'}> +CONFIG_AS3935 policy<{'arm64': 'm'}> +CONFIG_AS73211 policy<{'arm64': 'm'}> +CONFIG_ASM_MODVERSIONS policy<{'arm64': 'y'}> +CONFIG_ASN1 policy<{'arm64': 'y'}> +CONFIG_ASN1_ENCODER policy<{'arm64': 'y'}> +CONFIG_ASSOCIATIVE_ARRAY policy<{'arm64': 'y'}> +CONFIG_ASYNC_CORE policy<{'arm64': 'm'}> +CONFIG_ASYNC_MEMCPY policy<{'arm64': 'm'}> +CONFIG_ASYNC_PQ policy<{'arm64': 'm'}> +CONFIG_ASYNC_RAID6_RECOV policy<{'arm64': 'm'}> +CONFIG_ASYNC_RAID6_TEST policy<{'arm64': 'n'}> +CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA policy<{'arm64': 'y'}> +CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA policy<{'arm64': 'y'}> +CONFIG_ASYNC_TX_DMA policy<{'arm64': 'y'}> +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH policy<{'arm64': 'y'}> +CONFIG_ASYNC_XOR policy<{'arm64': 'm'}> +CONFIG_AS_HAS_ARMV8_5 policy<{'arm64': 'y'}> +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE policy<{'arm64': 'y'}> +CONFIG_AS_HAS_LSUI policy<{'arm64': 'y'}> +CONFIG_AS_HAS_MOPS policy<{'arm64': 'y'}> +CONFIG_AS_HAS_NON_CONST_ULEB128 policy<{'arm64': 'y'}> +CONFIG_AS_HAS_SME policy<{'arm64': 'y'}> +CONFIG_AS_IS_GNU policy<{'arm64': 'y'}> +CONFIG_AS_VERSION policy<{'arm64': '24600'}> +CONFIG_AT76C50X_USB policy<{'arm64': 'm'}> +CONFIG_AT803X_PHY policy<{'arm64': 'y'}> +CONFIG_ATA policy<{'arm64': 'y'}> +CONFIG_ATARI_PARTITION policy<{'arm64': 'y'}> +CONFIG_ATA_ACPI policy<{'arm64': 'y'}> +CONFIG_ATA_BMDMA policy<{'arm64': 'y'}> +CONFIG_ATA_FORCE policy<{'arm64': 'y'}> +CONFIG_ATA_GENERIC policy<{'arm64': 'm'}> +CONFIG_ATA_OVER_ETH policy<{'arm64': 'm'}> +CONFIG_ATA_SFF policy<{'arm64': 'y'}> +CONFIG_ATA_VERBOSE_ERROR policy<{'arm64': 'y'}> +CONFIG_ATH10K policy<{'arm64': 'm'}> +CONFIG_ATH10K_AHB policy<{'arm64': 'y'}> +CONFIG_ATH10K_CE policy<{'arm64': 'y'}> +CONFIG_ATH10K_DEBUG policy<{'arm64': 'n'}> +CONFIG_ATH10K_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_ATH10K_LEDS policy<{'arm64': 'y'}> +CONFIG_ATH10K_PCI policy<{'arm64': 'm'}> +CONFIG_ATH10K_SDIO policy<{'arm64': 'm'}> +CONFIG_ATH10K_SNOC policy<{'arm64': 'm'}> +CONFIG_ATH10K_SPECTRAL policy<{'arm64': 'y'}> +CONFIG_ATH10K_TRACING policy<{'arm64': 'y'}> +CONFIG_ATH10K_USB policy<{'arm64': 'm'}> +CONFIG_ATH11K policy<{'arm64': 'm'}> +CONFIG_ATH11K_AHB policy<{'arm64': 'm'}> +CONFIG_ATH11K_CFR policy<{'arm64': 'n'}> +CONFIG_ATH11K_DEBUG policy<{'arm64': 'n'}> +CONFIG_ATH11K_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_ATH11K_PCI policy<{'arm64': 'm'}> +CONFIG_ATH11K_SPECTRAL policy<{'arm64': 'y'}> +CONFIG_ATH11K_TRACING policy<{'arm64': 'y'}> +CONFIG_ATH12K policy<{'arm64': 'm'}> +CONFIG_ATH12K_AHB policy<{'arm64': 'y'}> +CONFIG_ATH12K_COREDUMP policy<{'arm64': 'n'}> +CONFIG_ATH12K_DEBUG policy<{'arm64': 'n'}> +CONFIG_ATH12K_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_ATH12K_TRACING policy<{'arm64': 'y'}> +CONFIG_ATH5K policy<{'arm64': 'm'}> +CONFIG_ATH5K_DEBUG policy<{'arm64': 'n'}> +CONFIG_ATH5K_PCI policy<{'arm64': 'y'}> +CONFIG_ATH5K_TRACER policy<{'arm64': 'n'}> +CONFIG_ATH6KL policy<{'arm64': 'm'}> +CONFIG_ATH6KL_DEBUG policy<{'arm64': 'n'}> +CONFIG_ATH6KL_SDIO policy<{'arm64': 'm'}> +CONFIG_ATH6KL_TRACING policy<{'arm64': 'n'}> +CONFIG_ATH6KL_USB policy<{'arm64': 'm'}> +CONFIG_ATH9K policy<{'arm64': 'm'}> +CONFIG_ATH9K_AHB policy<{'arm64': 'y'}> +CONFIG_ATH9K_BTCOEX_SUPPORT policy<{'arm64': 'y'}> +CONFIG_ATH9K_CHANNEL_CONTEXT policy<{'arm64': 'y'}> +CONFIG_ATH9K_COMMON policy<{'arm64': 'm'}> +CONFIG_ATH9K_COMMON_DEBUG policy<{'arm64': 'y'}> +CONFIG_ATH9K_COMMON_SPECTRAL policy<{'arm64': 'y'}> +CONFIG_ATH9K_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_ATH9K_DYNACK policy<{'arm64': 'n'}> +CONFIG_ATH9K_HTC policy<{'arm64': 'm'}> +CONFIG_ATH9K_HTC_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_ATH9K_HW policy<{'arm64': 'm'}> +CONFIG_ATH9K_HWRNG policy<{'arm64': 'y'}> +CONFIG_ATH9K_PCI policy<{'arm64': 'y'}> +CONFIG_ATH9K_PCI_NO_EEPROM policy<{'arm64': 'm'}> +CONFIG_ATH9K_PCOEM policy<{'arm64': 'y'}> +CONFIG_ATH9K_RFKILL policy<{'arm64': 'y'}> +CONFIG_ATH9K_STATION_STATISTICS policy<{'arm64': 'y'}> +CONFIG_ATH9K_WOW policy<{'arm64': 'y'}> +CONFIG_ATH_COMMON policy<{'arm64': 'm'}> +CONFIG_ATH_DEBUG policy<{'arm64': 'n'}> +CONFIG_ATL1 policy<{'arm64': 'm'}> +CONFIG_ATL1C policy<{'arm64': 'm'}> +CONFIG_ATL1E policy<{'arm64': 'm'}> +CONFIG_ATL2 policy<{'arm64': 'm'}> +CONFIG_ATLAS_EZO_SENSOR policy<{'arm64': 'm'}> +CONFIG_ATLAS_PH_SENSOR policy<{'arm64': 'm'}> +CONFIG_ATM policy<{'arm64': 'm'}> +CONFIG_ATM_BR2684 policy<{'arm64': 'm'}> +CONFIG_ATM_BR2684_IPFILTER policy<{'arm64': 'n'}> +CONFIG_ATM_DRIVERS policy<{'arm64': 'y'}> +CONFIG_ATM_SOLOS policy<{'arm64': 'm'}> +CONFIG_ATOMIC64_SELFTEST policy<{'arm64': 'n'}> +CONFIG_AT_XDMAC policy<{'arm64': 'n'}> +CONFIG_AUDIT policy<{'arm64': 'y'}> +CONFIG_AUDITSYSCALL policy<{'arm64': 'y'}> +CONFIG_AUDIT_ARCH_COMPAT_GENERIC policy<{'arm64': 'y'}> +CONFIG_AUDIT_COMPAT_GENERIC policy<{'arm64': 'y'}> +CONFIG_AUDIT_GENERIC policy<{'arm64': 'y'}> +CONFIG_AUTOFS_FS policy<{'arm64': 'm'}> +CONFIG_AUXDISPLAY policy<{'arm64': 'y'}> +CONFIG_AUXILIARY_BUS policy<{'arm64': 'y'}> +CONFIG_AW96103 policy<{'arm64': 'n'}> +CONFIG_AX88796B_PHY policy<{'arm64': 'm'}> +CONFIG_AXI_DMAC policy<{'arm64': 'm'}> +CONFIG_AXP20X_ADC policy<{'arm64': 'm'}> +CONFIG_AXP20X_POWER policy<{'arm64': 'm'}> +CONFIG_AXP288_ADC policy<{'arm64': 'm'}> +CONFIG_B43 policy<{'arm64': 'm'}> +CONFIG_B43LEGACY policy<{'arm64': 'm'}> +CONFIG_B43LEGACY_DEBUG policy<{'arm64': 'y'}> +CONFIG_B43LEGACY_DMA policy<{'arm64': 'y'}> +CONFIG_B43LEGACY_DMA_AND_PIO_MODE policy<{'arm64': 'y'}> +CONFIG_B43LEGACY_DMA_MODE policy<{'arm64': 'n'}> +CONFIG_B43LEGACY_HWRNG policy<{'arm64': 'y'}> +CONFIG_B43LEGACY_LEDS policy<{'arm64': 'y'}> +CONFIG_B43LEGACY_PCICORE_AUTOSELECT policy<{'arm64': 'y'}> +CONFIG_B43LEGACY_PCI_AUTOSELECT policy<{'arm64': 'y'}> +CONFIG_B43LEGACY_PIO policy<{'arm64': 'y'}> +CONFIG_B43LEGACY_PIO_MODE policy<{'arm64': 'n'}> +CONFIG_B43_BCMA policy<{'arm64': 'y'}> +CONFIG_B43_BCMA_PIO policy<{'arm64': 'y'}> +CONFIG_B43_BUSES_BCMA policy<{'arm64': 'n'}> +CONFIG_B43_BUSES_BCMA_AND_SSB policy<{'arm64': 'y'}> +CONFIG_B43_BUSES_SSB policy<{'arm64': 'n'}> +CONFIG_B43_DEBUG policy<{'arm64': 'n'}> +CONFIG_B43_HWRNG policy<{'arm64': 'y'}> +CONFIG_B43_LEDS policy<{'arm64': 'y'}> +CONFIG_B43_PCICORE_AUTOSELECT policy<{'arm64': 'y'}> +CONFIG_B43_PCI_AUTOSELECT policy<{'arm64': 'y'}> +CONFIG_B43_PHY_G policy<{'arm64': 'y'}> +CONFIG_B43_PHY_HT policy<{'arm64': 'y'}> +CONFIG_B43_PHY_LP policy<{'arm64': 'y'}> +CONFIG_B43_PHY_N policy<{'arm64': 'y'}> +CONFIG_B43_PIO policy<{'arm64': 'y'}> +CONFIG_B43_SDIO policy<{'arm64': 'n'}> +CONFIG_B43_SSB policy<{'arm64': 'y'}> +CONFIG_B44 policy<{'arm64': 'm'}> +CONFIG_B44_PCI policy<{'arm64': 'y'}> +CONFIG_B44_PCICORE_AUTOSELECT policy<{'arm64': 'y'}> +CONFIG_B44_PCI_AUTOSELECT policy<{'arm64': 'y'}> +CONFIG_B53 policy<{'arm64': 'm'}> +CONFIG_B53_MDIO_DRIVER policy<{'arm64': 'm'}> +CONFIG_B53_MMAP_DRIVER policy<{'arm64': 'm'}> +CONFIG_B53_SERDES policy<{'arm64': 'm'}> +CONFIG_B53_SPI_DRIVER policy<{'arm64': 'm'}> +CONFIG_B53_SRAB_DRIVER policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_88PM860X policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_AAT2870 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_ADP5520 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_ADP8860 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_ADP8870 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_APPLE_DWI policy<{'arm64': 'n'}> +CONFIG_BACKLIGHT_ARCXCNN policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_AS3711 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_AW99706 policy<{'arm64': 'n'}> +CONFIG_BACKLIGHT_BD6107 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_CLASS_DEVICE policy<{'arm64': 'y'}> +CONFIG_BACKLIGHT_DA903X policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_DA9052 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_GPIO policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_KTD253 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_KTD2801 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_KTZ8866 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_LED policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_LM3509 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_LM3533 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_LM3630A policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_LM3639 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_LP855X policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_LP8788 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_LV5207LP policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_MAX25014 policy<{'arm64': 'n'}> +CONFIG_BACKLIGHT_MAX8925 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_MP3309C policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_MT6370 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_PANDORA policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_PWM policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_QCOM_WLED policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_RAVE_SP policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_RT4831 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_SKY81452 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_TPS65217 policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_WM831X policy<{'arm64': 'm'}> +CONFIG_BACKTRACE_SELF_TEST policy<{'arm64': 'n'}> +CONFIG_BALLOON policy<{'arm64': 'y'}> +CONFIG_BALLOON_MIGRATION policy<{'arm64': 'y'}> +CONFIG_BAREUDP policy<{'arm64': 'm'}> +CONFIG_BASE_SMALL policy<{'arm64': 'n'}> +CONFIG_BASIC_MODVERSIONS policy<{'arm64': 'y'}> +CONFIG_BATMAN_ADV policy<{'arm64': 'm'}> +CONFIG_BATMAN_ADV_BATMAN_V policy<{'arm64': 'y'}> +CONFIG_BATMAN_ADV_BLA policy<{'arm64': 'y'}> +CONFIG_BATMAN_ADV_DAT policy<{'arm64': 'y'}> +CONFIG_BATMAN_ADV_DEBUG policy<{'arm64': 'n'}> +CONFIG_BATMAN_ADV_MCAST policy<{'arm64': 'y'}> +CONFIG_BATMAN_ADV_TRACING policy<{'arm64': 'n'}> +CONFIG_BATTERY_88PM860X policy<{'arm64': 'm'}> +CONFIG_BATTERY_ACT8945A policy<{'arm64': 'm'}> +CONFIG_BATTERY_AXP20X policy<{'arm64': 'm'}> +CONFIG_BATTERY_BQ27XXX policy<{'arm64': 'm'}> +CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM policy<{'arm64': 'n'}> +CONFIG_BATTERY_BQ27XXX_HDQ policy<{'arm64': 'm'}> +CONFIG_BATTERY_BQ27XXX_I2C policy<{'arm64': 'm'}> +CONFIG_BATTERY_CHAGALL policy<{'arm64': 'n'}> +CONFIG_BATTERY_CHARGER_SURFACE_RT policy<{'arm64': 'n'}> +CONFIG_BATTERY_CPCAP policy<{'arm64': 'm'}> +CONFIG_BATTERY_CW2015 policy<{'arm64': 'm'}> +CONFIG_BATTERY_DA9030 policy<{'arm64': 'm'}> +CONFIG_BATTERY_DA9052 policy<{'arm64': 'm'}> +CONFIG_BATTERY_DA9150 policy<{'arm64': 'm'}> +CONFIG_BATTERY_DS2760 policy<{'arm64': 'm'}> +CONFIG_BATTERY_DS2780 policy<{'arm64': 'm'}> +CONFIG_BATTERY_DS2781 policy<{'arm64': 'm'}> +CONFIG_BATTERY_DS2782 policy<{'arm64': 'm'}> +CONFIG_BATTERY_GAUGE_LTC2941 policy<{'arm64': 'm'}> +CONFIG_BATTERY_GOLDFISH policy<{'arm64': 'm'}> +CONFIG_BATTERY_HUAWEI_GAOKUN policy<{'arm64': 'n'}> +CONFIG_BATTERY_LENOVO_YOGA_C630 policy<{'arm64': 'm'}> +CONFIG_BATTERY_MAX17040 policy<{'arm64': 'm'}> +CONFIG_BATTERY_MAX17042 policy<{'arm64': 'm'}> +CONFIG_BATTERY_MAX1720X policy<{'arm64': 'm'}> +CONFIG_BATTERY_MAX1721X policy<{'arm64': 'm'}> +CONFIG_BATTERY_PM8916_BMS_VM policy<{'arm64': 'm'}> +CONFIG_BATTERY_QCOM_BATTMGR policy<{'arm64': 'm'}> +CONFIG_BATTERY_RT5033 policy<{'arm64': 'm'}> +CONFIG_BATTERY_RX51 policy<{'arm64': 'm'}> +CONFIG_BATTERY_S2MU005 policy<{'arm64': 'n'}> +CONFIG_BATTERY_SAMSUNG_SDI policy<{'arm64': 'y'}> +CONFIG_BATTERY_SBS policy<{'arm64': 'm'}> +CONFIG_BATTERY_SURFACE policy<{'arm64': 'm'}> +CONFIG_BATTERY_TWL4030_MADC policy<{'arm64': 'm'}> +CONFIG_BATTERY_UG3105 policy<{'arm64': 'm'}> +CONFIG_BCACHE policy<{'arm64': 'm'}> +CONFIG_BCACHE_ASYNC_REGISTRATION policy<{'arm64': 'y'}> +CONFIG_BCACHE_DEBUG policy<{'arm64': 'n'}> +CONFIG_BCH policy<{'arm64': 'm'}> +CONFIG_BCM54140_PHY policy<{'arm64': 'm'}> +CONFIG_BCM7XXX_PHY policy<{'arm64': 'm'}> +CONFIG_BCM84881_PHY policy<{'arm64': 'y'}> +CONFIG_BCM87XX_PHY policy<{'arm64': 'm'}> +CONFIG_BCMA policy<{'arm64': 'm'}> +CONFIG_BCMA_BLOCKIO policy<{'arm64': 'y'}> +CONFIG_BCMA_DEBUG policy<{'arm64': 'n'}> +CONFIG_BCMA_DRIVER_GMAC_CMN policy<{'arm64': 'y'}> +CONFIG_BCMA_DRIVER_GPIO policy<{'arm64': 'y'}> +CONFIG_BCMA_DRIVER_PCI policy<{'arm64': 'y'}> +CONFIG_BCMA_HOST_PCI policy<{'arm64': 'y'}> +CONFIG_BCMA_HOST_PCI_POSSIBLE policy<{'arm64': 'y'}> +CONFIG_BCMA_HOST_SOC policy<{'arm64': 'y'}> +CONFIG_BCMA_POSSIBLE policy<{'arm64': 'y'}> +CONFIG_BCMA_SFLASH policy<{'arm64': 'y'}> +CONFIG_BCMGENET policy<{'arm64': 'm'}> +CONFIG_BCM_KONA_USB2_PHY policy<{'arm64': 'm'}> +CONFIG_BCM_NET_PHYLIB policy<{'arm64': 'm'}> +CONFIG_BCM_NET_PHYPTP policy<{'arm64': 'm'}> +CONFIG_BCM_SBA_RAID policy<{'arm64': 'm'}> +CONFIG_BCM_VK policy<{'arm64': 'm'}> +CONFIG_BCM_VK_TTY policy<{'arm64': 'y'}> +CONFIG_BD79703 policy<{'arm64': 'm'}> +CONFIG_BD957XMUF_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_BD96801_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_BE2ISCSI policy<{'arm64': 'm'}> +CONFIG_BE2NET policy<{'arm64': 'm'}> +CONFIG_BE2NET_BE2 policy<{'arm64': 'y'}> +CONFIG_BE2NET_BE3 policy<{'arm64': 'y'}> +CONFIG_BE2NET_HWMON policy<{'arm64': 'y'}> +CONFIG_BE2NET_LANCER policy<{'arm64': 'y'}> +CONFIG_BE2NET_SKYHAWK policy<{'arm64': 'y'}> +CONFIG_BEFS_DEBUG policy<{'arm64': 'n'}> +CONFIG_BEFS_FS policy<{'arm64': 'm'}> +CONFIG_BERLIN2_ADC policy<{'arm64': 'm'}> +CONFIG_BFQ_CGROUP_DEBUG policy<{'arm64': 'n'}> +CONFIG_BFQ_GROUP_IOSCHED policy<{'arm64': 'y'}> +CONFIG_BFS_FS policy<{'arm64': 'm'}> +CONFIG_BH1745 policy<{'arm64': 'm'}> +CONFIG_BH1750 policy<{'arm64': 'm'}> +CONFIG_BH1780 policy<{'arm64': 'm'}> +CONFIG_BIG_KEYS policy<{'arm64': 'n'}> +CONFIG_BINARY_PRINTF policy<{'arm64': 'y'}> +CONFIG_BINFMT_ELF policy<{'arm64': 'y'}> +CONFIG_BINFMT_MISC policy<{'arm64': 'm'}> +CONFIG_BITREVERSE policy<{'arm64': 'y'}> +CONFIG_BLKDEV_UBLK_LEGACY_OPCODES policy<{'arm64': 'y'}> +CONFIG_BLK_CGROUP policy<{'arm64': 'y'}> +CONFIG_BLK_CGROUP_FC_APPID policy<{'arm64': 'y'}> +CONFIG_BLK_CGROUP_IOCOST policy<{'arm64': 'y'}> +CONFIG_BLK_CGROUP_IOLATENCY policy<{'arm64': 'n'}> +CONFIG_BLK_CGROUP_IOPRIO policy<{'arm64': 'y'}> +CONFIG_BLK_CGROUP_PUNT_BIO policy<{'arm64': 'y'}> +CONFIG_BLK_CGROUP_RWSTAT policy<{'arm64': 'y'}> +CONFIG_BLK_DEBUG_FS policy<{'arm64': 'y'}> +CONFIG_BLK_DEV policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_3W_XXXX_RAID policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_BSG policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_BSGLIB policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_BSG_COMMON policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_DM_BUILTIN policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_DRBD policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_INITRD policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_INTEGRITY policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_IO_TRACE policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_LOOP policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_LOOP_MIN_COUNT policy<{'arm64': '8'}> +CONFIG_BLK_DEV_MD policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_NBD policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_NULL_BLK policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_PCIESSD_MTIP32XX policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_PMEM policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_RAM_COUNT policy<{'arm64': '16'}> +CONFIG_BLK_DEV_RBD policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_RNBD policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_RNBD_CLIENT policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_RNBD_SERVER policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_UBLK policy<{'arm64': 'm'}> +CONFIG_BLK_DEV_WRITE_MOUNTED policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_ZONED policy<{'arm64': 'y'}> +CONFIG_BLK_DEV_ZONED_LOOP policy<{'arm64': 'n'}> +CONFIG_BLK_ERROR_INJECTION policy<{'arm64': 'n'}> +CONFIG_BLK_ICQ policy<{'arm64': 'y'}> +CONFIG_BLK_INLINE_ENCRYPTION policy<{'arm64': 'y'}> +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK policy<{'arm64': 'y'}> +CONFIG_BLK_MQ_STACKING policy<{'arm64': 'y'}> +CONFIG_BLK_PM policy<{'arm64': 'y'}> +CONFIG_BLK_RQ_ALLOC_TIME policy<{'arm64': 'y'}> +CONFIG_BLK_SED_OPAL policy<{'arm64': 'y'}> +CONFIG_BLK_WBT policy<{'arm64': 'y'}> +CONFIG_BLK_WBT_MQ policy<{'arm64': 'y'}> +CONFIG_BLOCK policy<{'arm64': 'y'}> +CONFIG_BLOCK_HOLDER_DEPRECATED policy<{'arm64': 'y'}> +CONFIG_BLOCK_LEGACY_AUTOLOAD policy<{'arm64': 'y'}> +CONFIG_BMA220 policy<{'arm64': 'm'}> +CONFIG_BMA220_I2C policy<{'arm64': 'm'}> +CONFIG_BMA220_SPI policy<{'arm64': 'm'}> +CONFIG_BMA400 policy<{'arm64': 'm'}> +CONFIG_BMA400_I2C policy<{'arm64': 'm'}> +CONFIG_BMA400_SPI policy<{'arm64': 'm'}> +CONFIG_BMC150_ACCEL policy<{'arm64': 'm'}> +CONFIG_BMC150_ACCEL_I2C policy<{'arm64': 'm'}> +CONFIG_BMC150_ACCEL_SPI policy<{'arm64': 'm'}> +CONFIG_BMC150_MAGN policy<{'arm64': 'm'}> +CONFIG_BMC150_MAGN_I2C policy<{'arm64': 'm'}> +CONFIG_BMC150_MAGN_SPI policy<{'arm64': 'm'}> +CONFIG_BME680 policy<{'arm64': 'm'}> +CONFIG_BME680_I2C policy<{'arm64': 'm'}> +CONFIG_BME680_SPI policy<{'arm64': 'm'}> +CONFIG_BMG160 policy<{'arm64': 'm'}> +CONFIG_BMG160_I2C policy<{'arm64': 'm'}> +CONFIG_BMG160_SPI policy<{'arm64': 'm'}> +CONFIG_BMI088_ACCEL policy<{'arm64': 'm'}> +CONFIG_BMI088_ACCEL_I2C policy<{'arm64': 'm'}> +CONFIG_BMI088_ACCEL_SPI policy<{'arm64': 'm'}> +CONFIG_BMI160 policy<{'arm64': 'm'}> +CONFIG_BMI160_I2C policy<{'arm64': 'm'}> +CONFIG_BMI160_SPI policy<{'arm64': 'm'}> +CONFIG_BMI270 policy<{'arm64': 'm'}> +CONFIG_BMI270_I2C policy<{'arm64': 'm'}> +CONFIG_BMI270_SPI policy<{'arm64': 'm'}> +CONFIG_BMI323 policy<{'arm64': 'm'}> +CONFIG_BMI323_I2C policy<{'arm64': 'm'}> +CONFIG_BMI323_SPI policy<{'arm64': 'm'}> +CONFIG_BMP280 policy<{'arm64': 'm'}> +CONFIG_BMP280_I2C policy<{'arm64': 'm'}> +CONFIG_BMP280_SPI policy<{'arm64': 'm'}> +CONFIG_BNA policy<{'arm64': 'm'}> +CONFIG_BNGE policy<{'arm64': 'n'}> +CONFIG_BNX2 policy<{'arm64': 'm'}> +CONFIG_BNX2X policy<{'arm64': 'm'}> +CONFIG_BNX2X_SRIOV policy<{'arm64': 'y'}> +CONFIG_BNXT policy<{'arm64': 'm'}> +CONFIG_BNXT_DCB policy<{'arm64': 'y'}> +CONFIG_BNXT_FLOWER_OFFLOAD policy<{'arm64': 'y'}> +CONFIG_BNXT_HWMON policy<{'arm64': 'y'}> +CONFIG_BNXT_SRIOV policy<{'arm64': 'y'}> +CONFIG_BOARD_TPCI200 policy<{'arm64': 'm'}> +CONFIG_BONDING policy<{'arm64': 'm'}> +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC policy<{'arm64': 'n'}> +CONFIG_BOOTPARAM_HUNG_TASK_PANIC policy<{'arm64': '0'}> +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC policy<{'arm64': '0'}> +CONFIG_BOOTTIME_TRACING policy<{'arm64': 'y'}> +CONFIG_BOOT_CONFIG policy<{'arm64': 'y'}> +CONFIG_BOOT_CONFIG_EMBED policy<{'arm64': 'n'}> +CONFIG_BOOT_CONFIG_FORCE policy<{'arm64': 'n'}> +CONFIG_BOOT_PRINTK_DELAY policy<{'arm64': 'y'}> +CONFIG_BOSCH_BNO055 policy<{'arm64': 'm'}> +CONFIG_BOSCH_BNO055_I2C policy<{'arm64': 'm'}> +CONFIG_BOSCH_BNO055_SERIAL policy<{'arm64': 'm'}> +CONFIG_BPF policy<{'arm64': 'y'}> +CONFIG_BPF_EVENTS policy<{'arm64': 'y'}> +CONFIG_BPF_JIT policy<{'arm64': 'y'}> +CONFIG_BPF_JIT_ALWAYS_ON policy<{'arm64': 'y'}> +CONFIG_BPF_JIT_DEFAULT_ON policy<{'arm64': 'y'}> +CONFIG_BPF_KPROBE_OVERRIDE policy<{'arm64': 'y'}> +CONFIG_BPF_LSM policy<{'arm64': 'y'}> +CONFIG_BPF_PRELOAD policy<{'arm64': 'n'}> +CONFIG_BPF_STREAM_PARSER policy<{'arm64': 'y'}> +CONFIG_BPF_SYSCALL policy<{'arm64': 'y'}> +CONFIG_BQL policy<{'arm64': 'y'}> +CONFIG_BRANCH_PROFILE_NONE policy<{'arm64': 'y'}> +CONFIG_BRCMDBG policy<{'arm64': 'n'}> +CONFIG_BRCMFMAC policy<{'arm64': 'm'}> +CONFIG_BRCMFMAC_PCIE policy<{'arm64': 'y'}> +CONFIG_BRCMFMAC_PROTO_BCDC policy<{'arm64': 'y'}> +CONFIG_BRCMFMAC_PROTO_MSGBUF policy<{'arm64': 'y'}> +CONFIG_BRCMFMAC_SDIO policy<{'arm64': 'y'}> +CONFIG_BRCMFMAC_USB policy<{'arm64': 'y'}> +CONFIG_BRCMSMAC policy<{'arm64': 'm'}> +CONFIG_BRCMSMAC_LEDS policy<{'arm64': 'y'}> +CONFIG_BRCMUTIL policy<{'arm64': 'm'}> +CONFIG_BRCM_TRACING policy<{'arm64': 'y'}> +CONFIG_BRIDGE policy<{'arm64': 'm'}> +CONFIG_BRIDGE_CFM policy<{'arm64': 'y'}> +CONFIG_BRIDGE_EBT_802_3 policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_AMONG policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_ARP policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_ARPREPLY policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_DNAT policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_IP policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_IP6 policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_LIMIT policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_LOG policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_MARK policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_MARK_T policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_NFLOG policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_PKTTYPE policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_REDIRECT policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_SNAT policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_STP policy<{'arm64': 'm'}> +CONFIG_BRIDGE_EBT_VLAN policy<{'arm64': 'm'}> +CONFIG_BRIDGE_IGMP_SNOOPING policy<{'arm64': 'y'}> +CONFIG_BRIDGE_MRP policy<{'arm64': 'y'}> +CONFIG_BRIDGE_NETFILTER policy<{'arm64': 'm'}> +CONFIG_BRIDGE_NF_EBTABLES policy<{'arm64': 'm'}> +CONFIG_BRIDGE_NF_EBTABLES_LEGACY policy<{'arm64': 'n'}> +CONFIG_BRIDGE_VLAN_FILTERING policy<{'arm64': 'y'}> +CONFIG_BROADCOM_PHY policy<{'arm64': 'm'}> +CONFIG_BSD_DISKLABEL policy<{'arm64': 'y'}> +CONFIG_BSD_PROCESS_ACCT policy<{'arm64': 'y'}> +CONFIG_BSD_PROCESS_ACCT_V3 policy<{'arm64': 'y'}> +CONFIG_BT policy<{'arm64': 'm'}> +CONFIG_BTREE policy<{'arm64': 'y'}> +CONFIG_BTRFS_ASSERT policy<{'arm64': 'n'}> +CONFIG_BTRFS_DEBUG policy<{'arm64': 'n'}> +CONFIG_BTRFS_EXPERIMENTAL policy<{'arm64': 'n'}> +CONFIG_BTRFS_FS policy<{'arm64': 'm'}> +CONFIG_BTRFS_FS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_BTRFS_FS_RUN_SANITY_TESTS policy<{'arm64': 'n'}> +CONFIG_BTT policy<{'arm64': 'y'}> +CONFIG_BT_6LOWPAN policy<{'arm64': 'm'}> +CONFIG_BT_AOSPEXT policy<{'arm64': 'y'}> +CONFIG_BT_ATH3K policy<{'arm64': 'm'}> +CONFIG_BT_BCM policy<{'arm64': 'm'}> +CONFIG_BT_BNEP policy<{'arm64': 'm'}> +CONFIG_BT_BNEP_MC_FILTER policy<{'arm64': 'y'}> +CONFIG_BT_BNEP_PROTO_FILTER policy<{'arm64': 'y'}> +CONFIG_BT_BREDR policy<{'arm64': 'y'}> +CONFIG_BT_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_BT_HCIBCM203X policy<{'arm64': 'm'}> +CONFIG_BT_HCIBCM4377 policy<{'arm64': 'm'}> +CONFIG_BT_HCIBFUSB policy<{'arm64': 'm'}> +CONFIG_BT_HCIBPA10X policy<{'arm64': 'm'}> +CONFIG_BT_HCIBTSDIO policy<{'arm64': 'm'}> +CONFIG_BT_HCIBTUSB policy<{'arm64': 'm'}> +CONFIG_BT_HCIBTUSB_AUTOSUSPEND policy<{'arm64': 'y'}> +CONFIG_BT_HCIBTUSB_BCM policy<{'arm64': 'y'}> +CONFIG_BT_HCIBTUSB_MTK policy<{'arm64': 'y'}> +CONFIG_BT_HCIBTUSB_POLL_SYNC policy<{'arm64': 'y'}> +CONFIG_BT_HCIBTUSB_RTL policy<{'arm64': 'y'}> +CONFIG_BT_HCIRSI policy<{'arm64': 'm'}> +CONFIG_BT_HCIUART policy<{'arm64': 'm'}> +CONFIG_BT_HCIUART_3WIRE policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_AG6XX policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_AML policy<{'arm64': 'n'}> +CONFIG_BT_HCIUART_ATH3K policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_BCM policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_BCSP policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_H4 policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_INTEL policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_LL policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_MRVL policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_NOKIA policy<{'arm64': 'm'}> +CONFIG_BT_HCIUART_QCA policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_RTL policy<{'arm64': 'y'}> +CONFIG_BT_HCIUART_SERDEV policy<{'arm64': 'y'}> +CONFIG_BT_HCIVHCI policy<{'arm64': 'm'}> +CONFIG_BT_HIDP policy<{'arm64': 'm'}> +CONFIG_BT_INTEL policy<{'arm64': 'm'}> +CONFIG_BT_INTEL_PCIE policy<{'arm64': 'm'}> +CONFIG_BT_LE policy<{'arm64': 'y'}> +CONFIG_BT_LEDS policy<{'arm64': 'y'}> +CONFIG_BT_LE_L2CAP_ECRED policy<{'arm64': 'y'}> +CONFIG_BT_MRVL policy<{'arm64': 'm'}> +CONFIG_BT_MRVL_SDIO policy<{'arm64': 'm'}> +CONFIG_BT_MSFTEXT policy<{'arm64': 'y'}> +CONFIG_BT_MTK policy<{'arm64': 'm'}> +CONFIG_BT_MTKSDIO policy<{'arm64': 'm'}> +CONFIG_BT_MTKUART policy<{'arm64': 'm'}> +CONFIG_BT_NXPUART policy<{'arm64': 'm'}> +CONFIG_BT_QCA policy<{'arm64': 'm'}> +CONFIG_BT_QCOMSMD policy<{'arm64': 'm'}> +CONFIG_BT_RFCOMM policy<{'arm64': 'm'}> +CONFIG_BT_RFCOMM_TTY policy<{'arm64': 'y'}> +CONFIG_BT_RTL policy<{'arm64': 'm'}> +CONFIG_BT_SELFTEST policy<{'arm64': 'n'}> +CONFIG_BT_VIRTIO policy<{'arm64': 'm'}> +CONFIG_BUFFER_HEAD policy<{'arm64': 'y'}> +CONFIG_BUG policy<{'arm64': 'y'}> +CONFIG_BUG_ON_DATA_CORRUPTION policy<{'arm64': 'n'}> +CONFIG_BUILDTIME_MCOUNT_SORT policy<{'arm64': 'y'}> +CONFIG_BUILDTIME_TABLE_SORT policy<{'arm64': 'y'}> +CONFIG_BUILD_SALT policy<{'arm64': '""'}> +CONFIG_BUILTIN_MODULE_RANGES policy<{'arm64': 'y'}> +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC policy<{'arm64': 'y'}> +CONFIG_C2PORT policy<{'arm64': 'm'}> +CONFIG_CACHEFILES policy<{'arm64': 'm'}> +CONFIG_CACHEFILES_DEBUG policy<{'arm64': 'n'}> +CONFIG_CACHEFILES_ERROR_INJECTION policy<{'arm64': 'y'}> +CONFIG_CACHEFILES_ONDEMAND policy<{'arm64': 'n'}> +CONFIG_CACHEMAINT_FOR_HOTPLUG policy<{'arm64': 'n'}> +CONFIG_CACHESTAT_SYSCALL policy<{'arm64': 'y'}> +CONFIG_CADENCE_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_CAN policy<{'arm64': 'm'}> +CONFIG_CAN_8DEV_USB policy<{'arm64': 'm'}> +CONFIG_CAN_BCM policy<{'arm64': 'm'}> +CONFIG_CAN_BXCAN policy<{'arm64': 'm'}> +CONFIG_CAN_CALC_BITTIMING policy<{'arm64': 'y'}> +CONFIG_CAN_CAN327 policy<{'arm64': 'm'}> +CONFIG_CAN_CC770 policy<{'arm64': 'm'}> +CONFIG_CAN_CC770_ISA policy<{'arm64': 'n'}> +CONFIG_CAN_CC770_PLATFORM policy<{'arm64': 'm'}> +CONFIG_CAN_CTUCANFD policy<{'arm64': 'm'}> +CONFIG_CAN_CTUCANFD_PCI policy<{'arm64': 'm'}> +CONFIG_CAN_CTUCANFD_PLATFORM policy<{'arm64': 'm'}> +CONFIG_CAN_C_CAN policy<{'arm64': 'm'}> +CONFIG_CAN_C_CAN_PCI policy<{'arm64': 'm'}> +CONFIG_CAN_C_CAN_PLATFORM policy<{'arm64': 'm'}> +CONFIG_CAN_DEBUG_DEVICES policy<{'arm64': 'n'}> +CONFIG_CAN_DEV policy<{'arm64': 'm'}> +CONFIG_CAN_DUMMY policy<{'arm64': 'n'}> +CONFIG_CAN_EMS_PCI policy<{'arm64': 'm'}> +CONFIG_CAN_EMS_PCMCIA policy<{'arm64': 'n'}> +CONFIG_CAN_EMS_USB policy<{'arm64': 'm'}> +CONFIG_CAN_ESD_402_PCI policy<{'arm64': 'm'}> +CONFIG_CAN_ESD_USB policy<{'arm64': 'm'}> +CONFIG_CAN_ETAS_ES58X policy<{'arm64': 'm'}> +CONFIG_CAN_F81601 policy<{'arm64': 'm'}> +CONFIG_CAN_F81604 policy<{'arm64': 'm'}> +CONFIG_CAN_FLEXCAN policy<{'arm64': 'm'}> +CONFIG_CAN_GRCAN policy<{'arm64': 'm'}> +CONFIG_CAN_GS_USB policy<{'arm64': 'm'}> +CONFIG_CAN_GW policy<{'arm64': 'm'}> +CONFIG_CAN_HI311X policy<{'arm64': 'm'}> +CONFIG_CAN_IFI_CANFD policy<{'arm64': 'm'}> +CONFIG_CAN_ISOTP policy<{'arm64': 'm'}> +CONFIG_CAN_J1939 policy<{'arm64': 'm'}> +CONFIG_CAN_JANZ_ICAN3 policy<{'arm64': 'm'}> +CONFIG_CAN_KVASER_PCI policy<{'arm64': 'm'}> +CONFIG_CAN_KVASER_PCIEFD policy<{'arm64': 'm'}> +CONFIG_CAN_KVASER_USB policy<{'arm64': 'm'}> +CONFIG_CAN_MCBA_USB policy<{'arm64': 'm'}> +CONFIG_CAN_MCP251X policy<{'arm64': 'm'}> +CONFIG_CAN_MCP251XFD policy<{'arm64': 'm'}> +CONFIG_CAN_MCP251XFD_SANITY policy<{'arm64': 'n'}> +CONFIG_CAN_M_CAN policy<{'arm64': 'm'}> +CONFIG_CAN_M_CAN_PCI policy<{'arm64': 'm'}> +CONFIG_CAN_M_CAN_PLATFORM policy<{'arm64': 'm'}> +CONFIG_CAN_M_CAN_TCAN4X5X policy<{'arm64': 'm'}> +CONFIG_CAN_NETLINK policy<{'arm64': 'y'}> +CONFIG_CAN_PEAK_PCI policy<{'arm64': 'm'}> +CONFIG_CAN_PEAK_PCIEC policy<{'arm64': 'y'}> +CONFIG_CAN_PEAK_PCIEFD policy<{'arm64': 'm'}> +CONFIG_CAN_PEAK_PCMCIA policy<{'arm64': 'n'}> +CONFIG_CAN_PEAK_USB policy<{'arm64': 'm'}> +CONFIG_CAN_PLX_PCI policy<{'arm64': 'm'}> +CONFIG_CAN_RAW policy<{'arm64': 'm'}> +CONFIG_CAN_RCAR policy<{'arm64': 'm'}> +CONFIG_CAN_RCAR_CANFD policy<{'arm64': 'm'}> +CONFIG_CAN_ROCKCHIP_CANFD policy<{'arm64': 'n'}> +CONFIG_CAN_RX_OFFLOAD policy<{'arm64': 'y'}> +CONFIG_CAN_SJA1000 policy<{'arm64': 'm'}> +CONFIG_CAN_SJA1000_ISA policy<{'arm64': 'n'}> +CONFIG_CAN_SJA1000_PLATFORM policy<{'arm64': 'm'}> +CONFIG_CAN_SLCAN policy<{'arm64': 'm'}> +CONFIG_CAN_SOFTING policy<{'arm64': 'm'}> +CONFIG_CAN_SOFTING_CS policy<{'arm64': 'n'}> +CONFIG_CAN_UCAN policy<{'arm64': 'm'}> +CONFIG_CAN_VCAN policy<{'arm64': 'm'}> +CONFIG_CAN_VIRTIO_CAN policy<{'arm64': 'n'}> +CONFIG_CAN_VXCAN policy<{'arm64': 'm'}> +CONFIG_CAN_XILINXCAN policy<{'arm64': 'm'}> +CONFIG_CARDBUS policy<{'arm64': 'y'}> +CONFIG_CARL9170 policy<{'arm64': 'm'}> +CONFIG_CARL9170_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_CARL9170_HWRNG policy<{'arm64': 'y'}> +CONFIG_CARL9170_LEDS policy<{'arm64': 'y'}> +CONFIG_CARL9170_WPC policy<{'arm64': 'y'}> +CONFIG_CARMINE_DRAM_CUSTOM policy<{'arm64': 'n'}> +CONFIG_CASSINI policy<{'arm64': 'm'}> +CONFIG_CAVIUM_CPT policy<{'arm64': 'm'}> +CONFIG_CAVIUM_ERRATUM_22375 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_23144 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_23154 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_27456 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_30115 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_PTP policy<{'arm64': 'm'}> +CONFIG_CAVIUM_TX2_ERRATUM_219 policy<{'arm64': 'y'}> +CONFIG_CB710_CORE policy<{'arm64': 'm'}> +CONFIG_CB710_DEBUG policy<{'arm64': 'n'}> +CONFIG_CB710_DEBUG_ASSUMPTIONS policy<{'arm64': 'y'}> +CONFIG_CC10001_ADC policy<{'arm64': 'm'}> +CONFIG_CCS811 policy<{'arm64': 'm'}> +CONFIG_CC_CAN_LINK policy<{'arm64': 'y'}> +CONFIG_CC_HAS_ASM_GOTO_OUTPUT policy<{'arm64': 'y'}> +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT policy<{'arm64': 'y'}> +CONFIG_CC_HAS_ASM_INLINE policy<{'arm64': 'y'}> +CONFIG_CC_HAS_ASSUME policy<{'arm64': 'y'}> +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN policy<{'arm64': 'y'}> +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO policy<{'arm64': 'y'}> +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE policy<{'arm64': 'y'}> +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET policy<{'arm64': 'y'}> +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI policy<{'arm64': 'y'}> +CONFIG_CC_HAS_COUNTED_BY policy<{'arm64': 'y'}> +CONFIG_CC_HAS_INT128 policy<{'arm64': 'y'}> +CONFIG_CC_HAS_KASAN_GENERIC policy<{'arm64': 'y'}> +CONFIG_CC_HAS_KASAN_SW_TAGS policy<{'arm64': 'y'}> +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT policy<{'arm64': 'y'}> +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING policy<{'arm64': 'y'}> +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR policy<{'arm64': 'y'}> +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT policy<{'arm64': 'y'}> +CONFIG_CC_HAS_UBSAN_BOUNDS_STRICT policy<{'arm64': 'y'}> +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS policy<{'arm64': 'y'}> +CONFIG_CC_HAS_ZERO_CALL_USED_REGS policy<{'arm64': 'y'}> +CONFIG_CC_HAVE_SHADOW_CALL_STACK policy<{'arm64': 'y'}> +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG policy<{'arm64': 'y'}> +CONFIG_CC_IMPLICIT_FALLTHROUGH policy<{'arm64': '"-Wimplicit-fallthrough=5"'}> +CONFIG_CC_IS_GCC policy<{'arm64': 'y'}> +CONFIG_CC_MS_EXTENSIONS policy<{'arm64': '"-fms-extensions"'}> +CONFIG_CC_NO_ARRAY_BOUNDS policy<{'arm64': 'y'}> +CONFIG_CC_NO_STRINGOP_OVERFLOW policy<{'arm64': 'y'}> +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE policy<{'arm64': 'y'}> +CONFIG_CC_OPTIMIZE_FOR_SIZE policy<{'arm64': 'n'}> +CONFIG_CC_VERSION_TEXT policy<{'arm64': '"aarch64-linux-gnu-gcc-15 (Ubuntu 15.2.0-16ubuntu1) 15.2.0"'}> +CONFIG_CDNS_I3C_MASTER policy<{'arm64': 'm'}> +CONFIG_CDROM policy<{'arm64': 'y'}> +CONFIG_CDX_BUS policy<{'arm64': 'y'}> +CONFIG_CDX_CONTROLLER policy<{'arm64': 'm'}> +CONFIG_CEC_CH7322 policy<{'arm64': 'm'}> +CONFIG_CEC_CORE policy<{'arm64': 'y'}> +CONFIG_CEC_CROS_EC policy<{'arm64': 'm'}> +CONFIG_CEC_GPIO policy<{'arm64': 'm'}> +CONFIG_CEC_MESON_AO policy<{'arm64': 'm'}> +CONFIG_CEC_MESON_G12A_AO policy<{'arm64': 'm'}> +CONFIG_CEC_NOTIFIER policy<{'arm64': 'y'}> +CONFIG_CEC_NXP_TDA9950 policy<{'arm64': 'm'}> +CONFIG_CEC_PIN policy<{'arm64': 'y'}> +CONFIG_CEC_PIN_ERROR_INJ policy<{'arm64': 'n'}> +CONFIG_CEC_STM32 policy<{'arm64': 'm'}> +CONFIG_CEC_TEGRA policy<{'arm64': 'm'}> +CONFIG_CEPH_FS policy<{'arm64': 'm'}> +CONFIG_CEPH_FSCACHE policy<{'arm64': 'y'}> +CONFIG_CEPH_FS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_CEPH_FS_SECURITY_LABEL policy<{'arm64': 'y'}> +CONFIG_CEPH_LIB policy<{'arm64': 'm'}> +CONFIG_CEPH_LIB_PRETTYDEBUG policy<{'arm64': 'n'}> +CONFIG_CEPH_LIB_USE_DNS_RESOLVER policy<{'arm64': 'y'}> +CONFIG_CFG80211 policy<{'arm64': 'm'}> +CONFIG_CFG80211_CERTIFICATION_ONUS policy<{'arm64': 'n'}> +CONFIG_CFG80211_CRDA_SUPPORT policy<{'arm64': 'y'}> +CONFIG_CFG80211_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_CFG80211_DEFAULT_PS policy<{'arm64': 'y'}> +CONFIG_CFG80211_DEVELOPER_WARNINGS policy<{'arm64': 'n'}> +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB policy<{'arm64': 'y'}> +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS policy<{'arm64': 'y'}> +CONFIG_CFG80211_WEXT policy<{'arm64': 'y'}> +CONFIG_CFS_BANDWIDTH policy<{'arm64': 'y'}> +CONFIG_CGROUPS policy<{'arm64': 'y'}> +CONFIG_CGROUP_BPF policy<{'arm64': 'y'}> +CONFIG_CGROUP_CPUACCT policy<{'arm64': 'y'}> +CONFIG_CGROUP_DEBUG policy<{'arm64': 'n'}> +CONFIG_CGROUP_DEVICE policy<{'arm64': 'y'}> +CONFIG_CGROUP_DMEM policy<{'arm64': 'n'}> +CONFIG_CGROUP_FAVOR_DYNMODS policy<{'arm64': 'n'}> +CONFIG_CGROUP_FREEZER policy<{'arm64': 'y'}> +CONFIG_CGROUP_HUGETLB policy<{'arm64': 'y'}> +CONFIG_CGROUP_MISC policy<{'arm64': 'y'}> +CONFIG_CGROUP_NET_CLASSID policy<{'arm64': 'y'}> +CONFIG_CGROUP_NET_PRIO policy<{'arm64': 'y'}> +CONFIG_CGROUP_PERF policy<{'arm64': 'y'}> +CONFIG_CGROUP_PIDS policy<{'arm64': 'y'}> +CONFIG_CGROUP_RDMA policy<{'arm64': 'y'}> +CONFIG_CGROUP_SCHED policy<{'arm64': 'y'}> +CONFIG_CGROUP_WRITEBACK policy<{'arm64': 'y'}> +CONFIG_CHARGER_88PM860X policy<{'arm64': 'm'}> +CONFIG_CHARGER_ADP5061 policy<{'arm64': 'm'}> +CONFIG_CHARGER_AXP20X policy<{'arm64': 'm'}> +CONFIG_CHARGER_BD71828 policy<{'arm64': 'n'}> +CONFIG_CHARGER_BD99954 policy<{'arm64': 'm'}> +CONFIG_CHARGER_BQ2415X policy<{'arm64': 'm'}> +CONFIG_CHARGER_BQ24190 policy<{'arm64': 'm'}> +CONFIG_CHARGER_BQ24257 policy<{'arm64': 'm'}> +CONFIG_CHARGER_BQ24735 policy<{'arm64': 'm'}> +CONFIG_CHARGER_BQ2515X policy<{'arm64': 'm'}> +CONFIG_CHARGER_BQ256XX policy<{'arm64': 'm'}> +CONFIG_CHARGER_BQ25890 policy<{'arm64': 'm'}> +CONFIG_CHARGER_BQ25980 policy<{'arm64': 'm'}> +CONFIG_CHARGER_CPCAP policy<{'arm64': 'm'}> +CONFIG_CHARGER_CROS_CONTROL policy<{'arm64': 'm'}> +CONFIG_CHARGER_CROS_PCHG policy<{'arm64': 'm'}> +CONFIG_CHARGER_CROS_USBPD policy<{'arm64': 'm'}> +CONFIG_CHARGER_DA9150 policy<{'arm64': 'm'}> +CONFIG_CHARGER_DETECTOR_MAX14656 policy<{'arm64': 'm'}> +CONFIG_CHARGER_GPIO policy<{'arm64': 'm'}> +CONFIG_CHARGER_ISP1704 policy<{'arm64': 'm'}> +CONFIG_CHARGER_LP8727 policy<{'arm64': 'm'}> +CONFIG_CHARGER_LP8788 policy<{'arm64': 'm'}> +CONFIG_CHARGER_LT3651 policy<{'arm64': 'm'}> +CONFIG_CHARGER_LTC4162L policy<{'arm64': 'm'}> +CONFIG_CHARGER_MANAGER policy<{'arm64': 'y'}> +CONFIG_CHARGER_MAX14577 policy<{'arm64': 'm'}> +CONFIG_CHARGER_MAX77650 policy<{'arm64': 'm'}> +CONFIG_CHARGER_MAX77693 policy<{'arm64': 'm'}> +CONFIG_CHARGER_MAX77976 policy<{'arm64': 'm'}> +CONFIG_CHARGER_MAX8903 policy<{'arm64': 'm'}> +CONFIG_CHARGER_MAX8971 policy<{'arm64': 'n'}> +CONFIG_CHARGER_MAX8997 policy<{'arm64': 'm'}> +CONFIG_CHARGER_MAX8998 policy<{'arm64': 'm'}> +CONFIG_CHARGER_MP2629 policy<{'arm64': 'm'}> +CONFIG_CHARGER_MT6360 policy<{'arm64': 'm'}> +CONFIG_CHARGER_MT6370 policy<{'arm64': 'm'}> +CONFIG_CHARGER_PM8916_LBC policy<{'arm64': 'm'}> +CONFIG_CHARGER_QCOM_SMB2 policy<{'arm64': 'm'}> +CONFIG_CHARGER_QCOM_SMBB policy<{'arm64': 'm'}> +CONFIG_CHARGER_RK817 policy<{'arm64': 'm'}> +CONFIG_CHARGER_RT5033 policy<{'arm64': 'm'}> +CONFIG_CHARGER_RT9455 policy<{'arm64': 'm'}> +CONFIG_CHARGER_RT9467 policy<{'arm64': 'm'}> +CONFIG_CHARGER_RT9471 policy<{'arm64': 'm'}> +CONFIG_CHARGER_RT9756 policy<{'arm64': 'n'}> +CONFIG_CHARGER_SBS policy<{'arm64': 'm'}> +CONFIG_CHARGER_SC2731 policy<{'arm64': 'm'}> +CONFIG_CHARGER_SMB347 policy<{'arm64': 'm'}> +CONFIG_CHARGER_SURFACE policy<{'arm64': 'm'}> +CONFIG_CHARGER_TPS65090 policy<{'arm64': 'm'}> +CONFIG_CHARGER_TPS65217 policy<{'arm64': 'm'}> +CONFIG_CHARGER_TWL4030 policy<{'arm64': 'm'}> +CONFIG_CHARGER_TWL6030 policy<{'arm64': 'm'}> +CONFIG_CHARGER_UCS1002 policy<{'arm64': 'm'}> +CONFIG_CHARLCD policy<{'arm64': 'm'}> +CONFIG_CHARLCD_BL_FLASH policy<{'arm64': 'y'}> +CONFIG_CHARLCD_BL_OFF policy<{'arm64': 'n'}> +CONFIG_CHARLCD_BL_ON policy<{'arm64': 'n'}> +CONFIG_CHECKPOINT_RESTORE policy<{'arm64': 'y'}> +CONFIG_CHECK_SIGNATURE policy<{'arm64': 'y'}> +CONFIG_CHELSIO_INLINE_CRYPTO policy<{'arm64': 'y'}> +CONFIG_CHELSIO_IPSEC_INLINE policy<{'arm64': 'm'}> +CONFIG_CHELSIO_LIB policy<{'arm64': 'm'}> +CONFIG_CHELSIO_T1 policy<{'arm64': 'm'}> +CONFIG_CHELSIO_T1_1G policy<{'arm64': 'y'}> +CONFIG_CHELSIO_T3 policy<{'arm64': 'm'}> +CONFIG_CHELSIO_T4 policy<{'arm64': 'm'}> +CONFIG_CHELSIO_T4VF policy<{'arm64': 'm'}> +CONFIG_CHELSIO_T4_DCB policy<{'arm64': 'y'}> +CONFIG_CHELSIO_T4_FCOE policy<{'arm64': 'y'}> +CONFIG_CHELSIO_TLS_DEVICE policy<{'arm64': 'm'}> +CONFIG_CHROMEOS_ACPI policy<{'arm64': 'm'}> +CONFIG_CHROMEOS_OF_HW_PROBER policy<{'arm64': 'y'}> +CONFIG_CHROMEOS_PRIVACY_SCREEN policy<{'arm64': 'm'}> +CONFIG_CHROMEOS_TBMC policy<{'arm64': 'm'}> +CONFIG_CHROME_PLATFORMS policy<{'arm64': 'y'}> +CONFIG_CHR_DEV_SCH policy<{'arm64': 'm'}> +CONFIG_CHR_DEV_ST policy<{'arm64': 'm'}> +CONFIG_CICADA_PHY policy<{'arm64': 'm'}> +CONFIG_CIFS policy<{'arm64': 'm'}> +CONFIG_CIFS_ALLOW_INSECURE_LEGACY policy<{'arm64': 'y'}> +CONFIG_CIFS_COMPRESSION policy<{'arm64': 'n'}> +CONFIG_CIFS_DEBUG policy<{'arm64': 'y'}> +CONFIG_CIFS_DEBUG2 policy<{'arm64': 'n'}> +CONFIG_CIFS_DEBUG_DUMP_KEYS policy<{'arm64': 'n'}> +CONFIG_CIFS_DFS_UPCALL policy<{'arm64': 'y'}> +CONFIG_CIFS_FSCACHE policy<{'arm64': 'y'}> +CONFIG_CIFS_POSIX policy<{'arm64': 'y'}> +CONFIG_CIFS_SMB_DIRECT policy<{'arm64': 'n'}> +CONFIG_CIFS_STATS2 policy<{'arm64': 'y'}> +CONFIG_CIFS_SWN_UPCALL policy<{'arm64': 'y'}> +CONFIG_CIFS_UPCALL policy<{'arm64': 'y'}> +CONFIG_CIFS_XATTR policy<{'arm64': 'y'}> +CONFIG_CLANG_VERSION policy<{'arm64': '0'}> +CONFIG_CLKSRC_MMIO policy<{'arm64': 'y'}> +CONFIG_CLKSRC_STM32_LP policy<{'arm64': 'y'}> +CONFIG_CLK_ACTIONS policy<{'arm64': 'y'}> +CONFIG_CLK_ELIZA_DISPCC policy<{'arm64': 'n'}> +CONFIG_CLK_ELIZA_GCC policy<{'arm64': 'n'}> +CONFIG_CLK_ELIZA_TCSRCC policy<{'arm64': 'n'}> +CONFIG_CLK_GFM_LPASS_SM8250 policy<{'arm64': 'm'}> +CONFIG_CLK_GLYMUR_DISPCC policy<{'arm64': 'n'}> +CONFIG_CLK_GLYMUR_GCC policy<{'arm64': 'n'}> +CONFIG_CLK_GLYMUR_GPUCC policy<{'arm64': 'n'}> +CONFIG_CLK_GLYMUR_TCSRCC policy<{'arm64': 'n'}> +CONFIG_CLK_GLYMUR_VIDEOCC policy<{'arm64': 'n'}> +CONFIG_CLK_HAWI_GCC policy<{'arm64': 'n'}> +CONFIG_CLK_HAWI_TCSRCC policy<{'arm64': 'n'}> +CONFIG_CLK_ICST policy<{'arm64': 'y'}> +CONFIG_CLK_IMX8MM policy<{'arm64': 'y'}> +CONFIG_CLK_IMX8MN policy<{'arm64': 'y'}> +CONFIG_CLK_IMX8MP policy<{'arm64': 'y'}> +CONFIG_CLK_IMX8MQ policy<{'arm64': 'y'}> +CONFIG_CLK_IMX8QXP policy<{'arm64': 'y'}> +CONFIG_CLK_IMX8ULP policy<{'arm64': 'm'}> +CONFIG_CLK_IMX93 policy<{'arm64': 'm'}> +CONFIG_CLK_IMX95_BLK_CTL policy<{'arm64': 'm'}> +CONFIG_CLK_INTEL_SOCFPGA policy<{'arm64': 'y'}> +CONFIG_CLK_INTEL_SOCFPGA64 policy<{'arm64': 'y'}> +CONFIG_CLK_KAANAPALI_CAMCC policy<{'arm64': 'n'}> +CONFIG_CLK_KAANAPALI_DISPCC policy<{'arm64': 'n'}> +CONFIG_CLK_KAANAPALI_GCC policy<{'arm64': 'n'}> +CONFIG_CLK_KAANAPALI_GPUCC policy<{'arm64': 'n'}> +CONFIG_CLK_KAANAPALI_TCSRCC policy<{'arm64': 'n'}> +CONFIG_CLK_KAANAPALI_VIDEOCC policy<{'arm64': 'n'}> +CONFIG_CLK_LS1028A_PLLDIG policy<{'arm64': 'm'}> +CONFIG_CLK_MA35D1 policy<{'arm64': 'y'}> +CONFIG_CLK_NORD_GCC policy<{'arm64': 'n'}> +CONFIG_CLK_NORD_TCSRCC policy<{'arm64': 'n'}> +CONFIG_CLK_OWL_S500 policy<{'arm64': 'y'}> +CONFIG_CLK_OWL_S700 policy<{'arm64': 'y'}> +CONFIG_CLK_OWL_S900 policy<{'arm64': 'y'}> +CONFIG_CLK_PX30 policy<{'arm64': 'y'}> +CONFIG_CLK_QCM2290_GPUCC policy<{'arm64': 'm'}> +CONFIG_CLK_QORIQ policy<{'arm64': 'y'}> +CONFIG_CLK_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A7795 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77960 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77961 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77965 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77970 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77980 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77990 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77995 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A07G043 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A07G044 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A07G054 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A08G045 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A08G046 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G011 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G056 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G057 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G077 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G087 policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_CPG_LIB policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_GEN3_CPG policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_GEN4_CPG policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_USB2_CLOCK_SEL policy<{'arm64': 'y'}> +CONFIG_CLK_RENESAS policy<{'arm64': 'y'}> +CONFIG_CLK_RENESAS_CPG_MSSR policy<{'arm64': 'y'}> +CONFIG_CLK_RENESAS_DIV6 policy<{'arm64': 'y'}> +CONFIG_CLK_RENESAS_VBATTB policy<{'arm64': 'm'}> +CONFIG_CLK_RK3308 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3328 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3368 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3399 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3528 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3562 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3568 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3576 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3588 policy<{'arm64': 'y'}> +CONFIG_CLK_RV1126B policy<{'arm64': 'y'}> +CONFIG_CLK_RZG2L policy<{'arm64': 'y'}> +CONFIG_CLK_RZV2H policy<{'arm64': 'y'}> +CONFIG_CLK_SP810 policy<{'arm64': 'y'}> +CONFIG_CLK_TEGRA_BPMP policy<{'arm64': 'y'}> +CONFIG_CLK_TWL policy<{'arm64': 'm'}> +CONFIG_CLK_TWL6040 policy<{'arm64': 'm'}> +CONFIG_CLK_VEXPRESS_OSC policy<{'arm64': 'y'}> +CONFIG_CLK_X1E80100_CAMCC policy<{'arm64': 'y'}> +CONFIG_CLK_X1E80100_DISPCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1E80100_GCC policy<{'arm64': 'y'}> +CONFIG_CLK_X1E80100_GPUCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1E80100_TCSRCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1P42100_CAMCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1P42100_GPUCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1P42100_VIDEOCC policy<{'arm64': 'm'}> +CONFIG_CLONE_BACKWARDS policy<{'arm64': 'y'}> +CONFIG_CLOSURES policy<{'arm64': 'y'}> +CONFIG_CLS_U32_MARK policy<{'arm64': 'y'}> +CONFIG_CLS_U32_PERF policy<{'arm64': 'n'}> +CONFIG_CLZ_TAB policy<{'arm64': 'y'}> +CONFIG_CM32181 policy<{'arm64': 'm'}> +CONFIG_CM3232 policy<{'arm64': 'm'}> +CONFIG_CM3323 policy<{'arm64': 'm'}> +CONFIG_CM3605 policy<{'arm64': 'm'}> +CONFIG_CM36651 policy<{'arm64': 'm'}> +CONFIG_CMA_ALIGNMENT policy<{'arm64': '8'}> +CONFIG_CMA_AREAS policy<{'arm64': '7'}> +CONFIG_CMA_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_CMA_SIZE_PERNUMA policy<{'arm64': 'y'}> +CONFIG_CMA_SIZE_SEL_MAX policy<{'arm64': 'n'}> +CONFIG_CMA_SIZE_SEL_MBYTES policy<{'arm64': 'y'}> +CONFIG_CMA_SIZE_SEL_MIN policy<{'arm64': 'n'}> +CONFIG_CMA_SIZE_SEL_PERCENTAGE policy<{'arm64': 'n'}> +CONFIG_CMA_SYSFS policy<{'arm64': 'y'}> +CONFIG_CMDLINE policy<{'arm64': '"console=ttyAMA0"'}> +CONFIG_CMDLINE_FORCE policy<{'arm64': 'n'}> +CONFIG_CMDLINE_FROM_BOOTLOADER policy<{'arm64': 'y'}> +CONFIG_CMDLINE_LOG_WRAP_IDEAL_LEN policy<{'arm64': '1021'}> +CONFIG_CMDLINE_PARTITION policy<{'arm64': 'y'}> +CONFIG_CNIC policy<{'arm64': 'm'}> +CONFIG_CODA_FS policy<{'arm64': 'm'}> +CONFIG_COMEDI policy<{'arm64': 'm'}> +CONFIG_COMEDI_8254 policy<{'arm64': 'm'}> +CONFIG_COMEDI_8255 policy<{'arm64': 'm'}> +CONFIG_COMEDI_8255_PCI policy<{'arm64': 'm'}> +CONFIG_COMEDI_8255_SA policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1032 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1500 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1516 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1564 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_16XX policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_2032 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_2200 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_3120 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_3501 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_3XXX policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADDI_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADL_PCI6208 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADL_PCI7250 policy<{'arm64': 'n'}> +CONFIG_COMEDI_ADL_PCI7X3X policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADL_PCI8164 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADL_PCI9111 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADL_PCI9118 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADQ12B policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADV_PCI1710 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADV_PCI1720 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADV_PCI1723 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADV_PCI1724 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADV_PCI1760 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ADV_PCI_DIO policy<{'arm64': 'm'}> +CONFIG_COMEDI_AIO_AIO12_8 policy<{'arm64': 'm'}> +CONFIG_COMEDI_AIO_IIRO_16 policy<{'arm64': 'm'}> +CONFIG_COMEDI_AMPLC_DIO200 policy<{'arm64': 'm'}> +CONFIG_COMEDI_AMPLC_DIO200_ISA policy<{'arm64': 'm'}> +CONFIG_COMEDI_AMPLC_DIO200_PCI policy<{'arm64': 'm'}> +CONFIG_COMEDI_AMPLC_PC236 policy<{'arm64': 'm'}> +CONFIG_COMEDI_AMPLC_PC236_ISA policy<{'arm64': 'm'}> +CONFIG_COMEDI_AMPLC_PC236_PCI policy<{'arm64': 'm'}> +CONFIG_COMEDI_AMPLC_PC263_ISA policy<{'arm64': 'm'}> +CONFIG_COMEDI_AMPLC_PC263_PCI policy<{'arm64': 'm'}> +CONFIG_COMEDI_AMPLC_PCI224 policy<{'arm64': 'm'}> +CONFIG_COMEDI_AMPLC_PCI230 policy<{'arm64': 'm'}> +CONFIG_COMEDI_BOND policy<{'arm64': 'm'}> +CONFIG_COMEDI_C6XDIGIO policy<{'arm64': 'm'}> +CONFIG_COMEDI_CB_PCIDAS policy<{'arm64': 'm'}> +CONFIG_COMEDI_CB_PCIDAS64 policy<{'arm64': 'm'}> +CONFIG_COMEDI_CB_PCIDDA policy<{'arm64': 'm'}> +CONFIG_COMEDI_CB_PCIMDAS policy<{'arm64': 'm'}> +CONFIG_COMEDI_CB_PCIMDDA policy<{'arm64': 'm'}> +CONFIG_COMEDI_CONTEC_PCI_DIO policy<{'arm64': 'm'}> +CONFIG_COMEDI_DAC02 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DAQBOARD2000 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DAS08 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DAS08_ISA policy<{'arm64': 'm'}> +CONFIG_COMEDI_DAS08_PCI policy<{'arm64': 'm'}> +CONFIG_COMEDI_DAS16 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DAS16M1 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DAS1800 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DAS6402 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DAS800 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DEBUG policy<{'arm64': 'n'}> +CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB policy<{'arm64': '20480'}> +CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB policy<{'arm64': '2048'}> +CONFIG_COMEDI_DMM32AT policy<{'arm64': 'm'}> +CONFIG_COMEDI_DT2801 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DT2811 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DT2814 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DT2815 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DT2817 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DT282X policy<{'arm64': 'm'}> +CONFIG_COMEDI_DT3000 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DT9812 policy<{'arm64': 'm'}> +CONFIG_COMEDI_DYNA_PCI10XX policy<{'arm64': 'm'}> +CONFIG_COMEDI_FL512 policy<{'arm64': 'm'}> +CONFIG_COMEDI_GSC_HPDI policy<{'arm64': 'm'}> +CONFIG_COMEDI_ICP_MULTI policy<{'arm64': 'm'}> +CONFIG_COMEDI_II_PCI20KC policy<{'arm64': 'm'}> +CONFIG_COMEDI_ISA_DRIVERS policy<{'arm64': 'y'}> +CONFIG_COMEDI_JR3_PCI policy<{'arm64': 'm'}> +CONFIG_COMEDI_KCOMEDILIB policy<{'arm64': 'm'}> +CONFIG_COMEDI_KE_COUNTER policy<{'arm64': 'm'}> +CONFIG_COMEDI_ME4000 policy<{'arm64': 'm'}> +CONFIG_COMEDI_ME_DAQ policy<{'arm64': 'm'}> +CONFIG_COMEDI_MF6X4 policy<{'arm64': 'm'}> +CONFIG_COMEDI_MISC_DRIVERS policy<{'arm64': 'y'}> +CONFIG_COMEDI_MITE policy<{'arm64': 'm'}> +CONFIG_COMEDI_MPC624 policy<{'arm64': 'm'}> +CONFIG_COMEDI_MULTIQ3 policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_6527 policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_65XX policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_660X policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_670X policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_ATMIO policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_ATMIO16D policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_AT_A2150 policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_AT_AO policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_LABPC policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_LABPC_ISA policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_LABPC_PCI policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_PCIDIO policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_PCIMIO policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_ROUTING policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_TIO policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_TIOCMD policy<{'arm64': 'm'}> +CONFIG_COMEDI_NI_USB6501 policy<{'arm64': 'm'}> +CONFIG_COMEDI_PARPORT policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCI_DRIVERS policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCL711 policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCL724 policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCL726 policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCL730 policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCL812 policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCL816 policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCL818 policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCM3724 policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCMAD policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCMCIA_DRIVERS policy<{'arm64': 'n'}> +CONFIG_COMEDI_PCMDA12 policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCMMIO policy<{'arm64': 'm'}> +CONFIG_COMEDI_PCMUIO policy<{'arm64': 'm'}> +CONFIG_COMEDI_RTD520 policy<{'arm64': 'm'}> +CONFIG_COMEDI_RTI800 policy<{'arm64': 'm'}> +CONFIG_COMEDI_RTI802 policy<{'arm64': 'm'}> +CONFIG_COMEDI_S526 policy<{'arm64': 'm'}> +CONFIG_COMEDI_S626 policy<{'arm64': 'm'}> +CONFIG_COMEDI_TEST policy<{'arm64': 'm'}> +CONFIG_COMEDI_TESTS policy<{'arm64': 'm'}> +CONFIG_COMEDI_TESTS_EXAMPLE policy<{'arm64': 'm'}> +CONFIG_COMEDI_TESTS_NI_ROUTES policy<{'arm64': 'm'}> +CONFIG_COMEDI_USBDUX policy<{'arm64': 'm'}> +CONFIG_COMEDI_USBDUXFAST policy<{'arm64': 'm'}> +CONFIG_COMEDI_USBDUXSIGMA policy<{'arm64': 'm'}> +CONFIG_COMEDI_USB_DRIVERS policy<{'arm64': 'm'}> +CONFIG_COMEDI_VMK80XX policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_A1_PERIPHERALS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_A1_PLL policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_APPLE_NCO policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_AXG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_AXG_AUDIO policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_AXI_CLKGEN policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_BD718XX policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_BM1880 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_C3_PERIPHERALS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_C3_PLL policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_CDCE706 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_CDCE925 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_CS2000_CP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_EN7523 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_FIXED_MMIO policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_FSL_FLEXSPI policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_FSL_SAI policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_G12A policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_GXBB policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_HI3516CV300 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_HI3519 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_HI3559A policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_HI3660 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_HI3670 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_HI3798CV200 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_HI6220 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_HI655X policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_LOCHNAGAR policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MAX77686 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MAX9485 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MEDIATEK policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MEDIATEK_FHCTL policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_AO_CLKC policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_CLKC_UTILS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_CPU_DYNDIV policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_DUALDIV policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_MPLL policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_PHASE policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MESON_PLL policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_REGMAP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_SCLK_DIV policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MESON_VCLK policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_VID_PLL_DIV policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_BDPSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_JPGDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6735 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT6735_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT6735_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT6735_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT6735_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT6765 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_AUDIOSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_GCESYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MFGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI0ASYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI0BSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI1ASYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI1BSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI2ASYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI2BSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_VCODECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_IPESYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6795 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT6795_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT6795_MMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT6795_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT6795_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT6797 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT7622 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT7622_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT7622_ETHSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT7622_HIFSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT7981 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT7981_ETHSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT7986 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT7986_ETHSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT7988 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8167 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8173 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8173_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8173_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8173_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8173_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8183 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_AUDIOSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_ADL policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_CONN policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_CORE0 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_CORE1 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8186 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8186_CAMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_IPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MCUSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MDPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_WPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_ADSP_AUDIO26M policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_CAMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_IPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VDOSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VPPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_WPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8192 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_IPESYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MDPSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MSDC policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_SCP_ADSP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8195 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8195_APUSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_CAMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_IPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_SCP_ADSP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VDOSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VPPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_WPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8196_MCUSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8196_MDPSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8196_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_MMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_PEXTPSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8196_UFSSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8196_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8365 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8365_APU policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8365_CAM policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8365_MFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8365_MMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8365_VDEC policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8365_VENC policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8516 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8516_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_NPCM8XX policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_NUVOTON policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_PALMAS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_PWM policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_QCOM policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_RK808 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_ROCKCHIP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_RS9_PCIE policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_S4_PERIPHERALS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_S4_PLL policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_SCMI policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_SCPI policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_SI514 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_SI521XX policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_SI5341 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_SI5351 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_SI544 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_SI570 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_STM32MP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_STM32MP215 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_STM32MP257 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_T7_PERIPHERALS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_T7_PLL policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_VC3 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_VC5 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_VC7 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_VISCONTI policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_WM831X policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_XGENE policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_XLNX_CLKWZRD policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_COMMON_RESET_HI3660 policy<{'arm64': 'm'}> +CONFIG_COMMON_RESET_HI6220 policy<{'arm64': 'm'}> +CONFIG_COMPACTION policy<{'arm64': 'y'}> +CONFIG_COMPACT_UNEVICTABLE_DEFAULT policy<{'arm64': '1'}> +CONFIG_COMPAT policy<{'arm64': 'y'}> +CONFIG_COMPAT_32BIT_TIME policy<{'arm64': 'y'}> +CONFIG_COMPAT_ALIGNMENT_FIXUPS policy<{'arm64': 'n'}> +CONFIG_COMPAT_BINFMT_ELF policy<{'arm64': 'y'}> +CONFIG_COMPAT_BRK policy<{'arm64': 'y'}> +CONFIG_COMPAT_NETLINK_MESSAGES policy<{'arm64': 'y'}> +CONFIG_COMPAT_OLD_SIGACTION policy<{'arm64': 'y'}> +CONFIG_COMPILE_TEST policy<{'arm64': 'n'}> +CONFIG_COMPRESSED_INSTALL policy<{'arm64': 'n'}> +CONFIG_CONFIGFS_FS policy<{'arm64': 'y'}> +CONFIG_CONNECTOR policy<{'arm64': 'y'}> +CONFIG_CONSOLE_LOGLEVEL_DEFAULT policy<{'arm64': '7'}> +CONFIG_CONSOLE_POLL policy<{'arm64': 'y'}> +CONFIG_CONSOLE_TRANSLATIONS policy<{'arm64': 'y'}> +CONFIG_CONTEXT_ANALYSIS_TEST policy<{'arm64': 'n'}> +CONFIG_CONTEXT_SWITCH_TRACER policy<{'arm64': 'y'}> +CONFIG_CONTEXT_TRACKING policy<{'arm64': 'y'}> +CONFIG_CONTEXT_TRACKING_IDLE policy<{'arm64': 'y'}> +CONFIG_CONTEXT_TRACKING_USER policy<{'arm64': 'y'}> +CONFIG_CONTEXT_TRACKING_USER_FORCE policy<{'arm64': 'n'}> +CONFIG_CONTIG_ALLOC policy<{'arm64': 'y'}> +CONFIG_CORDIC policy<{'arm64': 'm'}> +CONFIG_COREDUMP policy<{'arm64': 'y'}> +CONFIG_CORESIGHT policy<{'arm64': 'n'}> +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS policy<{'arm64': 'y'}> +CONFIG_CORTINA_PHY policy<{'arm64': 'm'}> +CONFIG_COUNTER policy<{'arm64': 'm'}> +CONFIG_CPCAP_ADC policy<{'arm64': 'm'}> +CONFIG_CPM_TSA policy<{'arm64': 'n'}> +CONFIG_CPUFREQ_DT_PLATDEV policy<{'arm64': 'y'}> +CONFIG_CPUFREQ_VIRT policy<{'arm64': 'n'}> +CONFIG_CPUMASK_OFFSTACK policy<{'arm64': 'y'}> +CONFIG_CPUSETS policy<{'arm64': 'y'}> +CONFIG_CPUSETS_V1 policy<{'arm64': 'n'}> +CONFIG_CPU_FREQ policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE policy<{'arm64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND policy<{'arm64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE policy<{'arm64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE policy<{'arm64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE policy<{'arm64': 'n'}> +CONFIG_CPU_FREQ_GOV_ATTR_SET policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_GOV_COMMON policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_GOV_SCHEDUTIL policy<{'arm64': 'y'}> +CONFIG_CPU_FREQ_THERMAL policy<{'arm64': 'y'}> +CONFIG_CPU_HOTPLUG_STATE_CONTROL policy<{'arm64': 'n'}> +CONFIG_CPU_IDLE policy<{'arm64': 'y'}> +CONFIG_CPU_IDLE_GOV_LADDER policy<{'arm64': 'y'}> +CONFIG_CPU_IDLE_GOV_MENU policy<{'arm64': 'y'}> +CONFIG_CPU_IDLE_GOV_TEO policy<{'arm64': 'y'}> +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS policy<{'arm64': 'y'}> +CONFIG_CPU_IDLE_THERMAL policy<{'arm64': 'y'}> +CONFIG_CPU_ISOLATION policy<{'arm64': 'y'}> +CONFIG_CPU_LITTLE_ENDIAN policy<{'arm64': 'y'}> +CONFIG_CPU_MITIGATIONS policy<{'arm64': 'y'}> +CONFIG_CPU_PM policy<{'arm64': 'y'}> +CONFIG_CPU_RMAP policy<{'arm64': 'y'}> +CONFIG_CPU_THERMAL policy<{'arm64': 'y'}> +CONFIG_CRAMFS policy<{'arm64': 'm'}> +CONFIG_CRAMFS_BLOCKDEV policy<{'arm64': 'y'}> +CONFIG_CRAMFS_MTD policy<{'arm64': 'y'}> +CONFIG_CRASH_DM_CRYPT policy<{'arm64': 'n'}> +CONFIG_CRASH_RESERVE policy<{'arm64': 'y'}> +CONFIG_CRC16 policy<{'arm64': 'y'}> +CONFIG_CRC32 policy<{'arm64': 'y'}> +CONFIG_CRC32_ARCH policy<{'arm64': 'y'}> +CONFIG_CRC4 policy<{'arm64': 'm'}> +CONFIG_CRC64 policy<{'arm64': 'y'}> +CONFIG_CRC64_ARCH policy<{'arm64': 'y'}> +CONFIG_CRC7 policy<{'arm64': 'm'}> +CONFIG_CRC8 policy<{'arm64': 'y'}> +CONFIG_CRC_CCITT policy<{'arm64': 'y'}> +CONFIG_CRC_ITU_T policy<{'arm64': 'm'}> +CONFIG_CRC_OPTIMIZATIONS policy<{'arm64': 'y'}> +CONFIG_CRC_T10DIF policy<{'arm64': 'y'}> +CONFIG_CRC_T10DIF_ARCH policy<{'arm64': 'y'}> +CONFIG_CROSS_MEMORY_ATTACH policy<{'arm64': 'y'}> +CONFIG_CROS_EC policy<{'arm64': 'm'}> +CONFIG_CROS_EC_CHARDEV policy<{'arm64': 'm'}> +CONFIG_CROS_EC_DEBUGFS policy<{'arm64': 'm'}> +CONFIG_CROS_EC_I2C policy<{'arm64': 'm'}> +CONFIG_CROS_EC_LIGHTBAR policy<{'arm64': 'm'}> +CONFIG_CROS_EC_MKBP_PROXIMITY policy<{'arm64': 'm'}> +CONFIG_CROS_EC_PROTO policy<{'arm64': 'm'}> +CONFIG_CROS_EC_RPMSG policy<{'arm64': 'm'}> +CONFIG_CROS_EC_SENSORHUB policy<{'arm64': 'm'}> +CONFIG_CROS_EC_SPI policy<{'arm64': 'm'}> +CONFIG_CROS_EC_SYSFS policy<{'arm64': 'm'}> +CONFIG_CROS_EC_TYPEC policy<{'arm64': 'm'}> +CONFIG_CROS_EC_TYPEC_ALTMODES policy<{'arm64': 'y'}> +CONFIG_CROS_EC_UART policy<{'arm64': 'm'}> +CONFIG_CROS_EC_UCSI policy<{'arm64': 'm'}> +CONFIG_CROS_EC_VBC policy<{'arm64': 'm'}> +CONFIG_CROS_EC_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_CROS_HPS_I2C policy<{'arm64': 'm'}> +CONFIG_CROS_KBD_LED_BACKLIGHT policy<{'arm64': 'm'}> +CONFIG_CROS_TYPEC_SWITCH policy<{'arm64': 'm'}> +CONFIG_CROS_USBPD_LOGGER policy<{'arm64': 'm'}> +CONFIG_CROS_USBPD_NOTIFY policy<{'arm64': 'm'}> +CONFIG_CRYPTO policy<{'arm64': 'y'}> +CONFIG_CRYPTO_842 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_ACOMP policy<{'arm64': 'm'}> +CONFIG_CRYPTO_ACOMP2 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_ADIANTUM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AEAD policy<{'arm64': 'y'}> +CONFIG_CRYPTO_AEAD2 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_AEGIS128 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AEGIS128_SIMD policy<{'arm64': 'y'}> +CONFIG_CRYPTO_AES policy<{'arm64': 'y'}> +CONFIG_CRYPTO_AES_ARM64_BS policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM64_CE_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM64_CE_CCM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM64_NEON_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AKCIPHER policy<{'arm64': 'y'}> +CONFIG_CRYPTO_AKCIPHER2 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_ALGAPI policy<{'arm64': 'y'}> +CONFIG_CRYPTO_ALGAPI2 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_ANUBIS policy<{'arm64': 'n'}> +CONFIG_CRYPTO_ARC4 policy<{'arm64': 'n'}> +CONFIG_CRYPTO_ARIA policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AUTHENC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_BENCHMARK policy<{'arm64': 'n'}> +CONFIG_CRYPTO_BLAKE2B policy<{'arm64': 'm'}> +CONFIG_CRYPTO_BLOWFISH policy<{'arm64': 'm'}> +CONFIG_CRYPTO_BLOWFISH_COMMON policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CAMELLIA policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CAST5 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CAST6 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CAST_COMMON policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CBC policy<{'arm64': 'y'}> +CONFIG_CRYPTO_CCM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CHACHA20 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CHACHA20POLY1305 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CMAC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CRC32 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CRC32C policy<{'arm64': 'y'}> +CONFIG_CRYPTO_CRYPTD policy<{'arm64': 'm'}> +CONFIG_CRYPTO_CTR policy<{'arm64': 'y'}> +CONFIG_CRYPTO_CTS policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEFLATE policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DES policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ALLWINNER policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_AMLOGIC_GXL policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_ATMEL_AES policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_ATMEL_ECC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ATMEL_I2C policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ATMEL_SHA204A policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_CCP policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_CCP_CRYPTO policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_CCP_DD policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_CCP_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_CCREE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_CHELSIO policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_CPT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_EIP93 policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_FSL_CAAM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD policy<{'arm64': '255'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD policy<{'arm64': '2048'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_JR policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE policy<{'arm64': '9'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_HPRE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_QM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_SEC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_SEC2 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_ZIP policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_MARVELL policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_MARVELL_CESA policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_MXS_DCP policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_NITROX policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_NITROX_CNN55XX policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_OCTEONTX2_CPT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_OCTEONTX_CPT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QAT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_420XX policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_4XXX policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C3XXX policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C3XXXVF policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C62X policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C62XVF policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_DH895xCC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_QCE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_QCE_AEAD policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_QCE_SHA policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_QCE_SKCIPHER policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN policy<{'arm64': '512'}> +CONFIG_CRYPTO_DEV_QCOM_RNG policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ROCKCHIP policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_SA2UL policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SAFEXCEL policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SAHARA policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SP_CCP policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_STM32_CRYP policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_STM32_HASH policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SUN4I_SS policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_SUN8I_CE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_SUN8I_SS policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_HASH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_TEGRA policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_TI_DTHEV2 policy<{'arm64': 'n'}> +CONFIG_CRYPTO_DEV_VIRTIO policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ZYNQMP_AES policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DH_RFC7919_GROUPS policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DRBG policy<{'arm64': 'y'}> +CONFIG_CRYPTO_ECB policy<{'arm64': 'y'}> +CONFIG_CRYPTO_ECC policy<{'arm64': 'y'}> +CONFIG_CRYPTO_ECDH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_ECDSA policy<{'arm64': 'm'}> +CONFIG_CRYPTO_ECHAINIV policy<{'arm64': 'm'}> +CONFIG_CRYPTO_ECRDSA policy<{'arm64': 'm'}> +CONFIG_CRYPTO_ENGINE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_ESSIV policy<{'arm64': 'm'}> +CONFIG_CRYPTO_GCM policy<{'arm64': 'y'}> +CONFIG_CRYPTO_GENIV policy<{'arm64': 'y'}> +CONFIG_CRYPTO_GHASH_ARM64_CE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_HASH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_HASH2 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_HASH_INFO policy<{'arm64': 'y'}> +CONFIG_CRYPTO_HCTR2 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_HMAC policy<{'arm64': 'y'}> +CONFIG_CRYPTO_HW policy<{'arm64': 'y'}> +CONFIG_CRYPTO_JITTERENTROPY policy<{'arm64': 'y'}> +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS policy<{'arm64': '64'}> +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE policy<{'arm64': '32'}> +CONFIG_CRYPTO_JITTERENTROPY_OSR policy<{'arm64': '1'}> +CONFIG_CRYPTO_KDF800108_CTR policy<{'arm64': 'y'}> +CONFIG_CRYPTO_KHAZAD policy<{'arm64': 'n'}> +CONFIG_CRYPTO_KPP policy<{'arm64': 'y'}> +CONFIG_CRYPTO_KPP2 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_KRB5 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_KRB5ENC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_KRB5_SELFTESTS policy<{'arm64': 'n'}> +CONFIG_CRYPTO_LIB_AES policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_AES_ARCH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_AES_CBC_MACS policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_ARC4 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LIB_BLAKE2B policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LIB_CHACHA policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LIB_CHACHA20POLY1305 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LIB_CHACHA_ARCH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_CURVE25519 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_DES policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LIB_GF128HASH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_GF128HASH_ARCH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_GF128MUL policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LIB_MD5 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_NH policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LIB_NH_ARCH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LIB_POLY1305_ARCH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305_GENERIC policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305_RSIZE policy<{'arm64': '9'}> +CONFIG_CRYPTO_LIB_SHA1 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_SHA1_ARCH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_SHA256 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_SHA256_ARCH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_SHA3 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_SHA3_ARCH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_SHA512 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_SHA512_ARCH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_SM3 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LIB_SM3_ARCH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LIB_UTILS policy<{'arm64': 'y'}> +CONFIG_CRYPTO_LRW policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LZ4 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LZ4HC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_LZO policy<{'arm64': 'y'}> +CONFIG_CRYPTO_MANAGER policy<{'arm64': 'y'}> +CONFIG_CRYPTO_MANAGER2 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_MD4 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_MD5 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_MLDSA policy<{'arm64': 'n'}> +CONFIG_CRYPTO_NULL policy<{'arm64': 'y'}> +CONFIG_CRYPTO_PCRYPT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_RMD160 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_RNG policy<{'arm64': 'y'}> +CONFIG_CRYPTO_RNG2 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_RSA policy<{'arm64': 'y'}> +CONFIG_CRYPTO_SEED policy<{'arm64': 'n'}> +CONFIG_CRYPTO_SELFTESTS policy<{'arm64': 'n'}> +CONFIG_CRYPTO_SEQIV policy<{'arm64': 'y'}> +CONFIG_CRYPTO_SERPENT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SHA1 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_SHA256 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_SHA3 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_SIG policy<{'arm64': 'y'}> +CONFIG_CRYPTO_SIG2 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_SKCIPHER policy<{'arm64': 'y'}> +CONFIG_CRYPTO_SKCIPHER2 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_SM3 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE_CCM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE_GCM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_NEON_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_GENERIC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_STREEBOG policy<{'arm64': 'm'}> +CONFIG_CRYPTO_TEA policy<{'arm64': 'n'}> +CONFIG_CRYPTO_TWOFISH policy<{'arm64': 'm'}> +CONFIG_CRYPTO_TWOFISH_COMMON policy<{'arm64': 'm'}> +CONFIG_CRYPTO_USER policy<{'arm64': 'm'}> +CONFIG_CRYPTO_USER_API policy<{'arm64': 'm'}> +CONFIG_CRYPTO_USER_API_AEAD policy<{'arm64': 'm'}> +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE policy<{'arm64': 'y'}> +CONFIG_CRYPTO_USER_API_HASH policy<{'arm64': 'm'}> +CONFIG_CRYPTO_USER_API_RNG policy<{'arm64': 'm'}> +CONFIG_CRYPTO_USER_API_RNG_CAVP policy<{'arm64': 'n'}> +CONFIG_CRYPTO_USER_API_SKCIPHER policy<{'arm64': 'm'}> +CONFIG_CRYPTO_WP512 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_XCBC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_XCTR policy<{'arm64': 'm'}> +CONFIG_CRYPTO_XTS policy<{'arm64': 'y'}> +CONFIG_CRYPTO_XXHASH policy<{'arm64': 'm'}> +CONFIG_CRYPTO_ZSTD policy<{'arm64': 'm'}> +CONFIG_CSD_LOCK_WAIT_DEBUG policy<{'arm64': 'n'}> +CONFIG_CUSE policy<{'arm64': 'm'}> +CONFIG_CW1200 policy<{'arm64': 'm'}> +CONFIG_CW1200_WLAN_SDIO policy<{'arm64': 'm'}> +CONFIG_CW1200_WLAN_SPI policy<{'arm64': 'm'}> +CONFIG_CXD2880_SPI_DRV policy<{'arm64': 'm'}> +CONFIG_CXL_ACPI policy<{'arm64': 'm'}> +CONFIG_CXL_BUS policy<{'arm64': 'm'}> +CONFIG_CXL_FEATURES policy<{'arm64': 'n'}> +CONFIG_CXL_MEM policy<{'arm64': 'm'}> +CONFIG_CXL_MEM_RAW_COMMANDS policy<{'arm64': 'n'}> +CONFIG_CXL_PCI policy<{'arm64': 'm'}> +CONFIG_CXL_PMEM policy<{'arm64': 'm'}> +CONFIG_CXL_PMU policy<{'arm64': 'm'}> +CONFIG_CXL_PORT policy<{'arm64': 'm'}> +CONFIG_CXL_RAS policy<{'arm64': 'y'}> +CONFIG_CXL_REGION policy<{'arm64': 'y'}> +CONFIG_CXL_REGION_INVALIDATION_TEST policy<{'arm64': 'n'}> +CONFIG_CXL_SUSPEND policy<{'arm64': 'y'}> +CONFIG_CYPRESS_FIRMWARE policy<{'arm64': 'm'}> +CONFIG_CZNIC_PLATFORMS policy<{'arm64': 'y'}> +CONFIG_D3323AA policy<{'arm64': 'n'}> +CONFIG_DA280 policy<{'arm64': 'm'}> +CONFIG_DA311 policy<{'arm64': 'm'}> +CONFIG_DA9052_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_DA9055_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_DA9062_THERMAL policy<{'arm64': 'm'}> +CONFIG_DA9062_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_DA9063_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_DA9150_GPADC policy<{'arm64': 'm'}> +CONFIG_DAMON policy<{'arm64': 'n'}> +CONFIG_DAVICOM_PHY policy<{'arm64': 'm'}> +CONFIG_DAX policy<{'arm64': 'y'}> +CONFIG_DA_MON_EVENTS_ID policy<{'arm64': 'y'}> +CONFIG_DCACHE_WORD_ACCESS policy<{'arm64': 'y'}> +CONFIG_DCB policy<{'arm64': 'y'}> +CONFIG_DE2104X policy<{'arm64': 'm'}> +CONFIG_DE2104X_DSL policy<{'arm64': '0'}> +CONFIG_DEBUG_ATOMIC policy<{'arm64': 'n'}> +CONFIG_DEBUG_ATOMIC_SLEEP policy<{'arm64': 'n'}> +CONFIG_DEBUG_BUGVERBOSE policy<{'arm64': 'y'}> +CONFIG_DEBUG_BUGVERBOSE_DETAILED policy<{'arm64': 'n'}> +CONFIG_DEBUG_CGROUP_REF policy<{'arm64': 'n'}> +CONFIG_DEBUG_CLOSURES policy<{'arm64': 'n'}> +CONFIG_DEBUG_DEVRES policy<{'arm64': 'n'}> +CONFIG_DEBUG_DRIVER policy<{'arm64': 'n'}> +CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B policy<{'arm64': 'n'}> +CONFIG_DEBUG_FORCE_WEAK_PER_CPU policy<{'arm64': 'n'}> +CONFIG_DEBUG_FS_ALLOW_ALL policy<{'arm64': 'y'}> +CONFIG_DEBUG_FS_ALLOW_NONE policy<{'arm64': 'n'}> +CONFIG_DEBUG_GPIO policy<{'arm64': 'n'}> +CONFIG_DEBUG_INFO_DWARF4 policy<{'arm64': 'n'}> +CONFIG_DEBUG_INFO_DWARF5 policy<{'arm64': 'n'}> +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT policy<{'arm64': 'n'}> +CONFIG_DEBUG_INFO_NONE policy<{'arm64': 'y'}> +CONFIG_DEBUG_IRQFLAGS policy<{'arm64': 'n'}> +CONFIG_DEBUG_KERNEL_DC policy<{'arm64': 'n'}> +CONFIG_DEBUG_KMEMLEAK policy<{'arm64': 'n'}> +CONFIG_DEBUG_KOBJECT policy<{'arm64': 'n'}> +CONFIG_DEBUG_LIST policy<{'arm64': 'n'}> +CONFIG_DEBUG_LOCKING_API_SELFTESTS policy<{'arm64': 'n'}> +CONFIG_DEBUG_LOCK_ALLOC policy<{'arm64': 'n'}> +CONFIG_DEBUG_MAPLE_TREE policy<{'arm64': 'n'}> +CONFIG_DEBUG_MEMORY_INIT policy<{'arm64': 'n'}> +CONFIG_DEBUG_MISC policy<{'arm64': 'y'}> +CONFIG_DEBUG_MUTEXES policy<{'arm64': 'n'}> +CONFIG_DEBUG_NET policy<{'arm64': 'n'}> +CONFIG_DEBUG_NET_SMALL_RTNL policy<{'arm64': 'n'}> +CONFIG_DEBUG_NOTIFIERS policy<{'arm64': 'n'}> +CONFIG_DEBUG_OBJECTS policy<{'arm64': 'n'}> +CONFIG_DEBUG_PAGEALLOC policy<{'arm64': 'n'}> +CONFIG_DEBUG_PAGE_REF policy<{'arm64': 'n'}> +CONFIG_DEBUG_PERF_USE_VMALLOC policy<{'arm64': 'n'}> +CONFIG_DEBUG_PER_CPU_MAPS policy<{'arm64': 'n'}> +CONFIG_DEBUG_PINCTRL policy<{'arm64': 'n'}> +CONFIG_DEBUG_PLIST policy<{'arm64': 'n'}> +CONFIG_DEBUG_PREEMPT policy<{'arm64': 'n'}> +CONFIG_DEBUG_RODATA_TEST policy<{'arm64': 'n'}> +CONFIG_DEBUG_RSEQ policy<{'arm64': 'n'}> +CONFIG_DEBUG_RT_MUTEXES policy<{'arm64': 'n'}> +CONFIG_DEBUG_RWSEMS policy<{'arm64': 'n'}> +CONFIG_DEBUG_SECTION_MISMATCH policy<{'arm64': 'n'}> +CONFIG_DEBUG_SG policy<{'arm64': 'n'}> +CONFIG_DEBUG_SHIRQ policy<{'arm64': 'n'}> +CONFIG_DEBUG_SPINLOCK policy<{'arm64': 'n'}> +CONFIG_DEBUG_STACK_USAGE policy<{'arm64': 'n'}> +CONFIG_DEBUG_TEST_DRIVER_REMOVE policy<{'arm64': 'n'}> +CONFIG_DEBUG_VFS policy<{'arm64': 'n'}> +CONFIG_DEBUG_VIRTUAL policy<{'arm64': 'n'}> +CONFIG_DEBUG_VM policy<{'arm64': 'n'}> +CONFIG_DEBUG_VM_PGTABLE policy<{'arm64': 'n'}> +CONFIG_DEBUG_WQ_FORCE_RR_CPU policy<{'arm64': 'n'}> +CONFIG_DEBUG_WW_MUTEX_SLOWPATH policy<{'arm64': 'n'}> +CONFIG_DEBUG_WX policy<{'arm64': 'y'}> +CONFIG_DECOMPRESS_BZIP2 policy<{'arm64': 'y'}> +CONFIG_DECOMPRESS_GZIP policy<{'arm64': 'y'}> +CONFIG_DECOMPRESS_LZ4 policy<{'arm64': 'y'}> +CONFIG_DECOMPRESS_LZMA policy<{'arm64': 'y'}> +CONFIG_DECOMPRESS_LZO policy<{'arm64': 'y'}> +CONFIG_DECOMPRESS_XZ policy<{'arm64': 'y'}> +CONFIG_DECOMPRESS_ZSTD policy<{'arm64': 'y'}> +CONFIG_DEFAULT_CUBIC policy<{'arm64': 'y'}> +CONFIG_DEFAULT_HOSTNAME policy<{'arm64': '"(none)"'}> +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT policy<{'arm64': '120'}> +CONFIG_DEFAULT_INIT policy<{'arm64': '""'}> +CONFIG_DEFAULT_RENO policy<{'arm64': 'n'}> +CONFIG_DEFAULT_SECURITY_APPARMOR policy<{'arm64': 'y'}> +CONFIG_DEFAULT_SECURITY_DAC policy<{'arm64': 'n'}> +CONFIG_DEFAULT_SECURITY_SELINUX policy<{'arm64': 'n'}> +CONFIG_DEFAULT_SECURITY_SMACK policy<{'arm64': 'n'}> +CONFIG_DEFAULT_SECURITY_TOMOYO policy<{'arm64': 'n'}> +CONFIG_DEFAULT_TCP_CONG policy<{'arm64': '"cubic"'}> +CONFIG_DEFERRED_STRUCT_PAGE_INIT policy<{'arm64': 'n'}> +CONFIG_DEFXX policy<{'arm64': 'm'}> +CONFIG_DETECT_HUNG_TASK policy<{'arm64': 'y'}> +CONFIG_DETECT_HUNG_TASK_BLOCKER policy<{'arm64': 'y'}> +CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI policy<{'arm64': 'm'}> +CONFIG_DEVFREQ_GOV_PASSIVE policy<{'arm64': 'y'}> +CONFIG_DEVFREQ_GOV_PERFORMANCE policy<{'arm64': 'y'}> +CONFIG_DEVFREQ_GOV_POWERSAVE policy<{'arm64': 'y'}> +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND policy<{'arm64': 'y'}> +CONFIG_DEVFREQ_GOV_USERSPACE policy<{'arm64': 'y'}> +CONFIG_DEVFREQ_THERMAL policy<{'arm64': 'y'}> +CONFIG_DEVICE_MIGRATION policy<{'arm64': 'y'}> +CONFIG_DEVICE_PRIVATE policy<{'arm64': 'y'}> +CONFIG_DEVMEM policy<{'arm64': 'y'}> +CONFIG_DEVPORT policy<{'arm64': 'y'}> +CONFIG_DEVTMPFS_SAFE policy<{'arm64': 'y'}> +CONFIG_DEV_COREDUMP policy<{'arm64': 'y'}> +CONFIG_DEV_DAX policy<{'arm64': 'm'}> +CONFIG_DEV_DAX_CXL policy<{'arm64': 'm'}> +CONFIG_DEV_DAX_FSDEV policy<{'arm64': 'm'}> +CONFIG_DEV_DAX_HMEM policy<{'arm64': 'm'}> +CONFIG_DEV_DAX_HMEM_DEVICES policy<{'arm64': 'y'}> +CONFIG_DEV_DAX_KMEM policy<{'arm64': 'm'}> +CONFIG_DEV_DAX_PMEM policy<{'arm64': 'm'}> +CONFIG_DHT11 policy<{'arm64': 'm'}> +CONFIG_DIBS policy<{'arm64': 'n'}> +CONFIG_DIMLIB policy<{'arm64': 'y'}> +CONFIG_DL2K policy<{'arm64': 'm'}> +CONFIG_DLHL60D policy<{'arm64': 'm'}> +CONFIG_DLM policy<{'arm64': 'm'}> +CONFIG_DLM_DEBUG policy<{'arm64': 'n'}> +CONFIG_DLN2_ADC policy<{'arm64': 'm'}> +CONFIG_DM9051 policy<{'arm64': 'm'}> +CONFIG_DM9102 policy<{'arm64': 'm'}> +CONFIG_DMABUF_DEBUG policy<{'arm64': 'n'}> +CONFIG_DMABUF_HEAPS policy<{'arm64': 'y'}> +CONFIG_DMABUF_HEAPS_CMA policy<{'arm64': 'y'}> +CONFIG_DMABUF_HEAPS_SYSTEM policy<{'arm64': 'y'}> +CONFIG_DMABUF_HEAPS_SYSTEM_CC_SHARED policy<{'arm64': 'n'}> +CONFIG_DMADEVICES policy<{'arm64': 'y'}> +CONFIG_DMADEVICES_DEBUG policy<{'arm64': 'n'}> +CONFIG_DMAPOOL_TEST policy<{'arm64': 'n'}> +CONFIG_DMARD06 policy<{'arm64': 'm'}> +CONFIG_DMARD09 policy<{'arm64': 'm'}> +CONFIG_DMARD10 policy<{'arm64': 'm'}> +CONFIG_DMATEST policy<{'arm64': 'n'}> +CONFIG_DMA_ACPI policy<{'arm64': 'y'}> +CONFIG_DMA_API_DEBUG policy<{'arm64': 'n'}> +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC policy<{'arm64': 'y'}> +CONFIG_DMA_COHERENT_POOL policy<{'arm64': 'y'}> +CONFIG_DMA_DECLARE_COHERENT policy<{'arm64': 'y'}> +CONFIG_DMA_DIRECT_REMAP policy<{'arm64': 'y'}> +CONFIG_DMA_ENGINE policy<{'arm64': 'y'}> +CONFIG_DMA_ENGINE_RAID policy<{'arm64': 'y'}> +CONFIG_DMA_FENCE_TRACE policy<{'arm64': 'n'}> +CONFIG_DMA_MAP_BENCHMARK policy<{'arm64': 'n'}> +CONFIG_DMA_NEED_SYNC policy<{'arm64': 'y'}> +CONFIG_DMA_NONCOHERENT_MMAP policy<{'arm64': 'y'}> +CONFIG_DMA_NUMA_CMA policy<{'arm64': 'y'}> +CONFIG_DMA_OF policy<{'arm64': 'y'}> +CONFIG_DMA_OPS_HELPERS policy<{'arm64': 'y'}> +CONFIG_DMA_RESTRICTED_POOL policy<{'arm64': 'y'}> +CONFIG_DMA_SHARED_BUFFER policy<{'arm64': 'y'}> +CONFIG_DMA_SUN6I policy<{'arm64': 'm'}> +CONFIG_DMA_VIRTUAL_CHANNELS policy<{'arm64': 'y'}> +CONFIG_DMI policy<{'arm64': 'y'}> +CONFIG_DMIID policy<{'arm64': 'y'}> +CONFIG_DMI_SYSFS policy<{'arm64': 'm'}> +CONFIG_DM_AUDIT policy<{'arm64': 'y'}> +CONFIG_DM_BIO_PRISON policy<{'arm64': 'm'}> +CONFIG_DM_BUFIO policy<{'arm64': 'm'}> +CONFIG_DM_CACHE policy<{'arm64': 'm'}> +CONFIG_DM_CACHE_SMQ policy<{'arm64': 'm'}> +CONFIG_DM_CLONE policy<{'arm64': 'm'}> +CONFIG_DM_CRYPT policy<{'arm64': 'm'}> +CONFIG_DM_DEBUG policy<{'arm64': 'n'}> +CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING policy<{'arm64': 'n'}> +CONFIG_DM_DELAY policy<{'arm64': 'm'}> +CONFIG_DM_DUST policy<{'arm64': 'n'}> +CONFIG_DM_EBS policy<{'arm64': 'm'}> +CONFIG_DM_ERA policy<{'arm64': 'm'}> +CONFIG_DM_FLAKEY policy<{'arm64': 'm'}> +CONFIG_DM_INIT policy<{'arm64': 'y'}> +CONFIG_DM_INLINECRYPT policy<{'arm64': 'n'}> +CONFIG_DM_INTEGRITY policy<{'arm64': 'm'}> +CONFIG_DM_LOG_USERSPACE policy<{'arm64': 'm'}> +CONFIG_DM_LOG_WRITES policy<{'arm64': 'm'}> +CONFIG_DM_MIRROR policy<{'arm64': 'm'}> +CONFIG_DM_MULTIPATH policy<{'arm64': 'm'}> +CONFIG_DM_MULTIPATH_HST policy<{'arm64': 'm'}> +CONFIG_DM_MULTIPATH_IOA policy<{'arm64': 'm'}> +CONFIG_DM_MULTIPATH_QL policy<{'arm64': 'm'}> +CONFIG_DM_MULTIPATH_ST policy<{'arm64': 'm'}> +CONFIG_DM_PCACHE policy<{'arm64': 'n'}> +CONFIG_DM_PERSISTENT_DATA policy<{'arm64': 'm'}> +CONFIG_DM_RAID policy<{'arm64': 'm'}> +CONFIG_DM_SNAPSHOT policy<{'arm64': 'm'}> +CONFIG_DM_SWITCH policy<{'arm64': 'm'}> +CONFIG_DM_THIN_PROVISIONING policy<{'arm64': 'm'}> +CONFIG_DM_UEVENT policy<{'arm64': 'y'}> +CONFIG_DM_UNSTRIPED policy<{'arm64': 'm'}> +CONFIG_DM_VDO policy<{'arm64': 'm'}> +CONFIG_DM_VERITY policy<{'arm64': 'm'}> +CONFIG_DM_VERITY_FEC policy<{'arm64': 'n'}> +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG policy<{'arm64': 'y'}> +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING policy<{'arm64': 'y'}> +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING policy<{'arm64': 'y'}> +CONFIG_DM_WRITECACHE policy<{'arm64': 'm'}> +CONFIG_DM_ZERO policy<{'arm64': 'm'}> +CONFIG_DM_ZONED policy<{'arm64': 'm'}> +CONFIG_DNOTIFY policy<{'arm64': 'y'}> +CONFIG_DNS_RESOLVER policy<{'arm64': 'y'}> +CONFIG_DP83640_PHY policy<{'arm64': 'm'}> +CONFIG_DP83822_PHY policy<{'arm64': 'm'}> +CONFIG_DP83848_PHY policy<{'arm64': 'm'}> +CONFIG_DP83867_PHY policy<{'arm64': 'm'}> +CONFIG_DP83869_PHY policy<{'arm64': 'm'}> +CONFIG_DP83TC811_PHY policy<{'arm64': 'm'}> +CONFIG_DP83TD510_PHY policy<{'arm64': 'm'}> +CONFIG_DP83TG720_PHY policy<{'arm64': 'm'}> +CONFIG_DPAA2_CONSOLE policy<{'arm64': 'm'}> +CONFIG_DPAA_ERRATUM_A050385 policy<{'arm64': 'y'}> +CONFIG_DPLL policy<{'arm64': 'y'}> +CONFIG_DPLL_REFCNT_TRACKER policy<{'arm64': 'n'}> +CONFIG_DPM_WATCHDOG policy<{'arm64': 'n'}> +CONFIG_DPOT_DAC policy<{'arm64': 'm'}> +CONFIG_DPS310 policy<{'arm64': 'm'}> +CONFIG_DQL policy<{'arm64': 'y'}> +CONFIG_DRAGONRISE_FF policy<{'arm64': 'y'}> +CONFIG_DRBD_FAULT_INJECTION policy<{'arm64': 'n'}> +CONFIG_DRIVER_DEFERRED_PROBE_TIMEOUT policy<{'arm64': '10'}> +CONFIG_DRM_ACCEL policy<{'arm64': 'y'}> +CONFIG_DRM_ACCEL_ARM_ETHOSU policy<{'arm64': 'm'}> +CONFIG_DRM_ACCEL_QAIC policy<{'arm64': 'm'}> +CONFIG_DRM_ACCEL_ROCKET policy<{'arm64': 'n'}> +CONFIG_DRM_ADP policy<{'arm64': 'n'}> +CONFIG_DRM_AMDGPU policy<{'arm64': 'm'}> +CONFIG_DRM_AMDGPU_CIK policy<{'arm64': 'y'}> +CONFIG_DRM_AMDGPU_SI policy<{'arm64': 'y'}> +CONFIG_DRM_AMDGPU_USERPTR policy<{'arm64': 'y'}> +CONFIG_DRM_AMDGPU_WERROR policy<{'arm64': 'n'}> +CONFIG_DRM_AMD_ACP policy<{'arm64': 'y'}> +CONFIG_DRM_AMD_DC policy<{'arm64': 'y'}> +CONFIG_DRM_AMD_DC_FP policy<{'arm64': 'y'}> +CONFIG_DRM_AMD_DC_SI policy<{'arm64': 'y'}> +CONFIG_DRM_AMD_ISP policy<{'arm64': 'y'}> +CONFIG_DRM_AMD_SECURE_DISPLAY policy<{'arm64': 'y'}> +CONFIG_DRM_ANALOGIX_ANX6345 policy<{'arm64': 'm'}> +CONFIG_DRM_ANALOGIX_ANX7625 policy<{'arm64': 'm'}> +CONFIG_DRM_ANALOGIX_ANX78XX policy<{'arm64': 'm'}> +CONFIG_DRM_ANALOGIX_DP policy<{'arm64': 'm'}> +CONFIG_DRM_ARCPGU policy<{'arm64': 'm'}> +CONFIG_DRM_AST policy<{'arm64': 'm'}> +CONFIG_DRM_AUX_BRIDGE policy<{'arm64': 'y'}> +CONFIG_DRM_AUX_HPD_BRIDGE policy<{'arm64': 'y'}> +CONFIG_DRM_BOCHS policy<{'arm64': 'm'}> +CONFIG_DRM_BRIDGE policy<{'arm64': 'y'}> +CONFIG_DRM_BRIDGE_CONNECTOR policy<{'arm64': 'y'}> +CONFIG_DRM_BUDDY policy<{'arm64': 'm'}> +CONFIG_DRM_CDNS_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_CDNS_DSI_J721E policy<{'arm64': 'y'}> +CONFIG_DRM_CDNS_MHDP8546 policy<{'arm64': 'm'}> +CONFIG_DRM_CDNS_MHDP8546_J721E policy<{'arm64': 'y'}> +CONFIG_DRM_CHIPONE_ICN6211 policy<{'arm64': 'm'}> +CONFIG_DRM_CHRONTEL_CH7033 policy<{'arm64': 'm'}> +CONFIG_DRM_CIRRUS_QEMU policy<{'arm64': 'm'}> +CONFIG_DRM_CLIENT policy<{'arm64': 'y'}> +CONFIG_DRM_CLIENT_DEFAULT policy<{'arm64': '"fbdev"'}> +CONFIG_DRM_CLIENT_DEFAULT_FBDEV policy<{'arm64': 'y'}> +CONFIG_DRM_CLIENT_DEFAULT_LOG policy<{'arm64': 'n'}> +CONFIG_DRM_CLIENT_LIB policy<{'arm64': 'y'}> +CONFIG_DRM_CLIENT_LOG policy<{'arm64': 'y'}> +CONFIG_DRM_CLIENT_SELECTION policy<{'arm64': 'y'}> +CONFIG_DRM_CLIENT_SETUP policy<{'arm64': 'y'}> +CONFIG_DRM_CROS_EC_ANX7688 policy<{'arm64': 'm'}> +CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS policy<{'arm64': 'n'}> +CONFIG_DRM_DEBUG_MM policy<{'arm64': 'n'}> +CONFIG_DRM_DEBUG_MODESET_LOCK policy<{'arm64': 'n'}> +CONFIG_DRM_DISPLAY_CONNECTOR policy<{'arm64': 'm'}> +CONFIG_DRM_DISPLAY_DP_AUX_BUS policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_DP_AUX_CEC policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_DP_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_DP_TUNNEL policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_DSC_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_HDCP_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_AUDIO_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_CEC_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_DISPLAY_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_DRAW policy<{'arm64': 'y'}> +CONFIG_DRM_DW_HDMI policy<{'arm64': 'm'}> +CONFIG_DRM_DW_HDMI_AHB_AUDIO policy<{'arm64': 'm'}> +CONFIG_DRM_DW_HDMI_CEC policy<{'arm64': 'm'}> +CONFIG_DRM_DW_HDMI_GP_AUDIO policy<{'arm64': 'm'}> +CONFIG_DRM_DW_HDMI_I2S_AUDIO policy<{'arm64': 'm'}> +CONFIG_DRM_DW_MIPI_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_ETNAVIV policy<{'arm64': 'm'}> +CONFIG_DRM_ETNAVIV_THERMAL policy<{'arm64': 'y'}> +CONFIG_DRM_EXEC policy<{'arm64': 'm'}> +CONFIG_DRM_FBDEV_EMULATION policy<{'arm64': 'y'}> +CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM policy<{'arm64': 'n'}> +CONFIG_DRM_FBDEV_OVERALLOC policy<{'arm64': '100'}> +CONFIG_DRM_FSL_LDB policy<{'arm64': 'm'}> +CONFIG_DRM_GEM_DMA_HELPER policy<{'arm64': 'm'}> +CONFIG_DRM_GEM_SHMEM_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_GM12U320 policy<{'arm64': 'm'}> +CONFIG_DRM_GPUSVM policy<{'arm64': 'm'}> +CONFIG_DRM_GPUVM policy<{'arm64': 'm'}> +CONFIG_DRM_GUD policy<{'arm64': 'm'}> +CONFIG_DRM_HDLCD policy<{'arm64': 'm'}> +CONFIG_DRM_HDLCD_SHOW_UNDERRUN policy<{'arm64': 'n'}> +CONFIG_DRM_HISI_KIRIN policy<{'arm64': 'm'}> +CONFIG_DRM_I2C_ADV7511 policy<{'arm64': 'm'}> +CONFIG_DRM_I2C_ADV7511_AUDIO policy<{'arm64': 'y'}> +CONFIG_DRM_I2C_ADV7511_CEC policy<{'arm64': 'y'}> +CONFIG_DRM_I2C_NXP_TDA998X policy<{'arm64': 'm'}> +CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE policy<{'arm64': 'm'}> +CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE_CONNECTOR_FIXUP policy<{'arm64': 'y'}> +CONFIG_DRM_IMX8MP_HDMI_PAI policy<{'arm64': 'm'}> +CONFIG_DRM_IMX8MP_HDMI_PVI policy<{'arm64': 'm'}> +CONFIG_DRM_IMX8QM_LDB policy<{'arm64': 'm'}> +CONFIG_DRM_IMX8QXP_LDB policy<{'arm64': 'm'}> +CONFIG_DRM_IMX8QXP_PIXEL_COMBINER policy<{'arm64': 'm'}> +CONFIG_DRM_IMX8QXP_PIXEL_LINK policy<{'arm64': 'm'}> +CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI policy<{'arm64': 'm'}> +CONFIG_DRM_IMX8_DC policy<{'arm64': 'n'}> +CONFIG_DRM_IMX93_MIPI_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_IMX_DCSS policy<{'arm64': 'm'}> +CONFIG_DRM_IMX_LCDC policy<{'arm64': 'm'}> +CONFIG_DRM_IMX_LCDIF policy<{'arm64': 'm'}> +CONFIG_DRM_IMX_LDB_HELPER policy<{'arm64': 'm'}> +CONFIG_DRM_INNO_HDMI policy<{'arm64': 'm'}> +CONFIG_DRM_ITE_IT6263 policy<{'arm64': 'm'}> +CONFIG_DRM_ITE_IT6505 policy<{'arm64': 'm'}> +CONFIG_DRM_ITE_IT66121 policy<{'arm64': 'm'}> +CONFIG_DRM_KMB_DISPLAY policy<{'arm64': 'm'}> +CONFIG_DRM_KMS_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_KOMEDA policy<{'arm64': 'm'}> +CONFIG_DRM_LIMA policy<{'arm64': 'm'}> +CONFIG_DRM_LOAD_EDID_FIRMWARE policy<{'arm64': 'y'}> +CONFIG_DRM_LOGICVC policy<{'arm64': 'm'}> +CONFIG_DRM_LONTIUM_LT8713SX policy<{'arm64': 'n'}> +CONFIG_DRM_LONTIUM_LT8912B policy<{'arm64': 'm'}> +CONFIG_DRM_LONTIUM_LT9211 policy<{'arm64': 'm'}> +CONFIG_DRM_LONTIUM_LT9611 policy<{'arm64': 'm'}> +CONFIG_DRM_LONTIUM_LT9611UXC policy<{'arm64': 'm'}> +CONFIG_DRM_LVDS_CODEC policy<{'arm64': 'm'}> +CONFIG_DRM_MALI_DISPLAY policy<{'arm64': 'm'}> +CONFIG_DRM_MEDIATEK policy<{'arm64': 'm'}> +CONFIG_DRM_MEDIATEK_DP policy<{'arm64': 'm'}> +CONFIG_DRM_MEDIATEK_HDMI policy<{'arm64': 'm'}> +CONFIG_DRM_MEDIATEK_HDMI_COMMON policy<{'arm64': 'm'}> +CONFIG_DRM_MEDIATEK_HDMI_V2 policy<{'arm64': 'n'}> +CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW policy<{'arm64': 'm'}> +CONFIG_DRM_MESON policy<{'arm64': 'm'}> +CONFIG_DRM_MESON_DW_HDMI policy<{'arm64': 'm'}> +CONFIG_DRM_MESON_DW_MIPI_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_MIPI_DBI policy<{'arm64': 'm'}> +CONFIG_DRM_MIPI_DSI policy<{'arm64': 'y'}> +CONFIG_DRM_MSM policy<{'arm64': 'm'}> +CONFIG_DRM_MSM_DP policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_DPU policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_DSI policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_DSI_10NM_PHY policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_DSI_14NM_PHY policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_DSI_20NM_PHY policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_DSI_28NM_8960_PHY policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_DSI_28NM_PHY policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_DSI_7NM_PHY policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_GPU_STATE policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_GPU_SUDO policy<{'arm64': 'n'}> +CONFIG_DRM_MSM_HDMI policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_HDMI_HDCP policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_KMS policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_KMS_FBDEV policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_MDP4 policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_MDP5 policy<{'arm64': 'y'}> +CONFIG_DRM_MSM_MDSS policy<{'arm64': 'y'}> +CONFIG_DRM_MXS policy<{'arm64': 'y'}> +CONFIG_DRM_MXSFB policy<{'arm64': 'm'}> +CONFIG_DRM_NOUVEAU policy<{'arm64': 'm'}> +CONFIG_DRM_NOUVEAU_BACKLIGHT policy<{'arm64': 'y'}> +CONFIG_DRM_NOUVEAU_CH7006 policy<{'arm64': 'm'}> +CONFIG_DRM_NOUVEAU_SIL164 policy<{'arm64': 'm'}> +CONFIG_DRM_NOUVEAU_SVM policy<{'arm64': 'n'}> +CONFIG_DRM_NWL_MIPI_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_NXP_PTN3460 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL policy<{'arm64': 'y'}> +CONFIG_DRM_PANEL_ABT_Y030XX067A policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_ARM_VERSATILE policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_AUO_A030JTN01 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_BOE_HIMAX8279D policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_BOE_TD4320 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_BRIDGE policy<{'arm64': 'y'}> +CONFIG_DRM_PANEL_CHIPWEALTH_CH13726A policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_DSI_CM policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_EBBG_FT8719 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_EDP policy<{'arm64': 'y'}> +CONFIG_DRM_PANEL_ELIDA_KD35T133 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_FOCALTECH_OTA7290B policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_HIMAX_HX8279 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_HIMAX_HX83102 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX83112A policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX83112B policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_HIMAX_HX83121A policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_HIMAX_HX8394 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_HYDIS_HV101HD1 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_ILITEK_IL9322 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9341 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9805 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9806E_DSI policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_ILITEK_ILI9806E_SPI policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_ILITEK_ILI9881C policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9882T policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_INNOLUX_EJ030NA policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_INNOLUX_P079ZCA policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_JDI_LPM102A188A policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_JDI_LT070ME05000 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_JDI_R63452 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_KHADAS_TS050 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_LG_LB035Q02 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_LG_LD070WX3 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_LG_LG4573 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_LG_SW43408 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_LVDS policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_LXD_M9189A policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_MIPI_DBI policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_MOTOROLA_MOT policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_NEC_NL8048HL11 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_NEWVISION_NV3051D policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_NEWVISION_NV3052C policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT35510 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT35532 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_NOVATEK_NT35560 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT35950 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT36523 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT36672A policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT36672E policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT37700F policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_NOVATEK_NT37801 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_NOVATEK_NT39016 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS policy<{'arm64': 'y'}> +CONFIG_DRM_PANEL_ORISETECH_OTA5601A policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_ORISETECH_OTM8009A policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM67191 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM67200 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_RAYDIUM_RM68200 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM692E5 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM69380 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_RENESAS_R61307 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_RENESAS_R69328 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_RONBO_RB070D30 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_ATNA40CT01 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_SAMSUNG_DB7430 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_LD9040 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_LTL106HL02 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3FC2X01 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E8FC0 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SEIKO_43WVF1G policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LQ079L1SX01 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LS037V7DW01 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LS043T1LE01 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LS060T1SX01 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SIMPLE policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SITRONIX_ST7701 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SITRONIX_ST7703 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SITRONIX_ST7789V policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SONY_ACX565AKM policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SONY_TD4353_JDI policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SUMMIT policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_SYNAPTICS_R63353 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_SYNAPTICS_TDDI policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_TDO_TL070WSH30 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_TPO_TD028TTEC1 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_TPO_TD043MTEA1 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_TPO_TPG110 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_G2647FB105 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_VISIONOX_R66451 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_RM69299 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_RM692E5 policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_VISIONOX_VTDR6130 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_WIDECHIPS_WS2401 policy<{'arm64': 'm'}> +CONFIG_DRM_PANEL_XINPENG_XPP055C272 policy<{'arm64': 'm'}> +CONFIG_DRM_PANFROST policy<{'arm64': 'm'}> +CONFIG_DRM_PANIC policy<{'arm64': 'y'}> +CONFIG_DRM_PANIC_BACKGROUND_COLOR policy<{'arm64': '0x5e2750'}> +CONFIG_DRM_PANIC_DEBUG policy<{'arm64': 'n'}> +CONFIG_DRM_PANIC_FOREGROUND_COLOR policy<{'arm64': '0xffffff'}> +CONFIG_DRM_PANIC_SCREEN policy<{'arm64': '"user"'}> +CONFIG_DRM_PANTHOR policy<{'arm64': 'm'}> +CONFIG_DRM_PARADE_PS8622 policy<{'arm64': 'm'}> +CONFIG_DRM_PARADE_PS8640 policy<{'arm64': 'm'}> +CONFIG_DRM_PIXPAPER policy<{'arm64': 'n'}> +CONFIG_DRM_PL111 policy<{'arm64': 'm'}> +CONFIG_DRM_POWERVR policy<{'arm64': 'm'}> +CONFIG_DRM_PRIVACY_SCREEN policy<{'arm64': 'y'}> +CONFIG_DRM_QXL policy<{'arm64': 'm'}> +CONFIG_DRM_RADEON policy<{'arm64': 'm'}> +CONFIG_DRM_RADEON_USERPTR policy<{'arm64': 'n'}> +CONFIG_DRM_RAS policy<{'arm64': 'n'}> +CONFIG_DRM_RCAR_CMM policy<{'arm64': 'm'}> +CONFIG_DRM_RCAR_DU policy<{'arm64': 'm'}> +CONFIG_DRM_RCAR_DW_HDMI policy<{'arm64': 'm'}> +CONFIG_DRM_RCAR_LVDS policy<{'arm64': 'm'}> +CONFIG_DRM_RCAR_MIPI_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_RCAR_USE_CMM policy<{'arm64': 'y'}> +CONFIG_DRM_RCAR_USE_LVDS policy<{'arm64': 'y'}> +CONFIG_DRM_RCAR_USE_MIPI_DSI policy<{'arm64': 'y'}> +CONFIG_DRM_RCAR_VSP policy<{'arm64': 'y'}> +CONFIG_DRM_RCAR_WRITEBACK policy<{'arm64': 'y'}> +CONFIG_DRM_ROCKCHIP policy<{'arm64': 'm'}> +CONFIG_DRM_RZG2L_DU policy<{'arm64': 'm'}> +CONFIG_DRM_RZG2L_MIPI_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_RZG2L_USE_MIPI_DSI policy<{'arm64': 'y'}> +CONFIG_DRM_SAMSUNG_DSIM policy<{'arm64': 'm'}> +CONFIG_DRM_SCHED policy<{'arm64': 'm'}> +CONFIG_DRM_SHMOBILE policy<{'arm64': 'm'}> +CONFIG_DRM_SII902X policy<{'arm64': 'm'}> +CONFIG_DRM_SII9234 policy<{'arm64': 'm'}> +CONFIG_DRM_SIL_SII8620 policy<{'arm64': 'm'}> +CONFIG_DRM_SIMPLE_BRIDGE policy<{'arm64': 'm'}> +CONFIG_DRM_SOLOMON_SSD2825 policy<{'arm64': 'n'}> +CONFIG_DRM_SPRD policy<{'arm64': 'm'}> +CONFIG_DRM_SSD130X policy<{'arm64': 'm'}> +CONFIG_DRM_SSD130X_I2C policy<{'arm64': 'm'}> +CONFIG_DRM_SSD130X_SPI policy<{'arm64': 'm'}> +CONFIG_DRM_ST7571 policy<{'arm64': 'n'}> +CONFIG_DRM_ST7586 policy<{'arm64': 'n'}> +CONFIG_DRM_ST7735R policy<{'arm64': 'n'}> +CONFIG_DRM_ST7920 policy<{'arm64': 'n'}> +CONFIG_DRM_STM policy<{'arm64': 'm'}> +CONFIG_DRM_STM_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_STM_LVDS policy<{'arm64': 'm'}> +CONFIG_DRM_SUBALLOC_HELPER policy<{'arm64': 'm'}> +CONFIG_DRM_SUN4I policy<{'arm64': 'm'}> +CONFIG_DRM_SUN6I_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_SUN8I_DW_HDMI policy<{'arm64': 'm'}> +CONFIG_DRM_SUN8I_MIXER policy<{'arm64': 'm'}> +CONFIG_DRM_SUN8I_TCON_TOP policy<{'arm64': 'm'}> +CONFIG_DRM_SYSFB_HELPER policy<{'arm64': 'y'}> +CONFIG_DRM_TEGRA policy<{'arm64': 'm'}> +CONFIG_DRM_TEGRA_DEBUG policy<{'arm64': 'n'}> +CONFIG_DRM_TEGRA_STAGING policy<{'arm64': 'y'}> +CONFIG_DRM_THINE_THC63LVD1024 policy<{'arm64': 'm'}> +CONFIG_DRM_TIDSS policy<{'arm64': 'm'}> +CONFIG_DRM_TI_DLPC3433 policy<{'arm64': 'm'}> +CONFIG_DRM_TI_SN65DSI83 policy<{'arm64': 'm'}> +CONFIG_DRM_TI_SN65DSI86 policy<{'arm64': 'm'}> +CONFIG_DRM_TI_TDP158 policy<{'arm64': 'm'}> +CONFIG_DRM_TI_TFP410 policy<{'arm64': 'm'}> +CONFIG_DRM_TI_TPD12S015 policy<{'arm64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358762 policy<{'arm64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358764 policy<{'arm64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358767 policy<{'arm64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358768 policy<{'arm64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358775 policy<{'arm64': 'm'}> +CONFIG_DRM_TTM policy<{'arm64': 'm'}> +CONFIG_DRM_TTM_HELPER policy<{'arm64': 'm'}> +CONFIG_DRM_UDL policy<{'arm64': 'm'}> +CONFIG_DRM_VGEM policy<{'arm64': 'm'}> +CONFIG_DRM_VIRTIO_GPU policy<{'arm64': 'm'}> +CONFIG_DRM_VIRTIO_GPU_KMS policy<{'arm64': 'y'}> +CONFIG_DRM_VKMS policy<{'arm64': 'm'}> +CONFIG_DRM_VMWGFX policy<{'arm64': 'm'}> +CONFIG_DRM_VRAM_HELPER policy<{'arm64': 'm'}> +CONFIG_DRM_WAVESHARE_BRIDGE policy<{'arm64': 'n'}> +CONFIG_DRM_WERROR policy<{'arm64': 'n'}> +CONFIG_DRM_XE policy<{'arm64': 'm'}> +CONFIG_DRM_XEN policy<{'arm64': 'y'}> +CONFIG_DRM_XEN_FRONTEND policy<{'arm64': 'm'}> +CONFIG_DRM_XE_DEBUG policy<{'arm64': 'n'}> +CONFIG_DRM_XE_DEBUG_MEM policy<{'arm64': 'n'}> +CONFIG_DRM_XE_DEBUG_MEMIRQ policy<{'arm64': 'n'}> +CONFIG_DRM_XE_DEBUG_SRIOV policy<{'arm64': 'n'}> +CONFIG_DRM_XE_DEBUG_VM policy<{'arm64': 'n'}> +CONFIG_DRM_XE_DISPLAY policy<{'arm64': 'y'}> +CONFIG_DRM_XE_DP_TUNNEL policy<{'arm64': 'y'}> +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT policy<{'arm64': 'y'}> +CONFIG_DRM_XE_FORCE_PROBE policy<{'arm64': '""'}> +CONFIG_DRM_XE_GPUSVM policy<{'arm64': 'y'}> +CONFIG_DRM_XE_JOB_TIMEOUT_MAX policy<{'arm64': '10000'}> +CONFIG_DRM_XE_JOB_TIMEOUT_MIN policy<{'arm64': '1'}> +CONFIG_DRM_XE_PAGEMAP policy<{'arm64': 'y'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT policy<{'arm64': '640000'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX policy<{'arm64': '10000000'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN policy<{'arm64': '1'}> +CONFIG_DRM_XE_TIMESLICE_MAX policy<{'arm64': '10000000'}> +CONFIG_DRM_XE_TIMESLICE_MIN policy<{'arm64': '1'}> +CONFIG_DRM_XE_USERPTR_INVAL_INJECT policy<{'arm64': 'n'}> +CONFIG_DRM_XE_WERROR policy<{'arm64': 'n'}> +CONFIG_DRM_ZYNQMP_DPSUB policy<{'arm64': 'm'}> +CONFIG_DRM_ZYNQMP_DPSUB_AUDIO policy<{'arm64': 'n'}> +CONFIG_DS1682 policy<{'arm64': 'm'}> +CONFIG_DS1803 policy<{'arm64': 'm'}> +CONFIG_DS4424 policy<{'arm64': 'm'}> +CONFIG_DST_CACHE policy<{'arm64': 'y'}> +CONFIG_DTC policy<{'arm64': 'y'}> +CONFIG_DTPM policy<{'arm64': 'y'}> +CONFIG_DTPM_CPU policy<{'arm64': 'y'}> +CONFIG_DTPM_DEVFREQ policy<{'arm64': 'n'}> +CONFIG_DT_IDLE_GENPD policy<{'arm64': 'y'}> +CONFIG_DT_IDLE_STATES policy<{'arm64': 'y'}> +CONFIG_DUMMY policy<{'arm64': 'm'}> +CONFIG_DUMMY_CONSOLE policy<{'arm64': 'y'}> +CONFIG_DUMMY_CONSOLE_COLUMNS policy<{'arm64': '80'}> +CONFIG_DUMMY_CONSOLE_ROWS policy<{'arm64': '25'}> +CONFIG_DUMMY_IRQ policy<{'arm64': 'm'}> +CONFIG_DVB_A8293 policy<{'arm64': 'm'}> +CONFIG_DVB_AF9013 policy<{'arm64': 'm'}> +CONFIG_DVB_AF9033 policy<{'arm64': 'm'}> +CONFIG_DVB_AS102 policy<{'arm64': 'm'}> +CONFIG_DVB_AS102_FE policy<{'arm64': 'm'}> +CONFIG_DVB_ASCOT2E policy<{'arm64': 'm'}> +CONFIG_DVB_ATBM8830 policy<{'arm64': 'm'}> +CONFIG_DVB_AU8522 policy<{'arm64': 'm'}> +CONFIG_DVB_AU8522_DTV policy<{'arm64': 'm'}> +CONFIG_DVB_AU8522_V4L policy<{'arm64': 'm'}> +CONFIG_DVB_AV7110 policy<{'arm64': 'm'}> +CONFIG_DVB_AV7110_IR policy<{'arm64': 'y'}> +CONFIG_DVB_AV7110_OSD policy<{'arm64': 'y'}> +CONFIG_DVB_B2C2_FLEXCOP policy<{'arm64': 'm'}> +CONFIG_DVB_B2C2_FLEXCOP_PCI policy<{'arm64': 'm'}> +CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG policy<{'arm64': 'n'}> +CONFIG_DVB_B2C2_FLEXCOP_USB policy<{'arm64': 'm'}> +CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG policy<{'arm64': 'n'}> +CONFIG_DVB_BCM3510 policy<{'arm64': 'm'}> +CONFIG_DVB_BT8XX policy<{'arm64': 'm'}> +CONFIG_DVB_BUDGET policy<{'arm64': 'm'}> +CONFIG_DVB_BUDGET_AV policy<{'arm64': 'm'}> +CONFIG_DVB_BUDGET_CI policy<{'arm64': 'm'}> +CONFIG_DVB_BUDGET_CORE policy<{'arm64': 'm'}> +CONFIG_DVB_CORE policy<{'arm64': 'm'}> +CONFIG_DVB_CX22700 policy<{'arm64': 'm'}> +CONFIG_DVB_CX22702 policy<{'arm64': 'm'}> +CONFIG_DVB_CX24110 policy<{'arm64': 'm'}> +CONFIG_DVB_CX24116 policy<{'arm64': 'm'}> +CONFIG_DVB_CX24117 policy<{'arm64': 'm'}> +CONFIG_DVB_CX24120 policy<{'arm64': 'm'}> +CONFIG_DVB_CX24123 policy<{'arm64': 'm'}> +CONFIG_DVB_CXD2099 policy<{'arm64': 'm'}> +CONFIG_DVB_CXD2820R policy<{'arm64': 'm'}> +CONFIG_DVB_CXD2841ER policy<{'arm64': 'm'}> +CONFIG_DVB_CXD2880 policy<{'arm64': 'm'}> +CONFIG_DVB_DDBRIDGE policy<{'arm64': 'm'}> +CONFIG_DVB_DDBRIDGE_MSIENABLE policy<{'arm64': 'n'}> +CONFIG_DVB_DEMUX_SECTION_LOSS_LOG policy<{'arm64': 'n'}> +CONFIG_DVB_DIB3000MB policy<{'arm64': 'm'}> +CONFIG_DVB_DIB3000MC policy<{'arm64': 'm'}> +CONFIG_DVB_DIB7000M policy<{'arm64': 'm'}> +CONFIG_DVB_DIB7000P policy<{'arm64': 'm'}> +CONFIG_DVB_DIB8000 policy<{'arm64': 'm'}> +CONFIG_DVB_DIB9000 policy<{'arm64': 'm'}> +CONFIG_DVB_DM1105 policy<{'arm64': 'm'}> +CONFIG_DVB_DRX39XYJ policy<{'arm64': 'm'}> +CONFIG_DVB_DRXD policy<{'arm64': 'm'}> +CONFIG_DVB_DRXK policy<{'arm64': 'm'}> +CONFIG_DVB_DS3000 policy<{'arm64': 'm'}> +CONFIG_DVB_DYNAMIC_MINORS policy<{'arm64': 'y'}> +CONFIG_DVB_EC100 policy<{'arm64': 'm'}> +CONFIG_DVB_FIREDTV policy<{'arm64': 'm'}> +CONFIG_DVB_FIREDTV_INPUT policy<{'arm64': 'y'}> +CONFIG_DVB_GP8PSK_FE policy<{'arm64': 'm'}> +CONFIG_DVB_HELENE policy<{'arm64': 'm'}> +CONFIG_DVB_HOPPER policy<{'arm64': 'm'}> +CONFIG_DVB_HORUS3A policy<{'arm64': 'm'}> +CONFIG_DVB_ISL6405 policy<{'arm64': 'm'}> +CONFIG_DVB_ISL6421 policy<{'arm64': 'm'}> +CONFIG_DVB_ISL6423 policy<{'arm64': 'm'}> +CONFIG_DVB_IX2505V policy<{'arm64': 'm'}> +CONFIG_DVB_L64781 policy<{'arm64': 'm'}> +CONFIG_DVB_LG2160 policy<{'arm64': 'm'}> +CONFIG_DVB_LGDT3305 policy<{'arm64': 'm'}> +CONFIG_DVB_LGDT3306A policy<{'arm64': 'm'}> +CONFIG_DVB_LGDT330X policy<{'arm64': 'm'}> +CONFIG_DVB_LGS8GL5 policy<{'arm64': 'm'}> +CONFIG_DVB_LGS8GXX policy<{'arm64': 'm'}> +CONFIG_DVB_LNBH25 policy<{'arm64': 'm'}> +CONFIG_DVB_LNBH29 policy<{'arm64': 'm'}> +CONFIG_DVB_LNBP21 policy<{'arm64': 'm'}> +CONFIG_DVB_LNBP22 policy<{'arm64': 'm'}> +CONFIG_DVB_M88DS3103 policy<{'arm64': 'm'}> +CONFIG_DVB_M88RS2000 policy<{'arm64': 'm'}> +CONFIG_DVB_MANTIS policy<{'arm64': 'm'}> +CONFIG_DVB_MAX_ADAPTERS policy<{'arm64': '8'}> +CONFIG_DVB_MB86A16 policy<{'arm64': 'm'}> +CONFIG_DVB_MB86A20S policy<{'arm64': 'm'}> +CONFIG_DVB_MMAP policy<{'arm64': 'n'}> +CONFIG_DVB_MN88443X policy<{'arm64': 'm'}> +CONFIG_DVB_MN88472 policy<{'arm64': 'm'}> +CONFIG_DVB_MN88473 policy<{'arm64': 'm'}> +CONFIG_DVB_MT312 policy<{'arm64': 'm'}> +CONFIG_DVB_MT352 policy<{'arm64': 'm'}> +CONFIG_DVB_MXL5XX policy<{'arm64': 'm'}> +CONFIG_DVB_MXL692 policy<{'arm64': 'm'}> +CONFIG_DVB_NET policy<{'arm64': 'y'}> +CONFIG_DVB_NETUP_UNIDVB policy<{'arm64': 'm'}> +CONFIG_DVB_NGENE policy<{'arm64': 'm'}> +CONFIG_DVB_NXT200X policy<{'arm64': 'm'}> +CONFIG_DVB_NXT6000 policy<{'arm64': 'm'}> +CONFIG_DVB_OR51132 policy<{'arm64': 'm'}> +CONFIG_DVB_OR51211 policy<{'arm64': 'm'}> +CONFIG_DVB_PLATFORM_DRIVERS policy<{'arm64': 'y'}> +CONFIG_DVB_PLL policy<{'arm64': 'm'}> +CONFIG_DVB_PLUTO2 policy<{'arm64': 'm'}> +CONFIG_DVB_PT1 policy<{'arm64': 'm'}> +CONFIG_DVB_PT3 policy<{'arm64': 'm'}> +CONFIG_DVB_RTL2830 policy<{'arm64': 'm'}> +CONFIG_DVB_RTL2832 policy<{'arm64': 'm'}> +CONFIG_DVB_RTL2832_SDR policy<{'arm64': 'm'}> +CONFIG_DVB_S5H1409 policy<{'arm64': 'm'}> +CONFIG_DVB_S5H1411 policy<{'arm64': 'm'}> +CONFIG_DVB_S5H1420 policy<{'arm64': 'm'}> +CONFIG_DVB_S5H1432 policy<{'arm64': 'm'}> +CONFIG_DVB_S921 policy<{'arm64': 'm'}> +CONFIG_DVB_SI2165 policy<{'arm64': 'm'}> +CONFIG_DVB_SI2168 policy<{'arm64': 'm'}> +CONFIG_DVB_SI21XX policy<{'arm64': 'm'}> +CONFIG_DVB_SMIPCIE policy<{'arm64': 'm'}> +CONFIG_DVB_SP2 policy<{'arm64': 'm'}> +CONFIG_DVB_SP8870 policy<{'arm64': 'm'}> +CONFIG_DVB_SP887X policy<{'arm64': 'm'}> +CONFIG_DVB_STB0899 policy<{'arm64': 'm'}> +CONFIG_DVB_STB6000 policy<{'arm64': 'm'}> +CONFIG_DVB_STB6100 policy<{'arm64': 'm'}> +CONFIG_DVB_STV0288 policy<{'arm64': 'm'}> +CONFIG_DVB_STV0297 policy<{'arm64': 'm'}> +CONFIG_DVB_STV0299 policy<{'arm64': 'm'}> +CONFIG_DVB_STV0367 policy<{'arm64': 'm'}> +CONFIG_DVB_STV0900 policy<{'arm64': 'm'}> +CONFIG_DVB_STV090x policy<{'arm64': 'm'}> +CONFIG_DVB_STV0910 policy<{'arm64': 'm'}> +CONFIG_DVB_STV6110 policy<{'arm64': 'm'}> +CONFIG_DVB_STV6110x policy<{'arm64': 'm'}> +CONFIG_DVB_STV6111 policy<{'arm64': 'm'}> +CONFIG_DVB_TC90522 policy<{'arm64': 'm'}> +CONFIG_DVB_TDA10021 policy<{'arm64': 'm'}> +CONFIG_DVB_TDA10023 policy<{'arm64': 'm'}> +CONFIG_DVB_TDA10048 policy<{'arm64': 'm'}> +CONFIG_DVB_TDA1004X policy<{'arm64': 'm'}> +CONFIG_DVB_TDA10071 policy<{'arm64': 'm'}> +CONFIG_DVB_TDA10086 policy<{'arm64': 'm'}> +CONFIG_DVB_TDA18271C2DD policy<{'arm64': 'm'}> +CONFIG_DVB_TDA665x policy<{'arm64': 'm'}> +CONFIG_DVB_TDA8083 policy<{'arm64': 'm'}> +CONFIG_DVB_TDA8261 policy<{'arm64': 'm'}> +CONFIG_DVB_TDA826X policy<{'arm64': 'm'}> +CONFIG_DVB_TEST_DRIVERS policy<{'arm64': 'n'}> +CONFIG_DVB_TS2020 policy<{'arm64': 'm'}> +CONFIG_DVB_TTUSB_BUDGET policy<{'arm64': 'm'}> +CONFIG_DVB_TTUSB_DEC policy<{'arm64': 'm'}> +CONFIG_DVB_TUA6100 policy<{'arm64': 'm'}> +CONFIG_DVB_TUNER_CX24113 policy<{'arm64': 'm'}> +CONFIG_DVB_TUNER_DIB0070 policy<{'arm64': 'm'}> +CONFIG_DVB_TUNER_DIB0090 policy<{'arm64': 'm'}> +CONFIG_DVB_TUNER_ITD1000 policy<{'arm64': 'm'}> +CONFIG_DVB_ULE_DEBUG policy<{'arm64': 'n'}> +CONFIG_DVB_USB policy<{'arm64': 'm'}> +CONFIG_DVB_USB_A800 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_AF9005 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_AF9005_REMOTE policy<{'arm64': 'm'}> +CONFIG_DVB_USB_AF9015 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_AF9035 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_ANYSEE policy<{'arm64': 'm'}> +CONFIG_DVB_USB_AU6610 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_AZ6007 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_AZ6027 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_CE6230 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_CINERGY_T2 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_CXUSB policy<{'arm64': 'm'}> +CONFIG_DVB_USB_CXUSB_ANALOG policy<{'arm64': 'y'}> +CONFIG_DVB_USB_DEBUG policy<{'arm64': 'n'}> +CONFIG_DVB_USB_DIB0700 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_DIB3000MC policy<{'arm64': 'm'}> +CONFIG_DVB_USB_DIBUSB_MB policy<{'arm64': 'm'}> +CONFIG_DVB_USB_DIBUSB_MB_FAULTY policy<{'arm64': 'n'}> +CONFIG_DVB_USB_DIBUSB_MC policy<{'arm64': 'm'}> +CONFIG_DVB_USB_DIGITV policy<{'arm64': 'm'}> +CONFIG_DVB_USB_DTT200U policy<{'arm64': 'm'}> +CONFIG_DVB_USB_DTV5100 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_DVBSKY policy<{'arm64': 'm'}> +CONFIG_DVB_USB_DW2102 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_EC168 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_GL861 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_GP8PSK policy<{'arm64': 'm'}> +CONFIG_DVB_USB_LME2510 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_M920X policy<{'arm64': 'm'}> +CONFIG_DVB_USB_MXL111SF policy<{'arm64': 'm'}> +CONFIG_DVB_USB_NOVA_T_USB2 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_OPERA1 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_PCTV452E policy<{'arm64': 'm'}> +CONFIG_DVB_USB_RTL28XXU policy<{'arm64': 'm'}> +CONFIG_DVB_USB_TECHNISAT_USB2 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_TTUSB2 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_UMT_010 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_V2 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_VP702X policy<{'arm64': 'm'}> +CONFIG_DVB_USB_VP7045 policy<{'arm64': 'm'}> +CONFIG_DVB_USB_ZD1301 policy<{'arm64': 'm'}> +CONFIG_DVB_VES1820 policy<{'arm64': 'm'}> +CONFIG_DVB_VES1X93 policy<{'arm64': 'm'}> +CONFIG_DVB_ZD1301_DEMOD policy<{'arm64': 'm'}> +CONFIG_DVB_ZL10036 policy<{'arm64': 'm'}> +CONFIG_DVB_ZL10039 policy<{'arm64': 'm'}> +CONFIG_DVB_ZL10353 policy<{'arm64': 'm'}> +CONFIG_DWC_PCIE_PMU policy<{'arm64': 'm'}> +CONFIG_DWC_XLGMAC policy<{'arm64': 'm'}> +CONFIG_DWC_XLGMAC_PCI policy<{'arm64': 'm'}> +CONFIG_DWMAC_DWC_QOS_ETH policy<{'arm64': 'm'}> +CONFIG_DWMAC_GENERIC policy<{'arm64': 'm'}> +CONFIG_DWMAC_IMX8 policy<{'arm64': 'm'}> +CONFIG_DWMAC_INTEL_PLAT policy<{'arm64': 'm'}> +CONFIG_DWMAC_IPQ806X policy<{'arm64': 'm'}> +CONFIG_DWMAC_MEDIATEK policy<{'arm64': 'm'}> +CONFIG_DWMAC_MESON policy<{'arm64': 'm'}> +CONFIG_DWMAC_MOTORCOMM policy<{'arm64': 'n'}> +CONFIG_DWMAC_NUVOTON policy<{'arm64': 'm'}> +CONFIG_DWMAC_QCOM_ETHQOS policy<{'arm64': 'm'}> +CONFIG_DWMAC_RENESAS_GBETH policy<{'arm64': 'm'}> +CONFIG_DWMAC_ROCKCHIP policy<{'arm64': 'm'}> +CONFIG_DWMAC_S32 policy<{'arm64': 'm'}> +CONFIG_DWMAC_SOCFPGA policy<{'arm64': 'm'}> +CONFIG_DWMAC_STM32 policy<{'arm64': 'm'}> +CONFIG_DWMAC_SUN55I policy<{'arm64': 'm'}> +CONFIG_DWMAC_SUN8I policy<{'arm64': 'm'}> +CONFIG_DWMAC_SUNXI policy<{'arm64': 'm'}> +CONFIG_DWMAC_TEGRA policy<{'arm64': 'm'}> +CONFIG_DWMAC_VISCONTI policy<{'arm64': 'm'}> +CONFIG_DW_APB_ICTL policy<{'arm64': 'y'}> +CONFIG_DW_APB_TIMER policy<{'arm64': 'y'}> +CONFIG_DW_APB_TIMER_OF policy<{'arm64': 'y'}> +CONFIG_DW_AXI_DMAC policy<{'arm64': 'm'}> +CONFIG_DW_DMAC policy<{'arm64': 'm'}> +CONFIG_DW_DMAC_CORE policy<{'arm64': 'm'}> +CONFIG_DW_DMAC_PCI policy<{'arm64': 'm'}> +CONFIG_DW_EDMA policy<{'arm64': 'm'}> +CONFIG_DW_EDMA_PCIE policy<{'arm64': 'm'}> +CONFIG_DW_I3C_MASTER policy<{'arm64': 'm'}> +CONFIG_DW_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_DW_XDATA_PCIE policy<{'arm64': 'm'}> +CONFIG_DYNAMIC_DEBUG policy<{'arm64': 'y'}> +CONFIG_DYNAMIC_DEBUG_CORE policy<{'arm64': 'y'}> +CONFIG_DYNAMIC_EVENTS policy<{'arm64': 'y'}> +CONFIG_DYNAMIC_FTRACE policy<{'arm64': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_ARGS policy<{'arm64': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS policy<{'arm64': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS policy<{'arm64': 'y'}> +CONFIG_E100 policy<{'arm64': 'm'}> +CONFIG_E1000 policy<{'arm64': 'm'}> +CONFIG_E1000E policy<{'arm64': 'm'}> +CONFIG_ECRYPT_FS_MESSAGING policy<{'arm64': 'y'}> +CONFIG_EC_ACER_ASPIRE1 policy<{'arm64': 'm'}> +CONFIG_EC_DELL_XPS policy<{'arm64': 'n'}> +CONFIG_EC_HUAWEI_GAOKUN policy<{'arm64': 'm'}> +CONFIG_EC_LENOVO_THINKPAD_T14S policy<{'arm64': 'm'}> +CONFIG_EC_LENOVO_YOGA_C630 policy<{'arm64': 'm'}> +CONFIG_EC_LENOVO_YOGA_SLIM7X policy<{'arm64': 'n'}> +CONFIG_EC_QCOM_HAMOA policy<{'arm64': 'n'}> +CONFIG_EDAC policy<{'arm64': 'y'}> +CONFIG_EDAC_ALTERA policy<{'arm64': 'y'}> +CONFIG_EDAC_ALTERA_ETHERNET policy<{'arm64': 'y'}> +CONFIG_EDAC_ALTERA_NAND policy<{'arm64': 'y'}> +CONFIG_EDAC_ALTERA_OCRAM policy<{'arm64': 'y'}> +CONFIG_EDAC_ALTERA_QSPI policy<{'arm64': 'y'}> +CONFIG_EDAC_ALTERA_SDMMC policy<{'arm64': 'y'}> +CONFIG_EDAC_ALTERA_SDRAM policy<{'arm64': 'y'}> +CONFIG_EDAC_ALTERA_USB policy<{'arm64': 'y'}> +CONFIG_EDAC_BLUEFIELD policy<{'arm64': 'm'}> +CONFIG_EDAC_CORTEX_A72 policy<{'arm64': 'n'}> +CONFIG_EDAC_DEBUG policy<{'arm64': 'n'}> +CONFIG_EDAC_DMC520 policy<{'arm64': 'm'}> +CONFIG_EDAC_ECS policy<{'arm64': 'n'}> +CONFIG_EDAC_GHES policy<{'arm64': 'y'}> +CONFIG_EDAC_LAYERSCAPE policy<{'arm64': 'm'}> +CONFIG_EDAC_MEM_REPAIR policy<{'arm64': 'n'}> +CONFIG_EDAC_NPCM policy<{'arm64': 'm'}> +CONFIG_EDAC_QCOM policy<{'arm64': 'm'}> +CONFIG_EDAC_SCRUB policy<{'arm64': 'n'}> +CONFIG_EDAC_SUPPORT policy<{'arm64': 'y'}> +CONFIG_EDAC_SYNOPSYS policy<{'arm64': 'm'}> +CONFIG_EDAC_THUNDERX policy<{'arm64': 'm'}> +CONFIG_EDAC_VERSAL policy<{'arm64': 'm'}> +CONFIG_EDAC_VERSALNET policy<{'arm64': 'n'}> +CONFIG_EDAC_XGENE policy<{'arm64': 'm'}> +CONFIG_EDAC_ZYNQMP policy<{'arm64': 'm'}> +CONFIG_EEPROM_93CX6 policy<{'arm64': 'm'}> +CONFIG_EEPROM_93XX46 policy<{'arm64': 'm'}> +CONFIG_EEPROM_AT24 policy<{'arm64': 'm'}> +CONFIG_EEPROM_AT25 policy<{'arm64': 'm'}> +CONFIG_EEPROM_EE1004 policy<{'arm64': 'm'}> +CONFIG_EEPROM_IDT_89HPESX policy<{'arm64': 'm'}> +CONFIG_EEPROM_M24LR policy<{'arm64': 'n'}> +CONFIG_EEPROM_MAX6875 policy<{'arm64': 'm'}> +CONFIG_EFI policy<{'arm64': 'y'}> +CONFIG_EFI_ARMSTUB_DTB_LOADER policy<{'arm64': 'n'}> +CONFIG_EFI_BOOTLOADER_CONTROL policy<{'arm64': 'm'}> +CONFIG_EFI_CAPSULE_LOADER policy<{'arm64': 'm'}> +CONFIG_EFI_COCO_SECRET policy<{'arm64': 'y'}> +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS policy<{'arm64': 'y'}> +CONFIG_EFI_DISABLE_PCI_DMA policy<{'arm64': 'n'}> +CONFIG_EFI_DISABLE_RUNTIME policy<{'arm64': 'n'}> +CONFIG_EFI_EARLYCON policy<{'arm64': 'y'}> +CONFIG_EFI_ESRT policy<{'arm64': 'y'}> +CONFIG_EFI_GENERIC_STUB policy<{'arm64': 'y'}> +CONFIG_EFI_PARAMS_FROM_FDT policy<{'arm64': 'y'}> +CONFIG_EFI_PARTITION policy<{'arm64': 'y'}> +CONFIG_EFI_RUNTIME_WRAPPERS policy<{'arm64': 'y'}> +CONFIG_EFI_SBAT_FILE policy<{'arm64': '""'}> +CONFIG_EFI_SECRET policy<{'arm64': 'n'}> +CONFIG_EFI_SOFT_RESERVE policy<{'arm64': 'y'}> +CONFIG_EFI_STUB policy<{'arm64': 'y'}> +CONFIG_EFI_TEST policy<{'arm64': 'm'}> +CONFIG_EFI_VARS_PSTORE policy<{'arm64': 'm'}> +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE policy<{'arm64': 'n'}> +CONFIG_EFS_FS policy<{'arm64': 'm'}> +CONFIG_EINT_MTK policy<{'arm64': 'y'}> +CONFIG_ELFCORE policy<{'arm64': 'y'}> +CONFIG_ELF_CORE policy<{'arm64': 'y'}> +CONFIG_EMAC_ROCKCHIP policy<{'arm64': 'm'}> +CONFIG_ENA_ETHERNET policy<{'arm64': 'm'}> +CONFIG_ENC28J60 policy<{'arm64': 'm'}> +CONFIG_ENC28J60_WRITEVERIFY policy<{'arm64': 'n'}> +CONFIG_ENCLOSURE_SERVICES policy<{'arm64': 'm'}> +CONFIG_ENCRYPTED_KEYS policy<{'arm64': 'y'}> +CONFIG_ENCX24J600 policy<{'arm64': 'm'}> +CONFIG_ENERGY_MODEL policy<{'arm64': 'y'}> +CONFIG_ENIC policy<{'arm64': 'm'}> +CONFIG_ENS160 policy<{'arm64': 'm'}> +CONFIG_ENS160_I2C policy<{'arm64': 'm'}> +CONFIG_ENS160_SPI policy<{'arm64': 'm'}> +CONFIG_ENS210 policy<{'arm64': 'm'}> +CONFIG_ENVELOPE_DETECTOR policy<{'arm64': 'm'}> +CONFIG_EPIC100 policy<{'arm64': 'm'}> +CONFIG_EPOLL policy<{'arm64': 'y'}> +CONFIG_EPROBE_EVENTS policy<{'arm64': 'y'}> +CONFIG_EQUALIZER policy<{'arm64': 'm'}> +CONFIG_EROFS_FS policy<{'arm64': 'm'}> +CONFIG_EROFS_FS_BACKED_BY_FILE policy<{'arm64': 'y'}> +CONFIG_EROFS_FS_DEBUG policy<{'arm64': 'n'}> +CONFIG_EROFS_FS_PAGE_CACHE_SHARE policy<{'arm64': 'n'}> +CONFIG_EROFS_FS_PCPU_KTHREAD policy<{'arm64': 'y'}> +CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI policy<{'arm64': 'n'}> +CONFIG_EROFS_FS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_EROFS_FS_SECURITY policy<{'arm64': 'y'}> +CONFIG_EROFS_FS_XATTR policy<{'arm64': 'y'}> +CONFIG_EROFS_FS_ZIP policy<{'arm64': 'y'}> +CONFIG_EROFS_FS_ZIP_ACCEL policy<{'arm64': 'n'}> +CONFIG_EROFS_FS_ZIP_DEFLATE policy<{'arm64': 'y'}> +CONFIG_EROFS_FS_ZIP_LZMA policy<{'arm64': 'y'}> +CONFIG_EROFS_FS_ZIP_LZMA_DEFAULT_MAX_STREAMS policy<{'arm64': '16'}> +CONFIG_EROFS_FS_ZIP_ZSTD policy<{'arm64': 'y'}> +CONFIG_ET131X policy<{'arm64': 'm'}> +CONFIG_ETHERNET policy<{'arm64': 'y'}> +CONFIG_ETHOC policy<{'arm64': 'm'}> +CONFIG_ETHTOOL_NETLINK policy<{'arm64': 'y'}> +CONFIG_EVENTFD policy<{'arm64': 'y'}> +CONFIG_EVENT_TRACING policy<{'arm64': 'y'}> +CONFIG_EVM_ADD_XATTRS policy<{'arm64': 'y'}> +CONFIG_EVM_EXTRA_SMACK_XATTRS policy<{'arm64': 'y'}> +CONFIG_EVM_LOAD_X509 policy<{'arm64': 'n'}> +CONFIG_EXCLUSIVE_SYSTEM_RAM policy<{'arm64': 'y'}> +CONFIG_EXECMEM policy<{'arm64': 'y'}> +CONFIG_EXFAT_DEFAULT_IOCHARSET policy<{'arm64': '"utf8"'}> +CONFIG_EXFAT_FS policy<{'arm64': 'm'}> +CONFIG_EXPERT policy<{'arm64': 'y'}> +CONFIG_EXPORTFS policy<{'arm64': 'y'}> +CONFIG_EXPORTFS_BLOCK_OPS policy<{'arm64': 'y'}> +CONFIG_EXT2_FS policy<{'arm64': 'n'}> +CONFIG_EXT4_DEBUG policy<{'arm64': 'n'}> +CONFIG_EXT4_FS policy<{'arm64': 'y'}> +CONFIG_EXT4_FS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_EXT4_FS_SECURITY policy<{'arm64': 'y'}> +CONFIG_EXT4_USE_FOR_EXT2 policy<{'arm64': 'y'}> +CONFIG_EXTCON policy<{'arm64': 'y'}> +CONFIG_EXTCON_ADC_JACK policy<{'arm64': 'm'}> +CONFIG_EXTCON_FSA9480 policy<{'arm64': 'm'}> +CONFIG_EXTCON_GPIO policy<{'arm64': 'm'}> +CONFIG_EXTCON_LC824206XA policy<{'arm64': 'm'}> +CONFIG_EXTCON_MAX14526 policy<{'arm64': 'n'}> +CONFIG_EXTCON_MAX14577 policy<{'arm64': 'm'}> +CONFIG_EXTCON_MAX3355 policy<{'arm64': 'm'}> +CONFIG_EXTCON_MAX77693 policy<{'arm64': 'm'}> +CONFIG_EXTCON_MAX77843 policy<{'arm64': 'm'}> +CONFIG_EXTCON_MAX8997 policy<{'arm64': 'm'}> +CONFIG_EXTCON_PALMAS policy<{'arm64': 'm'}> +CONFIG_EXTCON_PTN5150 policy<{'arm64': 'm'}> +CONFIG_EXTCON_QCOM_SPMI_MISC policy<{'arm64': 'm'}> +CONFIG_EXTCON_RT8973A policy<{'arm64': 'm'}> +CONFIG_EXTCON_RTK_TYPE_C policy<{'arm64': 'm'}> +CONFIG_EXTCON_SM5502 policy<{'arm64': 'm'}> +CONFIG_EXTCON_USBC_CROS_EC policy<{'arm64': 'm'}> +CONFIG_EXTCON_USBC_TUSB320 policy<{'arm64': 'm'}> +CONFIG_EXTCON_USB_GPIO policy<{'arm64': 'm'}> +CONFIG_EXTENDED_MODVERSIONS policy<{'arm64': 'y'}> +CONFIG_EXTRA_FIRMWARE policy<{'arm64': '""'}> +CONFIG_EZCHIP_NPS_MANAGEMENT_ENET policy<{'arm64': 'm'}> +CONFIG_F2FS_CHECK_FS policy<{'arm64': 'n'}> +CONFIG_F2FS_FAULT_INJECTION policy<{'arm64': 'n'}> +CONFIG_F2FS_FS policy<{'arm64': 'm'}> +CONFIG_F2FS_FS_COMPRESSION policy<{'arm64': 'y'}> +CONFIG_F2FS_FS_LZ4 policy<{'arm64': 'y'}> +CONFIG_F2FS_FS_LZ4HC policy<{'arm64': 'y'}> +CONFIG_F2FS_FS_LZO policy<{'arm64': 'y'}> +CONFIG_F2FS_FS_LZORLE policy<{'arm64': 'y'}> +CONFIG_F2FS_FS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_F2FS_FS_SECURITY policy<{'arm64': 'y'}> +CONFIG_F2FS_FS_XATTR policy<{'arm64': 'y'}> +CONFIG_F2FS_FS_ZSTD policy<{'arm64': 'y'}> +CONFIG_F2FS_IOSTAT policy<{'arm64': 'y'}> +CONFIG_F2FS_STAT_FS policy<{'arm64': 'y'}> +CONFIG_F2FS_UNFAIR_RWSEM policy<{'arm64': 'y'}> +CONFIG_FAILOVER policy<{'arm64': 'y'}> +CONFIG_FAIR_GROUP_SCHED policy<{'arm64': 'y'}> +CONFIG_FANOTIFY policy<{'arm64': 'y'}> +CONFIG_FANOTIFY_ACCESS_PERMISSIONS policy<{'arm64': 'y'}> +CONFIG_FARSYNC policy<{'arm64': 'm'}> +CONFIG_FAT_DEFAULT_CODEPAGE policy<{'arm64': '437'}> +CONFIG_FAT_DEFAULT_IOCHARSET policy<{'arm64': '"iso8859-1"'}> +CONFIG_FAT_DEFAULT_UTF8 policy<{'arm64': 'n'}> +CONFIG_FAT_FS policy<{'arm64': 'y'}> +CONFIG_FAULT_INJECTION policy<{'arm64': 'n'}> +CONFIG_FB policy<{'arm64': 'y'}> +CONFIG_FBNIC policy<{'arm64': 'n'}> +CONFIG_FB_3DFX policy<{'arm64': 'm'}> +CONFIG_FB_3DFX_ACCEL policy<{'arm64': 'n'}> +CONFIG_FB_3DFX_I2C policy<{'arm64': 'n'}> +CONFIG_FB_ARK policy<{'arm64': 'm'}> +CONFIG_FB_ASILIANT policy<{'arm64': 'y'}> +CONFIG_FB_ATY policy<{'arm64': 'm'}> +CONFIG_FB_ATY128 policy<{'arm64': 'm'}> +CONFIG_FB_ATY128_BACKLIGHT policy<{'arm64': 'y'}> +CONFIG_FB_ATY_BACKLIGHT policy<{'arm64': 'y'}> +CONFIG_FB_ATY_CT policy<{'arm64': 'y'}> +CONFIG_FB_ATY_GENERIC_LCD policy<{'arm64': 'n'}> +CONFIG_FB_ATY_GX policy<{'arm64': 'y'}> +CONFIG_FB_BACKLIGHT policy<{'arm64': 'y'}> +CONFIG_FB_CARMINE policy<{'arm64': 'm'}> +CONFIG_FB_CARMINE_DRAM_EVAL policy<{'arm64': 'y'}> +CONFIG_FB_CFB_COPYAREA policy<{'arm64': 'y'}> +CONFIG_FB_CFB_FILLRECT policy<{'arm64': 'y'}> +CONFIG_FB_CFB_IMAGEBLIT policy<{'arm64': 'y'}> +CONFIG_FB_CFB_REV_PIXELS_IN_BYTE policy<{'arm64': 'y'}> +CONFIG_FB_CIRRUS policy<{'arm64': 'm'}> +CONFIG_FB_CORE policy<{'arm64': 'y'}> +CONFIG_FB_CYBER2000 policy<{'arm64': 'm'}> +CONFIG_FB_CYBER2000_DDC policy<{'arm64': 'y'}> +CONFIG_FB_DDC policy<{'arm64': 'm'}> +CONFIG_FB_DEFERRED_IO policy<{'arm64': 'y'}> +CONFIG_FB_DEVICE policy<{'arm64': 'y'}> +CONFIG_FB_DMAMEM_HELPERS policy<{'arm64': 'y'}> +CONFIG_FB_DMAMEM_HELPERS_DEFERRED policy<{'arm64': 'y'}> +CONFIG_FB_EFI policy<{'arm64': 'y'}> +CONFIG_FB_FOREIGN_ENDIAN policy<{'arm64': 'n'}> +CONFIG_FB_I740 policy<{'arm64': 'm'}> +CONFIG_FB_IBM_GXT4500 policy<{'arm64': 'n'}> +CONFIG_FB_IMSTT policy<{'arm64': 'y'}> +CONFIG_FB_IMX policy<{'arm64': 'm'}> +CONFIG_FB_IOMEM_FOPS policy<{'arm64': 'y'}> +CONFIG_FB_IOMEM_HELPERS policy<{'arm64': 'y'}> +CONFIG_FB_KYRO policy<{'arm64': 'm'}> +CONFIG_FB_MATROX policy<{'arm64': 'm'}> +CONFIG_FB_MATROX_G policy<{'arm64': 'y'}> +CONFIG_FB_MATROX_I2C policy<{'arm64': 'm'}> +CONFIG_FB_MATROX_MAVEN policy<{'arm64': 'm'}> +CONFIG_FB_MATROX_MILLENIUM policy<{'arm64': 'y'}> +CONFIG_FB_MATROX_MYSTIQUE policy<{'arm64': 'y'}> +CONFIG_FB_MB862XX policy<{'arm64': 'm'}> +CONFIG_FB_MB862XX_I2C policy<{'arm64': 'y'}> +CONFIG_FB_MB862XX_PCI_GDC policy<{'arm64': 'y'}> +CONFIG_FB_METRONOME policy<{'arm64': 'm'}> +CONFIG_FB_MODE_HELPERS policy<{'arm64': 'y'}> +CONFIG_FB_NEOMAGIC policy<{'arm64': 'm'}> +CONFIG_FB_NOTIFY policy<{'arm64': 'y'}> +CONFIG_FB_NVIDIA policy<{'arm64': 'm'}> +CONFIG_FB_NVIDIA_BACKLIGHT policy<{'arm64': 'y'}> +CONFIG_FB_NVIDIA_DEBUG policy<{'arm64': 'n'}> +CONFIG_FB_NVIDIA_I2C policy<{'arm64': 'y'}> +CONFIG_FB_OPENCORES policy<{'arm64': 'm'}> +CONFIG_FB_PM2 policy<{'arm64': 'm'}> +CONFIG_FB_PM2_FIFO_DISCONNECT policy<{'arm64': 'y'}> +CONFIG_FB_PM3 policy<{'arm64': 'm'}> +CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA policy<{'arm64': 'y'}> +CONFIG_FB_RADEON policy<{'arm64': 'm'}> +CONFIG_FB_RADEON_BACKLIGHT policy<{'arm64': 'y'}> +CONFIG_FB_RADEON_DEBUG policy<{'arm64': 'n'}> +CONFIG_FB_RADEON_I2C policy<{'arm64': 'y'}> +CONFIG_FB_RIVA policy<{'arm64': 'm'}> +CONFIG_FB_RIVA_BACKLIGHT policy<{'arm64': 'y'}> +CONFIG_FB_RIVA_DEBUG policy<{'arm64': 'n'}> +CONFIG_FB_RIVA_I2C policy<{'arm64': 'y'}> +CONFIG_FB_S1D13XXX policy<{'arm64': 'm'}> +CONFIG_FB_S3 policy<{'arm64': 'm'}> +CONFIG_FB_S3_DDC policy<{'arm64': 'y'}> +CONFIG_FB_SAVAGE policy<{'arm64': 'm'}> +CONFIG_FB_SAVAGE_ACCEL policy<{'arm64': 'n'}> +CONFIG_FB_SAVAGE_I2C policy<{'arm64': 'y'}> +CONFIG_FB_SIS policy<{'arm64': 'm'}> +CONFIG_FB_SIS_300 policy<{'arm64': 'y'}> +CONFIG_FB_SIS_315 policy<{'arm64': 'y'}> +CONFIG_FB_SM501 policy<{'arm64': 'm'}> +CONFIG_FB_SM712 policy<{'arm64': 'm'}> +CONFIG_FB_SM750 policy<{'arm64': 'm'}> +CONFIG_FB_SMSCUFX policy<{'arm64': 'm'}> +CONFIG_FB_SSD1307 policy<{'arm64': 'm'}> +CONFIG_FB_SVGALIB policy<{'arm64': 'm'}> +CONFIG_FB_SYSMEM_FOPS policy<{'arm64': 'y'}> +CONFIG_FB_SYSMEM_HELPERS policy<{'arm64': 'y'}> +CONFIG_FB_SYSMEM_HELPERS_DEFERRED policy<{'arm64': 'y'}> +CONFIG_FB_SYS_COPYAREA policy<{'arm64': 'y'}> +CONFIG_FB_SYS_FILLRECT policy<{'arm64': 'y'}> +CONFIG_FB_SYS_IMAGEBLIT policy<{'arm64': 'y'}> +CONFIG_FB_TFT policy<{'arm64': 'm'}> +CONFIG_FB_TFT_AGM1264K_FL policy<{'arm64': 'm'}> +CONFIG_FB_TFT_BD663474 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_HX8340BN policy<{'arm64': 'm'}> +CONFIG_FB_TFT_HX8347D policy<{'arm64': 'm'}> +CONFIG_FB_TFT_HX8353D policy<{'arm64': 'm'}> +CONFIG_FB_TFT_HX8357D policy<{'arm64': 'm'}> +CONFIG_FB_TFT_ILI9163 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_ILI9320 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_ILI9325 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_ILI9340 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_ILI9341 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_ILI9481 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_ILI9486 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_PCD8544 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_RA8875 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_S6D02A1 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_S6D1121 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_SEPS525 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_SH1106 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_SSD1289 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_SSD1305 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_SSD1306 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_SSD1331 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_SSD1351 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_ST7735R policy<{'arm64': 'm'}> +CONFIG_FB_TFT_ST7789V policy<{'arm64': 'm'}> +CONFIG_FB_TFT_TINYLCD policy<{'arm64': 'm'}> +CONFIG_FB_TFT_TLS8204 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_UC1611 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_UC1701 policy<{'arm64': 'm'}> +CONFIG_FB_TFT_UPD161704 policy<{'arm64': 'm'}> +CONFIG_FB_TILEBLITTING policy<{'arm64': 'y'}> +CONFIG_FB_TRIDENT policy<{'arm64': 'm'}> +CONFIG_FB_UDL policy<{'arm64': 'm'}> +CONFIG_FB_UVESA policy<{'arm64': 'm'}> +CONFIG_FB_VIRTUAL policy<{'arm64': 'n'}> +CONFIG_FB_VOODOO1 policy<{'arm64': 'm'}> +CONFIG_FB_VT8623 policy<{'arm64': 'm'}> +CONFIG_FB_XILINX policy<{'arm64': 'm'}> +CONFIG_FCOE policy<{'arm64': 'm'}> +CONFIG_FDDI policy<{'arm64': 'y'}> +CONFIG_FDMA policy<{'arm64': 'y'}> +CONFIG_FEALNX policy<{'arm64': 'm'}> +CONFIG_FEC policy<{'arm64': 'y'}> +CONFIG_FIB_RULES policy<{'arm64': 'y'}> +CONFIG_FILE_LOCKING policy<{'arm64': 'y'}> +CONFIG_FIND_BIT_BENCHMARK policy<{'arm64': 'n'}> +CONFIG_FIND_NORMAL_PAGE policy<{'arm64': 'y'}> +CONFIG_FIPS_SIGNATURE_SELFTEST policy<{'arm64': 'n'}> +CONFIG_FIREWIRE policy<{'arm64': 'm'}> +CONFIG_FIREWIRE_NET policy<{'arm64': 'm'}> +CONFIG_FIREWIRE_NOSY policy<{'arm64': 'm'}> +CONFIG_FIREWIRE_OHCI policy<{'arm64': 'm'}> +CONFIG_FIREWIRE_SBP2 policy<{'arm64': 'm'}> +CONFIG_FIRMWARE_EDID policy<{'arm64': 'n'}> +CONFIG_FIRMWARE_MEMMAP policy<{'arm64': 'y'}> +CONFIG_FIRMWARE_TABLE policy<{'arm64': 'y'}> +CONFIG_FIXED_PHY policy<{'arm64': 'y'}> +CONFIG_FIX_EARLYCON_MEM policy<{'arm64': 'y'}> +CONFIG_FM10K policy<{'arm64': 'm'}> +CONFIG_FONTS policy<{'arm64': 'y'}> +CONFIG_FONT_10x18 policy<{'arm64': 'n'}> +CONFIG_FONT_6x10 policy<{'arm64': 'y'}> +CONFIG_FONT_6x11 policy<{'arm64': 'n'}> +CONFIG_FONT_6x8 policy<{'arm64': 'n'}> +CONFIG_FONT_7x14 policy<{'arm64': 'n'}> +CONFIG_FONT_8x16 policy<{'arm64': 'y'}> +CONFIG_FONT_8x8 policy<{'arm64': 'y'}> +CONFIG_FONT_ACORN_8x8 policy<{'arm64': 'y'}> +CONFIG_FONT_MINI_4x6 policy<{'arm64': 'n'}> +CONFIG_FONT_PEARL_8x8 policy<{'arm64': 'n'}> +CONFIG_FONT_SUN12x22 policy<{'arm64': 'n'}> +CONFIG_FONT_SUN8x16 policy<{'arm64': 'n'}> +CONFIG_FONT_SUPPORT policy<{'arm64': 'y'}> +CONFIG_FONT_TER10x18 policy<{'arm64': 'n'}> +CONFIG_FONT_TER16x32 policy<{'arm64': 'y'}> +CONFIG_FORCEDETH policy<{'arm64': 'm'}> +CONFIG_FORTIFY_SOURCE policy<{'arm64': 'y'}> +CONFIG_FPGA policy<{'arm64': 'm'}> +CONFIG_FPGA_BRIDGE policy<{'arm64': 'm'}> +CONFIG_FPGA_DFL policy<{'arm64': 'm'}> +CONFIG_FPGA_DFL_AFU policy<{'arm64': 'm'}> +CONFIG_FPGA_DFL_EMIF policy<{'arm64': 'm'}> +CONFIG_FPGA_DFL_FME policy<{'arm64': 'm'}> +CONFIG_FPGA_DFL_FME_BRIDGE policy<{'arm64': 'm'}> +CONFIG_FPGA_DFL_FME_MGR policy<{'arm64': 'm'}> +CONFIG_FPGA_DFL_FME_REGION policy<{'arm64': 'm'}> +CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000 policy<{'arm64': 'm'}> +CONFIG_FPGA_DFL_PCI policy<{'arm64': 'm'}> +CONFIG_FPGA_M10_BMC_SEC_UPDATE policy<{'arm64': 'n'}> +CONFIG_FPGA_MGR_ALTERA_CVP policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_ALTERA_PS_SPI policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_EFINIX_SPI policy<{'arm64': 'n'}> +CONFIG_FPGA_MGR_ICE40_SPI policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_MACHXO2_SPI policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_MICROCHIP_SPI policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_SOCFPGA policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_SOCFPGA_A10 policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_STRATIX10_SOC policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_VERSAL_FPGA policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_XILINX_CORE policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_XILINX_SELECTMAP policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_XILINX_SPI policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_ZYNQMP_FPGA policy<{'arm64': 'm'}> +CONFIG_FPGA_REGION policy<{'arm64': 'm'}> +CONFIG_FPROBE policy<{'arm64': 'n'}> +CONFIG_FRAMEBUFFER_CONSOLE policy<{'arm64': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER policy<{'arm64': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY policy<{'arm64': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION policy<{'arm64': 'n'}> +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION policy<{'arm64': 'y'}> +CONFIG_FRAMER policy<{'arm64': 'm'}> +CONFIG_FRAMER_PEF2256 policy<{'arm64': 'm'}> +CONFIG_FRAME_POINTER policy<{'arm64': 'y'}> +CONFIG_FRAME_WARN policy<{'arm64': '1024'}> +CONFIG_FREEZER policy<{'arm64': 'y'}> +CONFIG_FSCACHE policy<{'arm64': 'y'}> +CONFIG_FSCACHE_STATS policy<{'arm64': 'y'}> +CONFIG_FSI policy<{'arm64': 'm'}> +CONFIG_FSI_MASTER_ASPEED policy<{'arm64': 'm'}> +CONFIG_FSI_MASTER_GPIO policy<{'arm64': 'm'}> +CONFIG_FSI_MASTER_HUB policy<{'arm64': 'm'}> +CONFIG_FSI_MASTER_I2CR policy<{'arm64': 'm'}> +CONFIG_FSI_NEW_DEV_NODE policy<{'arm64': 'n'}> +CONFIG_FSI_OCC policy<{'arm64': 'm'}> +CONFIG_FSI_SBEFIFO policy<{'arm64': 'm'}> +CONFIG_FSI_SCOM policy<{'arm64': 'm'}> +CONFIG_FSL_BMAN_TEST policy<{'arm64': 'm'}> +CONFIG_FSL_BMAN_TEST_API policy<{'arm64': 'y'}> +CONFIG_FSL_DPAA policy<{'arm64': 'y'}> +CONFIG_FSL_DPAA2_ETH policy<{'arm64': 'm'}> +CONFIG_FSL_DPAA2_ETH_DCB policy<{'arm64': 'y'}> +CONFIG_FSL_DPAA2_PTP_CLOCK policy<{'arm64': 'm'}> +CONFIG_FSL_DPAA2_QDMA policy<{'arm64': 'm'}> +CONFIG_FSL_DPAA2_SWITCH policy<{'arm64': 'm'}> +CONFIG_FSL_DPAA_CHECKING policy<{'arm64': 'y'}> +CONFIG_FSL_DPAA_ETH policy<{'arm64': 'm'}> +CONFIG_FSL_EDMA policy<{'arm64': 'm'}> +CONFIG_FSL_ENETC policy<{'arm64': 'm'}> +CONFIG_FSL_ENETC_CORE policy<{'arm64': 'm'}> +CONFIG_FSL_ENETC_IERB policy<{'arm64': 'm'}> +CONFIG_FSL_ENETC_MDIO policy<{'arm64': 'm'}> +CONFIG_FSL_ENETC_PTP_CLOCK policy<{'arm64': 'm'}> +CONFIG_FSL_ENETC_QOS policy<{'arm64': 'y'}> +CONFIG_FSL_ENETC_VF policy<{'arm64': 'm'}> +CONFIG_FSL_ERRATUM_A008585 policy<{'arm64': 'y'}> +CONFIG_FSL_FMAN policy<{'arm64': 'y'}> +CONFIG_FSL_GUTS policy<{'arm64': 'y'}> +CONFIG_FSL_IFC policy<{'arm64': 'y'}> +CONFIG_FSL_IMX8_DDR_PMU policy<{'arm64': 'm'}> +CONFIG_FSL_IMX9_DDR_PMU policy<{'arm64': 'm'}> +CONFIG_FSL_MC_BUS policy<{'arm64': 'y'}> +CONFIG_FSL_MC_DPIO policy<{'arm64': 'm'}> +CONFIG_FSL_MC_UAPI_SUPPORT policy<{'arm64': 'y'}> +CONFIG_FSL_PQ_MDIO policy<{'arm64': 'm'}> +CONFIG_FSL_QDMA policy<{'arm64': 'm'}> +CONFIG_FSL_QMAN_TEST policy<{'arm64': 'n'}> +CONFIG_FSL_RCPM policy<{'arm64': 'y'}> +CONFIG_FSL_UCC_HDLC policy<{'arm64': 'm'}> +CONFIG_FSL_XGMAC_MDIO policy<{'arm64': 'y'}> +CONFIG_FSNOTIFY policy<{'arm64': 'y'}> +CONFIG_FS_DAX policy<{'arm64': 'y'}> +CONFIG_FS_DAX_PMD policy<{'arm64': 'y'}> +CONFIG_FS_ENCRYPTION policy<{'arm64': 'y'}> +CONFIG_FS_ENCRYPTION_ALGS policy<{'arm64': 'y'}> +CONFIG_FS_ENCRYPTION_INLINE_CRYPT policy<{'arm64': 'y'}> +CONFIG_FS_IOMAP policy<{'arm64': 'y'}> +CONFIG_FS_MBCACHE policy<{'arm64': 'y'}> +CONFIG_FS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_FS_STACK policy<{'arm64': 'y'}> +CONFIG_FS_VERITY policy<{'arm64': 'y'}> +CONFIG_FS_VERITY_BUILTIN_SIGNATURES policy<{'arm64': 'y'}> +CONFIG_FTL policy<{'arm64': 'm'}> +CONFIG_FTRACE policy<{'arm64': 'y'}> +CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY policy<{'arm64': 'y'}> +CONFIG_FTRACE_RECORD_RECURSION policy<{'arm64': 'n'}> +CONFIG_FTRACE_SORT_STARTUP_TEST policy<{'arm64': 'n'}> +CONFIG_FTRACE_STARTUP_TEST policy<{'arm64': 'n'}> +CONFIG_FTRACE_SYSCALLS policy<{'arm64': 'y'}> +CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING policy<{'arm64': 'n'}> +CONFIG_FUEL_GAUGE_MM8013 policy<{'arm64': 'm'}> +CONFIG_FUEL_GAUGE_SC27XX policy<{'arm64': 'm'}> +CONFIG_FUEL_GAUGE_STC3117 policy<{'arm64': 'n'}> +CONFIG_FUJITSU_ERRATUM_010001 policy<{'arm64': 'y'}> +CONFIG_FUJITSU_ES policy<{'arm64': 'm'}> +CONFIG_FUJITSU_UNCORE_PMU policy<{'arm64': 'n'}> +CONFIG_FUNCTION_ALIGNMENT policy<{'arm64': '8'}> +CONFIG_FUNCTION_ALIGNMENT_4B policy<{'arm64': 'y'}> +CONFIG_FUNCTION_ALIGNMENT_8B policy<{'arm64': 'y'}> +CONFIG_FUNCTION_ERROR_INJECTION policy<{'arm64': 'y'}> +CONFIG_FUNCTION_GRAPH_RETADDR policy<{'arm64': 'n'}> +CONFIG_FUNCTION_GRAPH_RETVAL policy<{'arm64': 'y'}> +CONFIG_FUNCTION_GRAPH_TRACER policy<{'arm64': 'y'}> +CONFIG_FUNCTION_PROFILER policy<{'arm64': 'y'}> +CONFIG_FUNCTION_SELF_TRACING policy<{'arm64': 'n'}> +CONFIG_FUNCTION_TRACER policy<{'arm64': 'y'}> +CONFIG_FUN_CORE policy<{'arm64': 'm'}> +CONFIG_FUN_ETH policy<{'arm64': 'm'}> +CONFIG_FUSE_DAX policy<{'arm64': 'y'}> +CONFIG_FUSE_IO_URING policy<{'arm64': 'y'}> +CONFIG_FUSE_PASSTHROUGH policy<{'arm64': 'y'}> +CONFIG_FUSION policy<{'arm64': 'y'}> +CONFIG_FUSION_CTL policy<{'arm64': 'm'}> +CONFIG_FUSION_FC policy<{'arm64': 'm'}> +CONFIG_FUSION_LAN policy<{'arm64': 'm'}> +CONFIG_FUSION_LOGGING policy<{'arm64': 'y'}> +CONFIG_FUSION_MAX_SGE policy<{'arm64': '128'}> +CONFIG_FUSION_SAS policy<{'arm64': 'm'}> +CONFIG_FUSION_SPI policy<{'arm64': 'm'}> +CONFIG_FUTEX policy<{'arm64': 'y'}> +CONFIG_FUTEX_MPOL policy<{'arm64': 'y'}> +CONFIG_FUTEX_PI policy<{'arm64': 'y'}> +CONFIG_FUTEX_PRIVATE_HASH policy<{'arm64': 'y'}> +CONFIG_FWCTL policy<{'arm64': 'n'}> +CONFIG_FWNODE_MDIO policy<{'arm64': 'y'}> +CONFIG_FW_CACHE policy<{'arm64': 'y'}> +CONFIG_FW_CFG_SYSFS policy<{'arm64': 'm'}> +CONFIG_FW_CFG_SYSFS_CMDLINE policy<{'arm64': 'n'}> +CONFIG_FW_CS_DSP policy<{'arm64': 'm'}> +CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT policy<{'arm64': 'n'}> +CONFIG_FW_LOADER policy<{'arm64': 'y'}> +CONFIG_FW_LOADER_COMPRESS policy<{'arm64': 'y'}> +CONFIG_FW_LOADER_COMPRESS_XZ policy<{'arm64': 'y'}> +CONFIG_FW_LOADER_COMPRESS_ZSTD policy<{'arm64': 'y'}> +CONFIG_FW_LOADER_DEBUG policy<{'arm64': 'y'}> +CONFIG_FW_LOADER_PAGED_BUF policy<{'arm64': 'y'}> +CONFIG_FW_LOADER_SYSFS policy<{'arm64': 'y'}> +CONFIG_FW_LOADER_USER_HELPER policy<{'arm64': 'y'}> +CONFIG_FW_LOADER_USER_HELPER_FALLBACK policy<{'arm64': 'n'}> +CONFIG_FW_UPLOAD policy<{'arm64': 'y'}> +CONFIG_FXAS21002C policy<{'arm64': 'm'}> +CONFIG_FXAS21002C_I2C policy<{'arm64': 'm'}> +CONFIG_FXAS21002C_SPI policy<{'arm64': 'm'}> +CONFIG_FXLS8962AF policy<{'arm64': 'm'}> +CONFIG_FXLS8962AF_I2C policy<{'arm64': 'm'}> +CONFIG_FXLS8962AF_SPI policy<{'arm64': 'm'}> +CONFIG_FXOS8700 policy<{'arm64': 'm'}> +CONFIG_FXOS8700_I2C policy<{'arm64': 'm'}> +CONFIG_FXOS8700_SPI policy<{'arm64': 'm'}> +CONFIG_GACT_PROB policy<{'arm64': 'y'}> +CONFIG_GADGET_UAC1 policy<{'arm64': 'y'}> +CONFIG_GADGET_UAC1_LEGACY policy<{'arm64': 'n'}> +CONFIG_GAMEPORT policy<{'arm64': 'm'}> +CONFIG_GAMEPORT_EMU10K1 policy<{'arm64': 'm'}> +CONFIG_GAMEPORT_FM801 policy<{'arm64': 'm'}> +CONFIG_GARP policy<{'arm64': 'm'}> +CONFIG_GCC10_NO_ARRAY_BOUNDS policy<{'arm64': 'y'}> +CONFIG_GCC_NO_STRINGOP_OVERFLOW policy<{'arm64': 'y'}> +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS policy<{'arm64': 'y'}> +CONFIG_GCC_VERSION policy<{'arm64': '150200'}> +CONFIG_GCOV_KERNEL policy<{'arm64': 'n'}> +CONFIG_GEHC_PMC_ADC policy<{'arm64': 'm'}> +CONFIG_GEMINI_ETHERNET policy<{'arm64': 'm'}> +CONFIG_GENERIC_ADC_BATTERY policy<{'arm64': 'm'}> +CONFIG_GENERIC_ADC_THERMAL policy<{'arm64': 'm'}> +CONFIG_GENERIC_ALLOCATOR policy<{'arm64': 'y'}> +CONFIG_GENERIC_ARCH_NUMA policy<{'arm64': 'y'}> +CONFIG_GENERIC_ARCH_TOPOLOGY policy<{'arm64': 'y'}> +CONFIG_GENERIC_BUG policy<{'arm64': 'y'}> +CONFIG_GENERIC_BUG_RELATIVE_POINTERS policy<{'arm64': 'y'}> +CONFIG_GENERIC_CALIBRATE_DELAY policy<{'arm64': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS policy<{'arm64': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST policy<{'arm64': 'y'}> +CONFIG_GENERIC_CPU_AUTOPROBE policy<{'arm64': 'y'}> +CONFIG_GENERIC_CPU_CACHE_MAINTENANCE policy<{'arm64': 'y'}> +CONFIG_GENERIC_CPU_DEVICES policy<{'arm64': 'y'}> +CONFIG_GENERIC_CPU_VULNERABILITIES policy<{'arm64': 'y'}> +CONFIG_GENERIC_CSUM policy<{'arm64': 'y'}> +CONFIG_GENERIC_EARLY_IOREMAP policy<{'arm64': 'y'}> +CONFIG_GENERIC_FRAMER policy<{'arm64': 'y'}> +CONFIG_GENERIC_GETTIMEOFDAY policy<{'arm64': 'y'}> +CONFIG_GENERIC_HWEIGHT policy<{'arm64': 'y'}> +CONFIG_GENERIC_IDLE_POLL_SETUP policy<{'arm64': 'y'}> +CONFIG_GENERIC_IOREMAP policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_CHIP policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_ENTRY policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_IPI policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_IPI_MUX policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_MIGRATION policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_PROBE policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_SHOW policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_SHOW_LEVEL policy<{'arm64': 'y'}> +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED policy<{'arm64': 'y'}> +CONFIG_GENERIC_MSI_IRQ policy<{'arm64': 'y'}> +CONFIG_GENERIC_NET_UTILS policy<{'arm64': 'y'}> +CONFIG_GENERIC_PCI_IOMAP policy<{'arm64': 'y'}> +CONFIG_GENERIC_PHY policy<{'arm64': 'y'}> +CONFIG_GENERIC_PHY_MIPI_DPHY policy<{'arm64': 'y'}> +CONFIG_GENERIC_PINCONF policy<{'arm64': 'y'}> +CONFIG_GENERIC_PINCTRL_GROUPS policy<{'arm64': 'y'}> +CONFIG_GENERIC_PINMUX_FUNCTIONS policy<{'arm64': 'y'}> +CONFIG_GENERIC_SCHED_CLOCK policy<{'arm64': 'y'}> +CONFIG_GENERIC_SMP_IDLE_THREAD policy<{'arm64': 'y'}> +CONFIG_GENERIC_STRNCPY_FROM_USER policy<{'arm64': 'y'}> +CONFIG_GENERIC_STRNLEN_USER policy<{'arm64': 'y'}> +CONFIG_GENERIC_TRACER policy<{'arm64': 'y'}> +CONFIG_GENEVE policy<{'arm64': 'm'}> +CONFIG_GENKSYMS policy<{'arm64': 'y'}> +CONFIG_GENWQE policy<{'arm64': 'm'}> +CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY policy<{'arm64': '0'}> +CONFIG_GET_FREE_REGION policy<{'arm64': 'y'}> +CONFIG_GFS2_FS policy<{'arm64': 'm'}> +CONFIG_GFS2_FS_LOCKING_DLM policy<{'arm64': 'y'}> +CONFIG_GIANFAR policy<{'arm64': 'm'}> +CONFIG_GLOB policy<{'arm64': 'y'}> +CONFIG_GNSS policy<{'arm64': 'm'}> +CONFIG_GNSS_MTK_SERIAL policy<{'arm64': 'm'}> +CONFIG_GNSS_SERIAL policy<{'arm64': 'm'}> +CONFIG_GNSS_SIRF_SERIAL policy<{'arm64': 'm'}> +CONFIG_GNSS_UBX_SERIAL policy<{'arm64': 'm'}> +CONFIG_GNSS_USB policy<{'arm64': 'm'}> +CONFIG_GOLDFISH policy<{'arm64': 'n'}> +CONFIG_GOOGLE_FIRMWARE policy<{'arm64': 'n'}> +CONFIG_GP2AP002 policy<{'arm64': 'm'}> +CONFIG_GP2AP020A00F policy<{'arm64': 'm'}> +CONFIG_GPIB policy<{'arm64': 'n'}> +CONFIG_GPIOLIB policy<{'arm64': 'y'}> +CONFIG_GPIOLIB_FASTPATH_LIMIT policy<{'arm64': '512'}> +CONFIG_GPIOLIB_IRQCHIP policy<{'arm64': 'y'}> +CONFIG_GPIOLIB_LEGACY policy<{'arm64': 'y'}> +CONFIG_GPIO_74X164 policy<{'arm64': 'm'}> +CONFIG_GPIO_74XX_MMIO policy<{'arm64': 'm'}> +CONFIG_GPIO_ACPI policy<{'arm64': 'y'}> +CONFIG_GPIO_ADNP policy<{'arm64': 'm'}> +CONFIG_GPIO_ADP5520 policy<{'arm64': 'm'}> +CONFIG_GPIO_AGGREGATOR policy<{'arm64': 'm'}> +CONFIG_GPIO_ALTERA policy<{'arm64': 'm'}> +CONFIG_GPIO_ALTERA_A10SR policy<{'arm64': 'm'}> +CONFIG_GPIO_AMDPT policy<{'arm64': 'm'}> +CONFIG_GPIO_AMD_FCH policy<{'arm64': 'm'}> +CONFIG_GPIO_ARIZONA policy<{'arm64': 'm'}> +CONFIG_GPIO_BD71815 policy<{'arm64': 'm'}> +CONFIG_GPIO_BD71828 policy<{'arm64': 'm'}> +CONFIG_GPIO_BD72720 policy<{'arm64': 'n'}> +CONFIG_GPIO_BD9571MWV policy<{'arm64': 'm'}> +CONFIG_GPIO_BY_PINCTRL policy<{'arm64': 'n'}> +CONFIG_GPIO_CADENCE policy<{'arm64': 'm'}> +CONFIG_GPIO_CDEV policy<{'arm64': 'y'}> +CONFIG_GPIO_CROS_EC policy<{'arm64': 'm'}> +CONFIG_GPIO_DA9052 policy<{'arm64': 'm'}> +CONFIG_GPIO_DA9055 policy<{'arm64': 'm'}> +CONFIG_GPIO_DAVINCI policy<{'arm64': 'y'}> +CONFIG_GPIO_DLN2 policy<{'arm64': 'm'}> +CONFIG_GPIO_DS4520 policy<{'arm64': 'm'}> +CONFIG_GPIO_DWAPB policy<{'arm64': 'm'}> +CONFIG_GPIO_EIC_SPRD policy<{'arm64': 'm'}> +CONFIG_GPIO_EN7523 policy<{'arm64': 'm'}> +CONFIG_GPIO_EXAR policy<{'arm64': 'm'}> +CONFIG_GPIO_FTGPIO010 policy<{'arm64': 'y'}> +CONFIG_GPIO_FXL6408 policy<{'arm64': 'm'}> +CONFIG_GPIO_GENERIC policy<{'arm64': 'y'}> +CONFIG_GPIO_GENERIC_PLATFORM policy<{'arm64': 'y'}> +CONFIG_GPIO_GRGPIO policy<{'arm64': 'm'}> +CONFIG_GPIO_GW_PLD policy<{'arm64': 'm'}> +CONFIG_GPIO_HISI policy<{'arm64': 'm'}> +CONFIG_GPIO_HLWD policy<{'arm64': 'm'}> +CONFIG_GPIO_IDIO_16 policy<{'arm64': 'm'}> +CONFIG_GPIO_IMX_SCU policy<{'arm64': 'y'}> +CONFIG_GPIO_JANZ_TTL policy<{'arm64': 'm'}> +CONFIG_GPIO_KEMPLD policy<{'arm64': 'm'}> +CONFIG_GPIO_LATCH policy<{'arm64': 'm'}> +CONFIG_GPIO_LINE_MUX policy<{'arm64': 'n'}> +CONFIG_GPIO_LJCA policy<{'arm64': 'm'}> +CONFIG_GPIO_LOGICVC policy<{'arm64': 'm'}> +CONFIG_GPIO_LP3943 policy<{'arm64': 'm'}> +CONFIG_GPIO_LP873X policy<{'arm64': 'm'}> +CONFIG_GPIO_LP87565 policy<{'arm64': 'm'}> +CONFIG_GPIO_MADERA policy<{'arm64': 'm'}> +CONFIG_GPIO_MAX3191X policy<{'arm64': 'm'}> +CONFIG_GPIO_MAX7300 policy<{'arm64': 'm'}> +CONFIG_GPIO_MAX7301 policy<{'arm64': 'm'}> +CONFIG_GPIO_MAX730X policy<{'arm64': 'm'}> +CONFIG_GPIO_MAX732X policy<{'arm64': 'm'}> +CONFIG_GPIO_MAX77620 policy<{'arm64': 'm'}> +CONFIG_GPIO_MAX77650 policy<{'arm64': 'm'}> +CONFIG_GPIO_MB86S7X policy<{'arm64': 'm'}> +CONFIG_GPIO_MC33880 policy<{'arm64': 'm'}> +CONFIG_GPIO_MENZ127 policy<{'arm64': 'm'}> +CONFIG_GPIO_MLXBF policy<{'arm64': 'm'}> +CONFIG_GPIO_MLXBF2 policy<{'arm64': 'm'}> +CONFIG_GPIO_MLXBF3 policy<{'arm64': 'm'}> +CONFIG_GPIO_MOCKUP policy<{'arm64': 'n'}> +CONFIG_GPIO_MOXTET policy<{'arm64': 'm'}> +CONFIG_GPIO_MPC8XXX policy<{'arm64': 'y'}> +CONFIG_GPIO_MPSSE policy<{'arm64': 'n'}> +CONFIG_GPIO_MVEBU policy<{'arm64': 'y'}> +CONFIG_GPIO_MXC policy<{'arm64': 'y'}> +CONFIG_GPIO_NPCM_SGPIO policy<{'arm64': 'y'}> +CONFIG_GPIO_PALMAS policy<{'arm64': 'y'}> +CONFIG_GPIO_PCA953X policy<{'arm64': 'm'}> +CONFIG_GPIO_PCA953X_IRQ policy<{'arm64': 'y'}> +CONFIG_GPIO_PCA9570 policy<{'arm64': 'm'}> +CONFIG_GPIO_PCF857X policy<{'arm64': 'm'}> +CONFIG_GPIO_PCIE_IDIO_24 policy<{'arm64': 'm'}> +CONFIG_GPIO_PCI_IDIO_16 policy<{'arm64': 'm'}> +CONFIG_GPIO_PISOSR policy<{'arm64': 'm'}> +CONFIG_GPIO_PL061 policy<{'arm64': 'y'}> +CONFIG_GPIO_PMIC_EIC_SPRD policy<{'arm64': 'm'}> +CONFIG_GPIO_POLARFIRE_SOC policy<{'arm64': 'n'}> +CONFIG_GPIO_QIXIS_FPGA policy<{'arm64': 'n'}> +CONFIG_GPIO_RC5T583 policy<{'arm64': 'y'}> +CONFIG_GPIO_RCAR policy<{'arm64': 'm'}> +CONFIG_GPIO_RDC321X policy<{'arm64': 'm'}> +CONFIG_GPIO_REGMAP policy<{'arm64': 'm'}> +CONFIG_GPIO_ROCKCHIP policy<{'arm64': 'm'}> +CONFIG_GPIO_RTD policy<{'arm64': 'm'}> +CONFIG_GPIO_SHARED policy<{'arm64': 'y'}> +CONFIG_GPIO_SHARED_PROXY policy<{'arm64': 'm'}> +CONFIG_GPIO_SIFIVE policy<{'arm64': 'y'}> +CONFIG_GPIO_SIM policy<{'arm64': 'm'}> +CONFIG_GPIO_SIOX policy<{'arm64': 'm'}> +CONFIG_GPIO_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER policy<{'arm64': 'm'}> +CONFIG_GPIO_SPRD policy<{'arm64': 'm'}> +CONFIG_GPIO_STMPE policy<{'arm64': 'y'}> +CONFIG_GPIO_SWNODE_UNDEFINED policy<{'arm64': 'y'}> +CONFIG_GPIO_SYSCON policy<{'arm64': 'm'}> +CONFIG_GPIO_SYSFS policy<{'arm64': 'y'}> +CONFIG_GPIO_SYSFS_LEGACY policy<{'arm64': 'y'}> +CONFIG_GPIO_TC3589X policy<{'arm64': 'y'}> +CONFIG_GPIO_TEGRA policy<{'arm64': 'y'}> +CONFIG_GPIO_TEGRA186 policy<{'arm64': 'y'}> +CONFIG_GPIO_THUNDERX policy<{'arm64': 'm'}> +CONFIG_GPIO_TPIC2810 policy<{'arm64': 'm'}> +CONFIG_GPIO_TPS65086 policy<{'arm64': 'm'}> +CONFIG_GPIO_TPS65218 policy<{'arm64': 'm'}> +CONFIG_GPIO_TPS65219 policy<{'arm64': 'm'}> +CONFIG_GPIO_TPS6586X policy<{'arm64': 'y'}> +CONFIG_GPIO_TPS65910 policy<{'arm64': 'y'}> +CONFIG_GPIO_TPS65912 policy<{'arm64': 'm'}> +CONFIG_GPIO_TQMX86 policy<{'arm64': 'm'}> +CONFIG_GPIO_TWL4030 policy<{'arm64': 'm'}> +CONFIG_GPIO_TWL6040 policy<{'arm64': 'm'}> +CONFIG_GPIO_VF610 policy<{'arm64': 'y'}> +CONFIG_GPIO_VIPERBOARD policy<{'arm64': 'm'}> +CONFIG_GPIO_VIRTIO policy<{'arm64': 'm'}> +CONFIG_GPIO_VIRTUSER policy<{'arm64': 'm'}> +CONFIG_GPIO_VISCONTI policy<{'arm64': 'm'}> +CONFIG_GPIO_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_GPIO_WAVESHARE_DSI_TOUCH policy<{'arm64': 'n'}> +CONFIG_GPIO_WCD934X policy<{'arm64': 'm'}> +CONFIG_GPIO_WM831X policy<{'arm64': 'm'}> +CONFIG_GPIO_WM8350 policy<{'arm64': 'm'}> +CONFIG_GPIO_WM8994 policy<{'arm64': 'm'}> +CONFIG_GPIO_XGENE policy<{'arm64': 'y'}> +CONFIG_GPIO_XGENE_SB policy<{'arm64': 'm'}> +CONFIG_GPIO_XILINX policy<{'arm64': 'y'}> +CONFIG_GPIO_XLP policy<{'arm64': 'm'}> +CONFIG_GPIO_XRA1403 policy<{'arm64': 'm'}> +CONFIG_GPIO_ZYNQ policy<{'arm64': 'm'}> +CONFIG_GPIO_ZYNQMP_MODEPIN policy<{'arm64': 'm'}> +CONFIG_GPU_BUDDY policy<{'arm64': 'y'}> +CONFIG_GP_PCI1XXXX policy<{'arm64': 'm'}> +CONFIG_GRACE_PERIOD policy<{'arm64': 'm'}> +CONFIG_GREENASIA_FF policy<{'arm64': 'y'}> +CONFIG_GREYBUS policy<{'arm64': 'm'}> +CONFIG_GREYBUS_AUDIO policy<{'arm64': 'm'}> +CONFIG_GREYBUS_AUDIO_APB_CODEC policy<{'arm64': 'm'}> +CONFIG_GREYBUS_BEAGLEPLAY policy<{'arm64': 'm'}> +CONFIG_GREYBUS_BOOTROM policy<{'arm64': 'm'}> +CONFIG_GREYBUS_BRIDGED_PHY policy<{'arm64': 'm'}> +CONFIG_GREYBUS_ES2 policy<{'arm64': 'm'}> +CONFIG_GREYBUS_FIRMWARE policy<{'arm64': 'm'}> +CONFIG_GREYBUS_GPIO policy<{'arm64': 'm'}> +CONFIG_GREYBUS_HID policy<{'arm64': 'm'}> +CONFIG_GREYBUS_I2C policy<{'arm64': 'm'}> +CONFIG_GREYBUS_LIGHT policy<{'arm64': 'm'}> +CONFIG_GREYBUS_LOG policy<{'arm64': 'm'}> +CONFIG_GREYBUS_LOOPBACK policy<{'arm64': 'm'}> +CONFIG_GREYBUS_POWER policy<{'arm64': 'm'}> +CONFIG_GREYBUS_PWM policy<{'arm64': 'm'}> +CONFIG_GREYBUS_RAW policy<{'arm64': 'm'}> +CONFIG_GREYBUS_SDIO policy<{'arm64': 'm'}> +CONFIG_GREYBUS_SPI policy<{'arm64': 'm'}> +CONFIG_GREYBUS_UART policy<{'arm64': 'm'}> +CONFIG_GREYBUS_USB policy<{'arm64': 'm'}> +CONFIG_GREYBUS_VIBRATOR policy<{'arm64': 'm'}> +CONFIG_GROUP_SCHED_BANDWIDTH policy<{'arm64': 'y'}> +CONFIG_GROUP_SCHED_WEIGHT policy<{'arm64': 'y'}> +CONFIG_GRO_CELLS policy<{'arm64': 'y'}> +CONFIG_GTP policy<{'arm64': 'm'}> +CONFIG_GUEST_PERF_EVENTS policy<{'arm64': 'y'}> +CONFIG_GUNYAH_WATCHDOG policy<{'arm64': 'n'}> +CONFIG_GUP_TEST policy<{'arm64': 'n'}> +CONFIG_GVE policy<{'arm64': 'm'}> +CONFIG_HAPPYMEAL policy<{'arm64': 'm'}> +CONFIG_HARDENED_USERCOPY policy<{'arm64': 'y'}> +CONFIG_HARDENED_USERCOPY_DEFAULT_ON policy<{'arm64': 'y'}> +CONFIG_HARDIRQS_SW_RESEND policy<{'arm64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR policy<{'arm64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR_ARCH policy<{'arm64': 'n'}> +CONFIG_HARDLOCKUP_DETECTOR_BUDDY policy<{'arm64': 'n'}> +CONFIG_HARDLOCKUP_DETECTOR_COUNTS_HRTIMER policy<{'arm64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR_PERF policy<{'arm64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR_PREFER_BUDDY policy<{'arm64': 'n'}> +CONFIG_HAS_DMA policy<{'arm64': 'y'}> +CONFIG_HAS_IOMEM policy<{'arm64': 'y'}> +CONFIG_HAS_IOPORT policy<{'arm64': 'y'}> +CONFIG_HAS_IOPORT_MAP policy<{'arm64': 'y'}> +CONFIG_HAS_SECURITY_AUDIT policy<{'arm64': 'y'}> +CONFIG_HAVE_ACPI_APEI policy<{'arm64': 'y'}> +CONFIG_HAVE_ALIGNED_STRUCT_PAGE policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_AUDITSYSCALL policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_BITREVERSE policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_COMPILER_H policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_GET_SECUREBOOT policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_HUGE_VMALLOC policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_HUGE_VMAP policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_JUMP_LABEL policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KASAN policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KASAN_HW_TAGS policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KASAN_SW_TAGS policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KASAN_VMALLOC policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KCSAN policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KFENCE policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KGDB policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KSTACK_ERASE policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_MMAP_RND_BITS policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_SECCOMP policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_SECCOMP_FILTER policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_TRACEHOOK policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_USERFAULTFD_MINOR policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_USERFAULTFD_WP policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_VMAP_STACK policy<{'arm64': 'y'}> +CONFIG_HAVE_ARM_SMCCC policy<{'arm64': 'y'}> +CONFIG_HAVE_ARM_SMCCC_DISCOVERY policy<{'arm64': 'y'}> +CONFIG_HAVE_ASM_MODVERSIONS policy<{'arm64': 'y'}> +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT policy<{'arm64': 'y'}> +CONFIG_HAVE_CLK policy<{'arm64': 'y'}> +CONFIG_HAVE_CLK_PREPARE policy<{'arm64': 'y'}> +CONFIG_HAVE_CMPXCHG_DOUBLE policy<{'arm64': 'y'}> +CONFIG_HAVE_CMPXCHG_LOCAL policy<{'arm64': 'y'}> +CONFIG_HAVE_CONTEXT_TRACKING_USER policy<{'arm64': 'y'}> +CONFIG_HAVE_C_RECORDMCOUNT policy<{'arm64': 'y'}> +CONFIG_HAVE_DEBUG_KMEMLEAK policy<{'arm64': 'y'}> +CONFIG_HAVE_DMA_CONTIGUOUS policy<{'arm64': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE policy<{'arm64': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS policy<{'arm64': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS policy<{'arm64': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS policy<{'arm64': 'y'}> +CONFIG_HAVE_EBPF_JIT policy<{'arm64': 'y'}> +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS policy<{'arm64': 'y'}> +CONFIG_HAVE_EXTRA_IPI_TRACEPOINTS policy<{'arm64': 'y'}> +CONFIG_HAVE_FTRACE_GRAPH_FUNC policy<{'arm64': 'y'}> +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API policy<{'arm64': 'y'}> +CONFIG_HAVE_FUNCTION_ERROR_INJECTION policy<{'arm64': 'y'}> +CONFIG_HAVE_FUNCTION_GRAPH_FREGS policy<{'arm64': 'y'}> +CONFIG_HAVE_FUNCTION_GRAPH_TRACER policy<{'arm64': 'y'}> +CONFIG_HAVE_FUNCTION_TRACER policy<{'arm64': 'y'}> +CONFIG_HAVE_GCC_PLUGINS policy<{'arm64': 'y'}> +CONFIG_HAVE_GENERIC_VDSO policy<{'arm64': 'y'}> +CONFIG_HAVE_GIGANTIC_FOLIOS policy<{'arm64': 'y'}> +CONFIG_HAVE_GUP_FAST policy<{'arm64': 'y'}> +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY policy<{'arm64': 'y'}> +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF policy<{'arm64': 'y'}> +CONFIG_HAVE_HW_BREAKPOINT policy<{'arm64': 'y'}> +CONFIG_HAVE_IMA_KEXEC policy<{'arm64': 'y'}> +CONFIG_HAVE_IOREMAP_PROT policy<{'arm64': 'y'}> +CONFIG_HAVE_IRQ_TIME_ACCOUNTING policy<{'arm64': 'y'}> +CONFIG_HAVE_KCSAN_COMPILER policy<{'arm64': 'y'}> +CONFIG_HAVE_KERNEL_GZIP policy<{'arm64': 'y'}> +CONFIG_HAVE_KERNEL_ZSTD policy<{'arm64': 'y'}> +CONFIG_HAVE_KPROBES policy<{'arm64': 'y'}> +CONFIG_HAVE_KRETPROBES policy<{'arm64': 'y'}> +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT policy<{'arm64': 'y'}> +CONFIG_HAVE_KVM_DIRTY_RING policy<{'arm64': 'y'}> +CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL policy<{'arm64': 'y'}> +CONFIG_HAVE_KVM_IRQCHIP policy<{'arm64': 'y'}> +CONFIG_HAVE_KVM_IRQ_BYPASS policy<{'arm64': 'y'}> +CONFIG_HAVE_KVM_IRQ_ROUTING policy<{'arm64': 'y'}> +CONFIG_HAVE_KVM_MSI policy<{'arm64': 'y'}> +CONFIG_HAVE_KVM_READONLY_MEM policy<{'arm64': 'y'}> +CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE policy<{'arm64': 'y'}> +CONFIG_HAVE_LIVEPATCH policy<{'arm64': 'y'}> +CONFIG_HAVE_MOD_ARCH_SPECIFIC policy<{'arm64': 'y'}> +CONFIG_HAVE_MOVE_PMD policy<{'arm64': 'y'}> +CONFIG_HAVE_MOVE_PUD policy<{'arm64': 'y'}> +CONFIG_HAVE_NMI policy<{'arm64': 'y'}> +CONFIG_HAVE_PAGE_SIZE_4KB policy<{'arm64': 'y'}> +CONFIG_HAVE_PCI policy<{'arm64': 'y'}> +CONFIG_HAVE_PERF_EVENTS policy<{'arm64': 'y'}> +CONFIG_HAVE_PERF_EVENTS_NMI policy<{'arm64': 'y'}> +CONFIG_HAVE_PERF_REGS policy<{'arm64': 'y'}> +CONFIG_HAVE_PERF_USER_STACK_DUMP policy<{'arm64': 'y'}> +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK policy<{'arm64': 'y'}> +CONFIG_HAVE_PREEMPT_DYNAMIC policy<{'arm64': 'y'}> +CONFIG_HAVE_PREEMPT_DYNAMIC_KEY policy<{'arm64': 'y'}> +CONFIG_HAVE_PV_STEAL_CLOCK_GEN policy<{'arm64': 'y'}> +CONFIG_HAVE_PWRCTRL policy<{'arm64': 'y'}> +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API policy<{'arm64': 'y'}> +CONFIG_HAVE_RELIABLE_STACKTRACE policy<{'arm64': 'y'}> +CONFIG_HAVE_RSEQ policy<{'arm64': 'y'}> +CONFIG_HAVE_RUST policy<{'arm64': 'y'}> +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT policy<{'arm64': 'y'}> +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI policy<{'arm64': 'y'}> +CONFIG_HAVE_SETUP_PER_CPU_AREA policy<{'arm64': 'y'}> +CONFIG_HAVE_SHARED_GPIOS policy<{'arm64': 'y'}> +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK policy<{'arm64': 'y'}> +CONFIG_HAVE_STACKPROTECTOR policy<{'arm64': 'y'}> +CONFIG_HAVE_SYSCALL_TRACEPOINTS policy<{'arm64': 'y'}> +CONFIG_HAVE_TRUSTED_KEYS policy<{'arm64': 'y'}> +CONFIG_HAVE_TRUSTED_KEYS_DEBUG policy<{'arm64': 'y'}> +CONFIG_HAVE_UID16 policy<{'arm64': 'y'}> +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN policy<{'arm64': 'y'}> +CONFIG_HBMC_AM654 policy<{'arm64': 'm'}> +CONFIG_HD44780 policy<{'arm64': 'm'}> +CONFIG_HD44780_COMMON policy<{'arm64': 'm'}> +CONFIG_HDC100X policy<{'arm64': 'm'}> +CONFIG_HDC2010 policy<{'arm64': 'm'}> +CONFIG_HDC3020 policy<{'arm64': 'm'}> +CONFIG_HDLC policy<{'arm64': 'm'}> +CONFIG_HDLC_CISCO policy<{'arm64': 'm'}> +CONFIG_HDLC_FR policy<{'arm64': 'm'}> +CONFIG_HDLC_PPP policy<{'arm64': 'm'}> +CONFIG_HDLC_RAW policy<{'arm64': 'm'}> +CONFIG_HDLC_RAW_ETH policy<{'arm64': 'm'}> +CONFIG_HDLC_X25 policy<{'arm64': 'm'}> +CONFIG_HDMI policy<{'arm64': 'y'}> +CONFIG_HEADERS_INSTALL policy<{'arm64': 'n'}> +CONFIG_HFSPLUS_FS policy<{'arm64': 'm'}> +CONFIG_HFS_FS policy<{'arm64': 'm'}> +CONFIG_HI13X1_GMAC policy<{'arm64': 'y'}> +CONFIG_HI3660_MBOX policy<{'arm64': 'm'}> +CONFIG_HI6220_MBOX policy<{'arm64': 'm'}> +CONFIG_HI6421V600_IRQ policy<{'arm64': 'm'}> +CONFIG_HI8435 policy<{'arm64': 'm'}> +CONFIG_HIBERNATION policy<{'arm64': 'n'}> +CONFIG_HIBMCGE policy<{'arm64': 'n'}> +CONFIG_HID policy<{'arm64': 'm'}> +CONFIG_HIDRAW policy<{'arm64': 'y'}> +CONFIG_HID_A4TECH policy<{'arm64': 'm'}> +CONFIG_HID_ACCUTOUCH policy<{'arm64': 'm'}> +CONFIG_HID_ACRUX policy<{'arm64': 'm'}> +CONFIG_HID_ACRUX_FF policy<{'arm64': 'y'}> +CONFIG_HID_ALPS policy<{'arm64': 'm'}> +CONFIG_HID_APPLE policy<{'arm64': 'm'}> +CONFIG_HID_APPLEIR policy<{'arm64': 'm'}> +CONFIG_HID_ASUS policy<{'arm64': 'm'}> +CONFIG_HID_AUREAL policy<{'arm64': 'm'}> +CONFIG_HID_BATTERY_STRENGTH policy<{'arm64': 'y'}> +CONFIG_HID_BELKIN policy<{'arm64': 'm'}> +CONFIG_HID_BETOP_FF policy<{'arm64': 'm'}> +CONFIG_HID_BIGBEN_FF policy<{'arm64': 'm'}> +CONFIG_HID_BPF policy<{'arm64': 'y'}> +CONFIG_HID_CHERRY policy<{'arm64': 'm'}> +CONFIG_HID_CHICONY policy<{'arm64': 'm'}> +CONFIG_HID_CMEDIA policy<{'arm64': 'm'}> +CONFIG_HID_CORSAIR policy<{'arm64': 'm'}> +CONFIG_HID_COUGAR policy<{'arm64': 'm'}> +CONFIG_HID_CP2112 policy<{'arm64': 'm'}> +CONFIG_HID_CREATIVE_SB0540 policy<{'arm64': 'm'}> +CONFIG_HID_CYPRESS policy<{'arm64': 'm'}> +CONFIG_HID_DRAGONRISE policy<{'arm64': 'm'}> +CONFIG_HID_ELAN policy<{'arm64': 'm'}> +CONFIG_HID_ELECOM policy<{'arm64': 'm'}> +CONFIG_HID_ELO policy<{'arm64': 'm'}> +CONFIG_HID_EMS_FF policy<{'arm64': 'm'}> +CONFIG_HID_EVISION policy<{'arm64': 'm'}> +CONFIG_HID_EZKEY policy<{'arm64': 'm'}> +CONFIG_HID_FT260 policy<{'arm64': 'm'}> +CONFIG_HID_GEMBIRD policy<{'arm64': 'm'}> +CONFIG_HID_GENERIC policy<{'arm64': 'm'}> +CONFIG_HID_GFRM policy<{'arm64': 'm'}> +CONFIG_HID_GLORIOUS policy<{'arm64': 'm'}> +CONFIG_HID_GOODIX_SPI policy<{'arm64': 'n'}> +CONFIG_HID_GOOGLE_HAMMER policy<{'arm64': 'm'}> +CONFIG_HID_GOOGLE_STADIA_FF policy<{'arm64': 'm'}> +CONFIG_HID_GREENASIA policy<{'arm64': 'm'}> +CONFIG_HID_GT683R policy<{'arm64': 'm'}> +CONFIG_HID_GYRATION policy<{'arm64': 'm'}> +CONFIG_HID_HAPTIC policy<{'arm64': 'n'}> +CONFIG_HID_HOLTEK policy<{'arm64': 'm'}> +CONFIG_HID_HUAWEI policy<{'arm64': 'n'}> +CONFIG_HID_ICADE policy<{'arm64': 'm'}> +CONFIG_HID_ITE policy<{'arm64': 'm'}> +CONFIG_HID_JABRA policy<{'arm64': 'm'}> +CONFIG_HID_KENSINGTON policy<{'arm64': 'm'}> +CONFIG_HID_KEYTOUCH policy<{'arm64': 'm'}> +CONFIG_HID_KYE policy<{'arm64': 'm'}> +CONFIG_HID_KYSONA policy<{'arm64': 'm'}> +CONFIG_HID_LCPOWER policy<{'arm64': 'm'}> +CONFIG_HID_LED policy<{'arm64': 'm'}> +CONFIG_HID_LENOVO policy<{'arm64': 'm'}> +CONFIG_HID_LENOVO_GO policy<{'arm64': 'n'}> +CONFIG_HID_LENOVO_GO_S policy<{'arm64': 'n'}> +CONFIG_HID_LETSKETCH policy<{'arm64': 'm'}> +CONFIG_HID_LOGITECH policy<{'arm64': 'm'}> +CONFIG_HID_LOGITECH_DJ policy<{'arm64': 'm'}> +CONFIG_HID_LOGITECH_HIDPP policy<{'arm64': 'm'}> +CONFIG_HID_MACALLY policy<{'arm64': 'm'}> +CONFIG_HID_MAGICMOUSE policy<{'arm64': 'm'}> +CONFIG_HID_MALTRON policy<{'arm64': 'm'}> +CONFIG_HID_MAYFLASH policy<{'arm64': 'm'}> +CONFIG_HID_MCP2200 policy<{'arm64': 'm'}> +CONFIG_HID_MCP2221 policy<{'arm64': 'm'}> +CONFIG_HID_MEGAWORLD_FF policy<{'arm64': 'm'}> +CONFIG_HID_MICROSOFT policy<{'arm64': 'm'}> +CONFIG_HID_MONTEREY policy<{'arm64': 'm'}> +CONFIG_HID_MULTITOUCH policy<{'arm64': 'm'}> +CONFIG_HID_NINTENDO policy<{'arm64': 'm'}> +CONFIG_HID_NTI policy<{'arm64': 'm'}> +CONFIG_HID_NTRIG policy<{'arm64': 'm'}> +CONFIG_HID_NVIDIA_SHIELD policy<{'arm64': 'm'}> +CONFIG_HID_ORTEK policy<{'arm64': 'm'}> +CONFIG_HID_OXP policy<{'arm64': 'n'}> +CONFIG_HID_PANTHERLORD policy<{'arm64': 'm'}> +CONFIG_HID_PENMOUNT policy<{'arm64': 'm'}> +CONFIG_HID_PETALYNX policy<{'arm64': 'm'}> +CONFIG_HID_PICOLCD policy<{'arm64': 'm'}> +CONFIG_HID_PICOLCD_BACKLIGHT policy<{'arm64': 'y'}> +CONFIG_HID_PICOLCD_CIR policy<{'arm64': 'y'}> +CONFIG_HID_PICOLCD_FB policy<{'arm64': 'y'}> +CONFIG_HID_PICOLCD_LCD policy<{'arm64': 'y'}> +CONFIG_HID_PICOLCD_LEDS policy<{'arm64': 'y'}> +CONFIG_HID_PID policy<{'arm64': 'y'}> +CONFIG_HID_PLANTRONICS policy<{'arm64': 'm'}> +CONFIG_HID_PLAYSTATION policy<{'arm64': 'm'}> +CONFIG_HID_PRIMAX policy<{'arm64': 'm'}> +CONFIG_HID_PRODIKEYS policy<{'arm64': 'm'}> +CONFIG_HID_PXRC policy<{'arm64': 'm'}> +CONFIG_HID_RAKK policy<{'arm64': 'n'}> +CONFIG_HID_RAPOO policy<{'arm64': 'n'}> +CONFIG_HID_RAZER policy<{'arm64': 'm'}> +CONFIG_HID_REDRAGON policy<{'arm64': 'm'}> +CONFIG_HID_RETRODE policy<{'arm64': 'm'}> +CONFIG_HID_RMI policy<{'arm64': 'm'}> +CONFIG_HID_ROCCAT policy<{'arm64': 'm'}> +CONFIG_HID_SAITEK policy<{'arm64': 'm'}> +CONFIG_HID_SAMSUNG policy<{'arm64': 'm'}> +CONFIG_HID_SEMITEK policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_ACCEL_3D policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_ALS policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_CUSTOM_SENSOR policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_DEVICE_ROTATION policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_GYRO_3D policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_HUB policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_HUMIDITY policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_IIO_COMMON policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_IIO_TRIGGER policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_INCLINOMETER_3D policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_MAGNETOMETER_3D policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_PRESS policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_PROX policy<{'arm64': 'm'}> +CONFIG_HID_SENSOR_TEMP policy<{'arm64': 'm'}> +CONFIG_HID_SIGMAMICRO policy<{'arm64': 'm'}> +CONFIG_HID_SMARTJOYPLUS policy<{'arm64': 'm'}> +CONFIG_HID_SONY policy<{'arm64': 'm'}> +CONFIG_HID_SPEEDLINK policy<{'arm64': 'm'}> +CONFIG_HID_STEAM policy<{'arm64': 'm'}> +CONFIG_HID_STEELSERIES policy<{'arm64': 'm'}> +CONFIG_HID_SUNPLUS policy<{'arm64': 'm'}> +CONFIG_HID_SUPPORT policy<{'arm64': 'y'}> +CONFIG_HID_THINGM policy<{'arm64': 'm'}> +CONFIG_HID_THRUSTMASTER policy<{'arm64': 'm'}> +CONFIG_HID_TIVO policy<{'arm64': 'm'}> +CONFIG_HID_TOPRE policy<{'arm64': 'm'}> +CONFIG_HID_TOPSEED policy<{'arm64': 'm'}> +CONFIG_HID_TWINHAN policy<{'arm64': 'm'}> +CONFIG_HID_U2FZERO policy<{'arm64': 'm'}> +CONFIG_HID_UCLOGIC policy<{'arm64': 'm'}> +CONFIG_HID_UDRAW_PS3 policy<{'arm64': 'm'}> +CONFIG_HID_UNIVERSAL_PIDFF policy<{'arm64': 'n'}> +CONFIG_HID_VIEWSONIC policy<{'arm64': 'm'}> +CONFIG_HID_VIVALDI policy<{'arm64': 'm'}> +CONFIG_HID_VIVALDI_COMMON policy<{'arm64': 'm'}> +CONFIG_HID_VRC2 policy<{'arm64': 'm'}> +CONFIG_HID_WACOM policy<{'arm64': 'm'}> +CONFIG_HID_WALTOP policy<{'arm64': 'm'}> +CONFIG_HID_WIIMOTE policy<{'arm64': 'm'}> +CONFIG_HID_WINWING policy<{'arm64': 'm'}> +CONFIG_HID_XIAOMI policy<{'arm64': 'm'}> +CONFIG_HID_XINMO policy<{'arm64': 'm'}> +CONFIG_HID_ZEROPLUS policy<{'arm64': 'm'}> +CONFIG_HID_ZYDACRON policy<{'arm64': 'm'}> +CONFIG_HIGH_RES_TIMERS policy<{'arm64': 'y'}> +CONFIG_HINIC policy<{'arm64': 'm'}> +CONFIG_HINIC3 policy<{'arm64': 'n'}> +CONFIG_HIP04_ETH policy<{'arm64': 'm'}> +CONFIG_HISILICON_ERRATUM_161010101 policy<{'arm64': 'y'}> +CONFIG_HISILICON_ERRATUM_161600802 policy<{'arm64': 'y'}> +CONFIG_HISILICON_ERRATUM_162100125 policy<{'arm64': 'y'}> +CONFIG_HISILICON_ERRATUM_162100801 policy<{'arm64': 'y'}> +CONFIG_HISILICON_IRQ_MBIGEN policy<{'arm64': 'y'}> +CONFIG_HISILICON_LPC policy<{'arm64': 'y'}> +CONFIG_HISI_ACC_VFIO_PCI policy<{'arm64': 'm'}> +CONFIG_HISI_DMA policy<{'arm64': 'n'}> +CONFIG_HISI_FEMAC policy<{'arm64': 'm'}> +CONFIG_HISI_HIKEY_USB policy<{'arm64': 'm'}> +CONFIG_HISI_PCIE_PMU policy<{'arm64': 'm'}> +CONFIG_HISI_PMU policy<{'arm64': 'm'}> +CONFIG_HISI_PTT policy<{'arm64': 'm'}> +CONFIG_HISI_THERMAL policy<{'arm64': 'm'}> +CONFIG_HIST_TRIGGERS policy<{'arm64': 'y'}> +CONFIG_HIST_TRIGGERS_DEBUG policy<{'arm64': 'n'}> +CONFIG_HIX5HD2_GMAC policy<{'arm64': 'm'}> +CONFIG_HMC425 policy<{'arm64': 'm'}> +CONFIG_HMC6352 policy<{'arm64': 'm'}> +CONFIG_HMEM_REPORTING policy<{'arm64': 'y'}> +CONFIG_HMM_MIRROR policy<{'arm64': 'y'}> +CONFIG_HNS policy<{'arm64': 'm'}> +CONFIG_HNS3 policy<{'arm64': 'm'}> +CONFIG_HNS3_DCB policy<{'arm64': 'y'}> +CONFIG_HNS3_ENET policy<{'arm64': 'm'}> +CONFIG_HNS3_HCLGE policy<{'arm64': 'm'}> +CONFIG_HNS3_HCLGEVF policy<{'arm64': 'm'}> +CONFIG_HNS3_PMU policy<{'arm64': 'm'}> +CONFIG_HNS_DSAF policy<{'arm64': 'm'}> +CONFIG_HNS_ENET policy<{'arm64': 'm'}> +CONFIG_HNS_MDIO policy<{'arm64': 'm'}> +CONFIG_HOLTEK_FF policy<{'arm64': 'y'}> +CONFIG_HOTPLUG_CORE_SYNC policy<{'arm64': 'y'}> +CONFIG_HOTPLUG_CORE_SYNC_DEAD policy<{'arm64': 'y'}> +CONFIG_HOTPLUG_CPU policy<{'arm64': 'y'}> +CONFIG_HOTPLUG_PCI policy<{'arm64': 'y'}> +CONFIG_HOTPLUG_PCI_ACPI policy<{'arm64': 'y'}> +CONFIG_HOTPLUG_PCI_ACPI_AMPERE_ALTRA policy<{'arm64': 'm'}> +CONFIG_HOTPLUG_PCI_ACPI_IBM policy<{'arm64': 'm'}> +CONFIG_HOTPLUG_PCI_CPCI policy<{'arm64': 'y'}> +CONFIG_HOTPLUG_PCI_OCTEONEP policy<{'arm64': 'n'}> +CONFIG_HOTPLUG_SMT policy<{'arm64': 'y'}> +CONFIG_HP03 policy<{'arm64': 'm'}> +CONFIG_HP206C policy<{'arm64': 'm'}> +CONFIG_HPFS_FS policy<{'arm64': 'm'}> +CONFIG_HP_ILO policy<{'arm64': 'm'}> +CONFIG_HP_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_HSA_AMD policy<{'arm64': 'y'}> +CONFIG_HSA_AMD_P2P policy<{'arm64': 'n'}> +CONFIG_HSA_AMD_SVM policy<{'arm64': 'y'}> +CONFIG_HSC030PA policy<{'arm64': 'm'}> +CONFIG_HSC030PA_I2C policy<{'arm64': 'm'}> +CONFIG_HSC030PA_SPI policy<{'arm64': 'm'}> +CONFIG_HSI policy<{'arm64': 'm'}> +CONFIG_HSI_BOARDINFO policy<{'arm64': 'y'}> +CONFIG_HSI_CHAR policy<{'arm64': 'm'}> +CONFIG_HSR policy<{'arm64': 'm'}> +CONFIG_HT16K33 policy<{'arm64': 'm'}> +CONFIG_HTE policy<{'arm64': 'y'}> +CONFIG_HTE_TEGRA194 policy<{'arm64': 'm'}> +CONFIG_HTE_TEGRA194_TEST policy<{'arm64': 'm'}> +CONFIG_HTS221 policy<{'arm64': 'm'}> +CONFIG_HTS221_I2C policy<{'arm64': 'm'}> +CONFIG_HTS221_SPI policy<{'arm64': 'm'}> +CONFIG_HTU21 policy<{'arm64': 'm'}> +CONFIG_HUGETLBFS policy<{'arm64': 'y'}> +CONFIG_HUGETLB_PAGE policy<{'arm64': 'y'}> +CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING policy<{'arm64': 'y'}> +CONFIG_HVC_DCC policy<{'arm64': 'n'}> +CONFIG_HVC_DRIVER policy<{'arm64': 'y'}> +CONFIG_HVC_IRQ policy<{'arm64': 'y'}> +CONFIG_HVC_XEN policy<{'arm64': 'y'}> +CONFIG_HVC_XEN_FRONTEND policy<{'arm64': 'y'}> +CONFIG_HWLAT_TRACER policy<{'arm64': 'y'}> +CONFIG_HWMON policy<{'arm64': 'y'}> +CONFIG_HWMON_DEBUG_CHIP policy<{'arm64': 'n'}> +CONFIG_HWMON_VID policy<{'arm64': 'm'}> +CONFIG_HWPOISON_INJECT policy<{'arm64': 'm'}> +CONFIG_HWSPINLOCK policy<{'arm64': 'y'}> +CONFIG_HWSPINLOCK_OMAP policy<{'arm64': 'm'}> +CONFIG_HWSPINLOCK_QCOM policy<{'arm64': 'y'}> +CONFIG_HWSPINLOCK_SPRD policy<{'arm64': 'm'}> +CONFIG_HWSPINLOCK_SUN6I policy<{'arm64': 'm'}> +CONFIG_HW_PERF_EVENTS policy<{'arm64': 'y'}> +CONFIG_HW_RANDOM policy<{'arm64': 'y'}> +CONFIG_HW_RANDOM_AIROHA policy<{'arm64': 'y'}> +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_ATMEL policy<{'arm64': 'y'}> +CONFIG_HW_RANDOM_BA431 policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_CAVIUM policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_CCTRNG policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_CN10K policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_HISI policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_HISI_TRNG policy<{'arm64': 'n'}> +CONFIG_HW_RANDOM_HISTB policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_MESON policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_MTK policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_NPCM policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_OMAP policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_OPTEE policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_ROCKCHIP policy<{'arm64': 'y'}> +CONFIG_HW_RANDOM_STM32 policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_TIMERIOMEM policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_TPM policy<{'arm64': 'y'}> +CONFIG_HW_RANDOM_VIRTIO policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_XGENE policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_XILINX policy<{'arm64': 'n'}> +CONFIG_HW_RANDOM_XIPHERA policy<{'arm64': 'm'}> +CONFIG_HX711 policy<{'arm64': 'm'}> +CONFIG_HX9023S policy<{'arm64': 'n'}> +CONFIG_HYPERV policy<{'arm64': 'n'}> +CONFIG_HZ policy<{'arm64': '1000'}> +CONFIG_HZ_100 policy<{'arm64': 'n'}> +CONFIG_HZ_250 policy<{'arm64': 'n'}> +CONFIG_HZ_300 policy<{'arm64': 'n'}> +CONFIG_HZ_PERIODIC policy<{'arm64': 'n'}> +CONFIG_I2C policy<{'arm64': 'y'}> +CONFIG_I2CR_SCOM policy<{'arm64': 'm'}> +CONFIG_I2C_ALGOBIT policy<{'arm64': 'm'}> +CONFIG_I2C_ALGOPCA policy<{'arm64': 'm'}> +CONFIG_I2C_ALI1535 policy<{'arm64': 'm'}> +CONFIG_I2C_ALI1563 policy<{'arm64': 'm'}> +CONFIG_I2C_ALI15X3 policy<{'arm64': 'm'}> +CONFIG_I2C_ALTERA policy<{'arm64': 'm'}> +CONFIG_I2C_AMD756 policy<{'arm64': 'm'}> +CONFIG_I2C_AMD8111 policy<{'arm64': 'm'}> +CONFIG_I2C_AMD_MP2 policy<{'arm64': 'n'}> +CONFIG_I2C_APPLE policy<{'arm64': 'm'}> +CONFIG_I2C_ARB_GPIO_CHALLENGE policy<{'arm64': 'm'}> +CONFIG_I2C_AT91 policy<{'arm64': 'n'}> +CONFIG_I2C_ATR policy<{'arm64': 'm'}> +CONFIG_I2C_BOARDINFO policy<{'arm64': 'y'}> +CONFIG_I2C_CADENCE policy<{'arm64': 'n'}> +CONFIG_I2C_CBUS_GPIO policy<{'arm64': 'm'}> +CONFIG_I2C_CCGX_UCSI policy<{'arm64': 'm'}> +CONFIG_I2C_CP2615 policy<{'arm64': 'm'}> +CONFIG_I2C_CROS_EC_TUNNEL policy<{'arm64': 'm'}> +CONFIG_I2C_DEBUG_ALGO policy<{'arm64': 'n'}> +CONFIG_I2C_DEBUG_BUS policy<{'arm64': 'n'}> +CONFIG_I2C_DEBUG_CORE policy<{'arm64': 'n'}> +CONFIG_I2C_DEMUX_PINCTRL policy<{'arm64': 'm'}> +CONFIG_I2C_DESIGNWARE_AMDISP policy<{'arm64': 'n'}> +CONFIG_I2C_DESIGNWARE_CORE policy<{'arm64': 'y'}> +CONFIG_I2C_DESIGNWARE_PCI policy<{'arm64': 'm'}> +CONFIG_I2C_DESIGNWARE_PLATFORM policy<{'arm64': 'y'}> +CONFIG_I2C_DIOLAN_U2C policy<{'arm64': 'm'}> +CONFIG_I2C_DLN2 policy<{'arm64': 'm'}> +CONFIG_I2C_EMEV2 policy<{'arm64': 'n'}> +CONFIG_I2C_FSI policy<{'arm64': 'm'}> +CONFIG_I2C_GPIO policy<{'arm64': 'm'}> +CONFIG_I2C_GPIO_FAULT_INJECTOR policy<{'arm64': 'n'}> +CONFIG_I2C_HELPER_AUTO policy<{'arm64': 'y'}> +CONFIG_I2C_HID policy<{'arm64': 'm'}> +CONFIG_I2C_HID_ACPI policy<{'arm64': 'm'}> +CONFIG_I2C_HID_CORE policy<{'arm64': 'm'}> +CONFIG_I2C_HID_OF policy<{'arm64': 'm'}> +CONFIG_I2C_HID_OF_ELAN policy<{'arm64': 'm'}> +CONFIG_I2C_HID_OF_GOODIX policy<{'arm64': 'm'}> +CONFIG_I2C_HISI policy<{'arm64': 'm'}> +CONFIG_I2C_HIX5HD2 policy<{'arm64': 'm'}> +CONFIG_I2C_I801 policy<{'arm64': 'm'}> +CONFIG_I2C_I801_MUX policy<{'arm64': 'y'}> +CONFIG_I2C_IMX policy<{'arm64': 'm'}> +CONFIG_I2C_IMX_LPI2C policy<{'arm64': 'm'}> +CONFIG_I2C_ISCH policy<{'arm64': 'm'}> +CONFIG_I2C_KEBA policy<{'arm64': 'n'}> +CONFIG_I2C_KEMPLD policy<{'arm64': 'm'}> +CONFIG_I2C_LJCA policy<{'arm64': 'm'}> +CONFIG_I2C_MESON policy<{'arm64': 'm'}> +CONFIG_I2C_MLXBF policy<{'arm64': 'm'}> +CONFIG_I2C_MLXCPLD policy<{'arm64': 'm'}> +CONFIG_I2C_MT65XX policy<{'arm64': 'm'}> +CONFIG_I2C_MT7621 policy<{'arm64': 'm'}> +CONFIG_I2C_MUX policy<{'arm64': 'm'}> +CONFIG_I2C_MUX_GPIO policy<{'arm64': 'm'}> +CONFIG_I2C_MUX_GPMUX policy<{'arm64': 'm'}> +CONFIG_I2C_MUX_LTC4306 policy<{'arm64': 'm'}> +CONFIG_I2C_MUX_MLXCPLD policy<{'arm64': 'm'}> +CONFIG_I2C_MUX_MULE policy<{'arm64': 'n'}> +CONFIG_I2C_MUX_PCA9541 policy<{'arm64': 'm'}> +CONFIG_I2C_MUX_PCA954x policy<{'arm64': 'm'}> +CONFIG_I2C_MUX_PINCTRL policy<{'arm64': 'm'}> +CONFIG_I2C_MUX_REG policy<{'arm64': 'm'}> +CONFIG_I2C_MV64XXX policy<{'arm64': 'm'}> +CONFIG_I2C_NFORCE2 policy<{'arm64': 'm'}> +CONFIG_I2C_NOMADIK policy<{'arm64': 'm'}> +CONFIG_I2C_NPCM policy<{'arm64': 'm'}> +CONFIG_I2C_NVIDIA_GPU policy<{'arm64': 'm'}> +CONFIG_I2C_OCORES policy<{'arm64': 'm'}> +CONFIG_I2C_OMAP policy<{'arm64': 'y'}> +CONFIG_I2C_OWL policy<{'arm64': 'm'}> +CONFIG_I2C_PARPORT policy<{'arm64': 'm'}> +CONFIG_I2C_PCA_PLATFORM policy<{'arm64': 'm'}> +CONFIG_I2C_PCI1XXXX policy<{'arm64': 'm'}> +CONFIG_I2C_PIIX4 policy<{'arm64': 'n'}> +CONFIG_I2C_PXA policy<{'arm64': 'm'}> +CONFIG_I2C_PXA_SLAVE policy<{'arm64': 'y'}> +CONFIG_I2C_QCOM_CCI policy<{'arm64': 'm'}> +CONFIG_I2C_QCOM_GENI policy<{'arm64': 'm'}> +CONFIG_I2C_QUP policy<{'arm64': 'm'}> +CONFIG_I2C_RCAR policy<{'arm64': 'm'}> +CONFIG_I2C_RIIC policy<{'arm64': 'm'}> +CONFIG_I2C_RK3X policy<{'arm64': 'm'}> +CONFIG_I2C_ROBOTFUZZ_OSIF policy<{'arm64': 'm'}> +CONFIG_I2C_RZV2M policy<{'arm64': 'm'}> +CONFIG_I2C_SCMI policy<{'arm64': 'm'}> +CONFIG_I2C_SH_MOBILE policy<{'arm64': 'm'}> +CONFIG_I2C_SI470X policy<{'arm64': 'm'}> +CONFIG_I2C_SI4713 policy<{'arm64': 'm'}> +CONFIG_I2C_SIMTEC policy<{'arm64': 'm'}> +CONFIG_I2C_SIS5595 policy<{'arm64': 'm'}> +CONFIG_I2C_SIS630 policy<{'arm64': 'm'}> +CONFIG_I2C_SIS96X policy<{'arm64': 'm'}> +CONFIG_I2C_SLAVE policy<{'arm64': 'y'}> +CONFIG_I2C_SLAVE_EEPROM policy<{'arm64': 'm'}> +CONFIG_I2C_SLAVE_TESTUNIT policy<{'arm64': 'n'}> +CONFIG_I2C_SMBUS policy<{'arm64': 'm'}> +CONFIG_I2C_SPRD policy<{'arm64': 'y'}> +CONFIG_I2C_STM32F4 policy<{'arm64': 'm'}> +CONFIG_I2C_STM32F7 policy<{'arm64': 'm'}> +CONFIG_I2C_STUB policy<{'arm64': 'm'}> +CONFIG_I2C_SYNQUACER policy<{'arm64': 'm'}> +CONFIG_I2C_TAOS_EVM policy<{'arm64': 'm'}> +CONFIG_I2C_TEGRA policy<{'arm64': 'm'}> +CONFIG_I2C_TEGRA_BPMP policy<{'arm64': 'm'}> +CONFIG_I2C_THUNDERX policy<{'arm64': 'm'}> +CONFIG_I2C_TINY_USB policy<{'arm64': 'm'}> +CONFIG_I2C_VERSATILE policy<{'arm64': 'm'}> +CONFIG_I2C_VIA policy<{'arm64': 'm'}> +CONFIG_I2C_VIAPRO policy<{'arm64': 'm'}> +CONFIG_I2C_VIPERBOARD policy<{'arm64': 'm'}> +CONFIG_I2C_VIRTIO policy<{'arm64': 'm'}> +CONFIG_I2C_XGENE_SLIMPRO policy<{'arm64': 'm'}> +CONFIG_I2C_XILINX policy<{'arm64': 'm'}> +CONFIG_I2C_XLP9XX policy<{'arm64': 'm'}> +CONFIG_I2C_ZHAOXIN policy<{'arm64': 'm'}> +CONFIG_I3C policy<{'arm64': 'm'}> +CONFIG_I3C_OR_I2C policy<{'arm64': 'm'}> +CONFIG_I40E policy<{'arm64': 'm'}> +CONFIG_I40EVF policy<{'arm64': 'm'}> +CONFIG_I40E_DCB policy<{'arm64': 'y'}> +CONFIG_I6300ESB_WDT policy<{'arm64': 'm'}> +CONFIG_IAQCORE policy<{'arm64': 'm'}> +CONFIG_IAVF policy<{'arm64': 'm'}> +CONFIG_ICE policy<{'arm64': 'm'}> +CONFIG_ICE_HWMON policy<{'arm64': 'y'}> +CONFIG_ICE_SWITCHDEV policy<{'arm64': 'y'}> +CONFIG_ICP10100 policy<{'arm64': 'm'}> +CONFIG_ICPLUS_PHY policy<{'arm64': 'm'}> +CONFIG_ICS932S401 policy<{'arm64': 'm'}> +CONFIG_IDLE_INJECT policy<{'arm64': 'y'}> +CONFIG_IDPF policy<{'arm64': 'm'}> +CONFIG_IDPF_SINGLEQ policy<{'arm64': 'n'}> +CONFIG_IEEE802154 policy<{'arm64': 'm'}> +CONFIG_IEEE802154_6LOWPAN policy<{'arm64': 'm'}> +CONFIG_IEEE802154_ADF7242 policy<{'arm64': 'm'}> +CONFIG_IEEE802154_AT86RF230 policy<{'arm64': 'm'}> +CONFIG_IEEE802154_ATUSB policy<{'arm64': 'm'}> +CONFIG_IEEE802154_CA8210 policy<{'arm64': 'm'}> +CONFIG_IEEE802154_CA8210_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_IEEE802154_CC2520 policy<{'arm64': 'm'}> +CONFIG_IEEE802154_DRIVERS policy<{'arm64': 'm'}> +CONFIG_IEEE802154_FAKELB policy<{'arm64': 'm'}> +CONFIG_IEEE802154_HWSIM policy<{'arm64': 'm'}> +CONFIG_IEEE802154_MCR20A policy<{'arm64': 'm'}> +CONFIG_IEEE802154_MRF24J40 policy<{'arm64': 'm'}> +CONFIG_IEEE802154_NL802154_EXPERIMENTAL policy<{'arm64': 'n'}> +CONFIG_IEEE802154_SOCKET policy<{'arm64': 'm'}> +CONFIG_IFB policy<{'arm64': 'm'}> +CONFIG_IFCVF policy<{'arm64': 'm'}> +CONFIG_IGB policy<{'arm64': 'm'}> +CONFIG_IGBVF policy<{'arm64': 'm'}> +CONFIG_IGB_HWMON policy<{'arm64': 'y'}> +CONFIG_IGC policy<{'arm64': 'm'}> +CONFIG_IGC_LEDS policy<{'arm64': 'y'}> +CONFIG_IGH_ECAT policy<{'arm64': 'm'}> +CONFIG_IGH_ECAT_ENABLE_EOE policy<{'arm64': 'y'}> +CONFIG_IGH_ECAT_GENERIC_DEVICE policy<{'arm64': 'n'}> +CONFIG_IIO policy<{'arm64': 'm'}> +CONFIG_IIO_ADC_HELPER policy<{'arm64': 'm'}> +CONFIG_IIO_ADIS_LIB policy<{'arm64': 'm'}> +CONFIG_IIO_ADIS_LIB_BUFFER policy<{'arm64': 'y'}> +CONFIG_IIO_BACKEND policy<{'arm64': 'm'}> +CONFIG_IIO_BUFFER policy<{'arm64': 'y'}> +CONFIG_IIO_BUFFER_CB policy<{'arm64': 'm'}> +CONFIG_IIO_BUFFER_DMA policy<{'arm64': 'm'}> +CONFIG_IIO_BUFFER_DMAENGINE policy<{'arm64': 'm'}> +CONFIG_IIO_BUFFER_HW_CONSUMER policy<{'arm64': 'm'}> +CONFIG_IIO_CONFIGFS policy<{'arm64': 'm'}> +CONFIG_IIO_CONSUMERS_PER_TRIGGER policy<{'arm64': '2'}> +CONFIG_IIO_CROS_EC_ACCEL_LEGACY policy<{'arm64': 'm'}> +CONFIG_IIO_CROS_EC_ACTIVITY policy<{'arm64': 'n'}> +CONFIG_IIO_CROS_EC_BARO policy<{'arm64': 'm'}> +CONFIG_IIO_CROS_EC_LIGHT_PROX policy<{'arm64': 'm'}> +CONFIG_IIO_CROS_EC_SENSORS policy<{'arm64': 'm'}> +CONFIG_IIO_CROS_EC_SENSORS_CORE policy<{'arm64': 'm'}> +CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE policy<{'arm64': 'm'}> +CONFIG_IIO_GTS_HELPER policy<{'arm64': 'm'}> +CONFIG_IIO_HRTIMER_TRIGGER policy<{'arm64': 'm'}> +CONFIG_IIO_INV_SENSORS_TIMESTAMP policy<{'arm64': 'm'}> +CONFIG_IIO_KFIFO_BUF policy<{'arm64': 'm'}> +CONFIG_IIO_KX022A policy<{'arm64': 'm'}> +CONFIG_IIO_KX022A_I2C policy<{'arm64': 'm'}> +CONFIG_IIO_KX022A_SPI policy<{'arm64': 'm'}> +CONFIG_IIO_MS_SENSORS_I2C policy<{'arm64': 'm'}> +CONFIG_IIO_MUX policy<{'arm64': 'm'}> +CONFIG_IIO_RESCALE policy<{'arm64': 'm'}> +CONFIG_IIO_SCMI policy<{'arm64': 'm'}> +CONFIG_IIO_SIMPLE_DUMMY policy<{'arm64': 'm'}> +CONFIG_IIO_SIMPLE_DUMMY_BUFFER policy<{'arm64': 'n'}> +CONFIG_IIO_SIMPLE_DUMMY_EVENTS policy<{'arm64': 'n'}> +CONFIG_IIO_SSP_SENSORHUB policy<{'arm64': 'm'}> +CONFIG_IIO_SSP_SENSORS_COMMONS policy<{'arm64': 'm'}> +CONFIG_IIO_STM32_LPTIMER_TRIGGER policy<{'arm64': 'm'}> +CONFIG_IIO_STM32_TIMER_TRIGGER policy<{'arm64': 'm'}> +CONFIG_IIO_ST_ACCEL_3AXIS policy<{'arm64': 'm'}> +CONFIG_IIO_ST_ACCEL_I2C_3AXIS policy<{'arm64': 'm'}> +CONFIG_IIO_ST_ACCEL_SPI_3AXIS policy<{'arm64': 'm'}> +CONFIG_IIO_ST_GYRO_3AXIS policy<{'arm64': 'm'}> +CONFIG_IIO_ST_GYRO_I2C_3AXIS policy<{'arm64': 'm'}> +CONFIG_IIO_ST_GYRO_SPI_3AXIS policy<{'arm64': 'm'}> +CONFIG_IIO_ST_LSM6DSX policy<{'arm64': 'm'}> +CONFIG_IIO_ST_LSM6DSX_I2C policy<{'arm64': 'm'}> +CONFIG_IIO_ST_LSM6DSX_I3C policy<{'arm64': 'm'}> +CONFIG_IIO_ST_LSM6DSX_SPI policy<{'arm64': 'm'}> +CONFIG_IIO_ST_LSM9DS0 policy<{'arm64': 'm'}> +CONFIG_IIO_ST_LSM9DS0_I2C policy<{'arm64': 'm'}> +CONFIG_IIO_ST_LSM9DS0_SPI policy<{'arm64': 'm'}> +CONFIG_IIO_ST_MAGN_3AXIS policy<{'arm64': 'm'}> +CONFIG_IIO_ST_MAGN_I2C_3AXIS policy<{'arm64': 'm'}> +CONFIG_IIO_ST_MAGN_SPI_3AXIS policy<{'arm64': 'm'}> +CONFIG_IIO_ST_PRESS policy<{'arm64': 'm'}> +CONFIG_IIO_ST_PRESS_I2C policy<{'arm64': 'm'}> +CONFIG_IIO_ST_PRESS_SPI policy<{'arm64': 'm'}> +CONFIG_IIO_ST_SENSORS_CORE policy<{'arm64': 'm'}> +CONFIG_IIO_ST_SENSORS_I2C policy<{'arm64': 'm'}> +CONFIG_IIO_ST_SENSORS_SPI policy<{'arm64': 'm'}> +CONFIG_IIO_SW_DEVICE policy<{'arm64': 'm'}> +CONFIG_IIO_SW_TRIGGER policy<{'arm64': 'm'}> +CONFIG_IIO_SYSFS_TRIGGER policy<{'arm64': 'm'}> +CONFIG_IIO_TIGHTLOOP_TRIGGER policy<{'arm64': 'm'}> +CONFIG_IIO_TRIGGER policy<{'arm64': 'y'}> +CONFIG_IIO_TRIGGERED_BUFFER policy<{'arm64': 'm'}> +CONFIG_IIO_TRIGGERED_EVENT policy<{'arm64': 'm'}> +CONFIG_IKCONFIG policy<{'arm64': 'n'}> +CONFIG_IKHEADERS policy<{'arm64': 'm'}> +CONFIG_ILLEGAL_POINTER_VALUE policy<{'arm64': '0xdead000000000000'}> +CONFIG_IMA_APPRAISE_BOOTPARAM policy<{'arm64': 'y'}> +CONFIG_IMA_APPRAISE_BUILD_POLICY policy<{'arm64': 'n'}> +CONFIG_IMA_APPRAISE_MODSIG policy<{'arm64': 'y'}> +CONFIG_IMA_ARCH_POLICY policy<{'arm64': 'y'}> +CONFIG_IMA_BLACKLIST_KEYRING policy<{'arm64': 'n'}> +CONFIG_IMA_DEFAULT_HASH policy<{'arm64': '"sha256"'}> +CONFIG_IMA_DEFAULT_HASH_SHA1 policy<{'arm64': 'n'}> +CONFIG_IMA_DEFAULT_HASH_SHA512 policy<{'arm64': 'n'}> +CONFIG_IMA_DEFAULT_TEMPLATE policy<{'arm64': '"ima-ng"'}> +CONFIG_IMA_DISABLE_HTABLE policy<{'arm64': 'n'}> +CONFIG_IMA_KEXEC_EXTRA_MEMORY_KB policy<{'arm64': '0'}> +CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY policy<{'arm64': 'n'}> +CONFIG_IMA_LOAD_X509 policy<{'arm64': 'n'}> +CONFIG_IMA_LSM_RULES policy<{'arm64': 'y'}> +CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS policy<{'arm64': 'y'}> +CONFIG_IMA_MEASURE_PCR_IDX policy<{'arm64': '10'}> +CONFIG_IMA_NG_TEMPLATE policy<{'arm64': 'y'}> +CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS policy<{'arm64': 'y'}> +CONFIG_IMA_READ_POLICY policy<{'arm64': 'n'}> +CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT policy<{'arm64': 'y'}> +CONFIG_IMA_SIG_TEMPLATE policy<{'arm64': 'n'}> +CONFIG_IMA_STAGING policy<{'arm64': 'n'}> +CONFIG_IMA_WRITE_POLICY policy<{'arm64': 'n'}> +CONFIG_IMG_ASCII_LCD policy<{'arm64': 'm'}> +CONFIG_IMX2_WDT policy<{'arm64': 'm'}> +CONFIG_IMX7D_ADC policy<{'arm64': 'm'}> +CONFIG_IMX7ULP_WDT policy<{'arm64': 'm'}> +CONFIG_IMX8MM_THERMAL policy<{'arm64': 'm'}> +CONFIG_IMX8M_BLK_CTRL policy<{'arm64': 'y'}> +CONFIG_IMX8QXP_ADC policy<{'arm64': 'm'}> +CONFIG_IMX91_THERMAL policy<{'arm64': 'n'}> +CONFIG_IMX93_ADC policy<{'arm64': 'm'}> +CONFIG_IMX9_BLK_CTRL policy<{'arm64': 'y'}> +CONFIG_IMX_AIPSTZ policy<{'arm64': 'n'}> +CONFIG_IMX_DMA policy<{'arm64': 'm'}> +CONFIG_IMX_DSP policy<{'arm64': 'm'}> +CONFIG_IMX_DSP_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_IMX_GPCV2 policy<{'arm64': 'y'}> +CONFIG_IMX_GPCV2_PM_DOMAINS policy<{'arm64': 'y'}> +CONFIG_IMX_INTMUX policy<{'arm64': 'y'}> +CONFIG_IMX_IRQSTEER policy<{'arm64': 'y'}> +CONFIG_IMX_MBOX policy<{'arm64': 'm'}> +CONFIG_IMX_MU_MSI policy<{'arm64': 'm'}> +CONFIG_IMX_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_IMX_SCMI_BBM_EXT policy<{'arm64': 'y'}> +CONFIG_IMX_SCMI_CPU_DRV policy<{'arm64': 'y'}> +CONFIG_IMX_SCMI_CPU_EXT policy<{'arm64': 'y'}> +CONFIG_IMX_SCMI_LMM_DRV policy<{'arm64': 'y'}> +CONFIG_IMX_SCMI_LMM_EXT policy<{'arm64': 'y'}> +CONFIG_IMX_SCMI_MISC_DRV policy<{'arm64': 'y'}> +CONFIG_IMX_SCMI_MISC_EXT policy<{'arm64': 'y'}> +CONFIG_IMX_SCU policy<{'arm64': 'y'}> +CONFIG_IMX_SCU_PD policy<{'arm64': 'y'}> +CONFIG_IMX_SC_THERMAL policy<{'arm64': 'm'}> +CONFIG_IMX_SC_WDT policy<{'arm64': 'm'}> +CONFIG_IMX_SDMA policy<{'arm64': 'm'}> +CONFIG_IMX_THERMAL policy<{'arm64': 'm'}> +CONFIG_IMX_WEIM policy<{'arm64': 'y'}> +CONFIG_INA2XX_ADC policy<{'arm64': 'm'}> +CONFIG_INDIRECT_PIO policy<{'arm64': 'y'}> +CONFIG_INET policy<{'arm64': 'y'}> +CONFIG_INET6_AH policy<{'arm64': 'm'}> +CONFIG_INET6_ESP policy<{'arm64': 'm'}> +CONFIG_INET6_ESPINTCP policy<{'arm64': 'y'}> +CONFIG_INET6_ESP_OFFLOAD policy<{'arm64': 'm'}> +CONFIG_INET6_IPCOMP policy<{'arm64': 'm'}> +CONFIG_INET6_TUNNEL policy<{'arm64': 'm'}> +CONFIG_INET6_XFRM_TUNNEL policy<{'arm64': 'm'}> +CONFIG_INET_AH policy<{'arm64': 'm'}> +CONFIG_INET_DIAG policy<{'arm64': 'm'}> +CONFIG_INET_DIAG_DESTROY policy<{'arm64': 'y'}> +CONFIG_INET_ESP policy<{'arm64': 'm'}> +CONFIG_INET_ESPINTCP policy<{'arm64': 'y'}> +CONFIG_INET_ESP_OFFLOAD policy<{'arm64': 'm'}> +CONFIG_INET_IPCOMP policy<{'arm64': 'm'}> +CONFIG_INET_MPTCP_DIAG policy<{'arm64': 'm'}> +CONFIG_INET_PSP policy<{'arm64': 'n'}> +CONFIG_INET_RAW_DIAG policy<{'arm64': 'm'}> +CONFIG_INET_SCTP_DIAG policy<{'arm64': 'm'}> +CONFIG_INET_TABLE_PERTURB_ORDER policy<{'arm64': '16'}> +CONFIG_INET_TCP_DIAG policy<{'arm64': 'm'}> +CONFIG_INET_TUNNEL policy<{'arm64': 'm'}> +CONFIG_INET_UDP_DIAG policy<{'arm64': 'm'}> +CONFIG_INET_XFRM_TUNNEL policy<{'arm64': 'm'}> +CONFIG_INFINEON_TLV493D policy<{'arm64': 'n'}> +CONFIG_INFINIBAND policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_ADDR_TRANS policy<{'arm64': 'y'}> +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS policy<{'arm64': 'y'}> +CONFIG_INFINIBAND_BNXT_RE policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_CXGB4 policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_EFA policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_ERDMA policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_HNS_HIP08 policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_IONIC policy<{'arm64': 'n'}> +CONFIG_INFINIBAND_IPOIB policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_IPOIB_CM policy<{'arm64': 'y'}> +CONFIG_INFINIBAND_IPOIB_DEBUG policy<{'arm64': 'y'}> +CONFIG_INFINIBAND_IPOIB_DEBUG_DATA policy<{'arm64': 'n'}> +CONFIG_INFINIBAND_IRDMA policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_ISER policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_ISERT policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_MTHCA policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_MTHCA_DEBUG policy<{'arm64': 'y'}> +CONFIG_INFINIBAND_OCRDMA policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_ON_DEMAND_PAGING policy<{'arm64': 'y'}> +CONFIG_INFINIBAND_QEDR policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_RTRS policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_RTRS_CLIENT policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_RTRS_SERVER policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_SRP policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_SRPT policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_USER_ACCESS policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_USER_ACCESS_CORE policy<{'arm64': 'y'}> +CONFIG_INFINIBAND_USER_MAD policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_USER_MEM policy<{'arm64': 'y'}> +CONFIG_INFINIBAND_VIRT_DMA policy<{'arm64': 'y'}> +CONFIG_INFINIBAND_VMWARE_PVRDMA policy<{'arm64': 'm'}> +CONFIG_INFTL policy<{'arm64': 'm'}> +CONFIG_INITRAMFS_PRESERVE_MTIME policy<{'arm64': 'y'}> +CONFIG_INITRAMFS_SOURCE policy<{'arm64': '""'}> +CONFIG_INIT_ENV_ARG_LIMIT policy<{'arm64': '32'}> +CONFIG_INIT_ON_ALLOC_DEFAULT_ON policy<{'arm64': 'y'}> +CONFIG_INIT_ON_FREE_DEFAULT_ON policy<{'arm64': 'n'}> +CONFIG_INIT_STACK_ALL_PATTERN policy<{'arm64': 'n'}> +CONFIG_INIT_STACK_ALL_ZERO policy<{'arm64': 'y'}> +CONFIG_INIT_STACK_NONE policy<{'arm64': 'n'}> +CONFIG_INOTIFY_USER policy<{'arm64': 'y'}> +CONFIG_INPUT policy<{'arm64': 'y'}> +CONFIG_INPUT_88PM80X_ONKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_88PM860X_ONKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_88PM886_ONKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_AD714X policy<{'arm64': 'm'}> +CONFIG_INPUT_AD714X_I2C policy<{'arm64': 'm'}> +CONFIG_INPUT_AD714X_SPI policy<{'arm64': 'm'}> +CONFIG_INPUT_ADXL34X policy<{'arm64': 'm'}> +CONFIG_INPUT_ADXL34X_I2C policy<{'arm64': 'm'}> +CONFIG_INPUT_ADXL34X_SPI policy<{'arm64': 'm'}> +CONFIG_INPUT_ARIZONA_HAPTICS policy<{'arm64': 'm'}> +CONFIG_INPUT_ATC260X_ONKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_ATI_REMOTE2 policy<{'arm64': 'm'}> +CONFIG_INPUT_ATMEL_CAPTOUCH policy<{'arm64': 'm'}> +CONFIG_INPUT_AW86927 policy<{'arm64': 'n'}> +CONFIG_INPUT_AXP20X_PEK policy<{'arm64': 'm'}> +CONFIG_INPUT_BBNSM_PWRKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_BMA150 policy<{'arm64': 'm'}> +CONFIG_INPUT_CM109 policy<{'arm64': 'm'}> +CONFIG_INPUT_CMA3000 policy<{'arm64': 'm'}> +CONFIG_INPUT_CMA3000_I2C policy<{'arm64': 'm'}> +CONFIG_INPUT_CPCAP_PWRBUTTON policy<{'arm64': 'm'}> +CONFIG_INPUT_CS40L50_VIBRA policy<{'arm64': 'm'}> +CONFIG_INPUT_DA7280_HAPTICS policy<{'arm64': 'm'}> +CONFIG_INPUT_DA9052_ONKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_DA9055_ONKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_DA9063_ONKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_DRV260X_HAPTICS policy<{'arm64': 'm'}> +CONFIG_INPUT_DRV2665_HAPTICS policy<{'arm64': 'm'}> +CONFIG_INPUT_DRV2667_HAPTICS policy<{'arm64': 'm'}> +CONFIG_INPUT_E3X0_BUTTON policy<{'arm64': 'm'}> +CONFIG_INPUT_EVDEV policy<{'arm64': 'y'}> +CONFIG_INPUT_FF_MEMLESS policy<{'arm64': 'm'}> +CONFIG_INPUT_GPIO_BEEPER policy<{'arm64': 'm'}> +CONFIG_INPUT_GPIO_DECODER policy<{'arm64': 'm'}> +CONFIG_INPUT_GPIO_ROTARY_ENCODER policy<{'arm64': 'm'}> +CONFIG_INPUT_GPIO_VIBRA policy<{'arm64': 'm'}> +CONFIG_INPUT_HISI_POWERKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_IBM_PANEL policy<{'arm64': 'm'}> +CONFIG_INPUT_IMS_PCU policy<{'arm64': 'm'}> +CONFIG_INPUT_IQS269A policy<{'arm64': 'm'}> +CONFIG_INPUT_IQS626A policy<{'arm64': 'm'}> +CONFIG_INPUT_IQS7222 policy<{'arm64': 'm'}> +CONFIG_INPUT_JOYDEV policy<{'arm64': 'm'}> +CONFIG_INPUT_JOYSTICK policy<{'arm64': 'y'}> +CONFIG_INPUT_KEYBOARD policy<{'arm64': 'y'}> +CONFIG_INPUT_KEYSPAN_REMOTE policy<{'arm64': 'm'}> +CONFIG_INPUT_KXTJ9 policy<{'arm64': 'm'}> +CONFIG_INPUT_LEDS policy<{'arm64': 'm'}> +CONFIG_INPUT_MATRIXKMAP policy<{'arm64': 'm'}> +CONFIG_INPUT_MAX77650_ONKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_MAX77693_HAPTIC policy<{'arm64': 'm'}> +CONFIG_INPUT_MAX8925_ONKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_MAX8997_HAPTIC policy<{'arm64': 'm'}> +CONFIG_INPUT_MC13783_PWRBUTTON policy<{'arm64': 'm'}> +CONFIG_INPUT_MISC policy<{'arm64': 'y'}> +CONFIG_INPUT_MMA8450 policy<{'arm64': 'm'}> +CONFIG_INPUT_MOUSE policy<{'arm64': 'y'}> +CONFIG_INPUT_MOUSEDEV policy<{'arm64': 'y'}> +CONFIG_INPUT_MOUSEDEV_PSAUX policy<{'arm64': 'y'}> +CONFIG_INPUT_MOUSEDEV_SCREEN_X policy<{'arm64': '1024'}> +CONFIG_INPUT_MOUSEDEV_SCREEN_Y policy<{'arm64': '768'}> +CONFIG_INPUT_PALMAS_PWRBUTTON policy<{'arm64': 'm'}> +CONFIG_INPUT_PCF8574 policy<{'arm64': 'm'}> +CONFIG_INPUT_PM8941_PWRKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_PM8XXX_VIBRATOR policy<{'arm64': 'm'}> +CONFIG_INPUT_POWERMATE policy<{'arm64': 'm'}> +CONFIG_INPUT_PWM_BEEPER policy<{'arm64': 'm'}> +CONFIG_INPUT_PWM_VIBRA policy<{'arm64': 'm'}> +CONFIG_INPUT_RAVE_SP_PWRBUTTON policy<{'arm64': 'm'}> +CONFIG_INPUT_REGULATOR_HAPTIC policy<{'arm64': 'm'}> +CONFIG_INPUT_RETU_PWRBUTTON policy<{'arm64': 'm'}> +CONFIG_INPUT_RK805_PWRKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_RT5120_PWRKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_SC27XX_VIBRA policy<{'arm64': 'm'}> +CONFIG_INPUT_SOC_BUTTON_ARRAY policy<{'arm64': 'm'}> +CONFIG_INPUT_SPARSEKMAP policy<{'arm64': 'm'}> +CONFIG_INPUT_STPMIC1_ONKEY policy<{'arm64': 'm'}> +CONFIG_INPUT_TABLET policy<{'arm64': 'y'}> +CONFIG_INPUT_TOUCHSCREEN policy<{'arm64': 'y'}> +CONFIG_INPUT_TPS65218_PWRBUTTON policy<{'arm64': 'm'}> +CONFIG_INPUT_TPS65219_PWRBUTTON policy<{'arm64': 'm'}> +CONFIG_INPUT_TPS6594_PWRBUTTON policy<{'arm64': 'n'}> +CONFIG_INPUT_TWL4030_PWRBUTTON policy<{'arm64': 'm'}> +CONFIG_INPUT_TWL4030_VIBRA policy<{'arm64': 'm'}> +CONFIG_INPUT_TWL6040_VIBRA policy<{'arm64': 'm'}> +CONFIG_INPUT_VIVALDIFMAP policy<{'arm64': 'y'}> +CONFIG_INPUT_WM831X_ON policy<{'arm64': 'm'}> +CONFIG_INPUT_XEN_KBDDEV_FRONTEND policy<{'arm64': 'm'}> +CONFIG_INPUT_YEALINK policy<{'arm64': 'm'}> +CONFIG_INTEGRITY policy<{'arm64': 'y'}> +CONFIG_INTEGRITY_ASYMMETRIC_KEYS policy<{'arm64': 'y'}> +CONFIG_INTEGRITY_AUDIT policy<{'arm64': 'y'}> +CONFIG_INTEGRITY_CA_MACHINE_KEYRING policy<{'arm64': 'n'}> +CONFIG_INTEGRITY_MACHINE_KEYRING policy<{'arm64': 'y'}> +CONFIG_INTEGRITY_PLATFORM_KEYRING policy<{'arm64': 'y'}> +CONFIG_INTEGRITY_SIGNATURE policy<{'arm64': 'y'}> +CONFIG_INTEGRITY_TRUSTED_KEYRING policy<{'arm64': 'y'}> +CONFIG_INTEL_IDMA64 policy<{'arm64': 'm'}> +CONFIG_INTEL_MEI policy<{'arm64': 'n'}> +CONFIG_INTEL_STRATIX10_RSU policy<{'arm64': 'm'}> +CONFIG_INTEL_STRATIX10_SERVICE policy<{'arm64': 'm'}> +CONFIG_INTEL_TH policy<{'arm64': 'm'}> +CONFIG_INTEL_TH_ACPI policy<{'arm64': 'm'}> +CONFIG_INTEL_TH_DEBUG policy<{'arm64': 'n'}> +CONFIG_INTEL_TH_GTH policy<{'arm64': 'm'}> +CONFIG_INTEL_TH_MSU policy<{'arm64': 'm'}> +CONFIG_INTEL_TH_PCI policy<{'arm64': 'm'}> +CONFIG_INTEL_TH_PTI policy<{'arm64': 'm'}> +CONFIG_INTEL_TH_STH policy<{'arm64': 'm'}> +CONFIG_INTEL_XWAY_PHY policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_CLK policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_IMX policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_IMX8MM policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_IMX8MN policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_IMX8MP policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_IMX8MQ policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_MTK policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_MTK_DVFSRC_EMI policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_MTK_MT8183 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_MTK_MT8195 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_MTK_MT8196 policy<{'arm64': 'n'}> +CONFIG_INTERCONNECT_QCOM policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_BCM_VOTER policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_ELIZA policy<{'arm64': 'n'}> +CONFIG_INTERCONNECT_QCOM_GLYMUR policy<{'arm64': 'n'}> +CONFIG_INTERCONNECT_QCOM_HAWI policy<{'arm64': 'n'}> +CONFIG_INTERCONNECT_QCOM_KAANAPALI policy<{'arm64': 'n'}> +CONFIG_INTERCONNECT_QCOM_MILOS policy<{'arm64': 'n'}> +CONFIG_INTERCONNECT_QCOM_MSM8916 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8937 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8939 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8953 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8976 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8996 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_NORD policy<{'arm64': 'n'}> +CONFIG_INTERCONNECT_QCOM_OSM_L3 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCM2290 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCS404 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCS615 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCS8300 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_QDU1000 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_RPMH policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_RPMH_POSSIBLE policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_SA8775P policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SAR2130P policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC7180 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC7280 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC8180X policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC8280XP policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDM660 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDM670 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDM845 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDX75 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SHIKRA policy<{'arm64': 'n'}> +CONFIG_INTERCONNECT_QCOM_SM6115 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM6350 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM7150 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8150 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8250 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8350 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8450 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8550 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8650 policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8750 policy<{'arm64': 'n'}> +CONFIG_INTERCONNECT_QCOM_SMD_RPM policy<{'arm64': 'm'}> +CONFIG_INTERCONNECT_QCOM_X1E80100 policy<{'arm64': 'y'}> +CONFIG_INTERRUPT_CNT policy<{'arm64': 'm'}> +CONFIG_INTERVAL_TREE policy<{'arm64': 'y'}> +CONFIG_INTERVAL_TREE_SPAN_ITER policy<{'arm64': 'y'}> +CONFIG_INTERVAL_TREE_TEST policy<{'arm64': 'n'}> +CONFIG_INV_ICM42600 policy<{'arm64': 'm'}> +CONFIG_INV_ICM42600_I2C policy<{'arm64': 'm'}> +CONFIG_INV_ICM42600_SPI policy<{'arm64': 'm'}> +CONFIG_INV_ICM45600_I2C policy<{'arm64': 'n'}> +CONFIG_INV_ICM45600_I3C policy<{'arm64': 'n'}> +CONFIG_INV_ICM45600_SPI policy<{'arm64': 'n'}> +CONFIG_INV_MPU6050_I2C policy<{'arm64': 'm'}> +CONFIG_INV_MPU6050_IIO policy<{'arm64': 'm'}> +CONFIG_INV_MPU6050_SPI policy<{'arm64': 'm'}> +CONFIG_IOMMUFD policy<{'arm64': 'm'}> +CONFIG_IOMMUFD_DRIVER policy<{'arm64': 'y'}> +CONFIG_IOMMUFD_DRIVER_CORE policy<{'arm64': 'y'}> +CONFIG_IOMMU_API policy<{'arm64': 'y'}> +CONFIG_IOMMU_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_IOMMU_DEFAULT_DMA_LAZY policy<{'arm64': 'n'}> +CONFIG_IOMMU_DEFAULT_PASSTHROUGH policy<{'arm64': 'n'}> +CONFIG_IOMMU_DMA policy<{'arm64': 'y'}> +CONFIG_IOMMU_IOPF policy<{'arm64': 'y'}> +CONFIG_IOMMU_IOVA policy<{'arm64': 'y'}> +CONFIG_IOMMU_IO_PGTABLE policy<{'arm64': 'y'}> +CONFIG_IOMMU_IO_PGTABLE_ARMV7S policy<{'arm64': 'y'}> +CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST policy<{'arm64': 'n'}> +CONFIG_IOMMU_IO_PGTABLE_DART policy<{'arm64': 'y'}> +CONFIG_IOMMU_IO_PGTABLE_LPAE policy<{'arm64': 'y'}> +CONFIG_IOMMU_MM_DATA policy<{'arm64': 'y'}> +CONFIG_IOMMU_SUPPORT policy<{'arm64': 'y'}> +CONFIG_IOMMU_SVA policy<{'arm64': 'y'}> +CONFIG_IONIC policy<{'arm64': 'm'}> +CONFIG_IOSCHED_BFQ policy<{'arm64': 'm'}> +CONFIG_IOSM policy<{'arm64': 'm'}> +CONFIG_IO_STRICT_DEVMEM policy<{'arm64': 'n'}> +CONFIG_IO_URING policy<{'arm64': 'y'}> +CONFIG_IO_URING_BPF policy<{'arm64': 'y'}> +CONFIG_IO_URING_MOCK_FILE policy<{'arm64': 'n'}> +CONFIG_IO_URING_ZCRX policy<{'arm64': 'y'}> +CONFIG_IO_WQ policy<{'arm64': 'y'}> +CONFIG_IP5XXX_POWER policy<{'arm64': 'm'}> +CONFIG_IP6_NF_FILTER policy<{'arm64': 'm'}> +CONFIG_IP6_NF_IPTABLES policy<{'arm64': 'm'}> +CONFIG_IP6_NF_IPTABLES_LEGACY policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MANGLE policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MATCH_AH policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MATCH_EUI64 policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MATCH_FRAG policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MATCH_HL policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MATCH_IPV6HEADER policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MATCH_MH policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MATCH_OPTS policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MATCH_RPFILTER policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MATCH_RT policy<{'arm64': 'm'}> +CONFIG_IP6_NF_MATCH_SRH policy<{'arm64': 'm'}> +CONFIG_IP6_NF_NAT policy<{'arm64': 'm'}> +CONFIG_IP6_NF_RAW policy<{'arm64': 'n'}> +CONFIG_IP6_NF_SECURITY policy<{'arm64': 'n'}> +CONFIG_IP6_NF_TARGET_HL policy<{'arm64': 'n'}> +CONFIG_IP6_NF_TARGET_MASQUERADE policy<{'arm64': 'n'}> +CONFIG_IP6_NF_TARGET_NPT policy<{'arm64': 'm'}> +CONFIG_IP6_NF_TARGET_REJECT policy<{'arm64': 'm'}> +CONFIG_IP6_NF_TARGET_SYNPROXY policy<{'arm64': 'm'}> +CONFIG_IPACK_BUS policy<{'arm64': 'm'}> +CONFIG_IPC_NS policy<{'arm64': 'y'}> +CONFIG_IPMB_DEVICE_INTERFACE policy<{'arm64': 'm'}> +CONFIG_IPMI_DEVICE_INTERFACE policy<{'arm64': 'm'}> +CONFIG_IPMI_DMI_DECODE policy<{'arm64': 'y'}> +CONFIG_IPMI_HANDLER policy<{'arm64': 'm'}> +CONFIG_IPMI_IPMB policy<{'arm64': 'm'}> +CONFIG_IPMI_KCS_BMC policy<{'arm64': 'm'}> +CONFIG_IPMI_KCS_BMC_CDEV_IPMI policy<{'arm64': 'm'}> +CONFIG_IPMI_KCS_BMC_SERIO policy<{'arm64': 'm'}> +CONFIG_IPMI_PANIC_EVENT policy<{'arm64': 'n'}> +CONFIG_IPMI_PLAT_DATA policy<{'arm64': 'y'}> +CONFIG_IPMI_POWEROFF policy<{'arm64': 'm'}> +CONFIG_IPMI_SI policy<{'arm64': 'm'}> +CONFIG_IPMI_SSIF policy<{'arm64': 'm'}> +CONFIG_IPMI_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_IPMMU_VMSA policy<{'arm64': 'n'}> +CONFIG_IPQ_APSS_5424 policy<{'arm64': 'm'}> +CONFIG_IPQ_APSS_6018 policy<{'arm64': 'm'}> +CONFIG_IPQ_APSS_PLL policy<{'arm64': 'm'}> +CONFIG_IPQ_CMN_PLL policy<{'arm64': 'n'}> +CONFIG_IPQ_GCC_4019 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_5018 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_5210 policy<{'arm64': 'n'}> +CONFIG_IPQ_GCC_5332 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_5424 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_6018 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_8074 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_9574 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_9650 policy<{'arm64': 'y'}> +CONFIG_IPQ_NSSCC_5424 policy<{'arm64': 'n'}> +CONFIG_IPQ_NSSCC_9574 policy<{'arm64': 'n'}> +CONFIG_IPQ_NSSCC_QCA8K policy<{'arm64': 'm'}> +CONFIG_IPU_BRIDGE policy<{'arm64': 'm'}> +CONFIG_IPV6_FOU policy<{'arm64': 'm'}> +CONFIG_IPV6_FOU_TUNNEL policy<{'arm64': 'm'}> +CONFIG_IPV6_GRE policy<{'arm64': 'm'}> +CONFIG_IPV6_ILA policy<{'arm64': 'm'}> +CONFIG_IPV6_IOAM6_LWTUNNEL policy<{'arm64': 'y'}> +CONFIG_IPV6_MIP6 policy<{'arm64': 'm'}> +CONFIG_IPV6_MROUTE policy<{'arm64': 'y'}> +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES policy<{'arm64': 'y'}> +CONFIG_IPV6_MULTIPLE_TABLES policy<{'arm64': 'y'}> +CONFIG_IPV6_NDISC_NODETYPE policy<{'arm64': 'y'}> +CONFIG_IPV6_OPTIMISTIC_DAD policy<{'arm64': 'n'}> +CONFIG_IPV6_PIMSM_V2 policy<{'arm64': 'y'}> +CONFIG_IPV6_ROUTER_PREF policy<{'arm64': 'y'}> +CONFIG_IPV6_ROUTE_INFO policy<{'arm64': 'y'}> +CONFIG_IPV6_RPL_LWTUNNEL policy<{'arm64': 'n'}> +CONFIG_IPV6_SEG6_BPF policy<{'arm64': 'y'}> +CONFIG_IPV6_SEG6_HMAC policy<{'arm64': 'y'}> +CONFIG_IPV6_SEG6_LWTUNNEL policy<{'arm64': 'y'}> +CONFIG_IPV6_SIT policy<{'arm64': 'm'}> +CONFIG_IPV6_SIT_6RD policy<{'arm64': 'y'}> +CONFIG_IPV6_SUBTREES policy<{'arm64': 'y'}> +CONFIG_IPV6_TUNNEL policy<{'arm64': 'm'}> +CONFIG_IPV6_VTI policy<{'arm64': 'm'}> +CONFIG_IPVLAN policy<{'arm64': 'm'}> +CONFIG_IPVLAN_L3S policy<{'arm64': 'y'}> +CONFIG_IPVTAP policy<{'arm64': 'm'}> +CONFIG_IPW2100 policy<{'arm64': 'm'}> +CONFIG_IPW2100_DEBUG policy<{'arm64': 'n'}> +CONFIG_IPW2100_MONITOR policy<{'arm64': 'y'}> +CONFIG_IPW2200 policy<{'arm64': 'm'}> +CONFIG_IPW2200_DEBUG policy<{'arm64': 'n'}> +CONFIG_IPW2200_MONITOR policy<{'arm64': 'y'}> +CONFIG_IPW2200_PROMISCUOUS policy<{'arm64': 'y'}> +CONFIG_IPW2200_QOS policy<{'arm64': 'y'}> +CONFIG_IPW2200_RADIOTAP policy<{'arm64': 'y'}> +CONFIG_IPWIRELESS policy<{'arm64': 'n'}> +CONFIG_IP_ADVANCED_ROUTER policy<{'arm64': 'y'}> +CONFIG_IP_FIB_TRIE_STATS policy<{'arm64': 'y'}> +CONFIG_IP_MROUTE policy<{'arm64': 'y'}> +CONFIG_IP_MROUTE_COMMON policy<{'arm64': 'y'}> +CONFIG_IP_MROUTE_MULTIPLE_TABLES policy<{'arm64': 'y'}> +CONFIG_IP_MULTICAST policy<{'arm64': 'y'}> +CONFIG_IP_MULTIPLE_TABLES policy<{'arm64': 'y'}> +CONFIG_IP_NF_ARPFILTER policy<{'arm64': 'n'}> +CONFIG_IP_NF_ARPTABLES policy<{'arm64': 'n'}> +CONFIG_IP_NF_ARP_MANGLE policy<{'arm64': 'm'}> +CONFIG_IP_NF_FILTER policy<{'arm64': 'm'}> +CONFIG_IP_NF_IPTABLES policy<{'arm64': 'm'}> +CONFIG_IP_NF_IPTABLES_LEGACY policy<{'arm64': 'm'}> +CONFIG_IP_NF_MANGLE policy<{'arm64': 'm'}> +CONFIG_IP_NF_MATCH_AH policy<{'arm64': 'm'}> +CONFIG_IP_NF_MATCH_ECN policy<{'arm64': 'm'}> +CONFIG_IP_NF_MATCH_RPFILTER policy<{'arm64': 'm'}> +CONFIG_IP_NF_MATCH_TTL policy<{'arm64': 'm'}> +CONFIG_IP_NF_NAT policy<{'arm64': 'm'}> +CONFIG_IP_NF_RAW policy<{'arm64': 'n'}> +CONFIG_IP_NF_SECURITY policy<{'arm64': 'n'}> +CONFIG_IP_NF_TARGET_ECN policy<{'arm64': 'm'}> +CONFIG_IP_NF_TARGET_MASQUERADE policy<{'arm64': 'n'}> +CONFIG_IP_NF_TARGET_NETMAP policy<{'arm64': 'n'}> +CONFIG_IP_NF_TARGET_REDIRECT policy<{'arm64': 'n'}> +CONFIG_IP_NF_TARGET_REJECT policy<{'arm64': 'm'}> +CONFIG_IP_NF_TARGET_SYNPROXY policy<{'arm64': 'm'}> +CONFIG_IP_NF_TARGET_TTL policy<{'arm64': 'n'}> +CONFIG_IP_PIMSM_V1 policy<{'arm64': 'y'}> +CONFIG_IP_PIMSM_V2 policy<{'arm64': 'y'}> +CONFIG_IP_PNP policy<{'arm64': 'n'}> +CONFIG_IP_ROUTE_CLASSID policy<{'arm64': 'y'}> +CONFIG_IP_ROUTE_MULTIPATH policy<{'arm64': 'y'}> +CONFIG_IP_ROUTE_VERBOSE policy<{'arm64': 'y'}> +CONFIG_IP_SCTP policy<{'arm64': 'm'}> +CONFIG_IP_SET policy<{'arm64': 'm'}> +CONFIG_IP_SET_BITMAP_IP policy<{'arm64': 'm'}> +CONFIG_IP_SET_BITMAP_IPMAC policy<{'arm64': 'm'}> +CONFIG_IP_SET_BITMAP_PORT policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_IP policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_IPMAC policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_IPMARK policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_IPPORT policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_IPPORTIP policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_IPPORTNET policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_MAC policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_NET policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_NETIFACE policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_NETNET policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_NETPORT policy<{'arm64': 'm'}> +CONFIG_IP_SET_HASH_NETPORTNET policy<{'arm64': 'm'}> +CONFIG_IP_SET_LIST_SET policy<{'arm64': 'm'}> +CONFIG_IP_SET_MAX policy<{'arm64': '256'}> +CONFIG_IP_VS policy<{'arm64': 'm'}> +CONFIG_IP_VS_DEBUG policy<{'arm64': 'n'}> +CONFIG_IP_VS_DH policy<{'arm64': 'm'}> +CONFIG_IP_VS_FO policy<{'arm64': 'm'}> +CONFIG_IP_VS_FTP policy<{'arm64': 'm'}> +CONFIG_IP_VS_IPV6 policy<{'arm64': 'y'}> +CONFIG_IP_VS_LBLC policy<{'arm64': 'm'}> +CONFIG_IP_VS_LBLCR policy<{'arm64': 'm'}> +CONFIG_IP_VS_LC policy<{'arm64': 'm'}> +CONFIG_IP_VS_MH policy<{'arm64': 'm'}> +CONFIG_IP_VS_MH_TAB_INDEX policy<{'arm64': '12'}> +CONFIG_IP_VS_NFCT policy<{'arm64': 'y'}> +CONFIG_IP_VS_NQ policy<{'arm64': 'm'}> +CONFIG_IP_VS_OVF policy<{'arm64': 'm'}> +CONFIG_IP_VS_PE_SIP policy<{'arm64': 'm'}> +CONFIG_IP_VS_PROTO_AH policy<{'arm64': 'y'}> +CONFIG_IP_VS_PROTO_AH_ESP policy<{'arm64': 'y'}> +CONFIG_IP_VS_PROTO_ESP policy<{'arm64': 'y'}> +CONFIG_IP_VS_PROTO_SCTP policy<{'arm64': 'y'}> +CONFIG_IP_VS_PROTO_TCP policy<{'arm64': 'y'}> +CONFIG_IP_VS_PROTO_UDP policy<{'arm64': 'y'}> +CONFIG_IP_VS_RR policy<{'arm64': 'm'}> +CONFIG_IP_VS_SED policy<{'arm64': 'm'}> +CONFIG_IP_VS_SH policy<{'arm64': 'm'}> +CONFIG_IP_VS_SH_TAB_BITS policy<{'arm64': '8'}> +CONFIG_IP_VS_TAB_BITS policy<{'arm64': '12'}> +CONFIG_IP_VS_TWOS policy<{'arm64': 'm'}> +CONFIG_IP_VS_WLC policy<{'arm64': 'm'}> +CONFIG_IP_VS_WRR policy<{'arm64': 'm'}> +CONFIG_IQS620AT_TEMP policy<{'arm64': 'm'}> +CONFIG_IQS621_ALS policy<{'arm64': 'm'}> +CONFIG_IQS624_POS policy<{'arm64': 'm'}> +CONFIG_IRQCHIP policy<{'arm64': 'y'}> +CONFIG_IRQSOFF_TRACER policy<{'arm64': 'n'}> +CONFIG_IRQ_BYPASS_MANAGER policy<{'arm64': 'y'}> +CONFIG_IRQ_DOMAIN policy<{'arm64': 'y'}> +CONFIG_IRQ_DOMAIN_HIERARCHY policy<{'arm64': 'y'}> +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS policy<{'arm64': 'y'}> +CONFIG_IRQ_FORCED_THREADING policy<{'arm64': 'y'}> +CONFIG_IRQ_MSI_IOMMU policy<{'arm64': 'y'}> +CONFIG_IRQ_MSI_LIB policy<{'arm64': 'y'}> +CONFIG_IRQ_POLL policy<{'arm64': 'y'}> +CONFIG_IRQ_SIM policy<{'arm64': 'y'}> +CONFIG_IRQ_TIME_ACCOUNTING policy<{'arm64': 'n'}> +CONFIG_IRQ_WORK policy<{'arm64': 'y'}> +CONFIG_IRSD200 policy<{'arm64': 'm'}> +CONFIG_IR_ENE policy<{'arm64': 'm'}> +CONFIG_IR_FINTEK policy<{'arm64': 'm'}> +CONFIG_IR_GPIO_CIR policy<{'arm64': 'm'}> +CONFIG_IR_GPIO_TX policy<{'arm64': 'm'}> +CONFIG_IR_HIX5HD2 policy<{'arm64': 'm'}> +CONFIG_IR_IGORPLUGUSB policy<{'arm64': 'm'}> +CONFIG_IR_IGUANA policy<{'arm64': 'm'}> +CONFIG_IR_IMON policy<{'arm64': 'm'}> +CONFIG_IR_IMON_DECODER policy<{'arm64': 'm'}> +CONFIG_IR_IMON_RAW policy<{'arm64': 'm'}> +CONFIG_IR_ITE_CIR policy<{'arm64': 'm'}> +CONFIG_IR_JVC_DECODER policy<{'arm64': 'm'}> +CONFIG_IR_MCEUSB policy<{'arm64': 'm'}> +CONFIG_IR_MCE_KBD_DECODER policy<{'arm64': 'm'}> +CONFIG_IR_MESON policy<{'arm64': 'm'}> +CONFIG_IR_MESON_TX policy<{'arm64': 'm'}> +CONFIG_IR_MTK policy<{'arm64': 'm'}> +CONFIG_IR_NEC_DECODER policy<{'arm64': 'm'}> +CONFIG_IR_NUVOTON policy<{'arm64': 'm'}> +CONFIG_IR_PWM_TX policy<{'arm64': 'm'}> +CONFIG_IR_RC5_DECODER policy<{'arm64': 'm'}> +CONFIG_IR_RC6_DECODER policy<{'arm64': 'm'}> +CONFIG_IR_RCMM_DECODER policy<{'arm64': 'm'}> +CONFIG_IR_REDRAT3 policy<{'arm64': 'm'}> +CONFIG_IR_SANYO_DECODER policy<{'arm64': 'm'}> +CONFIG_IR_SERIAL policy<{'arm64': 'm'}> +CONFIG_IR_SERIAL_TRANSMITTER policy<{'arm64': 'y'}> +CONFIG_IR_SHARP_DECODER policy<{'arm64': 'm'}> +CONFIG_IR_SONY_DECODER policy<{'arm64': 'm'}> +CONFIG_IR_SPI policy<{'arm64': 'm'}> +CONFIG_IR_STREAMZAP policy<{'arm64': 'm'}> +CONFIG_IR_SUNXI policy<{'arm64': 'm'}> +CONFIG_IR_TOY policy<{'arm64': 'm'}> +CONFIG_IR_TTUSBIR policy<{'arm64': 'm'}> +CONFIG_IR_XMP_DECODER policy<{'arm64': 'm'}> +CONFIG_ISCSI_BOOT_SYSFS policy<{'arm64': 'm'}> +CONFIG_ISCSI_IBFT policy<{'arm64': 'm'}> +CONFIG_ISCSI_TARGET policy<{'arm64': 'm'}> +CONFIG_ISCSI_TARGET_CXGB4 policy<{'arm64': 'm'}> +CONFIG_ISCSI_TCP policy<{'arm64': 'm'}> +CONFIG_ISL29003 policy<{'arm64': 'm'}> +CONFIG_ISL29020 policy<{'arm64': 'm'}> +CONFIG_ISL29125 policy<{'arm64': 'm'}> +CONFIG_ISL29501 policy<{'arm64': 'm'}> +CONFIG_ISL76682 policy<{'arm64': 'm'}> +CONFIG_ISO9660_FS policy<{'arm64': 'm'}> +CONFIG_ITG3200 policy<{'arm64': 'm'}> +CONFIG_IWL3945 policy<{'arm64': 'm'}> +CONFIG_IWL4965 policy<{'arm64': 'm'}> +CONFIG_IWLDVM policy<{'arm64': 'm'}> +CONFIG_IWLEGACY policy<{'arm64': 'm'}> +CONFIG_IWLEGACY_DEBUG policy<{'arm64': 'n'}> +CONFIG_IWLEGACY_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_IWLMLD policy<{'arm64': 'n'}> +CONFIG_IWLMVM policy<{'arm64': 'm'}> +CONFIG_IWLWIFI policy<{'arm64': 'm'}> +CONFIG_IWLWIFI_DEBUG policy<{'arm64': 'n'}> +CONFIG_IWLWIFI_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_IWLWIFI_DEVICE_TRACING policy<{'arm64': 'y'}> +CONFIG_IWLWIFI_LEDS policy<{'arm64': 'y'}> +CONFIG_IWLWIFI_OPMODE_MODULAR policy<{'arm64': 'y'}> +CONFIG_IXGBE policy<{'arm64': 'm'}> +CONFIG_IXGBEVF policy<{'arm64': 'm'}> +CONFIG_IXGBEVF_IPSEC policy<{'arm64': 'y'}> +CONFIG_IXGBE_DCB policy<{'arm64': 'y'}> +CONFIG_IXGBE_HWMON policy<{'arm64': 'y'}> +CONFIG_IXGBE_IPSEC policy<{'arm64': 'y'}> +CONFIG_JBD2 policy<{'arm64': 'y'}> +CONFIG_JBD2_DEBUG policy<{'arm64': 'n'}> +CONFIG_JFFS2_CMODE_FAVOURLZO policy<{'arm64': 'y'}> +CONFIG_JFFS2_CMODE_NONE policy<{'arm64': 'n'}> +CONFIG_JFFS2_CMODE_PRIORITY policy<{'arm64': 'n'}> +CONFIG_JFFS2_CMODE_SIZE policy<{'arm64': 'n'}> +CONFIG_JFFS2_COMPRESSION_OPTIONS policy<{'arm64': 'y'}> +CONFIG_JFFS2_FS policy<{'arm64': 'm'}> +CONFIG_JFFS2_FS_DEBUG policy<{'arm64': '0'}> +CONFIG_JFFS2_FS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_JFFS2_FS_SECURITY policy<{'arm64': 'y'}> +CONFIG_JFFS2_FS_WBUF_VERIFY policy<{'arm64': 'n'}> +CONFIG_JFFS2_FS_WRITEBUFFER policy<{'arm64': 'y'}> +CONFIG_JFFS2_FS_XATTR policy<{'arm64': 'y'}> +CONFIG_JFFS2_LZO policy<{'arm64': 'y'}> +CONFIG_JFFS2_RTIME policy<{'arm64': 'y'}> +CONFIG_JFFS2_RUBIN policy<{'arm64': 'n'}> +CONFIG_JFFS2_SUMMARY policy<{'arm64': 'n'}> +CONFIG_JFFS2_ZLIB policy<{'arm64': 'y'}> +CONFIG_JFS_DEBUG policy<{'arm64': 'n'}> +CONFIG_JFS_FS policy<{'arm64': 'm'}> +CONFIG_JFS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_JFS_SECURITY policy<{'arm64': 'y'}> +CONFIG_JFS_STATISTICS policy<{'arm64': 'y'}> +CONFIG_JME policy<{'arm64': 'm'}> +CONFIG_JOLIET policy<{'arm64': 'y'}> +CONFIG_JOYSTICK_A3D policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_ADC policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_ADI policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_ANALOG policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_AS5011 policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_COBRA policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_DB9 policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_FSIA6B policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_GAMECON policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_GF2K policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_GRIP policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_GRIP_MP policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_GUILLEMOT policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_IFORCE policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_IFORCE_232 policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_IFORCE_USB policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_INTERACT policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_JOYDUMP policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_MAGELLAN policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_PSXPAD_SPI policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_PSXPAD_SPI_FF policy<{'arm64': 'y'}> +CONFIG_JOYSTICK_PXRC policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_QWIIC policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_SEESAW policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_SENSEHAT policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_SIDEWINDER policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_SPACEBALL policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_SPACEORB policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_STINGER policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_TMDC policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_TURBOGRAFX policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_TWIDJOY policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_WALKERA0701 policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_WARRIOR policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_XPAD policy<{'arm64': 'm'}> +CONFIG_JOYSTICK_XPAD_FF policy<{'arm64': 'y'}> +CONFIG_JOYSTICK_XPAD_LEDS policy<{'arm64': 'y'}> +CONFIG_JOYSTICK_ZHENHUA policy<{'arm64': 'm'}> +CONFIG_JSA1212 policy<{'arm64': 'm'}> +CONFIG_JUMP_LABEL policy<{'arm64': 'y'}> +CONFIG_K3_DMA policy<{'arm64': 'm'}> +CONFIG_K3_RTI_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_K3_THERMAL policy<{'arm64': 'm'}> +CONFIG_KALLSYMS policy<{'arm64': 'y'}> +CONFIG_KALLSYMS_ALL policy<{'arm64': 'y'}> +CONFIG_KALLSYMS_SELFTEST policy<{'arm64': 'n'}> +CONFIG_KARMA_PARTITION policy<{'arm64': 'y'}> +CONFIG_KASAN policy<{'arm64': 'n'}> +CONFIG_KCMP policy<{'arm64': 'y'}> +CONFIG_KCOV policy<{'arm64': 'n'}> +CONFIG_KCSAN policy<{'arm64': 'n'}> +CONFIG_KDB_CONTINUE_CATASTROPHIC policy<{'arm64': '0'}> +CONFIG_KDB_DEFAULT_ENABLE policy<{'arm64': '0x1'}> +CONFIG_KDB_KEYBOARD policy<{'arm64': 'y'}> +CONFIG_KEBA_CP500 policy<{'arm64': 'm'}> +CONFIG_KEBA_LAN9252 policy<{'arm64': 'n'}> +CONFIG_KEEMBAY_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_KEMPLD_WDT policy<{'arm64': 'm'}> +CONFIG_KERNEL_GZIP policy<{'arm64': 'n'}> +CONFIG_KERNEL_MODE_NEON policy<{'arm64': 'y'}> +CONFIG_KERNEL_ZSTD policy<{'arm64': 'y'}> +CONFIG_KERNFS policy<{'arm64': 'y'}> +CONFIG_KEXEC policy<{'arm64': 'y'}> +CONFIG_KEXEC_CORE policy<{'arm64': 'y'}> +CONFIG_KEXEC_FILE policy<{'arm64': 'y'}> +CONFIG_KEXEC_HANDOVER policy<{'arm64': 'n'}> +CONFIG_KEXEC_IMAGE_VERIFY_SIG policy<{'arm64': 'y'}> +CONFIG_KEXEC_SIG policy<{'arm64': 'y'}> +CONFIG_KEYBOARD_ADC policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_ADP5520 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_ADP5588 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_ATKBD policy<{'arm64': 'y'}> +CONFIG_KEYBOARD_BCM policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_CAP11XX policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_CHARLIEPLEX policy<{'arm64': 'n'}> +CONFIG_KEYBOARD_CROS_EC policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_CYPRESS_SF policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_DLINK_DIR685 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_GPIO policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_GPIO_POLLED policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_IMX policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_IMX_BBM_SCMI policy<{'arm64': 'y'}> +CONFIG_KEYBOARD_IMX_SC_KEY policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_IQS62X policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_LKKBD policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_LM8323 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_LM8333 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_MATRIX policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_MAX7359 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_MPR121 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_MT6779 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_MTK_PMIC policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_NEWTON policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_NVEC policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_OMAP4 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_OPENCORES policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_PINEPHONE policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_QT1050 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_QT1070 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_QT2160 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_SAMSUNG policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_SNVS_PWRKEY policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_STMPE policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_STOWAWAY policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_SUN4I_LRADC policy<{'arm64': 'n'}> +CONFIG_KEYBOARD_SUNKBD policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_TC3589X policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_TCA8418 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_TEGRA policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_TM2_TOUCHKEY policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_TWL4030 policy<{'arm64': 'm'}> +CONFIG_KEYBOARD_XTKBD policy<{'arm64': 'm'}> +CONFIG_KEYS policy<{'arm64': 'y'}> +CONFIG_KEYS_REQUEST_CACHE policy<{'arm64': 'y'}> +CONFIG_KEY_DH_OPERATIONS policy<{'arm64': 'y'}> +CONFIG_KEY_NOTIFICATIONS policy<{'arm64': 'y'}> +CONFIG_KFENCE policy<{'arm64': 'y'}> +CONFIG_KFENCE_DEFERRABLE policy<{'arm64': 'n'}> +CONFIG_KFENCE_NUM_OBJECTS policy<{'arm64': '255'}> +CONFIG_KFENCE_SAMPLE_INTERVAL policy<{'arm64': '0'}> +CONFIG_KFENCE_STATIC_KEYS policy<{'arm64': 'n'}> +CONFIG_KFENCE_STRESS_TEST_FAULTS policy<{'arm64': '0'}> +CONFIG_KGDB policy<{'arm64': 'y'}> +CONFIG_KGDB_HONOUR_BLOCKLIST policy<{'arm64': 'y'}> +CONFIG_KGDB_KDB policy<{'arm64': 'y'}> +CONFIG_KGDB_SERIAL_CONSOLE policy<{'arm64': 'y'}> +CONFIG_KGDB_TESTS policy<{'arm64': 'n'}> +CONFIG_KHADAS_MCU_FAN_THERMAL policy<{'arm64': 'm'}> +CONFIG_KMALLOC_PARTITION_CACHES policy<{'arm64': 'y'}> +CONFIG_KMALLOC_PARTITION_RANDOM policy<{'arm64': 'y'}> +CONFIG_KMX61 policy<{'arm64': 'm'}> +CONFIG_KPROBES policy<{'arm64': 'y'}> +CONFIG_KPROBE_EVENTS policy<{'arm64': 'y'}> +CONFIG_KPROBE_EVENTS_ON_NOTRACE policy<{'arm64': 'n'}> +CONFIG_KPROBE_EVENT_GEN_TEST policy<{'arm64': 'n'}> +CONFIG_KPSS_XCC policy<{'arm64': 'm'}> +CONFIG_KRETPROBES policy<{'arm64': 'y'}> +CONFIG_KS0108 policy<{'arm64': 'm'}> +CONFIG_KS0108_DELAY policy<{'arm64': '2'}> +CONFIG_KS0108_PORT policy<{'arm64': '0x378'}> +CONFIG_KS8842 policy<{'arm64': 'm'}> +CONFIG_KS8851 policy<{'arm64': 'm'}> +CONFIG_KS8851_MLL policy<{'arm64': 'm'}> +CONFIG_KSM policy<{'arm64': 'y'}> +CONFIG_KSZ884X_PCI policy<{'arm64': 'm'}> +CONFIG_KUNIT policy<{'arm64': 'n'}> +CONFIG_KUNPENG_HCCS policy<{'arm64': 'm'}> +CONFIG_KUSER_HELPERS policy<{'arm64': 'y'}> +CONFIG_KVFREE_RCU_BATCHED policy<{'arm64': 'y'}> +CONFIG_KVM_COMMON policy<{'arm64': 'y'}> +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT policy<{'arm64': 'y'}> +CONFIG_KVM_GENERIC_HARDWARE_ENABLING policy<{'arm64': 'y'}> +CONFIG_KVM_GUEST_MEMFD policy<{'arm64': 'y'}> +CONFIG_KVM_MMIO policy<{'arm64': 'y'}> +CONFIG_KVM_VFIO policy<{'arm64': 'y'}> +CONFIG_KXCJK1013 policy<{'arm64': 'm'}> +CONFIG_KXSD9 policy<{'arm64': 'm'}> +CONFIG_KXSD9_I2C policy<{'arm64': 'm'}> +CONFIG_KXSD9_SPI policy<{'arm64': 'm'}> +CONFIG_L2TP policy<{'arm64': 'm'}> +CONFIG_L2TP_DEBUGFS policy<{'arm64': 'm'}> +CONFIG_L2TP_ETH policy<{'arm64': 'm'}> +CONFIG_L2TP_IP policy<{'arm64': 'm'}> +CONFIG_L2TP_V3 policy<{'arm64': 'y'}> +CONFIG_LAN743X policy<{'arm64': 'm'}> +CONFIG_LAN865X policy<{'arm64': 'n'}> +CONFIG_LAN966X_DCB policy<{'arm64': 'y'}> +CONFIG_LAN966X_SWITCH policy<{'arm64': 'm'}> +CONFIG_LAN969X_SWITCH policy<{'arm64': 'n'}> +CONFIG_LAPB policy<{'arm64': 'm'}> +CONFIG_LAPBETHER policy<{'arm64': 'm'}> +CONFIG_LATTICE_ECP3_CONFIG policy<{'arm64': 'm'}> +CONFIG_LCD2S policy<{'arm64': 'm'}> +CONFIG_LCD_AMS369FG06 policy<{'arm64': 'm'}> +CONFIG_LCD_CLASS_DEVICE policy<{'arm64': 'm'}> +CONFIG_LCD_HX8357 policy<{'arm64': 'm'}> +CONFIG_LCD_ILI922X policy<{'arm64': 'm'}> +CONFIG_LCD_ILI9320 policy<{'arm64': 'm'}> +CONFIG_LCD_L4F00242T03 policy<{'arm64': 'm'}> +CONFIG_LCD_LMS283GF05 policy<{'arm64': 'm'}> +CONFIG_LCD_LMS501KF03 policy<{'arm64': 'm'}> +CONFIG_LCD_LTV350QV policy<{'arm64': 'm'}> +CONFIG_LCD_OTM3225A policy<{'arm64': 'm'}> +CONFIG_LCD_PLATFORM policy<{'arm64': 'm'}> +CONFIG_LCD_TDO24M policy<{'arm64': 'm'}> +CONFIG_LCD_VGG2432A4 policy<{'arm64': 'm'}> +CONFIG_LDISC_AUTOLOAD policy<{'arm64': 'y'}> +CONFIG_LDM_DEBUG policy<{'arm64': 'n'}> +CONFIG_LDM_PARTITION policy<{'arm64': 'y'}> +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY policy<{'arm64': 'y'}> +CONFIG_LD_IS_BFD policy<{'arm64': 'y'}> +CONFIG_LD_ORPHAN_WARN policy<{'arm64': 'y'}> +CONFIG_LD_ORPHAN_WARN_LEVEL policy<{'arm64': '"warn"'}> +CONFIG_LD_VERSION policy<{'arm64': '24600'}> +CONFIG_LEDS_88PM860X policy<{'arm64': 'm'}> +CONFIG_LEDS_AAT1290 policy<{'arm64': 'm'}> +CONFIG_LEDS_ADP5520 policy<{'arm64': 'm'}> +CONFIG_LEDS_AN30259A policy<{'arm64': 'm'}> +CONFIG_LEDS_AS3645A policy<{'arm64': 'm'}> +CONFIG_LEDS_AW200XX policy<{'arm64': 'm'}> +CONFIG_LEDS_AW2013 policy<{'arm64': 'm'}> +CONFIG_LEDS_BCM6328 policy<{'arm64': 'm'}> +CONFIG_LEDS_BCM6358 policy<{'arm64': 'm'}> +CONFIG_LEDS_BD2606MVV policy<{'arm64': 'm'}> +CONFIG_LEDS_BD2802 policy<{'arm64': 'm'}> +CONFIG_LEDS_BLINKM policy<{'arm64': 'm'}> +CONFIG_LEDS_BLINKM_MULTICOLOR policy<{'arm64': 'n'}> +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED policy<{'arm64': 'y'}> +CONFIG_LEDS_CLASS policy<{'arm64': 'y'}> +CONFIG_LEDS_CLASS_FLASH policy<{'arm64': 'm'}> +CONFIG_LEDS_CLASS_MULTICOLOR policy<{'arm64': 'm'}> +CONFIG_LEDS_CPCAP policy<{'arm64': 'm'}> +CONFIG_LEDS_CR0014114 policy<{'arm64': 'm'}> +CONFIG_LEDS_CROS_EC policy<{'arm64': 'm'}> +CONFIG_LEDS_DA903X policy<{'arm64': 'm'}> +CONFIG_LEDS_DA9052 policy<{'arm64': 'm'}> +CONFIG_LEDS_DAC124S085 policy<{'arm64': 'm'}> +CONFIG_LEDS_EL15203000 policy<{'arm64': 'm'}> +CONFIG_LEDS_EXPRESSWIRE policy<{'arm64': 'y'}> +CONFIG_LEDS_GPIO policy<{'arm64': 'm'}> +CONFIG_LEDS_GROUP_MULTICOLOR policy<{'arm64': 'm'}> +CONFIG_LEDS_IS31FL319X policy<{'arm64': 'm'}> +CONFIG_LEDS_IS31FL32XX policy<{'arm64': 'm'}> +CONFIG_LEDS_KTD202X policy<{'arm64': 'm'}> +CONFIG_LEDS_KTD2692 policy<{'arm64': 'm'}> +CONFIG_LEDS_LM3530 policy<{'arm64': 'm'}> +CONFIG_LEDS_LM3532 policy<{'arm64': 'm'}> +CONFIG_LEDS_LM3533 policy<{'arm64': 'm'}> +CONFIG_LEDS_LM355x policy<{'arm64': 'm'}> +CONFIG_LEDS_LM3601X policy<{'arm64': 'm'}> +CONFIG_LEDS_LM36274 policy<{'arm64': 'm'}> +CONFIG_LEDS_LM3642 policy<{'arm64': 'm'}> +CONFIG_LEDS_LM3692X policy<{'arm64': 'm'}> +CONFIG_LEDS_LM3697 policy<{'arm64': 'm'}> +CONFIG_LEDS_LP3944 policy<{'arm64': 'm'}> +CONFIG_LEDS_LP3952 policy<{'arm64': 'm'}> +CONFIG_LEDS_LP50XX policy<{'arm64': 'm'}> +CONFIG_LEDS_LP5521 policy<{'arm64': 'm'}> +CONFIG_LEDS_LP5523 policy<{'arm64': 'm'}> +CONFIG_LEDS_LP5562 policy<{'arm64': 'm'}> +CONFIG_LEDS_LP5569 policy<{'arm64': 'm'}> +CONFIG_LEDS_LP55XX_COMMON policy<{'arm64': 'm'}> +CONFIG_LEDS_LP5812 policy<{'arm64': 'n'}> +CONFIG_LEDS_LP5860_CORE policy<{'arm64': 'n'}> +CONFIG_LEDS_LP5860_SPI policy<{'arm64': 'n'}> +CONFIG_LEDS_LP8501 policy<{'arm64': 'm'}> +CONFIG_LEDS_LP8788 policy<{'arm64': 'm'}> +CONFIG_LEDS_LP8860 policy<{'arm64': 'm'}> +CONFIG_LEDS_LP8864 policy<{'arm64': 'n'}> +CONFIG_LEDS_LT3593 policy<{'arm64': 'm'}> +CONFIG_LEDS_MAX5970 policy<{'arm64': 'm'}> +CONFIG_LEDS_MAX77650 policy<{'arm64': 'm'}> +CONFIG_LEDS_MAX77693 policy<{'arm64': 'm'}> +CONFIG_LEDS_MAX8997 policy<{'arm64': 'm'}> +CONFIG_LEDS_MC13783 policy<{'arm64': 'm'}> +CONFIG_LEDS_MENF21BMC policy<{'arm64': 'm'}> +CONFIG_LEDS_MLXREG policy<{'arm64': 'm'}> +CONFIG_LEDS_MT6323 policy<{'arm64': 'm'}> +CONFIG_LEDS_MT6360 policy<{'arm64': 'm'}> +CONFIG_LEDS_MT6370_FLASH policy<{'arm64': 'm'}> +CONFIG_LEDS_MT6370_RGB policy<{'arm64': 'm'}> +CONFIG_LEDS_NCP5623 policy<{'arm64': 'm'}> +CONFIG_LEDS_OSRAM_AMS_AS3668 policy<{'arm64': 'n'}> +CONFIG_LEDS_PCA9532 policy<{'arm64': 'm'}> +CONFIG_LEDS_PCA9532_GPIO policy<{'arm64': 'y'}> +CONFIG_LEDS_PCA955X policy<{'arm64': 'm'}> +CONFIG_LEDS_PCA955X_GPIO policy<{'arm64': 'y'}> +CONFIG_LEDS_PCA963X policy<{'arm64': 'm'}> +CONFIG_LEDS_PCA995X policy<{'arm64': 'm'}> +CONFIG_LEDS_PWM policy<{'arm64': 'm'}> +CONFIG_LEDS_PWM_MULTICOLOR policy<{'arm64': 'm'}> +CONFIG_LEDS_QCOM_FLASH policy<{'arm64': 'm'}> +CONFIG_LEDS_QCOM_LPG policy<{'arm64': 'm'}> +CONFIG_LEDS_REGULATOR policy<{'arm64': 'm'}> +CONFIG_LEDS_RT4505 policy<{'arm64': 'm'}> +CONFIG_LEDS_RT8515 policy<{'arm64': 'm'}> +CONFIG_LEDS_SC27XX_BLTC policy<{'arm64': 'm'}> +CONFIG_LEDS_SGM3140 policy<{'arm64': 'm'}> +CONFIG_LEDS_SPI_BYTE policy<{'arm64': 'm'}> +CONFIG_LEDS_ST1202 policy<{'arm64': 'n'}> +CONFIG_LEDS_SUN50I_A100 policy<{'arm64': 'm'}> +CONFIG_LEDS_SY7802 policy<{'arm64': 'm'}> +CONFIG_LEDS_SYSCON policy<{'arm64': 'y'}> +CONFIG_LEDS_TCA6507 policy<{'arm64': 'm'}> +CONFIG_LEDS_TI_LMU_COMMON policy<{'arm64': 'm'}> +CONFIG_LEDS_TLC591XX policy<{'arm64': 'm'}> +CONFIG_LEDS_TPS6105X policy<{'arm64': 'm'}> +CONFIG_LEDS_TPS6131X policy<{'arm64': 'n'}> +CONFIG_LEDS_TRIGGERS policy<{'arm64': 'y'}> +CONFIG_LEDS_TRIGGER_ACTIVITY policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_BACKLIGHT policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_CAMERA policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_CPU policy<{'arm64': 'y'}> +CONFIG_LEDS_TRIGGER_DEFAULT_ON policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_DISK policy<{'arm64': 'y'}> +CONFIG_LEDS_TRIGGER_GPIO policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_HEARTBEAT policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_INPUT_EVENTS policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_MTD policy<{'arm64': 'y'}> +CONFIG_LEDS_TRIGGER_NETDEV policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_ONESHOT policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_PANIC policy<{'arm64': 'y'}> +CONFIG_LEDS_TRIGGER_PATTERN policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_TIMER policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_TRANSIENT policy<{'arm64': 'm'}> +CONFIG_LEDS_TRIGGER_TTY policy<{'arm64': 'm'}> +CONFIG_LEDS_USER policy<{'arm64': 'm'}> +CONFIG_LEDS_WM831X_STATUS policy<{'arm64': 'm'}> +CONFIG_LEDS_WM8350 policy<{'arm64': 'm'}> +CONFIG_LED_TRIGGER_PHY policy<{'arm64': 'y'}> +CONFIG_LEGACY_DIRECT_IO policy<{'arm64': 'y'}> +CONFIG_LEGACY_PTYS policy<{'arm64': 'y'}> +CONFIG_LEGACY_PTY_COUNT policy<{'arm64': '0'}> +CONFIG_LEGACY_TIOCSTI policy<{'arm64': 'n'}> +CONFIG_LIBERTAS policy<{'arm64': 'm'}> +CONFIG_LIBERTAS_DEBUG policy<{'arm64': 'n'}> +CONFIG_LIBERTAS_MESH policy<{'arm64': 'y'}> +CONFIG_LIBERTAS_SDIO policy<{'arm64': 'm'}> +CONFIG_LIBERTAS_SPI policy<{'arm64': 'm'}> +CONFIG_LIBERTAS_THINFIRM policy<{'arm64': 'm'}> +CONFIG_LIBERTAS_THINFIRM_DEBUG policy<{'arm64': 'n'}> +CONFIG_LIBERTAS_THINFIRM_USB policy<{'arm64': 'm'}> +CONFIG_LIBERTAS_USB policy<{'arm64': 'm'}> +CONFIG_LIBETH policy<{'arm64': 'm'}> +CONFIG_LIBETH_XDP policy<{'arm64': 'm'}> +CONFIG_LIBFC policy<{'arm64': 'm'}> +CONFIG_LIBFCOE policy<{'arm64': 'm'}> +CONFIG_LIBFDT policy<{'arm64': 'y'}> +CONFIG_LIBIE policy<{'arm64': 'm'}> +CONFIG_LIBIE_ADMINQ policy<{'arm64': 'm'}> +CONFIG_LIBIE_FWLOG policy<{'arm64': 'm'}> +CONFIG_LIBIPW policy<{'arm64': 'm'}> +CONFIG_LIBIPW_DEBUG policy<{'arm64': 'n'}> +CONFIG_LIBNVDIMM policy<{'arm64': 'y'}> +CONFIG_LIBWX policy<{'arm64': 'm'}> +CONFIG_LIDAR_LITE_V2 policy<{'arm64': 'm'}> +CONFIG_LINEAR_RANGES policy<{'arm64': 'y'}> +CONFIG_LINEDISP policy<{'arm64': 'm'}> +CONFIG_LIQUIDIO policy<{'arm64': 'm'}> +CONFIG_LIQUIDIO_CORE policy<{'arm64': 'm'}> +CONFIG_LIQUIDIO_VF policy<{'arm64': 'm'}> +CONFIG_LIRC policy<{'arm64': 'y'}> +CONFIG_LIST_HARDENED policy<{'arm64': 'n'}> +CONFIG_LITEX policy<{'arm64': 'y'}> +CONFIG_LITEX_LITEETH policy<{'arm64': 'm'}> +CONFIG_LITEX_SOC_CONTROLLER policy<{'arm64': 'm'}> +CONFIG_LIVEPATCH policy<{'arm64': 'n'}> +CONFIG_LKDTM policy<{'arm64': 'n'}> +CONFIG_LLC policy<{'arm64': 'm'}> +CONFIG_LLC2 policy<{'arm64': 'm'}> +CONFIG_LLD_VERSION policy<{'arm64': '0'}> +CONFIG_LMK04832 policy<{'arm64': 'm'}> +CONFIG_LMP91000 policy<{'arm64': 'm'}> +CONFIG_LOAD_UEFI_KEYS policy<{'arm64': 'y'}> +CONFIG_LOCALVERSION policy<{'arm64': '""'}> +CONFIG_LOCALVERSION_AUTO policy<{'arm64': 'n'}> +CONFIG_LOCKD policy<{'arm64': 'm'}> +CONFIG_LOCKDEP_SUPPORT policy<{'arm64': 'y'}> +CONFIG_LOCKD_V4 policy<{'arm64': 'y'}> +CONFIG_LOCKUP_DETECTOR policy<{'arm64': 'y'}> +CONFIG_LOCK_DEBUGGING_SUPPORT policy<{'arm64': 'y'}> +CONFIG_LOCK_DOWN_IN_SECURE_BOOT policy<{'arm64': 'n'}> +CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY policy<{'arm64': 'n'}> +CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY policy<{'arm64': 'n'}> +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE policy<{'arm64': 'y'}> +CONFIG_LOCK_EVENT_COUNTS policy<{'arm64': 'n'}> +CONFIG_LOCK_MM_AND_FIND_VMA policy<{'arm64': 'y'}> +CONFIG_LOCK_SPIN_ON_OWNER policy<{'arm64': 'y'}> +CONFIG_LOCK_STAT policy<{'arm64': 'n'}> +CONFIG_LOCK_TORTURE_TEST policy<{'arm64': 'n'}> +CONFIG_LOGIG940_FF policy<{'arm64': 'y'}> +CONFIG_LOGIRUMBLEPAD2_FF policy<{'arm64': 'y'}> +CONFIG_LOGITECH_FF policy<{'arm64': 'y'}> +CONFIG_LOGIWHEELS_FF policy<{'arm64': 'y'}> +CONFIG_LOGO policy<{'arm64': 'n'}> +CONFIG_LOG_BUF_SHIFT policy<{'arm64': '18'}> +CONFIG_LOG_CPU_MAX_BUF_SHIFT policy<{'arm64': '12'}> +CONFIG_LOOPBACK_TARGET policy<{'arm64': 'm'}> +CONFIG_LP8788_ADC policy<{'arm64': 'm'}> +CONFIG_LPC_ICH policy<{'arm64': 'm'}> +CONFIG_LPC_SCH policy<{'arm64': 'm'}> +CONFIG_LP_CONSOLE policy<{'arm64': 'n'}> +CONFIG_LRU_CACHE policy<{'arm64': 'm'}> +CONFIG_LRU_GEN_STATS policy<{'arm64': 'n'}> +CONFIG_LRU_GEN_WALKS_MMU policy<{'arm64': 'y'}> +CONFIG_LSI_ET1011C_PHY policy<{'arm64': 'm'}> +CONFIG_LSM policy<{'arm64': '"landlock,lockdown,yama,integrity,apparmor"'}> +CONFIG_LSM_MMAP_MIN_ADDR policy<{'arm64': '0'}> +CONFIG_LS_EXTIRQ policy<{'arm64': 'y'}> +CONFIG_LS_SCFG_MSI policy<{'arm64': 'y'}> +CONFIG_LTC1660 policy<{'arm64': 'm'}> +CONFIG_LTC2309 policy<{'arm64': 'm'}> +CONFIG_LTC2471 policy<{'arm64': 'm'}> +CONFIG_LTC2485 policy<{'arm64': 'm'}> +CONFIG_LTC2496 policy<{'arm64': 'm'}> +CONFIG_LTC2497 policy<{'arm64': 'm'}> +CONFIG_LTC2632 policy<{'arm64': 'm'}> +CONFIG_LTC2664 policy<{'arm64': 'n'}> +CONFIG_LTC2688 policy<{'arm64': 'm'}> +CONFIG_LTC2983 policy<{'arm64': 'm'}> +CONFIG_LTO_NONE policy<{'arm64': 'y'}> +CONFIG_LTR390 policy<{'arm64': 'm'}> +CONFIG_LTR501 policy<{'arm64': 'm'}> +CONFIG_LTRF216A policy<{'arm64': 'm'}> +CONFIG_LV0104CS policy<{'arm64': 'm'}> +CONFIG_LWQ_TEST policy<{'arm64': 'n'}> +CONFIG_LWTUNNEL policy<{'arm64': 'y'}> +CONFIG_LWTUNNEL_BPF policy<{'arm64': 'y'}> +CONFIG_LXT_PHY policy<{'arm64': 'm'}> +CONFIG_LZ4HC_COMPRESS policy<{'arm64': 'm'}> +CONFIG_LZ4_COMPRESS policy<{'arm64': 'm'}> +CONFIG_LZ4_DECOMPRESS policy<{'arm64': 'y'}> +CONFIG_LZO_COMPRESS policy<{'arm64': 'y'}> +CONFIG_LZO_DECOMPRESS policy<{'arm64': 'y'}> +CONFIG_M62332 policy<{'arm64': 'm'}> +CONFIG_MAC80211 policy<{'arm64': 'm'}> +CONFIG_MAC80211_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_MAC80211_DEBUG_MENU policy<{'arm64': 'n'}> +CONFIG_MAC80211_HAS_RC policy<{'arm64': 'y'}> +CONFIG_MAC80211_HWSIM policy<{'arm64': 'm'}> +CONFIG_MAC80211_LEDS policy<{'arm64': 'y'}> +CONFIG_MAC80211_MESH policy<{'arm64': 'y'}> +CONFIG_MAC80211_MESSAGE_TRACING policy<{'arm64': 'y'}> +CONFIG_MAC80211_RC_DEFAULT policy<{'arm64': '"minstrel_ht"'}> +CONFIG_MAC80211_RC_DEFAULT_MINSTREL policy<{'arm64': 'y'}> +CONFIG_MAC80211_RC_MINSTREL policy<{'arm64': 'y'}> +CONFIG_MAC80211_STA_HASH_MAX_SIZE policy<{'arm64': '0'}> +CONFIG_MAC802154 policy<{'arm64': 'm'}> +CONFIG_MACB policy<{'arm64': 'm'}> +CONFIG_MACB_PCI policy<{'arm64': 'm'}> +CONFIG_MACB_USE_HWSTAMP policy<{'arm64': 'y'}> +CONFIG_MACSEC policy<{'arm64': 'm'}> +CONFIG_MACVLAN policy<{'arm64': 'm'}> +CONFIG_MACVTAP policy<{'arm64': 'm'}> +CONFIG_MAC_PARTITION policy<{'arm64': 'y'}> +CONFIG_MADERA_IRQ policy<{'arm64': 'm'}> +CONFIG_MAG3110 policy<{'arm64': 'm'}> +CONFIG_MAGIC_SYSRQ policy<{'arm64': 'y'}> +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE policy<{'arm64': '0x01b6'}> +CONFIG_MAGIC_SYSRQ_SERIAL policy<{'arm64': 'y'}> +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE policy<{'arm64': '""'}> +CONFIG_MAILBOX policy<{'arm64': 'y'}> +CONFIG_MAILBOX_TEST policy<{'arm64': 'm'}> +CONFIG_MANAGER_SBS policy<{'arm64': 'm'}> +CONFIG_MANTIS_CORE policy<{'arm64': 'm'}> +CONFIG_MAPPING_DIRTY_HELPERS policy<{'arm64': 'y'}> +CONFIG_MARVELL_10G_PHY policy<{'arm64': 'm'}> +CONFIG_MARVELL_88Q2XXX_PHY policy<{'arm64': 'm'}> +CONFIG_MARVELL_88X2222_PHY policy<{'arm64': 'm'}> +CONFIG_MARVELL_CN10K_DDR_PMU policy<{'arm64': 'm'}> +CONFIG_MARVELL_CN10K_DPI policy<{'arm64': 'm'}> +CONFIG_MARVELL_CN10K_TAD_PMU policy<{'arm64': 'm'}> +CONFIG_MARVELL_GTI_WDT policy<{'arm64': 'm'}> +CONFIG_MARVELL_PEM_PMU policy<{'arm64': 'm'}> +CONFIG_MARVELL_PHY policy<{'arm64': 'm'}> +CONFIG_MAX1027 policy<{'arm64': 'm'}> +CONFIG_MAX11100 policy<{'arm64': 'm'}> +CONFIG_MAX1118 policy<{'arm64': 'm'}> +CONFIG_MAX11205 policy<{'arm64': 'm'}> +CONFIG_MAX11410 policy<{'arm64': 'm'}> +CONFIG_MAX1241 policy<{'arm64': 'm'}> +CONFIG_MAX1363 policy<{'arm64': 'm'}> +CONFIG_MAX14001 policy<{'arm64': 'n'}> +CONFIG_MAX22007 policy<{'arm64': 'n'}> +CONFIG_MAX30100 policy<{'arm64': 'm'}> +CONFIG_MAX30102 policy<{'arm64': 'm'}> +CONFIG_MAX30208 policy<{'arm64': 'm'}> +CONFIG_MAX31827 policy<{'arm64': 'm'}> +CONFIG_MAX31856 policy<{'arm64': 'm'}> +CONFIG_MAX31865 policy<{'arm64': 'm'}> +CONFIG_MAX34408 policy<{'arm64': 'm'}> +CONFIG_MAX44000 policy<{'arm64': 'm'}> +CONFIG_MAX44009 policy<{'arm64': 'm'}> +CONFIG_MAX517 policy<{'arm64': 'm'}> +CONFIG_MAX5432 policy<{'arm64': 'm'}> +CONFIG_MAX5481 policy<{'arm64': 'm'}> +CONFIG_MAX5487 policy<{'arm64': 'm'}> +CONFIG_MAX5522 policy<{'arm64': 'm'}> +CONFIG_MAX5821 policy<{'arm64': 'm'}> +CONFIG_MAX63XX_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_MAX6959 policy<{'arm64': 'm'}> +CONFIG_MAX77541_ADC policy<{'arm64': 'm'}> +CONFIG_MAX77620_THERMAL policy<{'arm64': 'm'}> +CONFIG_MAX77620_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_MAX8925_POWER policy<{'arm64': 'm'}> +CONFIG_MAX9611 policy<{'arm64': 'm'}> +CONFIG_MAXIM_THERMOCOUPLE policy<{'arm64': 'm'}> +CONFIG_MAXLINEAR_86110_PHY policy<{'arm64': 'n'}> +CONFIG_MAXLINEAR_GPHY policy<{'arm64': 'm'}> +CONFIG_MAX_SKB_FRAGS policy<{'arm64': '17'}> +CONFIG_MB1232 policy<{'arm64': 'm'}> +CONFIG_MC3230 policy<{'arm64': 'm'}> +CONFIG_MCB policy<{'arm64': 'm'}> +CONFIG_MCB_LPC policy<{'arm64': 'm'}> +CONFIG_MCB_PCI policy<{'arm64': 'm'}> +CONFIG_MCHP_CLK_MPFS policy<{'arm64': 'y'}> +CONFIG_MCHP_LAN966X_PCI policy<{'arm64': 'n'}> +CONFIG_MCP320X policy<{'arm64': 'm'}> +CONFIG_MCP3422 policy<{'arm64': 'm'}> +CONFIG_MCP3564 policy<{'arm64': 'm'}> +CONFIG_MCP3911 policy<{'arm64': 'm'}> +CONFIG_MCP4018 policy<{'arm64': 'm'}> +CONFIG_MCP41010 policy<{'arm64': 'm'}> +CONFIG_MCP4131 policy<{'arm64': 'm'}> +CONFIG_MCP4531 policy<{'arm64': 'm'}> +CONFIG_MCP4725 policy<{'arm64': 'm'}> +CONFIG_MCP4728 policy<{'arm64': 'm'}> +CONFIG_MCP47FEB02 policy<{'arm64': 'n'}> +CONFIG_MCP4821 policy<{'arm64': 'm'}> +CONFIG_MCP4922 policy<{'arm64': 'm'}> +CONFIG_MCP9600 policy<{'arm64': 'm'}> +CONFIG_MCTP policy<{'arm64': 'y'}> +CONFIG_MCTP_FLOWS policy<{'arm64': 'y'}> +CONFIG_MCTP_SERIAL policy<{'arm64': 'm'}> +CONFIG_MCTP_TRANSPORT_I2C policy<{'arm64': 'm'}> +CONFIG_MCTP_TRANSPORT_I3C policy<{'arm64': 'm'}> +CONFIG_MCTP_TRANSPORT_USB policy<{'arm64': 'n'}> +CONFIG_MD policy<{'arm64': 'y'}> +CONFIG_MDIO policy<{'arm64': 'm'}> +CONFIG_MDIO_AIROHA policy<{'arm64': 'n'}> +CONFIG_MDIO_BCM_UNIMAC policy<{'arm64': 'm'}> +CONFIG_MDIO_BITBANG policy<{'arm64': 'y'}> +CONFIG_MDIO_BUS_MUX policy<{'arm64': 'm'}> +CONFIG_MDIO_BUS_MUX_GPIO policy<{'arm64': 'm'}> +CONFIG_MDIO_BUS_MUX_MESON_G12A policy<{'arm64': 'm'}> +CONFIG_MDIO_BUS_MUX_MESON_GXL policy<{'arm64': 'm'}> +CONFIG_MDIO_BUS_MUX_MMIOREG policy<{'arm64': 'm'}> +CONFIG_MDIO_BUS_MUX_MULTIPLEXER policy<{'arm64': 'm'}> +CONFIG_MDIO_CAVIUM policy<{'arm64': 'm'}> +CONFIG_MDIO_GPIO policy<{'arm64': 'm'}> +CONFIG_MDIO_HISI_FEMAC policy<{'arm64': 'm'}> +CONFIG_MDIO_I2C policy<{'arm64': 'm'}> +CONFIG_MDIO_IPQ4019 policy<{'arm64': 'm'}> +CONFIG_MDIO_IPQ8064 policy<{'arm64': 'm'}> +CONFIG_MDIO_MSCC_MIIM policy<{'arm64': 'm'}> +CONFIG_MDIO_MVUSB policy<{'arm64': 'm'}> +CONFIG_MDIO_OCTEON policy<{'arm64': 'm'}> +CONFIG_MDIO_PIC64HPSC policy<{'arm64': 'n'}> +CONFIG_MDIO_REGMAP policy<{'arm64': 'm'}> +CONFIG_MDIO_SUN4I policy<{'arm64': 'n'}> +CONFIG_MDIO_THUNDER policy<{'arm64': 'm'}> +CONFIG_MDIO_XGENE policy<{'arm64': 'm'}> +CONFIG_MD_AUTODETECT policy<{'arm64': 'y'}> +CONFIG_MD_BITMAP policy<{'arm64': 'y'}> +CONFIG_MD_BITMAP_FILE policy<{'arm64': 'y'}> +CONFIG_MD_CLUSTER policy<{'arm64': 'm'}> +CONFIG_MD_LINEAR policy<{'arm64': 'n'}> +CONFIG_MD_LLBITMAP policy<{'arm64': 'n'}> +CONFIG_MD_RAID0 policy<{'arm64': 'm'}> +CONFIG_MD_RAID1 policy<{'arm64': 'm'}> +CONFIG_MD_RAID10 policy<{'arm64': 'm'}> +CONFIG_MD_RAID456 policy<{'arm64': 'm'}> +CONFIG_MEDIATEK_2P5GE_PHY policy<{'arm64': 'n'}> +CONFIG_MEDIATEK_GE_PHY policy<{'arm64': 'm'}> +CONFIG_MEDIATEK_GE_SOC_PHY policy<{'arm64': 'm'}> +CONFIG_MEDIATEK_MT6359_AUXADC policy<{'arm64': 'm'}> +CONFIG_MEDIATEK_MT6360_ADC policy<{'arm64': 'm'}> +CONFIG_MEDIATEK_MT6370_ADC policy<{'arm64': 'm'}> +CONFIG_MEDIATEK_MT6577_AUXADC policy<{'arm64': 'm'}> +CONFIG_MEDIATEK_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_MEDIA_ALTERA_CI policy<{'arm64': 'm'}> +CONFIG_MEDIA_ANALOG_TV_SUPPORT policy<{'arm64': 'y'}> +CONFIG_MEDIA_ATTACH policy<{'arm64': 'y'}> +CONFIG_MEDIA_CAMERA_SUPPORT policy<{'arm64': 'y'}> +CONFIG_MEDIA_CEC_SUPPORT policy<{'arm64': 'y'}> +CONFIG_MEDIA_COMMON_OPTIONS policy<{'arm64': 'y'}> +CONFIG_MEDIA_CONTROLLER policy<{'arm64': 'y'}> +CONFIG_MEDIA_CONTROLLER_DVB policy<{'arm64': 'y'}> +CONFIG_MEDIA_DIGITAL_TV_SUPPORT policy<{'arm64': 'y'}> +CONFIG_MEDIA_PCI_SUPPORT policy<{'arm64': 'y'}> +CONFIG_MEDIA_PLATFORM_DRIVERS policy<{'arm64': 'y'}> +CONFIG_MEDIA_PLATFORM_SUPPORT policy<{'arm64': 'y'}> +CONFIG_MEDIA_RADIO_SUPPORT policy<{'arm64': 'y'}> +CONFIG_MEDIA_SDR_SUPPORT policy<{'arm64': 'y'}> +CONFIG_MEDIA_SUBDRV_AUTOSELECT policy<{'arm64': 'y'}> +CONFIG_MEDIA_SUPPORT policy<{'arm64': 'm'}> +CONFIG_MEDIA_SUPPORT_FILTER policy<{'arm64': 'y'}> +CONFIG_MEDIA_TEST_SUPPORT policy<{'arm64': 'y'}> +CONFIG_MEDIA_TUNER policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_E4000 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_FC0011 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_FC0012 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_FC0013 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_FC2580 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_IT913X policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_M88RS6000T policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MAX2165 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MC44S803 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MSI001 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MT2060 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MT2063 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MT20XX policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MT2131 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MT2266 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MXL301RF policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MXL5005S policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_MXL5007T policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_QM1D1B0004 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_QM1D1C0042 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_QT1010 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_R820T policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_SI2157 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_SIMPLE policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18212 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18218 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18250 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18271 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_TDA827X policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_TDA8290 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_TDA9887 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_TEA5761 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_TEA5767 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_TUA9001 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_XC2028 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_XC4000 policy<{'arm64': 'm'}> +CONFIG_MEDIA_TUNER_XC5000 policy<{'arm64': 'm'}> +CONFIG_MEDIA_USB_SUPPORT policy<{'arm64': 'y'}> +CONFIG_MEGARAID_LEGACY policy<{'arm64': 'm'}> +CONFIG_MEGARAID_MAILBOX policy<{'arm64': 'm'}> +CONFIG_MEGARAID_MM policy<{'arm64': 'm'}> +CONFIG_MEGARAID_NEWGEN policy<{'arm64': 'y'}> +CONFIG_MEGARAID_SAS policy<{'arm64': 'm'}> +CONFIG_MELLANOX_PLATFORM policy<{'arm64': 'y'}> +CONFIG_MEMBARRIER policy<{'arm64': 'y'}> +CONFIG_MEMCG policy<{'arm64': 'y'}> +CONFIG_MEMCG_V1 policy<{'arm64': 'n'}> +CONFIG_MEMFD_CREATE policy<{'arm64': 'y'}> +CONFIG_MEMORY policy<{'arm64': 'y'}> +CONFIG_MEMORY_FAILURE policy<{'arm64': 'y'}> +CONFIG_MEMORY_HOTPLUG policy<{'arm64': 'y'}> +CONFIG_MEMORY_HOTREMOVE policy<{'arm64': 'y'}> +CONFIG_MEMORY_ISOLATION policy<{'arm64': 'y'}> +CONFIG_MEMORY_NOTIFIER_ERROR_INJECT policy<{'arm64': 'm'}> +CONFIG_MEMREGION policy<{'arm64': 'y'}> +CONFIG_MEMSTICK policy<{'arm64': 'm'}> +CONFIG_MEMSTICK_DEBUG policy<{'arm64': 'n'}> +CONFIG_MEMSTICK_JMICRON_38X policy<{'arm64': 'm'}> +CONFIG_MEMSTICK_R592 policy<{'arm64': 'm'}> +CONFIG_MEMSTICK_REALTEK_USB policy<{'arm64': 'm'}> +CONFIG_MEMSTICK_TIFM_MS policy<{'arm64': 'm'}> +CONFIG_MEMSTICK_UNSAFE_RESUME policy<{'arm64': 'n'}> +CONFIG_MEMTEST policy<{'arm64': 'y'}> +CONFIG_MEM_ALLOC_PROFILING policy<{'arm64': 'n'}> +CONFIG_MENF21BMC_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_MENZ069_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_MEN_A21_WDT policy<{'arm64': 'm'}> +CONFIG_MEN_Z188_ADC policy<{'arm64': 'm'}> +CONFIG_MESON_CANVAS policy<{'arm64': 'm'}> +CONFIG_MESON_CLK_MEASURE policy<{'arm64': 'y'}> +CONFIG_MESON_DDR_PMU policy<{'arm64': 'm'}> +CONFIG_MESON_EE_PM_DOMAINS policy<{'arm64': 'y'}> +CONFIG_MESON_GXBB_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_MESON_GXL_PHY policy<{'arm64': 'm'}> +CONFIG_MESON_GX_SOCINFO policy<{'arm64': 'y'}> +CONFIG_MESON_IRQ_GPIO policy<{'arm64': 'y'}> +CONFIG_MESON_SARADC policy<{'arm64': 'm'}> +CONFIG_MESON_SECURE_PM_DOMAINS policy<{'arm64': 'y'}> +CONFIG_MESON_SM policy<{'arm64': 'y'}> +CONFIG_MESON_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_MESSAGE_LOGLEVEL_DEFAULT policy<{'arm64': '4'}> +CONFIG_MFD_88PM800 policy<{'arm64': 'm'}> +CONFIG_MFD_88PM805 policy<{'arm64': 'm'}> +CONFIG_MFD_88PM860X policy<{'arm64': 'y'}> +CONFIG_MFD_88PM886_PMIC policy<{'arm64': 'y'}> +CONFIG_MFD_AAT2870_CORE policy<{'arm64': 'y'}> +CONFIG_MFD_AC100 policy<{'arm64': 'n'}> +CONFIG_MFD_ACT8945A policy<{'arm64': 'm'}> +CONFIG_MFD_ADP5585 policy<{'arm64': 'n'}> +CONFIG_MFD_ALTERA_A10SR policy<{'arm64': 'y'}> +CONFIG_MFD_ALTERA_SYSMGR policy<{'arm64': 'y'}> +CONFIG_MFD_ARIZONA policy<{'arm64': 'm'}> +CONFIG_MFD_ARIZONA_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_ARIZONA_SPI policy<{'arm64': 'm'}> +CONFIG_MFD_AS3711 policy<{'arm64': 'y'}> +CONFIG_MFD_AS3722 policy<{'arm64': 'y'}> +CONFIG_MFD_AT91_USART policy<{'arm64': 'n'}> +CONFIG_MFD_ATC260X policy<{'arm64': 'm'}> +CONFIG_MFD_ATC260X_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_ATMEL_FLEXCOM policy<{'arm64': 'm'}> +CONFIG_MFD_ATMEL_HLCDC policy<{'arm64': 'm'}> +CONFIG_MFD_AXP20X policy<{'arm64': 'm'}> +CONFIG_MFD_AXP20X_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_AXP20X_RSB policy<{'arm64': 'm'}> +CONFIG_MFD_BCM590XX policy<{'arm64': 'm'}> +CONFIG_MFD_BD9571MWV policy<{'arm64': 'm'}> +CONFIG_MFD_BQ257XX policy<{'arm64': 'n'}> +CONFIG_MFD_CORE policy<{'arm64': 'y'}> +CONFIG_MFD_CPCAP policy<{'arm64': 'm'}> +CONFIG_MFD_CROS_EC_DEV policy<{'arm64': 'm'}> +CONFIG_MFD_CS40L50_CORE policy<{'arm64': 'm'}> +CONFIG_MFD_CS40L50_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_CS40L50_SPI policy<{'arm64': 'm'}> +CONFIG_MFD_CS42L43 policy<{'arm64': 'm'}> +CONFIG_MFD_CS42L43_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_CS42L43_SDW policy<{'arm64': 'm'}> +CONFIG_MFD_CS47L15 policy<{'arm64': 'y'}> +CONFIG_MFD_CS47L24 policy<{'arm64': 'y'}> +CONFIG_MFD_CS47L35 policy<{'arm64': 'y'}> +CONFIG_MFD_CS47L85 policy<{'arm64': 'y'}> +CONFIG_MFD_CS47L90 policy<{'arm64': 'y'}> +CONFIG_MFD_CS47L92 policy<{'arm64': 'y'}> +CONFIG_MFD_DA9052_I2C policy<{'arm64': 'y'}> +CONFIG_MFD_DA9052_SPI policy<{'arm64': 'y'}> +CONFIG_MFD_DA9055 policy<{'arm64': 'y'}> +CONFIG_MFD_DA9062 policy<{'arm64': 'm'}> +CONFIG_MFD_DA9063 policy<{'arm64': 'y'}> +CONFIG_MFD_DA9150 policy<{'arm64': 'm'}> +CONFIG_MFD_DLN2 policy<{'arm64': 'm'}> +CONFIG_MFD_GATEWORKS_GSC policy<{'arm64': 'm'}> +CONFIG_MFD_HI6421_PMIC policy<{'arm64': 'm'}> +CONFIG_MFD_HI6421_SPMI policy<{'arm64': 'm'}> +CONFIG_MFD_HI655X_PMIC policy<{'arm64': 'm'}> +CONFIG_MFD_INTEL_M10_BMC_CORE policy<{'arm64': 'm'}> +CONFIG_MFD_INTEL_M10_BMC_PMCI policy<{'arm64': 'm'}> +CONFIG_MFD_INTEL_M10_BMC_SPI policy<{'arm64': 'm'}> +CONFIG_MFD_IQS62X policy<{'arm64': 'm'}> +CONFIG_MFD_JANZ_CMODIO policy<{'arm64': 'm'}> +CONFIG_MFD_KEMPLD policy<{'arm64': 'm'}> +CONFIG_MFD_KHADAS_MCU policy<{'arm64': 'm'}> +CONFIG_MFD_LM3533 policy<{'arm64': 'm'}> +CONFIG_MFD_LOCHNAGAR policy<{'arm64': 'y'}> +CONFIG_MFD_LP3943 policy<{'arm64': 'm'}> +CONFIG_MFD_LP8788 policy<{'arm64': 'y'}> +CONFIG_MFD_LS2K_BMC_CORE policy<{'arm64': 'n'}> +CONFIG_MFD_MACSMC policy<{'arm64': 'n'}> +CONFIG_MFD_MADERA policy<{'arm64': 'm'}> +CONFIG_MFD_MADERA_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_MADERA_SPI policy<{'arm64': 'm'}> +CONFIG_MFD_MAX14577 policy<{'arm64': 'y'}> +CONFIG_MFD_MAX5970 policy<{'arm64': 'm'}> +CONFIG_MFD_MAX7360 policy<{'arm64': 'n'}> +CONFIG_MFD_MAX77541 policy<{'arm64': 'm'}> +CONFIG_MFD_MAX77620 policy<{'arm64': 'y'}> +CONFIG_MFD_MAX77650 policy<{'arm64': 'm'}> +CONFIG_MFD_MAX77686 policy<{'arm64': 'y'}> +CONFIG_MFD_MAX77693 policy<{'arm64': 'y'}> +CONFIG_MFD_MAX77705 policy<{'arm64': 'n'}> +CONFIG_MFD_MAX77714 policy<{'arm64': 'm'}> +CONFIG_MFD_MAX77759 policy<{'arm64': 'n'}> +CONFIG_MFD_MAX77843 policy<{'arm64': 'y'}> +CONFIG_MFD_MAX8907 policy<{'arm64': 'm'}> +CONFIG_MFD_MAX8925 policy<{'arm64': 'y'}> +CONFIG_MFD_MAX8997 policy<{'arm64': 'y'}> +CONFIG_MFD_MAX8998 policy<{'arm64': 'y'}> +CONFIG_MFD_MC13XXX policy<{'arm64': 'm'}> +CONFIG_MFD_MC13XXX_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_MC13XXX_SPI policy<{'arm64': 'm'}> +CONFIG_MFD_MENF21BMC policy<{'arm64': 'm'}> +CONFIG_MFD_MP2629 policy<{'arm64': 'm'}> +CONFIG_MFD_MT6360 policy<{'arm64': 'm'}> +CONFIG_MFD_MT6370 policy<{'arm64': 'm'}> +CONFIG_MFD_MT6397 policy<{'arm64': 'm'}> +CONFIG_MFD_NCT6694 policy<{'arm64': 'n'}> +CONFIG_MFD_NTXEC policy<{'arm64': 'm'}> +CONFIG_MFD_NVEC policy<{'arm64': 'm'}> +CONFIG_MFD_OCELOT policy<{'arm64': 'm'}> +CONFIG_MFD_PALMAS policy<{'arm64': 'y'}> +CONFIG_MFD_PF1550 policy<{'arm64': 'n'}> +CONFIG_MFD_QCOM_PM8008 policy<{'arm64': 'm'}> +CONFIG_MFD_QCOM_RPM policy<{'arm64': 'y'}> +CONFIG_MFD_QNAP_MCU policy<{'arm64': 'n'}> +CONFIG_MFD_RC5T583 policy<{'arm64': 'y'}> +CONFIG_MFD_RDC321X policy<{'arm64': 'm'}> +CONFIG_MFD_RETU policy<{'arm64': 'm'}> +CONFIG_MFD_RK8XX policy<{'arm64': 'm'}> +CONFIG_MFD_RK8XX_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_RK8XX_SPI policy<{'arm64': 'm'}> +CONFIG_MFD_RN5T618 policy<{'arm64': 'm'}> +CONFIG_MFD_ROHM_BD71828 policy<{'arm64': 'm'}> +CONFIG_MFD_ROHM_BD718XX policy<{'arm64': 'm'}> +CONFIG_MFD_ROHM_BD957XMUF policy<{'arm64': 'm'}> +CONFIG_MFD_ROHM_BD96801 policy<{'arm64': 'm'}> +CONFIG_MFD_RSMU_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_RSMU_SPI policy<{'arm64': 'm'}> +CONFIG_MFD_RT4831 policy<{'arm64': 'm'}> +CONFIG_MFD_RT5033 policy<{'arm64': 'm'}> +CONFIG_MFD_RT5120 policy<{'arm64': 'm'}> +CONFIG_MFD_SC27XX_PMIC policy<{'arm64': 'm'}> +CONFIG_MFD_SEC_I2C policy<{'arm64': 'n'}> +CONFIG_MFD_SI476X_CORE policy<{'arm64': 'm'}> +CONFIG_MFD_SIMPLE_MFD_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_SKY81452 policy<{'arm64': 'm'}> +CONFIG_MFD_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_MFD_SM501_GPIO policy<{'arm64': 'y'}> +CONFIG_MFD_SMPRO policy<{'arm64': 'm'}> +CONFIG_MFD_SPMI_PMIC policy<{'arm64': 'm'}> +CONFIG_MFD_STM32_LPTIMER policy<{'arm64': 'm'}> +CONFIG_MFD_STM32_TIMERS policy<{'arm64': 'm'}> +CONFIG_MFD_STMFX policy<{'arm64': 'm'}> +CONFIG_MFD_STMPE policy<{'arm64': 'y'}> +CONFIG_MFD_STPMIC1 policy<{'arm64': 'm'}> +CONFIG_MFD_SUN4I_GPADC policy<{'arm64': 'm'}> +CONFIG_MFD_SUN6I_PRCM policy<{'arm64': 'y'}> +CONFIG_MFD_SY7636A policy<{'arm64': 'm'}> +CONFIG_MFD_SYSCON policy<{'arm64': 'y'}> +CONFIG_MFD_TC3589X policy<{'arm64': 'y'}> +CONFIG_MFD_TI_AM335X_TSCADC policy<{'arm64': 'm'}> +CONFIG_MFD_TI_LMU policy<{'arm64': 'm'}> +CONFIG_MFD_TI_LP873X policy<{'arm64': 'm'}> +CONFIG_MFD_TI_LP87565 policy<{'arm64': 'm'}> +CONFIG_MFD_TN48M_CPLD policy<{'arm64': 'n'}> +CONFIG_MFD_TPS65086 policy<{'arm64': 'm'}> +CONFIG_MFD_TPS65090 policy<{'arm64': 'y'}> +CONFIG_MFD_TPS65218 policy<{'arm64': 'm'}> +CONFIG_MFD_TPS65219 policy<{'arm64': 'm'}> +CONFIG_MFD_TPS6586X policy<{'arm64': 'y'}> +CONFIG_MFD_TPS65910 policy<{'arm64': 'y'}> +CONFIG_MFD_TPS65912 policy<{'arm64': 'y'}> +CONFIG_MFD_TPS65912_I2C policy<{'arm64': 'y'}> +CONFIG_MFD_TPS65912_SPI policy<{'arm64': 'y'}> +CONFIG_MFD_TPS6594 policy<{'arm64': 'm'}> +CONFIG_MFD_TPS6594_I2C policy<{'arm64': 'm'}> +CONFIG_MFD_TPS6594_SPI policy<{'arm64': 'm'}> +CONFIG_MFD_TQMX86 policy<{'arm64': 'm'}> +CONFIG_MFD_TWL4030_AUDIO policy<{'arm64': 'y'}> +CONFIG_MFD_VEXPRESS_SYSREG policy<{'arm64': 'y'}> +CONFIG_MFD_VIPERBOARD policy<{'arm64': 'm'}> +CONFIG_MFD_VX855 policy<{'arm64': 'm'}> +CONFIG_MFD_WCD934X policy<{'arm64': 'm'}> +CONFIG_MFD_WM5102 policy<{'arm64': 'y'}> +CONFIG_MFD_WM5110 policy<{'arm64': 'y'}> +CONFIG_MFD_WM831X policy<{'arm64': 'y'}> +CONFIG_MFD_WM831X_I2C policy<{'arm64': 'y'}> +CONFIG_MFD_WM831X_SPI policy<{'arm64': 'y'}> +CONFIG_MFD_WM8350 policy<{'arm64': 'y'}> +CONFIG_MFD_WM8350_I2C policy<{'arm64': 'y'}> +CONFIG_MFD_WM8400 policy<{'arm64': 'y'}> +CONFIG_MFD_WM8994 policy<{'arm64': 'm'}> +CONFIG_MFD_WM8997 policy<{'arm64': 'y'}> +CONFIG_MFD_WM8998 policy<{'arm64': 'y'}> +CONFIG_MGBE policy<{'arm64': 'n'}> +CONFIG_MHI_BUS policy<{'arm64': 'm'}> +CONFIG_MHI_BUS_DEBUG policy<{'arm64': 'n'}> +CONFIG_MHI_BUS_EP policy<{'arm64': 'm'}> +CONFIG_MHI_BUS_PCI_GENERIC policy<{'arm64': 'm'}> +CONFIG_MHI_NET policy<{'arm64': 'm'}> +CONFIG_MHI_WWAN_CTRL policy<{'arm64': 'm'}> +CONFIG_MHI_WWAN_MBIM policy<{'arm64': 'm'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE policy<{'arm64': 'y'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO policy<{'arm64': 'n'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_KERNEL policy<{'arm64': 'n'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE policy<{'arm64': 'n'}> +CONFIG_MHP_MEMMAP_ON_MEMORY policy<{'arm64': 'y'}> +CONFIG_MHZ19B policy<{'arm64': 'n'}> +CONFIG_MICREL_PHY policy<{'arm64': 'm'}> +CONFIG_MICROCHIP_PHY policy<{'arm64': 'm'}> +CONFIG_MICROCHIP_PHY_RDS_PTP policy<{'arm64': 'm'}> +CONFIG_MICROCHIP_T1S_PHY policy<{'arm64': 'm'}> +CONFIG_MICROCHIP_T1_PHY policy<{'arm64': 'm'}> +CONFIG_MICROSEMI_PHY policy<{'arm64': 'm'}> +CONFIG_MIGRATION policy<{'arm64': 'y'}> +CONFIG_MII policy<{'arm64': 'y'}> +CONFIG_MINIX_FS policy<{'arm64': 'm'}> +CONFIG_MINIX_SUBPARTITION policy<{'arm64': 'y'}> +CONFIG_MIN_HEAP policy<{'arm64': 'y'}> +CONFIG_MIPI_I3C_HCI policy<{'arm64': 'm'}> +CONFIG_MIPI_I3C_HCI_PCI policy<{'arm64': 'n'}> +CONFIG_MISC_ALCOR_PCI policy<{'arm64': 'm'}> +CONFIG_MISC_FILESYSTEMS policy<{'arm64': 'y'}> +CONFIG_MISC_RP1 policy<{'arm64': 'n'}> +CONFIG_MISC_RTSX policy<{'arm64': 'm'}> +CONFIG_MISC_RTSX_PCI policy<{'arm64': 'm'}> +CONFIG_MISC_RTSX_USB policy<{'arm64': 'm'}> +CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY policy<{'arm64': 'y'}> +CONFIG_MLX4_CORE policy<{'arm64': 'm'}> +CONFIG_MLX4_CORE_GEN2 policy<{'arm64': 'y'}> +CONFIG_MLX4_DEBUG policy<{'arm64': 'y'}> +CONFIG_MLX4_EN policy<{'arm64': 'm'}> +CONFIG_MLX4_EN_DCB policy<{'arm64': 'y'}> +CONFIG_MLX4_INFINIBAND policy<{'arm64': 'm'}> +CONFIG_MLX5_BRIDGE policy<{'arm64': 'y'}> +CONFIG_MLX5_CLS_ACT policy<{'arm64': 'y'}> +CONFIG_MLX5_CORE policy<{'arm64': 'm'}> +CONFIG_MLX5_CORE_EN policy<{'arm64': 'y'}> +CONFIG_MLX5_CORE_EN_DCB policy<{'arm64': 'y'}> +CONFIG_MLX5_CORE_IPOIB policy<{'arm64': 'y'}> +CONFIG_MLX5_DPLL policy<{'arm64': 'm'}> +CONFIG_MLX5_EN_ARFS policy<{'arm64': 'y'}> +CONFIG_MLX5_EN_IPSEC policy<{'arm64': 'y'}> +CONFIG_MLX5_EN_RXNFC policy<{'arm64': 'y'}> +CONFIG_MLX5_EN_TLS policy<{'arm64': 'y'}> +CONFIG_MLX5_ESWITCH policy<{'arm64': 'y'}> +CONFIG_MLX5_FPGA policy<{'arm64': 'y'}> +CONFIG_MLX5_HW_STEERING policy<{'arm64': 'y'}> +CONFIG_MLX5_INFINIBAND policy<{'arm64': 'm'}> +CONFIG_MLX5_MACSEC policy<{'arm64': 'y'}> +CONFIG_MLX5_MPFS policy<{'arm64': 'y'}> +CONFIG_MLX5_SF policy<{'arm64': 'y'}> +CONFIG_MLX5_SF_MANAGER policy<{'arm64': 'y'}> +CONFIG_MLX5_SW_STEERING policy<{'arm64': 'y'}> +CONFIG_MLX5_TC_CT policy<{'arm64': 'y'}> +CONFIG_MLX5_TC_SAMPLE policy<{'arm64': 'y'}> +CONFIG_MLX5_VDPA policy<{'arm64': 'y'}> +CONFIG_MLX5_VDPA_NET policy<{'arm64': 'm'}> +CONFIG_MLX5_VDPA_STEERING_DEBUG policy<{'arm64': 'y'}> +CONFIG_MLX5_VFIO_PCI policy<{'arm64': 'm'}> +CONFIG_MLX90614 policy<{'arm64': 'm'}> +CONFIG_MLX90632 policy<{'arm64': 'm'}> +CONFIG_MLX90635 policy<{'arm64': 'm'}> +CONFIG_MLXBF_BOOTCTL policy<{'arm64': 'm'}> +CONFIG_MLXBF_GIGE policy<{'arm64': 'm'}> +CONFIG_MLXBF_PMC policy<{'arm64': 'm'}> +CONFIG_MLXBF_TMFIFO policy<{'arm64': 'm'}> +CONFIG_MLXFW policy<{'arm64': 'm'}> +CONFIG_MLXREG_DPU policy<{'arm64': 'n'}> +CONFIG_MLXREG_HOTPLUG policy<{'arm64': 'm'}> +CONFIG_MLXREG_IO policy<{'arm64': 'm'}> +CONFIG_MLXREG_LC policy<{'arm64': 'm'}> +CONFIG_MLXSW_CORE policy<{'arm64': 'm'}> +CONFIG_MLXSW_CORE_HWMON policy<{'arm64': 'y'}> +CONFIG_MLXSW_CORE_THERMAL policy<{'arm64': 'y'}> +CONFIG_MLXSW_I2C policy<{'arm64': 'm'}> +CONFIG_MLXSW_MINIMAL policy<{'arm64': 'm'}> +CONFIG_MLXSW_PCI policy<{'arm64': 'm'}> +CONFIG_MLXSW_SPECTRUM policy<{'arm64': 'm'}> +CONFIG_MLXSW_SPECTRUM_DCB policy<{'arm64': 'y'}> +CONFIG_MLX_PLATFORM policy<{'arm64': 'n'}> +CONFIG_MLX_WDT policy<{'arm64': 'm'}> +CONFIG_MMA7455 policy<{'arm64': 'm'}> +CONFIG_MMA7455_I2C policy<{'arm64': 'm'}> +CONFIG_MMA7455_SPI policy<{'arm64': 'm'}> +CONFIG_MMA7660 policy<{'arm64': 'm'}> +CONFIG_MMA8452 policy<{'arm64': 'm'}> +CONFIG_MMA9551 policy<{'arm64': 'm'}> +CONFIG_MMA9551_CORE policy<{'arm64': 'm'}> +CONFIG_MMA9553 policy<{'arm64': 'm'}> +CONFIG_MMC policy<{'arm64': 'y'}> +CONFIG_MMC35240 policy<{'arm64': 'm'}> +CONFIG_MMC5633 policy<{'arm64': 'n'}> +CONFIG_MMC5983 policy<{'arm64': 'n'}> +CONFIG_MMC_ALCOR policy<{'arm64': 'm'}> +CONFIG_MMC_ARMMMCI policy<{'arm64': 'y'}> +CONFIG_MMC_BLOCK_MINORS policy<{'arm64': '8'}> +CONFIG_MMC_CAVIUM_THUNDERX policy<{'arm64': 'm'}> +CONFIG_MMC_CB710 policy<{'arm64': 'm'}> +CONFIG_MMC_CQHCI policy<{'arm64': 'm'}> +CONFIG_MMC_CRYPTO policy<{'arm64': 'y'}> +CONFIG_MMC_DEBUG policy<{'arm64': 'n'}> +CONFIG_MMC_DW policy<{'arm64': 'm'}> +CONFIG_MMC_DW_BLUEFIELD policy<{'arm64': 'm'}> +CONFIG_MMC_DW_EXYNOS policy<{'arm64': 'm'}> +CONFIG_MMC_DW_HI3798CV200 policy<{'arm64': 'm'}> +CONFIG_MMC_DW_HI3798MV200 policy<{'arm64': 'm'}> +CONFIG_MMC_DW_K3 policy<{'arm64': 'm'}> +CONFIG_MMC_DW_PCI policy<{'arm64': 'm'}> +CONFIG_MMC_DW_PLTFM policy<{'arm64': 'm'}> +CONFIG_MMC_DW_ROCKCHIP policy<{'arm64': 'm'}> +CONFIG_MMC_HSQ policy<{'arm64': 'm'}> +CONFIG_MMC_LITEX policy<{'arm64': 'm'}> +CONFIG_MMC_MESON_GX policy<{'arm64': 'm'}> +CONFIG_MMC_MESON_MX_SDIO policy<{'arm64': 'm'}> +CONFIG_MMC_MTK policy<{'arm64': 'm'}> +CONFIG_MMC_MXC policy<{'arm64': 'm'}> +CONFIG_MMC_OWL policy<{'arm64': 'm'}> +CONFIG_MMC_QCOM_DML policy<{'arm64': 'y'}> +CONFIG_MMC_REALTEK_PCI policy<{'arm64': 'm'}> +CONFIG_MMC_REALTEK_USB policy<{'arm64': 'm'}> +CONFIG_MMC_RICOH_MMC policy<{'arm64': 'y'}> +CONFIG_MMC_SDHCI_ACPI policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_AM654 policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_CADENCE policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_ESDHC_IMX policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_F_SDH30 policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_IO_ACCESSORS policy<{'arm64': 'y'}> +CONFIG_MMC_SDHCI_MILBEAUT policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_MSM policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_NPCM policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_OF_ARASAN policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_OF_AT91 policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_OF_DWCMSHC policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_OF_ESDHC policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_OF_MA35D1 policy<{'arm64': 'n'}> +CONFIG_MMC_SDHCI_OF_SPARX5 policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_PCI policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_PXAV3 policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_SPRD policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_TEGRA policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_UHS2 policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_XENON policy<{'arm64': 'm'}> +CONFIG_MMC_SDHI policy<{'arm64': 'm'}> +CONFIG_MMC_SDHI_INTERNAL_DMAC policy<{'arm64': 'm'}> +CONFIG_MMC_SDHI_SYS_DMAC policy<{'arm64': 'm'}> +CONFIG_MMC_SDRICOH_CS policy<{'arm64': 'n'}> +CONFIG_MMC_SH_MMCIF policy<{'arm64': 'm'}> +CONFIG_MMC_SPI policy<{'arm64': 'm'}> +CONFIG_MMC_STM32_SDMMC policy<{'arm64': 'y'}> +CONFIG_MMC_SUNXI policy<{'arm64': 'm'}> +CONFIG_MMC_TEST policy<{'arm64': 'n'}> +CONFIG_MMC_TIFM_SD policy<{'arm64': 'm'}> +CONFIG_MMC_TMIO_CORE policy<{'arm64': 'm'}> +CONFIG_MMC_TOSHIBA_PCI policy<{'arm64': 'm'}> +CONFIG_MMC_USDHI6ROL0 policy<{'arm64': 'm'}> +CONFIG_MMC_USHC policy<{'arm64': 'm'}> +CONFIG_MMC_VIA_SDMMC policy<{'arm64': 'm'}> +CONFIG_MMC_VUB300 policy<{'arm64': 'm'}> +CONFIG_MMU policy<{'arm64': 'y'}> +CONFIG_MMU_GATHER_RCU_TABLE_FREE policy<{'arm64': 'y'}> +CONFIG_MMU_GATHER_TABLE_FREE policy<{'arm64': 'y'}> +CONFIG_MMU_LAZY_TLB_REFCOUNT policy<{'arm64': 'y'}> +CONFIG_MMU_NOTIFIER policy<{'arm64': 'y'}> +CONFIG_MM_ID policy<{'arm64': 'y'}> +CONFIG_MODPROBE_PATH policy<{'arm64': '"/sbin/modprobe"'}> +CONFIG_MODULES policy<{'arm64': 'y'}> +CONFIG_MODULES_TREE_LOOKUP policy<{'arm64': 'y'}> +CONFIG_MODULES_USE_ELF_RELA policy<{'arm64': 'y'}> +CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS policy<{'arm64': 'n'}> +CONFIG_MODULE_COMPRESS policy<{'arm64': 'y'}> +CONFIG_MODULE_COMPRESS_ALL policy<{'arm64': 'y'}> +CONFIG_MODULE_COMPRESS_GZIP policy<{'arm64': 'n'}> +CONFIG_MODULE_COMPRESS_XZ policy<{'arm64': 'n'}> +CONFIG_MODULE_DEBUG policy<{'arm64': 'n'}> +CONFIG_MODULE_DECOMPRESS policy<{'arm64': 'y'}> +CONFIG_MODULE_FORCE_LOAD policy<{'arm64': 'n'}> +CONFIG_MODULE_FORCE_UNLOAD policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG policy<{'arm64': 'y'}> +CONFIG_MODULE_SIG_ALL policy<{'arm64': 'y'}> +CONFIG_MODULE_SIG_FORCE policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG_FORMAT policy<{'arm64': 'y'}> +CONFIG_MODULE_SIG_HASH policy<{'arm64': '"sha512"'}> +CONFIG_MODULE_SIG_KEY policy<{'arm64': '"certs/signing_key.pem"'}> +CONFIG_MODULE_SIG_KEY_TYPE_ECDSA policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_44 policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_65 policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_87 policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_RSA policy<{'arm64': 'y'}> +CONFIG_MODULE_SIG_SHA256 policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG_SHA384 policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG_SHA3_256 policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG_SHA3_384 policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG_SHA3_512 policy<{'arm64': 'n'}> +CONFIG_MODULE_SIG_SHA512 policy<{'arm64': 'y'}> +CONFIG_MODULE_SRCVERSION_ALL policy<{'arm64': 'y'}> +CONFIG_MODULE_UNLOAD policy<{'arm64': 'y'}> +CONFIG_MODULE_UNLOAD_TAINT_TRACKING policy<{'arm64': 'n'}> +CONFIG_MOST policy<{'arm64': 'm'}> +CONFIG_MOST_CDEV policy<{'arm64': 'm'}> +CONFIG_MOST_COMPONENTS policy<{'arm64': 'm'}> +CONFIG_MOST_DIM2 policy<{'arm64': 'm'}> +CONFIG_MOST_NET policy<{'arm64': 'm'}> +CONFIG_MOST_SND policy<{'arm64': 'm'}> +CONFIG_MOST_USB_HDM policy<{'arm64': 'm'}> +CONFIG_MOST_VIDEO policy<{'arm64': 'm'}> +CONFIG_MOTORCOMM_PHY policy<{'arm64': 'm'}> +CONFIG_MOUSE_APPLETOUCH policy<{'arm64': 'm'}> +CONFIG_MOUSE_BCM5974 policy<{'arm64': 'm'}> +CONFIG_MOUSE_CYAPA policy<{'arm64': 'm'}> +CONFIG_MOUSE_ELAN_I2C policy<{'arm64': 'm'}> +CONFIG_MOUSE_ELAN_I2C_I2C policy<{'arm64': 'y'}> +CONFIG_MOUSE_ELAN_I2C_SMBUS policy<{'arm64': 'y'}> +CONFIG_MOUSE_GPIO policy<{'arm64': 'm'}> +CONFIG_MOUSE_PS2 policy<{'arm64': 'm'}> +CONFIG_MOUSE_PS2_ALPS policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_BYD policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_CYPRESS policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_ELANTECH policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_ELANTECH_SMBUS policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_FOCALTECH policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_LOGIPS2PP policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_SENTELIC policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_SMBUS policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_SYNAPTICS policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_TOUCHKIT policy<{'arm64': 'y'}> +CONFIG_MOUSE_PS2_TRACKPOINT policy<{'arm64': 'y'}> +CONFIG_MOUSE_SERIAL policy<{'arm64': 'm'}> +CONFIG_MOUSE_SYNAPTICS_I2C policy<{'arm64': 'm'}> +CONFIG_MOUSE_SYNAPTICS_USB policy<{'arm64': 'm'}> +CONFIG_MOUSE_VSXXXAA policy<{'arm64': 'm'}> +CONFIG_MOXA_INTELLIO policy<{'arm64': 'm'}> +CONFIG_MOXA_SMARTIO policy<{'arm64': 'm'}> +CONFIG_MOXTET policy<{'arm64': 'm'}> +CONFIG_MP2629_ADC policy<{'arm64': 'm'}> +CONFIG_MPILIB policy<{'arm64': 'y'}> +CONFIG_MPL115 policy<{'arm64': 'm'}> +CONFIG_MPL115_I2C policy<{'arm64': 'm'}> +CONFIG_MPL115_SPI policy<{'arm64': 'm'}> +CONFIG_MPL3115 policy<{'arm64': 'm'}> +CONFIG_MPLS policy<{'arm64': 'y'}> +CONFIG_MPLS_IPTUNNEL policy<{'arm64': 'm'}> +CONFIG_MPLS_ROUTING policy<{'arm64': 'm'}> +CONFIG_MPRLS0025PA policy<{'arm64': 'm'}> +CONFIG_MPRLS0025PA_I2C policy<{'arm64': 'm'}> +CONFIG_MPRLS0025PA_SPI policy<{'arm64': 'm'}> +CONFIG_MPTCP policy<{'arm64': 'y'}> +CONFIG_MPTCP_IPV6 policy<{'arm64': 'y'}> +CONFIG_MPU3050 policy<{'arm64': 'm'}> +CONFIG_MPU3050_I2C policy<{'arm64': 'm'}> +CONFIG_MQ_IOSCHED_DEADLINE policy<{'arm64': 'y'}> +CONFIG_MQ_IOSCHED_KYBER policy<{'arm64': 'm'}> +CONFIG_MRP policy<{'arm64': 'm'}> +CONFIG_MS5611 policy<{'arm64': 'm'}> +CONFIG_MS5611_I2C policy<{'arm64': 'm'}> +CONFIG_MS5611_SPI policy<{'arm64': 'm'}> +CONFIG_MS5637 policy<{'arm64': 'm'}> +CONFIG_MSA311 policy<{'arm64': 'm'}> +CONFIG_MSCC_OCELOT_SWITCH policy<{'arm64': 'm'}> +CONFIG_MSCC_OCELOT_SWITCH_LIB policy<{'arm64': 'm'}> +CONFIG_MSDOS_FS policy<{'arm64': 'm'}> +CONFIG_MSDOS_PARTITION policy<{'arm64': 'y'}> +CONFIG_MSE102X policy<{'arm64': 'm'}> +CONFIG_MSM_GCC_8916 policy<{'arm64': 'y'}> +CONFIG_MSM_GCC_8917 policy<{'arm64': 'm'}> +CONFIG_MSM_GCC_8939 policy<{'arm64': 'm'}> +CONFIG_MSM_GCC_8953 policy<{'arm64': 'm'}> +CONFIG_MSM_GCC_8976 policy<{'arm64': 'm'}> +CONFIG_MSM_GCC_8994 policy<{'arm64': 'm'}> +CONFIG_MSM_GCC_8996 policy<{'arm64': 'm'}> +CONFIG_MSM_GCC_8998 policy<{'arm64': 'm'}> +CONFIG_MSM_GPUCC_8998 policy<{'arm64': 'm'}> +CONFIG_MSM_MMCC_8994 policy<{'arm64': 'm'}> +CONFIG_MSM_MMCC_8996 policy<{'arm64': 'm'}> +CONFIG_MSM_MMCC_8998 policy<{'arm64': 'm'}> +CONFIG_MSPRO_BLOCK policy<{'arm64': 'm'}> +CONFIG_MST_IRQ policy<{'arm64': 'y'}> +CONFIG_MS_BLOCK policy<{'arm64': 'm'}> +CONFIG_MT7601U policy<{'arm64': 'm'}> +CONFIG_MT7603E policy<{'arm64': 'm'}> +CONFIG_MT7615E policy<{'arm64': 'm'}> +CONFIG_MT7615_COMMON policy<{'arm64': 'm'}> +CONFIG_MT7622_WMAC policy<{'arm64': 'y'}> +CONFIG_MT7663S policy<{'arm64': 'm'}> +CONFIG_MT7663U policy<{'arm64': 'm'}> +CONFIG_MT7663_USB_SDIO_COMMON policy<{'arm64': 'm'}> +CONFIG_MT76_CONNAC_LIB policy<{'arm64': 'm'}> +CONFIG_MT76_CORE policy<{'arm64': 'm'}> +CONFIG_MT76_LEDS policy<{'arm64': 'y'}> +CONFIG_MT76_SDIO policy<{'arm64': 'm'}> +CONFIG_MT76_USB policy<{'arm64': 'm'}> +CONFIG_MT76x02_LIB policy<{'arm64': 'm'}> +CONFIG_MT76x02_USB policy<{'arm64': 'm'}> +CONFIG_MT76x0E policy<{'arm64': 'm'}> +CONFIG_MT76x0U policy<{'arm64': 'm'}> +CONFIG_MT76x0_COMMON policy<{'arm64': 'm'}> +CONFIG_MT76x2E policy<{'arm64': 'm'}> +CONFIG_MT76x2U policy<{'arm64': 'm'}> +CONFIG_MT76x2_COMMON policy<{'arm64': 'm'}> +CONFIG_MT7915E policy<{'arm64': 'm'}> +CONFIG_MT7921E policy<{'arm64': 'm'}> +CONFIG_MT7921S policy<{'arm64': 'm'}> +CONFIG_MT7921U policy<{'arm64': 'm'}> +CONFIG_MT7921_COMMON policy<{'arm64': 'm'}> +CONFIG_MT7925E policy<{'arm64': 'm'}> +CONFIG_MT7925U policy<{'arm64': 'm'}> +CONFIG_MT7925_COMMON policy<{'arm64': 'm'}> +CONFIG_MT792x_LIB policy<{'arm64': 'm'}> +CONFIG_MT792x_USB policy<{'arm64': 'm'}> +CONFIG_MT798X_WMAC policy<{'arm64': 'y'}> +CONFIG_MT7996E policy<{'arm64': 'm'}> +CONFIG_MTDRAM_ERASE_SIZE policy<{'arm64': '128'}> +CONFIG_MTDRAM_TOTAL_SIZE policy<{'arm64': '4096'}> +CONFIG_MTD_ABSENT policy<{'arm64': 'm'}> +CONFIG_MTD_AFS_PARTS policy<{'arm64': 'm'}> +CONFIG_MTD_BLKDEVS policy<{'arm64': 'm'}> +CONFIG_MTD_BLOCK2MTD policy<{'arm64': 'm'}> +CONFIG_MTD_BLOCK_RO policy<{'arm64': 'm'}> +CONFIG_MTD_CFI policy<{'arm64': 'm'}> +CONFIG_MTD_CFI_ADV_OPTIONS policy<{'arm64': 'y'}> +CONFIG_MTD_CFI_AMDSTD policy<{'arm64': 'm'}> +CONFIG_MTD_CFI_BE_BYTE_SWAP policy<{'arm64': 'n'}> +CONFIG_MTD_CFI_GEOMETRY policy<{'arm64': 'n'}> +CONFIG_MTD_CFI_I1 policy<{'arm64': 'y'}> +CONFIG_MTD_CFI_I2 policy<{'arm64': 'y'}> +CONFIG_MTD_CFI_INTELEXT policy<{'arm64': 'm'}> +CONFIG_MTD_CFI_LE_BYTE_SWAP policy<{'arm64': 'n'}> +CONFIG_MTD_CFI_NOSWAP policy<{'arm64': 'y'}> +CONFIG_MTD_CFI_STAA policy<{'arm64': 'm'}> +CONFIG_MTD_CFI_UTIL policy<{'arm64': 'm'}> +CONFIG_MTD_CMDLINE_PARTS policy<{'arm64': 'm'}> +CONFIG_MTD_COMPLEX_MAPPINGS policy<{'arm64': 'y'}> +CONFIG_MTD_DATAFLASH policy<{'arm64': 'm'}> +CONFIG_MTD_DATAFLASH_OTP policy<{'arm64': 'y'}> +CONFIG_MTD_DATAFLASH_WRITE_VERIFY policy<{'arm64': 'n'}> +CONFIG_MTD_DOCG3 policy<{'arm64': 'n'}> +CONFIG_MTD_GEN_PROBE policy<{'arm64': 'm'}> +CONFIG_MTD_HYPERBUS policy<{'arm64': 'm'}> +CONFIG_MTD_INTEL_DG policy<{'arm64': 'n'}> +CONFIG_MTD_JEDECPROBE policy<{'arm64': 'm'}> +CONFIG_MTD_LPDDR policy<{'arm64': 'm'}> +CONFIG_MTD_MAP_BANK_WIDTH_1 policy<{'arm64': 'y'}> +CONFIG_MTD_MAP_BANK_WIDTH_2 policy<{'arm64': 'y'}> +CONFIG_MTD_MAP_BANK_WIDTH_4 policy<{'arm64': 'y'}> +CONFIG_MTD_MCHP23K256 policy<{'arm64': 'm'}> +CONFIG_MTD_MCHP48L640 policy<{'arm64': 'm'}> +CONFIG_MTD_MTDRAM policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_ARASAN policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_BRCMNAND policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_BCM63XX policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_BCMBCA policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_BRCMSTB policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_IPROC policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_CADENCE policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_CAFE policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_CORE policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_DENALI policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_DENALI_DT policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_DENALI_PCI policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_DISKONCHIP policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE policy<{'arm64': 'n'}> +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS policy<{'arm64': '0'}> +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED policy<{'arm64': 'n'}> +CONFIG_MTD_NAND_ECC policy<{'arm64': 'y'}> +CONFIG_MTD_NAND_ECC_MEDIATEK policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_ECC_MXIC policy<{'arm64': 'y'}> +CONFIG_MTD_NAND_ECC_SW_BCH policy<{'arm64': 'y'}> +CONFIG_MTD_NAND_ECC_SW_HAMMING policy<{'arm64': 'y'}> +CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC policy<{'arm64': 'n'}> +CONFIG_MTD_NAND_FSL_IFC policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_GPIO policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_GPMI_NAND policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_HISI504 policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_INTEL_LGM policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_MARVELL policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_MESON policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_MTK policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_MXC policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_MXIC policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_NANDSIM policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_NUVOTON_MA35 policy<{'arm64': 'n'}> +CONFIG_MTD_NAND_OMAP2 policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_OMAP_BCH policy<{'arm64': 'y'}> +CONFIG_MTD_NAND_OMAP_BCH_BUILD policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_PLATFORM policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_QCOM policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_RENESAS policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_RICOH policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_ROCKCHIP policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_STM32_FMC2 policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_SUNXI policy<{'arm64': 'n'}> +CONFIG_MTD_NAND_TEGRA policy<{'arm64': 'm'}> +CONFIG_MTD_ONENAND policy<{'arm64': 'm'}> +CONFIG_MTD_ONENAND_2X_PROGRAM policy<{'arm64': 'y'}> +CONFIG_MTD_ONENAND_GENERIC policy<{'arm64': 'm'}> +CONFIG_MTD_ONENAND_OTP policy<{'arm64': 'n'}> +CONFIG_MTD_ONENAND_VERIFY_WRITE policy<{'arm64': 'y'}> +CONFIG_MTD_OOPS policy<{'arm64': 'm'}> +CONFIG_MTD_OTP policy<{'arm64': 'n'}> +CONFIG_MTD_PARSER_TRX policy<{'arm64': 'm'}> +CONFIG_MTD_PARTITIONED_MASTER policy<{'arm64': 'n'}> +CONFIG_MTD_PCI policy<{'arm64': 'm'}> +CONFIG_MTD_PCMCIA policy<{'arm64': 'n'}> +CONFIG_MTD_PHRAM policy<{'arm64': 'm'}> +CONFIG_MTD_PHYSMAP policy<{'arm64': 'm'}> +CONFIG_MTD_PHYSMAP_COMPAT policy<{'arm64': 'n'}> +CONFIG_MTD_PHYSMAP_GEMINI policy<{'arm64': 'y'}> +CONFIG_MTD_PHYSMAP_GPIO_ADDR policy<{'arm64': 'y'}> +CONFIG_MTD_PHYSMAP_OF policy<{'arm64': 'y'}> +CONFIG_MTD_PHYSMAP_VERSATILE policy<{'arm64': 'y'}> +CONFIG_MTD_PLATRAM policy<{'arm64': 'm'}> +CONFIG_MTD_PMC551 policy<{'arm64': 'm'}> +CONFIG_MTD_PMC551_BUGFIX policy<{'arm64': 'n'}> +CONFIG_MTD_PMC551_DEBUG policy<{'arm64': 'n'}> +CONFIG_MTD_PSTORE policy<{'arm64': 'm'}> +CONFIG_MTD_QCOMSMEM_PARTS policy<{'arm64': 'm'}> +CONFIG_MTD_QINFO_PROBE policy<{'arm64': 'm'}> +CONFIG_MTD_RAM policy<{'arm64': 'm'}> +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK policy<{'arm64': '-1'}> +CONFIG_MTD_REDBOOT_PARTS policy<{'arm64': 'm'}> +CONFIG_MTD_REDBOOT_PARTS_READONLY policy<{'arm64': 'n'}> +CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED policy<{'arm64': 'n'}> +CONFIG_MTD_ROM policy<{'arm64': 'm'}> +CONFIG_MTD_SLRAM policy<{'arm64': 'm'}> +CONFIG_MTD_SM_COMMON policy<{'arm64': 'm'}> +CONFIG_MTD_SPI_NAND policy<{'arm64': 'm'}> +CONFIG_MTD_SPI_NOR policy<{'arm64': 'm'}> +CONFIG_MTD_SPI_NOR_SWP_DISABLE policy<{'arm64': 'n'}> +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE policy<{'arm64': 'y'}> +CONFIG_MTD_SPI_NOR_SWP_KEEP policy<{'arm64': 'n'}> +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS policy<{'arm64': 'y'}> +CONFIG_MTD_SST25L policy<{'arm64': 'm'}> +CONFIG_MTD_SWAP policy<{'arm64': 'm'}> +CONFIG_MTD_TESTS policy<{'arm64': 'n'}> +CONFIG_MTD_UBI policy<{'arm64': 'm'}> +CONFIG_MTD_UBI_BEB_LIMIT policy<{'arm64': '20'}> +CONFIG_MTD_UBI_BLOCK policy<{'arm64': 'y'}> +CONFIG_MTD_UBI_FASTMAP policy<{'arm64': 'y'}> +CONFIG_MTD_UBI_GLUEBI policy<{'arm64': 'm'}> +CONFIG_MTD_UBI_NVMEM policy<{'arm64': 'm'}> +CONFIG_MTD_UBI_WL_THRESHOLD policy<{'arm64': '4096'}> +CONFIG_MTK_ADSP_IPC policy<{'arm64': 'm'}> +CONFIG_MTK_ADSP_MBOX policy<{'arm64': 'm'}> +CONFIG_MTK_CMDQ policy<{'arm64': 'm'}> +CONFIG_MTK_CMDQ_MBOX policy<{'arm64': 'm'}> +CONFIG_MTK_CPUX_TIMER policy<{'arm64': 'y'}> +CONFIG_MTK_CQDMA policy<{'arm64': 'm'}> +CONFIG_MTK_DEVAPC policy<{'arm64': 'm'}> +CONFIG_MTK_DVFSRC policy<{'arm64': 'm'}> +CONFIG_MTK_GPUEB_MBOX policy<{'arm64': 'n'}> +CONFIG_MTK_HSDMA policy<{'arm64': 'm'}> +CONFIG_MTK_INFRACFG policy<{'arm64': 'y'}> +CONFIG_MTK_IOMMU policy<{'arm64': 'm'}> +CONFIG_MTK_LVTS_THERMAL policy<{'arm64': 'm'}> +CONFIG_MTK_LVTS_THERMAL_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_MTK_MFG_PM_DOMAIN policy<{'arm64': 'y'}> +CONFIG_MTK_MMSYS policy<{'arm64': 'm'}> +CONFIG_MTK_NET_PHYLIB policy<{'arm64': 'm'}> +CONFIG_MTK_PMIC_WRAP policy<{'arm64': 'm'}> +CONFIG_MTK_REGULATOR_COUPLER policy<{'arm64': 'y'}> +CONFIG_MTK_SCP policy<{'arm64': 'm'}> +CONFIG_MTK_SCPSYS policy<{'arm64': 'y'}> +CONFIG_MTK_SCPSYS_PM_DOMAINS policy<{'arm64': 'y'}> +CONFIG_MTK_SMI policy<{'arm64': 'm'}> +CONFIG_MTK_SOCINFO policy<{'arm64': 'm'}> +CONFIG_MTK_SOC_THERMAL policy<{'arm64': 'm'}> +CONFIG_MTK_SVS policy<{'arm64': 'm'}> +CONFIG_MTK_T7XX policy<{'arm64': 'm'}> +CONFIG_MTK_THERMAL policy<{'arm64': 'm'}> +CONFIG_MTK_TIMER policy<{'arm64': 'y'}> +CONFIG_MTK_UART_APDMA policy<{'arm64': 'm'}> +CONFIG_MTK_VCP_MBOX policy<{'arm64': 'n'}> +CONFIG_MULTIPLEXER policy<{'arm64': 'y'}> +CONFIG_MULTIUSER policy<{'arm64': 'y'}> +CONFIG_MUSB_PIO_ONLY policy<{'arm64': 'y'}> +CONFIG_MUTEX_SPIN_ON_OWNER policy<{'arm64': 'y'}> +CONFIG_MUX_ADG792A policy<{'arm64': 'm'}> +CONFIG_MUX_ADGS1408 policy<{'arm64': 'm'}> +CONFIG_MUX_CORE policy<{'arm64': 'n'}> +CONFIG_MUX_GPIO policy<{'arm64': 'm'}> +CONFIG_MUX_MMIO policy<{'arm64': 'm'}> +CONFIG_MVEBU_GICP policy<{'arm64': 'y'}> +CONFIG_MVEBU_ICU policy<{'arm64': 'y'}> +CONFIG_MVEBU_ODMI policy<{'arm64': 'y'}> +CONFIG_MVEBU_PIC policy<{'arm64': 'y'}> +CONFIG_MVEBU_SEI policy<{'arm64': 'y'}> +CONFIG_MVMDIO policy<{'arm64': 'm'}> +CONFIG_MVNETA policy<{'arm64': 'm'}> +CONFIG_MVPP2 policy<{'arm64': 'm'}> +CONFIG_MVPP2_PTP policy<{'arm64': 'y'}> +CONFIG_MV_XOR policy<{'arm64': 'y'}> +CONFIG_MV_XOR_V2 policy<{'arm64': 'y'}> +CONFIG_MWIFIEX policy<{'arm64': 'm'}> +CONFIG_MWIFIEX_PCIE policy<{'arm64': 'm'}> +CONFIG_MWIFIEX_SDIO policy<{'arm64': 'm'}> +CONFIG_MWIFIEX_USB policy<{'arm64': 'm'}> +CONFIG_MWL8K policy<{'arm64': 'm'}> +CONFIG_MXC4005 policy<{'arm64': 'm'}> +CONFIG_MXC6255 policy<{'arm64': 'm'}> +CONFIG_MXC_CLK policy<{'arm64': 'y'}> +CONFIG_MXC_CLK_SCU policy<{'arm64': 'y'}> +CONFIG_MXS_DMA policy<{'arm64': 'y'}> +CONFIG_MYRI10GE policy<{'arm64': 'm'}> +CONFIG_NAMESPACES policy<{'arm64': 'y'}> +CONFIG_NATIONAL_PHY policy<{'arm64': 'm'}> +CONFIG_NATSEMI policy<{'arm64': 'm'}> +CONFIG_NAU7802 policy<{'arm64': 'm'}> +CONFIG_NCN26000_PHY policy<{'arm64': 'm'}> +CONFIG_NCSI_OEM_CMD_GET_MAC policy<{'arm64': 'y'}> +CONFIG_NCSI_OEM_CMD_KEEP_PHY policy<{'arm64': 'n'}> +CONFIG_NCT7201 policy<{'arm64': 'n'}> +CONFIG_NDC_DIS_DYNAMIC_CACHING policy<{'arm64': 'y'}> +CONFIG_ND_BTT policy<{'arm64': 'm'}> +CONFIG_ND_CLAIM policy<{'arm64': 'y'}> +CONFIG_ND_PFN policy<{'arm64': 'm'}> +CONFIG_NE2K_PCI policy<{'arm64': 'm'}> +CONFIG_NEED_DMA_MAP_STATE policy<{'arm64': 'y'}> +CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP policy<{'arm64': 'y'}> +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK policy<{'arm64': 'y'}> +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK policy<{'arm64': 'y'}> +CONFIG_NEED_SG_DMA_FLAGS policy<{'arm64': 'y'}> +CONFIG_NEED_SG_DMA_LENGTH policy<{'arm64': 'y'}> +CONFIG_NEED_TASKS_RCU policy<{'arm64': 'y'}> +CONFIG_NET policy<{'arm64': 'y'}> +CONFIG_NETCONSOLE policy<{'arm64': 'm'}> +CONFIG_NETCONSOLE_DYNAMIC policy<{'arm64': 'y'}> +CONFIG_NETCONSOLE_EXTENDED_LOG policy<{'arm64': 'n'}> +CONFIG_NETDEVICES policy<{'arm64': 'y'}> +CONFIG_NETDEVSIM policy<{'arm64': 'm'}> +CONFIG_NETDEV_NOTIFIER_ERROR_INJECT policy<{'arm64': 'n'}> +CONFIG_NETFILTER policy<{'arm64': 'y'}> +CONFIG_NETFILTER_ADVANCED policy<{'arm64': 'y'}> +CONFIG_NETFILTER_BPF_LINK policy<{'arm64': 'y'}> +CONFIG_NETFILTER_CONNCOUNT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_EGRESS policy<{'arm64': 'y'}> +CONFIG_NETFILTER_FAMILY_ARP policy<{'arm64': 'y'}> +CONFIG_NETFILTER_FAMILY_BRIDGE policy<{'arm64': 'y'}> +CONFIG_NETFILTER_INGRESS policy<{'arm64': 'y'}> +CONFIG_NETFILTER_NETLINK policy<{'arm64': 'y'}> +CONFIG_NETFILTER_NETLINK_ACCT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_NETLINK_GLUE_CT policy<{'arm64': 'y'}> +CONFIG_NETFILTER_NETLINK_HOOK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_NETLINK_LOG policy<{'arm64': 'm'}> +CONFIG_NETFILTER_NETLINK_OSF policy<{'arm64': 'm'}> +CONFIG_NETFILTER_NETLINK_QUEUE policy<{'arm64': 'm'}> +CONFIG_NETFILTER_SKIP_EGRESS policy<{'arm64': 'y'}> +CONFIG_NETFILTER_SYNPROXY policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XTABLES policy<{'arm64': 'y'}> +CONFIG_NETFILTER_XTABLES_COMPAT policy<{'arm64': 'y'}> +CONFIG_NETFILTER_XTABLES_LEGACY policy<{'arm64': 'y'}> +CONFIG_NETFILTER_XT_CONNMARK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MARK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_BPF policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CGROUP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CLUSTER policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_COMMENT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNBYTES policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNLABEL policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNMARK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNTRACK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CPU policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_DCCP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_DEVGROUP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_DSCP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_ECN policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_ESP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_HELPER policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_HL policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_IPCOMP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_IPRANGE policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_IPVS policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_L2TP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_LENGTH policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_LIMIT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_MAC policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_MARK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_MULTIPORT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_NFACCT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_OSF policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_OWNER policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_PHYSDEV policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_PKTTYPE policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_POLICY policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_QUOTA policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_RATEEST policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_REALM policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_RECENT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_SCTP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_SOCKET policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_STATE policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_STATISTIC policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_STRING policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_TCPMSS policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_TIME policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_MATCH_U32 policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_NAT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_SET policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_AUDIT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CHECKSUM policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CLASSIFY policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CONNMARK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_DSCP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_HL policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_HMARK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_IDLETIMER policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_LED policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_LOG policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_MARK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_MASQUERADE policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NETMAP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NFLOG policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NFQUEUE policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_RATEEST policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_REDIRECT policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_SECMARK policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TCPMSS policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TEE policy<{'arm64': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TPROXY policy<{'arm64': 'm'}> +CONFIG_NETFS_DEBUG policy<{'arm64': 'y'}> +CONFIG_NETFS_STATS policy<{'arm64': 'y'}> +CONFIG_NETFS_SUPPORT policy<{'arm64': 'm'}> +CONFIG_NETKIT policy<{'arm64': 'y'}> +CONFIG_NETLABEL policy<{'arm64': 'y'}> +CONFIG_NETLINK_DIAG policy<{'arm64': 'm'}> +CONFIG_NETPOLL policy<{'arm64': 'y'}> +CONFIG_NETWORK_FILESYSTEMS policy<{'arm64': 'y'}> +CONFIG_NETWORK_SECMARK policy<{'arm64': 'y'}> +CONFIG_NETXEN_NIC policy<{'arm64': 'm'}> +CONFIG_NET_9P_DEBUG policy<{'arm64': 'n'}> +CONFIG_NET_9P_FD policy<{'arm64': 'm'}> +CONFIG_NET_9P_RDMA policy<{'arm64': 'm'}> +CONFIG_NET_9P_USBG policy<{'arm64': 'n'}> +CONFIG_NET_9P_VIRTIO policy<{'arm64': 'm'}> +CONFIG_NET_9P_XEN policy<{'arm64': 'm'}> +CONFIG_NET_ACT_BPF policy<{'arm64': 'm'}> +CONFIG_NET_ACT_CONNMARK policy<{'arm64': 'm'}> +CONFIG_NET_ACT_CSUM policy<{'arm64': 'm'}> +CONFIG_NET_ACT_CT policy<{'arm64': 'm'}> +CONFIG_NET_ACT_CTINFO policy<{'arm64': 'm'}> +CONFIG_NET_ACT_GACT policy<{'arm64': 'm'}> +CONFIG_NET_ACT_GATE policy<{'arm64': 'm'}> +CONFIG_NET_ACT_IFE policy<{'arm64': 'n'}> +CONFIG_NET_ACT_MIRRED policy<{'arm64': 'm'}> +CONFIG_NET_ACT_MPLS policy<{'arm64': 'm'}> +CONFIG_NET_ACT_NAT policy<{'arm64': 'm'}> +CONFIG_NET_ACT_PEDIT policy<{'arm64': 'm'}> +CONFIG_NET_ACT_POLICE policy<{'arm64': 'm'}> +CONFIG_NET_ACT_SAMPLE policy<{'arm64': 'm'}> +CONFIG_NET_ACT_SIMP policy<{'arm64': 'm'}> +CONFIG_NET_ACT_SKBEDIT policy<{'arm64': 'm'}> +CONFIG_NET_ACT_SKBMOD policy<{'arm64': 'm'}> +CONFIG_NET_ACT_TUNNEL_KEY policy<{'arm64': 'm'}> +CONFIG_NET_ACT_VLAN policy<{'arm64': 'm'}> +CONFIG_NET_CLS policy<{'arm64': 'y'}> +CONFIG_NET_CLS_ACT policy<{'arm64': 'y'}> +CONFIG_NET_CLS_BASIC policy<{'arm64': 'm'}> +CONFIG_NET_CLS_BPF policy<{'arm64': 'm'}> +CONFIG_NET_CLS_CGROUP policy<{'arm64': 'm'}> +CONFIG_NET_CLS_FLOW policy<{'arm64': 'm'}> +CONFIG_NET_CLS_FLOWER policy<{'arm64': 'm'}> +CONFIG_NET_CLS_FW policy<{'arm64': 'm'}> +CONFIG_NET_CLS_MATCHALL policy<{'arm64': 'm'}> +CONFIG_NET_CLS_ROUTE4 policy<{'arm64': 'm'}> +CONFIG_NET_CLS_U32 policy<{'arm64': 'm'}> +CONFIG_NET_CORE policy<{'arm64': 'y'}> +CONFIG_NET_CRC32C policy<{'arm64': 'y'}> +CONFIG_NET_DEVLINK policy<{'arm64': 'y'}> +CONFIG_NET_DEVMEM policy<{'arm64': 'y'}> +CONFIG_NET_DEV_REFCNT_TRACKER policy<{'arm64': 'n'}> +CONFIG_NET_DSA policy<{'arm64': 'm'}> +CONFIG_NET_DSA_AR9331 policy<{'arm64': 'm'}> +CONFIG_NET_DSA_BCM_SF2 policy<{'arm64': 'm'}> +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK policy<{'arm64': 'm'}> +CONFIG_NET_DSA_KS8995 policy<{'arm64': 'n'}> +CONFIG_NET_DSA_LANTIQ_COMMON policy<{'arm64': 'm'}> +CONFIG_NET_DSA_LANTIQ_GSWIP policy<{'arm64': 'm'}> +CONFIG_NET_DSA_LOOP policy<{'arm64': 'n'}> +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MICROCHIP_KSZ_PTP policy<{'arm64': 'y'}> +CONFIG_NET_DSA_MICROCHIP_KSZ_SPI policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MSCC_FELIX policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MSCC_OCELOT_EXT policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MSCC_SEVILLE policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MT7530 policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MT7530_MDIO policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MT7530_MMIO policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MV88E6060 policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MV88E6XXX policy<{'arm64': 'm'}> +CONFIG_NET_DSA_MV88E6XXX_LEDS policy<{'arm64': 'y'}> +CONFIG_NET_DSA_MV88E6XXX_PTP policy<{'arm64': 'y'}> +CONFIG_NET_DSA_MXL862 policy<{'arm64': 'n'}> +CONFIG_NET_DSA_MXL_GSW1XX policy<{'arm64': 'n'}> +CONFIG_NET_DSA_NETC_SWITCH policy<{'arm64': 'n'}> +CONFIG_NET_DSA_QCA8K policy<{'arm64': 'm'}> +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT policy<{'arm64': 'y'}> +CONFIG_NET_DSA_REALTEK policy<{'arm64': 'm'}> +CONFIG_NET_DSA_REALTEK_MDIO policy<{'arm64': 'y'}> +CONFIG_NET_DSA_REALTEK_RTL8365MB policy<{'arm64': 'm'}> +CONFIG_NET_DSA_REALTEK_RTL8366RB policy<{'arm64': 'm'}> +CONFIG_NET_DSA_REALTEK_RTL8366RB_LEDS policy<{'arm64': 'y'}> +CONFIG_NET_DSA_REALTEK_SMI policy<{'arm64': 'y'}> +CONFIG_NET_DSA_SJA1105 policy<{'arm64': 'm'}> +CONFIG_NET_DSA_SJA1105_PTP policy<{'arm64': 'y'}> +CONFIG_NET_DSA_SJA1105_TAS policy<{'arm64': 'y'}> +CONFIG_NET_DSA_SJA1105_VL policy<{'arm64': 'y'}> +CONFIG_NET_DSA_SMSC_LAN9303 policy<{'arm64': 'm'}> +CONFIG_NET_DSA_SMSC_LAN9303_I2C policy<{'arm64': 'm'}> +CONFIG_NET_DSA_SMSC_LAN9303_MDIO policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_AR9331 policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_COMMON policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_LEGACY policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_LEGACY_FCS policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_PREPEND policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_DSA policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_DSA_COMMON policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_EDSA policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_GSWIP policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_HELLCREEK policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_KSZ policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_LAN9303 policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_MTK policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_MXL_862XX policy<{'arm64': 'n'}> +CONFIG_NET_DSA_TAG_MXL_GSW1XX policy<{'arm64': 'n'}> +CONFIG_NET_DSA_TAG_NETC policy<{'arm64': 'n'}> +CONFIG_NET_DSA_TAG_NONE policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_OCELOT policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_OCELOT_8021Q policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_QCA policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_RTL4_A policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_RTL8_4 policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_RZN1_A5PSW policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_SJA1105 policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_TRAILER policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_VSC73XX_8021Q policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_XRS700X policy<{'arm64': 'm'}> +CONFIG_NET_DSA_TAG_YT921X policy<{'arm64': 'n'}> +CONFIG_NET_DSA_VITESSE_VSC73XX policy<{'arm64': 'm'}> +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM policy<{'arm64': 'm'}> +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI policy<{'arm64': 'm'}> +CONFIG_NET_DSA_XRS700X policy<{'arm64': 'm'}> +CONFIG_NET_DSA_XRS700X_I2C policy<{'arm64': 'm'}> +CONFIG_NET_DSA_XRS700X_MDIO policy<{'arm64': 'm'}> +CONFIG_NET_DSA_YT921X policy<{'arm64': 'n'}> +CONFIG_NET_EGRESS policy<{'arm64': 'y'}> +CONFIG_NET_EMATCH policy<{'arm64': 'y'}> +CONFIG_NET_EMATCH_CANID policy<{'arm64': 'm'}> +CONFIG_NET_EMATCH_CMP policy<{'arm64': 'm'}> +CONFIG_NET_EMATCH_IPSET policy<{'arm64': 'm'}> +CONFIG_NET_EMATCH_IPT policy<{'arm64': 'm'}> +CONFIG_NET_EMATCH_META policy<{'arm64': 'm'}> +CONFIG_NET_EMATCH_NBYTE policy<{'arm64': 'm'}> +CONFIG_NET_EMATCH_STACK policy<{'arm64': '32'}> +CONFIG_NET_EMATCH_TEXT policy<{'arm64': 'm'}> +CONFIG_NET_EMATCH_U32 policy<{'arm64': 'm'}> +CONFIG_NET_FAILOVER policy<{'arm64': 'y'}> +CONFIG_NET_FC policy<{'arm64': 'y'}> +CONFIG_NET_FLOW_LIMIT policy<{'arm64': 'y'}> +CONFIG_NET_FOU policy<{'arm64': 'm'}> +CONFIG_NET_FOU_IP_TUNNELS policy<{'arm64': 'y'}> +CONFIG_NET_HANDSHAKE policy<{'arm64': 'y'}> +CONFIG_NET_IEEE8021Q_HELPERS policy<{'arm64': 'y'}> +CONFIG_NET_IFE policy<{'arm64': 'm'}> +CONFIG_NET_INGRESS policy<{'arm64': 'y'}> +CONFIG_NET_IPGRE policy<{'arm64': 'm'}> +CONFIG_NET_IPGRE_BROADCAST policy<{'arm64': 'y'}> +CONFIG_NET_IPGRE_DEMUX policy<{'arm64': 'm'}> +CONFIG_NET_IPIP policy<{'arm64': 'm'}> +CONFIG_NET_IPVTI policy<{'arm64': 'm'}> +CONFIG_NET_IP_TUNNEL policy<{'arm64': 'm'}> +CONFIG_NET_KEY policy<{'arm64': 'm'}> +CONFIG_NET_KEY_MIGRATE policy<{'arm64': 'n'}> +CONFIG_NET_L3_MASTER_DEV policy<{'arm64': 'y'}> +CONFIG_NET_MPLS_GSO policy<{'arm64': 'm'}> +CONFIG_NET_NCSI policy<{'arm64': 'y'}> +CONFIG_NET_NS policy<{'arm64': 'y'}> +CONFIG_NET_NSH policy<{'arm64': 'm'}> +CONFIG_NET_NS_REFCNT_TRACKER policy<{'arm64': 'n'}> +CONFIG_NET_PKTGEN policy<{'arm64': 'm'}> +CONFIG_NET_POLL_CONTROLLER policy<{'arm64': 'y'}> +CONFIG_NET_PTP_CLASSIFY policy<{'arm64': 'y'}> +CONFIG_NET_REDIRECT policy<{'arm64': 'y'}> +CONFIG_NET_RX_BUSY_POLL policy<{'arm64': 'y'}> +CONFIG_NET_SCHED policy<{'arm64': 'y'}> +CONFIG_NET_SCH_CAKE policy<{'arm64': 'm'}> +CONFIG_NET_SCH_CBS policy<{'arm64': 'm'}> +CONFIG_NET_SCH_CHOKE policy<{'arm64': 'm'}> +CONFIG_NET_SCH_CODEL policy<{'arm64': 'm'}> +CONFIG_NET_SCH_DEFAULT policy<{'arm64': 'n'}> +CONFIG_NET_SCH_DRR policy<{'arm64': 'm'}> +CONFIG_NET_SCH_DUALPI2 policy<{'arm64': 'n'}> +CONFIG_NET_SCH_ETF policy<{'arm64': 'm'}> +CONFIG_NET_SCH_ETS policy<{'arm64': 'm'}> +CONFIG_NET_SCH_FIFO policy<{'arm64': 'y'}> +CONFIG_NET_SCH_FQ policy<{'arm64': 'm'}> +CONFIG_NET_SCH_FQ_CODEL policy<{'arm64': 'm'}> +CONFIG_NET_SCH_FQ_PIE policy<{'arm64': 'm'}> +CONFIG_NET_SCH_GRED policy<{'arm64': 'm'}> +CONFIG_NET_SCH_HFSC policy<{'arm64': 'm'}> +CONFIG_NET_SCH_HHF policy<{'arm64': 'm'}> +CONFIG_NET_SCH_HTB policy<{'arm64': 'm'}> +CONFIG_NET_SCH_INGRESS policy<{'arm64': 'm'}> +CONFIG_NET_SCH_MQPRIO policy<{'arm64': 'm'}> +CONFIG_NET_SCH_MQPRIO_LIB policy<{'arm64': 'm'}> +CONFIG_NET_SCH_MULTIQ policy<{'arm64': 'm'}> +CONFIG_NET_SCH_NETEM policy<{'arm64': 'm'}> +CONFIG_NET_SCH_PIE policy<{'arm64': 'm'}> +CONFIG_NET_SCH_PLUG policy<{'arm64': 'm'}> +CONFIG_NET_SCH_PRIO policy<{'arm64': 'm'}> +CONFIG_NET_SCH_QFQ policy<{'arm64': 'm'}> +CONFIG_NET_SCH_RED policy<{'arm64': 'm'}> +CONFIG_NET_SCH_SFB policy<{'arm64': 'm'}> +CONFIG_NET_SCH_SFQ policy<{'arm64': 'm'}> +CONFIG_NET_SCH_SKBPRIO policy<{'arm64': 'm'}> +CONFIG_NET_SCH_TAPRIO policy<{'arm64': 'm'}> +CONFIG_NET_SCH_TBF policy<{'arm64': 'm'}> +CONFIG_NET_SCH_TEQL policy<{'arm64': 'm'}> +CONFIG_NET_SELFTESTS policy<{'arm64': 'y'}> +CONFIG_NET_SHAPER policy<{'arm64': 'y'}> +CONFIG_NET_SOCK_MSG policy<{'arm64': 'y'}> +CONFIG_NET_TC_SKB_EXT policy<{'arm64': 'y'}> +CONFIG_NET_TEAM policy<{'arm64': 'm'}> +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP policy<{'arm64': 'm'}> +CONFIG_NET_TEAM_MODE_BROADCAST policy<{'arm64': 'm'}> +CONFIG_NET_TEAM_MODE_LOADBALANCE policy<{'arm64': 'm'}> +CONFIG_NET_TEAM_MODE_RANDOM policy<{'arm64': 'm'}> +CONFIG_NET_TEAM_MODE_ROUNDROBIN policy<{'arm64': 'm'}> +CONFIG_NET_TULIP policy<{'arm64': 'y'}> +CONFIG_NET_UDP_TUNNEL policy<{'arm64': 'm'}> +CONFIG_NET_VENDOR_3COM policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_8390 policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_ACTIONS policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_ADAPTEC policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_ADI policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_AGERE policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_AIROHA policy<{'arm64': 'n'}> +CONFIG_NET_VENDOR_ALACRITECH policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_ALIBABA policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_ALLWINNER policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_AMAZON policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_AMD policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_AQUANTIA policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_ARC policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_ASIX policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_ATHEROS policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_BROADCOM policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_BROCADE policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_CADENCE policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_CAVIUM policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_CHELSIO policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_CISCO policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_CORTINA policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_DAVICOM policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_DEC policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_DLINK policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_ENGLEDER policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_EZCHIP policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_FREESCALE policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_FUNGIBLE policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_GOOGLE policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_HISILICON policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_HUAWEI policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_I825XX policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_INTEL policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_LITEX policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_MARVELL policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_MEDIATEK policy<{'arm64': 'n'}> +CONFIG_NET_VENDOR_MELLANOX policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_META policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_MICREL policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_MICROCHIP policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_MICROSEMI policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_MICROSOFT policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_MUCSE policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_MYRI policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_NATSEMI policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_NETRONOME policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_NI policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_NVIDIA policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_OKI policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_PENSANDO policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_QLOGIC policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_QUALCOMM policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_RDC policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_REALTEK policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_RENESAS policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_ROCKER policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_SAMSUNG policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_SEEQ policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_SILAN policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_SIS policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_SMSC policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_SOCIONEXT policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_SOLARFLARE policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_STMICRO policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_SUN policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_SYNOPSYS policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_TEHUTI policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_TI policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_VERTEXCOM policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_VIA policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_WANGXUN policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_WIZNET policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_XILINX policy<{'arm64': 'y'}> +CONFIG_NET_VENDOR_XIRCOM policy<{'arm64': 'y'}> +CONFIG_NET_VRF policy<{'arm64': 'm'}> +CONFIG_NET_XGENE policy<{'arm64': 'm'}> +CONFIG_NET_XGENE_V2 policy<{'arm64': 'm'}> +CONFIG_NET_XGRESS policy<{'arm64': 'y'}> +CONFIG_NEW_LEDS policy<{'arm64': 'y'}> +CONFIG_NFC policy<{'arm64': 'm'}> +CONFIG_NFC_DIGITAL policy<{'arm64': 'm'}> +CONFIG_NFC_FDP policy<{'arm64': 'm'}> +CONFIG_NFC_FDP_I2C policy<{'arm64': 'm'}> +CONFIG_NFC_HCI policy<{'arm64': 'm'}> +CONFIG_NFC_MICROREAD policy<{'arm64': 'm'}> +CONFIG_NFC_MICROREAD_I2C policy<{'arm64': 'm'}> +CONFIG_NFC_MRVL policy<{'arm64': 'm'}> +CONFIG_NFC_MRVL_I2C policy<{'arm64': 'm'}> +CONFIG_NFC_MRVL_SPI policy<{'arm64': 'm'}> +CONFIG_NFC_MRVL_UART policy<{'arm64': 'm'}> +CONFIG_NFC_MRVL_USB policy<{'arm64': 'm'}> +CONFIG_NFC_NCI policy<{'arm64': 'm'}> +CONFIG_NFC_NCI_SPI policy<{'arm64': 'm'}> +CONFIG_NFC_NCI_UART policy<{'arm64': 'm'}> +CONFIG_NFC_NXP_NCI policy<{'arm64': 'm'}> +CONFIG_NFC_NXP_NCI_I2C policy<{'arm64': 'm'}> +CONFIG_NFC_PN532_UART policy<{'arm64': 'm'}> +CONFIG_NFC_PN533 policy<{'arm64': 'm'}> +CONFIG_NFC_PN533_I2C policy<{'arm64': 'm'}> +CONFIG_NFC_PN533_USB policy<{'arm64': 'm'}> +CONFIG_NFC_PN544 policy<{'arm64': 'm'}> +CONFIG_NFC_PN544_I2C policy<{'arm64': 'm'}> +CONFIG_NFC_PORT100 policy<{'arm64': 'm'}> +CONFIG_NFC_S3FWRN5 policy<{'arm64': 'm'}> +CONFIG_NFC_S3FWRN5_I2C policy<{'arm64': 'm'}> +CONFIG_NFC_S3FWRN82_UART policy<{'arm64': 'm'}> +CONFIG_NFC_SHDLC policy<{'arm64': 'y'}> +CONFIG_NFC_SIM policy<{'arm64': 'm'}> +CONFIG_NFC_ST21NFCA policy<{'arm64': 'm'}> +CONFIG_NFC_ST21NFCA_I2C policy<{'arm64': 'm'}> +CONFIG_NFC_ST95HF policy<{'arm64': 'm'}> +CONFIG_NFC_ST_NCI policy<{'arm64': 'm'}> +CONFIG_NFC_ST_NCI_I2C policy<{'arm64': 'm'}> +CONFIG_NFC_ST_NCI_SPI policy<{'arm64': 'm'}> +CONFIG_NFC_TRF7970A policy<{'arm64': 'm'}> +CONFIG_NFC_VIRTUAL_NCI policy<{'arm64': 'm'}> +CONFIG_NFIT_SECURITY_DEBUG policy<{'arm64': 'n'}> +CONFIG_NFP policy<{'arm64': 'm'}> +CONFIG_NFP_APP_ABM_NIC policy<{'arm64': 'y'}> +CONFIG_NFP_APP_FLOWER policy<{'arm64': 'y'}> +CONFIG_NFP_DEBUG policy<{'arm64': 'n'}> +CONFIG_NFP_NET_IPSEC policy<{'arm64': 'y'}> +CONFIG_NFSD policy<{'arm64': 'm'}> +CONFIG_NFSD_BLOCKLAYOUT policy<{'arm64': 'y'}> +CONFIG_NFSD_FLEXFILELAYOUT policy<{'arm64': 'y'}> +CONFIG_NFSD_LEGACY_CLIENT_TRACKING policy<{'arm64': 'y'}> +CONFIG_NFSD_PNFS policy<{'arm64': 'y'}> +CONFIG_NFSD_SCSILAYOUT policy<{'arm64': 'y'}> +CONFIG_NFSD_V2 policy<{'arm64': 'n'}> +CONFIG_NFSD_V3_ACL policy<{'arm64': 'y'}> +CONFIG_NFSD_V4 policy<{'arm64': 'y'}> +CONFIG_NFSD_V4_POSIX_ACLS policy<{'arm64': 'n'}> +CONFIG_NFSD_V4_SECURITY_LABEL policy<{'arm64': 'y'}> +CONFIG_NFS_ACL_SUPPORT policy<{'arm64': 'm'}> +CONFIG_NFS_COMMON policy<{'arm64': 'y'}> +CONFIG_NFS_DEBUG policy<{'arm64': 'y'}> +CONFIG_NFS_DISABLE_UDP_SUPPORT policy<{'arm64': 'y'}> +CONFIG_NFS_FS policy<{'arm64': 'm'}> +CONFIG_NFS_FSCACHE policy<{'arm64': 'y'}> +CONFIG_NFS_LOCALIO policy<{'arm64': 'n'}> +CONFIG_NFS_SWAP policy<{'arm64': 'y'}> +CONFIG_NFS_USE_KERNEL_DNS policy<{'arm64': 'y'}> +CONFIG_NFS_USE_LEGACY_DNS policy<{'arm64': 'n'}> +CONFIG_NFS_V2 policy<{'arm64': 'm'}> +CONFIG_NFS_V3 policy<{'arm64': 'm'}> +CONFIG_NFS_V3_ACL policy<{'arm64': 'y'}> +CONFIG_NFS_V4 policy<{'arm64': 'm'}> +CONFIG_NFS_V4_0 policy<{'arm64': 'y'}> +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN policy<{'arm64': '"kernel.org"'}> +CONFIG_NFS_V4_1_MIGRATION policy<{'arm64': 'n'}> +CONFIG_NFS_V4_2 policy<{'arm64': 'n'}> +CONFIG_NFTL policy<{'arm64': 'm'}> +CONFIG_NFTL_RW policy<{'arm64': 'y'}> +CONFIG_NFT_BRIDGE_META policy<{'arm64': 'm'}> +CONFIG_NFT_BRIDGE_REJECT policy<{'arm64': 'm'}> +CONFIG_NFT_COMPAT policy<{'arm64': 'm'}> +CONFIG_NFT_COMPAT_ARP policy<{'arm64': 'm'}> +CONFIG_NFT_CONNLIMIT policy<{'arm64': 'm'}> +CONFIG_NFT_CT policy<{'arm64': 'm'}> +CONFIG_NFT_DUP_IPV4 policy<{'arm64': 'm'}> +CONFIG_NFT_DUP_IPV6 policy<{'arm64': 'm'}> +CONFIG_NFT_DUP_NETDEV policy<{'arm64': 'm'}> +CONFIG_NFT_EXTHDR_DCCP policy<{'arm64': 'n'}> +CONFIG_NFT_FIB policy<{'arm64': 'm'}> +CONFIG_NFT_FIB_INET policy<{'arm64': 'm'}> +CONFIG_NFT_FIB_IPV4 policy<{'arm64': 'm'}> +CONFIG_NFT_FIB_IPV6 policy<{'arm64': 'm'}> +CONFIG_NFT_FIB_NETDEV policy<{'arm64': 'm'}> +CONFIG_NFT_FLOW_OFFLOAD policy<{'arm64': 'm'}> +CONFIG_NFT_FWD_NETDEV policy<{'arm64': 'm'}> +CONFIG_NFT_HASH policy<{'arm64': 'm'}> +CONFIG_NFT_LIMIT policy<{'arm64': 'm'}> +CONFIG_NFT_LOG policy<{'arm64': 'm'}> +CONFIG_NFT_MASQ policy<{'arm64': 'm'}> +CONFIG_NFT_NAT policy<{'arm64': 'm'}> +CONFIG_NFT_NUMGEN policy<{'arm64': 'm'}> +CONFIG_NFT_OSF policy<{'arm64': 'm'}> +CONFIG_NFT_QUEUE policy<{'arm64': 'm'}> +CONFIG_NFT_QUOTA policy<{'arm64': 'm'}> +CONFIG_NFT_REDIR policy<{'arm64': 'm'}> +CONFIG_NFT_REJECT policy<{'arm64': 'm'}> +CONFIG_NFT_REJECT_INET policy<{'arm64': 'm'}> +CONFIG_NFT_REJECT_IPV4 policy<{'arm64': 'm'}> +CONFIG_NFT_REJECT_IPV6 policy<{'arm64': 'm'}> +CONFIG_NFT_REJECT_NETDEV policy<{'arm64': 'm'}> +CONFIG_NFT_SOCKET policy<{'arm64': 'm'}> +CONFIG_NFT_SYNPROXY policy<{'arm64': 'm'}> +CONFIG_NFT_TPROXY policy<{'arm64': 'm'}> +CONFIG_NFT_TUNNEL policy<{'arm64': 'm'}> +CONFIG_NFT_XFRM policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_AMANDA policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_BRIDGE policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_BROADCAST policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_EVENTS policy<{'arm64': 'y'}> +CONFIG_NF_CONNTRACK_FTP policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_H323 policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_IRC policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_LABELS policy<{'arm64': 'y'}> +CONFIG_NF_CONNTRACK_MARK policy<{'arm64': 'y'}> +CONFIG_NF_CONNTRACK_NETBIOS_NS policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_OVS policy<{'arm64': 'y'}> +CONFIG_NF_CONNTRACK_PPTP policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_PROCFS policy<{'arm64': 'n'}> +CONFIG_NF_CONNTRACK_SANE policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_SECMARK policy<{'arm64': 'y'}> +CONFIG_NF_CONNTRACK_SIP policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_SNMP policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_TFTP policy<{'arm64': 'm'}> +CONFIG_NF_CONNTRACK_TIMEOUT policy<{'arm64': 'y'}> +CONFIG_NF_CONNTRACK_TIMESTAMP policy<{'arm64': 'y'}> +CONFIG_NF_CONNTRACK_ZONES policy<{'arm64': 'y'}> +CONFIG_NF_CT_NETLINK policy<{'arm64': 'm'}> +CONFIG_NF_CT_NETLINK_HELPER policy<{'arm64': 'm'}> +CONFIG_NF_CT_NETLINK_TIMEOUT policy<{'arm64': 'm'}> +CONFIG_NF_CT_PROTO_GRE policy<{'arm64': 'y'}> +CONFIG_NF_CT_PROTO_SCTP policy<{'arm64': 'y'}> +CONFIG_NF_DEFRAG_IPV4 policy<{'arm64': 'm'}> +CONFIG_NF_DEFRAG_IPV6 policy<{'arm64': 'm'}> +CONFIG_NF_DUP_IPV4 policy<{'arm64': 'm'}> +CONFIG_NF_DUP_IPV6 policy<{'arm64': 'm'}> +CONFIG_NF_DUP_NETDEV policy<{'arm64': 'm'}> +CONFIG_NF_FLOW_TABLE policy<{'arm64': 'm'}> +CONFIG_NF_FLOW_TABLE_INET policy<{'arm64': 'm'}> +CONFIG_NF_FLOW_TABLE_PROCFS policy<{'arm64': 'n'}> +CONFIG_NF_LOG_ARP policy<{'arm64': 'm'}> +CONFIG_NF_LOG_IPV4 policy<{'arm64': 'm'}> +CONFIG_NF_LOG_IPV6 policy<{'arm64': 'm'}> +CONFIG_NF_LOG_SYSLOG policy<{'arm64': 'm'}> +CONFIG_NF_NAT policy<{'arm64': 'm'}> +CONFIG_NF_NAT_AMANDA policy<{'arm64': 'm'}> +CONFIG_NF_NAT_FTP policy<{'arm64': 'm'}> +CONFIG_NF_NAT_H323 policy<{'arm64': 'm'}> +CONFIG_NF_NAT_IRC policy<{'arm64': 'm'}> +CONFIG_NF_NAT_MASQUERADE policy<{'arm64': 'y'}> +CONFIG_NF_NAT_OVS policy<{'arm64': 'y'}> +CONFIG_NF_NAT_PPTP policy<{'arm64': 'm'}> +CONFIG_NF_NAT_REDIRECT policy<{'arm64': 'y'}> +CONFIG_NF_NAT_SIP policy<{'arm64': 'm'}> +CONFIG_NF_NAT_SNMP_BASIC policy<{'arm64': 'm'}> +CONFIG_NF_NAT_TFTP policy<{'arm64': 'm'}> +CONFIG_NF_REJECT_IPV4 policy<{'arm64': 'm'}> +CONFIG_NF_REJECT_IPV6 policy<{'arm64': 'm'}> +CONFIG_NF_SOCKET_IPV4 policy<{'arm64': 'm'}> +CONFIG_NF_SOCKET_IPV6 policy<{'arm64': 'm'}> +CONFIG_NF_TABLES policy<{'arm64': 'm'}> +CONFIG_NF_TABLES_ARP policy<{'arm64': 'y'}> +CONFIG_NF_TABLES_BRIDGE policy<{'arm64': 'm'}> +CONFIG_NF_TABLES_INET policy<{'arm64': 'y'}> +CONFIG_NF_TABLES_IPV4 policy<{'arm64': 'y'}> +CONFIG_NF_TABLES_IPV6 policy<{'arm64': 'y'}> +CONFIG_NF_TABLES_NETDEV policy<{'arm64': 'y'}> +CONFIG_NF_TPROXY_IPV4 policy<{'arm64': 'm'}> +CONFIG_NF_TPROXY_IPV6 policy<{'arm64': 'm'}> +CONFIG_NGBE policy<{'arm64': 'm'}> +CONFIG_NGBEVF policy<{'arm64': 'n'}> +CONFIG_NIC7018_WDT policy<{'arm64': 'n'}> +CONFIG_NILFS2_FS policy<{'arm64': 'm'}> +CONFIG_NINTENDO_FF policy<{'arm64': 'y'}> +CONFIG_NITRO_ENCLAVES policy<{'arm64': 'm'}> +CONFIG_NIU policy<{'arm64': 'm'}> +CONFIG_NI_XGE_MANAGEMENT_ENET policy<{'arm64': 'm'}> +CONFIG_NL80211_TESTMODE policy<{'arm64': 'n'}> +CONFIG_NLATTR policy<{'arm64': 'y'}> +CONFIG_NLMON policy<{'arm64': 'm'}> +CONFIG_NLS_ASCII policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_1250 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_1251 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_437 policy<{'arm64': 'y'}> +CONFIG_NLS_CODEPAGE_737 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_775 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_850 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_852 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_855 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_857 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_860 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_861 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_862 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_863 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_864 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_865 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_866 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_869 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_874 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_932 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_936 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_949 policy<{'arm64': 'm'}> +CONFIG_NLS_CODEPAGE_950 policy<{'arm64': 'm'}> +CONFIG_NLS_DEFAULT policy<{'arm64': '"utf8"'}> +CONFIG_NLS_ISO8859_1 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_13 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_14 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_15 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_2 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_3 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_4 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_5 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_6 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_7 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_8 policy<{'arm64': 'm'}> +CONFIG_NLS_ISO8859_9 policy<{'arm64': 'm'}> +CONFIG_NLS_KOI8_R policy<{'arm64': 'm'}> +CONFIG_NLS_KOI8_U policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_CELTIC policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_CENTEURO policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_CROATIAN policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_CYRILLIC policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_GAELIC policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_GREEK policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_ICELAND policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_INUIT policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_ROMAN policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_ROMANIAN policy<{'arm64': 'm'}> +CONFIG_NLS_MAC_TURKISH policy<{'arm64': 'm'}> +CONFIG_NLS_UCS2_UTILS policy<{'arm64': 'm'}> +CONFIG_NLS_UTF8 policy<{'arm64': 'm'}> +CONFIG_NOA1305 policy<{'arm64': 'm'}> +CONFIG_NODES_SHIFT policy<{'arm64': '6'}> +CONFIG_NOP_TRACER policy<{'arm64': 'y'}> +CONFIG_NOTIFIER_ERROR_INJECTION policy<{'arm64': 'm'}> +CONFIG_NOUVEAU_DEBUG policy<{'arm64': '5'}> +CONFIG_NOUVEAU_DEBUG_DEFAULT policy<{'arm64': '3'}> +CONFIG_NOUVEAU_DEBUG_MMU policy<{'arm64': 'n'}> +CONFIG_NOUVEAU_DEBUG_PUSH policy<{'arm64': 'n'}> +CONFIG_NOUVEAU_PLATFORM_DRIVER policy<{'arm64': 'y'}> +CONFIG_NOZOMI policy<{'arm64': 'm'}> +CONFIG_NO_HZ policy<{'arm64': 'y'}> +CONFIG_NO_HZ_COMMON policy<{'arm64': 'y'}> +CONFIG_NO_HZ_IDLE policy<{'arm64': 'n'}> +CONFIG_NO_PAGE_MAPCOUNT policy<{'arm64': 'n'}> +CONFIG_NPCM7XX_KCS_IPMI_BMC policy<{'arm64': 'm'}> +CONFIG_NPCM7XX_TIMER policy<{'arm64': 'y'}> +CONFIG_NPCM7XX_WATCHDOG policy<{'arm64': 'y'}> +CONFIG_NPCM_ADC policy<{'arm64': 'm'}> +CONFIG_NS83820 policy<{'arm64': 'm'}> +CONFIG_NSM policy<{'arm64': 'm'}> +CONFIG_NTB policy<{'arm64': 'm'}> +CONFIG_NTB_EPF policy<{'arm64': 'm'}> +CONFIG_NTB_IDT policy<{'arm64': 'm'}> +CONFIG_NTB_MSI policy<{'arm64': 'y'}> +CONFIG_NTB_MSI_TEST policy<{'arm64': 'n'}> +CONFIG_NTB_NETDEV policy<{'arm64': 'm'}> +CONFIG_NTB_PERF policy<{'arm64': 'm'}> +CONFIG_NTB_PINGPONG policy<{'arm64': 'm'}> +CONFIG_NTB_SWITCHTEC policy<{'arm64': 'm'}> +CONFIG_NTB_TOOL policy<{'arm64': 'm'}> +CONFIG_NTB_TRANSPORT policy<{'arm64': 'm'}> +CONFIG_NTFS3_64BIT_CLUSTER policy<{'arm64': 'n'}> +CONFIG_NTFS3_FS policy<{'arm64': 'm'}> +CONFIG_NTFS3_FS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_NTFS3_LZX_XPRESS policy<{'arm64': 'y'}> +CONFIG_NTFS_DEBUG policy<{'arm64': 'n'}> +CONFIG_NTFS_FS policy<{'arm64': 'm'}> +CONFIG_NTFS_FS_POSIX_ACL policy<{'arm64': 'n'}> +CONFIG_NTSYNC policy<{'arm64': 'y'}> +CONFIG_NULL_TTY policy<{'arm64': 'm'}> +CONFIG_NUMA_BALANCING policy<{'arm64': 'y'}> +CONFIG_NUMA_EMU policy<{'arm64': 'n'}> +CONFIG_NUMA_KEEP_MEMINFO policy<{'arm64': 'y'}> +CONFIG_NUMA_MEMBLKS policy<{'arm64': 'y'}> +CONFIG_NUMA_MIGRATION policy<{'arm64': 'y'}> +CONFIG_NVDIMM_DAX policy<{'arm64': 'y'}> +CONFIG_NVDIMM_KEYS policy<{'arm64': 'y'}> +CONFIG_NVDIMM_PFN policy<{'arm64': 'y'}> +CONFIG_NVDIMM_SECURITY_TEST policy<{'arm64': 'n'}> +CONFIG_NVEC_PAZ00 policy<{'arm64': 'm'}> +CONFIG_NVEC_POWER policy<{'arm64': 'm'}> +CONFIG_NVGRACE_GPU_VFIO_PCI policy<{'arm64': 'm'}> +CONFIG_NVHE_EL2_DEBUG policy<{'arm64': 'n'}> +CONFIG_NVIDIA_CARMEL_CNP_ERRATUM policy<{'arm64': 'y'}> +CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU policy<{'arm64': 'm'}> +CONFIG_NVIDIA_SHIELD_FF policy<{'arm64': 'y'}> +CONFIG_NVIDIA_TEGRA410_C2C_PMU policy<{'arm64': 'n'}> +CONFIG_NVIDIA_TEGRA410_CMEM_LATENCY_PMU policy<{'arm64': 'n'}> +CONFIG_NVMEM_APPLE_EFUSES policy<{'arm64': 'm'}> +CONFIG_NVMEM_APPLE_SPMI policy<{'arm64': 'n'}> +CONFIG_NVMEM_IMX_IIM policy<{'arm64': 'm'}> +CONFIG_NVMEM_IMX_OCOTP policy<{'arm64': 'm'}> +CONFIG_NVMEM_IMX_OCOTP_ELE policy<{'arm64': 'm'}> +CONFIG_NVMEM_IMX_OCOTP_SCU policy<{'arm64': 'm'}> +CONFIG_NVMEM_LAYERSCAPE_SFP policy<{'arm64': 'm'}> +CONFIG_NVMEM_LAYOUTS policy<{'arm64': 'y'}> +CONFIG_NVMEM_LAYOUT_ONIE_TLV policy<{'arm64': 'm'}> +CONFIG_NVMEM_LAYOUT_SL28_VPD policy<{'arm64': 'm'}> +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV policy<{'arm64': 'm'}> +CONFIG_NVMEM_MESON_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_MESON_MX_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_MTK_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_QCOM_QFPROM policy<{'arm64': 'y'}> +CONFIG_NVMEM_QCOM_SEC_QFPROM policy<{'arm64': 'm'}> +CONFIG_NVMEM_RAVE_SP_EEPROM policy<{'arm64': 'm'}> +CONFIG_NVMEM_RCAR_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_REBOOT_MODE policy<{'arm64': 'm'}> +CONFIG_NVMEM_RMEM policy<{'arm64': 'm'}> +CONFIG_NVMEM_ROCKCHIP_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_ROCKCHIP_OTP policy<{'arm64': 'm'}> +CONFIG_NVMEM_S32G_OCOTP policy<{'arm64': 'n'}> +CONFIG_NVMEM_SC27XX_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_SNVS_LPGPR policy<{'arm64': 'm'}> +CONFIG_NVMEM_SPMI_SDAM policy<{'arm64': 'm'}> +CONFIG_NVMEM_SPRD_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_STM32_BSEC_OPTEE_TA policy<{'arm64': 'y'}> +CONFIG_NVMEM_STM32_ROMEM policy<{'arm64': 'm'}> +CONFIG_NVMEM_SUNXI_SID policy<{'arm64': 'm'}> +CONFIG_NVMEM_SYSFS policy<{'arm64': 'y'}> +CONFIG_NVMEM_U_BOOT_ENV policy<{'arm64': 'm'}> +CONFIG_NVMEM_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_NVME_APPLE policy<{'arm64': 'm'}> +CONFIG_NVME_AUTH policy<{'arm64': 'm'}> +CONFIG_NVME_CORE policy<{'arm64': 'm'}> +CONFIG_NVME_FABRICS policy<{'arm64': 'm'}> +CONFIG_NVME_FC policy<{'arm64': 'm'}> +CONFIG_NVME_HOST_AUTH policy<{'arm64': 'y'}> +CONFIG_NVME_HWMON policy<{'arm64': 'y'}> +CONFIG_NVME_KEYRING policy<{'arm64': 'm'}> +CONFIG_NVME_MULTIPATH policy<{'arm64': 'y'}> +CONFIG_NVME_RDMA policy<{'arm64': 'm'}> +CONFIG_NVME_TARGET policy<{'arm64': 'm'}> +CONFIG_NVME_TARGET_AUTH policy<{'arm64': 'y'}> +CONFIG_NVME_TARGET_AUTH_DEBUG policy<{'arm64': 'n'}> +CONFIG_NVME_TARGET_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_NVME_TARGET_FC policy<{'arm64': 'm'}> +CONFIG_NVME_TARGET_FCLOOP policy<{'arm64': 'n'}> +CONFIG_NVME_TARGET_LOOP policy<{'arm64': 'm'}> +CONFIG_NVME_TARGET_PASSTHRU policy<{'arm64': 'y'}> +CONFIG_NVME_TARGET_PCI_EPF policy<{'arm64': 'n'}> +CONFIG_NVME_TARGET_RDMA policy<{'arm64': 'm'}> +CONFIG_NVME_TARGET_TCP policy<{'arm64': 'm'}> +CONFIG_NVME_TARGET_TCP_TLS policy<{'arm64': 'y'}> +CONFIG_NVME_TCP policy<{'arm64': 'm'}> +CONFIG_NVME_TCP_TLS policy<{'arm64': 'y'}> +CONFIG_NVME_VERBOSE_ERRORS policy<{'arm64': 'n'}> +CONFIG_NVSW_SN2201 policy<{'arm64': 'm'}> +CONFIG_NXP_C45_TJA11XX_PHY policy<{'arm64': 'm'}> +CONFIG_NXP_CBTX_PHY policy<{'arm64': 'm'}> +CONFIG_NXP_ENETC4 policy<{'arm64': 'n'}> +CONFIG_NXP_ENETC_PF_COMMON policy<{'arm64': 'm'}> +CONFIG_NXP_NETC_BLK_CTRL policy<{'arm64': 'n'}> +CONFIG_NXP_SAR_ADC policy<{'arm64': 'n'}> +CONFIG_NXP_STM_TIMER policy<{'arm64': 'n'}> +CONFIG_NXP_TJA11XX_PHY policy<{'arm64': 'm'}> +CONFIG_N_HDLC policy<{'arm64': 'm'}> +CONFIG_OBJAGG policy<{'arm64': 'm'}> +CONFIG_OCFS2_DEBUG_FS policy<{'arm64': 'n'}> +CONFIG_OCFS2_DEBUG_MASKLOG policy<{'arm64': 'y'}> +CONFIG_OCFS2_FS policy<{'arm64': 'm'}> +CONFIG_OCFS2_FS_O2CB policy<{'arm64': 'm'}> +CONFIG_OCFS2_FS_STATS policy<{'arm64': 'y'}> +CONFIG_OCFS2_FS_USERSPACE_CLUSTER policy<{'arm64': 'm'}> +CONFIG_OCTEONEP_VDPA policy<{'arm64': 'm'}> +CONFIG_OCTEONTX2_AF policy<{'arm64': 'm'}> +CONFIG_OCTEONTX2_MBOX policy<{'arm64': 'm'}> +CONFIG_OCTEONTX2_PF policy<{'arm64': 'm'}> +CONFIG_OCTEONTX2_VF policy<{'arm64': 'm'}> +CONFIG_OCTEON_EP policy<{'arm64': 'm'}> +CONFIG_OCTEON_EP_VF policy<{'arm64': 'm'}> +CONFIG_OF policy<{'arm64': 'y'}> +CONFIG_OF_ADDRESS policy<{'arm64': 'y'}> +CONFIG_OF_DYNAMIC policy<{'arm64': 'y'}> +CONFIG_OF_EARLY_FLATTREE policy<{'arm64': 'y'}> +CONFIG_OF_FLATTREE policy<{'arm64': 'y'}> +CONFIG_OF_FPGA_REGION policy<{'arm64': 'm'}> +CONFIG_OF_GPIO policy<{'arm64': 'y'}> +CONFIG_OF_IOMMU policy<{'arm64': 'y'}> +CONFIG_OF_IRQ policy<{'arm64': 'y'}> +CONFIG_OF_KOBJ policy<{'arm64': 'y'}> +CONFIG_OF_MDIO policy<{'arm64': 'y'}> +CONFIG_OF_NUMA policy<{'arm64': 'y'}> +CONFIG_OF_OVERLAY policy<{'arm64': 'y'}> +CONFIG_OF_PARTITION policy<{'arm64': 'y'}> +CONFIG_OF_PMEM policy<{'arm64': 'm'}> +CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT policy<{'arm64': 'n'}> +CONFIG_OF_RESERVED_MEM policy<{'arm64': 'y'}> +CONFIG_OF_RESOLVE policy<{'arm64': 'y'}> +CONFIG_OF_UNITTEST policy<{'arm64': 'n'}> +CONFIG_OID_REGISTRY policy<{'arm64': 'y'}> +CONFIG_OLD_SIGSUSPEND3 policy<{'arm64': 'y'}> +CONFIG_OMAP2PLUS_MBOX policy<{'arm64': 'm'}> +CONFIG_OMAP_DM_TIMER policy<{'arm64': 'y'}> +CONFIG_OMAP_GPMC policy<{'arm64': 'y'}> +CONFIG_OMAP_GPMC_DEBUG policy<{'arm64': 'n'}> +CONFIG_OMAP_USB2 policy<{'arm64': 'm'}> +CONFIG_OMFS_FS policy<{'arm64': 'm'}> +CONFIG_OPENSSL_SUPPORTS_ML_DSA policy<{'arm64': 'y'}> +CONFIG_OPENVSWITCH policy<{'arm64': 'm'}> +CONFIG_OPENVSWITCH_GENEVE policy<{'arm64': 'm'}> +CONFIG_OPENVSWITCH_GRE policy<{'arm64': 'm'}> +CONFIG_OPENVSWITCH_VXLAN policy<{'arm64': 'm'}> +CONFIG_OPEN_ALLIANCE_HELPERS policy<{'arm64': 'y'}> +CONFIG_OPEN_DICE policy<{'arm64': 'm'}> +CONFIG_OPT3001 policy<{'arm64': 'm'}> +CONFIG_OPT4001 policy<{'arm64': 'm'}> +CONFIG_OPT4060 policy<{'arm64': 'n'}> +CONFIG_OPTEE policy<{'arm64': 'm'}> +CONFIG_OPTEE_INSECURE_LOAD_IMAGE policy<{'arm64': 'n'}> +CONFIG_OPTEE_STATIC_PROTMEM_POOL policy<{'arm64': 'y'}> +CONFIG_ORANGEFS_FS policy<{'arm64': 'm'}> +CONFIG_OSF_PARTITION policy<{'arm64': 'y'}> +CONFIG_OVERLAY_FS policy<{'arm64': 'm'}> +CONFIG_OVERLAY_FS_DEBUG policy<{'arm64': 'n'}> +CONFIG_OVERLAY_FS_INDEX policy<{'arm64': 'n'}> +CONFIG_OVERLAY_FS_METACOPY policy<{'arm64': 'n'}> +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW policy<{'arm64': 'y'}> +CONFIG_OVERLAY_FS_REDIRECT_DIR policy<{'arm64': 'n'}> +CONFIG_OVERLAY_FS_XINO_AUTO policy<{'arm64': 'y'}> +CONFIG_OVMF_DEBUG_LOG policy<{'arm64': 'n'}> +CONFIG_OVPN policy<{'arm64': 'n'}> +CONFIG_OWL_DMA policy<{'arm64': 'm'}> +CONFIG_OWL_EMAC policy<{'arm64': 'm'}> +CONFIG_OWL_PM_DOMAINS policy<{'arm64': 'y'}> +CONFIG_OWL_PM_DOMAINS_HELPER policy<{'arm64': 'y'}> +CONFIG_OWL_TIMER policy<{'arm64': 'y'}> +CONFIG_P54_COMMON policy<{'arm64': 'm'}> +CONFIG_P54_LEDS policy<{'arm64': 'y'}> +CONFIG_P54_PCI policy<{'arm64': 'm'}> +CONFIG_P54_SPI policy<{'arm64': 'm'}> +CONFIG_P54_SPI_DEFAULT_EEPROM policy<{'arm64': 'n'}> +CONFIG_P54_USB policy<{'arm64': 'm'}> +CONFIG_PA12203001 policy<{'arm64': 'm'}> +CONFIG_PAC1921 policy<{'arm64': 'n'}> +CONFIG_PAC1934 policy<{'arm64': 'm'}> +CONFIG_PACKET policy<{'arm64': 'y'}> +CONFIG_PACKET_DIAG policy<{'arm64': 'm'}> +CONFIG_PACKING policy<{'arm64': 'y'}> +CONFIG_PADATA policy<{'arm64': 'y'}> +CONFIG_PAGE_BLOCK_MAX_ORDER policy<{'arm64': '10'}> +CONFIG_PAGE_COUNTER policy<{'arm64': 'y'}> +CONFIG_PAGE_EXTENSION policy<{'arm64': 'n'}> +CONFIG_PAGE_IDLE_FLAG policy<{'arm64': 'y'}> +CONFIG_PAGE_MAPCOUNT policy<{'arm64': 'y'}> +CONFIG_PAGE_OWNER policy<{'arm64': 'n'}> +CONFIG_PAGE_POOL policy<{'arm64': 'y'}> +CONFIG_PAGE_POOL_STATS policy<{'arm64': 'y'}> +CONFIG_PAGE_REPORTING policy<{'arm64': 'y'}> +CONFIG_PAGE_SHIFT policy<{'arm64': '12'}> +CONFIG_PAGE_SIZE_4KB policy<{'arm64': 'y'}> +CONFIG_PAGE_SIZE_LESS_THAN_256KB policy<{'arm64': 'y'}> +CONFIG_PAGE_SIZE_LESS_THAN_64KB policy<{'arm64': 'y'}> +CONFIG_PAGE_TABLE_CHECK policy<{'arm64': 'n'}> +CONFIG_PAHOLE_VERSION policy<{'arm64': '131'}> +CONFIG_PALMAS_GPADC policy<{'arm64': 'm'}> +CONFIG_PANEL policy<{'arm64': 'm'}> +CONFIG_PANEL_CHANGE_MESSAGE policy<{'arm64': 'n'}> +CONFIG_PANEL_PARPORT policy<{'arm64': '0'}> +CONFIG_PANEL_PROFILE policy<{'arm64': '5'}> +CONFIG_PANIC_ON_OOPS policy<{'arm64': 'n'}> +CONFIG_PANIC_TIMEOUT policy<{'arm64': '0'}> +CONFIG_PANTHERLORD_FF policy<{'arm64': 'y'}> +CONFIG_PARAVIRT policy<{'arm64': 'y'}> +CONFIG_PARAVIRT_TIME_ACCOUNTING policy<{'arm64': 'n'}> +CONFIG_PARMAN policy<{'arm64': 'm'}> +CONFIG_PARPORT policy<{'arm64': 'm'}> +CONFIG_PARPORT_1284 policy<{'arm64': 'y'}> +CONFIG_PARPORT_NOT_PC policy<{'arm64': 'y'}> +CONFIG_PARPORT_PANEL policy<{'arm64': 'm'}> +CONFIG_PARPORT_PC policy<{'arm64': 'm'}> +CONFIG_PARPORT_PC_FIFO policy<{'arm64': 'y'}> +CONFIG_PARPORT_PC_PCMCIA policy<{'arm64': 'n'}> +CONFIG_PARPORT_SERIAL policy<{'arm64': 'm'}> +CONFIG_PARTITION_ADVANCED policy<{'arm64': 'y'}> +CONFIG_PATA_ACPI policy<{'arm64': 'm'}> +CONFIG_PATA_ALI policy<{'arm64': 'm'}> +CONFIG_PATA_AMD policy<{'arm64': 'm'}> +CONFIG_PATA_ARTOP policy<{'arm64': 'm'}> +CONFIG_PATA_ATIIXP policy<{'arm64': 'm'}> +CONFIG_PATA_ATP867X policy<{'arm64': 'm'}> +CONFIG_PATA_CMD640_PCI policy<{'arm64': 'm'}> +CONFIG_PATA_CMD64X policy<{'arm64': 'm'}> +CONFIG_PATA_CYPRESS policy<{'arm64': 'm'}> +CONFIG_PATA_EFAR policy<{'arm64': 'm'}> +CONFIG_PATA_HPT366 policy<{'arm64': 'm'}> +CONFIG_PATA_HPT37X policy<{'arm64': 'm'}> +CONFIG_PATA_HPT3X2N policy<{'arm64': 'm'}> +CONFIG_PATA_HPT3X3 policy<{'arm64': 'm'}> +CONFIG_PATA_HPT3X3_DMA policy<{'arm64': 'n'}> +CONFIG_PATA_IMX policy<{'arm64': 'm'}> +CONFIG_PATA_IT8213 policy<{'arm64': 'm'}> +CONFIG_PATA_IT821X policy<{'arm64': 'm'}> +CONFIG_PATA_JMICRON policy<{'arm64': 'm'}> +CONFIG_PATA_LEGACY policy<{'arm64': 'm'}> +CONFIG_PATA_MARVELL policy<{'arm64': 'm'}> +CONFIG_PATA_MPIIX policy<{'arm64': 'm'}> +CONFIG_PATA_NETCELL policy<{'arm64': 'm'}> +CONFIG_PATA_NINJA32 policy<{'arm64': 'm'}> +CONFIG_PATA_NS87410 policy<{'arm64': 'm'}> +CONFIG_PATA_NS87415 policy<{'arm64': 'm'}> +CONFIG_PATA_OF_PLATFORM policy<{'arm64': 'm'}> +CONFIG_PATA_OLDPIIX policy<{'arm64': 'm'}> +CONFIG_PATA_OPTI policy<{'arm64': 'm'}> +CONFIG_PATA_OPTIDMA policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_ATEN policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_BPCK policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_BPCK6 policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_COMM policy<{'arm64': 'n'}> +CONFIG_PATA_PARPORT_DSTR policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_EPAT policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_EPATC8 policy<{'arm64': 'y'}> +CONFIG_PATA_PARPORT_EPIA policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_FIT2 policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_FIT3 policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_FRIQ policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_FRPW policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_KBIC policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_KTTI policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_ON20 policy<{'arm64': 'm'}> +CONFIG_PATA_PARPORT_ON26 policy<{'arm64': 'm'}> +CONFIG_PATA_PCMCIA policy<{'arm64': 'n'}> +CONFIG_PATA_PDC2027X policy<{'arm64': 'm'}> +CONFIG_PATA_PDC_OLD policy<{'arm64': 'm'}> +CONFIG_PATA_PLATFORM policy<{'arm64': 'm'}> +CONFIG_PATA_RADISYS policy<{'arm64': 'm'}> +CONFIG_PATA_RDC policy<{'arm64': 'm'}> +CONFIG_PATA_RZ1000 policy<{'arm64': 'm'}> +CONFIG_PATA_SCH policy<{'arm64': 'm'}> +CONFIG_PATA_SERVERWORKS policy<{'arm64': 'm'}> +CONFIG_PATA_SIL680 policy<{'arm64': 'm'}> +CONFIG_PATA_SIS policy<{'arm64': 'm'}> +CONFIG_PATA_TIMINGS policy<{'arm64': 'y'}> +CONFIG_PATA_TOSHIBA policy<{'arm64': 'm'}> +CONFIG_PATA_TRIFLEX policy<{'arm64': 'm'}> +CONFIG_PATA_VIA policy<{'arm64': 'm'}> +CONFIG_PATA_WINBOND policy<{'arm64': 'm'}> +CONFIG_PC104 policy<{'arm64': 'y'}> +CONFIG_PC300TOO policy<{'arm64': 'm'}> +CONFIG_PCC policy<{'arm64': 'y'}> +CONFIG_PCCARD policy<{'arm64': 'm'}> +CONFIG_PCCARD_NONSTATIC policy<{'arm64': 'y'}> +CONFIG_PCI policy<{'arm64': 'y'}> +CONFIG_PCI200SYN policy<{'arm64': 'm'}> +CONFIG_PCIEAER policy<{'arm64': 'y'}> +CONFIG_PCIEAER_INJECT policy<{'arm64': 'n'}> +CONFIG_PCIEASPM policy<{'arm64': 'y'}> +CONFIG_PCIEASPM_PERFORMANCE policy<{'arm64': 'n'}> +CONFIG_PCIEASPM_POWERSAVE policy<{'arm64': 'n'}> +CONFIG_PCIEASPM_POWER_SUPERSAVE policy<{'arm64': 'n'}> +CONFIG_PCIE_AL policy<{'arm64': 'y'}> +CONFIG_PCIE_ALTERA policy<{'arm64': 'y'}> +CONFIG_PCIE_ALTERA_MSI policy<{'arm64': 'y'}> +CONFIG_PCIE_AMD_MDB policy<{'arm64': 'n'}> +CONFIG_PCIE_APPLE policy<{'arm64': 'm'}> +CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR policy<{'arm64': '0xfffff000'}> +CONFIG_PCIE_ARMADA_8K policy<{'arm64': 'y'}> +CONFIG_PCIE_CADENCE policy<{'arm64': 'y'}> +CONFIG_PCIE_CADENCE_EP policy<{'arm64': 'y'}> +CONFIG_PCIE_CADENCE_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_CADENCE_PLAT policy<{'arm64': 'y'}> +CONFIG_PCIE_CADENCE_PLAT_EP policy<{'arm64': 'y'}> +CONFIG_PCIE_CADENCE_PLAT_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_DPC policy<{'arm64': 'y'}> +CONFIG_PCIE_DW policy<{'arm64': 'y'}> +CONFIG_PCIE_DW_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_PCIE_DW_EP policy<{'arm64': 'y'}> +CONFIG_PCIE_DW_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_DW_PLAT policy<{'arm64': 'y'}> +CONFIG_PCIE_DW_PLAT_EP policy<{'arm64': 'y'}> +CONFIG_PCIE_DW_PLAT_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_ECRC policy<{'arm64': 'n'}> +CONFIG_PCIE_EDR policy<{'arm64': 'y'}> +CONFIG_PCIE_HISI_ERR policy<{'arm64': 'y'}> +CONFIG_PCIE_HISI_STB policy<{'arm64': 'y'}> +CONFIG_PCIE_KEEMBAY policy<{'arm64': 'y'}> +CONFIG_PCIE_KEEMBAY_EP policy<{'arm64': 'y'}> +CONFIG_PCIE_KEEMBAY_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_KIRIN policy<{'arm64': 'y'}> +CONFIG_PCIE_LAYERSCAPE_GEN4 policy<{'arm64': 'n'}> +CONFIG_PCIE_MEDIATEK policy<{'arm64': 'y'}> +CONFIG_PCIE_MEDIATEK_GEN3 policy<{'arm64': 'm'}> +CONFIG_PCIE_MICROCHIP_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_MOBIVEIL_PLAT policy<{'arm64': 'n'}> +CONFIG_PCIE_NXP_S32G policy<{'arm64': 'n'}> +CONFIG_PCIE_PLDA_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_PME policy<{'arm64': 'y'}> +CONFIG_PCIE_PTM policy<{'arm64': 'y'}> +CONFIG_PCIE_QCOM policy<{'arm64': 'y'}> +CONFIG_PCIE_QCOM_COMMON policy<{'arm64': 'y'}> +CONFIG_PCIE_QCOM_EP policy<{'arm64': 'm'}> +CONFIG_PCIE_RCAR_EP policy<{'arm64': 'y'}> +CONFIG_PCIE_RCAR_GEN4 policy<{'arm64': 'm'}> +CONFIG_PCIE_RCAR_GEN4_EP policy<{'arm64': 'm'}> +CONFIG_PCIE_RCAR_GEN4_HOST policy<{'arm64': 'm'}> +CONFIG_PCIE_RCAR_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_RENESAS_RZG3S_HOST policy<{'arm64': 'n'}> +CONFIG_PCIE_ROCKCHIP policy<{'arm64': 'y'}> +CONFIG_PCIE_ROCKCHIP_DW policy<{'arm64': 'y'}> +CONFIG_PCIE_ROCKCHIP_DW_EP policy<{'arm64': 'y'}> +CONFIG_PCIE_ROCKCHIP_DW_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_ROCKCHIP_EP policy<{'arm64': 'y'}> +CONFIG_PCIE_ROCKCHIP_HOST policy<{'arm64': 'm'}> +CONFIG_PCIE_STM32_EP policy<{'arm64': 'n'}> +CONFIG_PCIE_STM32_HOST policy<{'arm64': 'n'}> +CONFIG_PCIE_TEGRA194 policy<{'arm64': 'm'}> +CONFIG_PCIE_TEGRA194_EP policy<{'arm64': 'm'}> +CONFIG_PCIE_TEGRA194_HOST policy<{'arm64': 'm'}> +CONFIG_PCIE_THERMAL policy<{'arm64': 'n'}> +CONFIG_PCIE_TPH policy<{'arm64': 'n'}> +CONFIG_PCIE_VISCONTI_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_XILINX policy<{'arm64': 'y'}> +CONFIG_PCIE_XILINX_CPM policy<{'arm64': 'y'}> +CONFIG_PCIE_XILINX_DMA_PL policy<{'arm64': 'y'}> +CONFIG_PCIE_XILINX_NWL policy<{'arm64': 'y'}> +CONFIG_PCIPCWATCHDOG policy<{'arm64': 'm'}> +CONFIG_PCI_AARDVARK policy<{'arm64': 'y'}> +CONFIG_PCI_ATS policy<{'arm64': 'y'}> +CONFIG_PCI_BRIDGE_EMUL policy<{'arm64': 'y'}> +CONFIG_PCI_DEBUG policy<{'arm64': 'n'}> +CONFIG_PCI_DOE policy<{'arm64': 'y'}> +CONFIG_PCI_DOMAINS policy<{'arm64': 'y'}> +CONFIG_PCI_DOMAINS_GENERIC policy<{'arm64': 'y'}> +CONFIG_PCI_DYNAMIC_OF_NODES policy<{'arm64': 'n'}> +CONFIG_PCI_ECAM policy<{'arm64': 'y'}> +CONFIG_PCI_ENDPOINT policy<{'arm64': 'y'}> +CONFIG_PCI_ENDPOINT_CONFIGFS policy<{'arm64': 'y'}> +CONFIG_PCI_ENDPOINT_MSI_DOORBELL policy<{'arm64': 'n'}> +CONFIG_PCI_ENDPOINT_TEST policy<{'arm64': 'n'}> +CONFIG_PCI_EPF_MHI policy<{'arm64': 'm'}> +CONFIG_PCI_EPF_NTB policy<{'arm64': 'm'}> +CONFIG_PCI_EPF_TEST policy<{'arm64': 'n'}> +CONFIG_PCI_EPF_VNTB policy<{'arm64': 'm'}> +CONFIG_PCI_FTPCI100 policy<{'arm64': 'y'}> +CONFIG_PCI_HISI policy<{'arm64': 'y'}> +CONFIG_PCI_HOST_COMMON policy<{'arm64': 'y'}> +CONFIG_PCI_HOST_GENERIC policy<{'arm64': 'y'}> +CONFIG_PCI_HOST_THUNDER_ECAM policy<{'arm64': 'y'}> +CONFIG_PCI_HOST_THUNDER_PEM policy<{'arm64': 'y'}> +CONFIG_PCI_IMX6 policy<{'arm64': 'y'}> +CONFIG_PCI_IMX6_EP policy<{'arm64': 'y'}> +CONFIG_PCI_IMX6_HOST policy<{'arm64': 'y'}> +CONFIG_PCI_IOV policy<{'arm64': 'y'}> +CONFIG_PCI_J721E policy<{'arm64': 'y'}> +CONFIG_PCI_J721E_EP policy<{'arm64': 'y'}> +CONFIG_PCI_J721E_HOST policy<{'arm64': 'y'}> +CONFIG_PCI_KEYSTONE_EP policy<{'arm64': 'y'}> +CONFIG_PCI_KEYSTONE_HOST policy<{'arm64': 'y'}> +CONFIG_PCI_KEYSTONE_TRISTATE policy<{'arm64': 'y'}> +CONFIG_PCI_LABEL policy<{'arm64': 'y'}> +CONFIG_PCI_LAYERSCAPE policy<{'arm64': 'y'}> +CONFIG_PCI_LAYERSCAPE_EP policy<{'arm64': 'y'}> +CONFIG_PCI_MSI policy<{'arm64': 'y'}> +CONFIG_PCI_NPEM policy<{'arm64': 'n'}> +CONFIG_PCI_P2PDMA policy<{'arm64': 'y'}> +CONFIG_PCI_PASID policy<{'arm64': 'y'}> +CONFIG_PCI_PF_STUB policy<{'arm64': 'm'}> +CONFIG_PCI_PRI policy<{'arm64': 'y'}> +CONFIG_PCI_PWRCTRL policy<{'arm64': 'y'}> +CONFIG_PCI_PWRCTRL_GENERIC policy<{'arm64': 'y'}> +CONFIG_PCI_PWRCTRL_PWRSEQ policy<{'arm64': 'm'}> +CONFIG_PCI_PWRCTRL_TC9563 policy<{'arm64': 'm'}> +CONFIG_PCI_QUIRKS policy<{'arm64': 'y'}> +CONFIG_PCI_REALLOC_ENABLE_AUTO policy<{'arm64': 'y'}> +CONFIG_PCI_STUB policy<{'arm64': 'm'}> +CONFIG_PCI_SW_SWITCHTEC policy<{'arm64': 'm'}> +CONFIG_PCI_SYSCALL policy<{'arm64': 'y'}> +CONFIG_PCI_TEGRA policy<{'arm64': 'y'}> +CONFIG_PCI_TSM policy<{'arm64': 'n'}> +CONFIG_PCI_XGENE policy<{'arm64': 'y'}> +CONFIG_PCI_XGENE_MSI policy<{'arm64': 'y'}> +CONFIG_PCMCIA policy<{'arm64': 'm'}> +CONFIG_PCMCIA_LOAD_CIS policy<{'arm64': 'y'}> +CONFIG_PCMCIA_PCNET policy<{'arm64': 'n'}> +CONFIG_PCMCIA_XIRC2PS policy<{'arm64': 'n'}> +CONFIG_PCMCIA_XIRCOM policy<{'arm64': 'm'}> +CONFIG_PCNET32 policy<{'arm64': 'm'}> +CONFIG_PCPU_DEV_REFCNT policy<{'arm64': 'y'}> +CONFIG_PCP_BATCH_SCALE_MAX policy<{'arm64': '5'}> +CONFIG_PCS_LYNX policy<{'arm64': 'y'}> +CONFIG_PCS_MTK_LYNXI policy<{'arm64': 'm'}> +CONFIG_PCS_RZN1_MIIC policy<{'arm64': 'm'}> +CONFIG_PCS_XPCS policy<{'arm64': 'm'}> +CONFIG_PD6729 policy<{'arm64': 'n'}> +CONFIG_PDC_ADMA policy<{'arm64': 'm'}> +CONFIG_PDS_CORE policy<{'arm64': 'm'}> +CONFIG_PDS_VDPA policy<{'arm64': 'm'}> +CONFIG_PDS_VFIO_PCI policy<{'arm64': 'm'}> +CONFIG_PECI policy<{'arm64': 'm'}> +CONFIG_PECI_CPU policy<{'arm64': 'm'}> +CONFIG_PECI_NPCM policy<{'arm64': 'm'}> +CONFIG_PERCPU_STATS policy<{'arm64': 'n'}> +CONFIG_PERCPU_TEST policy<{'arm64': 'n'}> +CONFIG_PERF_EVENTS policy<{'arm64': 'y'}> +CONFIG_PERSISTENT_HUGE_ZERO_FOLIO policy<{'arm64': 'n'}> +CONFIG_PERSISTENT_KEYRINGS policy<{'arm64': 'y'}> +CONFIG_PER_VMA_LOCK policy<{'arm64': 'y'}> +CONFIG_PER_VMA_LOCK_STATS policy<{'arm64': 'n'}> +CONFIG_PFCP policy<{'arm64': 'm'}> +CONFIG_PGTABLE_HAS_HUGE_LEAVES policy<{'arm64': 'y'}> +CONFIG_PGTABLE_LEVELS policy<{'arm64': '5'}> +CONFIG_PHANTOM policy<{'arm64': 'm'}> +CONFIG_PHONET policy<{'arm64': 'm'}> +CONFIG_PHYLIB policy<{'arm64': 'y'}> +CONFIG_PHYLIB_LEDS policy<{'arm64': 'y'}> +CONFIG_PHYLINK policy<{'arm64': 'y'}> +CONFIG_PHYS_ADDR_T_64BIT policy<{'arm64': 'y'}> +CONFIG_PHY_AIROHA_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_AM654_SERDES policy<{'arm64': 'm'}> +CONFIG_PHY_APPLE_ATC policy<{'arm64': 'n'}> +CONFIG_PHY_BERLIN_SATA policy<{'arm64': 'm'}> +CONFIG_PHY_BERLIN_USB policy<{'arm64': 'm'}> +CONFIG_PHY_CADENCE_DPHY policy<{'arm64': 'm'}> +CONFIG_PHY_CADENCE_DPHY_RX policy<{'arm64': 'm'}> +CONFIG_PHY_CADENCE_SALVO policy<{'arm64': 'm'}> +CONFIG_PHY_CADENCE_SIERRA policy<{'arm64': 'm'}> +CONFIG_PHY_CADENCE_TORRENT policy<{'arm64': 'm'}> +CONFIG_PHY_CAN_TRANSCEIVER policy<{'arm64': 'm'}> +CONFIG_PHY_COMMON_PROPS policy<{'arm64': 'y'}> +CONFIG_PHY_CPCAP_USB policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_IMX8MQ_USB policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_IMX8M_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_IMX8QM_HSIO policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_LYNX_10G policy<{'arm64': 'n'}> +CONFIG_PHY_FSL_LYNX_28G policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_LYNX_CORE policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY policy<{'arm64': 'm'}> +CONFIG_PHY_GOOGLE_USB policy<{'arm64': 'n'}> +CONFIG_PHY_HI3660_USB policy<{'arm64': 'm'}> +CONFIG_PHY_HI3670_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_HI3670_USB policy<{'arm64': 'm'}> +CONFIG_PHY_HI6220_USB policy<{'arm64': 'm'}> +CONFIG_PHY_HISI_INNO_USB2 policy<{'arm64': 'm'}> +CONFIG_PHY_HISTB_COMBPHY policy<{'arm64': 'm'}> +CONFIG_PHY_INTEL_KEEMBAY_EMMC policy<{'arm64': 'm'}> +CONFIG_PHY_INTEL_KEEMBAY_USB policy<{'arm64': 'm'}> +CONFIG_PHY_J721E_WIZ policy<{'arm64': 'm'}> +CONFIG_PHY_MA35_USB policy<{'arm64': 'n'}> +CONFIG_PHY_MAPPHONE_MDM6600 policy<{'arm64': 'm'}> +CONFIG_PHY_MESON8B_USB2 policy<{'arm64': 'm'}> +CONFIG_PHY_MESON_AXG_MIPI_DPHY policy<{'arm64': 'm'}> +CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG policy<{'arm64': 'y'}> +CONFIG_PHY_MESON_AXG_PCIE policy<{'arm64': 'y'}> +CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG policy<{'arm64': 'm'}> +CONFIG_PHY_MESON_G12A_USB2 policy<{'arm64': 'm'}> +CONFIG_PHY_MESON_G12A_USB3_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_MESON_GXL_USB2 policy<{'arm64': 'm'}> +CONFIG_PHY_MIXEL_LVDS_PHY policy<{'arm64': 'm'}> +CONFIG_PHY_MIXEL_MIPI_DPHY policy<{'arm64': 'm'}> +CONFIG_PHY_MTK_DP policy<{'arm64': 'm'}> +CONFIG_PHY_MTK_HDMI policy<{'arm64': 'm'}> +CONFIG_PHY_MTK_MIPI_CSI_0_5 policy<{'arm64': 'm'}> +CONFIG_PHY_MTK_MIPI_DSI policy<{'arm64': 'm'}> +CONFIG_PHY_MTK_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_MTK_TPHY policy<{'arm64': 'm'}> +CONFIG_PHY_MTK_UFS policy<{'arm64': 'm'}> +CONFIG_PHY_MTK_XFI_TPHY policy<{'arm64': 'm'}> +CONFIG_PHY_MTK_XSPHY policy<{'arm64': 'm'}> +CONFIG_PHY_MVEBU_A3700_COMPHY policy<{'arm64': 'm'}> +CONFIG_PHY_MVEBU_A3700_UTMI policy<{'arm64': 'm'}> +CONFIG_PHY_MVEBU_A38X_COMPHY policy<{'arm64': 'm'}> +CONFIG_PHY_MVEBU_CP110_COMPHY policy<{'arm64': 'm'}> +CONFIG_PHY_MVEBU_CP110_UTMI policy<{'arm64': 'm'}> +CONFIG_PHY_NXP_PTN3222 policy<{'arm64': 'm'}> +CONFIG_PHY_NXP_TJA1145 policy<{'arm64': 'n'}> +CONFIG_PHY_OCELOT_SERDES policy<{'arm64': 'm'}> +CONFIG_PHY_PACKAGE policy<{'arm64': 'm'}> +CONFIG_PHY_PXA_28NM_HSIC policy<{'arm64': 'm'}> +CONFIG_PHY_PXA_28NM_USB2 policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_APQ8064_SATA policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_EDP policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_EUSB2_REPEATER policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_IPQ4019_USB policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_IPQ806X_SATA policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_IPQ806X_USB policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_M31_EUSB policy<{'arm64': 'n'}> +CONFIG_PHY_QCOM_M31_USB policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_MIPI_CSI2 policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_PCIE2 policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_QMP policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_QMP_COMBO policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_QMP_PCIE policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_QMP_PCIE_8996 policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_QMP_UFS policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_QMP_USB policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_QMP_USB_LEGACY policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_QUSB2 policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_SGMII_ETH policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_USB_HS policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_USB_HSIC policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_USB_HS_28NM policy<{'arm64': 'm'}> +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_USB_SS policy<{'arm64': 'm'}> +CONFIG_PHY_R8A779F0_ETHERNET_SERDES policy<{'arm64': 'm'}> +CONFIG_PHY_RCAR_GEN2 policy<{'arm64': 'm'}> +CONFIG_PHY_RCAR_GEN3_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_RCAR_GEN3_USB2 policy<{'arm64': 'm'}> +CONFIG_PHY_RCAR_GEN3_USB3 policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_DP policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_DPHY_RX0 policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_EMMC policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_HDMI policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_USB2 policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY policy<{'arm64': 'n'}> +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_TYPEC policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_USB policy<{'arm64': 'm'}> +CONFIG_PHY_ROCKCHIP_USBDP policy<{'arm64': 'm'}> +CONFIG_PHY_RTK_RTD_USB2PHY policy<{'arm64': 'm'}> +CONFIG_PHY_RTK_RTD_USB3PHY policy<{'arm64': 'm'}> +CONFIG_PHY_RZ_G3E_USB3 policy<{'arm64': 'n'}> +CONFIG_PHY_SAMSUNG_USB2 policy<{'arm64': 'm'}> +CONFIG_PHY_SNPS_EUSB2 policy<{'arm64': 'y'}> +CONFIG_PHY_SPARX5_SERDES policy<{'arm64': 'm'}> +CONFIG_PHY_STM32_COMBOPHY policy<{'arm64': 'm'}> +CONFIG_PHY_STM32_USBPHYC policy<{'arm64': 'm'}> +CONFIG_PHY_SUN4I_USB policy<{'arm64': 'm'}> +CONFIG_PHY_SUN50I_USB3 policy<{'arm64': 'm'}> +CONFIG_PHY_SUN6I_MIPI_DPHY policy<{'arm64': 'm'}> +CONFIG_PHY_SUN9I_USB policy<{'arm64': 'n'}> +CONFIG_PHY_TEGRA194_P2U policy<{'arm64': 'm'}> +CONFIG_PHY_TEGRA_XUSB policy<{'arm64': 'm'}> +CONFIG_PHY_TI_DS125DF111 policy<{'arm64': 'n'}> +CONFIG_PHY_TI_GMII_SEL policy<{'arm64': 'm'}> +CONFIG_PHY_TUSB1210 policy<{'arm64': 'm'}> +CONFIG_PHY_XGENE policy<{'arm64': 'y'}> +CONFIG_PHY_XILINX_ZYNQMP policy<{'arm64': 'm'}> +CONFIG_PID_IN_CONTEXTIDR policy<{'arm64': 'n'}> +CONFIG_PID_NS policy<{'arm64': 'y'}> +CONFIG_PINCONF policy<{'arm64': 'y'}> +CONFIG_PINCTRL policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AC5 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AIROHA policy<{'arm64': 'n'}> +CONFIG_PINCTRL_AMD policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AMDISP policy<{'arm64': 'n'}> +CONFIG_PINCTRL_AMLOGIC_A4 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AMLOGIC_C3 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_AMLOGIC_T7 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_APPLE_GPIO policy<{'arm64': 'm'}> +CONFIG_PINCTRL_ARMADA_37XX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_ARMADA_AP806 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_ARMADA_CP110 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AS370 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AS3722 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AW9523 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_AXP209 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_BERLIN policy<{'arm64': 'y'}> +CONFIG_PINCTRL_BERLIN_BG4CT policy<{'arm64': 'y'}> +CONFIG_PINCTRL_BM1880 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_CS42L43 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_CS47L15 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_CS47L35 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_CS47L85 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_CS47L90 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_CS47L92 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_CY8C95X0 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_DA9062 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_ELIZA policy<{'arm64': 'n'}> +CONFIG_PINCTRL_GENERIC_MUX policy<{'arm64': 'n'}> +CONFIG_PINCTRL_GLYMUR policy<{'arm64': 'n'}> +CONFIG_PINCTRL_HAWI policy<{'arm64': 'n'}> +CONFIG_PINCTRL_IMX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8DXL policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MM policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MN policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MQ policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8QM policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8QXP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8ULP policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IMX91 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IMX93 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IMX_SCMI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IMX_SCU policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IPQ5018 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ5210 policy<{'arm64': 'n'}> +CONFIG_PINCTRL_IPQ5332 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ5424 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ6018 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ8074 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ9574 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ9650 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_KAANAPALI policy<{'arm64': 'n'}> +CONFIG_PINCTRL_KEEMBAY policy<{'arm64': 'm'}> +CONFIG_PINCTRL_LOCHNAGAR policy<{'arm64': 'm'}> +CONFIG_PINCTRL_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MA35 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MA35D1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MADERA policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MAX77620 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MCP23S08 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MCP23S08_I2C policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MCP23S08_SPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MDM9607 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MESON policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON8_PMX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_A1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_AXG policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_AXG_PMX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_G12A policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_GXBB policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_GXL policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_S4 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MICROCHIP_SGPIO policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MILOS policy<{'arm64': 'n'}> +CONFIG_PINCTRL_MILOS_LPASS_LPI policy<{'arm64': 'n'}> +CONFIG_PINCTRL_MLXBF3 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MSM8916 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8917 policy<{'arm64': 'n'}> +CONFIG_PINCTRL_MSM8953 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8976 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8994 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8996 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8998 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MT2712 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6397 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6765 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6779 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MT6795 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6797 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6878 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6893 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7622 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7981 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7986 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7988 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8167 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8173 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8183 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8186 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8188 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8189 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8192 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8195 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8196 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8365 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8516 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MTK policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MTK_MOORE policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MTK_PARIS policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MTK_V2 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MVEBU policy<{'arm64': 'y'}> +CONFIG_PINCTRL_NORD policy<{'arm64': 'y'}> +CONFIG_PINCTRL_NPCM8XX policy<{'arm64': 'm'}> +CONFIG_PINCTRL_OCELOT policy<{'arm64': 'y'}> +CONFIG_PINCTRL_OWL policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PALMAS policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PEF2256 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_PFC_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77951 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77960 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77961 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77965 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77970 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77980 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77990 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77995 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PIC64GX policy<{'arm64': 'n'}> +CONFIG_PINCTRL_POLARFIRE_SOC policy<{'arm64': 'n'}> +CONFIG_PINCTRL_QCM2290 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QCOM_SPMI_PMIC policy<{'arm64': 'y'}> +CONFIG_PINCTRL_QCOM_SSBI_PMIC policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QCS404 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QCS615 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QCS8300 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QDF2XXX policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QDU1000 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_RENESAS policy<{'arm64': 'y'}> +CONFIG_PINCTRL_RK805 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_ROCKCHIP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_RTD policy<{'arm64': 'm'}> +CONFIG_PINCTRL_RTD1315E policy<{'arm64': 'm'}> +CONFIG_PINCTRL_RTD1319D policy<{'arm64': 'm'}> +CONFIG_PINCTRL_RTD1619B policy<{'arm64': 'm'}> +CONFIG_PINCTRL_RTD1625 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_RZG2L policy<{'arm64': 'y'}> +CONFIG_PINCTRL_RZT2H policy<{'arm64': 'y'}> +CONFIG_PINCTRL_RZV2M policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S32CC policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S32G2 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S700 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S900 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SA8775P policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SAR2130P policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SC7180 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SC7280 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SC7280_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SC8180X policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SC8280XP policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SC8280XP_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SCMI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDM660 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDM660_LPASS_LPI policy<{'arm64': 'n'}> +CONFIG_PINCTRL_SDM670 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDM670_LPASS_LPI policy<{'arm64': 'n'}> +CONFIG_PINCTRL_SDM845 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDX75 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SHIKRA policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SH_PFC policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SINGLE policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SM4250_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM4450 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6115 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6115_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6125 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6350 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6350_LPASS_LPI policy<{'arm64': 'n'}> +CONFIG_PINCTRL_SM6375 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM7150 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8150 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8250 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8250_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8350 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8450 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8450_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8550 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8550_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8650 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8650_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8750 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SPRD policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SPRD_SC9860 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STM32 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STM32MP257 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STM32_HDP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STMFX policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SUN20I_D1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN4I_A10 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN50I_A100 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN50I_A100_R policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN50I_A64 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN50I_A64_R policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN50I_H5 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN50I_H6 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN50I_H616 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN50I_H616_R policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN50I_H6_R policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN55I_A523 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN55I_A523_R policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN5I policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN6I_A31 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN6I_A31_R policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN8I_A23 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN8I_A23_R policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN8I_A33 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN8I_A83T policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN8I_A83T_R policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN8I_H3 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN8I_H3_R policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN8I_V3S policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN9I_A80 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUN9I_A80_R policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SUNXI policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SX150X policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA124 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA186 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA194 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA210 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA234 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA238 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_TEGRA264 policy<{'arm64': 'n'}> +CONFIG_PINCTRL_TEGRA_XUSB policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TMPV7700 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TPS6594 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_VISCONTI policy<{'arm64': 'y'}> +CONFIG_PINCTRL_X1E80100 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_ZYNQMP policy<{'arm64': 'm'}> +CONFIG_PING policy<{'arm64': 'm'}> +CONFIG_PINMUX policy<{'arm64': 'y'}> +CONFIG_PKCS7_MESSAGE_PARSER policy<{'arm64': 'y'}> +CONFIG_PKCS7_TEST_KEY policy<{'arm64': 'm'}> +CONFIG_PKCS8_PRIVATE_KEY_PARSER policy<{'arm64': 'm'}> +CONFIG_PL320_MBOX policy<{'arm64': 'y'}> +CONFIG_PL330_DMA policy<{'arm64': 'm'}> +CONFIG_PLATFORM_MHU policy<{'arm64': 'm'}> +CONFIG_PLATFORM_SI4713 policy<{'arm64': 'm'}> +CONFIG_PLAYSTATION_FF policy<{'arm64': 'y'}> +CONFIG_PLDMFW policy<{'arm64': 'y'}> +CONFIG_PLFXLC policy<{'arm64': 'm'}> +CONFIG_PLIP policy<{'arm64': 'm'}> +CONFIG_PLX_DMA policy<{'arm64': 'm'}> +CONFIG_PM8916_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_PMBUS policy<{'arm64': 'm'}> +CONFIG_PMIC_ADP5520 policy<{'arm64': 'y'}> +CONFIG_PMIC_DA903X policy<{'arm64': 'y'}> +CONFIG_PMIC_DA9052 policy<{'arm64': 'y'}> +CONFIG_PMIC_OPREGION policy<{'arm64': 'n'}> +CONFIG_PMS7003 policy<{'arm64': 'm'}> +CONFIG_PM_ADVANCED_DEBUG policy<{'arm64': 'y'}> +CONFIG_PM_AUTOSLEEP policy<{'arm64': 'n'}> +CONFIG_PM_CLK policy<{'arm64': 'y'}> +CONFIG_PM_DEBUG policy<{'arm64': 'y'}> +CONFIG_PM_DEVFREQ policy<{'arm64': 'y'}> +CONFIG_PM_DEVFREQ_EVENT policy<{'arm64': 'y'}> +CONFIG_PM_GENERIC_DOMAINS policy<{'arm64': 'y'}> +CONFIG_PM_GENERIC_DOMAINS_OF policy<{'arm64': 'y'}> +CONFIG_PM_GENERIC_DOMAINS_SLEEP policy<{'arm64': 'y'}> +CONFIG_PM_NOTIFIER_ERROR_INJECT policy<{'arm64': 'm'}> +CONFIG_PM_OPP policy<{'arm64': 'y'}> +CONFIG_PM_QOS_CPU_SYSTEM_WAKEUP policy<{'arm64': 'n'}> +CONFIG_PM_SLEEP policy<{'arm64': 'y'}> +CONFIG_PM_SLEEP_DEBUG policy<{'arm64': 'y'}> +CONFIG_PM_SLEEP_SMP policy<{'arm64': 'y'}> +CONFIG_PM_TEST_SUSPEND policy<{'arm64': 'n'}> +CONFIG_PM_USERSPACE_AUTOSLEEP policy<{'arm64': 'n'}> +CONFIG_PM_WAKELOCKS policy<{'arm64': 'y'}> +CONFIG_PM_WAKELOCKS_GC policy<{'arm64': 'y'}> +CONFIG_PM_WAKELOCKS_LIMIT policy<{'arm64': '100'}> +CONFIG_PNFS_BLOCK policy<{'arm64': 'm'}> +CONFIG_PNFS_FILE_LAYOUT policy<{'arm64': 'm'}> +CONFIG_PNFS_FLEXFILE_LAYOUT policy<{'arm64': 'm'}> +CONFIG_PNP policy<{'arm64': 'y'}> +CONFIG_PNPACPI policy<{'arm64': 'y'}> +CONFIG_PNP_DEBUG_MESSAGES policy<{'arm64': 'y'}> +CONFIG_POLARFIRE_SOC_IRQ_MUX policy<{'arm64': 'y'}> +CONFIG_POLARFIRE_SOC_MAILBOX policy<{'arm64': 'n'}> +CONFIG_POLARFIRE_SOC_SYSCONS policy<{'arm64': 'y'}> +CONFIG_POLYNOMIAL policy<{'arm64': 'm'}> +CONFIG_POSIX_AUX_CLOCKS policy<{'arm64': 'n'}> +CONFIG_POSIX_CPU_TIMERS_TASK_WORK policy<{'arm64': 'y'}> +CONFIG_POSIX_MQUEUE policy<{'arm64': 'y'}> +CONFIG_POSIX_MQUEUE_SYSCTL policy<{'arm64': 'y'}> +CONFIG_POSIX_TIMERS policy<{'arm64': 'y'}> +CONFIG_POWERCAP policy<{'arm64': 'y'}> +CONFIG_POWER_MLXBF policy<{'arm64': 'm'}> +CONFIG_POWER_RESET policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_AS3722 policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_ATC260X policy<{'arm64': 'm'}> +CONFIG_POWER_RESET_GPIO policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_GPIO_RESTART policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_HISI policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_LINKSTATION policy<{'arm64': 'm'}> +CONFIG_POWER_RESET_LTC2952 policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_MSM policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_MT6323 policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_OCELOT_RESET policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_QCOM_PON policy<{'arm64': 'm'}> +CONFIG_POWER_RESET_QEMU_VIRT_CTRL policy<{'arm64': 'n'}> +CONFIG_POWER_RESET_REGULATOR policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_RESTART policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_SC27XX policy<{'arm64': 'm'}> +CONFIG_POWER_RESET_SYSCON policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_SYSCON_POWEROFF policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_TORADEX_EC policy<{'arm64': 'n'}> +CONFIG_POWER_RESET_TPS65086 policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_VEXPRESS policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_XGENE policy<{'arm64': 'n'}> +CONFIG_POWER_SEQUENCING policy<{'arm64': 'y'}> +CONFIG_POWER_SEQUENCING_PCIE_M2 policy<{'arm64': 'n'}> +CONFIG_POWER_SEQUENCING_QCOM_WCN policy<{'arm64': 'm'}> +CONFIG_POWER_SUPPLY policy<{'arm64': 'y'}> +CONFIG_POWER_SUPPLY_DEBUG policy<{'arm64': 'n'}> +CONFIG_POWER_SUPPLY_HWMON policy<{'arm64': 'y'}> +CONFIG_PPDEV policy<{'arm64': 'm'}> +CONFIG_PPP policy<{'arm64': 'y'}> +CONFIG_PPPOATM policy<{'arm64': 'm'}> +CONFIG_PPPOE policy<{'arm64': 'm'}> +CONFIG_PPPOE_HASH_BITS policy<{'arm64': '4'}> +CONFIG_PPPOE_HASH_BITS_1 policy<{'arm64': 'n'}> +CONFIG_PPPOE_HASH_BITS_2 policy<{'arm64': 'n'}> +CONFIG_PPPOE_HASH_BITS_4 policy<{'arm64': 'y'}> +CONFIG_PPPOE_HASH_BITS_8 policy<{'arm64': 'n'}> +CONFIG_PPPOL2TP policy<{'arm64': 'm'}> +CONFIG_PPPOX policy<{'arm64': 'm'}> +CONFIG_PPP_ASYNC policy<{'arm64': 'm'}> +CONFIG_PPP_BSDCOMP policy<{'arm64': 'm'}> +CONFIG_PPP_DEFLATE policy<{'arm64': 'm'}> +CONFIG_PPP_FILTER policy<{'arm64': 'y'}> +CONFIG_PPP_MPPE policy<{'arm64': 'm'}> +CONFIG_PPP_MULTILINK policy<{'arm64': 'y'}> +CONFIG_PPP_SYNC_TTY policy<{'arm64': 'm'}> +CONFIG_PPS policy<{'arm64': 'y'}> +CONFIG_PPS_CLIENT_GPIO policy<{'arm64': 'm'}> +CONFIG_PPS_CLIENT_KTIMER policy<{'arm64': 'n'}> +CONFIG_PPS_CLIENT_LDISC policy<{'arm64': 'm'}> +CONFIG_PPS_CLIENT_PARPORT policy<{'arm64': 'm'}> +CONFIG_PPS_DEBUG policy<{'arm64': 'n'}> +CONFIG_PPS_GENERATOR policy<{'arm64': 'n'}> +CONFIG_PPTP policy<{'arm64': 'm'}> +CONFIG_PREEMPT policy<{'arm64': 'y'}> +CONFIG_PREEMPTION policy<{'arm64': 'y'}> +CONFIG_PREEMPTIRQ_DELAY_TEST policy<{'arm64': 'n'}> +CONFIG_PREEMPT_BUILD policy<{'arm64': 'y'}> +CONFIG_PREEMPT_COUNT policy<{'arm64': 'y'}> +CONFIG_PREEMPT_LAZY policy<{'arm64': 'n'}> +CONFIG_PREEMPT_NOTIFIERS policy<{'arm64': 'y'}> +CONFIG_PREEMPT_RCU policy<{'arm64': 'y'}> +CONFIG_PREEMPT_RT policy<{'arm64': 'n'}> +CONFIG_PREEMPT_TRACER policy<{'arm64': 'n'}> +CONFIG_PRESTERA policy<{'arm64': 'm'}> +CONFIG_PRESTERA_PCI policy<{'arm64': 'm'}> +CONFIG_PREVENT_FIRMWARE_BUILD policy<{'arm64': 'y'}> +CONFIG_PRIME_NUMBERS policy<{'arm64': 'n'}> +CONFIG_PRINTER policy<{'arm64': 'm'}> +CONFIG_PRINTK policy<{'arm64': 'y'}> +CONFIG_PRINTK_CALLER policy<{'arm64': 'n'}> +CONFIG_PRINTK_EXECUTION_CTX policy<{'arm64': 'y'}> +CONFIG_PRINTK_INDEX policy<{'arm64': 'n'}> +CONFIG_PRINTK_TIME policy<{'arm64': 'y'}> +CONFIG_PROBE_EVENTS policy<{'arm64': 'y'}> +CONFIG_PROC_CHILDREN policy<{'arm64': 'y'}> +CONFIG_PROC_EVENTS policy<{'arm64': 'y'}> +CONFIG_PROC_FS policy<{'arm64': 'y'}> +CONFIG_PROC_KCORE policy<{'arm64': 'y'}> +CONFIG_PROC_MEM_ALWAYS_FORCE policy<{'arm64': 'y'}> +CONFIG_PROC_MEM_FORCE_PTRACE policy<{'arm64': 'n'}> +CONFIG_PROC_MEM_NO_FORCE policy<{'arm64': 'n'}> +CONFIG_PROC_PAGE_MONITOR policy<{'arm64': 'y'}> +CONFIG_PROC_SYSCTL policy<{'arm64': 'y'}> +CONFIG_PROC_VMCORE policy<{'arm64': 'y'}> +CONFIG_PROC_VMCORE_DEVICE_DUMP policy<{'arm64': 'y'}> +CONFIG_PROFILE_ANNOTATED_BRANCHES policy<{'arm64': 'n'}> +CONFIG_PROFILING policy<{'arm64': 'y'}> +CONFIG_PROVE_LOCKING policy<{'arm64': 'n'}> +CONFIG_PRU_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_PSAMPLE policy<{'arm64': 'm'}> +CONFIG_PSE_CONTROLLER policy<{'arm64': 'y'}> +CONFIG_PSE_PD692X0 policy<{'arm64': 'm'}> +CONFIG_PSE_REGULATOR policy<{'arm64': 'm'}> +CONFIG_PSE_SI3474 policy<{'arm64': 'n'}> +CONFIG_PSE_TPS23881 policy<{'arm64': 'm'}> +CONFIG_PSI policy<{'arm64': 'y'}> +CONFIG_PSI_DEFAULT_DISABLED policy<{'arm64': 'n'}> +CONFIG_PSTORE policy<{'arm64': 'y'}> +CONFIG_PSTORE_BLK policy<{'arm64': 'm'}> +CONFIG_PSTORE_BLK_BLKDEV policy<{'arm64': '""'}> +CONFIG_PSTORE_BLK_KMSG_SIZE policy<{'arm64': '64'}> +CONFIG_PSTORE_BLK_MAX_REASON policy<{'arm64': '2'}> +CONFIG_PSTORE_COMPRESS policy<{'arm64': 'y'}> +CONFIG_PSTORE_CONSOLE policy<{'arm64': 'n'}> +CONFIG_PSTORE_DEFAULT_KMSG_BYTES policy<{'arm64': '10240'}> +CONFIG_PSTORE_FTRACE policy<{'arm64': 'n'}> +CONFIG_PSTORE_PMSG policy<{'arm64': 'n'}> +CONFIG_PSTORE_RAM policy<{'arm64': 'm'}> +CONFIG_PSTORE_ZONE policy<{'arm64': 'm'}> +CONFIG_PTDUMP policy<{'arm64': 'y'}> +CONFIG_PTDUMP_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_PTDUMP_STAGE2_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_PTE_MARKER_UFFD_WP policy<{'arm64': 'y'}> +CONFIG_PTP_1588_CLOCK policy<{'arm64': 'y'}> +CONFIG_PTP_1588_CLOCK_FC3W policy<{'arm64': 'm'}> +CONFIG_PTP_1588_CLOCK_IDT82P33 policy<{'arm64': 'm'}> +CONFIG_PTP_1588_CLOCK_IDTCM policy<{'arm64': 'm'}> +CONFIG_PTP_1588_CLOCK_INES policy<{'arm64': 'm'}> +CONFIG_PTP_1588_CLOCK_KVM policy<{'arm64': 'm'}> +CONFIG_PTP_1588_CLOCK_MOCK policy<{'arm64': 'm'}> +CONFIG_PTP_1588_CLOCK_OCP policy<{'arm64': 'm'}> +CONFIG_PTP_1588_CLOCK_OPTIONAL policy<{'arm64': 'y'}> +CONFIG_PTP_1588_CLOCK_QORIQ policy<{'arm64': 'm'}> +CONFIG_PTP_1588_CLOCK_VMCLOCK policy<{'arm64': 'm'}> +CONFIG_PTP_DFL_TOD policy<{'arm64': 'm'}> +CONFIG_PTP_NETC_V4_TIMER policy<{'arm64': 'n'}> +CONFIG_PT_RECLAIM policy<{'arm64': 'y'}> +CONFIG_PVPANIC policy<{'arm64': 'y'}> +CONFIG_PVPANIC_MMIO policy<{'arm64': 'm'}> +CONFIG_PVPANIC_PCI policy<{'arm64': 'm'}> +CONFIG_PWC_RZV2M policy<{'arm64': 'y'}> +CONFIG_PWM policy<{'arm64': 'y'}> +CONFIG_PWM_AIROHA policy<{'arm64': 'n'}> +CONFIG_PWM_APPLE policy<{'arm64': 'm'}> +CONFIG_PWM_ARGON_FAN_HAT policy<{'arm64': 'n'}> +CONFIG_PWM_ATMEL_HLCDC_PWM policy<{'arm64': 'm'}> +CONFIG_PWM_ATMEL_TCB policy<{'arm64': 'm'}> +CONFIG_PWM_AXI_PWMGEN policy<{'arm64': 'm'}> +CONFIG_PWM_BERLIN policy<{'arm64': 'm'}> +CONFIG_PWM_CLK policy<{'arm64': 'm'}> +CONFIG_PWM_CROS_EC policy<{'arm64': 'm'}> +CONFIG_PWM_DEBUG policy<{'arm64': 'n'}> +CONFIG_PWM_DWC policy<{'arm64': 'm'}> +CONFIG_PWM_DWC_CORE policy<{'arm64': 'm'}> +CONFIG_PWM_FSL_FTM policy<{'arm64': 'm'}> +CONFIG_PWM_GPIO policy<{'arm64': 'm'}> +CONFIG_PWM_HIBVT policy<{'arm64': 'm'}> +CONFIG_PWM_IMX1 policy<{'arm64': 'm'}> +CONFIG_PWM_IMX27 policy<{'arm64': 'm'}> +CONFIG_PWM_IMX_TPM policy<{'arm64': 'm'}> +CONFIG_PWM_IPQ policy<{'arm64': 'n'}> +CONFIG_PWM_IQS620A policy<{'arm64': 'm'}> +CONFIG_PWM_KEEMBAY policy<{'arm64': 'm'}> +CONFIG_PWM_LP3943 policy<{'arm64': 'm'}> +CONFIG_PWM_MC33XS2410 policy<{'arm64': 'n'}> +CONFIG_PWM_MEDIATEK policy<{'arm64': 'm'}> +CONFIG_PWM_MESON policy<{'arm64': 'm'}> +CONFIG_PWM_MTK_DISP policy<{'arm64': 'm'}> +CONFIG_PWM_NTXEC policy<{'arm64': 'm'}> +CONFIG_PWM_OMAP_DMTIMER policy<{'arm64': 'm'}> +CONFIG_PWM_PCA9685 policy<{'arm64': 'm'}> +CONFIG_PWM_PROVIDE_GPIO policy<{'arm64': 'n'}> +CONFIG_PWM_RENESAS_RCAR policy<{'arm64': 'n'}> +CONFIG_PWM_RENESAS_RZG2L_GPT policy<{'arm64': 'n'}> +CONFIG_PWM_RENESAS_RZ_MTU3 policy<{'arm64': 'n'}> +CONFIG_PWM_RENESAS_TPU policy<{'arm64': 'm'}> +CONFIG_PWM_ROCKCHIP policy<{'arm64': 'm'}> +CONFIG_PWM_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_PWM_SPRD policy<{'arm64': 'm'}> +CONFIG_PWM_STM32 policy<{'arm64': 'm'}> +CONFIG_PWM_STM32_LP policy<{'arm64': 'm'}> +CONFIG_PWM_STMPE policy<{'arm64': 'y'}> +CONFIG_PWM_SUN4I policy<{'arm64': 'm'}> +CONFIG_PWM_TEGRA policy<{'arm64': 'm'}> +CONFIG_PWM_TIECAP policy<{'arm64': 'm'}> +CONFIG_PWM_TIEHRPWM policy<{'arm64': 'm'}> +CONFIG_PWM_TWL policy<{'arm64': 'm'}> +CONFIG_PWM_TWL_LED policy<{'arm64': 'm'}> +CONFIG_PWM_VISCONTI policy<{'arm64': 'm'}> +CONFIG_PWM_XILINX policy<{'arm64': 'm'}> +CONFIG_PWRSEQ_EMMC policy<{'arm64': 'm'}> +CONFIG_PWRSEQ_SD8787 policy<{'arm64': 'm'}> +CONFIG_PWRSEQ_SIMPLE policy<{'arm64': 'm'}> +CONFIG_PXA168_ETH policy<{'arm64': 'm'}> +CONFIG_QAT_VFIO_PCI policy<{'arm64': 'm'}> +CONFIG_QCA7000 policy<{'arm64': 'm'}> +CONFIG_QCA7000_SPI policy<{'arm64': 'm'}> +CONFIG_QCA7000_UART policy<{'arm64': 'm'}> +CONFIG_QCA807X_PHY policy<{'arm64': 'm'}> +CONFIG_QCA808X_PHY policy<{'arm64': 'm'}> +CONFIG_QCA83XX_PHY policy<{'arm64': 'm'}> +CONFIG_QCM_DISPCC_2290 policy<{'arm64': 'm'}> +CONFIG_QCM_GCC_2290 policy<{'arm64': 'm'}> +CONFIG_QCOMTEE policy<{'arm64': 'n'}> +CONFIG_QCOM_A53PLL policy<{'arm64': 'y'}> +CONFIG_QCOM_A7PLL policy<{'arm64': 'm'}> +CONFIG_QCOM_AOSS_QMP policy<{'arm64': 'y'}> +CONFIG_QCOM_APCS_IPC policy<{'arm64': 'y'}> +CONFIG_QCOM_APR policy<{'arm64': 'm'}> +CONFIG_QCOM_BAM_DMA policy<{'arm64': 'y'}> +CONFIG_QCOM_BAM_DMUX policy<{'arm64': 'm'}> +CONFIG_QCOM_CLK_APCC_MSM8996 policy<{'arm64': 'y'}> +CONFIG_QCOM_CLK_APCS_MSM8916 policy<{'arm64': 'y'}> +CONFIG_QCOM_CLK_RPM policy<{'arm64': 'y'}> +CONFIG_QCOM_CLK_RPMH policy<{'arm64': 'y'}> +CONFIG_QCOM_CLK_SMD_RPM policy<{'arm64': 'y'}> +CONFIG_QCOM_COINCELL policy<{'arm64': 'm'}> +CONFIG_QCOM_COMMAND_DB policy<{'arm64': 'y'}> +CONFIG_QCOM_CPR policy<{'arm64': 'y'}> +CONFIG_QCOM_CPUCP_MBOX policy<{'arm64': 'm'}> +CONFIG_QCOM_EBI2 policy<{'arm64': 'y'}> +CONFIG_QCOM_EMAC policy<{'arm64': 'm'}> +CONFIG_QCOM_FALKOR_ERRATUM_1003 policy<{'arm64': 'y'}> +CONFIG_QCOM_FALKOR_ERRATUM_1009 policy<{'arm64': 'y'}> +CONFIG_QCOM_FALKOR_ERRATUM_E1041 policy<{'arm64': 'y'}> +CONFIG_QCOM_FASTRPC policy<{'arm64': 'm'}> +CONFIG_QCOM_GDSC policy<{'arm64': 'y'}> +CONFIG_QCOM_GENI_SE policy<{'arm64': 'y'}> +CONFIG_QCOM_GPI_DMA policy<{'arm64': 'm'}> +CONFIG_QCOM_GSBI policy<{'arm64': 'm'}> +CONFIG_QCOM_HFPLL policy<{'arm64': 'y'}> +CONFIG_QCOM_HIDMA policy<{'arm64': 'y'}> +CONFIG_QCOM_HIDMA_MGMT policy<{'arm64': 'y'}> +CONFIG_QCOM_ICC_BWMON policy<{'arm64': 'm'}> +CONFIG_QCOM_INLINE_CRYPTO_ENGINE policy<{'arm64': 'm'}> +CONFIG_QCOM_IOMMU policy<{'arm64': 'y'}> +CONFIG_QCOM_IPA policy<{'arm64': 'm'}> +CONFIG_QCOM_IPCC policy<{'arm64': 'y'}> +CONFIG_QCOM_IRQ_COMBINER policy<{'arm64': 'y'}> +CONFIG_QCOM_KRYO_L2_ACCESSORS policy<{'arm64': 'y'}> +CONFIG_QCOM_L2_PMU policy<{'arm64': 'y'}> +CONFIG_QCOM_L3_PMU policy<{'arm64': 'y'}> +CONFIG_QCOM_LLCC policy<{'arm64': 'y'}> +CONFIG_QCOM_LMH policy<{'arm64': 'm'}> +CONFIG_QCOM_MDT_LOADER policy<{'arm64': 'm'}> +CONFIG_QCOM_MPM policy<{'arm64': 'y'}> +CONFIG_QCOM_NET_PHYLIB policy<{'arm64': 'y'}> +CONFIG_QCOM_OCMEM policy<{'arm64': 'm'}> +CONFIG_QCOM_PBS policy<{'arm64': 'm'}> +CONFIG_QCOM_PDC policy<{'arm64': 'y'}> +CONFIG_QCOM_PDR_HELPERS policy<{'arm64': 'y'}> +CONFIG_QCOM_PDR_MSG policy<{'arm64': 'y'}> +CONFIG_QCOM_PD_MAPPER policy<{'arm64': 'm'}> +CONFIG_QCOM_PIL_INFO policy<{'arm64': 'm'}> +CONFIG_QCOM_PMIC_GLINK policy<{'arm64': 'y'}> +CONFIG_QCOM_PMIC_PDCHARGER_ULOG policy<{'arm64': 'm'}> +CONFIG_QCOM_PPE policy<{'arm64': 'n'}> +CONFIG_QCOM_Q6V5_ADSP policy<{'arm64': 'm'}> +CONFIG_QCOM_Q6V5_COMMON policy<{'arm64': 'm'}> +CONFIG_QCOM_Q6V5_MSS policy<{'arm64': 'm'}> +CONFIG_QCOM_Q6V5_PAS policy<{'arm64': 'm'}> +CONFIG_QCOM_Q6V5_WCSS policy<{'arm64': 'm'}> +CONFIG_QCOM_QMI_HELPERS policy<{'arm64': 'y'}> +CONFIG_QCOM_QSEECOM policy<{'arm64': 'y'}> +CONFIG_QCOM_QSEECOM_UEFISECAPP policy<{'arm64': 'y'}> +CONFIG_QCOM_RAMP_CTRL policy<{'arm64': 'm'}> +CONFIG_QCOM_RMTFS_MEM policy<{'arm64': 'm'}> +CONFIG_QCOM_RPMH policy<{'arm64': 'y'}> +CONFIG_QCOM_RPMHPD policy<{'arm64': 'y'}> +CONFIG_QCOM_RPMPD policy<{'arm64': 'y'}> +CONFIG_QCOM_RPM_MASTER_STATS policy<{'arm64': 'm'}> +CONFIG_QCOM_RPROC_COMMON policy<{'arm64': 'm'}> +CONFIG_QCOM_SCM policy<{'arm64': 'y'}> +CONFIG_QCOM_SMD_RPM policy<{'arm64': 'y'}> +CONFIG_QCOM_SMEM policy<{'arm64': 'y'}> +CONFIG_QCOM_SMEM_STATE policy<{'arm64': 'y'}> +CONFIG_QCOM_SMP2P policy<{'arm64': 'y'}> +CONFIG_QCOM_SMSM policy<{'arm64': 'y'}> +CONFIG_QCOM_SOCINFO policy<{'arm64': 'm'}> +CONFIG_QCOM_SPEL policy<{'arm64': 'y'}> +CONFIG_QCOM_SPM policy<{'arm64': 'y'}> +CONFIG_QCOM_SPMI_ADC5 policy<{'arm64': 'm'}> +CONFIG_QCOM_SPMI_ADC5_GEN3 policy<{'arm64': 'n'}> +CONFIG_QCOM_SPMI_ADC_TM5 policy<{'arm64': 'm'}> +CONFIG_QCOM_SPMI_IADC policy<{'arm64': 'm'}> +CONFIG_QCOM_SPMI_RRADC policy<{'arm64': 'm'}> +CONFIG_QCOM_SPMI_TEMP_ALARM policy<{'arm64': 'm'}> +CONFIG_QCOM_SPMI_VADC policy<{'arm64': 'm'}> +CONFIG_QCOM_SSC_BLOCK_BUS policy<{'arm64': 'y'}> +CONFIG_QCOM_STATS policy<{'arm64': 'm'}> +CONFIG_QCOM_SYSMON policy<{'arm64': 'm'}> +CONFIG_QCOM_TSENS policy<{'arm64': 'y'}> +CONFIG_QCOM_TZMEM policy<{'arm64': 'y'}> +CONFIG_QCOM_TZMEM_MODE_GENERIC policy<{'arm64': 'n'}> +CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE policy<{'arm64': 'y'}> +CONFIG_QCOM_UBWC_CONFIG policy<{'arm64': 'm'}> +CONFIG_QCOM_VADC_COMMON policy<{'arm64': 'm'}> +CONFIG_QCOM_WCNSS_CTRL policy<{'arm64': 'm'}> +CONFIG_QCOM_WCNSS_PIL policy<{'arm64': 'm'}> +CONFIG_QCOM_WDT policy<{'arm64': 'm'}> +CONFIG_QCS_CAMCC_615 policy<{'arm64': 'n'}> +CONFIG_QCS_DISPCC_615 policy<{'arm64': 'n'}> +CONFIG_QCS_GCC_404 policy<{'arm64': 'y'}> +CONFIG_QCS_GCC_615 policy<{'arm64': 'n'}> +CONFIG_QCS_GCC_8300 policy<{'arm64': 'm'}> +CONFIG_QCS_GPUCC_615 policy<{'arm64': 'n'}> +CONFIG_QCS_Q6SSTOP_404 policy<{'arm64': 'm'}> +CONFIG_QCS_TURING_404 policy<{'arm64': 'm'}> +CONFIG_QCS_VIDEOCC_615 policy<{'arm64': 'n'}> +CONFIG_QDU_ECPRICC_1000 policy<{'arm64': 'm'}> +CONFIG_QDU_GCC_1000 policy<{'arm64': 'm'}> +CONFIG_QED policy<{'arm64': 'm'}> +CONFIG_QEDE policy<{'arm64': 'm'}> +CONFIG_QEDF policy<{'arm64': 'm'}> +CONFIG_QEDI policy<{'arm64': 'm'}> +CONFIG_QED_FCOE policy<{'arm64': 'y'}> +CONFIG_QED_ISCSI policy<{'arm64': 'y'}> +CONFIG_QED_LL2 policy<{'arm64': 'y'}> +CONFIG_QED_OOO policy<{'arm64': 'y'}> +CONFIG_QED_RDMA policy<{'arm64': 'y'}> +CONFIG_QED_SRIOV policy<{'arm64': 'y'}> +CONFIG_QE_TDM policy<{'arm64': 'y'}> +CONFIG_QFMT_V1 policy<{'arm64': 'm'}> +CONFIG_QFMT_V2 policy<{'arm64': 'y'}> +CONFIG_QLA3XXX policy<{'arm64': 'm'}> +CONFIG_QLCNIC policy<{'arm64': 'm'}> +CONFIG_QLCNIC_DCB policy<{'arm64': 'y'}> +CONFIG_QLCNIC_HWMON policy<{'arm64': 'y'}> +CONFIG_QLCNIC_SRIOV policy<{'arm64': 'y'}> +CONFIG_QNX4FS_FS policy<{'arm64': 'm'}> +CONFIG_QNX6FS_DEBUG policy<{'arm64': 'n'}> +CONFIG_QNX6FS_FS policy<{'arm64': 'm'}> +CONFIG_QORIQ_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_QORIQ_THERMAL policy<{'arm64': 'm'}> +CONFIG_QRTR policy<{'arm64': 'm'}> +CONFIG_QRTR_MHI policy<{'arm64': 'm'}> +CONFIG_QRTR_SMD policy<{'arm64': 'm'}> +CONFIG_QRTR_TUN policy<{'arm64': 'm'}> +CONFIG_QSEMI_PHY policy<{'arm64': 'm'}> +CONFIG_QTNFMAC policy<{'arm64': 'm'}> +CONFIG_QTNFMAC_PCIE policy<{'arm64': 'm'}> +CONFIG_QUEUED_RWLOCKS policy<{'arm64': 'y'}> +CONFIG_QUEUED_SPINLOCKS policy<{'arm64': 'y'}> +CONFIG_QUICC_ENGINE policy<{'arm64': 'y'}> +CONFIG_QUOTA policy<{'arm64': 'y'}> +CONFIG_QUOTACTL policy<{'arm64': 'y'}> +CONFIG_QUOTA_DEBUG policy<{'arm64': 'n'}> +CONFIG_QUOTA_NETLINK_INTERFACE policy<{'arm64': 'y'}> +CONFIG_QUOTA_TREE policy<{'arm64': 'y'}> +CONFIG_R6040 policy<{'arm64': 'm'}> +CONFIG_R8169 policy<{'arm64': 'm'}> +CONFIG_R8169_LEDS policy<{'arm64': 'y'}> +CONFIG_RADIO_ADAPTERS policy<{'arm64': 'm'}> +CONFIG_RADIO_MAXIRADIO policy<{'arm64': 'm'}> +CONFIG_RADIO_SAA7706H policy<{'arm64': 'm'}> +CONFIG_RADIO_SHARK policy<{'arm64': 'm'}> +CONFIG_RADIO_SHARK2 policy<{'arm64': 'm'}> +CONFIG_RADIO_SI470X policy<{'arm64': 'm'}> +CONFIG_RADIO_SI4713 policy<{'arm64': 'm'}> +CONFIG_RADIO_SI476X policy<{'arm64': 'm'}> +CONFIG_RADIO_TEA575X policy<{'arm64': 'm'}> +CONFIG_RADIO_TEA5764 policy<{'arm64': 'm'}> +CONFIG_RADIO_TEF6862 policy<{'arm64': 'm'}> +CONFIG_RAID6_PQ policy<{'arm64': 'm'}> +CONFIG_RAID6_PQ_ARCH policy<{'arm64': 'y'}> +CONFIG_RAID6_PQ_BENCHMARK policy<{'arm64': 'y'}> +CONFIG_RAID_ATTRS policy<{'arm64': 'm'}> +CONFIG_RAMDAX policy<{'arm64': 'y'}> +CONFIG_RANDOM32_SELFTEST policy<{'arm64': 'n'}> +CONFIG_RANDOMIZE_BASE policy<{'arm64': 'y'}> +CONFIG_RANDOMIZE_KSTACK_OFFSET policy<{'arm64': 'y'}> +CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT policy<{'arm64': 'y'}> +CONFIG_RANDOMIZE_MODULE_REGION_FULL policy<{'arm64': 'y'}> +CONFIG_RANDSTRUCT_NONE policy<{'arm64': 'y'}> +CONFIG_RAPIDIO policy<{'arm64': 'y'}> +CONFIG_RAPIDIO_CHMAN policy<{'arm64': 'm'}> +CONFIG_RAPIDIO_CPS_GEN2 policy<{'arm64': 'm'}> +CONFIG_RAPIDIO_CPS_XX policy<{'arm64': 'm'}> +CONFIG_RAPIDIO_DEBUG policy<{'arm64': 'n'}> +CONFIG_RAPIDIO_DISC_TIMEOUT policy<{'arm64': '30'}> +CONFIG_RAPIDIO_DMA_ENGINE policy<{'arm64': 'y'}> +CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS policy<{'arm64': 'n'}> +CONFIG_RAPIDIO_ENUM_BASIC policy<{'arm64': 'm'}> +CONFIG_RAPIDIO_MPORT_CDEV policy<{'arm64': 'm'}> +CONFIG_RAPIDIO_RXS_GEN3 policy<{'arm64': 'm'}> +CONFIG_RAPIDIO_TSI721 policy<{'arm64': 'm'}> +CONFIG_RAS policy<{'arm64': 'y'}> +CONFIG_RATIONAL policy<{'arm64': 'y'}> +CONFIG_RAVB policy<{'arm64': 'm'}> +CONFIG_RAVE_SP_CORE policy<{'arm64': 'm'}> +CONFIG_RAVE_SP_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_RBTREE_TEST policy<{'arm64': 'n'}> +CONFIG_RCAR_DMAC policy<{'arm64': 'm'}> +CONFIG_RCAR_GEN3_THERMAL policy<{'arm64': 'm'}> +CONFIG_RCAR_MFIS policy<{'arm64': 'n'}> +CONFIG_RCAR_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_RCAR_THERMAL policy<{'arm64': 'm'}> +CONFIG_RCU_CPU_STALL_CPUTIME policy<{'arm64': 'y'}> +CONFIG_RCU_CPU_STALL_TIMEOUT policy<{'arm64': '60'}> +CONFIG_RCU_EQS_DEBUG policy<{'arm64': 'n'}> +CONFIG_RCU_EXPERT policy<{'arm64': 'n'}> +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT policy<{'arm64': '0'}> +CONFIG_RCU_NEED_SEGCBLIST policy<{'arm64': 'y'}> +CONFIG_RCU_NOCB_CPU_DEFAULT_ALL policy<{'arm64': 'n'}> +CONFIG_RCU_REF_SCALE_TEST policy<{'arm64': 'n'}> +CONFIG_RCU_SCALE_TEST policy<{'arm64': 'n'}> +CONFIG_RCU_STALL_COMMON policy<{'arm64': 'y'}> +CONFIG_RCU_TORTURE_TEST policy<{'arm64': 'n'}> +CONFIG_RCU_TRACE policy<{'arm64': 'y'}> +CONFIG_RC_ATI_REMOTE policy<{'arm64': 'm'}> +CONFIG_RC_CORE policy<{'arm64': 'm'}> +CONFIG_RC_DECODERS policy<{'arm64': 'y'}> +CONFIG_RC_DEVICES policy<{'arm64': 'y'}> +CONFIG_RC_LOOPBACK policy<{'arm64': 'm'}> +CONFIG_RC_MAP policy<{'arm64': 'm'}> +CONFIG_RC_XBOX_DVD policy<{'arm64': 'm'}> +CONFIG_RDMA_RXE policy<{'arm64': 'm'}> +CONFIG_RDMA_SIW policy<{'arm64': 'm'}> +CONFIG_RDS policy<{'arm64': 'm'}> +CONFIG_RDS_DEBUG policy<{'arm64': 'n'}> +CONFIG_RDS_RDMA policy<{'arm64': 'm'}> +CONFIG_RDS_TCP policy<{'arm64': 'm'}> +CONFIG_RD_BZIP2 policy<{'arm64': 'y'}> +CONFIG_RD_GZIP policy<{'arm64': 'y'}> +CONFIG_RD_LZ4 policy<{'arm64': 'y'}> +CONFIG_RD_LZMA policy<{'arm64': 'y'}> +CONFIG_RD_LZO policy<{'arm64': 'y'}> +CONFIG_RD_XZ policy<{'arm64': 'y'}> +CONFIG_RD_ZSTD policy<{'arm64': 'y'}> +CONFIG_READABLE_ASM policy<{'arm64': 'n'}> +CONFIG_REALTEK_AUTOPM policy<{'arm64': 'y'}> +CONFIG_REALTEK_PHY policy<{'arm64': 'm'}> +CONFIG_REALTEK_PHY_HWMON policy<{'arm64': 'y'}> +CONFIG_REBOOT_MODE policy<{'arm64': 'm'}> +CONFIG_REED_SOLOMON policy<{'arm64': 'm'}> +CONFIG_REED_SOLOMON_DEC16 policy<{'arm64': 'y'}> +CONFIG_REED_SOLOMON_DEC8 policy<{'arm64': 'y'}> +CONFIG_REED_SOLOMON_ENC8 policy<{'arm64': 'y'}> +CONFIG_REED_SOLOMON_TEST policy<{'arm64': 'n'}> +CONFIG_REGMAP policy<{'arm64': 'y'}> +CONFIG_REGMAP_AC97 policy<{'arm64': 'm'}> +CONFIG_REGMAP_I2C policy<{'arm64': 'y'}> +CONFIG_REGMAP_I3C policy<{'arm64': 'm'}> +CONFIG_REGMAP_IRQ policy<{'arm64': 'y'}> +CONFIG_REGMAP_MMIO policy<{'arm64': 'y'}> +CONFIG_REGMAP_SCCB policy<{'arm64': 'm'}> +CONFIG_REGMAP_SLIMBUS policy<{'arm64': 'm'}> +CONFIG_REGMAP_SOUNDWIRE policy<{'arm64': 'm'}> +CONFIG_REGMAP_SOUNDWIRE_MBQ policy<{'arm64': 'm'}> +CONFIG_REGMAP_SPI policy<{'arm64': 'y'}> +CONFIG_REGMAP_SPI_AVMM policy<{'arm64': 'm'}> +CONFIG_REGMAP_SPMI policy<{'arm64': 'y'}> +CONFIG_REGMAP_W1 policy<{'arm64': 'm'}> +CONFIG_REGULATOR policy<{'arm64': 'y'}> +CONFIG_REGULATOR_88PG86X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_88PM800 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_88PM8607 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_88PM886 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_AAT2870 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_ACT8865 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_ACT8945A policy<{'arm64': 'm'}> +CONFIG_REGULATOR_AD5398 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_ADP5055 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_ANATOP policy<{'arm64': 'm'}> +CONFIG_REGULATOR_ARIZONA_LDO1 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_ARIZONA_MICSUPP policy<{'arm64': 'm'}> +CONFIG_REGULATOR_ARM_SCMI policy<{'arm64': 'y'}> +CONFIG_REGULATOR_AS3711 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_AS3722 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_ATC260X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_AW37503 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_AXP20X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_BCM590XX policy<{'arm64': 'm'}> +CONFIG_REGULATOR_BD71815 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_BD71828 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_BD718XX policy<{'arm64': 'm'}> +CONFIG_REGULATOR_BD9571MWV policy<{'arm64': 'm'}> +CONFIG_REGULATOR_BD957XMUF policy<{'arm64': 'm'}> +CONFIG_REGULATOR_BD96801 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_CPCAP policy<{'arm64': 'm'}> +CONFIG_REGULATOR_CROS_EC policy<{'arm64': 'm'}> +CONFIG_REGULATOR_DA903X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_DA9052 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_DA9055 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_DA9062 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_DA9063 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_DA9121 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_DA9210 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_DA9211 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_DEBUG policy<{'arm64': 'n'}> +CONFIG_REGULATOR_DUMMY_CONSUMER policy<{'arm64': 'n'}> +CONFIG_REGULATOR_FAN53555 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_FAN53880 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_FP9931 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_GPIO policy<{'arm64': 'm'}> +CONFIG_REGULATOR_HI6421 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_HI6421V530 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_HI6421V600 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_HI655X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_ISL6271A policy<{'arm64': 'm'}> +CONFIG_REGULATOR_ISL9305 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LM363X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LOCHNAGAR policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LP3971 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LP3972 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LP872X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LP873X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LP8755 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LP87565 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LP8788 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LTC3589 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_LTC3676 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX14577 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX1586 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX20086 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX20411 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX5970 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX77503 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX77541 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX77620 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX77650 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX77675 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_MAX77686 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX77693 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX77802 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX77826 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX77838 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_MAX77857 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX8649 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX8660 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX8893 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX8907 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX8925 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX8952 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX8973 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX8997 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MAX8998 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MC13783 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MC13892 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MC13XXX_CORE policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MCP16502 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MP5416 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MP8859 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MP886X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MPQ7920 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6311 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6315 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6316 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_MT6323 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6331 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6332 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6357 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6358 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6359 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6360 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6363 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_MT6370 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6380 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MT6397 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_MTK_DVFSRC policy<{'arm64': 'm'}> +CONFIG_REGULATOR_NETLINK_EVENTS policy<{'arm64': 'y'}> +CONFIG_REGULATOR_PALMAS policy<{'arm64': 'm'}> +CONFIG_REGULATOR_PCA9450 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_PF0900 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_PF530X policy<{'arm64': 'n'}> +CONFIG_REGULATOR_PF8X00 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_PF9453 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_PFUZE100 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_PV88060 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_PV88080 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_PV88090 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_PWM policy<{'arm64': 'm'}> +CONFIG_REGULATOR_QCOM_LABIBB policy<{'arm64': 'm'}> +CONFIG_REGULATOR_QCOM_PM8008 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_QCOM_REFGEN policy<{'arm64': 'y'}> +CONFIG_REGULATOR_QCOM_RPM policy<{'arm64': 'y'}> +CONFIG_REGULATOR_QCOM_RPMH policy<{'arm64': 'y'}> +CONFIG_REGULATOR_QCOM_SMD_RPM policy<{'arm64': 'y'}> +CONFIG_REGULATOR_QCOM_SPMI policy<{'arm64': 'y'}> +CONFIG_REGULATOR_QCOM_USB_VBUS policy<{'arm64': 'y'}> +CONFIG_REGULATOR_RAA215300 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_RC5T583 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RK808 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RN5T618 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_ROHM policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT4801 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT4803 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT4831 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT5033 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT5120 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT5133 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_RT5190A policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT5739 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT5759 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT6160 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT6190 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT6245 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RT8092 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_RTMV20 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RTQ2134 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RTQ2208 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RTQ6752 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_RZG2L_VBCTRL policy<{'arm64': 'y'}> +CONFIG_REGULATOR_SC2731 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_SGM3804 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_SKY81452 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_SLG51000 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_STM32_BOOSTER policy<{'arm64': 'm'}> +CONFIG_REGULATOR_STM32_PWR policy<{'arm64': 'y'}> +CONFIG_REGULATOR_STM32_VREFBUF policy<{'arm64': 'm'}> +CONFIG_REGULATOR_STPMIC1 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_SUN20I policy<{'arm64': 'm'}> +CONFIG_REGULATOR_SY7636A policy<{'arm64': 'm'}> +CONFIG_REGULATOR_SY8106A policy<{'arm64': 'm'}> +CONFIG_REGULATOR_SY8824X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_SY8827N policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS51632 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS6105X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS62360 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS6286X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS6287X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS65023 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS6507X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS65086 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS65090 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS65132 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS65185 policy<{'arm64': 'n'}> +CONFIG_REGULATOR_TPS65218 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS65219 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS6524X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS6586X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS65910 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS65912 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TPS6594 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_TWL4030 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_USERSPACE_CONSUMER policy<{'arm64': 'm'}> +CONFIG_REGULATOR_VCTRL policy<{'arm64': 'm'}> +CONFIG_REGULATOR_VEXPRESS policy<{'arm64': 'm'}> +CONFIG_REGULATOR_VIRTUAL_CONSUMER policy<{'arm64': 'm'}> +CONFIG_REGULATOR_VQMMC_IPQ4019 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_WM831X policy<{'arm64': 'm'}> +CONFIG_REGULATOR_WM8350 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_WM8400 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_WM8994 policy<{'arm64': 'm'}> +CONFIG_RELAY policy<{'arm64': 'y'}> +CONFIG_RELOCATABLE policy<{'arm64': 'y'}> +CONFIG_RELR policy<{'arm64': 'y'}> +CONFIG_REMOTEPROC policy<{'arm64': 'y'}> +CONFIG_REMOTEPROC_CDEV policy<{'arm64': 'y'}> +CONFIG_REMOTE_TARGET policy<{'arm64': 'm'}> +CONFIG_RENESAS_DMA policy<{'arm64': 'y'}> +CONFIG_RENESAS_ETHER_SWITCH policy<{'arm64': 'm'}> +CONFIG_RENESAS_GEN4_PTP policy<{'arm64': 'm'}> +CONFIG_RENESAS_I3C policy<{'arm64': 'n'}> +CONFIG_RENESAS_IRQC policy<{'arm64': 'y'}> +CONFIG_RENESAS_OSTM policy<{'arm64': 'y'}> +CONFIG_RENESAS_PHY policy<{'arm64': 'm'}> +CONFIG_RENESAS_RPCIF policy<{'arm64': 'm'}> +CONFIG_RENESAS_RZAWDT policy<{'arm64': 'm'}> +CONFIG_RENESAS_RZG2LWDT policy<{'arm64': 'm'}> +CONFIG_RENESAS_RZG2L_IRQC policy<{'arm64': 'y'}> +CONFIG_RENESAS_RZN1WDT policy<{'arm64': 'm'}> +CONFIG_RENESAS_RZT2H_ICU policy<{'arm64': 'y'}> +CONFIG_RENESAS_RZV2HWDT policy<{'arm64': 'n'}> +CONFIG_RENESAS_RZV2H_ICU policy<{'arm64': 'y'}> +CONFIG_RENESAS_USB_DMAC policy<{'arm64': 'm'}> +CONFIG_RENESAS_WDT policy<{'arm64': 'm'}> +CONFIG_RENESAS_WWDT policy<{'arm64': 'n'}> +CONFIG_RESET_A10SR policy<{'arm64': 'm'}> +CONFIG_RESET_ATTACK_MITIGATION policy<{'arm64': 'y'}> +CONFIG_RESET_BERLIN policy<{'arm64': 'y'}> +CONFIG_RESET_CONTROLLER policy<{'arm64': 'y'}> +CONFIG_RESET_GPIO policy<{'arm64': 'm'}> +CONFIG_RESET_HISI policy<{'arm64': 'y'}> +CONFIG_RESET_IMX7 policy<{'arm64': 'y'}> +CONFIG_RESET_IMX8MP_AUDIOMIX policy<{'arm64': 'm'}> +CONFIG_RESET_IMX_SCU policy<{'arm64': 'n'}> +CONFIG_RESET_MCHP_SPARX5 policy<{'arm64': 'y'}> +CONFIG_RESET_MESON policy<{'arm64': 'y'}> +CONFIG_RESET_MESON_AUDIO_ARB policy<{'arm64': 'm'}> +CONFIG_RESET_MESON_AUX policy<{'arm64': 'm'}> +CONFIG_RESET_MESON_COMMON policy<{'arm64': 'y'}> +CONFIG_RESET_NPCM policy<{'arm64': 'y'}> +CONFIG_RESET_NUVOTON_MA35D1 policy<{'arm64': 'y'}> +CONFIG_RESET_POLARFIRE_SOC policy<{'arm64': 'y'}> +CONFIG_RESET_QCOM_AOSS policy<{'arm64': 'y'}> +CONFIG_RESET_QCOM_PDC policy<{'arm64': 'm'}> +CONFIG_RESET_RZG2L_USBPHY_CTRL policy<{'arm64': 'y'}> +CONFIG_RESET_RZV2H_USB2PHY policy<{'arm64': 'n'}> +CONFIG_RESET_SCMI policy<{'arm64': 'm'}> +CONFIG_RESET_SIMPLE policy<{'arm64': 'y'}> +CONFIG_RESET_SUNXI policy<{'arm64': 'y'}> +CONFIG_RESET_TEGRA_BPMP policy<{'arm64': 'y'}> +CONFIG_RESET_TI_SCI policy<{'arm64': 'm'}> +CONFIG_RESET_TI_SYSCON policy<{'arm64': 'm'}> +CONFIG_RESET_TI_TPS380X policy<{'arm64': 'm'}> +CONFIG_RESET_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_RETU_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_RFD77402 policy<{'arm64': 'm'}> +CONFIG_RFD_FTL policy<{'arm64': 'm'}> +CONFIG_RFKILL policy<{'arm64': 'y'}> +CONFIG_RFKILL_GPIO policy<{'arm64': 'm'}> +CONFIG_RFKILL_INPUT policy<{'arm64': 'y'}> +CONFIG_RFKILL_LEDS policy<{'arm64': 'y'}> +CONFIG_RFS_ACCEL policy<{'arm64': 'y'}> +CONFIG_RICHTEK_RTQ6056 policy<{'arm64': 'm'}> +CONFIG_RING_BUFFER policy<{'arm64': 'y'}> +CONFIG_RING_BUFFER_BENCHMARK policy<{'arm64': 'n'}> +CONFIG_RING_BUFFER_PERSISTENT_INJECT policy<{'arm64': 'n'}> +CONFIG_RING_BUFFER_STARTUP_TEST policy<{'arm64': 'n'}> +CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS policy<{'arm64': 'n'}> +CONFIG_RIONET policy<{'arm64': 'm'}> +CONFIG_RIONET_RX_SIZE policy<{'arm64': '128'}> +CONFIG_RIONET_TX_SIZE policy<{'arm64': '128'}> +CONFIG_RMI4_2D_SENSOR policy<{'arm64': 'y'}> +CONFIG_RMI4_CORE policy<{'arm64': 'm'}> +CONFIG_RMI4_F03 policy<{'arm64': 'y'}> +CONFIG_RMI4_F03_SERIO policy<{'arm64': 'm'}> +CONFIG_RMI4_F11 policy<{'arm64': 'y'}> +CONFIG_RMI4_F12 policy<{'arm64': 'y'}> +CONFIG_RMI4_F1A policy<{'arm64': 'n'}> +CONFIG_RMI4_F21 policy<{'arm64': 'n'}> +CONFIG_RMI4_F30 policy<{'arm64': 'y'}> +CONFIG_RMI4_F34 policy<{'arm64': 'y'}> +CONFIG_RMI4_F3A policy<{'arm64': 'y'}> +CONFIG_RMI4_F54 policy<{'arm64': 'y'}> +CONFIG_RMI4_F55 policy<{'arm64': 'y'}> +CONFIG_RMI4_I2C policy<{'arm64': 'm'}> +CONFIG_RMI4_SMB policy<{'arm64': 'm'}> +CONFIG_RMI4_SPI policy<{'arm64': 'm'}> +CONFIG_RMNET policy<{'arm64': 'm'}> +CONFIG_RN5T618_ADC policy<{'arm64': 'm'}> +CONFIG_RN5T618_POWER policy<{'arm64': 'm'}> +CONFIG_RN5T618_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_ROCKCHIP_ANALOGIX_DP policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_CDN_DP policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_DTPM policy<{'arm64': 'm'}> +CONFIG_ROCKCHIP_DW_DP policy<{'arm64': 'n'}> +CONFIG_ROCKCHIP_DW_HDMI policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_DW_HDMI_QP policy<{'arm64': 'n'}> +CONFIG_ROCKCHIP_DW_MIPI_DSI policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_DW_MIPI_DSI2 policy<{'arm64': 'n'}> +CONFIG_ROCKCHIP_ERRATUM_3568002 policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_ERRATUM_3588001 policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_GRF policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_INNO_HDMI policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_IODOMAIN policy<{'arm64': 'm'}> +CONFIG_ROCKCHIP_IOMMU policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_LVDS policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_MBOX policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_PHY policy<{'arm64': 'm'}> +CONFIG_ROCKCHIP_PM_DOMAINS policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_RGB policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_RK3066_HDMI policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_SARADC policy<{'arm64': 'm'}> +CONFIG_ROCKCHIP_THERMAL policy<{'arm64': 'm'}> +CONFIG_ROCKCHIP_TIMER policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_VOP policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_VOP2 policy<{'arm64': 'y'}> +CONFIG_ROCKER policy<{'arm64': 'm'}> +CONFIG_ROHM_BD79112 policy<{'arm64': 'n'}> +CONFIG_ROHM_BD79124 policy<{'arm64': 'n'}> +CONFIG_ROHM_BM1390 policy<{'arm64': 'm'}> +CONFIG_ROHM_BU27034 policy<{'arm64': 'm'}> +CONFIG_ROMFS_BACKED_BY_BLOCK policy<{'arm64': 'y'}> +CONFIG_ROMFS_BACKED_BY_BOTH policy<{'arm64': 'n'}> +CONFIG_ROMFS_BACKED_BY_MTD policy<{'arm64': 'n'}> +CONFIG_ROMFS_FS policy<{'arm64': 'm'}> +CONFIG_ROMFS_ON_BLOCK policy<{'arm64': 'y'}> +CONFIG_RPCSEC_GSS_KRB5 policy<{'arm64': 'm'}> +CONFIG_RPMB policy<{'arm64': 'n'}> +CONFIG_RPMSG policy<{'arm64': 'y'}> +CONFIG_RPMSG_CHAR policy<{'arm64': 'y'}> +CONFIG_RPMSG_CTRL policy<{'arm64': 'm'}> +CONFIG_RPMSG_MTK_SCP policy<{'arm64': 'm'}> +CONFIG_RPMSG_NS policy<{'arm64': 'm'}> +CONFIG_RPMSG_QCOM_GLINK policy<{'arm64': 'y'}> +CONFIG_RPMSG_QCOM_GLINK_RPM policy<{'arm64': 'y'}> +CONFIG_RPMSG_QCOM_GLINK_SMEM policy<{'arm64': 'm'}> +CONFIG_RPMSG_QCOM_SMD policy<{'arm64': 'y'}> +CONFIG_RPMSG_TTY policy<{'arm64': 'm'}> +CONFIG_RPMSG_VIRTIO policy<{'arm64': 'm'}> +CONFIG_RPMSG_WWAN_CTRL policy<{'arm64': 'm'}> +CONFIG_RPR0521 policy<{'arm64': 'm'}> +CONFIG_RPS policy<{'arm64': 'y'}> +CONFIG_RSEQ policy<{'arm64': 'y'}> +CONFIG_RSEQ_DEBUG_DEFAULT_ENABLE policy<{'arm64': 'n'}> +CONFIG_RSEQ_STATS policy<{'arm64': 'n'}> +CONFIG_RSI_91X policy<{'arm64': 'm'}> +CONFIG_RSI_COEX policy<{'arm64': 'y'}> +CONFIG_RSI_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_RSI_SDIO policy<{'arm64': 'm'}> +CONFIG_RSI_USB policy<{'arm64': 'm'}> +CONFIG_RST_RCAR policy<{'arm64': 'y'}> +CONFIG_RT2400PCI policy<{'arm64': 'm'}> +CONFIG_RT2500PCI policy<{'arm64': 'm'}> +CONFIG_RT2500USB policy<{'arm64': 'm'}> +CONFIG_RT2800PCI policy<{'arm64': 'm'}> +CONFIG_RT2800PCI_RT3290 policy<{'arm64': 'y'}> +CONFIG_RT2800PCI_RT33XX policy<{'arm64': 'y'}> +CONFIG_RT2800PCI_RT35XX policy<{'arm64': 'y'}> +CONFIG_RT2800PCI_RT53XX policy<{'arm64': 'y'}> +CONFIG_RT2800USB policy<{'arm64': 'm'}> +CONFIG_RT2800USB_RT33XX policy<{'arm64': 'y'}> +CONFIG_RT2800USB_RT3573 policy<{'arm64': 'y'}> +CONFIG_RT2800USB_RT35XX policy<{'arm64': 'y'}> +CONFIG_RT2800USB_RT53XX policy<{'arm64': 'y'}> +CONFIG_RT2800USB_RT55XX policy<{'arm64': 'y'}> +CONFIG_RT2800USB_UNKNOWN policy<{'arm64': 'y'}> +CONFIG_RT2800_LIB policy<{'arm64': 'm'}> +CONFIG_RT2800_LIB_MMIO policy<{'arm64': 'm'}> +CONFIG_RT2X00 policy<{'arm64': 'm'}> +CONFIG_RT2X00_DEBUG policy<{'arm64': 'n'}> +CONFIG_RT2X00_LIB policy<{'arm64': 'm'}> +CONFIG_RT2X00_LIB_CRYPTO policy<{'arm64': 'y'}> +CONFIG_RT2X00_LIB_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_RT2X00_LIB_FIRMWARE policy<{'arm64': 'y'}> +CONFIG_RT2X00_LIB_LEDS policy<{'arm64': 'y'}> +CONFIG_RT2X00_LIB_MMIO policy<{'arm64': 'm'}> +CONFIG_RT2X00_LIB_PCI policy<{'arm64': 'm'}> +CONFIG_RT2X00_LIB_USB policy<{'arm64': 'm'}> +CONFIG_RT61PCI policy<{'arm64': 'm'}> +CONFIG_RT73USB policy<{'arm64': 'm'}> +CONFIG_RTASE policy<{'arm64': 'n'}> +CONFIG_RTC_CLASS policy<{'arm64': 'y'}> +CONFIG_RTC_DEBUG policy<{'arm64': 'n'}> +CONFIG_RTC_DRV_88PM80X policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_88PM860X policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_88PM886 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_ABB5ZES3 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_ABEOZ9 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_ABX80X policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_AMLOGIC_A4 policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_ARMADA38X policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_AS3722 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_BBNSM policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_BD70528 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_BQ32K policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_CADENCE policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_CPCAP policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_CROS_EC policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DA9052 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DA9055 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DA9063 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1286 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1302 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1305 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1307 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1307_CENTURY policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_DS1343 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1347 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1374 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1374_WDT policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_DS1390 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1511 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1553 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1672 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1685 policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_DS1685_FAMILY policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS1689 policy<{'arm64': 'n'}> +CONFIG_RTC_DRV_DS17285 policy<{'arm64': 'n'}> +CONFIG_RTC_DRV_DS1742 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS17485 policy<{'arm64': 'n'}> +CONFIG_RTC_DRV_DS17885 policy<{'arm64': 'n'}> +CONFIG_RTC_DRV_DS2404 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS3232 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_DS3232_HWMON policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_EFI policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_EM3027 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_FM3130 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_FSL_FTM_ALARM policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_FTRTC010 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_GOLDFISH policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_HID_SENSOR_TIME policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_HYM8563 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_IMXDI policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_IMX_BBM_SCMI policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_IMX_SC policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_ISL12022 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_ISL12026 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_ISL1208 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_LP8788 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_M41T80 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_M41T80_WDT policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_M41T93 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_M41T94 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_M48T35 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_M48T59 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_M48T86 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MA35D1 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX31335 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX6900 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX6902 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX6916 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX77686 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX8907 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX8925 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX8997 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX8998 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MC13XXX policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MCP795 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MESON_VRTC policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MSM6242 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MT2712 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MT6397 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MT7622 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MV policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_MXC policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MXC_V2 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_NCT3018Y policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_NTXEC policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_NVIDIA_VRS10 policy<{'arm64': 'n'}> +CONFIG_RTC_DRV_OPTEE policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PALMAS policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PCF2123 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PCF2127 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PCF85063 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PCF8523 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PCF85363 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PCF8563 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PCF8583 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PL030 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PL031 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_PM8XXX policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_R7301 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_R9701 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RC5T583 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RC5T619 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RENESAS_RTCA3 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RK808 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RP5C01 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RS5C348 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RS5C372 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RTD119X policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_RV3028 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RV3029C2 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RV3029_HWMON policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_RV3032 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RV8803 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RX4581 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RX6110 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RX8010 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RX8025 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RX8111 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_RX8581 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_S32G policy<{'arm64': 'n'}> +CONFIG_RTC_DRV_S35390A policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_SC27XX policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_SD2405AL policy<{'arm64': 'n'}> +CONFIG_RTC_DRV_SD3078 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_SH policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_SNVS policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_STK17TA8 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_STM32 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_SUN6I policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_TEGRA policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_TEST policy<{'arm64': 'n'}> +CONFIG_RTC_DRV_TI_K3 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_TPS6586X policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_TPS65910 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_TPS6594 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_TWL4030 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_WM831X policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_WM8350 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_X1205 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_XGENE policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_ZYNQMP policy<{'arm64': 'm'}> +CONFIG_RTC_HCTOSYS policy<{'arm64': 'y'}> +CONFIG_RTC_HCTOSYS_DEVICE policy<{'arm64': '"rtc0"'}> +CONFIG_RTC_I2C_AND_SPI policy<{'arm64': 'y'}> +CONFIG_RTC_INTF_DEV policy<{'arm64': 'y'}> +CONFIG_RTC_INTF_DEV_UIE_EMUL policy<{'arm64': 'n'}> +CONFIG_RTC_INTF_PROC policy<{'arm64': 'y'}> +CONFIG_RTC_INTF_SYSFS policy<{'arm64': 'y'}> +CONFIG_RTC_LIB policy<{'arm64': 'y'}> +CONFIG_RTC_NVMEM policy<{'arm64': 'y'}> +CONFIG_RTC_SYSTOHC policy<{'arm64': 'y'}> +CONFIG_RTC_SYSTOHC_DEVICE policy<{'arm64': '"rtc0"'}> +CONFIG_RTD119X_WATCHDOG policy<{'arm64': 'y'}> +CONFIG_RTK_SYSTIMER policy<{'arm64': 'n'}> +CONFIG_RTL8180 policy<{'arm64': 'm'}> +CONFIG_RTL8187 policy<{'arm64': 'm'}> +CONFIG_RTL8187_LEDS policy<{'arm64': 'y'}> +CONFIG_RTL8188EE policy<{'arm64': 'm'}> +CONFIG_RTL8192CE policy<{'arm64': 'm'}> +CONFIG_RTL8192CU policy<{'arm64': 'm'}> +CONFIG_RTL8192C_COMMON policy<{'arm64': 'm'}> +CONFIG_RTL8192DE policy<{'arm64': 'm'}> +CONFIG_RTL8192DU policy<{'arm64': 'm'}> +CONFIG_RTL8192D_COMMON policy<{'arm64': 'm'}> +CONFIG_RTL8192EE policy<{'arm64': 'm'}> +CONFIG_RTL8192SE policy<{'arm64': 'm'}> +CONFIG_RTL8723AE policy<{'arm64': 'm'}> +CONFIG_RTL8723BE policy<{'arm64': 'm'}> +CONFIG_RTL8723BS policy<{'arm64': 'm'}> +CONFIG_RTL8723_COMMON policy<{'arm64': 'm'}> +CONFIG_RTL8821AE policy<{'arm64': 'm'}> +CONFIG_RTL8XXXU policy<{'arm64': 'm'}> +CONFIG_RTL8XXXU_UNTESTED policy<{'arm64': 'y'}> +CONFIG_RTLBTCOEXIST policy<{'arm64': 'm'}> +CONFIG_RTLWIFI policy<{'arm64': 'm'}> +CONFIG_RTLWIFI_DEBUG policy<{'arm64': 'y'}> +CONFIG_RTLWIFI_PCI policy<{'arm64': 'm'}> +CONFIG_RTLWIFI_USB policy<{'arm64': 'm'}> +CONFIG_RTL_CARDS policy<{'arm64': 'm'}> +CONFIG_RTSN policy<{'arm64': 'm'}> +CONFIG_RTW88 policy<{'arm64': 'm'}> +CONFIG_RTW88_8703B policy<{'arm64': 'm'}> +CONFIG_RTW88_8723CS policy<{'arm64': 'm'}> +CONFIG_RTW88_8723D policy<{'arm64': 'm'}> +CONFIG_RTW88_8723DE policy<{'arm64': 'm'}> +CONFIG_RTW88_8723DS policy<{'arm64': 'm'}> +CONFIG_RTW88_8723DU policy<{'arm64': 'm'}> +CONFIG_RTW88_8723X policy<{'arm64': 'm'}> +CONFIG_RTW88_8812A policy<{'arm64': 'm'}> +CONFIG_RTW88_8812AU policy<{'arm64': 'm'}> +CONFIG_RTW88_8814AE policy<{'arm64': 'n'}> +CONFIG_RTW88_8814AU policy<{'arm64': 'n'}> +CONFIG_RTW88_8821A policy<{'arm64': 'm'}> +CONFIG_RTW88_8821AU policy<{'arm64': 'm'}> +CONFIG_RTW88_8821C policy<{'arm64': 'm'}> +CONFIG_RTW88_8821CE policy<{'arm64': 'm'}> +CONFIG_RTW88_8821CS policy<{'arm64': 'm'}> +CONFIG_RTW88_8821CU policy<{'arm64': 'm'}> +CONFIG_RTW88_8822B policy<{'arm64': 'm'}> +CONFIG_RTW88_8822BE policy<{'arm64': 'm'}> +CONFIG_RTW88_8822BS policy<{'arm64': 'm'}> +CONFIG_RTW88_8822BU policy<{'arm64': 'm'}> +CONFIG_RTW88_8822C policy<{'arm64': 'm'}> +CONFIG_RTW88_8822CE policy<{'arm64': 'm'}> +CONFIG_RTW88_8822CS policy<{'arm64': 'm'}> +CONFIG_RTW88_8822CU policy<{'arm64': 'm'}> +CONFIG_RTW88_88XXA policy<{'arm64': 'm'}> +CONFIG_RTW88_CORE policy<{'arm64': 'm'}> +CONFIG_RTW88_DEBUG policy<{'arm64': 'y'}> +CONFIG_RTW88_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_RTW88_LEDS policy<{'arm64': 'y'}> +CONFIG_RTW88_PCI policy<{'arm64': 'm'}> +CONFIG_RTW88_SDIO policy<{'arm64': 'm'}> +CONFIG_RTW88_USB policy<{'arm64': 'm'}> +CONFIG_RTW89 policy<{'arm64': 'm'}> +CONFIG_RTW89_8851B policy<{'arm64': 'm'}> +CONFIG_RTW89_8851BE policy<{'arm64': 'm'}> +CONFIG_RTW89_8851BU policy<{'arm64': 'n'}> +CONFIG_RTW89_8852A policy<{'arm64': 'm'}> +CONFIG_RTW89_8852AE policy<{'arm64': 'm'}> +CONFIG_RTW89_8852AU policy<{'arm64': 'n'}> +CONFIG_RTW89_8852B policy<{'arm64': 'm'}> +CONFIG_RTW89_8852BE policy<{'arm64': 'm'}> +CONFIG_RTW89_8852BTE policy<{'arm64': 'n'}> +CONFIG_RTW89_8852BU policy<{'arm64': 'm'}> +CONFIG_RTW89_8852B_COMMON policy<{'arm64': 'm'}> +CONFIG_RTW89_8852C policy<{'arm64': 'm'}> +CONFIG_RTW89_8852CE policy<{'arm64': 'm'}> +CONFIG_RTW89_8852CU policy<{'arm64': 'n'}> +CONFIG_RTW89_8922A policy<{'arm64': 'm'}> +CONFIG_RTW89_8922AE policy<{'arm64': 'm'}> +CONFIG_RTW89_8922AU policy<{'arm64': 'n'}> +CONFIG_RTW89_CORE policy<{'arm64': 'm'}> +CONFIG_RTW89_DEBUG policy<{'arm64': 'y'}> +CONFIG_RTW89_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_RTW89_DEBUGMSG policy<{'arm64': 'y'}> +CONFIG_RTW89_PCI policy<{'arm64': 'm'}> +CONFIG_RTW89_USB policy<{'arm64': 'm'}> +CONFIG_RT_GROUP_SCHED policy<{'arm64': 'n'}> +CONFIG_RT_MUTEXES policy<{'arm64': 'y'}> +CONFIG_RUNTIME_TESTING_MENU policy<{'arm64': 'y'}> +CONFIG_RUSTC_HAS_FILE_AS_C_STR policy<{'arm64': 'y'}> +CONFIG_RUSTC_HAS_FILE_WITH_NUL policy<{'arm64': 'y'}> +CONFIG_RUSTC_HAS_SPAN_FILE policy<{'arm64': 'y'}> +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES policy<{'arm64': 'y'}> +CONFIG_RUSTC_LLVM_MAJOR_VERSION policy<{'arm64': '21'}> +CONFIG_RUSTC_LLVM_VERSION policy<{'arm64': '210108'}> +CONFIG_RUSTC_SUPPORTS_ARM64 policy<{'arm64': 'y'}> +CONFIG_RUSTC_VERSION policy<{'arm64': '109301'}> +CONFIG_RUST_IS_AVAILABLE policy<{'arm64': 'y'}> +CONFIG_RV policy<{'arm64': 'y'}> +CONFIG_RVU_ESWITCH policy<{'arm64': 'm'}> +CONFIG_RV_MON_DEADLINE policy<{'arm64': 'n'}> +CONFIG_RV_MON_EVENTS policy<{'arm64': 'y'}> +CONFIG_RV_MON_MAINTENANCE_EVENTS policy<{'arm64': 'y'}> +CONFIG_RV_MON_RTAPP policy<{'arm64': 'n'}> +CONFIG_RV_MON_STALL policy<{'arm64': 'n'}> +CONFIG_RV_MON_WWNR policy<{'arm64': 'y'}> +CONFIG_RV_PER_TASK_MONITORS policy<{'arm64': '2'}> +CONFIG_RV_REACTORS policy<{'arm64': 'y'}> +CONFIG_RV_REACT_PANIC policy<{'arm64': 'y'}> +CONFIG_RV_REACT_PRINTK policy<{'arm64': 'y'}> +CONFIG_RWSEM_SPIN_ON_OWNER policy<{'arm64': 'y'}> +CONFIG_RXGK policy<{'arm64': 'n'}> +CONFIG_RXKAD policy<{'arm64': 'y'}> +CONFIG_RXPERF policy<{'arm64': 'm'}> +CONFIG_RZG2L_ADC policy<{'arm64': 'm'}> +CONFIG_RZG2L_THERMAL policy<{'arm64': 'm'}> +CONFIG_RZG3E_THERMAL policy<{'arm64': 'n'}> +CONFIG_RZG3S_THERMAL policy<{'arm64': 'n'}> +CONFIG_RZT2H_ADC policy<{'arm64': 'n'}> +CONFIG_RZ_DMAC policy<{'arm64': 'm'}> +CONFIG_RZ_MTU3 policy<{'arm64': 'y'}> +CONFIG_RZ_MTU3_CNT policy<{'arm64': 'm'}> +CONFIG_S32G_WDT policy<{'arm64': 'n'}> +CONFIG_SAMPLES policy<{'arm64': 'y'}> +CONFIG_SAMPLE_AUXDISPLAY policy<{'arm64': 'n'}> +CONFIG_SAMPLE_CONFIGFS policy<{'arm64': 'n'}> +CONFIG_SAMPLE_FTRACE_DIRECT policy<{'arm64': 'n'}> +CONFIG_SAMPLE_FTRACE_DIRECT_MULTI policy<{'arm64': 'n'}> +CONFIG_SAMPLE_FTRACE_OPS policy<{'arm64': 'n'}> +CONFIG_SAMPLE_HUNG_TASK policy<{'arm64': 'n'}> +CONFIG_SAMPLE_HW_BREAKPOINT policy<{'arm64': 'n'}> +CONFIG_SAMPLE_KDB policy<{'arm64': 'n'}> +CONFIG_SAMPLE_KFIFO policy<{'arm64': 'n'}> +CONFIG_SAMPLE_KOBJECT policy<{'arm64': 'n'}> +CONFIG_SAMPLE_KPROBES policy<{'arm64': 'n'}> +CONFIG_SAMPLE_QMI_CLIENT policy<{'arm64': 'n'}> +CONFIG_SAMPLE_RPMSG_CLIENT policy<{'arm64': 'n'}> +CONFIG_SAMPLE_TRACE_ARRAY policy<{'arm64': 'm'}> +CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS policy<{'arm64': 'n'}> +CONFIG_SAMPLE_TRACE_EVENTS policy<{'arm64': 'n'}> +CONFIG_SAMPLE_TRACE_PRINTK policy<{'arm64': 'm'}> +CONFIG_SAMPLE_TSM_MR policy<{'arm64': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MBOCHS policy<{'arm64': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MDPY policy<{'arm64': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB policy<{'arm64': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MTTY policy<{'arm64': 'n'}> +CONFIG_SAMPLE_WATCHDOG policy<{'arm64': 'n'}> +CONFIG_SAR_GCC_2130P policy<{'arm64': 'm'}> +CONFIG_SAR_GPUCC_2130P policy<{'arm64': 'm'}> +CONFIG_SATA_ACARD_AHCI policy<{'arm64': 'm'}> +CONFIG_SATA_AHCI policy<{'arm64': 'm'}> +CONFIG_SATA_AHCI_SEATTLE policy<{'arm64': 'm'}> +CONFIG_SATA_DWC policy<{'arm64': 'm'}> +CONFIG_SATA_DWC_OLD_DMA policy<{'arm64': 'y'}> +CONFIG_SATA_HOST policy<{'arm64': 'y'}> +CONFIG_SATA_INIC162X policy<{'arm64': 'm'}> +CONFIG_SATA_MOBILE_LPM_POLICY policy<{'arm64': '3'}> +CONFIG_SATA_MV policy<{'arm64': 'm'}> +CONFIG_SATA_NV policy<{'arm64': 'm'}> +CONFIG_SATA_PMP policy<{'arm64': 'y'}> +CONFIG_SATA_PROMISE policy<{'arm64': 'm'}> +CONFIG_SATA_QSTOR policy<{'arm64': 'm'}> +CONFIG_SATA_RCAR policy<{'arm64': 'm'}> +CONFIG_SATA_SIL policy<{'arm64': 'm'}> +CONFIG_SATA_SIL24 policy<{'arm64': 'm'}> +CONFIG_SATA_SIS policy<{'arm64': 'm'}> +CONFIG_SATA_SVW policy<{'arm64': 'm'}> +CONFIG_SATA_SX4 policy<{'arm64': 'm'}> +CONFIG_SATA_ULI policy<{'arm64': 'm'}> +CONFIG_SATA_VIA policy<{'arm64': 'm'}> +CONFIG_SATA_VITESSE policy<{'arm64': 'm'}> +CONFIG_SATA_ZPODD policy<{'arm64': 'y'}> +CONFIG_SA_CAMCC_8775P policy<{'arm64': 'm'}> +CONFIG_SA_DISPCC_8775P policy<{'arm64': 'm'}> +CONFIG_SA_GCC_8775P policy<{'arm64': 'm'}> +CONFIG_SA_GPUCC_8775P policy<{'arm64': 'm'}> +CONFIG_SA_VIDEOCC_8775P policy<{'arm64': 'm'}> +CONFIG_SBITMAP policy<{'arm64': 'y'}> +CONFIG_SBP_TARGET policy<{'arm64': 'm'}> +CONFIG_SC27XX_ADC policy<{'arm64': 'm'}> +CONFIG_SC92031 policy<{'arm64': 'm'}> +CONFIG_SCA3000 policy<{'arm64': 'm'}> +CONFIG_SCA3300 policy<{'arm64': 'm'}> +CONFIG_SCD30_CORE policy<{'arm64': 'm'}> +CONFIG_SCD30_I2C policy<{'arm64': 'm'}> +CONFIG_SCD30_SERIAL policy<{'arm64': 'm'}> +CONFIG_SCD4X policy<{'arm64': 'm'}> +CONFIG_SCF_TORTURE_TEST policy<{'arm64': 'n'}> +CONFIG_SCHEDSTATS policy<{'arm64': 'y'}> +CONFIG_SCHED_AUTOGROUP policy<{'arm64': 'y'}> +CONFIG_SCHED_CACHE policy<{'arm64': 'y'}> +CONFIG_SCHED_CLUSTER policy<{'arm64': 'y'}> +CONFIG_SCHED_CORE policy<{'arm64': 'y'}> +CONFIG_SCHED_HRTICK policy<{'arm64': 'y'}> +CONFIG_SCHED_HW_PRESSURE policy<{'arm64': 'y'}> +CONFIG_SCHED_INFO policy<{'arm64': 'y'}> +CONFIG_SCHED_MC policy<{'arm64': 'y'}> +CONFIG_SCHED_MM_CID policy<{'arm64': 'y'}> +CONFIG_SCHED_PROXY_EXEC policy<{'arm64': 'n'}> +CONFIG_SCHED_SMT policy<{'arm64': 'y'}> +CONFIG_SCHED_STACK_END_CHECK policy<{'arm64': 'y'}> +CONFIG_SCHED_TRACER policy<{'arm64': 'y'}> +CONFIG_SCREEN_INFO policy<{'arm64': 'y'}> +CONFIG_SCSI policy<{'arm64': 'y'}> +CONFIG_SCSI_3W_9XXX policy<{'arm64': 'm'}> +CONFIG_SCSI_3W_SAS policy<{'arm64': 'm'}> +CONFIG_SCSI_AACRAID policy<{'arm64': 'm'}> +CONFIG_SCSI_ACARD policy<{'arm64': 'm'}> +CONFIG_SCSI_ADVANSYS policy<{'arm64': 'm'}> +CONFIG_SCSI_AIC79XX policy<{'arm64': 'm'}> +CONFIG_SCSI_AIC7XXX policy<{'arm64': 'm'}> +CONFIG_SCSI_AIC94XX policy<{'arm64': 'm'}> +CONFIG_SCSI_AM53C974 policy<{'arm64': 'm'}> +CONFIG_SCSI_ARCMSR policy<{'arm64': 'm'}> +CONFIG_SCSI_BFA_FC policy<{'arm64': 'm'}> +CONFIG_SCSI_BNX2X_FCOE policy<{'arm64': 'm'}> +CONFIG_SCSI_BNX2_ISCSI policy<{'arm64': 'm'}> +CONFIG_SCSI_BUSLOGIC policy<{'arm64': 'm'}> +CONFIG_SCSI_CHELSIO_FCOE policy<{'arm64': 'm'}> +CONFIG_SCSI_COMMON policy<{'arm64': 'y'}> +CONFIG_SCSI_CONSTANTS policy<{'arm64': 'y'}> +CONFIG_SCSI_CXGB3_ISCSI policy<{'arm64': 'm'}> +CONFIG_SCSI_CXGB4_ISCSI policy<{'arm64': 'm'}> +CONFIG_SCSI_DC395x policy<{'arm64': 'm'}> +CONFIG_SCSI_DEBUG policy<{'arm64': 'm'}> +CONFIG_SCSI_DH policy<{'arm64': 'y'}> +CONFIG_SCSI_DH_ALUA policy<{'arm64': 'm'}> +CONFIG_SCSI_DH_EMC policy<{'arm64': 'm'}> +CONFIG_SCSI_DH_HP_SW policy<{'arm64': 'm'}> +CONFIG_SCSI_DH_RDAC policy<{'arm64': 'm'}> +CONFIG_SCSI_DMA policy<{'arm64': 'y'}> +CONFIG_SCSI_DMX3191D policy<{'arm64': 'm'}> +CONFIG_SCSI_EFCT policy<{'arm64': 'm'}> +CONFIG_SCSI_ENCLOSURE policy<{'arm64': 'm'}> +CONFIG_SCSI_ESAS2R policy<{'arm64': 'm'}> +CONFIG_SCSI_FC_ATTRS policy<{'arm64': 'm'}> +CONFIG_SCSI_FDOMAIN policy<{'arm64': 'm'}> +CONFIG_SCSI_FDOMAIN_PCI policy<{'arm64': 'm'}> +CONFIG_SCSI_FLASHPOINT policy<{'arm64': 'y'}> +CONFIG_SCSI_HISI_SAS policy<{'arm64': 'm'}> +CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE policy<{'arm64': 'n'}> +CONFIG_SCSI_HISI_SAS_PCI policy<{'arm64': 'm'}> +CONFIG_SCSI_HPSA policy<{'arm64': 'm'}> +CONFIG_SCSI_HPTIOP policy<{'arm64': 'm'}> +CONFIG_SCSI_IMM policy<{'arm64': 'm'}> +CONFIG_SCSI_INIA100 policy<{'arm64': 'm'}> +CONFIG_SCSI_INITIO policy<{'arm64': 'm'}> +CONFIG_SCSI_IPR policy<{'arm64': 'm'}> +CONFIG_SCSI_IPR_DUMP policy<{'arm64': 'y'}> +CONFIG_SCSI_IPR_TRACE policy<{'arm64': 'y'}> +CONFIG_SCSI_IPS policy<{'arm64': 'm'}> +CONFIG_SCSI_ISCSI_ATTRS policy<{'arm64': 'm'}> +CONFIG_SCSI_IZIP_SLOW_CTR policy<{'arm64': 'n'}> +CONFIG_SCSI_LOGGING policy<{'arm64': 'y'}> +CONFIG_SCSI_LOWLEVEL policy<{'arm64': 'y'}> +CONFIG_SCSI_LOWLEVEL_PCMCIA policy<{'arm64': 'n'}> +CONFIG_SCSI_LPFC policy<{'arm64': 'm'}> +CONFIG_SCSI_LPFC_DEBUG_FS policy<{'arm64': 'n'}> +CONFIG_SCSI_MOD policy<{'arm64': 'y'}> +CONFIG_SCSI_MPI3MR policy<{'arm64': 'm'}> +CONFIG_SCSI_MPT2SAS policy<{'arm64': 'm'}> +CONFIG_SCSI_MPT2SAS_MAX_SGE policy<{'arm64': '128'}> +CONFIG_SCSI_MPT3SAS policy<{'arm64': 'm'}> +CONFIG_SCSI_MPT3SAS_MAX_SGE policy<{'arm64': '128'}> +CONFIG_SCSI_MVSAS policy<{'arm64': 'm'}> +CONFIG_SCSI_MVSAS_DEBUG policy<{'arm64': 'y'}> +CONFIG_SCSI_MVSAS_TASKLET policy<{'arm64': 'n'}> +CONFIG_SCSI_MVUMI policy<{'arm64': 'm'}> +CONFIG_SCSI_MYRB policy<{'arm64': 'm'}> +CONFIG_SCSI_MYRS policy<{'arm64': 'm'}> +CONFIG_SCSI_NETLINK policy<{'arm64': 'y'}> +CONFIG_SCSI_PM8001 policy<{'arm64': 'm'}> +CONFIG_SCSI_PMCRAID policy<{'arm64': 'm'}> +CONFIG_SCSI_PPA policy<{'arm64': 'm'}> +CONFIG_SCSI_PROC_FS policy<{'arm64': 'y'}> +CONFIG_SCSI_QLA_FC policy<{'arm64': 'm'}> +CONFIG_SCSI_QLA_ISCSI policy<{'arm64': 'm'}> +CONFIG_SCSI_QLOGIC_1280 policy<{'arm64': 'm'}> +CONFIG_SCSI_SAS_ATA policy<{'arm64': 'y'}> +CONFIG_SCSI_SAS_ATTRS policy<{'arm64': 'm'}> +CONFIG_SCSI_SAS_HOST_SMP policy<{'arm64': 'y'}> +CONFIG_SCSI_SAS_LIBSAS policy<{'arm64': 'm'}> +CONFIG_SCSI_SCAN_ASYNC policy<{'arm64': 'y'}> +CONFIG_SCSI_SMARTPQI policy<{'arm64': 'm'}> +CONFIG_SCSI_SNIC policy<{'arm64': 'm'}> +CONFIG_SCSI_SNIC_DEBUG_FS policy<{'arm64': 'n'}> +CONFIG_SCSI_SPI_ATTRS policy<{'arm64': 'm'}> +CONFIG_SCSI_SRP_ATTRS policy<{'arm64': 'm'}> +CONFIG_SCSI_STEX policy<{'arm64': 'm'}> +CONFIG_SCSI_SYM53C8XX_2 policy<{'arm64': 'm'}> +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS policy<{'arm64': '16'}> +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE policy<{'arm64': '1'}> +CONFIG_SCSI_SYM53C8XX_MAX_TAGS policy<{'arm64': '64'}> +CONFIG_SCSI_SYM53C8XX_MMIO policy<{'arm64': 'y'}> +CONFIG_SCSI_UFSHCD policy<{'arm64': 'm'}> +CONFIG_SCSI_UFSHCD_PCI policy<{'arm64': 'm'}> +CONFIG_SCSI_UFSHCD_PLATFORM policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_AMD_VERSAL2 policy<{'arm64': 'n'}> +CONFIG_SCSI_UFS_BSG policy<{'arm64': 'y'}> +CONFIG_SCSI_UFS_CDNS_PLATFORM policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_CRYPTO policy<{'arm64': 'y'}> +CONFIG_SCSI_UFS_DWC_TC_PCI policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_DWC_TC_PLATFORM policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_HISI policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_HWMON policy<{'arm64': 'n'}> +CONFIG_SCSI_UFS_MEDIATEK policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_QCOM policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_RENESAS policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_ROCKCHIP policy<{'arm64': 'n'}> +CONFIG_SCSI_UFS_SPRD policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_TI_J721E policy<{'arm64': 'm'}> +CONFIG_SCSI_WD719X policy<{'arm64': 'm'}> +CONFIG_SCTP_DBG_OBJCNT policy<{'arm64': 'n'}> +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE policy<{'arm64': 'n'}> +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256 policy<{'arm64': 'y'}> +CONFIG_SC_CAMCC_7180 policy<{'arm64': 'm'}> +CONFIG_SC_CAMCC_7280 policy<{'arm64': 'm'}> +CONFIG_SC_CAMCC_8180X policy<{'arm64': 'n'}> +CONFIG_SC_CAMCC_8280XP policy<{'arm64': 'm'}> +CONFIG_SC_DISPCC_7180 policy<{'arm64': 'm'}> +CONFIG_SC_DISPCC_7280 policy<{'arm64': 'm'}> +CONFIG_SC_DISPCC_8280XP policy<{'arm64': 'm'}> +CONFIG_SC_GCC_7180 policy<{'arm64': 'm'}> +CONFIG_SC_GCC_7280 policy<{'arm64': 'm'}> +CONFIG_SC_GCC_8180X policy<{'arm64': 'm'}> +CONFIG_SC_GCC_8280XP policy<{'arm64': 'm'}> +CONFIG_SC_GPUCC_7180 policy<{'arm64': 'm'}> +CONFIG_SC_GPUCC_7280 policy<{'arm64': 'm'}> +CONFIG_SC_GPUCC_8280XP policy<{'arm64': 'm'}> +CONFIG_SC_LPASSCC_7280 policy<{'arm64': 'm'}> +CONFIG_SC_LPASSCC_8280XP policy<{'arm64': 'm'}> +CONFIG_SC_LPASS_CORECC_7180 policy<{'arm64': 'm'}> +CONFIG_SC_LPASS_CORECC_7280 policy<{'arm64': 'm'}> +CONFIG_SC_VIDEOCC_7180 policy<{'arm64': 'm'}> +CONFIG_SC_VIDEOCC_7280 policy<{'arm64': 'm'}> +CONFIG_SDIO_UART policy<{'arm64': 'm'}> +CONFIG_SDM_CAMCC_845 policy<{'arm64': 'm'}> +CONFIG_SDM_DISPCC_845 policy<{'arm64': 'm'}> +CONFIG_SDM_GCC_660 policy<{'arm64': 'm'}> +CONFIG_SDM_GCC_845 policy<{'arm64': 'm'}> +CONFIG_SDM_GPUCC_660 policy<{'arm64': 'm'}> +CONFIG_SDM_GPUCC_845 policy<{'arm64': 'm'}> +CONFIG_SDM_LPASSCC_845 policy<{'arm64': 'm'}> +CONFIG_SDM_MMCC_660 policy<{'arm64': 'm'}> +CONFIG_SDM_VIDEOCC_845 policy<{'arm64': 'm'}> +CONFIG_SDP500 policy<{'arm64': 'n'}> +CONFIG_SDR_MAX2175 policy<{'arm64': 'm'}> +CONFIG_SDR_PLATFORM_DRIVERS policy<{'arm64': 'y'}> +CONFIG_SDX_GCC_75 policy<{'arm64': 'm'}> +CONFIG_SD_ADC_MODULATOR policy<{'arm64': 'm'}> +CONFIG_SECCOMP policy<{'arm64': 'y'}> +CONFIG_SECCOMP_CACHE_DEBUG policy<{'arm64': 'n'}> +CONFIG_SECCOMP_FILTER policy<{'arm64': 'y'}> +CONFIG_SECONDARY_TRUSTED_KEYRING policy<{'arm64': 'y'}> +CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN policy<{'arm64': 'n'}> +CONFIG_SECRETMEM policy<{'arm64': 'y'}> +CONFIG_SECTION_MISMATCH_WARN_ONLY policy<{'arm64': 'y'}> +CONFIG_SECURITY policy<{'arm64': 'y'}> +CONFIG_SECURITYFS policy<{'arm64': 'y'}> +CONFIG_SECURITY_APPARMOR policy<{'arm64': 'y'}> +CONFIG_SECURITY_APPARMOR_DEBUG policy<{'arm64': 'n'}> +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY policy<{'arm64': 'y'}> +CONFIG_SECURITY_APPARMOR_HASH policy<{'arm64': 'y'}> +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT policy<{'arm64': 'y'}> +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY policy<{'arm64': 'y'}> +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD policy<{'arm64': 'y'}> +CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS policy<{'arm64': 'y'}> +CONFIG_SECURITY_DMESG_RESTRICT policy<{'arm64': 'y'}> +CONFIG_SECURITY_INFINIBAND policy<{'arm64': 'y'}> +CONFIG_SECURITY_IPE policy<{'arm64': 'n'}> +CONFIG_SECURITY_LANDLOCK policy<{'arm64': 'y'}> +CONFIG_SECURITY_LOADPIN policy<{'arm64': 'n'}> +CONFIG_SECURITY_LOCKDOWN_LSM policy<{'arm64': 'y'}> +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY policy<{'arm64': 'y'}> +CONFIG_SECURITY_NETWORK policy<{'arm64': 'y'}> +CONFIG_SECURITY_NETWORK_XFRM policy<{'arm64': 'y'}> +CONFIG_SECURITY_PATH policy<{'arm64': 'y'}> +CONFIG_SECURITY_PERF_EVENTS_RESTRICT policy<{'arm64': 'n'}> +CONFIG_SECURITY_SELINUX policy<{'arm64': 'y'}> +CONFIG_SECURITY_SELINUX_AVC_HASH_BITS policy<{'arm64': '9'}> +CONFIG_SECURITY_SELINUX_AVC_STATS policy<{'arm64': 'y'}> +CONFIG_SECURITY_SELINUX_BOOTPARAM policy<{'arm64': 'y'}> +CONFIG_SECURITY_SELINUX_DEBUG policy<{'arm64': 'n'}> +CONFIG_SECURITY_SELINUX_DEVELOP policy<{'arm64': 'y'}> +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE policy<{'arm64': '256'}> +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS policy<{'arm64': '9'}> +CONFIG_SECURITY_SMACK policy<{'arm64': 'y'}> +CONFIG_SECURITY_SMACK_APPEND_SIGNALS policy<{'arm64': 'y'}> +CONFIG_SECURITY_SMACK_BRINGUP policy<{'arm64': 'n'}> +CONFIG_SECURITY_SMACK_NETFILTER policy<{'arm64': 'y'}> +CONFIG_SECURITY_TOMOYO policy<{'arm64': 'y'}> +CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER policy<{'arm64': '"/sbin/init"'}> +CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING policy<{'arm64': 'n'}> +CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY policy<{'arm64': '2048'}> +CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG policy<{'arm64': '1024'}> +CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER policy<{'arm64': 'n'}> +CONFIG_SECURITY_TOMOYO_POLICY_LOADER policy<{'arm64': '"/sbin/tomoyo-init"'}> +CONFIG_SECURITY_YAMA policy<{'arm64': 'y'}> +CONFIG_SEG_LED_GPIO policy<{'arm64': 'm'}> +CONFIG_SEN0322 policy<{'arm64': 'n'}> +CONFIG_SENSEAIR_SUNRISE_CO2 policy<{'arm64': 'm'}> +CONFIG_SENSIRION_SGP30 policy<{'arm64': 'm'}> +CONFIG_SENSIRION_SGP40 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ACBEL_FSG032 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ACPI_POWER policy<{'arm64': 'm'}> +CONFIG_SENSORS_AD7314 policy<{'arm64': 'm'}> +CONFIG_SENSORS_AD7414 policy<{'arm64': 'm'}> +CONFIG_SENSORS_AD7418 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADC128D818 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADCXX policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADM1025 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADM1026 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADM1029 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADM1031 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADM1177 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADM1266 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADM1275 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADM9240 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADP1050 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADP1050_REGULATOR policy<{'arm64': 'n'}> +CONFIG_SENSORS_ADS7828 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADS7871 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADT7310 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADT7410 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADT7411 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADT7462 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADT7470 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADT7475 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ADT7X10 policy<{'arm64': 'm'}> +CONFIG_SENSORS_AHT10 policy<{'arm64': 'm'}> +CONFIG_SENSORS_AMC6821 policy<{'arm64': 'm'}> +CONFIG_SENSORS_APS_379 policy<{'arm64': 'n'}> +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT policy<{'arm64': 'm'}> +CONFIG_SENSORS_ARCTIC_FAN_CONTROLLER policy<{'arm64': 'n'}> +CONFIG_SENSORS_ARM_SCMI policy<{'arm64': 'm'}> +CONFIG_SENSORS_ARM_SCPI policy<{'arm64': 'm'}> +CONFIG_SENSORS_AS370 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ASC7621 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ASUS_ROG_RYUJIN policy<{'arm64': 'm'}> +CONFIG_SENSORS_ATXP1 policy<{'arm64': 'm'}> +CONFIG_SENSORS_AXI_FAN_CONTROL policy<{'arm64': 'm'}> +CONFIG_SENSORS_BEL_PFE policy<{'arm64': 'm'}> +CONFIG_SENSORS_BH1770 policy<{'arm64': 'm'}> +CONFIG_SENSORS_BPA_RS600 policy<{'arm64': 'm'}> +CONFIG_SENSORS_CHIPCAP2 policy<{'arm64': 'm'}> +CONFIG_SENSORS_CORSAIR_CPRO policy<{'arm64': 'm'}> +CONFIG_SENSORS_CORSAIR_PSU policy<{'arm64': 'm'}> +CONFIG_SENSORS_CROS_EC policy<{'arm64': 'm'}> +CONFIG_SENSORS_CRPS policy<{'arm64': 'n'}> +CONFIG_SENSORS_D1U74T policy<{'arm64': 'n'}> +CONFIG_SENSORS_DA9052_ADC policy<{'arm64': 'm'}> +CONFIG_SENSORS_DA9055 policy<{'arm64': 'm'}> +CONFIG_SENSORS_DELTA_AHE50DC_FAN policy<{'arm64': 'm'}> +CONFIG_SENSORS_DME1737 policy<{'arm64': 'm'}> +CONFIG_SENSORS_DPS920AB policy<{'arm64': 'm'}> +CONFIG_SENSORS_DRIVETEMP policy<{'arm64': 'm'}> +CONFIG_SENSORS_DS1621 policy<{'arm64': 'm'}> +CONFIG_SENSORS_DS620 policy<{'arm64': 'm'}> +CONFIG_SENSORS_E50SN12051 policy<{'arm64': 'n'}> +CONFIG_SENSORS_EMC1403 policy<{'arm64': 'm'}> +CONFIG_SENSORS_EMC1812 policy<{'arm64': 'n'}> +CONFIG_SENSORS_EMC2103 policy<{'arm64': 'm'}> +CONFIG_SENSORS_EMC2305 policy<{'arm64': 'm'}> +CONFIG_SENSORS_EMC6W201 policy<{'arm64': 'm'}> +CONFIG_SENSORS_F71805F policy<{'arm64': 'm'}> +CONFIG_SENSORS_F71882FG policy<{'arm64': 'm'}> +CONFIG_SENSORS_F75375S policy<{'arm64': 'm'}> +CONFIG_SENSORS_FSP_3Y policy<{'arm64': 'm'}> +CONFIG_SENSORS_FTSTEUTATES policy<{'arm64': 'm'}> +CONFIG_SENSORS_G760A policy<{'arm64': 'm'}> +CONFIG_SENSORS_G762 policy<{'arm64': 'm'}> +CONFIG_SENSORS_GIGABYTE_WATERFORCE policy<{'arm64': 'm'}> +CONFIG_SENSORS_GL518SM policy<{'arm64': 'm'}> +CONFIG_SENSORS_GL520SM policy<{'arm64': 'm'}> +CONFIG_SENSORS_GPIO_FAN policy<{'arm64': 'm'}> +CONFIG_SENSORS_GSC policy<{'arm64': 'm'}> +CONFIG_SENSORS_HAC300S policy<{'arm64': 'n'}> +CONFIG_SENSORS_HIH6130 policy<{'arm64': 'm'}> +CONFIG_SENSORS_HMC5843 policy<{'arm64': 'm'}> +CONFIG_SENSORS_HMC5843_I2C policy<{'arm64': 'm'}> +CONFIG_SENSORS_HMC5843_SPI policy<{'arm64': 'm'}> +CONFIG_SENSORS_HS3001 policy<{'arm64': 'm'}> +CONFIG_SENSORS_HTU31 policy<{'arm64': 'n'}> +CONFIG_SENSORS_I5K_AMB policy<{'arm64': 'm'}> +CONFIG_SENSORS_IBMAEM policy<{'arm64': 'm'}> +CONFIG_SENSORS_IBMPEX policy<{'arm64': 'm'}> +CONFIG_SENSORS_IBM_CFFPS policy<{'arm64': 'm'}> +CONFIG_SENSORS_IIO_HWMON policy<{'arm64': 'm'}> +CONFIG_SENSORS_INA209 policy<{'arm64': 'm'}> +CONFIG_SENSORS_INA233 policy<{'arm64': 'n'}> +CONFIG_SENSORS_INA238 policy<{'arm64': 'm'}> +CONFIG_SENSORS_INA2XX policy<{'arm64': 'm'}> +CONFIG_SENSORS_INA3221 policy<{'arm64': 'm'}> +CONFIG_SENSORS_INSPUR_IPSPS policy<{'arm64': 'm'}> +CONFIG_SENSORS_INTEL_M10_BMC_HWMON policy<{'arm64': 'm'}> +CONFIG_SENSORS_IR35221 policy<{'arm64': 'm'}> +CONFIG_SENSORS_IR36021 policy<{'arm64': 'm'}> +CONFIG_SENSORS_IR38064 policy<{'arm64': 'm'}> +CONFIG_SENSORS_IR38064_REGULATOR policy<{'arm64': 'y'}> +CONFIG_SENSORS_IRPS5401 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ISL28022 policy<{'arm64': 'n'}> +CONFIG_SENSORS_ISL29018 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ISL29028 policy<{'arm64': 'm'}> +CONFIG_SENSORS_ISL68137 policy<{'arm64': 'm'}> +CONFIG_SENSORS_IT87 policy<{'arm64': 'm'}> +CONFIG_SENSORS_JC42 policy<{'arm64': 'm'}> +CONFIG_SENSORS_KBATT policy<{'arm64': 'n'}> +CONFIG_SENSORS_KFAN policy<{'arm64': 'n'}> +CONFIG_SENSORS_LINEAGE policy<{'arm64': 'm'}> +CONFIG_SENSORS_LIS3LV02D policy<{'arm64': 'm'}> +CONFIG_SENSORS_LIS3_I2C policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM25066 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM25066_REGULATOR policy<{'arm64': 'y'}> +CONFIG_SENSORS_LM3533 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM63 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM70 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM73 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM75 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM77 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM78 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM80 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM83 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM85 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM87 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM90 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM92 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM93 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM95234 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM95241 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LM95245 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LOCHNAGAR policy<{'arm64': 'm'}> +CONFIG_SENSORS_LT3074 policy<{'arm64': 'n'}> +CONFIG_SENSORS_LT7182S policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC2945 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC2947 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC2947_I2C policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC2947_SPI policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC2978 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC2978_REGULATOR policy<{'arm64': 'y'}> +CONFIG_SENSORS_LTC2990 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC2991 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC2992 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC3815 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC4151 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC4215 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC4222 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC4245 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC4260 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC4261 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC4282 policy<{'arm64': 'm'}> +CONFIG_SENSORS_LTC4283 policy<{'arm64': 'n'}> +CONFIG_SENSORS_LTC4286 policy<{'arm64': 'y'}> +CONFIG_SENSORS_LX1308 policy<{'arm64': 'n'}> +CONFIG_SENSORS_MAX1111 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX127 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX15301 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX16064 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX16065 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX1619 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX16601 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX1668 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX17616 policy<{'arm64': 'n'}> +CONFIG_SENSORS_MAX197 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX20730 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX20751 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX20830 policy<{'arm64': 'n'}> +CONFIG_SENSORS_MAX20860A policy<{'arm64': 'n'}> +CONFIG_SENSORS_MAX31722 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX31730 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX31760 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX31785 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX31790 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX34440 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX6620 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX6621 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX6639 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX6650 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX6697 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX8688 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MC13783_ADC policy<{'arm64': 'm'}> +CONFIG_SENSORS_MC34VR500 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MCP3021 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MCP9982 policy<{'arm64': 'n'}> +CONFIG_SENSORS_MENF21BMC_HWMON policy<{'arm64': 'm'}> +CONFIG_SENSORS_MLXREG_FAN policy<{'arm64': 'm'}> +CONFIG_SENSORS_MP2856 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MP2869 policy<{'arm64': 'n'}> +CONFIG_SENSORS_MP2888 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MP2891 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MP2925 policy<{'arm64': 'n'}> +CONFIG_SENSORS_MP29502 policy<{'arm64': 'n'}> +CONFIG_SENSORS_MP2975 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MP2975_REGULATOR policy<{'arm64': 'y'}> +CONFIG_SENSORS_MP2985 policy<{'arm64': 'n'}> +CONFIG_SENSORS_MP2993 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MP5023 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MP5920 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MP5926 policy<{'arm64': 'n'}> +CONFIG_SENSORS_MP5990 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MP9941 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MP9945 policy<{'arm64': 'n'}> +CONFIG_SENSORS_MPQ7932 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MPQ7932_REGULATOR policy<{'arm64': 'y'}> +CONFIG_SENSORS_MPQ8785 policy<{'arm64': 'm'}> +CONFIG_SENSORS_MR75203 policy<{'arm64': 'm'}> +CONFIG_SENSORS_NCT6683 policy<{'arm64': 'm'}> +CONFIG_SENSORS_NCT6775 policy<{'arm64': 'm'}> +CONFIG_SENSORS_NCT6775_CORE policy<{'arm64': 'm'}> +CONFIG_SENSORS_NCT6775_I2C policy<{'arm64': 'm'}> +CONFIG_SENSORS_NCT7363 policy<{'arm64': 'n'}> +CONFIG_SENSORS_NCT7802 policy<{'arm64': 'm'}> +CONFIG_SENSORS_NCT7904 policy<{'arm64': 'm'}> +CONFIG_SENSORS_NPCM7XX policy<{'arm64': 'm'}> +CONFIG_SENSORS_NTC_THERMISTOR policy<{'arm64': 'm'}> +CONFIG_SENSORS_NZXT_KRAKEN2 policy<{'arm64': 'm'}> +CONFIG_SENSORS_NZXT_KRAKEN3 policy<{'arm64': 'm'}> +CONFIG_SENSORS_NZXT_SMART2 policy<{'arm64': 'm'}> +CONFIG_SENSORS_OCC_P8_I2C policy<{'arm64': 'n'}> +CONFIG_SENSORS_OCC_P9_SBE policy<{'arm64': 'n'}> +CONFIG_SENSORS_PC87360 policy<{'arm64': 'm'}> +CONFIG_SENSORS_PC87427 policy<{'arm64': 'm'}> +CONFIG_SENSORS_PCF8591 policy<{'arm64': 'm'}> +CONFIG_SENSORS_PECI policy<{'arm64': 'm'}> +CONFIG_SENSORS_PECI_CPUTEMP policy<{'arm64': 'm'}> +CONFIG_SENSORS_PECI_DIMMTEMP policy<{'arm64': 'm'}> +CONFIG_SENSORS_PIM4328 policy<{'arm64': 'm'}> +CONFIG_SENSORS_PLI1209BC policy<{'arm64': 'm'}> +CONFIG_SENSORS_PLI1209BC_REGULATOR policy<{'arm64': 'y'}> +CONFIG_SENSORS_PM6764TR policy<{'arm64': 'm'}> +CONFIG_SENSORS_PMBUS policy<{'arm64': 'm'}> +CONFIG_SENSORS_POWERZ policy<{'arm64': 'm'}> +CONFIG_SENSORS_POWR1220 policy<{'arm64': 'm'}> +CONFIG_SENSORS_PROM21_XHCI policy<{'arm64': 'n'}> +CONFIG_SENSORS_PT5161L policy<{'arm64': 'm'}> +CONFIG_SENSORS_PWM_FAN policy<{'arm64': 'm'}> +CONFIG_SENSORS_PXE1610 policy<{'arm64': 'm'}> +CONFIG_SENSORS_Q54SJ108A2 policy<{'arm64': 'm'}> +CONFIG_SENSORS_RM3100 policy<{'arm64': 'm'}> +CONFIG_SENSORS_RM3100_I2C policy<{'arm64': 'm'}> +CONFIG_SENSORS_RM3100_SPI policy<{'arm64': 'm'}> +CONFIG_SENSORS_SBTSI policy<{'arm64': 'm'}> +CONFIG_SENSORS_SCH5627 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SCH5636 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SCH56XX_COMMON policy<{'arm64': 'm'}> +CONFIG_SENSORS_SHT15 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SHT21 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SHT3x policy<{'arm64': 'm'}> +CONFIG_SENSORS_SHT4x policy<{'arm64': 'm'}> +CONFIG_SENSORS_SHTC1 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SIS5595 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_SENSORS_SMPRO policy<{'arm64': 'm'}> +CONFIG_SENSORS_SMSC47B397 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SMSC47M1 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SMSC47M192 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SPARX5 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SPD5118 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SPD5118_DETECT policy<{'arm64': 'y'}> +CONFIG_SENSORS_STEF48H28 policy<{'arm64': 'n'}> +CONFIG_SENSORS_STPDDC60 policy<{'arm64': 'm'}> +CONFIG_SENSORS_STTS751 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SURFACE_FAN policy<{'arm64': 'm'}> +CONFIG_SENSORS_SURFACE_TEMP policy<{'arm64': 'n'}> +CONFIG_SENSORS_SY7636A policy<{'arm64': 'm'}> +CONFIG_SENSORS_T14S_FAN_CTRL policy<{'arm64': 'n'}> +CONFIG_SENSORS_TC654 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TC74 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TDA38640 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TDA38640_REGULATOR policy<{'arm64': 'y'}> +CONFIG_SENSORS_THMC50 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TMP102 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TMP103 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TMP108 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TMP401 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TMP421 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TMP464 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TMP513 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TPS23861 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TPS25990 policy<{'arm64': 'n'}> +CONFIG_SENSORS_TPS40422 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TPS53679 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TPS546D24 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TSC1641 policy<{'arm64': 'n'}> +CONFIG_SENSORS_TSL2550 policy<{'arm64': 'm'}> +CONFIG_SENSORS_TSL2563 policy<{'arm64': 'm'}> +CONFIG_SENSORS_UCD9000 policy<{'arm64': 'm'}> +CONFIG_SENSORS_UCD9200 policy<{'arm64': 'm'}> +CONFIG_SENSORS_VEXPRESS policy<{'arm64': 'm'}> +CONFIG_SENSORS_VIA686A policy<{'arm64': 'm'}> +CONFIG_SENSORS_VT1211 policy<{'arm64': 'm'}> +CONFIG_SENSORS_VT8231 policy<{'arm64': 'm'}> +CONFIG_SENSORS_W83627EHF policy<{'arm64': 'm'}> +CONFIG_SENSORS_W83627HF policy<{'arm64': 'm'}> +CONFIG_SENSORS_W83773G policy<{'arm64': 'm'}> +CONFIG_SENSORS_W83781D policy<{'arm64': 'm'}> +CONFIG_SENSORS_W83791D policy<{'arm64': 'm'}> +CONFIG_SENSORS_W83792D policy<{'arm64': 'm'}> +CONFIG_SENSORS_W83793 policy<{'arm64': 'm'}> +CONFIG_SENSORS_W83795 policy<{'arm64': 'm'}> +CONFIG_SENSORS_W83795_FANCTRL policy<{'arm64': 'n'}> +CONFIG_SENSORS_W83L785TS policy<{'arm64': 'm'}> +CONFIG_SENSORS_W83L786NG policy<{'arm64': 'm'}> +CONFIG_SENSORS_WM831X policy<{'arm64': 'm'}> +CONFIG_SENSORS_WM8350 policy<{'arm64': 'm'}> +CONFIG_SENSORS_XDP710 policy<{'arm64': 'm'}> +CONFIG_SENSORS_XDP720 policy<{'arm64': 'n'}> +CONFIG_SENSORS_XDPE122 policy<{'arm64': 'm'}> +CONFIG_SENSORS_XDPE122_REGULATOR policy<{'arm64': 'y'}> +CONFIG_SENSORS_XDPE152 policy<{'arm64': 'm'}> +CONFIG_SENSORS_XDPE1A2G7B policy<{'arm64': 'n'}> +CONFIG_SENSORS_XGENE policy<{'arm64': 'm'}> +CONFIG_SENSORS_YOGAFAN policy<{'arm64': 'n'}> +CONFIG_SENSORS_ZL6100 policy<{'arm64': 'm'}> +CONFIG_SERIAL_8250 policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_16550A_VARIANTS policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_CS policy<{'arm64': 'n'}> +CONFIG_SERIAL_8250_DETECT_IRQ policy<{'arm64': 'n'}> +CONFIG_SERIAL_8250_DFL policy<{'arm64': 'm'}> +CONFIG_SERIAL_8250_DMA policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_DWLIB policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_EM policy<{'arm64': 'n'}> +CONFIG_SERIAL_8250_EXAR policy<{'arm64': 'm'}> +CONFIG_SERIAL_8250_EXTENDED policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_FINTEK policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_FSL policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_KEBA policy<{'arm64': 'n'}> +CONFIG_SERIAL_8250_MANY_PORTS policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_MEN_MCB policy<{'arm64': 'm'}> +CONFIG_SERIAL_8250_MT6577 policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_NR_UARTS policy<{'arm64': '48'}> +CONFIG_SERIAL_8250_OMAP policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_PCI policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_PCI1XXXX policy<{'arm64': 'm'}> +CONFIG_SERIAL_8250_PCILIB policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_PERICOM policy<{'arm64': 'm'}> +CONFIG_SERIAL_8250_PNP policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_RSA policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_RT288X policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_RUNTIME_UARTS policy<{'arm64': '32'}> +CONFIG_SERIAL_8250_SHARE_IRQ policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_TEGRA policy<{'arm64': 'y'}> +CONFIG_SERIAL_ALTERA_JTAGUART policy<{'arm64': 'm'}> +CONFIG_SERIAL_ALTERA_UART policy<{'arm64': 'm'}> +CONFIG_SERIAL_ALTERA_UART_BAUDRATE policy<{'arm64': '115200'}> +CONFIG_SERIAL_ALTERA_UART_MAXPORTS policy<{'arm64': '4'}> +CONFIG_SERIAL_AMBA_PL010 policy<{'arm64': 'm'}> +CONFIG_SERIAL_AMBA_PL011 policy<{'arm64': 'y'}> +CONFIG_SERIAL_AMBA_PL011_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_ARC policy<{'arm64': 'm'}> +CONFIG_SERIAL_ARC_NR_PORTS policy<{'arm64': '1'}> +CONFIG_SERIAL_ATMEL policy<{'arm64': 'n'}> +CONFIG_SERIAL_CONEXANT_DIGICOLOR policy<{'arm64': 'm'}> +CONFIG_SERIAL_CORE policy<{'arm64': 'y'}> +CONFIG_SERIAL_CORE_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_EARLYCON policy<{'arm64': 'y'}> +CONFIG_SERIAL_EARLYCON_SEMIHOST policy<{'arm64': 'y'}> +CONFIG_SERIAL_FSL_LINFLEXUART policy<{'arm64': 'm'}> +CONFIG_SERIAL_FSL_LPUART policy<{'arm64': 'm'}> +CONFIG_SERIAL_IMX policy<{'arm64': 'y'}> +CONFIG_SERIAL_IMX_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_IMX_EARLYCON policy<{'arm64': 'y'}> +CONFIG_SERIAL_IPOCTAL policy<{'arm64': 'm'}> +CONFIG_SERIAL_JSM policy<{'arm64': 'm'}> +CONFIG_SERIAL_LITEUART policy<{'arm64': 'm'}> +CONFIG_SERIAL_LITEUART_MAX_PORTS policy<{'arm64': '1'}> +CONFIG_SERIAL_MAX3100 policy<{'arm64': 'm'}> +CONFIG_SERIAL_MAX310X policy<{'arm64': 'y'}> +CONFIG_SERIAL_MCTRL_GPIO policy<{'arm64': 'y'}> +CONFIG_SERIAL_MEN_Z135 policy<{'arm64': 'm'}> +CONFIG_SERIAL_MESON policy<{'arm64': 'y'}> +CONFIG_SERIAL_MESON_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_MSM policy<{'arm64': 'y'}> +CONFIG_SERIAL_MSM_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_MULTI_INSTANTIATE policy<{'arm64': 'n'}> +CONFIG_SERIAL_MVEBU_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_MVEBU_UART policy<{'arm64': 'y'}> +CONFIG_SERIAL_NONSTANDARD policy<{'arm64': 'y'}> +CONFIG_SERIAL_NUVOTON_MA35D1 policy<{'arm64': 'm'}> +CONFIG_SERIAL_OF_PLATFORM policy<{'arm64': 'y'}> +CONFIG_SERIAL_OWL policy<{'arm64': 'y'}> +CONFIG_SERIAL_OWL_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_QCOM_GENI policy<{'arm64': 'm'}> +CONFIG_SERIAL_QCOM_GENI_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_QCOM_GENI_UART_PORTS policy<{'arm64': '8'}> +CONFIG_SERIAL_QE policy<{'arm64': 'm'}> +CONFIG_SERIAL_RP2 policy<{'arm64': 'm'}> +CONFIG_SERIAL_RP2_NR_UARTS policy<{'arm64': '32'}> +CONFIG_SERIAL_RSCI policy<{'arm64': 'n'}> +CONFIG_SERIAL_SAMSUNG policy<{'arm64': 'm'}> +CONFIG_SERIAL_SAMSUNG_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_SAMSUNG_UARTS policy<{'arm64': '4'}> +CONFIG_SERIAL_SC16IS7XX policy<{'arm64': 'm'}> +CONFIG_SERIAL_SC16IS7XX_I2C policy<{'arm64': 'm'}> +CONFIG_SERIAL_SC16IS7XX_SPI policy<{'arm64': 'm'}> +CONFIG_SERIAL_SCCNXP policy<{'arm64': 'y'}> +CONFIG_SERIAL_SCCNXP_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_SH_SCI policy<{'arm64': 'y'}> +CONFIG_SERIAL_SH_SCI_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_SH_SCI_DMA policy<{'arm64': 'y'}> +CONFIG_SERIAL_SH_SCI_EARLYCON policy<{'arm64': 'y'}> +CONFIG_SERIAL_SH_SCI_NR_UARTS policy<{'arm64': '2'}> +CONFIG_SERIAL_SIFIVE policy<{'arm64': 'm'}> +CONFIG_SERIAL_SPRD policy<{'arm64': 'm'}> +CONFIG_SERIAL_STM32 policy<{'arm64': 'm'}> +CONFIG_SERIAL_STM32_CONSOLE policy<{'arm64': 'n'}> +CONFIG_SERIAL_TEGRA policy<{'arm64': 'm'}> +CONFIG_SERIAL_TEGRA_TCU policy<{'arm64': 'y'}> +CONFIG_SERIAL_TEGRA_TCU_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_TEGRA_UTC policy<{'arm64': 'n'}> +CONFIG_SERIAL_UARTLITE policy<{'arm64': 'm'}> +CONFIG_SERIAL_UARTLITE_NR_UARTS policy<{'arm64': '1'}> +CONFIG_SERIAL_XILINX_PS_UART policy<{'arm64': 'm'}> +CONFIG_SERIO policy<{'arm64': 'y'}> +CONFIG_SERIO_ALTERA_PS2 policy<{'arm64': 'm'}> +CONFIG_SERIO_AMBAKMI policy<{'arm64': 'm'}> +CONFIG_SERIO_APBPS2 policy<{'arm64': 'm'}> +CONFIG_SERIO_ARC_PS2 policy<{'arm64': 'm'}> +CONFIG_SERIO_GPIO_PS2 policy<{'arm64': 'm'}> +CONFIG_SERIO_LIBPS2 policy<{'arm64': 'y'}> +CONFIG_SERIO_NVEC_PS2 policy<{'arm64': 'm'}> +CONFIG_SERIO_PARKBD policy<{'arm64': 'm'}> +CONFIG_SERIO_PCIPS2 policy<{'arm64': 'm'}> +CONFIG_SERIO_PS2MULT policy<{'arm64': 'm'}> +CONFIG_SERIO_RAW policy<{'arm64': 'm'}> +CONFIG_SERIO_SERPORT policy<{'arm64': 'm'}> +CONFIG_SERIO_SUN4I_PS2 policy<{'arm64': 'n'}> +CONFIG_SFC policy<{'arm64': 'm'}> +CONFIG_SFC_FALCON policy<{'arm64': 'm'}> +CONFIG_SFC_FALCON_MTD policy<{'arm64': 'y'}> +CONFIG_SFC_MCDI_LOGGING policy<{'arm64': 'y'}> +CONFIG_SFC_MCDI_MON policy<{'arm64': 'y'}> +CONFIG_SFC_MTD policy<{'arm64': 'y'}> +CONFIG_SFC_SIENA policy<{'arm64': 'm'}> +CONFIG_SFC_SIENA_MCDI_LOGGING policy<{'arm64': 'y'}> +CONFIG_SFC_SIENA_MCDI_MON policy<{'arm64': 'y'}> +CONFIG_SFC_SIENA_MTD policy<{'arm64': 'y'}> +CONFIG_SFC_SIENA_SRIOV policy<{'arm64': 'y'}> +CONFIG_SFC_SRIOV policy<{'arm64': 'y'}> +CONFIG_SFP policy<{'arm64': 'm'}> +CONFIG_SF_PDMA policy<{'arm64': 'm'}> +CONFIG_SGETMASK_SYSCALL policy<{'arm64': 'y'}> +CONFIG_SGI_PARTITION policy<{'arm64': 'y'}> +CONFIG_SGL_ALLOC policy<{'arm64': 'y'}> +CONFIG_SG_POOL policy<{'arm64': 'y'}> +CONFIG_SG_SPLIT policy<{'arm64': 'y'}> +CONFIG_SHADOW_CALL_STACK policy<{'arm64': 'n'}> +CONFIG_SHMEM policy<{'arm64': 'y'}> +CONFIG_SHRINKER_DEBUG policy<{'arm64': 'n'}> +CONFIG_SHUFFLE_PAGE_ALLOCATOR policy<{'arm64': 'y'}> +CONFIG_SH_ETH policy<{'arm64': 'm'}> +CONFIG_SH_TIMER_CMT policy<{'arm64': 'y'}> +CONFIG_SH_TIMER_TMU policy<{'arm64': 'y'}> +CONFIG_SI1133 policy<{'arm64': 'm'}> +CONFIG_SI1145 policy<{'arm64': 'm'}> +CONFIG_SI7005 policy<{'arm64': 'm'}> +CONFIG_SI7020 policy<{'arm64': 'm'}> +CONFIG_SI7210 policy<{'arm64': 'n'}> +CONFIG_SIGNALFD policy<{'arm64': 'y'}> +CONFIG_SIGNATURE policy<{'arm64': 'y'}> +CONFIG_SIGNED_PE_FILE_VERIFICATION policy<{'arm64': 'y'}> +CONFIG_SIOX policy<{'arm64': 'm'}> +CONFIG_SIOX_BUS_GPIO policy<{'arm64': 'm'}> +CONFIG_SIS190 policy<{'arm64': 'm'}> +CONFIG_SIS900 policy<{'arm64': 'm'}> +CONFIG_SKB_DECRYPTED policy<{'arm64': 'y'}> +CONFIG_SKB_EXTENSIONS policy<{'arm64': 'y'}> +CONFIG_SKFP policy<{'arm64': 'm'}> +CONFIG_SKGE policy<{'arm64': 'm'}> +CONFIG_SKGE_DEBUG policy<{'arm64': 'n'}> +CONFIG_SKGE_GENESIS policy<{'arm64': 'y'}> +CONFIG_SKY2 policy<{'arm64': 'm'}> +CONFIG_SKY2_DEBUG policy<{'arm64': 'n'}> +CONFIG_SL28CPLD_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_SLAB_BUCKETS policy<{'arm64': 'y'}> +CONFIG_SLAB_FREELIST_HARDENED policy<{'arm64': 'y'}> +CONFIG_SLAB_FREELIST_RANDOM policy<{'arm64': 'y'}> +CONFIG_SLAB_MERGE_DEFAULT policy<{'arm64': 'y'}> +CONFIG_SLAB_OBJ_EXT policy<{'arm64': 'y'}> +CONFIG_SLHC policy<{'arm64': 'y'}> +CONFIG_SLICOSS policy<{'arm64': 'm'}> +CONFIG_SLIC_DS26522 policy<{'arm64': 'm'}> +CONFIG_SLIMBUS policy<{'arm64': 'm'}> +CONFIG_SLIM_QCOM_NGD_CTRL policy<{'arm64': 'm'}> +CONFIG_SLIP policy<{'arm64': 'm'}> +CONFIG_SLIP_COMPRESSED policy<{'arm64': 'y'}> +CONFIG_SLIP_MODE_SLIP6 policy<{'arm64': 'y'}> +CONFIG_SLIP_SMART policy<{'arm64': 'y'}> +CONFIG_SLUB policy<{'arm64': 'y'}> +CONFIG_SLUB_DEBUG policy<{'arm64': 'y'}> +CONFIG_SLUB_DEBUG_ON policy<{'arm64': 'n'}> +CONFIG_SLUB_STATS policy<{'arm64': 'n'}> +CONFIG_SLUB_TINY policy<{'arm64': 'n'}> +CONFIG_SMARTJOYPLUS_FF policy<{'arm64': 'y'}> +CONFIG_SMBDIRECT policy<{'arm64': 'm'}> +CONFIG_SMBFS policy<{'arm64': 'm'}> +CONFIG_SMB_SERVER policy<{'arm64': 'm'}> +CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN policy<{'arm64': 'y'}> +CONFIG_SMB_SERVER_KERBEROS5 policy<{'arm64': 'y'}> +CONFIG_SMB_SERVER_SMBDIRECT policy<{'arm64': 'y'}> +CONFIG_SMC91X policy<{'arm64': 'y'}> +CONFIG_SMI240 policy<{'arm64': 'm'}> +CONFIG_SMI330_I2C policy<{'arm64': 'n'}> +CONFIG_SMI330_SPI policy<{'arm64': 'n'}> +CONFIG_SMP policy<{'arm64': 'y'}> +CONFIG_SMPRO_ERRMON policy<{'arm64': 'm'}> +CONFIG_SMPRO_MISC policy<{'arm64': 'm'}> +CONFIG_SMSC911X policy<{'arm64': 'm'}> +CONFIG_SMSC9420 policy<{'arm64': 'm'}> +CONFIG_SMSC_PHY policy<{'arm64': 'm'}> +CONFIG_SMS_SDIO_DRV policy<{'arm64': 'm'}> +CONFIG_SMS_SIANO_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_SMS_SIANO_MDTV policy<{'arm64': 'm'}> +CONFIG_SMS_SIANO_RC policy<{'arm64': 'y'}> +CONFIG_SMS_USB_DRV policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_4450 policy<{'arm64': 'n'}> +CONFIG_SM_CAMCC_6350 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_7150 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8150 policy<{'arm64': 'n'}> +CONFIG_SM_CAMCC_8250 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8450 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8550 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8650 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8750 policy<{'arm64': 'n'}> +CONFIG_SM_CAMCC_MILOS policy<{'arm64': 'n'}> +CONFIG_SM_DISPCC_4450 policy<{'arm64': 'n'}> +CONFIG_SM_DISPCC_6115 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_6125 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_6350 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_6375 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_7150 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_8250 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_8450 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_8550 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_FTL policy<{'arm64': 'm'}> +CONFIG_SM_GCC_4450 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_6115 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_6125 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_6350 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_6375 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_7150 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_8150 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_8250 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_8350 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_8450 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_8550 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_8650 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_MILOS policy<{'arm64': 'n'}> +CONFIG_SM_GPUCC_4450 policy<{'arm64': 'n'}> +CONFIG_SM_GPUCC_6115 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_6125 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_6350 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_6375 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_8150 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_8250 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_8350 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_8450 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_8550 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_8650 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_8750 policy<{'arm64': 'n'}> +CONFIG_SM_GPUCC_MILOS policy<{'arm64': 'n'}> +CONFIG_SM_LPASSCC_6115 policy<{'arm64': 'n'}> +CONFIG_SM_TCSRCC_8550 policy<{'arm64': 'm'}> +CONFIG_SM_TCSRCC_8650 policy<{'arm64': 'm'}> +CONFIG_SM_TCSRCC_8750 policy<{'arm64': 'n'}> +CONFIG_SM_VIDEOCC_6350 policy<{'arm64': 'n'}> +CONFIG_SM_VIDEOCC_7150 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_8150 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_8250 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_8350 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_8450 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_8550 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_8750 policy<{'arm64': 'n'}> +CONFIG_SM_VIDEOCC_MILOS policy<{'arm64': 'n'}> +CONFIG_SND_AC97_CODEC policy<{'arm64': 'm'}> +CONFIG_SND_AC97_POWER_SAVE policy<{'arm64': 'y'}> +CONFIG_SND_AC97_POWER_SAVE_DEFAULT policy<{'arm64': '0'}> +CONFIG_SND_AD1889 policy<{'arm64': 'm'}> +CONFIG_SND_ALI5451 policy<{'arm64': 'm'}> +CONFIG_SND_ALOOP policy<{'arm64': 'm'}> +CONFIG_SND_ALS300 policy<{'arm64': 'm'}> +CONFIG_SND_AMD_ACP_CONFIG policy<{'arm64': 'm'}> +CONFIG_SND_ATIIXP policy<{'arm64': 'm'}> +CONFIG_SND_ATIIXP_MODEM policy<{'arm64': 'm'}> +CONFIG_SND_AU8810 policy<{'arm64': 'm'}> +CONFIG_SND_AU8820 policy<{'arm64': 'm'}> +CONFIG_SND_AU8830 policy<{'arm64': 'm'}> +CONFIG_SND_AUDIO_GRAPH_CARD policy<{'arm64': 'm'}> +CONFIG_SND_AUDIO_GRAPH_CARD2 policy<{'arm64': 'm'}> +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE policy<{'arm64': 'm'}> +CONFIG_SND_AW2 policy<{'arm64': 'm'}> +CONFIG_SND_AZT3328 policy<{'arm64': 'm'}> +CONFIG_SND_BCD2000 policy<{'arm64': 'm'}> +CONFIG_SND_BCM63XX_I2S_WHISTLER policy<{'arm64': 'm'}> +CONFIG_SND_BEBOB policy<{'arm64': 'm'}> +CONFIG_SND_BT87X policy<{'arm64': 'm'}> +CONFIG_SND_BT87X_OVERCLOCK policy<{'arm64': 'n'}> +CONFIG_SND_CA0106 policy<{'arm64': 'm'}> +CONFIG_SND_CMIPCI policy<{'arm64': 'm'}> +CONFIG_SND_COMPRESS_ACCEL policy<{'arm64': 'y'}> +CONFIG_SND_COMPRESS_OFFLOAD policy<{'arm64': 'm'}> +CONFIG_SND_CS4281 policy<{'arm64': 'm'}> +CONFIG_SND_CS46XX policy<{'arm64': 'm'}> +CONFIG_SND_CS46XX_NEW_DSP policy<{'arm64': 'y'}> +CONFIG_SND_CTL_FAST_LOOKUP policy<{'arm64': 'y'}> +CONFIG_SND_CTL_INPUT_VALIDATION policy<{'arm64': 'n'}> +CONFIG_SND_CTL_LED policy<{'arm64': 'm'}> +CONFIG_SND_CTXFI policy<{'arm64': 'm'}> +CONFIG_SND_DARLA20 policy<{'arm64': 'm'}> +CONFIG_SND_DARLA24 policy<{'arm64': 'm'}> +CONFIG_SND_DEBUG policy<{'arm64': 'n'}> +CONFIG_SND_DESIGNWARE_I2S policy<{'arm64': 'm'}> +CONFIG_SND_DESIGNWARE_PCM policy<{'arm64': 'y'}> +CONFIG_SND_DICE policy<{'arm64': 'm'}> +CONFIG_SND_DMAENGINE_PCM policy<{'arm64': 'm'}> +CONFIG_SND_DRIVERS policy<{'arm64': 'y'}> +CONFIG_SND_DUMMY policy<{'arm64': 'm'}> +CONFIG_SND_DYNAMIC_MINORS policy<{'arm64': 'y'}> +CONFIG_SND_ECHO3G policy<{'arm64': 'm'}> +CONFIG_SND_EMU10K1 policy<{'arm64': 'm'}> +CONFIG_SND_EMU10K1X policy<{'arm64': 'm'}> +CONFIG_SND_EMU10K1_SEQ policy<{'arm64': 'm'}> +CONFIG_SND_ENS1370 policy<{'arm64': 'm'}> +CONFIG_SND_ENS1371 policy<{'arm64': 'm'}> +CONFIG_SND_ES1938 policy<{'arm64': 'm'}> +CONFIG_SND_ES1968 policy<{'arm64': 'm'}> +CONFIG_SND_ES1968_INPUT policy<{'arm64': 'y'}> +CONFIG_SND_ES1968_RADIO policy<{'arm64': 'y'}> +CONFIG_SND_FIREFACE policy<{'arm64': 'm'}> +CONFIG_SND_FIREWIRE policy<{'arm64': 'y'}> +CONFIG_SND_FIREWIRE_DIGI00X policy<{'arm64': 'm'}> +CONFIG_SND_FIREWIRE_LIB policy<{'arm64': 'm'}> +CONFIG_SND_FIREWIRE_MOTU policy<{'arm64': 'm'}> +CONFIG_SND_FIREWIRE_TASCAM policy<{'arm64': 'm'}> +CONFIG_SND_FIREWORKS policy<{'arm64': 'm'}> +CONFIG_SND_FM801 policy<{'arm64': 'm'}> +CONFIG_SND_FM801_TEA575X_BOOL policy<{'arm64': 'y'}> +CONFIG_SND_GINA20 policy<{'arm64': 'm'}> +CONFIG_SND_GINA24 policy<{'arm64': 'm'}> +CONFIG_SND_HDA policy<{'arm64': 'm'}> +CONFIG_SND_HDA_ACPI policy<{'arm64': 'n'}> +CONFIG_SND_HDA_ALIGNED_MMIO policy<{'arm64': 'y'}> +CONFIG_SND_HDA_CIRRUS_SCODEC policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC260 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC262 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC268 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC269 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC662 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC680 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC861 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC861VD policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC880 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC882 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ANALOG policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_CA0110 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_CA0132 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_CA0132_DSP policy<{'arm64': 'y'}> +CONFIG_SND_HDA_CODEC_CIRRUS policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_CM9825 policy<{'arm64': 'n'}> +CONFIG_SND_HDA_CODEC_CMEDIA policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_CONEXANT policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_CS420X policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_CS421X policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_CS8409 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_ATI policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_GENERIC policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_INTEL policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_NVIDIA policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_NVIDIA_MCP policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_SIMPLE policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_TEGRA policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_REALTEK policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_REALTEK_LIB policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_SENARYTECH policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_SI3054 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_SIGMATEL policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_VIA policy<{'arm64': 'm'}> +CONFIG_SND_HDA_COMPONENT policy<{'arm64': 'y'}> +CONFIG_SND_HDA_CORE policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CTL_DEV_ID policy<{'arm64': 'n'}> +CONFIG_SND_HDA_DSP_LOADER policy<{'arm64': 'y'}> +CONFIG_SND_HDA_EXT_CORE policy<{'arm64': 'm'}> +CONFIG_SND_HDA_GENERIC policy<{'arm64': 'm'}> +CONFIG_SND_HDA_GENERIC_LEDS policy<{'arm64': 'y'}> +CONFIG_SND_HDA_HWDEP policy<{'arm64': 'y'}> +CONFIG_SND_HDA_I915 policy<{'arm64': 'y'}> +CONFIG_SND_HDA_INPUT_BEEP policy<{'arm64': 'y'}> +CONFIG_SND_HDA_INPUT_BEEP_MODE policy<{'arm64': '0'}> +CONFIG_SND_HDA_INTEL policy<{'arm64': 'm'}> +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM policy<{'arm64': 'n'}> +CONFIG_SND_HDA_PATCH_LOADER policy<{'arm64': 'y'}> +CONFIG_SND_HDA_POWER_SAVE_DEFAULT policy<{'arm64': '1'}> +CONFIG_SND_HDA_PREALLOC_SIZE policy<{'arm64': '64'}> +CONFIG_SND_HDA_RECONFIG policy<{'arm64': 'y'}> +CONFIG_SND_HDA_SCODEC_COMPONENT policy<{'arm64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L41 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L41_I2C policy<{'arm64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L41_SPI policy<{'arm64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L56 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L56_CAL_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_SND_HDA_SCODEC_CS35L56_I2C policy<{'arm64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L56_SPI policy<{'arm64': 'm'}> +CONFIG_SND_HDA_SCODEC_TAS2781 policy<{'arm64': 'm'}> +CONFIG_SND_HDA_SCODEC_TAS2781_I2C policy<{'arm64': 'm'}> +CONFIG_SND_HDA_SCODEC_TAS2781_SPI policy<{'arm64': 'n'}> +CONFIG_SND_HDA_TEGRA policy<{'arm64': 'm'}> +CONFIG_SND_HDSP policy<{'arm64': 'm'}> +CONFIG_SND_HDSPM policy<{'arm64': 'm'}> +CONFIG_SND_HRTIMER policy<{'arm64': 'm'}> +CONFIG_SND_HWDEP policy<{'arm64': 'm'}> +CONFIG_SND_I2S_HI6210_I2S policy<{'arm64': 'm'}> +CONFIG_SND_ICE1712 policy<{'arm64': 'm'}> +CONFIG_SND_ICE1724 policy<{'arm64': 'm'}> +CONFIG_SND_IMX_SOC policy<{'arm64': 'm'}> +CONFIG_SND_INDIGO policy<{'arm64': 'm'}> +CONFIG_SND_INDIGODJ policy<{'arm64': 'm'}> +CONFIG_SND_INDIGODJX policy<{'arm64': 'm'}> +CONFIG_SND_INDIGOIO policy<{'arm64': 'm'}> +CONFIG_SND_INDIGOIOX policy<{'arm64': 'm'}> +CONFIG_SND_INTEL8X0 policy<{'arm64': 'm'}> +CONFIG_SND_INTEL8X0M policy<{'arm64': 'm'}> +CONFIG_SND_INTEL_DSP_CONFIG policy<{'arm64': 'm'}> +CONFIG_SND_INTEL_NHLT policy<{'arm64': 'y'}> +CONFIG_SND_INTEL_SOUNDWIRE_ACPI policy<{'arm64': 'm'}> +CONFIG_SND_ISIGHT policy<{'arm64': 'm'}> +CONFIG_SND_JACK policy<{'arm64': 'y'}> +CONFIG_SND_JACK_INPUT_DEV policy<{'arm64': 'y'}> +CONFIG_SND_KIRKWOOD_SOC policy<{'arm64': 'm'}> +CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB policy<{'arm64': 'm'}> +CONFIG_SND_KORG1212 policy<{'arm64': 'm'}> +CONFIG_SND_LAYLA20 policy<{'arm64': 'm'}> +CONFIG_SND_LAYLA24 policy<{'arm64': 'm'}> +CONFIG_SND_LOLA policy<{'arm64': 'm'}> +CONFIG_SND_LX6464ES policy<{'arm64': 'm'}> +CONFIG_SND_MAESTRO3 policy<{'arm64': 'm'}> +CONFIG_SND_MAESTRO3_INPUT policy<{'arm64': 'y'}> +CONFIG_SND_MAX_CARDS policy<{'arm64': '32'}> +CONFIG_SND_MESON_AIU policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_FIFO policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_FRDDR policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_PDM policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_SOUND_CARD policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_SPDIFIN policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_SPDIFOUT policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_TDMIN policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_TDMOUT policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_TDM_FORMATTER policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_TDM_INTERFACE policy<{'arm64': 'm'}> +CONFIG_SND_MESON_AXG_TODDR policy<{'arm64': 'm'}> +CONFIG_SND_MESON_CARD_UTILS policy<{'arm64': 'm'}> +CONFIG_SND_MESON_CODEC_GLUE policy<{'arm64': 'm'}> +CONFIG_SND_MESON_G12A_TOACODEC policy<{'arm64': 'm'}> +CONFIG_SND_MESON_G12A_TOHDMITX policy<{'arm64': 'm'}> +CONFIG_SND_MESON_GX_SOUND_CARD policy<{'arm64': 'm'}> +CONFIG_SND_MIA policy<{'arm64': 'm'}> +CONFIG_SND_MIXART policy<{'arm64': 'm'}> +CONFIG_SND_MIXER_OSS policy<{'arm64': 'm'}> +CONFIG_SND_MONA policy<{'arm64': 'm'}> +CONFIG_SND_MPU401 policy<{'arm64': 'm'}> +CONFIG_SND_MPU401_UART policy<{'arm64': 'm'}> +CONFIG_SND_MTPAV policy<{'arm64': 'm'}> +CONFIG_SND_MTS64 policy<{'arm64': 'm'}> +CONFIG_SND_NM256 policy<{'arm64': 'm'}> +CONFIG_SND_OPL3_LIB policy<{'arm64': 'm'}> +CONFIG_SND_OPL3_LIB_SEQ policy<{'arm64': 'm'}> +CONFIG_SND_OSSEMUL policy<{'arm64': 'y'}> +CONFIG_SND_OXFW policy<{'arm64': 'm'}> +CONFIG_SND_OXYGEN policy<{'arm64': 'm'}> +CONFIG_SND_OXYGEN_LIB policy<{'arm64': 'm'}> +CONFIG_SND_PCI policy<{'arm64': 'y'}> +CONFIG_SND_PCM policy<{'arm64': 'm'}> +CONFIG_SND_PCMCIA policy<{'arm64': 'y'}> +CONFIG_SND_PCMTEST policy<{'arm64': 'm'}> +CONFIG_SND_PCM_ELD policy<{'arm64': 'y'}> +CONFIG_SND_PCM_IEC958 policy<{'arm64': 'y'}> +CONFIG_SND_PCM_OSS policy<{'arm64': 'n'}> +CONFIG_SND_PCM_TIMER policy<{'arm64': 'y'}> +CONFIG_SND_PCXHR policy<{'arm64': 'm'}> +CONFIG_SND_PDAUDIOCF policy<{'arm64': 'n'}> +CONFIG_SND_PORTMAN2X4 policy<{'arm64': 'm'}> +CONFIG_SND_PROC_FS policy<{'arm64': 'y'}> +CONFIG_SND_RAWMIDI policy<{'arm64': 'm'}> +CONFIG_SND_RIPTIDE policy<{'arm64': 'm'}> +CONFIG_SND_RME32 policy<{'arm64': 'm'}> +CONFIG_SND_RME96 policy<{'arm64': 'm'}> +CONFIG_SND_RME9652 policy<{'arm64': 'm'}> +CONFIG_SND_SEQUENCER policy<{'arm64': 'm'}> +CONFIG_SND_SEQUENCER_OSS policy<{'arm64': 'n'}> +CONFIG_SND_SEQ_DEVICE policy<{'arm64': 'm'}> +CONFIG_SND_SEQ_DUMMY policy<{'arm64': 'm'}> +CONFIG_SND_SEQ_HRTIMER_DEFAULT policy<{'arm64': 'y'}> +CONFIG_SND_SEQ_MIDI policy<{'arm64': 'm'}> +CONFIG_SND_SEQ_MIDI_EMUL policy<{'arm64': 'm'}> +CONFIG_SND_SEQ_MIDI_EVENT policy<{'arm64': 'm'}> +CONFIG_SND_SEQ_UMP policy<{'arm64': 'y'}> +CONFIG_SND_SEQ_UMP_CLIENT policy<{'arm64': 'm'}> +CONFIG_SND_SEQ_VIRMIDI policy<{'arm64': 'm'}> +CONFIG_SND_SERIAL_GENERIC policy<{'arm64': 'm'}> +CONFIG_SND_SERIAL_U16550 policy<{'arm64': 'm'}> +CONFIG_SND_SIMPLE_CARD policy<{'arm64': 'm'}> +CONFIG_SND_SIMPLE_CARD_UTILS policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AC97_BUS policy<{'arm64': 'y'}> +CONFIG_SND_SOC_AC97_CODEC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ACPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU1372 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU1372_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU1372_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU1373 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU1701 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU1761 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU1761_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU1761_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU17X1 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU7002 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU7118 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU7118_HW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU7118_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADAU_UTILS policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADI_AXI_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ADI_AXI_SPDIF policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AK4104 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AK4118 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AK4375 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AK4458 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AK4554 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AK4613 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AK4619 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AK4642 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AK5386 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AK5558 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ALC5623 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ALC5632 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AMD_ACP policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AMD_ST_ES8336_MACH policy<{'arm64': 'm'}> +CONFIG_SND_SOC_APPLE_MCA policy<{'arm64': 'm'}> +CONFIG_SND_SOC_APQ8016_SBC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ARIZONA policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AUDIO_IIO_AUX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AW8738 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AW87390 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AW88081 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AW88166 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_AW88261 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AW88395 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AW88395_LIB policy<{'arm64': 'm'}> +CONFIG_SND_SOC_AW88399 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_BD28623 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_BT_SCO policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CHV3_CODEC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CHV3_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_COMPRESS policy<{'arm64': 'y'}> +CONFIG_SND_SOC_CPCAP policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CROS_EC_CODEC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L32 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L33 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L34 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L35 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L36 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L41 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L41_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L41_LIB policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L41_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L45 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L45_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L45_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L56 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_SND_SOC_CS35L56_CAL_PERFORM_CTRL policy<{'arm64': 'n'}> +CONFIG_SND_SOC_CS35L56_CAL_SET_CTRL policy<{'arm64': 'n'}> +CONFIG_SND_SOC_CS35L56_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L56_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L56_SHARED policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS35L56_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS40L50 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS4234 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS4265 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS4270 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS4271 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS4271_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS4271_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L42 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L42_CORE policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L42_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L43 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L43_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L51 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L51_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L52 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L56 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L73 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L83 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42L84 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42XX8 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42XX8_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS42XX8_SPI policy<{'arm64': 'n'}> +CONFIG_SND_SOC_CS43130 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS4341 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS4349 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS48L32 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_CS530X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS530X_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS530X_SPI policy<{'arm64': 'n'}> +CONFIG_SND_SOC_CS53L30 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CS_AMP_LIB policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CX2072X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_DA7213 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_DA7219 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_DAVINCI_MCASP policy<{'arm64': 'm'}> +CONFIG_SND_SOC_DMIC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ES7134 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ES7241 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ES8311 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ES8316 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ES8323 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ES8326 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ES8328 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ES8328_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ES8328_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ES8375 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_ES8389 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_FRAMER policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FS210X policy<{'arm64': 'n'}> +CONFIG_SND_SOC_FSL_ASOC_CARD policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_ASRC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_AUD2HTX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_AUDMIX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_EASRC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_ESAI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_MICFIL policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_MQS policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_RPMSG policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_SAI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_SPDIF policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_SSI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_UTILS policy<{'arm64': 'm'}> +CONFIG_SND_SOC_FSL_XCVR policy<{'arm64': 'm'}> +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM policy<{'arm64': 'y'}> +CONFIG_SND_SOC_GTM601 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_HDA policy<{'arm64': 'm'}> +CONFIG_SND_SOC_HDMI_CODEC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_I2C_AND_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ICS43432 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IDT821034 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IMX_AUDIO_RPMSG policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IMX_AUDMIX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IMX_AUDMUX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IMX_CARD policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IMX_ES8328 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IMX_HDMI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IMX_PCM_DMA policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IMX_PCM_RPMSG policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IMX_RPMSG policy<{'arm64': 'm'}> +CONFIG_SND_SOC_IMX_SGTL5000 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_INNO_RK3036 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_INTEL_KEEMBAY policy<{'arm64': 'm'}> +CONFIG_SND_SOC_J721E_EVM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LOCHNAGAR_SC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_APQ8016 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_CDC_DMA policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_CPU policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_HDMI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_IPQ806X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_MACRO_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_PLATFORM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_RX_MACRO policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_SC7180 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_SC7280 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_TX_MACRO policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_VA_MACRO policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LPASS_WSA_MACRO policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX9759 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98088 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98090 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98357A policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98363 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98373 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98373_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98373_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98388 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98390 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98396 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98504 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98520 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX9860 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX9867 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MAX98927 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MEDIATEK policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MESON_T9015 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MIKROE_PROTO policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MSIOF policy<{'arm64': 'n'}> +CONFIG_SND_SOC_MSM8916_WCD_ANALOG policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MSM8996 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT2701 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_MT6351 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT6357 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_MT6358 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT6359 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT6359_ACCDET policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT6660 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT6797 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT6797_MT6351 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT7986 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT7986_WM8960 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8173 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_MT8183 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8183_DA7219_MAX98357A policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8186 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8186_MT6366 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8188 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8188_MT6359 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8189 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_MT8192 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8195 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8195_MT6359 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_MT8196 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_MT8365 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_MTK_BTCVSD policy<{'arm64': 'm'}> +CONFIG_SND_SOC_NAU8315 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_NAU8325 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_NAU8540 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_NAU8810 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_NAU8821 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_NAU8822 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_NAU8824 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_NAU8825 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_NTP8835 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_NTP8918 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_NTPFW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM1681 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM1754 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_PCM1789 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM1789_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM179X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM179X_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM179X_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM186X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM186X_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM186X_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM3060 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM3060_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM3060_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM3168A policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM3168A_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM3168A_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM5102A policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM512x policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM512x_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM512x_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PCM6240 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PEB2466 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_PM4125_SDW policy<{'arm64': 'n'}> +CONFIG_SND_SOC_QCOM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QCOM_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QCOM_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_ADM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_AFE policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_AFE_CLOCKS policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_AFE_DAI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_APM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_APM_DAI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_ASM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_ASM_DAI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_CORE policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_PRM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS policy<{'arm64': 'm'}> +CONFIG_SND_SOC_QDSP6_ROUTING policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RCAR policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RK3288_HDMI_ANALOG policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RK3308 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RK3328 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RK3399_GRU_SOUND policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RK817 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RL6231 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_MAX98090 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_PDM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_RT5645 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_SAI policy<{'arm64': 'n'}> +CONFIG_SND_SOC_ROCKCHIP_SPDIF policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT1011 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT1015 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT1015P policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT1017_SDCA_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT1308_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT1316_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT1318_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT1320_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5514 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5514_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5575 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_RT5616 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5631 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5640 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5645 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5659 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5663 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5677 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5677_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5682 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5682S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5682_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT5682_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT700 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT700_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT711 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT711_SDCA_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT711_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT712_SDCA_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT715 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT715_SDCA_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT715_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT721_SDCA_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT722_SDCA_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT9120 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT9123 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_RT9123P policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RTQ9124 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_RTQ9128 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RT_SDW_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RZ policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SC7180 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SC7280 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SC8280XP policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SDCA policy<{'arm64': 'n'}> +CONFIG_SND_SOC_SDCA_OPTIONAL policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SDM845 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SDW_MOCKUP policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SGTL5000 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SH4_FSI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SI476X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SIGMADSP policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SIGMADSP_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SIGMADSP_REGMAP policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SIMPLE_AMPLIFIER policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SIMPLE_MUX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SM8250 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SMA1303 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SMA1307 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_ACPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_COMPRESS policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT policy<{'arm64': 'n'}> +CONFIG_SND_SOC_SOF_IMX8 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_IMX9 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_SOF_IMX_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_IPC3 policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_MT8186 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_MT8195 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_MTK_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_MTK_TOPLEVEL policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_OF policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_OF_DEV policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_PCI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_TOPLEVEL policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_XTENSA policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SPDIF policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SPRD policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SPRD_MCDT policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SRC4XXX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SRC4XXX_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SSM2305 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SSM2518 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SSM2602 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SSM2602_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SSM2602_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SSM3515 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SSM4567 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STA32X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STA350 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STI_SAS policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STM32_DFSDM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STM32_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STM32_SAI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STM32_SPDIFRX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STORM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS2552 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS2562 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS2764 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS2770 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS2780 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS2781_COMLIB policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS2781_COMLIB_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS2781_FMWLIB policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS2781_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS5086 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS571X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS5720 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS5805M policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS6424 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TAS675X policy<{'arm64': 'n'}> +CONFIG_SND_SOC_TDA7419 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA186_ASRC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA186_DSPK policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA20_AC97 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA20_DAS policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA20_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA20_SPDIF policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA210_ADMAIF policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA210_ADX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA210_AHUB policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA210_AMX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA210_DMIC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA210_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA210_MIXER policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA210_MVC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA210_OPE policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA210_SFC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA30_AHUB policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA30_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_ALC5632 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_CPCAP policy<{'arm64': 'n'}> +CONFIG_SND_SOC_TEGRA_MACHINE_DRV policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_MAX98088 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_MAX98090 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_RT5631 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_RT5640 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_RT5677 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_SGTL5000 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_TRIMSLICE policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_WM8753 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_WM8903 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TEGRA_WM8962 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_TEGRA_WM9712 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TFA9879 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TFA989X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TI_EDMA_PCM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TI_SDMA_PCM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TI_UDMA_PCM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320ADC3XXX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320ADCX140 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320AIC23 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320AIC23_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320AIC23_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320AIC31XX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320AIC32X4 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320AIC32X4_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320AIC32X4_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320AIC3X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320AIC3X_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TLV320AIC3X_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TOPOLOGY policy<{'arm64': 'y'}> +CONFIG_SND_SOC_TPA6130A2 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TS3A227E policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TSCS42XX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_TSCS454 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_UDA1334 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_UDA1342 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_UDA1380 policy<{'arm64': 'n'}> +CONFIG_SND_SOC_USB policy<{'arm64': 'n'}> +CONFIG_SND_SOC_WCD9335 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WCD934X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WCD937X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WCD937X_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WCD938X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WCD938X_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WCD939X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WCD939X_SDW policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WCD_CLASSH policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WCD_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WCD_MBHC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8510 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8523 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8524 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8580 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8711 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8728 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8731 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8731_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8731_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8737 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8741 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8750 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8753 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8770 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8776 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8782 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8804 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8804_I2C policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8804_SPI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8903 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8904 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8940 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8960 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8961 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8962 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8974 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8978 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8985 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8994 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM8998 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM9712 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM_ADSP policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WM_HUBS policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WSA881X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WSA883X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_WSA884X policy<{'arm64': 'm'}> +CONFIG_SND_SOC_X1E80100 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER policy<{'arm64': 'm'}> +CONFIG_SND_SOC_XILINX_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_XILINX_SPDIF policy<{'arm64': 'm'}> +CONFIG_SND_SOC_XTFPGA_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_ZL38060 policy<{'arm64': 'm'}> +CONFIG_SND_SONICVIBES policy<{'arm64': 'm'}> +CONFIG_SND_SPI policy<{'arm64': 'y'}> +CONFIG_SND_SUN4I_CODEC policy<{'arm64': 'n'}> +CONFIG_SND_SUN4I_I2S policy<{'arm64': 'n'}> +CONFIG_SND_SUN4I_SPDIF policy<{'arm64': 'n'}> +CONFIG_SND_SUN50I_CODEC_ANALOG policy<{'arm64': 'm'}> +CONFIG_SND_SUN50I_DMIC policy<{'arm64': 'm'}> +CONFIG_SND_SUN8I_ADDA_PR_REGMAP policy<{'arm64': 'm'}> +CONFIG_SND_SUN8I_CODEC policy<{'arm64': 'm'}> +CONFIG_SND_SUN8I_CODEC_ANALOG policy<{'arm64': 'm'}> +CONFIG_SND_SUPPORT_OLD_API policy<{'arm64': 'y'}> +CONFIG_SND_SYNTH_EMUX policy<{'arm64': 'm'}> +CONFIG_SND_TEST_COMPONENT policy<{'arm64': 'm'}> +CONFIG_SND_TIMER policy<{'arm64': 'm'}> +CONFIG_SND_TRIDENT policy<{'arm64': 'm'}> +CONFIG_SND_UMP policy<{'arm64': 'm'}> +CONFIG_SND_UMP_LEGACY_RAWMIDI policy<{'arm64': 'y'}> +CONFIG_SND_USB policy<{'arm64': 'y'}> +CONFIG_SND_USB_6FIRE policy<{'arm64': 'm'}> +CONFIG_SND_USB_AUDIO policy<{'arm64': 'm'}> +CONFIG_SND_USB_AUDIO_MIDI_V2 policy<{'arm64': 'y'}> +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER policy<{'arm64': 'y'}> +CONFIG_SND_USB_CAIAQ policy<{'arm64': 'm'}> +CONFIG_SND_USB_CAIAQ_INPUT policy<{'arm64': 'y'}> +CONFIG_SND_USB_HIFACE policy<{'arm64': 'm'}> +CONFIG_SND_USB_LINE6 policy<{'arm64': 'm'}> +CONFIG_SND_USB_POD policy<{'arm64': 'm'}> +CONFIG_SND_USB_PODHD policy<{'arm64': 'm'}> +CONFIG_SND_USB_TONEPORT policy<{'arm64': 'm'}> +CONFIG_SND_USB_UA101 policy<{'arm64': 'm'}> +CONFIG_SND_USB_VARIAX policy<{'arm64': 'm'}> +CONFIG_SND_UTIMER policy<{'arm64': 'n'}> +CONFIG_SND_VERBOSE_PROCFS policy<{'arm64': 'y'}> +CONFIG_SND_VIA82XX policy<{'arm64': 'm'}> +CONFIG_SND_VIA82XX_MODEM policy<{'arm64': 'm'}> +CONFIG_SND_VIRMIDI policy<{'arm64': 'm'}> +CONFIG_SND_VIRTIO policy<{'arm64': 'm'}> +CONFIG_SND_VIRTUOSO policy<{'arm64': 'm'}> +CONFIG_SND_VMASTER policy<{'arm64': 'y'}> +CONFIG_SND_VX222 policy<{'arm64': 'm'}> +CONFIG_SND_VXPOCKET policy<{'arm64': 'n'}> +CONFIG_SND_VX_LIB policy<{'arm64': 'm'}> +CONFIG_SND_XEN_FRONTEND policy<{'arm64': 'm'}> +CONFIG_SND_YMFPCI policy<{'arm64': 'm'}> +CONFIG_SNET_VDPA policy<{'arm64': 'm'}> +CONFIG_SNI_NETSEC policy<{'arm64': 'm'}> +CONFIG_SOCFPGA_FPGA_BRIDGE policy<{'arm64': 'm'}> +CONFIG_SOCIONEXT_SYNQUACER_PREITS policy<{'arm64': 'y'}> +CONFIG_SOCK_CGROUP_DATA policy<{'arm64': 'y'}> +CONFIG_SOCK_RX_QUEUE_MAPPING policy<{'arm64': 'y'}> +CONFIG_SOCK_VALIDATE_XMIT policy<{'arm64': 'y'}> +CONFIG_SOC_BUS policy<{'arm64': 'y'}> +CONFIG_SOC_IMX8M policy<{'arm64': 'y'}> +CONFIG_SOC_IMX9 policy<{'arm64': 'm'}> +CONFIG_SOC_RENESAS policy<{'arm64': 'y'}> +CONFIG_SOC_TEGRA_CBB policy<{'arm64': 'm'}> +CONFIG_SOC_TEGRA_FLOWCTRL policy<{'arm64': 'y'}> +CONFIG_SOC_TEGRA_FUSE policy<{'arm64': 'y'}> +CONFIG_SOC_TEGRA_PMC policy<{'arm64': 'y'}> +CONFIG_SOC_TEGRA_POWERGATE_BPMP policy<{'arm64': 'y'}> +CONFIG_SOC_TI policy<{'arm64': 'y'}> +CONFIG_SOFTIRQ_ON_OWN_STACK policy<{'arm64': 'y'}> +CONFIG_SOFTLOCKUP_DETECTOR policy<{'arm64': 'y'}> +CONFIG_SOFT_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_SOFT_WATCHDOG_PRETIMEOUT policy<{'arm64': 'y'}> +CONFIG_SOLARIS_X86_PARTITION policy<{'arm64': 'y'}> +CONFIG_SONY_FF policy<{'arm64': 'y'}> +CONFIG_SOUNDWIRE_AMD policy<{'arm64': 'm'}> +CONFIG_SOUNDWIRE_CADENCE policy<{'arm64': 'm'}> +CONFIG_SOUNDWIRE_GENERIC_ALLOCATION policy<{'arm64': 'm'}> +CONFIG_SOUNDWIRE_INTEL policy<{'arm64': 'm'}> +CONFIG_SOUNDWIRE_QCOM policy<{'arm64': 'm'}> +CONFIG_SOUND_OSS_CORE policy<{'arm64': 'y'}> +CONFIG_SOUND_OSS_CORE_PRECLAIM policy<{'arm64': 'y'}> +CONFIG_SPARSEMEM policy<{'arm64': 'y'}> +CONFIG_SPARSEMEM_EXTREME policy<{'arm64': 'y'}> +CONFIG_SPARSEMEM_VMEMMAP policy<{'arm64': 'y'}> +CONFIG_SPARSEMEM_VMEMMAP_ENABLE policy<{'arm64': 'y'}> +CONFIG_SPARSE_IRQ policy<{'arm64': 'y'}> +CONFIG_SPARX5_DCB policy<{'arm64': 'y'}> +CONFIG_SPARX5_SWITCH policy<{'arm64': 'm'}> +CONFIG_SPEAKUP policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_ACNTSA policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_APOLLO policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_AUDPTR policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_BNS policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_DECEXT policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_DECTLK policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_DUMMY policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_LTLK policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_SOFT policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_SPKOUT policy<{'arm64': 'm'}> +CONFIG_SPEAKUP_SYNTH_TXPRT policy<{'arm64': 'm'}> +CONFIG_SPI policy<{'arm64': 'y'}> +CONFIG_SPI_AIROHA_SNFI policy<{'arm64': 'm'}> +CONFIG_SPI_ALTERA policy<{'arm64': 'm'}> +CONFIG_SPI_ALTERA_CORE policy<{'arm64': 'm'}> +CONFIG_SPI_ALTERA_DFL policy<{'arm64': 'm'}> +CONFIG_SPI_AMD policy<{'arm64': 'm'}> +CONFIG_SPI_AMLOGIC_SPIFC_A1 policy<{'arm64': 'm'}> +CONFIG_SPI_AMLOGIC_SPIFC_A4 policy<{'arm64': 'n'}> +CONFIG_SPI_AMLOGIC_SPISG policy<{'arm64': 'n'}> +CONFIG_SPI_APPLE policy<{'arm64': 'm'}> +CONFIG_SPI_ARMADA_3700 policy<{'arm64': 'm'}> +CONFIG_SPI_ATMEL policy<{'arm64': 'n'}> +CONFIG_SPI_AX88796C policy<{'arm64': 'm'}> +CONFIG_SPI_AX88796C_COMPRESSION policy<{'arm64': 'n'}> +CONFIG_SPI_AXI_SPI_ENGINE policy<{'arm64': 'm'}> +CONFIG_SPI_BITBANG policy<{'arm64': 'm'}> +CONFIG_SPI_BUTTERFLY policy<{'arm64': 'm'}> +CONFIG_SPI_CADENCE policy<{'arm64': 'm'}> +CONFIG_SPI_CADENCE_QUADSPI policy<{'arm64': 'm'}> +CONFIG_SPI_CADENCE_XSPI policy<{'arm64': 'm'}> +CONFIG_SPI_CH341 policy<{'arm64': 'm'}> +CONFIG_SPI_CS42L43 policy<{'arm64': 'm'}> +CONFIG_SPI_DEBUG policy<{'arm64': 'n'}> +CONFIG_SPI_DESIGNWARE policy<{'arm64': 'm'}> +CONFIG_SPI_DLN2 policy<{'arm64': 'm'}> +CONFIG_SPI_DW_DMA policy<{'arm64': 'y'}> +CONFIG_SPI_DW_MMIO policy<{'arm64': 'm'}> +CONFIG_SPI_DW_PCI policy<{'arm64': 'm'}> +CONFIG_SPI_DYNAMIC policy<{'arm64': 'y'}> +CONFIG_SPI_FSI policy<{'arm64': 'm'}> +CONFIG_SPI_FSL_DSPI policy<{'arm64': 'm'}> +CONFIG_SPI_FSL_LIB policy<{'arm64': 'y'}> +CONFIG_SPI_FSL_LPSPI policy<{'arm64': 'm'}> +CONFIG_SPI_FSL_QUADSPI policy<{'arm64': 'm'}> +CONFIG_SPI_FSL_SPI policy<{'arm64': 'y'}> +CONFIG_SPI_GPIO policy<{'arm64': 'm'}> +CONFIG_SPI_HID policy<{'arm64': 'm'}> +CONFIG_SPI_HID_ACPI policy<{'arm64': 'n'}> +CONFIG_SPI_HID_OF policy<{'arm64': 'n'}> +CONFIG_SPI_HISI_KUNPENG policy<{'arm64': 'm'}> +CONFIG_SPI_HISI_SFC policy<{'arm64': 'm'}> +CONFIG_SPI_HISI_SFC_V3XX policy<{'arm64': 'm'}> +CONFIG_SPI_IMX policy<{'arm64': 'm'}> +CONFIG_SPI_KSPI2 policy<{'arm64': 'n'}> +CONFIG_SPI_LJCA policy<{'arm64': 'm'}> +CONFIG_SPI_LM70_LLP policy<{'arm64': 'm'}> +CONFIG_SPI_LOOPBACK_TEST policy<{'arm64': 'm'}> +CONFIG_SPI_MASTER policy<{'arm64': 'y'}> +CONFIG_SPI_MEM policy<{'arm64': 'y'}> +CONFIG_SPI_MESON_SPICC policy<{'arm64': 'm'}> +CONFIG_SPI_MESON_SPIFC policy<{'arm64': 'm'}> +CONFIG_SPI_MICROCHIP_CORE_QSPI policy<{'arm64': 'm'}> +CONFIG_SPI_MICROCHIP_CORE_SPI policy<{'arm64': 'n'}> +CONFIG_SPI_MT65XX policy<{'arm64': 'm'}> +CONFIG_SPI_MTK_NOR policy<{'arm64': 'm'}> +CONFIG_SPI_MTK_SNFI policy<{'arm64': 'm'}> +CONFIG_SPI_MUX policy<{'arm64': 'm'}> +CONFIG_SPI_MXIC policy<{'arm64': 'm'}> +CONFIG_SPI_NPCM_FIU policy<{'arm64': 'm'}> +CONFIG_SPI_NPCM_PSPI policy<{'arm64': 'm'}> +CONFIG_SPI_NXP_FLEXSPI policy<{'arm64': 'm'}> +CONFIG_SPI_NXP_XSPI policy<{'arm64': 'n'}> +CONFIG_SPI_OC_TINY policy<{'arm64': 'm'}> +CONFIG_SPI_OFFLOAD policy<{'arm64': 'y'}> +CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD policy<{'arm64': 'n'}> +CONFIG_SPI_OFFLOAD_TRIGGER_PWM policy<{'arm64': 'm'}> +CONFIG_SPI_OMAP24XX policy<{'arm64': 'y'}> +CONFIG_SPI_ORION policy<{'arm64': 'm'}> +CONFIG_SPI_PCI1XXXX policy<{'arm64': 'm'}> +CONFIG_SPI_PL022 policy<{'arm64': 'm'}> +CONFIG_SPI_POLARFIRE_SOC policy<{'arm64': 'n'}> +CONFIG_SPI_QCOM_GENI policy<{'arm64': 'm'}> +CONFIG_SPI_QCOM_QSPI policy<{'arm64': 'm'}> +CONFIG_SPI_QPIC_SNAND policy<{'arm64': 'n'}> +CONFIG_SPI_QUP policy<{'arm64': 'm'}> +CONFIG_SPI_ROCKCHIP policy<{'arm64': 'm'}> +CONFIG_SPI_ROCKCHIP_SFC policy<{'arm64': 'm'}> +CONFIG_SPI_RPCIF policy<{'arm64': 'm'}> +CONFIG_SPI_RSPI policy<{'arm64': 'm'}> +CONFIG_SPI_RZV2H_RSPI policy<{'arm64': 'n'}> +CONFIG_SPI_RZV2M_CSI policy<{'arm64': 'm'}> +CONFIG_SPI_SC18IS602 policy<{'arm64': 'm'}> +CONFIG_SPI_SH_HSPI policy<{'arm64': 'm'}> +CONFIG_SPI_SH_MSIOF policy<{'arm64': 'm'}> +CONFIG_SPI_SIFIVE policy<{'arm64': 'm'}> +CONFIG_SPI_SLAVE policy<{'arm64': 'y'}> +CONFIG_SPI_SLAVE_MT27XX policy<{'arm64': 'm'}> +CONFIG_SPI_SLAVE_SYSTEM_CONTROL policy<{'arm64': 'm'}> +CONFIG_SPI_SLAVE_TIME policy<{'arm64': 'm'}> +CONFIG_SPI_SN_F_OSPI policy<{'arm64': 'm'}> +CONFIG_SPI_SPIDEV policy<{'arm64': 'm'}> +CONFIG_SPI_SPRD policy<{'arm64': 'm'}> +CONFIG_SPI_SPRD_ADI policy<{'arm64': 'm'}> +CONFIG_SPI_STM32 policy<{'arm64': 'm'}> +CONFIG_SPI_STM32_OSPI policy<{'arm64': 'n'}> +CONFIG_SPI_STM32_QSPI policy<{'arm64': 'm'}> +CONFIG_SPI_SUN4I policy<{'arm64': 'n'}> +CONFIG_SPI_SUN6I policy<{'arm64': 'm'}> +CONFIG_SPI_SYNQUACER policy<{'arm64': 'm'}> +CONFIG_SPI_TEGRA114 policy<{'arm64': 'm'}> +CONFIG_SPI_TEGRA20_SFLASH policy<{'arm64': 'm'}> +CONFIG_SPI_TEGRA20_SLINK policy<{'arm64': 'm'}> +CONFIG_SPI_TEGRA210_QUAD policy<{'arm64': 'y'}> +CONFIG_SPI_THUNDERX policy<{'arm64': 'm'}> +CONFIG_SPI_TLE62X0 policy<{'arm64': 'm'}> +CONFIG_SPI_VIRTIO policy<{'arm64': 'n'}> +CONFIG_SPI_WPCM_FIU policy<{'arm64': 'm'}> +CONFIG_SPI_XCOMM policy<{'arm64': 'm'}> +CONFIG_SPI_XILINX policy<{'arm64': 'm'}> +CONFIG_SPI_XLP policy<{'arm64': 'm'}> +CONFIG_SPI_ZYNQMP_GQSPI policy<{'arm64': 'm'}> +CONFIG_SPLIT_PMD_PTLOCKS policy<{'arm64': 'y'}> +CONFIG_SPLIT_PTE_PTLOCKS policy<{'arm64': 'y'}> +CONFIG_SPMI policy<{'arm64': 'y'}> +CONFIG_SPMI_APPLE policy<{'arm64': 'n'}> +CONFIG_SPMI_HISI3670 policy<{'arm64': 'n'}> +CONFIG_SPMI_MSM_PMIC_ARB policy<{'arm64': 'y'}> +CONFIG_SPMI_MTK_PMIF policy<{'arm64': 'y'}> +CONFIG_SPMI_PMIC_CLKDIV policy<{'arm64': 'm'}> +CONFIG_SPRD_COMMON_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_DMA policy<{'arm64': 'm'}> +CONFIG_SPRD_IOMMU policy<{'arm64': 'm'}> +CONFIG_SPRD_MBOX policy<{'arm64': 'm'}> +CONFIG_SPRD_SC9860_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_SC9863A_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_THERMAL policy<{'arm64': 'm'}> +CONFIG_SPRD_TIMER policy<{'arm64': 'y'}> +CONFIG_SPRD_UMS512_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_SPS30 policy<{'arm64': 'm'}> +CONFIG_SPS30_I2C policy<{'arm64': 'm'}> +CONFIG_SPS30_SERIAL policy<{'arm64': 'm'}> +CONFIG_SQUASHFS_4K_DEVBLK_SIZE policy<{'arm64': 'n'}> +CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_COMP_CACHE_FULL policy<{'arm64': 'n'}> +CONFIG_SQUASHFS_DECOMP_MULTI policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_DECOMP_SINGLE policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_EMBEDDED policy<{'arm64': 'n'}> +CONFIG_SQUASHFS_FILE_CACHE policy<{'arm64': 'n'}> +CONFIG_SQUASHFS_FILE_DIRECT policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE policy<{'arm64': '3'}> +CONFIG_SQUASHFS_LZ4 policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_LZO policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_MOUNT_DECOMP_THREADS policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_XATTR policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_XZ policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_ZLIB policy<{'arm64': 'y'}> +CONFIG_SQUASHFS_ZSTD policy<{'arm64': 'y'}> +CONFIG_SRAM policy<{'arm64': 'y'}> +CONFIG_SRF04 policy<{'arm64': 'm'}> +CONFIG_SRF08 policy<{'arm64': 'm'}> +CONFIG_SSB policy<{'arm64': 'm'}> +CONFIG_SSB_B43_PCI_BRIDGE policy<{'arm64': 'y'}> +CONFIG_SSB_BLOCKIO policy<{'arm64': 'y'}> +CONFIG_SSB_DRIVER_GPIO policy<{'arm64': 'y'}> +CONFIG_SSB_DRIVER_PCICORE policy<{'arm64': 'y'}> +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE policy<{'arm64': 'y'}> +CONFIG_SSB_PCIHOST policy<{'arm64': 'y'}> +CONFIG_SSB_PCIHOST_POSSIBLE policy<{'arm64': 'y'}> +CONFIG_SSB_PCMCIAHOST policy<{'arm64': 'n'}> +CONFIG_SSB_PCMCIAHOST_POSSIBLE policy<{'arm64': 'y'}> +CONFIG_SSB_POSSIBLE policy<{'arm64': 'y'}> +CONFIG_SSB_SDIOHOST policy<{'arm64': 'y'}> +CONFIG_SSB_SDIOHOST_POSSIBLE policy<{'arm64': 'y'}> +CONFIG_SSB_SPROM policy<{'arm64': 'y'}> +CONFIG_SSFDC policy<{'arm64': 'm'}> +CONFIG_SSIF_IPMI_BMC policy<{'arm64': 'm'}> +CONFIG_STACKDEPOT policy<{'arm64': 'y'}> +CONFIG_STACKDEPOT_MAX_FRAMES policy<{'arm64': '64'}> +CONFIG_STACKPROTECTOR policy<{'arm64': 'y'}> +CONFIG_STACKPROTECTOR_PER_TASK policy<{'arm64': 'y'}> +CONFIG_STACKPROTECTOR_STRONG policy<{'arm64': 'y'}> +CONFIG_STACKTRACE policy<{'arm64': 'y'}> +CONFIG_STACKTRACE_BUILD_ID policy<{'arm64': 'n'}> +CONFIG_STACKTRACE_SUPPORT policy<{'arm64': 'y'}> +CONFIG_STACK_TRACER policy<{'arm64': 'y'}> +CONFIG_STAGING policy<{'arm64': 'y'}> +CONFIG_STAGING_MEDIA policy<{'arm64': 'y'}> +CONFIG_STAGING_MEDIA_DEPRECATED policy<{'arm64': 'n'}> +CONFIG_STANDALONE policy<{'arm64': 'y'}> +CONFIG_STATIC_KEYS_SELFTEST policy<{'arm64': 'n'}> +CONFIG_STATIC_USERMODEHELPER policy<{'arm64': 'n'}> +CONFIG_STE10XP policy<{'arm64': 'm'}> +CONFIG_STEAM_FF policy<{'arm64': 'y'}> +CONFIG_STK3310 policy<{'arm64': 'm'}> +CONFIG_STK8312 policy<{'arm64': 'm'}> +CONFIG_STK8BA50 policy<{'arm64': 'm'}> +CONFIG_STM policy<{'arm64': 'm'}> +CONFIG_STM32MP_EXTI policy<{'arm64': 'm'}> +CONFIG_STM32_ADC policy<{'arm64': 'm'}> +CONFIG_STM32_ADC_CORE policy<{'arm64': 'm'}> +CONFIG_STM32_DAC policy<{'arm64': 'm'}> +CONFIG_STM32_DAC_CORE policy<{'arm64': 'm'}> +CONFIG_STM32_DBG_BUS policy<{'arm64': 'n'}> +CONFIG_STM32_DFSDM_ADC policy<{'arm64': 'm'}> +CONFIG_STM32_DFSDM_CORE policy<{'arm64': 'm'}> +CONFIG_STM32_DMA policy<{'arm64': 'y'}> +CONFIG_STM32_DMA3 policy<{'arm64': 'm'}> +CONFIG_STM32_DMAMUX policy<{'arm64': 'y'}> +CONFIG_STM32_FIREWALL policy<{'arm64': 'y'}> +CONFIG_STM32_FMC2_EBI policy<{'arm64': 'm'}> +CONFIG_STM32_LPTIMER_CNT policy<{'arm64': 'm'}> +CONFIG_STM32_MDMA policy<{'arm64': 'y'}> +CONFIG_STM32_RPROC policy<{'arm64': 'm'}> +CONFIG_STM32_TIMER_CNT policy<{'arm64': 'm'}> +CONFIG_STM32_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_STMMAC_ETH policy<{'arm64': 'm'}> +CONFIG_STMMAC_LIBPCI policy<{'arm64': 'm'}> +CONFIG_STMMAC_PCI policy<{'arm64': 'm'}> +CONFIG_STMMAC_PLATFORM policy<{'arm64': 'm'}> +CONFIG_STMMAC_SELFTESTS policy<{'arm64': 'n'}> +CONFIG_STMPE_ADC policy<{'arm64': 'm'}> +CONFIG_STMPE_I2C policy<{'arm64': 'y'}> +CONFIG_STMPE_SPI policy<{'arm64': 'y'}> +CONFIG_STMP_DEVICE policy<{'arm64': 'y'}> +CONFIG_STM_DUMMY policy<{'arm64': 'm'}> +CONFIG_STM_PROTO_BASIC policy<{'arm64': 'm'}> +CONFIG_STM_PROTO_SYS_T policy<{'arm64': 'm'}> +CONFIG_STM_SOURCE_CONSOLE policy<{'arm64': 'm'}> +CONFIG_STM_SOURCE_FTRACE policy<{'arm64': 'm'}> +CONFIG_STM_SOURCE_HEARTBEAT policy<{'arm64': 'm'}> +CONFIG_STP policy<{'arm64': 'm'}> +CONFIG_STPMIC1_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_STREAM_PARSER policy<{'arm64': 'y'}> +CONFIG_STRICT_DEVMEM policy<{'arm64': 'y'}> +CONFIG_STRICT_KERNEL_RWX policy<{'arm64': 'y'}> +CONFIG_STRICT_MODULE_RWX policy<{'arm64': 'y'}> +CONFIG_STRIP_ASM_SYMS policy<{'arm64': 'n'}> +CONFIG_STUB_CLK_HI3660 policy<{'arm64': 'y'}> +CONFIG_STUB_CLK_HI6220 policy<{'arm64': 'y'}> +CONFIG_ST_THERMAL policy<{'arm64': 'm'}> +CONFIG_ST_THERMAL_MEMMAP policy<{'arm64': 'm'}> +CONFIG_ST_UVIS25 policy<{'arm64': 'm'}> +CONFIG_ST_UVIS25_I2C policy<{'arm64': 'm'}> +CONFIG_ST_UVIS25_SPI policy<{'arm64': 'm'}> +CONFIG_SUN20I_GPADC policy<{'arm64': 'm'}> +CONFIG_SUN20I_PPU policy<{'arm64': 'y'}> +CONFIG_SUN4I_EMAC policy<{'arm64': 'n'}> +CONFIG_SUN4I_GPADC policy<{'arm64': 'n'}> +CONFIG_SUN4I_TIMER policy<{'arm64': 'y'}> +CONFIG_SUN50I_A100_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_A100_R_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_A64_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_DE2_BUS policy<{'arm64': 'y'}> +CONFIG_SUN50I_ERRATUM_UNKNOWN1 policy<{'arm64': 'y'}> +CONFIG_SUN50I_H616_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_H6_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_H6_PRCM_PPU policy<{'arm64': 'n'}> +CONFIG_SUN50I_H6_R_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_IOMMU policy<{'arm64': 'y'}> +CONFIG_SUN55I_A523_CCU policy<{'arm64': 'y'}> +CONFIG_SUN55I_A523_MCU_CCU policy<{'arm64': 'y'}> +CONFIG_SUN55I_A523_R_CCU policy<{'arm64': 'y'}> +CONFIG_SUN55I_PCK600 policy<{'arm64': 'y'}> +CONFIG_SUN6I_MSGBOX policy<{'arm64': 'y'}> +CONFIG_SUN6I_RTC_CCU policy<{'arm64': 'm'}> +CONFIG_SUN6I_R_INTC policy<{'arm64': 'y'}> +CONFIG_SUN8I_DE2_CCU policy<{'arm64': 'y'}> +CONFIG_SUN8I_H3_CCU policy<{'arm64': 'y'}> +CONFIG_SUN8I_R_CCU policy<{'arm64': 'y'}> +CONFIG_SUN8I_THERMAL policy<{'arm64': 'm'}> +CONFIG_SUNDANCE policy<{'arm64': 'n'}> +CONFIG_SUNGEM policy<{'arm64': 'm'}> +CONFIG_SUNGEM_PHY policy<{'arm64': 'm'}> +CONFIG_SUNRPC policy<{'arm64': 'm'}> +CONFIG_SUNRPC_BACKCHANNEL policy<{'arm64': 'y'}> +CONFIG_SUNRPC_DEBUG policy<{'arm64': 'y'}> +CONFIG_SUNRPC_DEBUG_TRACE policy<{'arm64': 'n'}> +CONFIG_SUNRPC_GSS policy<{'arm64': 'm'}> +CONFIG_SUNRPC_SWAP policy<{'arm64': 'y'}> +CONFIG_SUNRPC_XPRT_RDMA policy<{'arm64': 'm'}> +CONFIG_SUNXI_CCU policy<{'arm64': 'y'}> +CONFIG_SUNXI_MBUS policy<{'arm64': 'y'}> +CONFIG_SUNXI_NMI_INTC policy<{'arm64': 'y'}> +CONFIG_SUNXI_RSB policy<{'arm64': 'm'}> +CONFIG_SUNXI_SRAM policy<{'arm64': 'y'}> +CONFIG_SUNXI_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_SUN_PARTITION policy<{'arm64': 'y'}> +CONFIG_SURFACE_3_POWER_OPREGION policy<{'arm64': 'n'}> +CONFIG_SURFACE_ACPI_NOTIFY policy<{'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR policy<{'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_BUS policy<{'arm64': 'y'}> +CONFIG_SURFACE_AGGREGATOR_CDEV policy<{'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION policy<{'arm64': 'n'}> +CONFIG_SURFACE_AGGREGATOR_HUB policy<{'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_REGISTRY policy<{'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH policy<{'arm64': 'm'}> +CONFIG_SURFACE_DTX policy<{'arm64': 'm'}> +CONFIG_SURFACE_GPE policy<{'arm64': 'm'}> +CONFIG_SURFACE_HID policy<{'arm64': 'm'}> +CONFIG_SURFACE_HID_CORE policy<{'arm64': 'm'}> +CONFIG_SURFACE_HOTPLUG policy<{'arm64': 'm'}> +CONFIG_SURFACE_KBD policy<{'arm64': 'm'}> +CONFIG_SURFACE_PLATFORMS policy<{'arm64': 'y'}> +CONFIG_SURFACE_PLATFORM_PROFILE policy<{'arm64': 'm'}> +CONFIG_SURFACE_PRO3_BUTTON policy<{'arm64': 'n'}> +CONFIG_SUSPEND policy<{'arm64': 'y'}> +CONFIG_SUSPEND_FREEZER policy<{'arm64': 'y'}> +CONFIG_SUSPEND_SKIP_SYNC policy<{'arm64': 'n'}> +CONFIG_SVC_I3C_MASTER policy<{'arm64': 'm'}> +CONFIG_SWAP policy<{'arm64': 'y'}> +CONFIG_SWIOTLB policy<{'arm64': 'y'}> +CONFIG_SWIOTLB_DYNAMIC policy<{'arm64': 'y'}> +CONFIG_SWIOTLB_XEN policy<{'arm64': 'y'}> +CONFIG_SWITCHTEC_DMA policy<{'arm64': 'n'}> +CONFIG_SWPHY policy<{'arm64': 'y'}> +CONFIG_SW_SYNC policy<{'arm64': 'y'}> +CONFIG_SX9310 policy<{'arm64': 'm'}> +CONFIG_SX9324 policy<{'arm64': 'm'}> +CONFIG_SX9360 policy<{'arm64': 'm'}> +CONFIG_SX9500 policy<{'arm64': 'm'}> +CONFIG_SXGBE_ETH policy<{'arm64': 'm'}> +CONFIG_SX_COMMON policy<{'arm64': 'm'}> +CONFIG_SYMBOLIC_ERRNAME policy<{'arm64': 'y'}> +CONFIG_SYNC_FILE policy<{'arm64': 'y'}> +CONFIG_SYNTH_EVENTS policy<{'arm64': 'y'}> +CONFIG_SYNTH_EVENT_GEN_TEST policy<{'arm64': 'n'}> +CONFIG_SYN_COOKIES policy<{'arm64': 'y'}> +CONFIG_SYSCON_REBOOT_MODE policy<{'arm64': 'm'}> +CONFIG_SYSCTL policy<{'arm64': 'y'}> +CONFIG_SYSCTL_EXCEPTION_TRACE policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A7795 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77960 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77961 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77965 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77970 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77980 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77990 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77995 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R9A08G045 policy<{'arm64': 'y'}> +CONFIG_SYSC_R9A08G046 policy<{'arm64': 'y'}> +CONFIG_SYSC_RCAR policy<{'arm64': 'y'}> +CONFIG_SYSC_RCAR_GEN4 policy<{'arm64': 'y'}> +CONFIG_SYSC_RZ policy<{'arm64': 'y'}> +CONFIG_SYSFB policy<{'arm64': 'y'}> +CONFIG_SYSFB_SIMPLEFB policy<{'arm64': 'y'}> +CONFIG_SYSFS policy<{'arm64': 'y'}> +CONFIG_SYSFS_SYSCALL policy<{'arm64': 'y'}> +CONFIG_SYSTEMPORT policy<{'arm64': 'm'}> +CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE policy<{'arm64': 'n'}> +CONFIG_SYSTEM_BLACKLIST_HASH_LIST policy<{'arm64': '""'}> +CONFIG_SYSTEM_BLACKLIST_KEYRING policy<{'arm64': 'y'}> +CONFIG_SYSTEM_DATA_VERIFICATION policy<{'arm64': 'y'}> +CONFIG_SYSTEM_EXTRA_CERTIFICATE policy<{'arm64': 'y'}> +CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE policy<{'arm64': '4096'}> +CONFIG_SYSTEM_REVOCATION_KEYS policy<{'arm64': '""'}> +CONFIG_SYSTEM_REVOCATION_LIST policy<{'arm64': 'y'}> +CONFIG_SYSTEM_TRUSTED_KEYRING policy<{'arm64': 'y'}> +CONFIG_SYSTEM_TRUSTED_KEYS policy<{'arm64': '""'}> +CONFIG_SYSV68_PARTITION policy<{'arm64': 'y'}> +CONFIG_SYSVIPC policy<{'arm64': 'y'}> +CONFIG_SYSVIPC_COMPAT policy<{'arm64': 'y'}> +CONFIG_SYSVIPC_SYSCTL policy<{'arm64': 'y'}> +CONFIG_SYS_HYPERVISOR policy<{'arm64': 'y'}> +CONFIG_SYS_R9A09G056 policy<{'arm64': 'y'}> +CONFIG_SYS_R9A09G057 policy<{'arm64': 'y'}> +CONFIG_SYS_SUPPORTS_SH_CMT policy<{'arm64': 'y'}> +CONFIG_SYS_SUPPORTS_SH_TMU policy<{'arm64': 'y'}> +CONFIG_T5403 policy<{'arm64': 'm'}> +CONFIG_TABLET_SERIAL_WACOM4 policy<{'arm64': 'm'}> +CONFIG_TABLET_USB_ACECAD policy<{'arm64': 'm'}> +CONFIG_TABLET_USB_AIPTEK policy<{'arm64': 'm'}> +CONFIG_TABLET_USB_HANWANG policy<{'arm64': 'm'}> +CONFIG_TABLET_USB_KBTAB policy<{'arm64': 'm'}> +CONFIG_TABLET_USB_PEGASUS policy<{'arm64': 'm'}> +CONFIG_TAHVO_USB policy<{'arm64': 'm'}> +CONFIG_TAHVO_USB_HOST_BY_DEFAULT policy<{'arm64': 'y'}> +CONFIG_TAP policy<{'arm64': 'm'}> +CONFIG_TARGET_CORE policy<{'arm64': 'm'}> +CONFIG_TASKSTATS policy<{'arm64': 'y'}> +CONFIG_TASKS_RCU policy<{'arm64': 'y'}> +CONFIG_TASKS_RCU_GENERIC policy<{'arm64': 'y'}> +CONFIG_TASKS_RUDE_RCU policy<{'arm64': 'y'}> +CONFIG_TASKS_TRACE_RCU policy<{'arm64': 'y'}> +CONFIG_TASK_DELAY_ACCT policy<{'arm64': 'y'}> +CONFIG_TASK_IO_ACCOUNTING policy<{'arm64': 'y'}> +CONFIG_TASK_XACCT policy<{'arm64': 'y'}> +CONFIG_TCG_ARM_CRB_FFA policy<{'arm64': 'm'}> +CONFIG_TCG_ATMEL policy<{'arm64': 'm'}> +CONFIG_TCG_CRB policy<{'arm64': 'y'}> +CONFIG_TCG_FTPM_TEE policy<{'arm64': 'm'}> +CONFIG_TCG_INFINEON policy<{'arm64': 'm'}> +CONFIG_TCG_TIS policy<{'arm64': 'y'}> +CONFIG_TCG_TIS_CORE policy<{'arm64': 'y'}> +CONFIG_TCG_TIS_I2C policy<{'arm64': 'm'}> +CONFIG_TCG_TIS_I2C_CR50 policy<{'arm64': 'm'}> +CONFIG_TCG_TIS_SPI policy<{'arm64': 'y'}> +CONFIG_TCG_TIS_SPI_CR50 policy<{'arm64': 'y'}> +CONFIG_TCG_TIS_ST33ZP24 policy<{'arm64': 'm'}> +CONFIG_TCG_TIS_ST33ZP24_I2C policy<{'arm64': 'm'}> +CONFIG_TCG_TIS_ST33ZP24_SPI policy<{'arm64': 'm'}> +CONFIG_TCG_TIS_SYNQUACER policy<{'arm64': 'm'}> +CONFIG_TCG_TPM2_HMAC policy<{'arm64': 'n'}> +CONFIG_TCG_VTPM_PROXY policy<{'arm64': 'm'}> +CONFIG_TCG_XEN policy<{'arm64': 'm'}> +CONFIG_TCM_FC policy<{'arm64': 'm'}> +CONFIG_TCM_FILEIO policy<{'arm64': 'm'}> +CONFIG_TCM_IBLOCK policy<{'arm64': 'm'}> +CONFIG_TCM_PSCSI policy<{'arm64': 'm'}> +CONFIG_TCM_QLA2XXX policy<{'arm64': 'm'}> +CONFIG_TCM_QLA2XXX_DEBUG policy<{'arm64': 'n'}> +CONFIG_TCM_USER2 policy<{'arm64': 'm'}> +CONFIG_TCP_AO policy<{'arm64': 'y'}> +CONFIG_TCP_CONG_ADVANCED policy<{'arm64': 'y'}> +CONFIG_TCP_CONG_BBR policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_BIC policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_CDG policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_CUBIC policy<{'arm64': 'y'}> +CONFIG_TCP_CONG_DCTCP policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_HSTCP policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_HTCP policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_HYBLA policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_ILLINOIS policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_LP policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_NV policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_SCALABLE policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_VEGAS policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_VENO policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_WESTWOOD policy<{'arm64': 'm'}> +CONFIG_TCP_CONG_YEAH policy<{'arm64': 'm'}> +CONFIG_TCP_MD5SIG policy<{'arm64': 'y'}> +CONFIG_TCS3414 policy<{'arm64': 'm'}> +CONFIG_TCS3472 policy<{'arm64': 'm'}> +CONFIG_TEE policy<{'arm64': 'm'}> +CONFIG_TEE_DMABUF_HEAPS policy<{'arm64': 'y'}> +CONFIG_TEE_STMM_EFI policy<{'arm64': 'n'}> +CONFIG_TEGRA186_GPC_DMA policy<{'arm64': 'm'}> +CONFIG_TEGRA186_TIMER policy<{'arm64': 'y'}> +CONFIG_TEGRA20_APB_DMA policy<{'arm64': 'y'}> +CONFIG_TEGRA210_ADMA policy<{'arm64': 'm'}> +CONFIG_TEGRA210_EMC policy<{'arm64': 'm'}> +CONFIG_TEGRA210_EMC_TABLE policy<{'arm64': 'y'}> +CONFIG_TEGRA241_CMDQV policy<{'arm64': 'n'}> +CONFIG_TEGRA_ACONNECT policy<{'arm64': 'm'}> +CONFIG_TEGRA_AHB policy<{'arm64': 'y'}> +CONFIG_TEGRA_BPMP policy<{'arm64': 'y'}> +CONFIG_TEGRA_BPMP_THERMAL policy<{'arm64': 'm'}> +CONFIG_TEGRA_CLK_DFLL policy<{'arm64': 'y'}> +CONFIG_TEGRA_GMI policy<{'arm64': 'm'}> +CONFIG_TEGRA_HOST1X policy<{'arm64': 'm'}> +CONFIG_TEGRA_HOST1X_CONTEXT_BUS policy<{'arm64': 'y'}> +CONFIG_TEGRA_HOST1X_FIREWALL policy<{'arm64': 'y'}> +CONFIG_TEGRA_HSP_MBOX policy<{'arm64': 'y'}> +CONFIG_TEGRA_IOMMU_SMMU policy<{'arm64': 'y'}> +CONFIG_TEGRA_IVC policy<{'arm64': 'y'}> +CONFIG_TEGRA_MC policy<{'arm64': 'y'}> +CONFIG_TEGRA_SOCTHERM policy<{'arm64': 'n'}> +CONFIG_TEGRA_TIMER policy<{'arm64': 'y'}> +CONFIG_TEGRA_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_TEHUTI policy<{'arm64': 'm'}> +CONFIG_TEHUTI_TN40 policy<{'arm64': 'm'}> +CONFIG_TERANETICS_PHY policy<{'arm64': 'm'}> +CONFIG_TEST_ASYNC_DRIVER_PROBE policy<{'arm64': 'n'}> +CONFIG_TEST_BITMAP policy<{'arm64': 'n'}> +CONFIG_TEST_BITOPS policy<{'arm64': 'n'}> +CONFIG_TEST_BPF policy<{'arm64': 'm'}> +CONFIG_TEST_DHRY policy<{'arm64': 'n'}> +CONFIG_TEST_DIV64 policy<{'arm64': 'n'}> +CONFIG_TEST_DYNAMIC_DEBUG policy<{'arm64': 'n'}> +CONFIG_TEST_FIRMWARE policy<{'arm64': 'n'}> +CONFIG_TEST_FPU policy<{'arm64': 'n'}> +CONFIG_TEST_FREE_PAGES policy<{'arm64': 'n'}> +CONFIG_TEST_HEXDUMP policy<{'arm64': 'n'}> +CONFIG_TEST_HMM policy<{'arm64': 'n'}> +CONFIG_TEST_IDA policy<{'arm64': 'n'}> +CONFIG_TEST_KALLSYMS policy<{'arm64': 'n'}> +CONFIG_TEST_KMOD policy<{'arm64': 'n'}> +CONFIG_TEST_KSTRTOX policy<{'arm64': 'n'}> +CONFIG_TEST_LKM policy<{'arm64': 'n'}> +CONFIG_TEST_LOCKUP policy<{'arm64': 'n'}> +CONFIG_TEST_MAPLE_TREE policy<{'arm64': 'n'}> +CONFIG_TEST_MEMCAT_P policy<{'arm64': 'n'}> +CONFIG_TEST_MEMINIT policy<{'arm64': 'n'}> +CONFIG_TEST_MULDIV64 policy<{'arm64': 'n'}> +CONFIG_TEST_OBJAGG policy<{'arm64': 'n'}> +CONFIG_TEST_OBJPOOL policy<{'arm64': 'n'}> +CONFIG_TEST_PARMAN policy<{'arm64': 'n'}> +CONFIG_TEST_POWER policy<{'arm64': 'm'}> +CONFIG_TEST_REF_TRACKER policy<{'arm64': 'n'}> +CONFIG_TEST_RHASHTABLE policy<{'arm64': 'n'}> +CONFIG_TEST_STATIC_KEYS policy<{'arm64': 'n'}> +CONFIG_TEST_SYSCTL policy<{'arm64': 'n'}> +CONFIG_TEST_UBSAN policy<{'arm64': 'n'}> +CONFIG_TEST_UDELAY policy<{'arm64': 'n'}> +CONFIG_TEST_VMALLOC policy<{'arm64': 'n'}> +CONFIG_TEST_WORKQUEUE policy<{'arm64': 'n'}> +CONFIG_TEST_XARRAY policy<{'arm64': 'n'}> +CONFIG_TEXTSEARCH policy<{'arm64': 'y'}> +CONFIG_TEXTSEARCH_BM policy<{'arm64': 'm'}> +CONFIG_TEXTSEARCH_FSM policy<{'arm64': 'm'}> +CONFIG_TEXTSEARCH_KMP policy<{'arm64': 'm'}> +CONFIG_THERMAL policy<{'arm64': 'y'}> +CONFIG_THERMAL_CORE_TESTING policy<{'arm64': 'm'}> +CONFIG_THERMAL_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG policy<{'arm64': 'n'}> +CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE policy<{'arm64': 'n'}> +CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR policy<{'arm64': 'n'}> +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE policy<{'arm64': 'y'}> +CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE policy<{'arm64': 'n'}> +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS policy<{'arm64': '0'}> +CONFIG_THERMAL_EMULATION policy<{'arm64': 'y'}> +CONFIG_THERMAL_GOV_BANG_BANG policy<{'arm64': 'y'}> +CONFIG_THERMAL_GOV_FAIR_SHARE policy<{'arm64': 'y'}> +CONFIG_THERMAL_GOV_POWER_ALLOCATOR policy<{'arm64': 'y'}> +CONFIG_THERMAL_GOV_STEP_WISE policy<{'arm64': 'y'}> +CONFIG_THERMAL_GOV_USER_SPACE policy<{'arm64': 'y'}> +CONFIG_THERMAL_HWMON policy<{'arm64': 'y'}> +CONFIG_THERMAL_MMIO policy<{'arm64': 'm'}> +CONFIG_THERMAL_NETLINK policy<{'arm64': 'y'}> +CONFIG_THERMAL_OF policy<{'arm64': 'y'}> +CONFIG_THERMAL_STATISTICS policy<{'arm64': 'y'}> +CONFIG_THP_SWAP policy<{'arm64': 'y'}> +CONFIG_THREAD_INFO_IN_TASK policy<{'arm64': 'y'}> +CONFIG_THRUSTMASTER_FF policy<{'arm64': 'y'}> +CONFIG_THUNDERX2_PMU policy<{'arm64': 'm'}> +CONFIG_THUNDER_NIC_BGX policy<{'arm64': 'm'}> +CONFIG_THUNDER_NIC_PF policy<{'arm64': 'm'}> +CONFIG_THUNDER_NIC_RGX policy<{'arm64': 'm'}> +CONFIG_THUNDER_NIC_VF policy<{'arm64': 'm'}> +CONFIG_TICK_ONESHOT policy<{'arm64': 'y'}> +CONFIG_TIFM_7XX1 policy<{'arm64': 'm'}> +CONFIG_TIFM_CORE policy<{'arm64': 'm'}> +CONFIG_TIGON3 policy<{'arm64': 'm'}> +CONFIG_TIGON3_HWMON policy<{'arm64': 'y'}> +CONFIG_TIMERFD policy<{'arm64': 'y'}> +CONFIG_TIMER_ACPI policy<{'arm64': 'y'}> +CONFIG_TIMER_IMX_SYS_CTR policy<{'arm64': 'y'}> +CONFIG_TIMER_OF policy<{'arm64': 'y'}> +CONFIG_TIMER_PROBE policy<{'arm64': 'y'}> +CONFIG_TIME_NS policy<{'arm64': 'y'}> +CONFIG_TIME_NS_VDSO policy<{'arm64': 'y'}> +CONFIG_TINYDRM_HX8357D policy<{'arm64': 'm'}> +CONFIG_TINYDRM_ILI9163 policy<{'arm64': 'm'}> +CONFIG_TINYDRM_ILI9225 policy<{'arm64': 'm'}> +CONFIG_TINYDRM_ILI9341 policy<{'arm64': 'm'}> +CONFIG_TINYDRM_ILI9486 policy<{'arm64': 'm'}> +CONFIG_TINYDRM_MI0283QT policy<{'arm64': 'm'}> +CONFIG_TINYDRM_REPAPER policy<{'arm64': 'm'}> +CONFIG_TINYDRM_SHARP_MEMORY policy<{'arm64': 'm'}> +CONFIG_TIPC policy<{'arm64': 'm'}> +CONFIG_TIPC_CRYPTO policy<{'arm64': 'y'}> +CONFIG_TIPC_DIAG policy<{'arm64': 'm'}> +CONFIG_TIPC_MEDIA_IB policy<{'arm64': 'y'}> +CONFIG_TIPC_MEDIA_UDP policy<{'arm64': 'y'}> +CONFIG_TI_ADC081C policy<{'arm64': 'm'}> +CONFIG_TI_ADC0832 policy<{'arm64': 'm'}> +CONFIG_TI_ADC084S021 policy<{'arm64': 'm'}> +CONFIG_TI_ADC108S102 policy<{'arm64': 'm'}> +CONFIG_TI_ADC12138 policy<{'arm64': 'm'}> +CONFIG_TI_ADC128S052 policy<{'arm64': 'm'}> +CONFIG_TI_ADC161S626 policy<{'arm64': 'm'}> +CONFIG_TI_ADS1015 policy<{'arm64': 'm'}> +CONFIG_TI_ADS1018 policy<{'arm64': 'n'}> +CONFIG_TI_ADS1100 policy<{'arm64': 'm'}> +CONFIG_TI_ADS1119 policy<{'arm64': 'm'}> +CONFIG_TI_ADS124S08 policy<{'arm64': 'm'}> +CONFIG_TI_ADS1298 policy<{'arm64': 'm'}> +CONFIG_TI_ADS131E08 policy<{'arm64': 'm'}> +CONFIG_TI_ADS131M02 policy<{'arm64': 'n'}> +CONFIG_TI_ADS7138 policy<{'arm64': 'n'}> +CONFIG_TI_ADS7924 policy<{'arm64': 'm'}> +CONFIG_TI_ADS7950 policy<{'arm64': 'm'}> +CONFIG_TI_ADS8344 policy<{'arm64': 'm'}> +CONFIG_TI_ADS8688 policy<{'arm64': 'm'}> +CONFIG_TI_AM335X_ADC policy<{'arm64': 'm'}> +CONFIG_TI_AM65_CPSW_QOS policy<{'arm64': 'y'}> +CONFIG_TI_CPSW_PHY_SEL policy<{'arm64': 'n'}> +CONFIG_TI_DAC082S085 policy<{'arm64': 'm'}> +CONFIG_TI_DAC5571 policy<{'arm64': 'm'}> +CONFIG_TI_DAC7311 policy<{'arm64': 'm'}> +CONFIG_TI_DAC7612 policy<{'arm64': 'm'}> +CONFIG_TI_DAVINCI_MDIO policy<{'arm64': 'y'}> +CONFIG_TI_ECAP_CAPTURE policy<{'arm64': 'm'}> +CONFIG_TI_EQEP policy<{'arm64': 'm'}> +CONFIG_TI_FPC202 policy<{'arm64': 'n'}> +CONFIG_TI_ICSSG_PRUETH policy<{'arm64': 'm'}> +CONFIG_TI_ICSSG_PRUETH_SR1 policy<{'arm64': 'm'}> +CONFIG_TI_ICSS_IEP policy<{'arm64': 'm'}> +CONFIG_TI_K3_AM65_CPSW_NUSS policy<{'arm64': 'm'}> +CONFIG_TI_K3_AM65_CPSW_SWITCHDEV policy<{'arm64': 'y'}> +CONFIG_TI_K3_AM65_CPTS policy<{'arm64': 'm'}> +CONFIG_TI_K3_CPPI_DESC_POOL policy<{'arm64': 'm'}> +CONFIG_TI_K3_DSP_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_TI_K3_M4_REMOTEPROC policy<{'arm64': 'n'}> +CONFIG_TI_K3_PSIL policy<{'arm64': 'y'}> +CONFIG_TI_K3_R5_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_TI_K3_RINGACC policy<{'arm64': 'y'}> +CONFIG_TI_K3_SOCINFO policy<{'arm64': 'y'}> +CONFIG_TI_K3_UDMA policy<{'arm64': 'y'}> +CONFIG_TI_K3_UDMA_GLUE_LAYER policy<{'arm64': 'y'}> +CONFIG_TI_LMP92064 policy<{'arm64': 'm'}> +CONFIG_TI_MESSAGE_MANAGER policy<{'arm64': 'y'}> +CONFIG_TI_PRUETH policy<{'arm64': 'n'}> +CONFIG_TI_PRUSS policy<{'arm64': 'm'}> +CONFIG_TI_PRUSS_INTC policy<{'arm64': 'm'}> +CONFIG_TI_SCI_CLK policy<{'arm64': 'm'}> +CONFIG_TI_SCI_CLK_PROBE_FROM_FW policy<{'arm64': 'n'}> +CONFIG_TI_SCI_INTA_IRQCHIP policy<{'arm64': 'y'}> +CONFIG_TI_SCI_INTA_MSI_DOMAIN policy<{'arm64': 'y'}> +CONFIG_TI_SCI_INTR_IRQCHIP policy<{'arm64': 'y'}> +CONFIG_TI_SCI_PM_DOMAINS policy<{'arm64': 'm'}> +CONFIG_TI_SCI_PROTOCOL policy<{'arm64': 'y'}> +CONFIG_TI_SYSC policy<{'arm64': 'y'}> +CONFIG_TI_SYSCON_CLK policy<{'arm64': 'y'}> +CONFIG_TI_TLC4541 policy<{'arm64': 'm'}> +CONFIG_TI_TMAG5273 policy<{'arm64': 'm'}> +CONFIG_TI_TSC2046 policy<{'arm64': 'm'}> +CONFIG_TLAN policy<{'arm64': 'm'}> +CONFIG_TLS policy<{'arm64': 'm'}> +CONFIG_TLS_DEVICE policy<{'arm64': 'y'}> +CONFIG_TMP006 policy<{'arm64': 'm'}> +CONFIG_TMP007 policy<{'arm64': 'm'}> +CONFIG_TMP117 policy<{'arm64': 'm'}> +CONFIG_TMPFS policy<{'arm64': 'y'}> +CONFIG_TMPFS_INODE64 policy<{'arm64': 'y'}> +CONFIG_TMPFS_QUOTA policy<{'arm64': 'y'}> +CONFIG_TMPFS_XATTR policy<{'arm64': 'y'}> +CONFIG_TOOLS_SUPPORT_RELR policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_88PM860X policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_AD7877 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_AD7879 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_AD7879_I2C policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_AD7879_SPI policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ADC policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ADS7846 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_APPLE_Z2 policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_AR1021_I2C policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ATMEL_MXT policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_AUO_PIXCIR policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_BU21013 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_BU21029 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_COLIBRI_VF50 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_CY8CTMA140 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_CY8CTMG110 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_CYTTSP5 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_CYTTSP_CORE policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_CYTTSP_I2C policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_CYTTSP_SPI policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_DA9034 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_DA9052 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_DYNAPRO policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_EDT_FT5X06 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_EETI policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_EGALAX policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_EGALAX_SERIAL policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_EKTF2127 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ELO policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_EXC3000 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_FUJITSU policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_GOODIX policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_CORE policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_GUNZE policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_HAMPSHIRE policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_HIDEEP policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_HIMAX_HX83112B policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_HIMAX_HX852X policy<{'arm64': 'n'}> +CONFIG_TOUCHSCREEN_HYCON_HY46XX policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_HYNITRON_CST816X policy<{'arm64': 'n'}> +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ILI210X policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ILITEK policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_IMAGIS policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_IMX6UL_TSC policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_INEXIO policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_IQS5XX policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_IQS7211 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_MAX11801 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_MC13783 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_MELFAS_MIP4 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_MMS114 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_MSG2638 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_MSHW0485 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_MTOUCH policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_PENMOUNT policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_PIXCIR policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_RM_TS policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ROHM_BU21023 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_S6SY761 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_SILEAD policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_SIS_I2C policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ST1232 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_STMFTS policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_STMPE policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_SUN4I policy<{'arm64': 'n'}> +CONFIG_TOUCHSCREEN_SUR40 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_SURFACE3_SPI policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_SX8654 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_TI_AM335X_TSC policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_TOUCHIT213 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_TOUCHRIGHT policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_TOUCHWIN policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_TPS6507X policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_TSC2004 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_TSC2005 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_TSC2007 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_TSC2007_IIO policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_TSC200X_CORE policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_TSC_SERIO policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_USB_3M policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_COMPOSITE policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_USB_DMC_TSC10 policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_E2I policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_EASYTOUCH policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_EGALAX policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ELO policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ETURBO policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_GOTOP policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_GUNZE policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_IDEALTEK policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_IRTOUCH policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ITM policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_JASTEC policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_NEXIO policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_PANJIT policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ZYTRONIC policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_WACOM_I2C policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_WACOM_W8001 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_WACOM_W9000 policy<{'arm64': 'n'}> +CONFIG_TOUCHSCREEN_WDT87XX_I2C policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_WM831X policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_WM9705 policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_WM9712 policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_WM9713 policy<{'arm64': 'y'}> +CONFIG_TOUCHSCREEN_WM97XX policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ZET6223 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ZFORCE policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_ZINITIX policy<{'arm64': 'm'}> +CONFIG_TPL0102 policy<{'arm64': 'm'}> +CONFIG_TPS6105X policy<{'arm64': 'm'}> +CONFIG_TPS65010 policy<{'arm64': 'm'}> +CONFIG_TPS6507X policy<{'arm64': 'm'}> +CONFIG_TPS6594_ESM policy<{'arm64': 'm'}> +CONFIG_TPS6594_PFSM policy<{'arm64': 'm'}> +CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED policy<{'arm64': 'y'}> +CONFIG_TRACEPOINTS policy<{'arm64': 'y'}> +CONFIG_TRACEPOINT_BENCHMARK policy<{'arm64': 'n'}> +CONFIG_TRACER_MAX_TRACE policy<{'arm64': 'y'}> +CONFIG_TRACER_SNAPSHOT policy<{'arm64': 'y'}> +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP policy<{'arm64': 'n'}> +CONFIG_TRACE_CLOCK policy<{'arm64': 'y'}> +CONFIG_TRACE_EVAL_MAP_FILE policy<{'arm64': 'n'}> +CONFIG_TRACE_EVENT_INJECT policy<{'arm64': 'y'}> +CONFIG_TRACE_GPU_MEM policy<{'arm64': 'y'}> +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT policy<{'arm64': 'y'}> +CONFIG_TRACE_IRQFLAGS_SUPPORT policy<{'arm64': 'y'}> +CONFIG_TRACE_MMIO_ACCESS policy<{'arm64': 'y'}> +CONFIG_TRACE_REMOTE_TEST policy<{'arm64': 'n'}> +CONFIG_TRACE_SYSCALL_BUF_SIZE_DEFAULT policy<{'arm64': '63'}> +CONFIG_TRACING policy<{'arm64': 'y'}> +CONFIG_TRACING_MAP policy<{'arm64': 'y'}> +CONFIG_TRACING_SUPPORT policy<{'arm64': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE policy<{'arm64': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS policy<{'arm64': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE policy<{'arm64': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_NEVER policy<{'arm64': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_ADVISE policy<{'arm64': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_ALWAYS policy<{'arm64': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_NEVER policy<{'arm64': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_WITHIN_SIZE policy<{'arm64': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_ADVISE policy<{'arm64': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_ALWAYS policy<{'arm64': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_NEVER policy<{'arm64': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_WITHIN_SIZE policy<{'arm64': 'n'}> +CONFIG_TRANS_TABLE policy<{'arm64': 'y'}> +CONFIG_TREE_RCU policy<{'arm64': 'y'}> +CONFIG_TREE_SRCU policy<{'arm64': 'y'}> +CONFIG_TRIM_UNUSED_KSYMS policy<{'arm64': 'n'}> +CONFIG_TRUSTED_KEYS policy<{'arm64': 'y'}> +CONFIG_TRUSTED_KEYS_DEBUG policy<{'arm64': 'n'}> +CONFIG_TRUSTED_KEYS_TPM policy<{'arm64': 'y'}> +CONFIG_TSL2583 policy<{'arm64': 'm'}> +CONFIG_TSL2591 policy<{'arm64': 'm'}> +CONFIG_TSL2772 policy<{'arm64': 'm'}> +CONFIG_TSL4531 policy<{'arm64': 'm'}> +CONFIG_TSNEP policy<{'arm64': 'm'}> +CONFIG_TSNEP_SELFTESTS policy<{'arm64': 'n'}> +CONFIG_TSYS01 policy<{'arm64': 'm'}> +CONFIG_TSYS02D policy<{'arm64': 'm'}> +CONFIG_TTPCI_EEPROM policy<{'arm64': 'm'}> +CONFIG_TTY policy<{'arm64': 'y'}> +CONFIG_TTY_PRINTK policy<{'arm64': 'y'}> +CONFIG_TTY_PRINTK_LEVEL policy<{'arm64': '6'}> +CONFIG_TULIP policy<{'arm64': 'm'}> +CONFIG_TULIP_MMIO policy<{'arm64': 'n'}> +CONFIG_TULIP_MWI policy<{'arm64': 'n'}> +CONFIG_TULIP_NAPI policy<{'arm64': 'n'}> +CONFIG_TUN policy<{'arm64': 'y'}> +CONFIG_TUN_VNET_CROSS_LE policy<{'arm64': 'n'}> +CONFIG_TURRIS_MOX_RWTM policy<{'arm64': 'm'}> +CONFIG_TURRIS_MOX_RWTM_KEYCTL policy<{'arm64': 'y'}> +CONFIG_TURRIS_SIGNING_KEY policy<{'arm64': 'm'}> +CONFIG_TWL4030_CORE policy<{'arm64': 'y'}> +CONFIG_TWL4030_MADC policy<{'arm64': 'm'}> +CONFIG_TWL4030_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_TWL6030_GPADC policy<{'arm64': 'm'}> +CONFIG_TWL6040_CORE policy<{'arm64': 'y'}> +CONFIG_TXGBE policy<{'arm64': 'm'}> +CONFIG_TXGBEVF policy<{'arm64': 'n'}> +CONFIG_TYPEC policy<{'arm64': 'y'}> +CONFIG_TYPEC_ANX7411 policy<{'arm64': 'm'}> +CONFIG_TYPEC_DP_ALTMODE policy<{'arm64': 'm'}> +CONFIG_TYPEC_FUSB302 policy<{'arm64': 'm'}> +CONFIG_TYPEC_HD3SS3220 policy<{'arm64': 'm'}> +CONFIG_TYPEC_MT6360 policy<{'arm64': 'm'}> +CONFIG_TYPEC_MUX_FSA4480 policy<{'arm64': 'm'}> +CONFIG_TYPEC_MUX_GPIO_SBU policy<{'arm64': 'm'}> +CONFIG_TYPEC_MUX_IT5205 policy<{'arm64': 'm'}> +CONFIG_TYPEC_MUX_NB7VPQ904M policy<{'arm64': 'm'}> +CONFIG_TYPEC_MUX_PI3USB30532 policy<{'arm64': 'm'}> +CONFIG_TYPEC_MUX_PS883X policy<{'arm64': 'm'}> +CONFIG_TYPEC_MUX_PTN36502 policy<{'arm64': 'm'}> +CONFIG_TYPEC_MUX_TUSB1046 policy<{'arm64': 'm'}> +CONFIG_TYPEC_MUX_WCD939X_USBSS policy<{'arm64': 'm'}> +CONFIG_TYPEC_NVIDIA_ALTMODE policy<{'arm64': 'm'}> +CONFIG_TYPEC_QCOM_PMIC policy<{'arm64': 'm'}> +CONFIG_TYPEC_RT1711H policy<{'arm64': 'm'}> +CONFIG_TYPEC_RT1719 policy<{'arm64': 'm'}> +CONFIG_TYPEC_STUSB160X policy<{'arm64': 'm'}> +CONFIG_TYPEC_TBT_ALTMODE policy<{'arm64': 'm'}> +CONFIG_TYPEC_TCPCI policy<{'arm64': 'm'}> +CONFIG_TYPEC_TCPCI_MAXIM policy<{'arm64': 'm'}> +CONFIG_TYPEC_TCPCI_MT6370 policy<{'arm64': 'm'}> +CONFIG_TYPEC_TCPM policy<{'arm64': 'm'}> +CONFIG_TYPEC_TPS6598X policy<{'arm64': 'm'}> +CONFIG_TYPEC_UCSI policy<{'arm64': 'm'}> +CONFIG_TYPEC_WUSB3801 policy<{'arm64': 'm'}> +CONFIG_TYPHOON policy<{'arm64': 'm'}> +CONFIG_UACCE policy<{'arm64': 'm'}> +CONFIG_UBIFS_ATIME_SUPPORT policy<{'arm64': 'n'}> +CONFIG_UBIFS_FS policy<{'arm64': 'm'}> +CONFIG_UBIFS_FS_ADVANCED_COMPR policy<{'arm64': 'n'}> +CONFIG_UBIFS_FS_AUTHENTICATION policy<{'arm64': 'y'}> +CONFIG_UBIFS_FS_LZO policy<{'arm64': 'y'}> +CONFIG_UBIFS_FS_SECURITY policy<{'arm64': 'y'}> +CONFIG_UBIFS_FS_XATTR policy<{'arm64': 'y'}> +CONFIG_UBIFS_FS_ZLIB policy<{'arm64': 'y'}> +CONFIG_UBIFS_FS_ZSTD policy<{'arm64': 'y'}> +CONFIG_UBSAN_ALIGNMENT policy<{'arm64': 'n'}> +CONFIG_UBSAN_BOOL policy<{'arm64': 'y'}> +CONFIG_UBSAN_BOUNDS policy<{'arm64': 'y'}> +CONFIG_UBSAN_BOUNDS_STRICT policy<{'arm64': 'y'}> +CONFIG_UBSAN_DIV_ZERO policy<{'arm64': 'n'}> +CONFIG_UBSAN_ENUM policy<{'arm64': 'y'}> +CONFIG_UBSAN_KVM_EL2 policy<{'arm64': 'n'}> +CONFIG_UBSAN_SHIFT policy<{'arm64': 'y'}> +CONFIG_UBSAN_TRAP policy<{'arm64': 'n'}> +CONFIG_UBSAN_UNREACHABLE policy<{'arm64': 'n'}> +CONFIG_UBUNTU_HOST policy<{'arm64': 'n'}> +CONFIG_UBUNTU_ODM_DRIVERS policy<{'arm64': 'n'}> +CONFIG_UCC policy<{'arm64': 'y'}> +CONFIG_UCC_FAST policy<{'arm64': 'y'}> +CONFIG_UCC_SLOW policy<{'arm64': 'y'}> +CONFIG_UCLAMP_BUCKETS_COUNT policy<{'arm64': '5'}> +CONFIG_UCLAMP_TASK policy<{'arm64': 'y'}> +CONFIG_UCLAMP_TASK_GROUP policy<{'arm64': 'y'}> +CONFIG_UCS2_STRING policy<{'arm64': 'y'}> +CONFIG_UCSI_ACPI policy<{'arm64': 'm'}> +CONFIG_UCSI_CCG policy<{'arm64': 'm'}> +CONFIG_UCSI_HUAWEI_GAOKUN policy<{'arm64': 'n'}> +CONFIG_UCSI_LENOVO_YOGA_C630 policy<{'arm64': 'm'}> +CONFIG_UCSI_PMIC_GLINK policy<{'arm64': 'm'}> +CONFIG_UCSI_STM32G0 policy<{'arm64': 'm'}> +CONFIG_UDF_FS policy<{'arm64': 'm'}> +CONFIG_UDMABUF policy<{'arm64': 'y'}> +CONFIG_UEFI_CPER policy<{'arm64': 'y'}> +CONFIG_UEFI_CPER_ARM policy<{'arm64': 'y'}> +CONFIG_UEVENT_HELPER policy<{'arm64': 'y'}> +CONFIG_UEVENT_HELPER_PATH policy<{'arm64': '""'}> +CONFIG_UFS_DEBUG policy<{'arm64': 'n'}> +CONFIG_UFS_FS policy<{'arm64': 'm'}> +CONFIG_UFS_FS_WRITE policy<{'arm64': 'n'}> +CONFIG_UHID policy<{'arm64': 'm'}> +CONFIG_UID16 policy<{'arm64': 'y'}> +CONFIG_UIO policy<{'arm64': 'm'}> +CONFIG_UIO_AEC policy<{'arm64': 'm'}> +CONFIG_UIO_CIF policy<{'arm64': 'm'}> +CONFIG_UIO_DFL policy<{'arm64': 'm'}> +CONFIG_UIO_DMEM_GENIRQ policy<{'arm64': 'm'}> +CONFIG_UIO_MF624 policy<{'arm64': 'm'}> +CONFIG_UIO_NETX policy<{'arm64': 'm'}> +CONFIG_UIO_PCI_GENERIC policy<{'arm64': 'm'}> +CONFIG_UIO_PCI_GENERIC_SVA policy<{'arm64': 'n'}> +CONFIG_UIO_PDRV_GENIRQ policy<{'arm64': 'm'}> +CONFIG_UIO_SERCOS3 policy<{'arm64': 'm'}> +CONFIG_ULI526X policy<{'arm64': 'm'}> +CONFIG_ULTRIX_PARTITION policy<{'arm64': 'y'}> +CONFIG_UNICODE policy<{'arm64': 'y'}> +CONFIG_UNINLINE_SPIN_UNLOCK policy<{'arm64': 'y'}> +CONFIG_UNION_FIND policy<{'arm64': 'y'}> +CONFIG_UNIX policy<{'arm64': 'y'}> +CONFIG_UNIX98_PTYS policy<{'arm64': 'y'}> +CONFIG_UNIXWARE_DISKLABEL policy<{'arm64': 'y'}> +CONFIG_UNIX_DIAG policy<{'arm64': 'm'}> +CONFIG_UNMAP_KERNEL_AT_EL0 policy<{'arm64': 'y'}> +CONFIG_UPROBES policy<{'arm64': 'y'}> +CONFIG_UPROBE_EVENTS policy<{'arm64': 'y'}> +CONFIG_US5182D policy<{'arm64': 'm'}> +CONFIG_USB policy<{'arm64': 'y'}> +CONFIG_USB4 policy<{'arm64': 'm'}> +CONFIG_USB4_CONFIGFS policy<{'arm64': 'm'}> +CONFIG_USB4_DEBUGFS_WRITE policy<{'arm64': 'n'}> +CONFIG_USB4_DMA_TEST policy<{'arm64': 'n'}> +CONFIG_USB4_NET policy<{'arm64': 'm'}> +CONFIG_USB4_STREAM policy<{'arm64': 'n'}> +CONFIG_USBIP_CORE policy<{'arm64': 'm'}> +CONFIG_USBIP_DEBUG policy<{'arm64': 'n'}> +CONFIG_USBIP_HOST policy<{'arm64': 'm'}> +CONFIG_USBIP_VHCI_HCD policy<{'arm64': 'm'}> +CONFIG_USBIP_VHCI_HC_PORTS policy<{'arm64': '8'}> +CONFIG_USBIP_VHCI_NR_HCS policy<{'arm64': '1'}> +CONFIG_USBIP_VUDC policy<{'arm64': 'm'}> +CONFIG_USBPCWATCHDOG policy<{'arm64': 'm'}> +CONFIG_USB_ACM policy<{'arm64': 'm'}> +CONFIG_USB_ADUTUX policy<{'arm64': 'm'}> +CONFIG_USB_AIRSPY policy<{'arm64': 'm'}> +CONFIG_USB_ALI_M5632 policy<{'arm64': 'y'}> +CONFIG_USB_AMD5536UDC policy<{'arm64': 'm'}> +CONFIG_USB_AN2720 policy<{'arm64': 'y'}> +CONFIG_USB_ANNOUNCE_NEW_DEVICES policy<{'arm64': 'y'}> +CONFIG_USB_APPLEDISPLAY policy<{'arm64': 'm'}> +CONFIG_USB_ARCH_HAS_HCD policy<{'arm64': 'y'}> +CONFIG_USB_ARMLINUX policy<{'arm64': 'y'}> +CONFIG_USB_ATM policy<{'arm64': 'm'}> +CONFIG_USB_AUDIO policy<{'arm64': 'm'}> +CONFIG_USB_AUTOSUSPEND_DELAY policy<{'arm64': '2'}> +CONFIG_USB_BDC_UDC policy<{'arm64': 'm'}> +CONFIG_USB_BELKIN policy<{'arm64': 'y'}> +CONFIG_USB_C67X00_HCD policy<{'arm64': 'm'}> +CONFIG_USB_CATC policy<{'arm64': 'm'}> +CONFIG_USB_CDC_COMPOSITE policy<{'arm64': 'm'}> +CONFIG_USB_CDC_PHONET policy<{'arm64': 'm'}> +CONFIG_USB_CDNS2_UDC policy<{'arm64': 'm'}> +CONFIG_USB_CDNS3 policy<{'arm64': 'm'}> +CONFIG_USB_CDNS3_GADGET policy<{'arm64': 'y'}> +CONFIG_USB_CDNS3_HOST policy<{'arm64': 'y'}> +CONFIG_USB_CDNS3_IMX policy<{'arm64': 'm'}> +CONFIG_USB_CDNS3_PCI_WRAP policy<{'arm64': 'm'}> +CONFIG_USB_CDNS3_TI policy<{'arm64': 'm'}> +CONFIG_USB_CDNSP_PCI policy<{'arm64': 'm'}> +CONFIG_USB_CDNS_SUPPORT policy<{'arm64': 'm'}> +CONFIG_USB_CHAOSKEY policy<{'arm64': 'm'}> +CONFIG_USB_CHIPIDEA policy<{'arm64': 'm'}> +CONFIG_USB_CHIPIDEA_GENERIC policy<{'arm64': 'm'}> +CONFIG_USB_CHIPIDEA_HOST policy<{'arm64': 'y'}> +CONFIG_USB_CHIPIDEA_IMX policy<{'arm64': 'm'}> +CONFIG_USB_CHIPIDEA_MSM policy<{'arm64': 'm'}> +CONFIG_USB_CHIPIDEA_NPCM policy<{'arm64': 'm'}> +CONFIG_USB_CHIPIDEA_PCI policy<{'arm64': 'm'}> +CONFIG_USB_CHIPIDEA_TEGRA policy<{'arm64': 'm'}> +CONFIG_USB_CHIPIDEA_UDC policy<{'arm64': 'y'}> +CONFIG_USB_COMMON policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS policy<{'arm64': 'm'}> +CONFIG_USB_CONFIGFS_ACM policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_ECM policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_ECM_SUBSET policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_EEM policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_FS policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_HID policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_LB_SS policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_MIDI policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_MIDI2 policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_PRINTER policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_TCM policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_UAC1 policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_UAC2 policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_F_UVC policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_MASS_STORAGE policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_NCM policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_OBEX policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_PHONET policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_RNDIS policy<{'arm64': 'y'}> +CONFIG_USB_CONFIGFS_SERIAL policy<{'arm64': 'y'}> +CONFIG_USB_CONN_GPIO policy<{'arm64': 'm'}> +CONFIG_USB_CXACRU policy<{'arm64': 'm'}> +CONFIG_USB_CYPRESS_CY7C63 policy<{'arm64': 'm'}> +CONFIG_USB_CYTHERM policy<{'arm64': 'm'}> +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE policy<{'arm64': '1'}> +CONFIG_USB_DEFAULT_PERSIST policy<{'arm64': 'y'}> +CONFIG_USB_DSBR policy<{'arm64': 'm'}> +CONFIG_USB_DUMMY_HCD policy<{'arm64': 'n'}> +CONFIG_USB_DWC2 policy<{'arm64': 'y'}> +CONFIG_USB_DWC2_DEBUG policy<{'arm64': 'n'}> +CONFIG_USB_DWC2_DUAL_ROLE policy<{'arm64': 'n'}> +CONFIG_USB_DWC2_HOST policy<{'arm64': 'y'}> +CONFIG_USB_DWC2_PCI policy<{'arm64': 'm'}> +CONFIG_USB_DWC2_PERIPHERAL policy<{'arm64': 'n'}> +CONFIG_USB_DWC2_TRACK_MISSED_SOFS policy<{'arm64': 'n'}> +CONFIG_USB_DWC3 policy<{'arm64': 'y'}> +CONFIG_USB_DWC3_AM62 policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_APPLE policy<{'arm64': 'y'}> +CONFIG_USB_DWC3_DUAL_ROLE policy<{'arm64': 'y'}> +CONFIG_USB_DWC3_GADGET policy<{'arm64': 'n'}> +CONFIG_USB_DWC3_GENERIC_PLAT policy<{'arm64': 'y'}> +CONFIG_USB_DWC3_GOOGLE policy<{'arm64': 'n'}> +CONFIG_USB_DWC3_HAPS policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_HOST policy<{'arm64': 'n'}> +CONFIG_USB_DWC3_IMX policy<{'arm64': 'y'}> +CONFIG_USB_DWC3_IMX8MP policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_KEYSTONE policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_MESON_G12A policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_OF_SIMPLE policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_PCI policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_QCOM policy<{'arm64': 'y'}> +CONFIG_USB_DWC3_RTK policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_ULPI policy<{'arm64': 'n'}> +CONFIG_USB_DWC3_XILINX policy<{'arm64': 'm'}> +CONFIG_USB_DYNAMIC_MINORS policy<{'arm64': 'y'}> +CONFIG_USB_EG20T policy<{'arm64': 'm'}> +CONFIG_USB_EHCI_FSL policy<{'arm64': 'm'}> +CONFIG_USB_EHCI_HCD_NPCM7XX policy<{'arm64': 'm'}> +CONFIG_USB_EHCI_HCD_ORION policy<{'arm64': 'y'}> +CONFIG_USB_EHCI_PCI policy<{'arm64': 'y'}> +CONFIG_USB_EHCI_ROOT_HUB_TT policy<{'arm64': 'y'}> +CONFIG_USB_EHCI_TEGRA policy<{'arm64': 'm'}> +CONFIG_USB_EHCI_TT_NEWSCHED policy<{'arm64': 'y'}> +CONFIG_USB_EHSET_TEST_FIXTURE policy<{'arm64': 'm'}> +CONFIG_USB_EMI26 policy<{'arm64': 'm'}> +CONFIG_USB_EMI62 policy<{'arm64': 'm'}> +CONFIG_USB_EPSON2888 policy<{'arm64': 'y'}> +CONFIG_USB_ETH policy<{'arm64': 'm'}> +CONFIG_USB_ETH_EEM policy<{'arm64': 'y'}> +CONFIG_USB_ETH_RNDIS policy<{'arm64': 'y'}> +CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC policy<{'arm64': 'n'}> +CONFIG_USB_EZUSB_FX2 policy<{'arm64': 'm'}> +CONFIG_USB_FEW_INIT_RETRIES policy<{'arm64': 'n'}> +CONFIG_USB_FUNCTIONFS policy<{'arm64': 'm'}> +CONFIG_USB_FUNCTIONFS_ETH policy<{'arm64': 'y'}> +CONFIG_USB_FUNCTIONFS_GENERIC policy<{'arm64': 'y'}> +CONFIG_USB_FUNCTIONFS_RNDIS policy<{'arm64': 'y'}> +CONFIG_USB_F_ACM policy<{'arm64': 'm'}> +CONFIG_USB_F_ECM policy<{'arm64': 'm'}> +CONFIG_USB_F_EEM policy<{'arm64': 'm'}> +CONFIG_USB_F_FS policy<{'arm64': 'm'}> +CONFIG_USB_F_HID policy<{'arm64': 'm'}> +CONFIG_USB_F_MASS_STORAGE policy<{'arm64': 'm'}> +CONFIG_USB_F_MIDI policy<{'arm64': 'm'}> +CONFIG_USB_F_MIDI2 policy<{'arm64': 'm'}> +CONFIG_USB_F_NCM policy<{'arm64': 'm'}> +CONFIG_USB_F_OBEX policy<{'arm64': 'm'}> +CONFIG_USB_F_PHONET policy<{'arm64': 'm'}> +CONFIG_USB_F_PRINTER policy<{'arm64': 'm'}> +CONFIG_USB_F_RNDIS policy<{'arm64': 'm'}> +CONFIG_USB_F_SERIAL policy<{'arm64': 'm'}> +CONFIG_USB_F_SS_LB policy<{'arm64': 'm'}> +CONFIG_USB_F_SUBSET policy<{'arm64': 'm'}> +CONFIG_USB_F_TCM policy<{'arm64': 'm'}> +CONFIG_USB_F_UAC1 policy<{'arm64': 'm'}> +CONFIG_USB_F_UAC1_LEGACY policy<{'arm64': 'm'}> +CONFIG_USB_F_UAC2 policy<{'arm64': 'm'}> +CONFIG_USB_F_UVC policy<{'arm64': 'm'}> +CONFIG_USB_GADGET policy<{'arm64': 'y'}> +CONFIG_USB_GADGETFS policy<{'arm64': 'm'}> +CONFIG_USB_GADGET_DEBUG policy<{'arm64': 'n'}> +CONFIG_USB_GADGET_DEBUG_FILES policy<{'arm64': 'n'}> +CONFIG_USB_GADGET_DEBUG_FS policy<{'arm64': 'n'}> +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS policy<{'arm64': '2'}> +CONFIG_USB_GADGET_TARGET policy<{'arm64': 'm'}> +CONFIG_USB_GADGET_VBUS_DRAW policy<{'arm64': '2'}> +CONFIG_USB_GADGET_XILINX policy<{'arm64': 'm'}> +CONFIG_USB_GL860 policy<{'arm64': 'm'}> +CONFIG_USB_GOKU policy<{'arm64': 'm'}> +CONFIG_USB_GPIO_VBUS policy<{'arm64': 'm'}> +CONFIG_USB_GR_UDC policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_BENQ policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_CONEX policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_CPIA1 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_DTCS033 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_ETOMS policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_FINEPIX policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_JEILINJ policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_JL2005BCD policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_KINECT policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_KONICA policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_MARS policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_MR97310A policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_NW80X policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_OV519 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_OV534 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_OV534_9 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_PAC207 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_PAC7302 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_PAC7311 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SE401 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SN9C2028 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SN9C20X policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SONIXB policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SONIXJ policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SPCA1528 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SPCA500 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SPCA501 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SPCA505 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SPCA506 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SPCA508 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SPCA561 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SQ905 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SQ905C policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SQ930X policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_STK014 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_STK1135 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_STV0680 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_SUNPLUS policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_T613 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_TOPRO policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_TOUPTEK policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_TV8532 policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_VC032X policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_VICAM policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_XIRLINK_CIT policy<{'arm64': 'm'}> +CONFIG_USB_GSPCA_ZC3XX policy<{'arm64': 'm'}> +CONFIG_USB_G_ACM_MS policy<{'arm64': 'm'}> +CONFIG_USB_G_DBGP policy<{'arm64': 'm'}> +CONFIG_USB_G_DBGP_PRINTK policy<{'arm64': 'n'}> +CONFIG_USB_G_DBGP_SERIAL policy<{'arm64': 'y'}> +CONFIG_USB_G_HID policy<{'arm64': 'm'}> +CONFIG_USB_G_MULTI policy<{'arm64': 'n'}> +CONFIG_USB_G_NCM policy<{'arm64': 'm'}> +CONFIG_USB_G_NOKIA policy<{'arm64': 'm'}> +CONFIG_USB_G_PRINTER policy<{'arm64': 'm'}> +CONFIG_USB_G_SERIAL policy<{'arm64': 'm'}> +CONFIG_USB_G_WEBCAM policy<{'arm64': 'm'}> +CONFIG_USB_HACKRF policy<{'arm64': 'm'}> +CONFIG_USB_HCD_BCMA policy<{'arm64': 'm'}> +CONFIG_USB_HCD_SSB policy<{'arm64': 'm'}> +CONFIG_USB_HCD_TEST_MODE policy<{'arm64': 'n'}> +CONFIG_USB_HID policy<{'arm64': 'm'}> +CONFIG_USB_HIDDEV policy<{'arm64': 'y'}> +CONFIG_USB_HSIC_USB3503 policy<{'arm64': 'm'}> +CONFIG_USB_HSIC_USB4604 policy<{'arm64': 'm'}> +CONFIG_USB_HSO policy<{'arm64': 'm'}> +CONFIG_USB_HUB_USB251XB policy<{'arm64': 'm'}> +CONFIG_USB_IDMOUSE policy<{'arm64': 'm'}> +CONFIG_USB_IOWARRIOR policy<{'arm64': 'm'}> +CONFIG_USB_IPHETH policy<{'arm64': 'm'}> +CONFIG_USB_ISIGHTFW policy<{'arm64': 'm'}> +CONFIG_USB_ISP116X_HCD policy<{'arm64': 'm'}> +CONFIG_USB_ISP1301 policy<{'arm64': 'm'}> +CONFIG_USB_ISP1760 policy<{'arm64': 'm'}> +CONFIG_USB_ISP1760_DUAL_ROLE policy<{'arm64': 'y'}> +CONFIG_USB_ISP1760_GADGET_ROLE policy<{'arm64': 'n'}> +CONFIG_USB_ISP1760_HCD policy<{'arm64': 'y'}> +CONFIG_USB_ISP1760_HOST_ROLE policy<{'arm64': 'n'}> +CONFIG_USB_ISP1761_UDC policy<{'arm64': 'y'}> +CONFIG_USB_KAWETH policy<{'arm64': 'm'}> +CONFIG_USB_KBD policy<{'arm64': 'm'}> +CONFIG_USB_KC2190 policy<{'arm64': 'y'}> +CONFIG_USB_KEENE policy<{'arm64': 'm'}> +CONFIG_USB_LAN78XX policy<{'arm64': 'm'}> +CONFIG_USB_LCD policy<{'arm64': 'm'}> +CONFIG_USB_LD policy<{'arm64': 'm'}> +CONFIG_USB_LEDS_TRIGGER_USBPORT policy<{'arm64': 'm'}> +CONFIG_USB_LED_TRIG policy<{'arm64': 'y'}> +CONFIG_USB_LEGOTOWER policy<{'arm64': 'm'}> +CONFIG_USB_LIBCOMPOSITE policy<{'arm64': 'm'}> +CONFIG_USB_LINK_LAYER_TEST policy<{'arm64': 'm'}> +CONFIG_USB_LJCA policy<{'arm64': 'm'}> +CONFIG_USB_M5602 policy<{'arm64': 'm'}> +CONFIG_USB_M66592 policy<{'arm64': 'n'}> +CONFIG_USB_MA901 policy<{'arm64': 'm'}> +CONFIG_USB_MASS_STORAGE policy<{'arm64': 'm'}> +CONFIG_USB_MAX3420_UDC policy<{'arm64': 'm'}> +CONFIG_USB_MAX3421_HCD policy<{'arm64': 'm'}> +CONFIG_USB_MDC800 policy<{'arm64': 'm'}> +CONFIG_USB_MICROTEK policy<{'arm64': 'm'}> +CONFIG_USB_MIDI_GADGET policy<{'arm64': 'm'}> +CONFIG_USB_MON policy<{'arm64': 'm'}> +CONFIG_USB_MOUSE policy<{'arm64': 'm'}> +CONFIG_USB_MR800 policy<{'arm64': 'm'}> +CONFIG_USB_MSI2500 policy<{'arm64': 'm'}> +CONFIG_USB_MTU3 policy<{'arm64': 'm'}> +CONFIG_USB_MTU3_DEBUG policy<{'arm64': 'n'}> +CONFIG_USB_MTU3_DUAL_ROLE policy<{'arm64': 'y'}> +CONFIG_USB_MTU3_GADGET policy<{'arm64': 'n'}> +CONFIG_USB_MTU3_HOST policy<{'arm64': 'n'}> +CONFIG_USB_MUSB_DUAL_ROLE policy<{'arm64': 'y'}> +CONFIG_USB_MUSB_GADGET policy<{'arm64': 'n'}> +CONFIG_USB_MUSB_HOST policy<{'arm64': 'n'}> +CONFIG_USB_MUSB_MEDIATEK policy<{'arm64': 'm'}> +CONFIG_USB_MUSB_SUNXI policy<{'arm64': 'm'}> +CONFIG_USB_MXS_PHY policy<{'arm64': 'y'}> +CONFIG_USB_NET2280 policy<{'arm64': 'm'}> +CONFIG_USB_NET_AQC111 policy<{'arm64': 'm'}> +CONFIG_USB_NET_AX88179_178A policy<{'arm64': 'm'}> +CONFIG_USB_NET_AX8817X policy<{'arm64': 'm'}> +CONFIG_USB_NET_CDCETHER policy<{'arm64': 'm'}> +CONFIG_USB_NET_CDC_EEM policy<{'arm64': 'm'}> +CONFIG_USB_NET_CDC_MBIM policy<{'arm64': 'm'}> +CONFIG_USB_NET_CDC_NCM policy<{'arm64': 'm'}> +CONFIG_USB_NET_CDC_SUBSET policy<{'arm64': 'm'}> +CONFIG_USB_NET_CDC_SUBSET_ENABLE policy<{'arm64': 'm'}> +CONFIG_USB_NET_CH9200 policy<{'arm64': 'm'}> +CONFIG_USB_NET_CX82310_ETH policy<{'arm64': 'm'}> +CONFIG_USB_NET_DM9601 policy<{'arm64': 'm'}> +CONFIG_USB_NET_DRIVERS policy<{'arm64': 'm'}> +CONFIG_USB_NET_GL620A policy<{'arm64': 'm'}> +CONFIG_USB_NET_HUAWEI_CDC_NCM policy<{'arm64': 'm'}> +CONFIG_USB_NET_INT51X1 policy<{'arm64': 'm'}> +CONFIG_USB_NET_KALMIA policy<{'arm64': 'm'}> +CONFIG_USB_NET_MCS7830 policy<{'arm64': 'm'}> +CONFIG_USB_NET_NET1080 policy<{'arm64': 'm'}> +CONFIG_USB_NET_PLUSB policy<{'arm64': 'm'}> +CONFIG_USB_NET_QMI_WWAN policy<{'arm64': 'm'}> +CONFIG_USB_NET_RNDIS_HOST policy<{'arm64': 'm'}> +CONFIG_USB_NET_SMSC75XX policy<{'arm64': 'm'}> +CONFIG_USB_NET_SMSC95XX policy<{'arm64': 'm'}> +CONFIG_USB_NET_SR9700 policy<{'arm64': 'm'}> +CONFIG_USB_NET_SR9800 policy<{'arm64': 'm'}> +CONFIG_USB_NET_ZAURUS policy<{'arm64': 'm'}> +CONFIG_USB_OHCI_HCD policy<{'arm64': 'y'}> +CONFIG_USB_OHCI_HCD_PCI policy<{'arm64': 'y'}> +CONFIG_USB_OHCI_HCD_PLATFORM policy<{'arm64': 'm'}> +CONFIG_USB_OHCI_LITTLE_ENDIAN policy<{'arm64': 'y'}> +CONFIG_USB_ONBOARD_DEV policy<{'arm64': 'm'}> +CONFIG_USB_ONBOARD_DEV_USB5744 policy<{'arm64': 'n'}> +CONFIG_USB_OTG policy<{'arm64': 'n'}> +CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB policy<{'arm64': 'n'}> +CONFIG_USB_OTG_PRODUCTLIST policy<{'arm64': 'n'}> +CONFIG_USB_OXU210HP_HCD policy<{'arm64': 'm'}> +CONFIG_USB_PCI policy<{'arm64': 'y'}> +CONFIG_USB_PCI_AMD policy<{'arm64': 'y'}> +CONFIG_USB_PEGASUS policy<{'arm64': 'm'}> +CONFIG_USB_PHY policy<{'arm64': 'y'}> +CONFIG_USB_PRINTER policy<{'arm64': 'm'}> +CONFIG_USB_PULSE8_CEC policy<{'arm64': 'm'}> +CONFIG_USB_PWC policy<{'arm64': 'm'}> +CONFIG_USB_PWC_DEBUG policy<{'arm64': 'n'}> +CONFIG_USB_PWC_INPUT_EVDEV policy<{'arm64': 'y'}> +CONFIG_USB_PXA27X policy<{'arm64': 'm'}> +CONFIG_USB_QCOM_EUD policy<{'arm64': 'm'}> +CONFIG_USB_R8A66597 policy<{'arm64': 'm'}> +CONFIG_USB_R8A66597_HCD policy<{'arm64': 'm'}> +CONFIG_USB_RAINSHADOW_CEC policy<{'arm64': 'm'}> +CONFIG_USB_RAREMONO policy<{'arm64': 'm'}> +CONFIG_USB_RAW_GADGET policy<{'arm64': 'm'}> +CONFIG_USB_RENESAS_USB3 policy<{'arm64': 'm'}> +CONFIG_USB_RENESAS_USBF policy<{'arm64': 'm'}> +CONFIG_USB_RENESAS_USBHS policy<{'arm64': 'm'}> +CONFIG_USB_RENESAS_USBHS_HCD policy<{'arm64': 'm'}> +CONFIG_USB_RENESAS_USBHS_UDC policy<{'arm64': 'm'}> +CONFIG_USB_ROLE_SWITCH policy<{'arm64': 'y'}> +CONFIG_USB_RTL8150 policy<{'arm64': 'm'}> +CONFIG_USB_RTL8152 policy<{'arm64': 'm'}> +CONFIG_USB_RTL8153_ECM policy<{'arm64': 'm'}> +CONFIG_USB_RZV2M_USB3DRD policy<{'arm64': 'm'}> +CONFIG_USB_S2255 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_AIRCABLE policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_ARK3116 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_BELKIN policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_CH341 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_CP210X policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_CYBERJACK policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_CYPRESS_M8 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_DIGI_ACCELEPORT policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_EDGEPORT policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_EDGEPORT_TI policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_EMPEG policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_F81232 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_F8153X policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_FTDI_SIO policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_GARMIN policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_GENERIC policy<{'arm64': 'y'}> +CONFIG_USB_SERIAL_IPAQ policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_IPW policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_IR policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_IUU policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_KEYSPAN policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_KEYSPAN_PDA policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_KLSI policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_KOBIL_SCT policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_MCT_U232 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_METRO policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_MOS7715_PARPORT policy<{'arm64': 'y'}> +CONFIG_USB_SERIAL_MOS7720 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_MOS7840 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_MXUPORT policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_NAVMAN policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_OMNINET policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_OPTICON policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_OPTION policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_OTI6858 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_PL2303 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_QCAUX policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_QT2 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_QUALCOMM policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_SAFE policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_SAFE_PADDED policy<{'arm64': 'n'}> +CONFIG_USB_SERIAL_SIERRAWIRELESS policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_SIMPLE policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_SPCP8X5 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_SSU100 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_SYMBOL policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_TI policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_UPD78F0730 policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_VISOR policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_WHITEHEAT policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_WISHBONE policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_WWAN policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_XR policy<{'arm64': 'm'}> +CONFIG_USB_SERIAL_XSENS_MT policy<{'arm64': 'm'}> +CONFIG_USB_SEVSEG policy<{'arm64': 'm'}> +CONFIG_USB_SI470X policy<{'arm64': 'm'}> +CONFIG_USB_SI4713 policy<{'arm64': 'm'}> +CONFIG_USB_SIERRA_NET policy<{'arm64': 'm'}> +CONFIG_USB_SISUSBVGA policy<{'arm64': 'm'}> +CONFIG_USB_SL811_CS policy<{'arm64': 'n'}> +CONFIG_USB_SL811_HCD policy<{'arm64': 'm'}> +CONFIG_USB_SL811_HCD_ISO policy<{'arm64': 'y'}> +CONFIG_USB_SNP_CORE policy<{'arm64': 'm'}> +CONFIG_USB_SNP_UDC_PLAT policy<{'arm64': 'm'}> +CONFIG_USB_SPEEDTOUCH policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_ALAUDA policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_CYPRESS_ATACB policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_DATAFAB policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_DEBUG policy<{'arm64': 'n'}> +CONFIG_USB_STORAGE_ENE_UB6250 policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_FREECOM policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_ISD200 policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_JUMPSHOT policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_KARMA policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_ONETOUCH policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_REALTEK policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_SDDR09 policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_SDDR55 policy<{'arm64': 'm'}> +CONFIG_USB_STORAGE_USBAT policy<{'arm64': 'm'}> +CONFIG_USB_STV06XX policy<{'arm64': 'm'}> +CONFIG_USB_SUPPORT policy<{'arm64': 'y'}> +CONFIG_USB_TEGRA_PHY policy<{'arm64': 'm'}> +CONFIG_USB_TEGRA_XUDC policy<{'arm64': 'm'}> +CONFIG_USB_TEST policy<{'arm64': 'm'}> +CONFIG_USB_TMC policy<{'arm64': 'm'}> +CONFIG_USB_TRANCEVIBRATOR policy<{'arm64': 'm'}> +CONFIG_USB_UAS policy<{'arm64': 'm'}> +CONFIG_USB_UEAGLEATM policy<{'arm64': 'm'}> +CONFIG_USB_ULPI policy<{'arm64': 'y'}> +CONFIG_USB_ULPI_BUS policy<{'arm64': 'y'}> +CONFIG_USB_ULPI_VIEWPORT policy<{'arm64': 'y'}> +CONFIG_USB_USBNET policy<{'arm64': 'm'}> +CONFIG_USB_USS720 policy<{'arm64': 'm'}> +CONFIG_USB_U_AUDIO policy<{'arm64': 'm'}> +CONFIG_USB_U_ETHER policy<{'arm64': 'm'}> +CONFIG_USB_U_SERIAL policy<{'arm64': 'm'}> +CONFIG_USB_VIDEO_CLASS policy<{'arm64': 'm'}> +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV policy<{'arm64': 'y'}> +CONFIG_USB_VL600 policy<{'arm64': 'm'}> +CONFIG_USB_WDM policy<{'arm64': 'm'}> +CONFIG_USB_XEN_HCD policy<{'arm64': 'm'}> +CONFIG_USB_XHCI_HISTB policy<{'arm64': 'm'}> +CONFIG_USB_XHCI_MTK policy<{'arm64': 'm'}> +CONFIG_USB_XHCI_MVEBU policy<{'arm64': 'm'}> +CONFIG_USB_XHCI_PCI policy<{'arm64': 'y'}> +CONFIG_USB_XHCI_PCI_RENESAS policy<{'arm64': 'm'}> +CONFIG_USB_XHCI_PLATFORM policy<{'arm64': 'y'}> +CONFIG_USB_XHCI_RCAR policy<{'arm64': 'm'}> +CONFIG_USB_XHCI_RZV2M policy<{'arm64': 'y'}> +CONFIG_USB_XHCI_SIDEBAND policy<{'arm64': 'n'}> +CONFIG_USB_XHCI_TEGRA policy<{'arm64': 'm'}> +CONFIG_USB_XUSBATM policy<{'arm64': 'm'}> +CONFIG_USB_YUREX policy<{'arm64': 'm'}> +CONFIG_USB_ZERO policy<{'arm64': 'm'}> +CONFIG_USERFAULTFD policy<{'arm64': 'y'}> +CONFIG_USERIO policy<{'arm64': 'm'}> +CONFIG_USER_DECRYPTED_DATA policy<{'arm64': 'y'}> +CONFIG_USER_EVENTS policy<{'arm64': 'y'}> +CONFIG_USER_NS policy<{'arm64': 'y'}> +CONFIG_USER_STACKTRACE_SUPPORT policy<{'arm64': 'y'}> +CONFIG_USE_PERCPU_NUMA_NODE_ID policy<{'arm64': 'y'}> +CONFIG_UTS_NS policy<{'arm64': 'y'}> +CONFIG_UVC_COMMON policy<{'arm64': 'm'}> +CONFIG_U_SERIAL_CONSOLE policy<{'arm64': 'y'}> +CONFIG_V4L2_ASYNC policy<{'arm64': 'm'}> +CONFIG_V4L2_CCI policy<{'arm64': 'm'}> +CONFIG_V4L2_CCI_I2C policy<{'arm64': 'm'}> +CONFIG_V4L2_FLASH_LED_CLASS policy<{'arm64': 'm'}> +CONFIG_V4L2_FWNODE policy<{'arm64': 'm'}> +CONFIG_V4L2_H264 policy<{'arm64': 'm'}> +CONFIG_V4L2_ISP policy<{'arm64': 'm'}> +CONFIG_V4L2_JPEG_HELPER policy<{'arm64': 'm'}> +CONFIG_V4L2_MEM2MEM_DEV policy<{'arm64': 'm'}> +CONFIG_V4L2_VP9 policy<{'arm64': 'm'}> +CONFIG_V4L_MEM2MEM_DRIVERS policy<{'arm64': 'y'}> +CONFIG_V4L_PLATFORM_DRIVERS policy<{'arm64': 'y'}> +CONFIG_V4L_TEST_DRIVERS policy<{'arm64': 'y'}> +CONFIG_VALIDATE_FS_PARSER policy<{'arm64': 'y'}> +CONFIG_VBOXGUEST policy<{'arm64': 'n'}> +CONFIG_VCAP policy<{'arm64': 'y'}> +CONFIG_VCNL3020 policy<{'arm64': 'm'}> +CONFIG_VCNL4000 policy<{'arm64': 'm'}> +CONFIG_VCNL4035 policy<{'arm64': 'm'}> +CONFIG_VCPU_STALL_DETECTOR policy<{'arm64': 'm'}> +CONFIG_VDPA policy<{'arm64': 'm'}> +CONFIG_VDPA_SIM policy<{'arm64': 'm'}> +CONFIG_VDPA_SIM_BLOCK policy<{'arm64': 'm'}> +CONFIG_VDPA_SIM_NET policy<{'arm64': 'm'}> +CONFIG_VDPA_USER policy<{'arm64': 'm'}> +CONFIG_VDSO_GETRANDOM policy<{'arm64': 'y'}> +CONFIG_VEML3235 policy<{'arm64': 'm'}> +CONFIG_VEML3328 policy<{'arm64': 'n'}> +CONFIG_VEML6030 policy<{'arm64': 'm'}> +CONFIG_VEML6040 policy<{'arm64': 'm'}> +CONFIG_VEML6046X00 policy<{'arm64': 'm'}> +CONFIG_VEML6070 policy<{'arm64': 'm'}> +CONFIG_VEML6075 policy<{'arm64': 'm'}> +CONFIG_VERSION_SIGNATURE policy<{'arm64': '""'}> +CONFIG_VETH policy<{'arm64': 'm'}> +CONFIG_VEXPRESS_CONFIG policy<{'arm64': 'y'}> +CONFIG_VF610_ADC policy<{'arm64': 'm'}> +CONFIG_VF610_DAC policy<{'arm64': 'm'}> +CONFIG_VFIO_AMBA policy<{'arm64': 'm'}> +CONFIG_VFIO_CDX policy<{'arm64': 'm'}> +CONFIG_VFIO_CONTAINER policy<{'arm64': 'y'}> +CONFIG_VFIO_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_VFIO_DEVICE_CDEV policy<{'arm64': 'y'}> +CONFIG_VFIO_FSL_MC policy<{'arm64': 'm'}> +CONFIG_VFIO_GROUP policy<{'arm64': 'y'}> +CONFIG_VFIO_IOMMU_TYPE1 policy<{'arm64': 'm'}> +CONFIG_VFIO_NOIOMMU policy<{'arm64': 'y'}> +CONFIG_VFIO_PCI_CORE policy<{'arm64': 'm'}> +CONFIG_VFIO_PCI_DMABUF policy<{'arm64': 'y'}> +CONFIG_VFIO_PCI_INTX policy<{'arm64': 'y'}> +CONFIG_VFIO_PLATFORM policy<{'arm64': 'm'}> +CONFIG_VFIO_PLATFORM_AMDXGBE_RESET policy<{'arm64': 'm'}> +CONFIG_VFIO_PLATFORM_BASE policy<{'arm64': 'm'}> +CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET policy<{'arm64': 'm'}> +CONFIG_VFIO_VIRQFD policy<{'arm64': 'y'}> +CONFIG_VF_TIMER_NONE policy<{'arm64': 'y'}> +CONFIG_VF_USE_PIT_TIMER policy<{'arm64': 'n'}> +CONFIG_VGASTATE policy<{'arm64': 'm'}> +CONFIG_VGA_ARB policy<{'arm64': 'y'}> +CONFIG_VGA_ARB_MAX_GPUS policy<{'arm64': '16'}> +CONFIG_VHOST policy<{'arm64': 'm'}> +CONFIG_VHOST_CROSS_ENDIAN_LEGACY policy<{'arm64': 'n'}> +CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL policy<{'arm64': 'y'}> +CONFIG_VHOST_IOTLB policy<{'arm64': 'm'}> +CONFIG_VHOST_MENU policy<{'arm64': 'y'}> +CONFIG_VHOST_NET policy<{'arm64': 'm'}> +CONFIG_VHOST_RING policy<{'arm64': 'm'}> +CONFIG_VHOST_SCSI policy<{'arm64': 'm'}> +CONFIG_VHOST_TASK policy<{'arm64': 'y'}> +CONFIG_VHOST_VDPA policy<{'arm64': 'm'}> +CONFIG_VHOST_VSOCK policy<{'arm64': 'm'}> +CONFIG_VIA_RHINE policy<{'arm64': 'm'}> +CONFIG_VIA_RHINE_MMIO policy<{'arm64': 'y'}> +CONFIG_VIA_VELOCITY policy<{'arm64': 'm'}> +CONFIG_VIDEO policy<{'arm64': 'y'}> +CONFIG_VIDEOBUF2_CORE policy<{'arm64': 'm'}> +CONFIG_VIDEOBUF2_DMA_CONTIG policy<{'arm64': 'm'}> +CONFIG_VIDEOBUF2_DMA_SG policy<{'arm64': 'm'}> +CONFIG_VIDEOBUF2_DVB policy<{'arm64': 'm'}> +CONFIG_VIDEOBUF2_MEMOPS policy<{'arm64': 'm'}> +CONFIG_VIDEOBUF2_V4L2 policy<{'arm64': 'm'}> +CONFIG_VIDEOBUF2_VMALLOC policy<{'arm64': 'm'}> +CONFIG_VIDEOMODE_HELPERS policy<{'arm64': 'y'}> +CONFIG_VIDEO_AD5820 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADP1653 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADV7170 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADV7175 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADV7180 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADV7183 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADV7343 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADV7393 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADV748X policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADV7604 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADV7604_CEC policy<{'arm64': 'y'}> +CONFIG_VIDEO_ADV7842 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ADV7842_CEC policy<{'arm64': 'y'}> +CONFIG_VIDEO_ADV_DEBUG policy<{'arm64': 'n'}> +CONFIG_VIDEO_AK7375 policy<{'arm64': 'm'}> +CONFIG_VIDEO_AK881X policy<{'arm64': 'm'}> +CONFIG_VIDEO_ALLEGRO_DVT policy<{'arm64': 'm'}> +CONFIG_VIDEO_ALVIUM_CSI2 policy<{'arm64': 'm'}> +CONFIG_VIDEO_AMD_ISP4_CAPTURE policy<{'arm64': 'n'}> +CONFIG_VIDEO_AMPHION_VPU policy<{'arm64': 'm'}> +CONFIG_VIDEO_APTINA_PLL policy<{'arm64': 'm'}> +CONFIG_VIDEO_AR0521 policy<{'arm64': 'm'}> +CONFIG_VIDEO_AU0828 policy<{'arm64': 'm'}> +CONFIG_VIDEO_AU0828_RC policy<{'arm64': 'y'}> +CONFIG_VIDEO_AU0828_V4L2 policy<{'arm64': 'y'}> +CONFIG_VIDEO_BT819 policy<{'arm64': 'm'}> +CONFIG_VIDEO_BT848 policy<{'arm64': 'm'}> +CONFIG_VIDEO_BT856 policy<{'arm64': 'm'}> +CONFIG_VIDEO_BT866 policy<{'arm64': 'm'}> +CONFIG_VIDEO_C3_ISP policy<{'arm64': 'n'}> +CONFIG_VIDEO_C3_MIPI_ADAPTER policy<{'arm64': 'n'}> +CONFIG_VIDEO_C3_MIPI_CSI2 policy<{'arm64': 'n'}> +CONFIG_VIDEO_CADENCE_CSI2RX policy<{'arm64': 'm'}> +CONFIG_VIDEO_CADENCE_CSI2TX policy<{'arm64': 'm'}> +CONFIG_VIDEO_CAFE_CCIC policy<{'arm64': 'm'}> +CONFIG_VIDEO_CAMERA_LENS policy<{'arm64': 'y'}> +CONFIG_VIDEO_CAMERA_SENSOR policy<{'arm64': 'y'}> +CONFIG_VIDEO_CCS policy<{'arm64': 'm'}> +CONFIG_VIDEO_CCS_PLL policy<{'arm64': 'm'}> +CONFIG_VIDEO_CODA policy<{'arm64': 'm'}> +CONFIG_VIDEO_CS3308 policy<{'arm64': 'm'}> +CONFIG_VIDEO_CS5345 policy<{'arm64': 'm'}> +CONFIG_VIDEO_CS53L32A policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX18 policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX18_ALSA policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX231XX policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX231XX_ALSA policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX231XX_DVB policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX231XX_RC policy<{'arm64': 'y'}> +CONFIG_VIDEO_CX2341X policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX23885 policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX25821 policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX25821_ALSA policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX25840 policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX88 policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX88_ALSA policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX88_BLACKBIRD policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX88_DVB policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX88_ENABLE_VP3054 policy<{'arm64': 'y'}> +CONFIG_VIDEO_CX88_MPEG policy<{'arm64': 'm'}> +CONFIG_VIDEO_CX88_VP3054 policy<{'arm64': 'm'}> +CONFIG_VIDEO_DEV policy<{'arm64': 'm'}> +CONFIG_VIDEO_DS90UB913 policy<{'arm64': 'm'}> +CONFIG_VIDEO_DS90UB953 policy<{'arm64': 'm'}> +CONFIG_VIDEO_DS90UB960 policy<{'arm64': 'm'}> +CONFIG_VIDEO_DT3155 policy<{'arm64': 'm'}> +CONFIG_VIDEO_DW100 policy<{'arm64': 'm'}> +CONFIG_VIDEO_DW9714 policy<{'arm64': 'm'}> +CONFIG_VIDEO_DW9719 policy<{'arm64': 'm'}> +CONFIG_VIDEO_DW9768 policy<{'arm64': 'm'}> +CONFIG_VIDEO_DW9807_VCM policy<{'arm64': 'm'}> +CONFIG_VIDEO_DW_MIPI_CSI2RX policy<{'arm64': 'n'}> +CONFIG_VIDEO_E5010_JPEG_ENC policy<{'arm64': 'm'}> +CONFIG_VIDEO_EM28XX policy<{'arm64': 'm'}> +CONFIG_VIDEO_EM28XX_ALSA policy<{'arm64': 'm'}> +CONFIG_VIDEO_EM28XX_DVB policy<{'arm64': 'm'}> +CONFIG_VIDEO_EM28XX_RC policy<{'arm64': 'm'}> +CONFIG_VIDEO_EM28XX_V4L2 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ET8EK8 policy<{'arm64': 'm'}> +CONFIG_VIDEO_FB_IVTV policy<{'arm64': 'm'}> +CONFIG_VIDEO_FIXED_MINOR_RANGES policy<{'arm64': 'n'}> +CONFIG_VIDEO_GC0308 policy<{'arm64': 'm'}> +CONFIG_VIDEO_GC0310 policy<{'arm64': 'm'}> +CONFIG_VIDEO_GC05A2 policy<{'arm64': 'm'}> +CONFIG_VIDEO_GC08A3 policy<{'arm64': 'm'}> +CONFIG_VIDEO_GC2145 policy<{'arm64': 'm'}> +CONFIG_VIDEO_GO7007 policy<{'arm64': 'm'}> +CONFIG_VIDEO_GO7007_LOADER policy<{'arm64': 'm'}> +CONFIG_VIDEO_GO7007_USB policy<{'arm64': 'm'}> +CONFIG_VIDEO_GO7007_USB_S2250_BOARD policy<{'arm64': 'm'}> +CONFIG_VIDEO_GS1662 policy<{'arm64': 'm'}> +CONFIG_VIDEO_HANTRO policy<{'arm64': 'm'}> +CONFIG_VIDEO_HANTRO_HEVC_RFC policy<{'arm64': 'n'}> +CONFIG_VIDEO_HANTRO_IMX8M policy<{'arm64': 'y'}> +CONFIG_VIDEO_HANTRO_ROCKCHIP policy<{'arm64': 'y'}> +CONFIG_VIDEO_HANTRO_STM32MP25 policy<{'arm64': 'y'}> +CONFIG_VIDEO_HANTRO_SUNXI policy<{'arm64': 'y'}> +CONFIG_VIDEO_HDPVR policy<{'arm64': 'm'}> +CONFIG_VIDEO_HEXIUM_GEMINI policy<{'arm64': 'm'}> +CONFIG_VIDEO_HEXIUM_ORION policy<{'arm64': 'm'}> +CONFIG_VIDEO_HI556 policy<{'arm64': 'm'}> +CONFIG_VIDEO_HI846 policy<{'arm64': 'm'}> +CONFIG_VIDEO_HI847 policy<{'arm64': 'm'}> +CONFIG_VIDEO_HWS policy<{'arm64': 'n'}> +CONFIG_VIDEO_I2C policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX111 policy<{'arm64': 'n'}> +CONFIG_VIDEO_IMX208 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX214 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX219 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX258 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX274 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX283 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX290 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX296 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX319 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX334 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX335 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX355 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX412 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX415 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX681 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX7_CSI policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX8_ISI policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX8_ISI_M2M policy<{'arm64': 'y'}> +CONFIG_VIDEO_IMX8_JPEG policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX_MIPI_CSIS policy<{'arm64': 'm'}> +CONFIG_VIDEO_IMX_PXP policy<{'arm64': 'm'}> +CONFIG_VIDEO_INTEL_CVS policy<{'arm64': 'n'}> +CONFIG_VIDEO_IR_I2C policy<{'arm64': 'm'}> +CONFIG_VIDEO_ISL7998X policy<{'arm64': 'm'}> +CONFIG_VIDEO_IVTV policy<{'arm64': 'm'}> +CONFIG_VIDEO_IVTV_ALSA policy<{'arm64': 'm'}> +CONFIG_VIDEO_KS0127 policy<{'arm64': 'm'}> +CONFIG_VIDEO_LM3560 policy<{'arm64': 'm'}> +CONFIG_VIDEO_LM3646 policy<{'arm64': 'm'}> +CONFIG_VIDEO_LT6911UXE policy<{'arm64': 'n'}> +CONFIG_VIDEO_M52790 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MALI_C55 policy<{'arm64': 'n'}> +CONFIG_VIDEO_MAX9271_LIB policy<{'arm64': 'm'}> +CONFIG_VIDEO_MAX9286 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MAX96712 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MAX96714 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MAX96717 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MEDIATEK_JPEG policy<{'arm64': 'n'}> +CONFIG_VIDEO_MEDIATEK_MDP policy<{'arm64': 'n'}> +CONFIG_VIDEO_MEDIATEK_MDP3 policy<{'arm64': 'n'}> +CONFIG_VIDEO_MEDIATEK_VCODEC policy<{'arm64': 'n'}> +CONFIG_VIDEO_MEDIATEK_VPU policy<{'arm64': 'm'}> +CONFIG_VIDEO_MEM2MEM_DEINTERLACE policy<{'arm64': 'm'}> +CONFIG_VIDEO_MESON_GE2D policy<{'arm64': 'm'}> +CONFIG_VIDEO_MESON_VDEC policy<{'arm64': 'm'}> +CONFIG_VIDEO_MGB4 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ML86V7667 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MSP3400 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MT9M001 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MT9M111 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MT9M114 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MT9P031 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MT9T112 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MT9V011 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MT9V032 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MT9V111 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MUX policy<{'arm64': 'm'}> +CONFIG_VIDEO_MXB policy<{'arm64': 'm'}> +CONFIG_VIDEO_NPCM_VCD_ECE policy<{'arm64': 'm'}> +CONFIG_VIDEO_OG01A1B policy<{'arm64': 'm'}> +CONFIG_VIDEO_OG0VE1B policy<{'arm64': 'm'}> +CONFIG_VIDEO_OS05B10 policy<{'arm64': 'n'}> +CONFIG_VIDEO_OV01A10 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV02A10 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV02C10 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV02E10 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV08D10 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV08X40 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV13858 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV13B10 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV2640 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV2659 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV2680 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV2685 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV2732 policy<{'arm64': 'n'}> +CONFIG_VIDEO_OV2735 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV2740 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV4689 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV5640 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV5645 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV5647 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV5648 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV5670 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV5675 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV5693 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV5695 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV6211 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV64A40 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV7251 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV7640 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV7670 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV772X policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV7740 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV8856 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV8858 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV8865 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV9282 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV9640 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV9650 policy<{'arm64': 'm'}> +CONFIG_VIDEO_OV9734 policy<{'arm64': 'm'}> +CONFIG_VIDEO_PCI_SKELETON policy<{'arm64': 'n'}> +CONFIG_VIDEO_PVRUSB2 policy<{'arm64': 'm'}> +CONFIG_VIDEO_PVRUSB2_DEBUGIFC policy<{'arm64': 'n'}> +CONFIG_VIDEO_PVRUSB2_DVB policy<{'arm64': 'y'}> +CONFIG_VIDEO_PVRUSB2_SYSFS policy<{'arm64': 'y'}> +CONFIG_VIDEO_QCOM_CAMSS policy<{'arm64': 'm'}> +CONFIG_VIDEO_QCOM_IRIS policy<{'arm64': 'm'}> +CONFIG_VIDEO_QCOM_VENUS policy<{'arm64': 'm'}> +CONFIG_VIDEO_RCAR_CSI2 policy<{'arm64': 'm'}> +CONFIG_VIDEO_RCAR_DRIF policy<{'arm64': 'm'}> +CONFIG_VIDEO_RCAR_ISP policy<{'arm64': 'm'}> +CONFIG_VIDEO_RCAR_VIN policy<{'arm64': 'm'}> +CONFIG_VIDEO_RDACM20 policy<{'arm64': 'm'}> +CONFIG_VIDEO_RDACM21 policy<{'arm64': 'm'}> +CONFIG_VIDEO_RENESAS_FCP policy<{'arm64': 'm'}> +CONFIG_VIDEO_RENESAS_FDP1 policy<{'arm64': 'm'}> +CONFIG_VIDEO_RENESAS_JPU policy<{'arm64': 'm'}> +CONFIG_VIDEO_RENESAS_VSP1 policy<{'arm64': 'm'}> +CONFIG_VIDEO_RJ54N1 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ROCKCHIP_CIF policy<{'arm64': 'n'}> +CONFIG_VIDEO_ROCKCHIP_ISP1 policy<{'arm64': 'm'}> +CONFIG_VIDEO_ROCKCHIP_RGA policy<{'arm64': 'm'}> +CONFIG_VIDEO_ROCKCHIP_VDEC policy<{'arm64': 'm'}> +CONFIG_VIDEO_RP1_CFE policy<{'arm64': 'n'}> +CONFIG_VIDEO_RZG2L_CRU policy<{'arm64': 'm'}> +CONFIG_VIDEO_RZG2L_CSI2 policy<{'arm64': 'm'}> +CONFIG_VIDEO_RZV2H_IVC policy<{'arm64': 'n'}> +CONFIG_VIDEO_S5C73M3 policy<{'arm64': 'm'}> +CONFIG_VIDEO_S5K3M5 policy<{'arm64': 'n'}> +CONFIG_VIDEO_S5K5BAF policy<{'arm64': 'm'}> +CONFIG_VIDEO_S5K6A3 policy<{'arm64': 'm'}> +CONFIG_VIDEO_S5KJN1 policy<{'arm64': 'n'}> +CONFIG_VIDEO_SAA6588 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA6752HS policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA7110 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA711X policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA7127 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA7134 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA7134_ALSA policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA7134_DVB policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA7134_GO7007 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA7134_RC policy<{'arm64': 'y'}> +CONFIG_VIDEO_SAA7146 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA7146_VV policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA7164 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA717X policy<{'arm64': 'm'}> +CONFIG_VIDEO_SAA7185 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SOLO6X10 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SONY_BTF_MPX policy<{'arm64': 'm'}> +CONFIG_VIDEO_STK1160 policy<{'arm64': 'm'}> +CONFIG_VIDEO_STM32_CSI policy<{'arm64': 'n'}> +CONFIG_VIDEO_STM32_DCMI policy<{'arm64': 'm'}> +CONFIG_VIDEO_STM32_DCMIPP policy<{'arm64': 'm'}> +CONFIG_VIDEO_STM32_DMA2D policy<{'arm64': 'm'}> +CONFIG_VIDEO_ST_MIPID02 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SUN4I_CSI policy<{'arm64': 'm'}> +CONFIG_VIDEO_SUN6I_CSI policy<{'arm64': 'm'}> +CONFIG_VIDEO_SUN6I_ISP policy<{'arm64': 'm'}> +CONFIG_VIDEO_SUN6I_MIPI_CSI2 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 policy<{'arm64': 'm'}> +CONFIG_VIDEO_SUN8I_DEINTERLACE policy<{'arm64': 'm'}> +CONFIG_VIDEO_SUN8I_ROTATE policy<{'arm64': 'm'}> +CONFIG_VIDEO_SUNXI policy<{'arm64': 'y'}> +CONFIG_VIDEO_SUNXI_CEDRUS policy<{'arm64': 'm'}> +CONFIG_VIDEO_SYNOPSYS_HDMIRX policy<{'arm64': 'n'}> +CONFIG_VIDEO_T4KA3 policy<{'arm64': 'n'}> +CONFIG_VIDEO_TC358743 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TC358743_CEC policy<{'arm64': 'y'}> +CONFIG_VIDEO_TC358746 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TDA1997X policy<{'arm64': 'm'}> +CONFIG_VIDEO_TDA7432 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TDA9840 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TEA6415C policy<{'arm64': 'm'}> +CONFIG_VIDEO_TEA6420 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TEGRA policy<{'arm64': 'm'}> +CONFIG_VIDEO_TEGRA_TPG policy<{'arm64': 'y'}> +CONFIG_VIDEO_TEGRA_VDE policy<{'arm64': 'm'}> +CONFIG_VIDEO_THP7312 policy<{'arm64': 'm'}> +CONFIG_VIDEO_THS7303 policy<{'arm64': 'm'}> +CONFIG_VIDEO_THS8200 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TI_CAL policy<{'arm64': 'm'}> +CONFIG_VIDEO_TI_CAL_MC policy<{'arm64': 'y'}> +CONFIG_VIDEO_TI_J721E_CSI2RX policy<{'arm64': 'm'}> +CONFIG_VIDEO_TLV320AIC23B policy<{'arm64': 'm'}> +CONFIG_VIDEO_TUNER policy<{'arm64': 'm'}> +CONFIG_VIDEO_TVAUDIO policy<{'arm64': 'm'}> +CONFIG_VIDEO_TVEEPROM policy<{'arm64': 'm'}> +CONFIG_VIDEO_TVP514X policy<{'arm64': 'm'}> +CONFIG_VIDEO_TVP5150 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TVP7002 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TW2804 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TW5864 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TW68 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TW686X policy<{'arm64': 'm'}> +CONFIG_VIDEO_TW9900 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TW9903 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TW9906 policy<{'arm64': 'm'}> +CONFIG_VIDEO_TW9910 policy<{'arm64': 'm'}> +CONFIG_VIDEO_UDA1342 policy<{'arm64': 'm'}> +CONFIG_VIDEO_UPD64031A policy<{'arm64': 'm'}> +CONFIG_VIDEO_UPD64083 policy<{'arm64': 'm'}> +CONFIG_VIDEO_USBTV policy<{'arm64': 'm'}> +CONFIG_VIDEO_V4L2_I2C policy<{'arm64': 'y'}> +CONFIG_VIDEO_V4L2_SUBDEV_API policy<{'arm64': 'y'}> +CONFIG_VIDEO_V4L2_TPG policy<{'arm64': 'm'}> +CONFIG_VIDEO_VD55G1 policy<{'arm64': 'n'}> +CONFIG_VIDEO_VD56G3 policy<{'arm64': 'n'}> +CONFIG_VIDEO_VGXY61 policy<{'arm64': 'm'}> +CONFIG_VIDEO_VICODEC policy<{'arm64': 'm'}> +CONFIG_VIDEO_VIM2M policy<{'arm64': 'm'}> +CONFIG_VIDEO_VISL policy<{'arm64': 'm'}> +CONFIG_VIDEO_VIVID policy<{'arm64': 'm'}> +CONFIG_VIDEO_VIVID_CEC policy<{'arm64': 'y'}> +CONFIG_VIDEO_VIVID_MAX_DEVS policy<{'arm64': '64'}> +CONFIG_VIDEO_VIVID_OSD policy<{'arm64': 'y'}> +CONFIG_VIDEO_VP27SMPX policy<{'arm64': 'm'}> +CONFIG_VIDEO_VPX3220 policy<{'arm64': 'm'}> +CONFIG_VIDEO_WAVE_VPU policy<{'arm64': 'm'}> +CONFIG_VIDEO_WM8739 policy<{'arm64': 'm'}> +CONFIG_VIDEO_WM8775 policy<{'arm64': 'm'}> +CONFIG_VIDEO_XILINX policy<{'arm64': 'm'}> +CONFIG_VIDEO_XILINX_CSI2RXSS policy<{'arm64': 'm'}> +CONFIG_VIDEO_XILINX_TPG policy<{'arm64': 'm'}> +CONFIG_VIDEO_XILINX_VTC policy<{'arm64': 'm'}> +CONFIG_VIDEO_ZORAN policy<{'arm64': 'n'}> +CONFIG_VIPERBOARD_ADC policy<{'arm64': 'm'}> +CONFIG_VIRTIO policy<{'arm64': 'y'}> +CONFIG_VIRTIO_ANCHOR policy<{'arm64': 'y'}> +CONFIG_VIRTIO_BALLOON policy<{'arm64': 'y'}> +CONFIG_VIRTIO_CONSOLE policy<{'arm64': 'y'}> +CONFIG_VIRTIO_DEBUG policy<{'arm64': 'n'}> +CONFIG_VIRTIO_DMA_SHARED_BUFFER policy<{'arm64': 'm'}> +CONFIG_VIRTIO_FS policy<{'arm64': 'm'}> +CONFIG_VIRTIO_INPUT policy<{'arm64': 'm'}> +CONFIG_VIRTIO_IOMMU policy<{'arm64': 'y'}> +CONFIG_VIRTIO_MEM policy<{'arm64': 'm'}> +CONFIG_VIRTIO_MENU policy<{'arm64': 'y'}> +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES policy<{'arm64': 'y'}> +CONFIG_VIRTIO_PCI policy<{'arm64': 'y'}> +CONFIG_VIRTIO_PCI_LEGACY policy<{'arm64': 'y'}> +CONFIG_VIRTIO_PCI_LIB policy<{'arm64': 'y'}> +CONFIG_VIRTIO_PCI_LIB_LEGACY policy<{'arm64': 'y'}> +CONFIG_VIRTIO_PMEM policy<{'arm64': 'm'}> +CONFIG_VIRTIO_RTC policy<{'arm64': 'n'}> +CONFIG_VIRTIO_VDPA policy<{'arm64': 'm'}> +CONFIG_VIRTIO_VFIO_PCI policy<{'arm64': 'n'}> +CONFIG_VIRTIO_VSOCKETS policy<{'arm64': 'm'}> +CONFIG_VIRTIO_VSOCKETS_COMMON policy<{'arm64': 'm'}> +CONFIG_VIRTUALIZATION policy<{'arm64': 'y'}> +CONFIG_VIRT_CPU_ACCOUNTING policy<{'arm64': 'y'}> +CONFIG_VIRT_CPU_ACCOUNTING_GEN policy<{'arm64': 'y'}> +CONFIG_VIRT_DRIVERS policy<{'arm64': 'y'}> +CONFIG_VIRT_WIFI policy<{'arm64': 'm'}> +CONFIG_VIRT_XFER_TO_GUEST_WORK policy<{'arm64': 'y'}> +CONFIG_VISCONTI_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_VISL_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_VITESSE_PHY policy<{'arm64': 'm'}> +CONFIG_VL53L0X_I2C policy<{'arm64': 'm'}> +CONFIG_VL53L1X_I2C policy<{'arm64': 'n'}> +CONFIG_VL6180 policy<{'arm64': 'm'}> +CONFIG_VLAN_8021Q policy<{'arm64': 'm'}> +CONFIG_VLAN_8021Q_GVRP policy<{'arm64': 'y'}> +CONFIG_VLAN_8021Q_MVRP policy<{'arm64': 'y'}> +CONFIG_VMAP_PFN policy<{'arm64': 'y'}> +CONFIG_VMAP_STACK policy<{'arm64': 'y'}> +CONFIG_VMCORE_INFO policy<{'arm64': 'y'}> +CONFIG_VME_BUS policy<{'arm64': 'y'}> +CONFIG_VME_FAKE policy<{'arm64': 'm'}> +CONFIG_VME_TSI148 policy<{'arm64': 'm'}> +CONFIG_VME_USER policy<{'arm64': 'm'}> +CONFIG_VMGENID policy<{'arm64': 'm'}> +CONFIG_VMLINUX_MAP policy<{'arm64': 'y'}> +CONFIG_VMWARE_VMCI policy<{'arm64': 'm'}> +CONFIG_VMWARE_VMCI_VSOCKETS policy<{'arm64': 'm'}> +CONFIG_VMXNET3 policy<{'arm64': 'm'}> +CONFIG_VM_EVENT_COUNTERS policy<{'arm64': 'y'}> +CONFIG_VORTEX policy<{'arm64': 'm'}> +CONFIG_VP_VDPA policy<{'arm64': 'm'}> +CONFIG_VSI_IOMMU policy<{'arm64': 'n'}> +CONFIG_VSOCKETS policy<{'arm64': 'm'}> +CONFIG_VSOCKETS_DIAG policy<{'arm64': 'm'}> +CONFIG_VSOCKETS_LOOPBACK policy<{'arm64': 'm'}> +CONFIG_VSOCKMON policy<{'arm64': 'm'}> +CONFIG_VT policy<{'arm64': 'y'}> +CONFIG_VT_CONSOLE policy<{'arm64': 'y'}> +CONFIG_VT_CONSOLE_SLEEP policy<{'arm64': 'y'}> +CONFIG_VT_HW_CONSOLE_BINDING policy<{'arm64': 'y'}> +CONFIG_VXFS_FS policy<{'arm64': 'm'}> +CONFIG_VXLAN policy<{'arm64': 'm'}> +CONFIG_VZ89X policy<{'arm64': 'm'}> +CONFIG_W1 policy<{'arm64': 'm'}> +CONFIG_W1_CON policy<{'arm64': 'y'}> +CONFIG_W1_MASTER_AMD_AXI policy<{'arm64': 'm'}> +CONFIG_W1_MASTER_DS2482 policy<{'arm64': 'm'}> +CONFIG_W1_MASTER_DS2490 policy<{'arm64': 'm'}> +CONFIG_W1_MASTER_GPIO policy<{'arm64': 'm'}> +CONFIG_W1_MASTER_MATROX policy<{'arm64': 'm'}> +CONFIG_W1_MASTER_MXC policy<{'arm64': 'm'}> +CONFIG_W1_MASTER_SGI policy<{'arm64': 'm'}> +CONFIG_W1_MASTER_UART policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2405 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2406 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2408 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2408_READBACK policy<{'arm64': 'y'}> +CONFIG_W1_SLAVE_DS2413 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2423 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2430 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2431 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2433 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2433_CRC policy<{'arm64': 'n'}> +CONFIG_W1_SLAVE_DS2438 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS250X policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2780 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2781 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS2805 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS28E04 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_DS28E17 policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_SMEM policy<{'arm64': 'm'}> +CONFIG_W1_SLAVE_THERM policy<{'arm64': 'm'}> +CONFIG_WAN policy<{'arm64': 'y'}> +CONFIG_WANT_DEV_COREDUMP policy<{'arm64': 'y'}> +CONFIG_WANXL policy<{'arm64': 'm'}> +CONFIG_WATCHDOG policy<{'arm64': 'y'}> +CONFIG_WATCHDOG_CORE policy<{'arm64': 'y'}> +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED policy<{'arm64': 'y'}> +CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT policy<{'arm64': 'n'}> +CONFIG_WATCHDOG_NOWAYOUT policy<{'arm64': 'n'}> +CONFIG_WATCHDOG_OPEN_TIMEOUT policy<{'arm64': '0'}> +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP policy<{'arm64': 'y'}> +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC policy<{'arm64': 'n'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV policy<{'arm64': 'y'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP policy<{'arm64': 'y'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC policy<{'arm64': 'm'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL policy<{'arm64': 'm'}> +CONFIG_WATCHDOG_SYSFS policy<{'arm64': 'y'}> +CONFIG_WATCH_QUEUE policy<{'arm64': 'y'}> +CONFIG_WCN36XX policy<{'arm64': 'm'}> +CONFIG_WCN36XX_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_WDAT_WDT policy<{'arm64': 'm'}> +CONFIG_WDTPCI policy<{'arm64': 'm'}> +CONFIG_WERROR policy<{'arm64': 'n'}> +CONFIG_WEXT_CORE policy<{'arm64': 'y'}> +CONFIG_WEXT_PRIV policy<{'arm64': 'y'}> +CONFIG_WEXT_PROC policy<{'arm64': 'y'}> +CONFIG_WFX policy<{'arm64': 'm'}> +CONFIG_WIL6210 policy<{'arm64': 'm'}> +CONFIG_WIL6210_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_WIL6210_ISR_COR policy<{'arm64': 'y'}> +CONFIG_WIL6210_TRACING policy<{'arm64': 'y'}> +CONFIG_WILC1000 policy<{'arm64': 'm'}> +CONFIG_WILC1000_HW_OOB_INTR policy<{'arm64': 'y'}> +CONFIG_WILC1000_SDIO policy<{'arm64': 'm'}> +CONFIG_WILC1000_SPI policy<{'arm64': 'm'}> +CONFIG_WINBOND_840 policy<{'arm64': 'm'}> +CONFIG_WIREGUARD policy<{'arm64': 'm'}> +CONFIG_WIREGUARD_DEBUG policy<{'arm64': 'n'}> +CONFIG_WIRELESS policy<{'arm64': 'y'}> +CONFIG_WIRELESS_EXT policy<{'arm64': 'y'}> +CONFIG_WIZNET_W5100 policy<{'arm64': 'm'}> +CONFIG_WL1251 policy<{'arm64': 'm'}> +CONFIG_WL1251_SDIO policy<{'arm64': 'm'}> +CONFIG_WL1251_SPI policy<{'arm64': 'm'}> +CONFIG_WL12XX policy<{'arm64': 'm'}> +CONFIG_WL18XX policy<{'arm64': 'm'}> +CONFIG_WLAN policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_ADMTEK policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_ATH policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_ATMEL policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_BROADCOM policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_INTEL policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_INTERSIL policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_MARVELL policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_MEDIATEK policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_MICROCHIP policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_PURELIFI policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_QUANTENNA policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_RALINK policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_REALTEK policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_RSI policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_SILABS policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_ST policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_TI policy<{'arm64': 'y'}> +CONFIG_WLAN_VENDOR_ZYDAS policy<{'arm64': 'y'}> +CONFIG_WLCORE policy<{'arm64': 'm'}> +CONFIG_WLCORE_SDIO policy<{'arm64': 'm'}> +CONFIG_WLCORE_SPI policy<{'arm64': 'm'}> +CONFIG_WM831X_BACKUP policy<{'arm64': 'm'}> +CONFIG_WM831X_POWER policy<{'arm64': 'm'}> +CONFIG_WM831X_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_WM8350_POWER policy<{'arm64': 'm'}> +CONFIG_WM8350_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_WPCM450_SOC policy<{'arm64': 'm'}> +CONFIG_WQ_CPU_INTENSIVE_REPORT policy<{'arm64': 'y'}> +CONFIG_WQ_POWER_EFFICIENT_DEFAULT policy<{'arm64': 'y'}> +CONFIG_WQ_WATCHDOG policy<{'arm64': 'n'}> +CONFIG_WWAN_DEBUGFS policy<{'arm64': 'y'}> +CONFIG_WWAN_HWSIM policy<{'arm64': 'm'}> +CONFIG_WW_MUTEX_SELFTEST policy<{'arm64': 'n'}> +CONFIG_X25 policy<{'arm64': 'm'}> +CONFIG_X9250 policy<{'arm64': 'm'}> +CONFIG_XARRAY_MULTI policy<{'arm64': 'y'}> +CONFIG_XDP_SOCKETS policy<{'arm64': 'y'}> +CONFIG_XDP_SOCKETS_DIAG policy<{'arm64': 'm'}> +CONFIG_XEN policy<{'arm64': 'y'}> +CONFIG_XENFS policy<{'arm64': 'm'}> +CONFIG_XEN_AUTO_XLATE policy<{'arm64': 'y'}> +CONFIG_XEN_BACKEND policy<{'arm64': 'y'}> +CONFIG_XEN_BALLOON policy<{'arm64': 'y'}> +CONFIG_XEN_BALLOON_MEMORY_HOTPLUG policy<{'arm64': 'y'}> +CONFIG_XEN_BLKDEV_BACKEND policy<{'arm64': 'm'}> +CONFIG_XEN_COMPAT_XENFS policy<{'arm64': 'y'}> +CONFIG_XEN_DEV_EVTCHN policy<{'arm64': 'm'}> +CONFIG_XEN_DOM0 policy<{'arm64': 'y'}> +CONFIG_XEN_EFI policy<{'arm64': 'y'}> +CONFIG_XEN_FBDEV_FRONTEND policy<{'arm64': 'm'}> +CONFIG_XEN_FRONT_PGDIR_SHBUF policy<{'arm64': 'm'}> +CONFIG_XEN_GNTDEV policy<{'arm64': 'm'}> +CONFIG_XEN_GNTDEV_DMABUF policy<{'arm64': 'y'}> +CONFIG_XEN_GRANT_DEV_ALLOC policy<{'arm64': 'm'}> +CONFIG_XEN_GRANT_DMA_ALLOC policy<{'arm64': 'y'}> +CONFIG_XEN_GRANT_DMA_IOMMU policy<{'arm64': 'y'}> +CONFIG_XEN_GRANT_DMA_OPS policy<{'arm64': 'y'}> +CONFIG_XEN_NETDEV_BACKEND policy<{'arm64': 'm'}> +CONFIG_XEN_PCIDEV_STUB policy<{'arm64': 'm'}> +CONFIG_XEN_PCI_STUB policy<{'arm64': 'y'}> +CONFIG_XEN_PRIVCMD policy<{'arm64': 'm'}> +CONFIG_XEN_PRIVCMD_EVENTFD policy<{'arm64': 'y'}> +CONFIG_XEN_PVCALLS_BACKEND policy<{'arm64': 'n'}> +CONFIG_XEN_PVCALLS_FRONTEND policy<{'arm64': 'm'}> +CONFIG_XEN_SCRUB_PAGES_DEFAULT policy<{'arm64': 'y'}> +CONFIG_XEN_SCSI_BACKEND policy<{'arm64': 'm'}> +CONFIG_XEN_SCSI_FRONTEND policy<{'arm64': 'm'}> +CONFIG_XEN_SYS_HYPERVISOR policy<{'arm64': 'y'}> +CONFIG_XEN_UNPOPULATED_ALLOC policy<{'arm64': 'y'}> +CONFIG_XEN_VIRTIO policy<{'arm64': 'y'}> +CONFIG_XEN_VIRTIO_FORCE_GRANT policy<{'arm64': 'n'}> +CONFIG_XEN_WDT policy<{'arm64': 'm'}> +CONFIG_XEN_XENBUS_FRONTEND policy<{'arm64': 'y'}> +CONFIG_XE_VFIO_PCI policy<{'arm64': 'n'}> +CONFIG_XFRM policy<{'arm64': 'y'}> +CONFIG_XFRM_AH policy<{'arm64': 'm'}> +CONFIG_XFRM_ALGO policy<{'arm64': 'm'}> +CONFIG_XFRM_ESP policy<{'arm64': 'm'}> +CONFIG_XFRM_ESPINTCP policy<{'arm64': 'y'}> +CONFIG_XFRM_INTERFACE policy<{'arm64': 'm'}> +CONFIG_XFRM_IPCOMP policy<{'arm64': 'm'}> +CONFIG_XFRM_IPTFS policy<{'arm64': 'n'}> +CONFIG_XFRM_MIGRATE policy<{'arm64': 'n'}> +CONFIG_XFRM_OFFLOAD policy<{'arm64': 'y'}> +CONFIG_XFRM_STATISTICS policy<{'arm64': 'y'}> +CONFIG_XFRM_SUB_POLICY policy<{'arm64': 'n'}> +CONFIG_XFRM_USER policy<{'arm64': 'm'}> +CONFIG_XFS_DEBUG policy<{'arm64': 'n'}> +CONFIG_XFS_FS policy<{'arm64': 'm'}> +CONFIG_XFS_ONLINE_SCRUB policy<{'arm64': 'n'}> +CONFIG_XFS_POSIX_ACL policy<{'arm64': 'y'}> +CONFIG_XFS_QUOTA policy<{'arm64': 'y'}> +CONFIG_XFS_RT policy<{'arm64': 'y'}> +CONFIG_XFS_SUPPORT_ASCII_CI policy<{'arm64': 'y'}> +CONFIG_XFS_SUPPORT_V4 policy<{'arm64': 'y'}> +CONFIG_XFS_WARN policy<{'arm64': 'n'}> +CONFIG_XGENE_DMA policy<{'arm64': 'm'}> +CONFIG_XGENE_PMU policy<{'arm64': 'y'}> +CONFIG_XGENE_SLIMPRO_MBOX policy<{'arm64': 'm'}> +CONFIG_XILINX_AMS policy<{'arm64': 'm'}> +CONFIG_XILINX_AXI_EMAC policy<{'arm64': 'm'}> +CONFIG_XILINX_DMA policy<{'arm64': 'm'}> +CONFIG_XILINX_EMACLITE policy<{'arm64': 'm'}> +CONFIG_XILINX_GMII2RGMII policy<{'arm64': 'm'}> +CONFIG_XILINX_INTC policy<{'arm64': 'y'}> +CONFIG_XILINX_LL_TEMAC policy<{'arm64': 'm'}> +CONFIG_XILINX_PR_DECOUPLER policy<{'arm64': 'm'}> +CONFIG_XILINX_SDFEC policy<{'arm64': 'm'}> +CONFIG_XILINX_VCU policy<{'arm64': 'm'}> +CONFIG_XILINX_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_XILINX_WINDOW_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_XILINX_XADC policy<{'arm64': 'm'}> +CONFIG_XILINX_XDMA policy<{'arm64': 'm'}> +CONFIG_XILINX_ZYNQMP_DMA policy<{'arm64': 'm'}> +CONFIG_XILINX_ZYNQMP_DPDMA policy<{'arm64': 'm'}> +CONFIG_XILLYBUS policy<{'arm64': 'm'}> +CONFIG_XILLYBUS_CLASS policy<{'arm64': 'm'}> +CONFIG_XILLYBUS_OF policy<{'arm64': 'm'}> +CONFIG_XILLYBUS_PCIE policy<{'arm64': 'm'}> +CONFIG_XILLYUSB policy<{'arm64': 'm'}> +CONFIG_XIL_AXIS_FIFO policy<{'arm64': 'm'}> +CONFIG_XLNX_EVENT_MANAGER policy<{'arm64': 'y'}> +CONFIG_XLNX_R5_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_XOR_BLOCKS policy<{'arm64': 'm'}> +CONFIG_XOR_BLOCKS_ARCH policy<{'arm64': 'y'}> +CONFIG_XPS policy<{'arm64': 'y'}> +CONFIG_XXHASH policy<{'arm64': 'y'}> +CONFIG_XZ_DEC_ARM policy<{'arm64': 'y'}> +CONFIG_XZ_DEC_ARM64 policy<{'arm64': 'y'}> +CONFIG_XZ_DEC_ARMTHUMB policy<{'arm64': 'y'}> +CONFIG_XZ_DEC_BCJ policy<{'arm64': 'y'}> +CONFIG_XZ_DEC_MICROLZMA policy<{'arm64': 'y'}> +CONFIG_XZ_DEC_POWERPC policy<{'arm64': 'y'}> +CONFIG_XZ_DEC_RISCV policy<{'arm64': 'y'}> +CONFIG_XZ_DEC_SPARC policy<{'arm64': 'y'}> +CONFIG_XZ_DEC_TEST policy<{'arm64': 'm'}> +CONFIG_XZ_DEC_X86 policy<{'arm64': 'y'}> +CONFIG_YAMAHA_YAS530 policy<{'arm64': 'm'}> +CONFIG_YENTA policy<{'arm64': 'm'}> +CONFIG_YENTA_ENE_TUNE policy<{'arm64': 'y'}> +CONFIG_YENTA_O2 policy<{'arm64': 'y'}> +CONFIG_YENTA_RICOH policy<{'arm64': 'y'}> +CONFIG_YENTA_TI policy<{'arm64': 'y'}> +CONFIG_YENTA_TOSHIBA policy<{'arm64': 'y'}> +CONFIG_ZD1211RW policy<{'arm64': 'm'}> +CONFIG_ZD1211RW_DEBUG policy<{'arm64': 'n'}> +CONFIG_ZEROPLUS_FF policy<{'arm64': 'y'}> +CONFIG_ZERO_CALL_USED_REGS policy<{'arm64': 'y'}> +CONFIG_ZIIRAVE_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_ZISOFS policy<{'arm64': 'y'}> +CONFIG_ZL3073X_I2C policy<{'arm64': 'n'}> +CONFIG_ZL3073X_SPI policy<{'arm64': 'n'}> +CONFIG_ZLIB_DEFLATE policy<{'arm64': 'y'}> +CONFIG_ZLIB_INFLATE policy<{'arm64': 'y'}> +CONFIG_ZONEFS_FS policy<{'arm64': 'm'}> +CONFIG_ZONE_DEVICE policy<{'arm64': 'y'}> +CONFIG_ZONE_DMA32 policy<{'arm64': 'y'}> +CONFIG_ZOPT2201 policy<{'arm64': 'm'}> +CONFIG_ZPA2326 policy<{'arm64': 'm'}> +CONFIG_ZPA2326_I2C policy<{'arm64': 'm'}> +CONFIG_ZPA2326_SPI policy<{'arm64': 'm'}> +CONFIG_ZRAM policy<{'arm64': 'm'}> +CONFIG_ZRAM_BACKEND_842 policy<{'arm64': 'y'}> +CONFIG_ZRAM_BACKEND_DEFLATE policy<{'arm64': 'y'}> +CONFIG_ZRAM_BACKEND_LZ4 policy<{'arm64': 'y'}> +CONFIG_ZRAM_BACKEND_LZ4HC policy<{'arm64': 'y'}> +CONFIG_ZRAM_BACKEND_LZO policy<{'arm64': 'y'}> +CONFIG_ZRAM_BACKEND_ZSTD policy<{'arm64': 'y'}> +CONFIG_ZRAM_DEF_COMP policy<{'arm64': '"lzo-rle"'}> +CONFIG_ZRAM_DEF_COMP_842 policy<{'arm64': 'n'}> +CONFIG_ZRAM_DEF_COMP_DEFLATE policy<{'arm64': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZ4 policy<{'arm64': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZ4HC policy<{'arm64': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZO policy<{'arm64': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZORLE policy<{'arm64': 'y'}> +CONFIG_ZRAM_DEF_COMP_ZSTD policy<{'arm64': 'n'}> +CONFIG_ZRAM_MEMORY_TRACKING policy<{'arm64': 'y'}> +CONFIG_ZRAM_MULTI_COMP policy<{'arm64': 'n'}> +CONFIG_ZRAM_TRACK_ENTRY_ACTIME policy<{'arm64': 'y'}> +CONFIG_ZRAM_WRITEBACK policy<{'arm64': 'y'}> +CONFIG_ZSMALLOC policy<{'arm64': 'y'}> +CONFIG_ZSMALLOC_CHAIN_SIZE policy<{'arm64': '8'}> +CONFIG_ZSMALLOC_STAT policy<{'arm64': 'n'}> +CONFIG_ZSTD_COMMON policy<{'arm64': 'y'}> +CONFIG_ZSTD_COMPRESS policy<{'arm64': 'y'}> +CONFIG_ZSTD_DECOMPRESS policy<{'arm64': 'y'}> +CONFIG_ZSWAP policy<{'arm64': 'y'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT policy<{'arm64': '"lzo"'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 policy<{'arm64': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE policy<{'arm64': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 policy<{'arm64': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC policy<{'arm64': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO policy<{'arm64': 'y'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD policy<{'arm64': 'n'}> +CONFIG_ZSWAP_DEFAULT_ON policy<{'arm64': 'n'}> +CONFIG_ZSWAP_SHRINKER_DEFAULT_ON policy<{'arm64': 'y'}> +CONFIG_ZYNQMP_FIRMWARE policy<{'arm64': 'y'}> +CONFIG_ZYNQMP_FIRMWARE_DEBUG policy<{'arm64': 'n'}> +CONFIG_ZYNQMP_IPI_MBOX policy<{'arm64': 'y'}> +CONFIG_ZYNQMP_PM_DOMAINS policy<{'arm64': 'y'}> +CONFIG_ZYNQMP_POWER policy<{'arm64': 'y'}> diff --git a/debian.qcom-x1e/control.d/flavour-control.stub b/debian.qcom-x1e/control.d/flavour-control.stub new file mode 100644 index 00000000000000..4055c769adb64d --- /dev/null +++ b/debian.qcom-x1e/control.d/flavour-control.stub @@ -0,0 +1,87 @@ +# Items that get replaced: +# FLAVOUR +# ARCH +# SUPPORTED +# TARGET +# BOOTLOADER +# =PROVIDES= +# +# Items marked with =FOO= are optional +# +# This file describes the template for packages that are created for each flavour +# in debian/control.d/vars.* +# +# This file gets edited in a couple of places. See the debian/control.stub rule in +# debian/rules. PGGVER, ABINUM, and SRCPKGNAME are all converted in the +# process of creating debian/control. +# +# The flavour specific strings (ARCH, etc) are converted using values from the various +# flavour files in debian/control.d/vars.* +# +# XXX: Leave the blank line before the first package!! + +Package: linux-modules-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, wireless-regdb +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel modules for version PKGVER + Contains the corresponding System.map file, the modules built by the + packager, and scripts that try to ensure that the system is not left in an + unbootable state after an update. + . + Supports SUPPORTED processors. + . + TARGET + . + You likely do not want to install this package directly. Instead, install + the linux-FLAVOUR meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-headers-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-headers-PKGVER-ABINUM, ${shlibs:Depends} +Provides: linux-headers, linux-headers-3.0 +Description: Linux kernel headers for version PKGVER + This package provides kernel header files for version PKGVER. + . + This is for sites that want the latest kernel headers. Please read + /usr/share/doc/linux-headers-PKGVER-ABINUM/debian.README.gz for details. + +Package: linux-lib-rust-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: amd64 +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Rust library files related to Linux kernel version PKGVER + This package provides kernel library files for version PKGVER, that allow to + compile out-of-tree kernel modules written in Rust. + +Package: linux-tools-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-tools-PKGVER-ABINUM +Description: Linux kernel version specific tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools (such as x86_energy_perf_policy) for + version PKGVER-ABINUM. + +Package: linux-cloud-tools-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-cloud-tools-PKGVER-ABINUM +Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools for cloud for version PKGVER-ABINUM. + diff --git a/debian.qcom-x1e/control.d/flavour-signed-control.stub b/debian.qcom-x1e/control.d/flavour-signed-control.stub new file mode 100644 index 00000000000000..b8551a52e743fa --- /dev/null +++ b/debian.qcom-x1e/control.d/flavour-signed-control.stub @@ -0,0 +1,38 @@ +Package: linux-image=SIGN-ME-PKG=-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Provides: linux-image, fuse-module, =PROVIDES=${linux:rprovides} +Depends: ${misc:Depends}, ${shlibs:Depends}, kmod, linux-base (>= 4.5ubuntu1~16.04.1), linux-modules-PKGVER-ABINUM-FLAVOUR +Recommends: BOOTLOADER, initramfs-tools | linux-initramfs-tool +Breaks: flash-kernel (<< 3.90ubuntu2) [arm64 armhf], s390-tools (<< 2.3.0-0ubuntu3) [s390x] +Conflicts: linux-image=SIGN-PEER-PKG=-PKGVER-ABINUM-FLAVOUR +Suggests: bpftool, linux-perf, SRCPKGNAME-tools, linux-headers-PKGVER-ABINUM-FLAVOUR +Description: Linux kernel image for version PKGVER + This package contains the=SIGN-ME-TXT= Linux kernel image for version PKGVER. + . + Supports SUPPORTED processors. + . + TARGET + . + You likely do not want to install this package directly. Instead, install + the linux-FLAVOUR meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-image=SIGN-ME-PKG=-PKGVER-ABINUM-FLAVOUR-dbgsym +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends} +Provides: linux-debug +Description: Linux kernel debug image for version PKGVER + This package provides the=SIGN-ME-TXT= kernel debug image for version PKGVER. + . + This is for sites that wish to debug the kernel. + . + The kernel image contained in this package is NOT meant to boot from. It + is uncompressed, and unstripped. This package also includes the + unstripped modules. + diff --git a/debian.qcom-x1e/control.d/qcom-x1e.inclusion-list b/debian.qcom-x1e/control.d/qcom-x1e.inclusion-list new file mode 100644 index 00000000000000..e414985ad12f15 --- /dev/null +++ b/debian.qcom-x1e/control.d/qcom-x1e.inclusion-list @@ -0,0 +1,306 @@ +arch/*/{crypto,kernel,oprofile} +arch/*/kvm/kvm.ko +arch/powerpc/kvm/kvm-hv.ko +arch/powerpc/kvm/kvm-pr.ko +arch/powerpc/kvm/vfio.ko +arch/powerpc/platforms/powernv/opal-prd.ko +arch/s390/* +arch/x86/kvm/kvm-amd.ko +arch/x86/kvm/kvm-intel.ko +crypto/* +drivers/acpi/* +drivers/ata/acard-ahci.ko +drivers/ata/ahci.ko +drivers/ata/ahci_platform.ko +drivers/ata/ahci_tegra.ko +drivers/ata/ata_generic.ko +drivers/ata/libahci.ko +drivers/ata/libahci_platform.ko +drivers/block/brd.ko +drivers/block/cryptoloop.ko +drivers/block/floppy.ko +drivers/block/loop.ko +drivers/block/nbd.ko +drivers/block/rbd.ko +drivers/block/virtio_blk.ko +drivers/block/xen-blkfront.ko +drivers/bus/tegra-aconnect.ko +drivers/char/hangcheck-timer.ko +drivers/char/hw_random/powernv-rng.ko +drivers/char/hw_random/virtio-rng.ko +drivers/char/ipmi/* +drivers/char/ipmi/ipmi_msghandler.ko +drivers/char/lp.ko +drivers/char/nvram.ko +drivers/char/ppdev.ko +drivers/char/raw.ko +drivers/char/virtio_console.ko +drivers/clk/clk-max77686.ko +drivers/cpufreq/tegra186-cpufreq.ko +drivers/cpufreq/tegra194-cpufreq.ko +drivers/crypto/nx/* +drivers/crypto/vmx/vmx-crypto.ko +drivers/dma/tegra210-adma.ko +drivers/firmware/dmi-sysfs.ko +drivers/firmware/efi/* +drivers/firmware/iscsi_ibft.ko +drivers/gpio/gpio-max77620.ko +drivers/gpu/drm/ast/ast.ko +drivers/gpu/drm/bochs/bochs-drm.ko +drivers/gpu/drm/cirrus/cirrus.ko +drivers/gpu/drm/drm.ko +drivers/gpu/drm/drm_kms_helper.ko +drivers/gpu/drm/tegra/tegra-drm.ko +drivers/gpu/drm/ttm/ttm.ko +drivers/gpu/drm/vboxvideo/vboxvideo.ko +drivers/gpu/drm/virtio/virtio-gpu.ko +drivers/gpu/drm/vmwgfx/vmwgfx.ko +drivers/gpu/drm/xen/drm_xen_front.ko +drivers/gpu/host1x/host1x.ko +drivers/hid/hid-generic.ko +drivers/hid/hid-hyperv.ko +drivers/hid/hid.ko +drivers/hid/usbhid/usbhid.ko +drivers/hv/* +drivers/hwmon/ibmpowernv.ko +drivers/hwmon/pwm-fan.ko +drivers/i2c/busses/i2c-tegra-bpmp.ko +drivers/i2c/busses/i2c-tegra-bpmp.ko +drivers/i2c/busses/i2c-tegra.ko +drivers/infiniband/core/ib_addr.ko +drivers/infiniband/core/ib_cm.ko +drivers/infiniband/core/ib_core.ko +drivers/infiniband/core/ib_mad.ko +drivers/infiniband/core/ib_sa.ko +drivers/infiniband/core/iw_cm.ko +drivers/infiniband/core/rdma_cm.ko +drivers/infiniband/ulp/iser/ib_iser.ko +drivers/infiniband/ulp/isert/ib_isert.ko +drivers/input/evbug.ko +drivers/input/gameport/gameport.ko +drivers/input/input-leds.ko +drivers/input/joydev.ko +drivers/input/keyboard/gpio_keys.ko +drivers/input/misc/xen-kbdfront.ko +drivers/input/mouse/psmouse.ko +drivers/input/serio/hyperv-keyboard.ko +drivers/input/serio/serio_raw.ko +drivers/input/serio/serport.ko +drivers/input/touchscreen/usbtouchscreen.ko +drivers/leds/leds-powernv.ko +drivers/md/* +drivers/memory/tegra/tegra210-emc.ko +drivers/message/fusion* +drivers/misc/cxl/* +drivers/misc/eeprom/at24.ko +drivers/misc/vmw_balloon.ko +drivers/misc/vmw_vmci/vmw_vmci.ko +drivers/mmc/host/sdhci-tegra.ko +drivers/mtd/cmdlinepart.ko +drivers/mtd/devices/powernv_flash.ko +drivers/mtd/ofpart.ko +drivers/net/appletalk/ipddp.ko +drivers/net/bonding/bonding.ko +drivers/net/caif/caif_virtio.ko +drivers/net/dummy.ko +drivers/net/eql.ko +drivers/net/ethernet/8390/8390.ko +drivers/net/ethernet/8390/ne2k-pci.ko +drivers/net/ethernet/amazon/ena/ena.ko +drivers/net/ethernet/amd/pcnet32.ko +drivers/net/ethernet/broadcom/bnx2x/* +drivers/net/ethernet/broadcom/tg3.ko +drivers/net/ethernet/dec/tulip/* +drivers/net/ethernet/emulex/benet/* +drivers/net/ethernet/ibm/* +drivers/net/ethernet/intel/e1000/e1000.ko +drivers/net/ethernet/intel/e1000e/e1000e.ko +drivers/net/ethernet/intel/i40e/* +drivers/net/ethernet/intel/iavf/iavf.ko +drivers/net/ethernet/intel/igb/* +drivers/net/ethernet/intel/igbvf/igbvf.ko +drivers/net/ethernet/intel/ixgbe/* +drivers/net/ethernet/intel/ixgbevf/ixgbevf.ko +drivers/net/ethernet/mellanox/* +drivers/net/ethernet/netronome/nfp/nfp.ko +drivers/net/ethernet/realtek/8139cp.ko +drivers/net/ethernet/realtek/8139too.ko +drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.ko +drivers/net/ethernet/stmicro/stmmac/stmmac-platform.ko +drivers/net/ethernet/stmicro/stmmac/stmmac.ko +drivers/net/fddi/* +drivers/net/geneve.ko +drivers/net/hyperv/hv_netvsc.ko +drivers/net/ifb.ko +drivers/net/ipvlan/* +drivers/net/macvlan.ko +drivers/net/macvtap.ko +drivers/net/mii.ko +drivers/net/netconsole.ko +drivers/net/pcs/pcs-xpcs.ko +drivers/net/phy/marvell.ko +drivers/net/phy/phylink.ko +drivers/net/ppp/* +drivers/net/ppp/bsd_comp.ko +drivers/net/slip/* +drivers/net/veth.ko +drivers/net/virtio_net.ko +drivers/net/vmxnet3/vmxnet3.ko +drivers/net/vxlan.ko +drivers/net/wireguard/wireguard.ko +drivers/net/wwan/* +drivers/net/xen-netback/* +drivers/net/xen-netfront.ko +drivers/nvme/host/nvme.ko +drivers/nvmem/nvmem_core.ko +drivers/parport/parport.ko +drivers/parport/parport_pc.ko +drivers/pci/controller/dwc/pcie-tegra194.ko +drivers/pci/host/vmd.ko +drivers/phy/tegra/phy-tegra194-p2u.ko +drivers/pinctrl/pinctrl-max77620.ko +drivers/platform/x86/pvpanic.ko +drivers/pps/pps_core.ko +drivers/ptp/ptp.ko +drivers/pwm/pwm-tegra.ko +drivers/regulator/fixed.ko +drivers/regulator/max77620-regulator.ko +drivers/rtc/rtc-max77686.ko +drivers/rtc/rtc-tegra.ko +drivers/s390/* +drivers/s390/block/xpram.ko +drivers/scsi/BusLogic.ko +drivers/scsi/aacraid/* +drivers/scsi/cxlflash/* +drivers/scsi/device_handler/scsi_dh_alua.ko +drivers/scsi/device_handler/scsi_dh_emc.ko +drivers/scsi/device_handler/scsi_dh_hp_sw.ko +drivers/scsi/device_handler/scsi_dh_rdac.ko +drivers/scsi/hv_storvsc.ko +drivers/scsi/ibmvscsi/* +drivers/scsi/ipr.ko +drivers/scsi/iscsi_boot_sysfs.ko +drivers/scsi/iscsi_tcp.ko +drivers/scsi/libiscsi.ko +drivers/scsi/libiscsi_tcp.ko +drivers/scsi/libsas/* +drivers/scsi/lpfc/* +drivers/scsi/megaraid/* +drivers/scsi/mpt3sas/* +drivers/scsi/osd/libosd.ko +drivers/scsi/osd/osd.ko +drivers/scsi/qla1280.ko +drivers/scsi/qla2xxx/* +drivers/scsi/raid_class.ko +drivers/scsi/scsi_transport_fc.ko +drivers/scsi/scsi_transport_iscsi.ko +drivers/scsi/scsi_transport_sas.ko +drivers/scsi/scsi_transport_spi.ko +drivers/scsi/sd_mod.ko +drivers/scsi/sr_mod.ko +drivers/scsi/virtio_scsi.ko +drivers/scsi/vmw_pvscsi.ko +drivers/spi/spi-tegra114.ko +drivers/staging/media/tegra-video/tegra-video.ko +drivers/target/loopback/tcm_loop.ko +drivers/target/target_core*.ko +drivers/thermal/tegra/tegra-bpmp-thermal.ko +drivers/tty/serial/jsm/* +drivers/tty/serial/serial-tegra.ko +drivers/uio/uio.ko +drivers/uio/uio_pdrv_genirq.ko +drivers/usb/gadget/udc/tegra-xudc.ko +drivers/usb/host/* +drivers/usb/storage/uas.ko +drivers/usb/storage/usb-storage.ko +drivers/vfio/* +drivers/vhost/* +drivers/video/fbdev/* +drivers/video/vgastate.ko +drivers/virt/vboxguest/vboxguest.ko +drivers/virtio/* +drivers/watchdog/softdog.ko +drivers/xen/* +fs/9p/* +fs/aufs/aufs.ko +fs/autofs/autofs4.ko +fs/binfmt_misc.ko +fs/btrfs/* +fs/cachefiles/cachefiles.ko +fs/ceph/* +fs/smb/* +fs/configfs/* +fs/dlm/dlm.ko +fs/ecryptfs/* +fs/efivarfs/* +fs/erofs/* +fs/exofs/libore.ko +fs/ext4/* +fs/fat/* +fs/fscache/* +fs/fuse/* +fs/isofs/* +fs/lockd/* +fs/nfs/* +fs/nfs_common/* +fs/nfsd/* +fs/nls/nls_cp437.ko +fs/nls/nls_iso8859-1.ko +fs/overlayfs/* +fs/shiftfs.ko +fs/squashfs/* +fs/udf/* +fs/ufs/* +fs/vboxsf/vboxsf.ko +fs/xfs/* +lib/* +net/6lowpan/* +net/802/* +net/8021q/* +net/9p/* +net/appletalk/* +net/atm/* +net/ax25/* +net/bpfilter/* +net/bridge/* +net/can/* +net/ceph/libceph.ko +net/core/* +net/dccp/* +net/decnet/* +net/ieee802154/* +net/ipv4/* +net/ipv6/* +net/ipx/* +net/key/* +net/lapb/* +net/llc/* +net/netfilter/* +net/netlink/netlink_diag.ko +net/netrom/* +net/openvswitch/* +net/packet/af_packet_diag.ko +net/phonet/* +net/rose/* +net/rxrpc/* +net/sched/* +net/sctp/* +net/sunrpc/auth_gss/auth_rpcgss.ko +net/sunrpc/auth_gss/rpcsec_gss_krb5.ko +net/sunrpc/sunrpc.ko +net/tipc/* +net/unix/unix_diag.ko +net/vmw_vsock/* +net/x25/* +net/xfrm/* +! find sound/core -name oss -prune -o -name *.ko -print +sound/drivers/pcsp/snd-pcsp.ko +sound/pci/hda/snd-hda-tegra.ko +sound/pci/snd-ens1370.ko +sound/soc/tegra/snd-soc-tegra186-dspk.ko +sound/soc/tegra/snd-soc-tegra210-admaif.ko +sound/soc/tegra/snd-soc-tegra210-ahub.ko +sound/soc/tegra/snd-soc-tegra210-dmic.ko +sound/soc/tegra/snd-soc-tegra210-i2s.ko +sound/soundcore.ko +ubuntu/ubuntu-host/ubuntu-host.ko diff --git a/debian.qcom-x1e/control.d/vars.qcom-x1e b/debian.qcom-x1e/control.d/vars.qcom-x1e new file mode 100644 index 00000000000000..25438e880eb931 --- /dev/null +++ b/debian.qcom-x1e/control.d/vars.qcom-x1e @@ -0,0 +1,5 @@ +arch="arm64" +supported="Snapdragon X Elite" +target="Geared toward desktop systems." +bootloader="grub-efi-arm64 [arm64]" +provides="kvm-api-4" diff --git a/debian.qcom-x1e/control.stub.in b/debian.qcom-x1e/control.stub.in new file mode 100644 index 00000000000000..9edce15a3af226 --- /dev/null +++ b/debian.qcom-x1e/control.stub.in @@ -0,0 +1,105 @@ +Source: SRCPKGNAME +Section: devel +Priority: optional +Maintainer: Ubuntu Kernel Team +Rules-Requires-Root: no +Standards-Version: 3.9.4.0 +Build-Depends: + autoconf , + automake , + bc , + bindgen:native [amd64 arm64 armhf ppc64el riscv64 s390x], + bison , + clang-19:native [amd64 arm64 armhf ppc64el riscv64 s390x], + cpio, + curl , + debhelper-compat (= 10), + default-jdk-headless:native , + dkms , + flex , + gawk , + java-common , + kmod , + libaudit-dev , + libbpf-dev , + libcap-dev , + libdebuginfod-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libdw-dev , + libelf-dev , + libiberty-dev , + liblzma-dev , + libnewt-dev , + libnl-3-dev, + libnl-genl-3-dev, + libnuma-dev [amd64 arm64 ppc64el s390x] , + libpci-dev , + libssl-dev , + libstdc++-dev, + libtool , + libtraceevent-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libtracefs-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libudev-dev , + libunwind8-dev [amd64 arm64 armhf ppc64el] , + llvm-19-dev, + makedumpfile:native [amd64] , + openssl , + pahole (>= 1.29-2ubuntu2) [amd64 arm64 armhf ppc64el s390x riscv64] | dwarves (>= 1.21) [amd64 arm64 armhf ppc64el s390x riscv64] , + pkg-config , + python3:native , + python3-dev:native , + libpython3-dev , + python3-libfdt, + python3-setuptools, + rsync [!i386] , + rust-src:native [amd64 arm64 armhf ppc64el riscv64 s390x], + rustc:native (>= 1.82) [amd64 arm64 armhf ppc64el riscv64 s390x], + rustfmt:native [amd64 arm64 armhf ppc64el riscv64 s390x], + stubble, + systemd-ukify, + uuid-dev , + zstd , + bpftool:native [amd64 arm64 armhf ppc64el riscv64 s390x] , +Build-Depends-Indep: + asciidoc , + bzip2 , + python3-docutils , + sharutils , + xmlto , +Vcs-Git: git://git.launchpad.net/~ubuntu-kernel/ubuntu/+source/linux/+git/=SERIES= +XS-Testsuite: autopkgtest +#XS-Testsuite-Depends: gcc-4.7 binutils + +Package: SRCPKGNAME-headers-PKGVER-ABINUM +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Header files related to Linux kernel version PKGVER + This package provides kernel header files for version PKGVER, for sites + that want the latest kernel headers. Please read + /usr/share/doc/SRCPKGNAME-headers-PKGVER-ABINUM/debian.README.gz for details + +Package: SRCPKGNAME-tools-PKGVER-ABINUM +Build-Profiles: +Architecture: amd64 armhf arm64 ppc64el s390x +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-tools-common +Description: Linux kernel version specific tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools (such as perf and x86_energy_perf_policy) for + version PKGVER-ABINUM. + You probably want to install linux-tools-PKGVER-ABINUM-. + +Package: SRCPKGNAME-cloud-tools-PKGVER-ABINUM +Build-Profiles: +Architecture: amd64 armhf +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-cloud-tools-common +Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools for cloud tools for version PKGVER-ABINUM. + You probably want to install linux-cloud-tools-PKGVER-ABINUM-. diff --git a/debian.qcom-x1e/dkms-versions b/debian.qcom-x1e/dkms-versions new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/debian.qcom-x1e/modprobe.d/common.conf b/debian.qcom-x1e/modprobe.d/common.conf new file mode 100644 index 00000000000000..e0fbbd6e060d43 --- /dev/null +++ b/debian.qcom-x1e/modprobe.d/common.conf @@ -0,0 +1,3 @@ +# LP:1434842 -- disable OSS drivers by default to allow pulseaudio to emulate +blacklist snd-mixer-oss +blacklist snd-pcm-oss diff --git a/debian.qcom-x1e/reconstruct b/debian.qcom-x1e/reconstruct new file mode 100644 index 00000000000000..ca916d098dabfe --- /dev/null +++ b/debian.qcom-x1e/reconstruct @@ -0,0 +1 @@ +exit 0 diff --git a/debian.qcom-x1e/rules.d/arm64.mk b/debian.qcom-x1e/rules.d/arm64.mk new file mode 100644 index 00000000000000..7e27373dbeca8e --- /dev/null +++ b/debian.qcom-x1e/rules.d/arm64.mk @@ -0,0 +1,23 @@ +build_arch = arm64 +defconfig = defconfig +flavours = qcom-x1e +build_image = vmlinuz.efi +kernel_file = arch/$(build_arch)/boot/vmlinuz.efi +install_file = vmlinuz +no_dumpfile = true + +vdso = vdso_install + +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_rtla = true + +do_dtbs = true +do_stubble = true +do_skip_checks = false +do_zfs = true + diff --git a/debian/.gitignore b/debian/.gitignore new file mode 100644 index 00000000000000..f1c9199e836c00 --- /dev/null +++ b/debian/.gitignore @@ -0,0 +1,15 @@ +/*.postinst +/*.postrm +/*.preinst +/*.prerm +/*.substvars +/*.triggers +/build/ +/canonical-certs.pem +/canonical-revoked-certs.pem +/changelog +/control +/files +/linux-*/ +/stamps/ +/tmp-headers/ diff --git a/debian/certs/canonical-livepatch-2025-all.pem b/debian/certs/canonical-livepatch-2025-all.pem new file mode 100644 index 00000000000000..e08cc784d021f5 --- /dev/null +++ b/debian/certs/canonical-livepatch-2025-all.pem @@ -0,0 +1,125 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + 47:77:26:6d:ae:6c:57:73:eb:80:e2:96:dd:26:93:ff:e9:f5:62:5d + Signature Algorithm: sha512WithRSAEncryption + Issuer: CN=Canonical Ltd. Live Patch Signing 2025 Kmod + Validity + Not Before: May 16 09:07:40 2025 GMT + Not After : May 16 09:07:40 2050 GMT + Subject: CN=Canonical Ltd. Live Patch Signing 2025 Kmod + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (4096 bit) + Modulus: + 00:b8:a9:03:47:2e:7b:c6:86:16:f4:b7:a8:4d:3b: + 05:f6:c4:75:35:e9:22:8a:4e:40:06:89:15:7f:ad: + 99:bb:e6:90:93:61:c8:16:cf:2e:00:1b:81:36:fd: + cc:31:7b:97:79:8d:5e:d2:4d:d3:2f:ab:35:2d:74: + 48:98:b3:d9:75:f9:bb:e1:f2:3f:6b:6d:dc:e4:bb: + ee:f5:aa:f7:8a:8c:7a:a8:0b:df:b1:f8:d6:04:13: + 27:e9:1a:aa:c2:4d:d2:35:3a:bc:06:d7:83:7f:e8: + c4:1c:63:8b:3a:ff:0e:0b:89:6e:4f:5f:ea:ad:78: + df:37:ab:f9:55:1d:fb:6e:29:a4:22:43:d1:9b:12: + 1e:b2:84:23:1b:d2:38:91:b8:a8:6c:1c:59:3c:ff: + 4c:a9:18:ce:d0:7f:1d:ef:04:cf:8a:e8:29:b2:4b: + 68:0d:92:32:bc:9c:5d:8f:0a:d1:dd:4d:25:ba:3a: + 8c:6a:48:5b:1e:9c:01:10:99:c1:a7:34:ee:68:ec: + a1:d3:26:be:45:c8:b4:97:ac:8a:aa:7e:13:a6:e5: + 43:f1:1b:3f:a1:80:0a:d2:a9:e7:f2:77:ca:e1:f5: + 29:36:df:75:8a:7e:02:d6:17:aa:46:12:b9:51:f0: + 6b:ca:22:f8:05:de:d6:02:47:76:0c:88:f1:c6:90: + 44:99:58:71:c7:62:1e:2b:94:c5:2b:8e:dc:ca:7b: + a7:bd:cd:38:8f:4e:73:6d:b0:9b:4e:7c:12:1f:5c: + c5:62:d6:82:c6:d2:78:09:52:dc:d7:78:2e:23:d0: + 63:1f:7d:77:91:c8:3f:66:7a:20:8a:cf:70:09:0f: + a2:c0:82:a5:42:d9:be:dc:5f:78:73:f7:fa:3c:70: + 47:7b:39:77:89:5a:6f:ef:83:09:c9:1b:21:53:89: + 7c:10:bf:99:9c:05:39:32:1e:84:3b:a5:84:7e:ef: + 08:6d:b0:b0:31:61:d6:1a:aa:dd:7a:d6:10:02:e6: + 72:02:e5:40:bf:07:b9:cd:61:d1:55:04:9a:cd:02: + 73:41:c1:df:20:30:12:97:ca:a1:83:1a:97:8a:92: + 1c:47:5c:0a:60:da:41:3b:e6:0e:2c:82:ce:45:65: + 81:ba:45:a1:66:cc:ef:ab:65:5c:e5:a8:0c:86:dd: + fc:86:54:f3:37:7c:89:a9:0c:fa:3a:da:82:c9:90: + 99:1e:1d:66:44:de:d3:c5:d4:0b:da:15:f8:d8:d4: + 63:2b:4e:6f:24:e9:c2:d7:74:9c:29:91:9f:25:39: + 8d:77:15:8c:cb:8e:ad:e3:80:0a:ea:79:04:72:9d: + 51:01:18:ae:35:51:ef:95:79:38:c4:db:99:50:47: + 62:38:e9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + D5:41:CE:F6:1D:C7:E7:93:B7:EB:7E:89:99:70:A2:EE:F0:B5:DC:8C + X509v3 Authority Key Identifier: + D5:41:CE:F6:1D:C7:E7:93:B7:EB:7E:89:99:70:A2:EE:F0:B5:DC:8C + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.2312.16.1.2 + Signature Algorithm: sha512WithRSAEncryption + Signature Value: + 40:9d:5b:70:66:fe:9c:99:eb:ed:78:61:be:da:67:da:ac:80: + a8:c2:78:91:f8:90:11:be:9f:6a:e7:bf:79:dc:11:0c:c7:83: + e8:13:c4:1c:b6:fe:f0:e7:7d:1a:12:97:5d:19:56:9c:10:12: + 1e:b9:19:88:30:95:c4:3b:2f:aa:91:6f:c1:9e:68:4a:f4:5c: + ef:a1:51:b5:a3:9b:58:3f:e2:ae:5c:29:a6:c4:30:fd:65:0b: + cc:8c:99:95:33:61:c6:07:fa:c3:bd:1a:57:80:e5:43:97:2e: + f3:5c:d6:1e:b7:23:9f:58:10:19:24:46:9e:f8:fd:2c:8e:88: + e7:ec:ef:15:4b:7a:6a:ce:b0:25:c0:01:c5:21:83:1a:d5:89: + 0c:90:86:ad:d4:3e:6e:28:bf:6c:21:91:ff:b9:a9:ef:d4:ac: + de:7c:67:c1:e4:ed:75:26:15:ff:5d:67:39:24:2d:15:57:21: + 09:76:e5:85:f3:45:e8:bf:b1:c0:39:2b:83:34:1a:f5:3f:1f: + ae:07:8c:82:1f:d4:dc:95:c0:4e:f3:7f:ac:db:8f:2c:db:a4: + d4:2a:4c:8c:de:e6:5b:84:fc:df:a3:74:d8:dc:9c:93:1f:5b: + c9:33:b5:b3:7d:2b:a4:4d:7a:bb:73:92:ff:8d:e9:9e:c7:a7: + d2:0d:83:bb:2c:2f:47:51:15:5c:6d:db:9a:d3:9e:6e:25:90: + 01:e6:09:bd:a2:d0:1e:cf:a3:12:22:0d:56:70:bf:89:e4:be: + 62:76:9c:d9:f5:c8:01:55:95:02:57:a1:67:59:88:97:57:f6: + bb:8d:c9:40:d5:e3:60:4f:43:dd:49:90:fa:a5:6d:08:96:b2: + 4d:dd:a7:c6:e3:5c:06:ba:af:8c:30:9d:d5:a5:b0:ab:c4:e5: + f3:09:47:05:ba:9b:46:f4:26:70:3b:fa:da:a5:0a:47:ce:be: + 43:87:eb:73:63:3b:cd:41:7a:78:a0:f6:7d:c5:37:fb:bb:26: + 3b:b3:e7:44:49:06:8c:14:03:fc:b3:46:54:3b:0d:57:02:08: + 99:79:68:a2:9c:62:95:4d:ac:8e:19:43:4e:8f:2d:52:fa:91: + ca:78:06:a2:b7:a3:66:6d:67:0b:13:ee:b1:01:38:e0:7c:ac: + 9a:16:27:36:f1:45:83:5d:eb:d6:cd:65:3f:56:9a:d3:56:c4: + 15:55:b2:64:ca:13:cb:31:1e:7e:03:85:68:61:40:02:99:4b: + 25:01:68:8d:97:cc:39:1a:54:1b:e5:51:38:8e:ce:66:74:61: + 5e:87:f4:31:7d:0d:be:9d:01:e1:b3:5c:bc:1a:d0:ea:5e:b2: + c8:ee:97:34:bc:9f:bb:98 +-----BEGIN CERTIFICATE----- +MIIFejCCA2KgAwIBAgIUR3cmba5sV3PrgOKW3SaT/+n1Yl0wDQYJKoZIhvcNAQEN +BQAwNjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTGl2ZSBQYXRjaCBTaWduaW5n +IDIwMjUgS21vZDAgFw0yNTA1MTYwOTA3NDBaGA8yMDUwMDUxNjA5MDc0MFowNjE0 +MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTGl2ZSBQYXRjaCBTaWduaW5nIDIwMjUg +S21vZDCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBALipA0cue8aGFvS3 +qE07BfbEdTXpIopOQAaJFX+tmbvmkJNhyBbPLgAbgTb9zDF7l3mNXtJN0y+rNS10 +SJiz2XX5u+HyP2tt3OS77vWq94qMeqgL37H41gQTJ+kaqsJN0jU6vAbXg3/oxBxj +izr/DguJbk9f6q143zer+VUd+24ppCJD0ZsSHrKEIxvSOJG4qGwcWTz/TKkYztB/ +He8Ez4roKbJLaA2SMrycXY8K0d1NJbo6jGpIWx6cARCZwac07mjsodMmvkXItJes +iqp+E6blQ/EbP6GACtKp5/J3yuH1KTbfdYp+AtYXqkYSuVHwa8oi+AXe1gJHdgyI +8caQRJlYccdiHiuUxSuO3Mp7p73NOI9Oc22wm058Eh9cxWLWgsbSeAlS3Nd4LiPQ +Yx99d5HIP2Z6IIrPcAkPosCCpULZvtxfeHP3+jxwR3s5d4lab++DCckbIVOJfBC/ +mZwFOTIehDulhH7vCG2wsDFh1hqq3XrWEALmcgLlQL8Huc1h0VUEms0Cc0HB3yAw +EpfKoYMal4qSHEdcCmDaQTvmDiyCzkVlgbpFoWbM76tlXOWoDIbd/IZU8zd8iakM ++jragsmQmR4dZkTe08XUC9oV+NjUYytObyTpwtd0nCmRnyU5jXcVjMuOreOACup5 +BHKdUQEYrjVR75V5OMTbmVBHYjjpAgMBAAGjfjB8MAwGA1UdEwEB/wQCMAAwCwYD +VR0PBAQDAgeAMB0GA1UdDgQWBBTVQc72Hcfnk7frfomZcKLu8LXcjDAfBgNVHSME +GDAWgBTVQc72Hcfnk7frfomZcKLu8LXcjDAfBgNVHSUEGDAWBggrBgEFBQcDAwYK +KwYBBAGSCBABAjANBgkqhkiG9w0BAQ0FAAOCAgEAQJ1bcGb+nJnr7Xhhvtpn2qyA +qMJ4kfiQEb6faue/edwRDMeD6BPEHLb+8Od9GhKXXRlWnBASHrkZiDCVxDsvqpFv +wZ5oSvRc76FRtaObWD/irlwppsQw/WULzIyZlTNhxgf6w70aV4DlQ5cu81zWHrcj +n1gQGSRGnvj9LI6I5+zvFUt6as6wJcABxSGDGtWJDJCGrdQ+bii/bCGR/7mp79Ss +3nxnweTtdSYV/11nOSQtFVchCXblhfNF6L+xwDkrgzQa9T8frgeMgh/U3JXATvN/ +rNuPLNuk1CpMjN7mW4T836N02Nyckx9byTO1s30rpE16u3OS/43pnsen0g2Duywv +R1EVXG3bmtOebiWQAeYJvaLQHs+jEiINVnC/ieS+Ynac2fXIAVWVAlehZ1mIl1f2 +u43JQNXjYE9D3UmQ+qVtCJayTd2nxuNcBrqvjDCd1aWwq8Tl8wlHBbqbRvQmcDv6 +2qUKR86+Q4frc2M7zUF6eKD2fcU3+7smO7PnREkGjBQD/LNGVDsNVwIImXloopxi +lU2sjhlDTo8tUvqRyngGorejZm1nCxPusQE44HysmhYnNvFFg13r1s1lP1aa01bE +FVWyZMoTyzEefgOFaGFAAplLJQFojZfMORpUG+VROI7OZnRhXof0MX0Nvp0B4bNc +vBrQ6l6yyO6XNLyfu5g= +-----END CERTIFICATE----- diff --git a/debian/certs/canonical-livepatch-all.pem b/debian/certs/canonical-livepatch-all.pem new file mode 100644 index 00000000000000..3f360f74344d84 --- /dev/null +++ b/debian/certs/canonical-livepatch-all.pem @@ -0,0 +1,121 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + c7:7e:51:6a:1c:25:cd:40 + Signature Algorithm: sha512WithRSAEncryption + Issuer: CN = Canonical Ltd. Live Patch Signing + Validity + Not Before: Jul 18 23:41:27 2016 GMT + Not After : Jul 16 23:41:27 2026 GMT + Subject: CN = Canonical Ltd. Live Patch Signing + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + RSA Public-Key: (4096 bit) + Modulus: + 00:bd:74:ee:72:b3:4a:ab:e6:31:e8:29:24:c2:bd: + 46:98:32:c0:39:ee:a3:fb:8a:ad:fe:ab:1a:5b:a3: + 2e:a1:80:db:79:61:9e:47:79:2c:75:57:a2:21:f0: + 93:f6:87:f2:9b:4b:9d:2f:b3:58:61:28:3c:41:70: + 13:16:a1:72:90:c9:d5:16:71:7c:e0:30:f9:28:5e: + 48:20:36:00:69:b7:59:9f:a3:ec:a8:eb:55:41:9f: + 38:1e:22:4a:57:20:f4:83:59:49:c5:00:93:d3:33: + 02:92:d1:fc:f0:84:3b:4a:5b:8f:b6:73:9a:89:fa: + 30:1e:e6:2a:68:f2:91:ef:59:57:3d:dc:1c:52:6f: + 5e:e6:9b:b5:b8:7c:98:c9:13:d1:39:68:01:67:91: + e0:d3:67:72:16:0a:5e:16:83:45:31:4f:b5:2b:b3: + f6:40:86:89:3a:84:6e:6f:16:61:bc:70:84:be:5a: + 13:36:7b:82:ea:07:19:fc:18:c1:16:c6:32:0b:7d: + 2c:6b:c4:21:b9:38:6b:31:dc:d9:0c:ad:56:40:68: + 7c:e3:c6:64:8e:bf:1c:e0:72:3e:6c:db:d2:73:79: + da:d7:c5:2f:5d:04:7d:b0:07:1e:95:dd:2a:47:5e: + bf:3e:3a:c8:66:f6:67:0f:d4:2a:f1:e2:71:59:d2: + 6c:7b:a0:37:ac:e6:97:80:30:13:97:48:d5:74:fc: + 38:68:e4:57:cb:99:69:5a:84:27:ac:98:51:e4:64: + bd:91:62:e8:58:27:06:2a:b9:0b:b8:08:e5:e5:b4: + 51:a7:a2:10:df:4e:07:6c:a0:3b:96:f2:6e:df:75: + 8c:97:1e:64:a0:9a:86:9b:98:26:f9:d8:b7:de:5b: + 21:b7:af:89:01:a3:f7:98:6b:da:19:ba:86:ef:ef: + f1:ce:bb:2f:89:ed:c0:b6:1b:e5:5b:f8:90:11:9a: + 52:93:e9:be:f7:35:b9:08:cb:ba:c3:ed:2f:73:af: + cc:96:07:55:b5:de:f6:03:f6:f1:89:f9:21:40:76: + c1:69:f2:61:cc:9a:94:df:9c:ec:6a:65:38:be:d1: + 4e:2a:87:c7:2f:3e:53:ae:8b:9f:54:a1:09:59:64: + 25:aa:a9:d8:44:a9:a8:a0:71:e1:32:aa:4c:32:fd: + 44:28:cc:9c:6f:8e:db:81:7e:6f:fa:00:56:c5:e5: + 03:46:63:fb:8e:71:8d:e3:13:91:9f:ac:60:3e:64: + f3:df:25:34:09:fa:2d:96:9f:16:05:ea:93:f5:e6: + 00:08:27:32:7b:3c:bd:ee:70:24:6c:3b:55:e9:db: + f4:10:2d:20:06:b4:ca:e9:29:65:55:ad:f6:52:54: + 5f:e5:a3 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + 14:DF:34:D1:A8:7C:F3:76:25:AB:EC:03:9E:F2:BF:52:12:49:B9:69 + X509v3 Authority Key Identifier: + keyid:14:DF:34:D1:A8:7C:F3:76:25:AB:EC:03:9E:F2:BF:52:12:49:B9:69 + + Signature Algorithm: sha512WithRSAEncryption + 30:e7:48:02:37:e9:28:cf:04:a2:4d:5c:fa:d8:4e:c9:76:c7: + 14:3f:bd:2c:51:3d:33:f0:1a:bc:49:f1:47:95:8f:69:d8:a9: + 54:14:44:6c:4d:9f:55:82:08:1e:c6:5b:d5:91:d9:bc:2e:b0: + af:d6:25:65:74:96:aa:36:de:ae:31:a8:11:f2:a4:2c:5a:e1: + 4f:73:f8:4a:c3:35:b0:76:96:71:f2:b5:7d:4b:75:ee:5d:bf: + 86:a5:ba:0b:a9:52:cb:ec:ab:e5:23:4b:f2:74:55:28:17:1e: + b3:ac:27:ad:45:13:6e:69:b3:5a:be:42:36:29:48:db:e7:5c: + 22:58:a0:90:82:2c:2a:21:2b:db:f4:64:b7:91:5d:1f:2c:48: + a4:1a:85:e3:86:a5:aa:19:cd:19:e8:a5:fb:a3:7b:94:77:48: + 25:a4:cf:a0:cf:71:82:5c:6f:71:22:7c:d6:97:a0:53:bb:ec: + 30:f6:cb:16:fb:7b:fd:16:94:7a:53:6e:bd:04:64:a2:01:10: + 9f:f0:5b:b5:a6:73:41:9d:5f:6f:45:73:0d:05:f7:30:6d:39: + 90:b6:7d:55:7d:4c:2f:ae:5f:38:56:2f:8b:df:f4:bf:12:06: + 93:6e:0d:02:23:bf:71:91:57:88:e8:bd:62:72:99:00:40:29: + 1e:c9:13:11:da:7e:8e:e1:d2:a5:0d:bf:f7:d6:ec:01:0d:89: + 41:cd:d5:dc:d2:f7:5f:33:0d:4c:2f:85:b7:85:b7:81:e4:17: + 29:f0:74:cf:0e:15:8c:1a:50:0b:08:63:1a:91:4f:e7:76:97: + f1:d4:3b:7e:72:d4:c5:45:58:0c:6a:e9:0d:f2:85:d8:91:1e: + 37:bd:78:e3:39:4d:2e:fd:85:31:c1:a6:3b:6a:cc:2c:53:72: + 1d:8e:7b:f0:e6:76:86:09:6f:1a:f3:e4:a1:e2:dd:76:5f:b0: + 8c:e2:2a:54:5d:c1:88:49:90:10:15:42:7d:05:24:53:8c:54: + ff:48:18:1a:36:e3:31:d3:54:32:78:0d:fe:f2:3d:aa:0d:37: + 15:84:b4:36:47:31:e8:85:6e:0b:58:38:ff:21:91:09:c9:a8: + 43:a3:ea:60:cb:7e:ed:f7:41:6f:4e:91:c1:fd:77:46:e7:d4: + e7:86:c0:1b:fd:50:6c:aa:be:00:b3:63:02:ff:4e:c7:a5:57: + 6e:29:64:e9:54:d5:30:63:38:5f:2d:5a:db:49:5f:14:14:22: + d2:81:1f:61:9e:ee:ee:16:66:d6:bc:bd:ac:1b:5c:fb:38:31: + 95:33:2e:84:6e:7a:de:ee:b9:fc:97:17:06:13:bf:70:1c:6e: + 76:ed:66:38:e2:70:08:00 +-----BEGIN CERTIFICATE----- +MIIFODCCAyCgAwIBAgIJAMd+UWocJc1AMA0GCSqGSIb3DQEBDQUAMCwxKjAoBgNV +BAMMIUNhbm9uaWNhbCBMdGQuIExpdmUgUGF0Y2ggU2lnbmluZzAeFw0xNjA3MTgy +MzQxMjdaFw0yNjA3MTYyMzQxMjdaMCwxKjAoBgNVBAMMIUNhbm9uaWNhbCBMdGQu +IExpdmUgUGF0Y2ggU2lnbmluZzCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoC +ggIBAL107nKzSqvmMegpJMK9RpgywDnuo/uKrf6rGlujLqGA23lhnkd5LHVXoiHw +k/aH8ptLnS+zWGEoPEFwExahcpDJ1RZxfOAw+SheSCA2AGm3WZ+j7KjrVUGfOB4i +Slcg9INZScUAk9MzApLR/PCEO0pbj7Zzmon6MB7mKmjyke9ZVz3cHFJvXuabtbh8 +mMkT0TloAWeR4NNnchYKXhaDRTFPtSuz9kCGiTqEbm8WYbxwhL5aEzZ7guoHGfwY +wRbGMgt9LGvEIbk4azHc2QytVkBofOPGZI6/HOByPmzb0nN52tfFL10EfbAHHpXd +Kkdevz46yGb2Zw/UKvHicVnSbHugN6zml4AwE5dI1XT8OGjkV8uZaVqEJ6yYUeRk +vZFi6FgnBiq5C7gI5eW0UaeiEN9OB2ygO5bybt91jJceZKCahpuYJvnYt95bIbev +iQGj95hr2hm6hu/v8c67L4ntwLYb5Vv4kBGaUpPpvvc1uQjLusPtL3OvzJYHVbXe +9gP28Yn5IUB2wWnyYcyalN+c7GplOL7RTiqHxy8+U66Ln1ShCVlkJaqp2ESpqKBx +4TKqTDL9RCjMnG+O24F+b/oAVsXlA0Zj+45xjeMTkZ+sYD5k898lNAn6LZafFgXq +k/XmAAgnMns8ve5wJGw7Venb9BAtIAa0yukpZVWt9lJUX+WjAgMBAAGjXTBbMAwG +A1UdEwEB/wQCMAAwCwYDVR0PBAQDAgeAMB0GA1UdDgQWBBQU3zTRqHzzdiWr7AOe +8r9SEkm5aTAfBgNVHSMEGDAWgBQU3zTRqHzzdiWr7AOe8r9SEkm5aTANBgkqhkiG +9w0BAQ0FAAOCAgEAMOdIAjfpKM8Eok1c+thOyXbHFD+9LFE9M/AavEnxR5WPadip +VBREbE2fVYIIHsZb1ZHZvC6wr9YlZXSWqjberjGoEfKkLFrhT3P4SsM1sHaWcfK1 +fUt17l2/hqW6C6lSy+yr5SNL8nRVKBces6wnrUUTbmmzWr5CNilI2+dcIligkIIs +KiEr2/Rkt5FdHyxIpBqF44alqhnNGeil+6N7lHdIJaTPoM9xglxvcSJ81pegU7vs +MPbLFvt7/RaUelNuvQRkogEQn/BbtaZzQZ1fb0VzDQX3MG05kLZ9VX1ML65fOFYv +i9/0vxIGk24NAiO/cZFXiOi9YnKZAEApHskTEdp+juHSpQ2/99bsAQ2JQc3V3NL3 +XzMNTC+Ft4W3geQXKfB0zw4VjBpQCwhjGpFP53aX8dQ7fnLUxUVYDGrpDfKF2JEe +N7144zlNLv2FMcGmO2rMLFNyHY578OZ2hglvGvPkoeLddl+wjOIqVF3BiEmQEBVC +fQUkU4xU/0gYGjbjMdNUMngN/vI9qg03FYS0Nkcx6IVuC1g4/yGRCcmoQ6PqYMt+ +7fdBb06Rwf13RufU54bAG/1QbKq+ALNjAv9Ox6VXbilk6VTVMGM4Xy1a20lfFBQi +0oEfYZ7u7hZm1ry9rBtc+zgxlTMuhG563u65/JcXBhO/cBxudu1mOOJwCAA= +-----END CERTIFICATE----- diff --git a/debian/certs/ubuntu-drivers-2025-all.pem b/debian/certs/ubuntu-drivers-2025-all.pem new file mode 100644 index 00000000000000..04af6bd7f2aead --- /dev/null +++ b/debian/certs/ubuntu-drivers-2025-all.pem @@ -0,0 +1,125 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + 2c:af:80:6d:b1:e0:8b:9f:49:90:7b:b2:39:4e:b3:c7:88:0e:44:53 + Signature Algorithm: sha512WithRSAEncryption + Issuer: CN=Canonical Ltd. Kernel Module Signing 2025 Kmod + Validity + Not Before: Nov 21 12:32:19 2025 GMT + Not After : Nov 21 12:32:19 2050 GMT + Subject: CN=Canonical Ltd. Kernel Module Signing 2025 Kmod + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (4096 bit) + Modulus: + 00:9e:20:bd:0d:2d:bd:af:fe:e2:68:a3:8e:fe:2b: + 50:21:08:03:3a:32:71:d5:35:ac:d0:0a:07:ae:f4: + dc:a2:8d:2f:c6:0d:2a:6b:ac:ef:84:72:d5:df:91: + 52:cf:76:01:b3:29:e1:ba:9f:5b:9f:f0:92:b7:03: + 65:80:ca:d0:aa:6d:26:28:07:8b:2c:19:9e:87:e9: + 5f:58:5c:aa:ad:3c:be:71:3a:2d:d6:79:72:23:7e: + bf:f3:39:48:c6:d0:2f:7f:c2:79:0e:35:51:c9:4f: + e9:bf:80:06:75:5e:76:30:c0:96:83:4a:79:f3:3a: + 9e:30:e5:0e:9d:b6:86:c3:7c:6a:eb:4d:4c:5c:0b: + e1:a8:48:b2:e4:f4:62:64:55:7b:f0:5b:10:15:07: + 51:89:e4:98:7e:7b:58:c0:38:dc:03:7e:ba:1a:0e: + c2:12:b0:1e:93:f1:dc:7d:8f:85:7d:d0:7f:d6:ef: + e6:6c:90:03:d9:85:a5:a1:43:20:af:b1:89:75:d4: + e7:af:63:b1:ba:0d:a3:a4:5e:29:a4:5c:f0:bf:9a: + c8:7e:c3:da:60:d4:ae:ad:13:3f:cc:4b:64:73:3d: + 59:3f:8b:91:7f:8c:fe:e6:4b:2f:e3:04:2b:e3:ae: + 0d:6f:8b:55:b9:e9:1b:67:37:25:9d:43:d3:70:b5: + 01:e8:d9:de:11:9a:b8:c9:5b:ba:b0:0c:6a:9f:9b: + fe:79:e3:a9:27:90:1d:56:95:84:8b:eb:96:a1:47: + 83:28:3c:d0:ea:81:7e:fe:a2:90:3d:84:02:5e:bc: + 68:0b:70:69:36:18:32:53:e3:4a:e1:c5:0d:dc:d6: + cd:3f:c0:1a:27:28:db:96:0a:ce:01:03:0d:8e:9e: + 38:e1:04:85:38:ad:f7:1f:10:40:b5:b1:d5:85:bd: + e6:62:b1:3c:f0:ac:8f:8a:88:62:46:cc:bf:64:9b: + e7:b6:c0:68:3e:96:14:54:6c:76:08:8d:6a:fd:08: + 4b:8e:0b:0e:ca:84:8a:17:60:fb:12:c7:f2:27:49: + 9b:b8:ff:a9:3f:70:5f:98:51:be:96:f1:0d:bf:1d: + 0e:c3:c7:34:5e:b3:35:e7:ff:43:e4:0e:7a:86:08: + d6:13:a6:6f:48:4a:d6:f5:61:cb:ba:29:e6:54:ac: + c9:c0:32:5e:fe:72:b2:e1:c4:e4:d9:ec:6a:1e:f2: + 5f:cc:db:44:30:42:79:ca:c8:d1:86:28:3b:3a:50: + d0:71:81:5f:ab:fb:f1:2f:65:df:8e:a4:7c:96:5c: + 46:c3:fc:b0:fd:3d:b1:38:cf:85:15:a6:da:ce:a9: + a3:b0:76:6a:4b:8a:4c:25:ce:c2:3d:fc:01:11:24: + 1d:c7:f9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + 46:27:60:3D:23:57:A2:A3:F8:10:06:37:08:94:C2:21:17:58:93:E9 + X509v3 Authority Key Identifier: + 46:27:60:3D:23:57:A2:A3:F8:10:06:37:08:94:C2:21:17:58:93:E9 + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.2312.16.1.2 + Signature Algorithm: sha512WithRSAEncryption + Signature Value: + 21:a6:29:45:48:fc:42:37:12:b8:71:af:06:9e:2a:63:91:19: + 7b:52:a5:c9:2a:63:66:36:94:3f:2b:ac:f7:01:7e:04:48:92: + 7c:33:66:94:c8:c0:c3:1e:a4:f4:10:d2:4a:67:1a:10:64:15: + dd:70:86:8c:4d:ef:a9:c2:09:bc:44:9b:83:06:7c:ce:b3:2f: + 09:9f:32:51:dd:f9:e6:87:96:c7:3f:08:e1:8f:ed:4d:b0:39: + 02:9c:c0:86:40:28:56:59:5c:1d:11:af:a8:ad:49:e8:91:a0: + 31:a2:e8:c4:5e:88:c4:31:c3:d4:6f:3f:5a:94:c7:6e:b8:2a: + 74:27:90:12:c6:1f:35:87:32:31:e9:38:14:d9:09:c3:42:e6: + e7:f7:8f:46:22:a1:c9:12:0c:34:1a:7c:d0:6b:e5:c7:42:49: + 3f:7d:c9:bb:38:65:e3:93:16:1b:ae:48:6c:29:53:ec:1a:a0: + 75:3f:3e:e4:a7:30:59:79:e7:8d:4b:76:06:8d:f5:4b:97:06: + 0a:af:0e:0b:7b:37:8c:9d:86:3d:92:40:cf:2d:87:ca:5c:66: + 01:9b:bd:42:99:5c:4b:39:91:0e:8f:db:d3:2b:57:fe:4a:17: + a0:10:17:e4:39:f1:a1:28:1b:51:53:9c:cf:95:4e:23:55:e3: + 24:2b:2e:dc:ed:cb:9c:1a:fb:64:f6:05:be:c4:71:70:62:af: + 52:2d:64:9f:4b:f0:87:5d:5d:53:8d:41:2e:6a:81:2a:e2:fb: + 55:89:7d:70:93:eb:59:61:b1:f7:75:64:0e:6c:f7:eb:b9:d4: + 83:08:20:29:9c:03:0b:5b:d5:8f:de:4e:bd:e0:d9:c2:c5:01: + 03:9d:a5:3a:db:2b:f2:32:89:67:0e:ec:32:a4:74:bd:fb:f8: + 0e:b4:cf:cd:5e:49:bb:02:2d:d1:0c:3d:2f:d7:22:e4:89:4c: + 6a:3c:e5:ce:6d:21:68:7e:74:2e:35:5e:3b:9a:44:3b:a5:54: + 9a:3c:be:df:5d:e2:f6:dd:1c:bd:f8:05:99:82:2f:16:4d:6e: + f6:37:8b:77:3f:81:2f:10:a6:4c:04:67:a4:58:34:0d:5d:6f: + e4:2a:c4:c2:be:00:f1:8e:8b:85:98:77:48:8a:47:21:2e:ff: + cc:55:6d:8c:f2:ec:3e:14:75:a5:7d:0c:24:40:b6:54:49:30: + 84:1a:62:b2:19:60:42:3c:a4:3f:bc:fc:21:f6:1d:19:83:cc: + f8:cb:08:2a:15:49:c8:35:8f:bd:14:c3:22:92:c9:5b:84:88: + 50:01:db:10:08:4b:24:08:00:c4:60:76:be:e8:62:e2:0c:bd: + 9a:28:3c:70:86:9c:dd:94 +-----BEGIN CERTIFICATE----- +MIIFgDCCA2igAwIBAgIULK+AbbHgi59JkHuyOU6zx4gORFMwDQYJKoZIhvcNAQEN +BQAwOTE3MDUGA1UEAwwuQ2Fub25pY2FsIEx0ZC4gS2VybmVsIE1vZHVsZSBTaWdu +aW5nIDIwMjUgS21vZDAgFw0yNTExMjExMjMyMTlaGA8yMDUwMTEyMTEyMzIxOVow +OTE3MDUGA1UEAwwuQ2Fub25pY2FsIEx0ZC4gS2VybmVsIE1vZHVsZSBTaWduaW5n +IDIwMjUgS21vZDCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAJ4gvQ0t +va/+4mijjv4rUCEIAzoycdU1rNAKB6703KKNL8YNKmus74Ry1d+RUs92AbMp4bqf +W5/wkrcDZYDK0KptJigHiywZnofpX1hcqq08vnE6LdZ5ciN+v/M5SMbQL3/CeQ41 +UclP6b+ABnVedjDAloNKefM6njDlDp22hsN8autNTFwL4ahIsuT0YmRVe/BbEBUH +UYnkmH57WMA43AN+uhoOwhKwHpPx3H2PhX3Qf9bv5myQA9mFpaFDIK+xiXXU569j +sboNo6ReKaRc8L+ayH7D2mDUrq0TP8xLZHM9WT+LkX+M/uZLL+MEK+OuDW+LVbnp +G2c3JZ1D03C1AejZ3hGauMlburAMap+b/nnjqSeQHVaVhIvrlqFHgyg80OqBfv6i +kD2EAl68aAtwaTYYMlPjSuHFDdzWzT/AGico25YKzgEDDY6eOOEEhTit9x8QQLWx +1YW95mKxPPCsj4qIYkbMv2Sb57bAaD6WFFRsdgiNav0IS44LDsqEihdg+xLH8idJ +m7j/qT9wX5hRvpbxDb8dDsPHNF6zNef/Q+QOeoYI1hOmb0hK1vVhy7op5lSsycAy +Xv5ysuHE5Nnsah7yX8zbRDBCecrI0YYoOzpQ0HGBX6v78S9l346kfJZcRsP8sP09 +sTjPhRWm2s6po7B2akuKTCXOwj38AREkHcf5AgMBAAGjfjB8MAwGA1UdEwEB/wQC +MAAwCwYDVR0PBAQDAgeAMB0GA1UdDgQWBBRGJ2A9I1eio/gQBjcIlMIhF1iT6TAf +BgNVHSMEGDAWgBRGJ2A9I1eio/gQBjcIlMIhF1iT6TAfBgNVHSUEGDAWBggrBgEF +BQcDAwYKKwYBBAGSCBABAjANBgkqhkiG9w0BAQ0FAAOCAgEAIaYpRUj8QjcSuHGv +Bp4qY5EZe1KlySpjZjaUPyus9wF+BEiSfDNmlMjAwx6k9BDSSmcaEGQV3XCGjE3v +qcIJvESbgwZ8zrMvCZ8yUd355oeWxz8I4Y/tTbA5ApzAhkAoVllcHRGvqK1J6JGg +MaLoxF6IxDHD1G8/WpTHbrgqdCeQEsYfNYcyMek4FNkJw0Lm5/ePRiKhyRIMNBp8 +0Gvlx0JJP33Juzhl45MWG65IbClT7BqgdT8+5KcwWXnnjUt2Bo31S5cGCq8OC3s3 +jJ2GPZJAzy2HylxmAZu9QplcSzmRDo/b0ytX/koXoBAX5DnxoSgbUVOcz5VOI1Xj +JCsu3O3LnBr7ZPYFvsRxcGKvUi1kn0vwh11dU41BLmqBKuL7VYl9cJPrWWGx93Vk +Dmz367nUgwggKZwDC1vVj95OveDZwsUBA52lOtsr8jKJZw7sMqR0vfv4DrTPzV5J +uwIt0Qw9L9ci5IlMajzlzm0haH50LjVeO5pEO6VUmjy+313i9t0cvfgFmYIvFk1u +9jeLdz+BLxCmTARnpFg0DV1v5CrEwr4A8Y6LhZh3SIpHIS7/zFVtjPLsPhR1pX0M +JEC2VEkwhBpishlgQjykP7z8IfYdGYPM+MsIKhVJyDWPvRTDIpLJW4SIUAHbEAhL +JAgAxGB2vuhi4gy9mig8cIac3ZQ= +-----END CERTIFICATE----- diff --git a/debian/certs/ubuntu-drivers-all.pem b/debian/certs/ubuntu-drivers-all.pem new file mode 100644 index 00000000000000..9966174f1f6bb9 --- /dev/null +++ b/debian/certs/ubuntu-drivers-all.pem @@ -0,0 +1,125 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + e9:df:13:0f:92:92:a9:b7 + Signature Algorithm: sha512WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Kernel Module Signing + Validity + Not Before: May 31 16:06:09 2016 GMT + Not After : May 29 16:06:09 2026 GMT + Subject: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Kernel Module Signing + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + RSA Public-Key: (4096 bit) + Modulus: + 00:b3:b0:4f:c6:0a:77:8b:f9:d1:53:33:34:d2:80: + b5:63:6f:e1:f6:a2:83:99:d5:b6:b1:e4:99:91:fa: + 6c:19:c6:d0:91:2a:b9:7d:b5:98:a6:0d:28:01:b8: + 7c:8e:aa:38:ec:51:37:33:96:f0:b0:9b:8d:86:5f: + 67:23:69:2f:d7:c2:f3:fb:c5:d7:f9:04:ff:f2:e5: + 61:68:b7:29:b9:c6:8e:4b:4d:2d:8f:92:0c:00:b3: + a3:d2:5a:08:64:cd:f2:09:0b:a5:0e:e6:64:75:d5: + 41:f4:4d:49:3a:0d:dc:b9:27:8e:c4:d6:b1:df:8f: + 6c:f0:e4:f7:31:cb:a9:04:a1:f9:a7:aa:15:da:59: + 03:4d:46:14:d0:dd:bf:e0:f5:9e:f0:71:0c:70:78: + 2b:08:fb:e0:b6:68:a4:74:12:9d:f7:f2:64:88:17: + 2a:8a:ed:1a:91:b5:6c:13:bd:4c:10:0a:0b:72:0b: + 90:db:7d:f3:78:44:4c:d2:a5:41:f7:1c:77:7d:5a: + 8a:54:bc:8f:fe:b7:ee:e1:bc:59:37:c4:d4:e8:14: + d0:5b:42:9b:04:00:8e:6d:83:8a:25:21:5b:08:c4: + 7b:b2:d9:99:52:c9:5e:59:6d:c4:aa:52:59:e2:e4: + 2f:7e:7e:ac:05:01:99:bf:13:72:b7:45:c5:17:da: + 8a:d5:3e:71:73:2e:d8:aa:e6:eb:5a:d0:9a:c4:93: + f3:be:eb:d2:47:25:34:16:29:fa:dd:9a:2f:b1:20: + e5:41:4e:ed:ea:51:7c:23:80:ba:3d:b5:3a:0b:8c: + 9c:85:48:6c:3c:8b:29:2f:2f:12:c7:52:34:02:ea: + 0f:ac:53:23:3c:f8:3e:40:1b:30:63:e9:2d:e6:f6: + 58:cc:51:f9:eb:08:4a:b4:c7:16:80:d1:8b:c2:64: + 6a:71:a9:70:31:a4:a7:3a:c0:93:99:1b:0e:42:c1: + 00:6d:43:27:99:6c:e5:fd:23:16:c1:8e:b5:66:17: + 2b:4c:53:5a:6d:1e:96:16:13:6a:c6:d4:85:5b:74: + 2e:ce:7c:45:2f:ad:cb:75:9e:5e:91:bd:9a:6a:86: + 1a:06:bd:39:be:a3:50:56:ea:e1:f6:e3:95:69:d7: + 31:e4:66:f7:36:b5:51:c2:22:b4:9c:74:9c:44:0b: + 0e:16:5f:53:f0:23:c6:b9:40:bd:d6:b8:7d:1b:f6: + 73:f6:27:e7:c0:e3:65:a0:58:ab:5c:59:b7:80:8c: + 8c:04:b4:a9:ae:a0:51:40:10:3b:63:59:49:87:d1: + 9b:df:a3:8c:c4:2e:eb:70:c1:0a:18:1f:cb:22:c2: + f2:4a:65:0d:e5:81:74:d8:ce:72:c6:35:be:ba:63: + 72:c4:f9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + 88:F7:52:E5:60:A1:E0:73:7E:31:16:3A:46:6A:D7:B7:0A:85:0C:19 + X509v3 Authority Key Identifier: + keyid:88:F7:52:E5:60:A1:E0:73:7E:31:16:3A:46:6A:D7:B7:0A:85:0C:19 + + Signature Algorithm: sha512WithRSAEncryption + 04:85:16:27:58:ba:71:28:57:86:7b:c2:83:db:e5:72:6f:1e: + b2:1c:63:b0:db:ad:c0:42:96:c0:4f:65:f6:35:4d:c0:07:0d: + 46:be:d3:1e:ec:f1:22:18:2a:18:5d:bb:69:a6:a6:d4:0d:c3: + 57:03:b9:e7:45:49:28:ca:6d:98:17:68:97:cb:7b:36:81:0a: + 37:9e:34:79:f3:e1:0e:5b:77:43:bb:5a:a5:45:b7:16:50:86: + fd:12:a4:96:0f:15:19:09:1c:e1:fa:80:a5:80:09:be:bb:c8: + 26:0b:3e:de:03:d2:c2:18:a4:8d:0d:de:c5:32:82:0b:fb:75: + 55:66:1a:2a:bb:e4:bd:25:91:20:15:d4:be:b8:3f:53:e3:fb: + a8:c3:55:e3:d5:e7:82:18:95:df:39:09:a7:fc:89:6e:b4:1c: + aa:2d:e8:67:c2:0d:34:34:3e:f9:fa:0b:ce:81:92:11:ae:12: + 0a:fe:35:63:ce:46:29:c4:2b:4f:cb:4e:05:0a:a1:11:e2:35: + f6:5a:5d:b5:e8:d2:6f:4c:fc:3d:24:a6:03:4b:dd:98:6b:f2: + 71:58:16:1d:a5:25:ef:d9:06:7c:e8:db:7b:88:6a:89:5c:59: + 01:92:64:db:44:08:63:6c:7c:32:d6:55:98:63:09:26:61:67: + 0a:fe:5d:ee:fd:23:59:b3:4d:91:c1:4d:41:8b:cd:20:58:fa: + 2d:45:e5:bd:1d:69:5c:03:a0:49:a6:97:54:13:b6:c9:e0:f8: + 56:83:a1:2a:c3:f4:6c:fd:ab:20:ca:3d:9c:95:c0:cf:04:bb: + 46:39:cf:34:81:65:45:27:64:01:7d:62:b3:b8:72:ea:10:d5: + 0f:53:7d:39:88:25:09:6f:8c:bc:e0:49:bb:39:e2:0e:8d:cf: + 56:4d:c1:82:6d:87:d2:e7:fc:c0:9f:a7:65:60:d2:6c:65:18: + 59:38:6e:d0:9c:d7:c3:81:9a:9a:29:8f:83:84:c3:b5:44:ff: + 28:ac:13:17:64:f2:26:13:d9:55:06:b7:69:68:7c:bf:ec:d1: + 8c:ef:b7:da:76:e1:07:73:c6:31:62:31:cb:b6:e1:e7:7f:0c: + c3:f7:4c:52:be:25:36:8e:a1:bb:60:02:c3:cb:3e:6f:29:fc: + 7f:6a:fa:f8:ec:0a:df:49:e2:57:0e:bc:bd:93:c3:1b:d5:36: + 8a:ff:d8:1b:17:c7:1f:cb:69:00:d2:54:9e:ad:61:89:92:95: + 11:f8:ea:17:83:9f:9b:09:7d:b8:94:a4:ea:f5:ae:ea:dc:dd: + 62:b9:9e:68:9c:18:ec:19:c4:13:08:c8:b1:62:ab:8e:84:69: + 11:3c:da:ea:0d:b7:22:bd +-----BEGIN CERTIFICATE----- +MIIF2jCCA8KgAwIBAgIJAOnfEw+Skqm3MA0GCSqGSIb3DQEBDQUAMH0xCzAJBgNV +BAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEQMA4GA1UEBwwHRG91Z2xhczEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xLTArBgNVBAMMJENhbm9uaWNhbCBMdGQu +IEtlcm5lbCBNb2R1bGUgU2lnbmluZzAeFw0xNjA1MzExNjA2MDlaFw0yNjA1Mjkx +NjA2MDlaMH0xCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEQMA4G +A1UEBwwHRG91Z2xhczEXMBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xLTArBgNVBAMM +JENhbm9uaWNhbCBMdGQuIEtlcm5lbCBNb2R1bGUgU2lnbmluZzCCAiIwDQYJKoZI +hvcNAQEBBQADggIPADCCAgoCggIBALOwT8YKd4v50VMzNNKAtWNv4faig5nVtrHk +mZH6bBnG0JEquX21mKYNKAG4fI6qOOxRNzOW8LCbjYZfZyNpL9fC8/vF1/kE//Ll +YWi3KbnGjktNLY+SDACzo9JaCGTN8gkLpQ7mZHXVQfRNSToN3LknjsTWsd+PbPDk +9zHLqQSh+aeqFdpZA01GFNDdv+D1nvBxDHB4Kwj74LZopHQSnffyZIgXKortGpG1 +bBO9TBAKC3ILkNt983hETNKlQfccd31ailS8j/637uG8WTfE1OgU0FtCmwQAjm2D +iiUhWwjEe7LZmVLJXlltxKpSWeLkL35+rAUBmb8TcrdFxRfaitU+cXMu2Krm61rQ +msST877r0kclNBYp+t2aL7Eg5UFO7epRfCOAuj21OguMnIVIbDyLKS8vEsdSNALq +D6xTIzz4PkAbMGPpLeb2WMxR+esISrTHFoDRi8JkanGpcDGkpzrAk5kbDkLBAG1D +J5ls5f0jFsGOtWYXK0xTWm0elhYTasbUhVt0Ls58RS+ty3WeXpG9mmqGGga9Ob6j +UFbq4fbjlWnXMeRm9za1UcIitJx0nEQLDhZfU/AjxrlAvda4fRv2c/Yn58DjZaBY +q1xZt4CMjAS0qa6gUUAQO2NZSYfRm9+jjMQu63DBChgfyyLC8kplDeWBdNjOcsY1 +vrpjcsT5AgMBAAGjXTBbMAwGA1UdEwEB/wQCMAAwCwYDVR0PBAQDAgeAMB0GA1Ud +DgQWBBSI91LlYKHgc34xFjpGate3CoUMGTAfBgNVHSMEGDAWgBSI91LlYKHgc34x +FjpGate3CoUMGTANBgkqhkiG9w0BAQ0FAAOCAgEABIUWJ1i6cShXhnvCg9vlcm8e +shxjsNutwEKWwE9l9jVNwAcNRr7THuzxIhgqGF27aaam1A3DVwO550VJKMptmBdo +l8t7NoEKN540efPhDlt3Q7tapUW3FlCG/RKklg8VGQkc4fqApYAJvrvIJgs+3gPS +whikjQ3exTKCC/t1VWYaKrvkvSWRIBXUvrg/U+P7qMNV49XnghiV3zkJp/yJbrQc +qi3oZ8INNDQ++foLzoGSEa4SCv41Y85GKcQrT8tOBQqhEeI19lpdtejSb0z8PSSm +A0vdmGvycVgWHaUl79kGfOjbe4hqiVxZAZJk20QIY2x8MtZVmGMJJmFnCv5d7v0j +WbNNkcFNQYvNIFj6LUXlvR1pXAOgSaaXVBO2yeD4VoOhKsP0bP2rIMo9nJXAzwS7 +RjnPNIFlRSdkAX1is7hy6hDVD1N9OYglCW+MvOBJuzniDo3PVk3Bgm2H0uf8wJ+n +ZWDSbGUYWThu0JzXw4GamimPg4TDtUT/KKwTF2TyJhPZVQa3aWh8v+zRjO+32nbh +B3PGMWIxy7bh538Mw/dMUr4lNo6hu2ACw8s+byn8f2r6+OwK30niVw68vZPDG9U2 +iv/YGxfHH8tpANJUnq1hiZKVEfjqF4Ofmwl9uJSk6vWu6tzdYrmeaJwY7BnEEwjI +sWKrjoRpETza6g23Ir0= +-----END CERTIFICATE----- diff --git a/debian/cloud-tools/hv_get_dhcp_info b/debian/cloud-tools/hv_get_dhcp_info new file mode 100755 index 00000000000000..09fabd266a453e --- /dev/null +++ b/debian/cloud-tools/hv_get_dhcp_info @@ -0,0 +1,55 @@ +#!/bin/bash + +# This example script retrieves the DHCP state of a given interface. +# In the interest of keeping the KVP daemon code free of distro specific +# information; the kvp daemon code invokes this external script to gather +# DHCP setting for the specific interface. +# +# Input: Name of the interface +# +# Output: The script prints the string "Enabled" to stdout to indicate +# that DHCP is enabled on the interface. If DHCP is not enabled, +# the script prints the string "Disabled" to stdout. +# +# Each Distro is expected to implement this script in a distro specific +# fashion. + +#set -x + +IF_FILE="/etc/network/interfaces" +NMCMD="nmcli" + +function checknetworkmanager { + #Assumes if $NMCMD exists, inteface exists and interface is not + # in $IF_FILE then dhcp is being used by NM + if hash $NMCMD >/dev/null 2>&1 ; then + if $NMCMD dev status |grep -q $1 ; then + echo "Enabled" + else + echo "Disabled" + fi + else + #Give up + echo "Disabled" + fi +} + +if [ -z $1 ] ; then echo "Disabled"; exit; fi + +if [ -e $IF_FILE ]; then + if grep -v -e "^#" $IF_FILE|grep -q $1 ; then + #interface exists so + if grep -q -e $1\.\*dhcp $IF_FILE; then + echo "Enabled"; exit; + else + echo "Disabled"; exit; + fi + else + checknetworkmanager $1 + exit + fi +else + checknetworkmanager $1 + exit +fi + diff --git a/debian/cloud-tools/hv_get_dns_info b/debian/cloud-tools/hv_get_dns_info new file mode 100755 index 00000000000000..058c17b46ffcdd --- /dev/null +++ b/debian/cloud-tools/hv_get_dns_info @@ -0,0 +1,13 @@ +#!/bin/bash + +# This example script parses /etc/resolv.conf to retrive DNS information. +# In the interest of keeping the KVP daemon code free of distro specific +# information; the kvp daemon code invokes this external script to gather +# DNS information. +# This script is expected to print the nameserver values to stdout. +# Each Distro is expected to implement this script in a distro specific +# fashion. For instance on Distros that ship with Network Manager enabled, +# this script can be based on the Network Manager APIs for retrieving DNS +# entries. + +cat /etc/resolv.conf 2>/dev/null | awk '/^nameserver/ { print $2 }' diff --git a/debian/cloud-tools/hv_set_ifconfig b/debian/cloud-tools/hv_set_ifconfig new file mode 100755 index 00000000000000..d8b04875c6ce74 --- /dev/null +++ b/debian/cloud-tools/hv_set_ifconfig @@ -0,0 +1,288 @@ +#!/usr/bin/python3 +# +# hv_set_ifconfig -- take the hv_kvp_daemon generated configuration +# file and apply it to the Ubuntu configuration. +# + +# CONFIG example: +# HWADDR=11:22:33:44:55:66 +# DEVICE=foo1 +# DHCP=yes + +# CONFIG example: +# HWADDR=11:22:33:44:55:66 +# DEVICE=foo1 +# IPADDR=192.168.99.10 +# GATEWAY=192.168.99.1 +# DNS1=192.168.88.250 +# IPADDR2=192.168.99.11 +# IPV6ADDR=2001:DB8:99::10 +# IPV6NETMASK=64 +# IPV6_DEFAULTGW=2001:DB8:99::10 + +# set interfaces in hv_kvp_daemon style +import fileinput +import sys +import errno +import os +import shutil +import tempfile +import subprocess + +if_filename="/etc/network/interfaces" + +# Drop our output (XXX?) +sys.stdout = open(os.devnull, 'w') +sys.stderr = open(os.devnull, 'w') + +# Confirm we can open the network configuration. +try: + if_file=open(if_filename,"r+") +except IOError as e: + exit(e.errno) +else: + if_file.close() + +# Usage: hv_set_ifconfig +if len(sys.argv) != 2 : + exit(errno.EINVAL) + +# +# Here is the format of the ip configuration file: +# +# HWADDR=macaddr +# DEVICE=interface name +# BOOTPROTO= (where is "dhcp" if DHCP is configured +# or "none" if no boot-time protocol should be used) +# +# IPADDR0=ipaddr1 +# IPADDR1=ipaddr2 +# IPADDRx=ipaddry (where y = x + 1) +# +# NETMASK0=netmask1 +# NETMASKx=netmasky (where y = x + 1) +# +# GATEWAY=ipaddr1 +# GATEWAYx=ipaddry (where y = x + 1) +# +# DNSx=ipaddrx (where first DNS address is tagged as DNS1 etc) +# +# IPV6 addresses will be tagged as IPV6ADDR, IPV6 gateway will be +# tagged as IPV6_DEFAULTGW and IPV6 NETMASK will be tagged as +# IPV6NETMASK. +# + +kvp=dict(line.strip().split("=") for line in fileinput.input()) + +# Setting the hwaddress to something azure is not expecting is fatal +# to networking. +if not "HWADDR" in kvp : + exit(errno.EPROTO) + +# Confirm we have a device specified. +if not "DEVICE" in kvp : + exit(1) + +autolist = [] +output=[] +basename=kvp["DEVICE"] + +# DNS entries will go with the first interface and there can be a max +# of three. These will be emitted with the first interface. +dns = [] +for count in (1, 2, 3): + key = "DNS" + str(count) + if key in kvp: + dns += [kvp[key]] +dns_emitted = False + +# IPV4 may either be dhcp or static. +if ("DHCP" in kvp and kvp["DHCP"] == "yes") or \ + ("BOOTPROTO" in kvp and kvp["BOOTPROTO"] == "dhcp"): + autolist.append(basename) + output += ["iface " + basename + " inet dhcp"] + output += [""] +else: + # Matchup the interface specific lines + + # No real max for the number of interface + aliases ... + # only required is the address (but mate everything up that comes in. + + # IPv4 -- ensure we sort by numeric suffixes. + v4names = [ int(name[6:]) for name in kvp.keys() if name.startswith("IPADDR") ] + v4names.sort() + + for if_count in v4names: + ifname = basename + which = str(if_count) + + if if_count: + ifname += ":" + str(if_count) + which_gw = which + else: + which_gw = "" + + if not ifname in autolist: + autolist += [ifname] + + output += [ "iface " + ifname + " inet static" ] + output += [ "\t" + "address " + kvp["IPADDR" + which] ] + if "NETMASK" + which in kvp: + output += [ "\tnetmask " + kvp["NETMASK" + which] ] + if "GATEWAY" + which_gw in kvp: + output += ["\tgateway " + kvp["GATEWAY" + which_gw]] + + if not dns_emitted: + dns_emitted = True + output += ["\tdns-nameservers " + ' '.join(dns)] + output += [""] + +# IPv6 requires a netmask +# If an ipv6 exists, you'll want to turn off /proc/sys/net/ipv6/conf/all/autoconf with +# echo 0 > /proc/sys/net/ipv6/conf/all/autoconf +v6names = [ int(name[8:]) for name in kvp.keys() if name.startswith("IPV6ADDR") ] +v6names.sort() + +for if6_count in v6names: + ifname = basename + which = str(if6_count) + + if if6_count: + ifname += ":" + str(if6_count) + which_gw = which + else: + which_gw = "" + + if not ifname in autolist: + autolist += [ifname] + + if "IPV6NETMASK" + which in kvp: + output += [ "iface " + ifname + " inet6 static"] + output += [ "\taddress " + kvp["IPV6ADDR" + which]] + output += [ "\tnetmask " + kvp["IPV6NETMASK" + which]] + if "IPV6_DEFAULTGW" + which_gw in kvp: + output += [ "\tgateway " + kvp["IPV6_DEFAULTGW" + which_gw] ] + if not dns_emitted: + dns_emitted = True + output += ["\tdns-nameservers " + ' '.join(dns)] + output += [""] + +# Mark this new interface for automatic up. +if len(autolist): + output = ["auto "+" ".join(autolist)] + output + +print("===================================") +print(output) +print("===================================") + + +# Time to clean out the existing interface file + +# Markers. +start_mark = "# The following stanza(s) added by hv_set_ifconfig" +end_mark = "#End of hv_set_ifconfig stanzas" + +f=open(if_filename,"r") +flines=f.readlines() +f.close() +newfile=[] +pitchstanza=0 +inastanza=0 +stanza=[] +prev_line=None +for line in flines: + if line.startswith("auto"): + if inastanza: + if not pitchstanza: + newfile.extend(stanza) + stanza=[] + inastanza=0 + newline="" + autoline=line.strip().split(" ") + for word in autoline: + if (not word == basename) and (not word.startswith(basename+":")): + newline+=word + " " + newline = newline.strip() + if not newline == "auto": + newfile += [newline.strip()] + elif line.startswith(("iface","mapping","source")): + '''Read a stanza''' + '''A Stanza can also start with allow- ie allow-hotplug''' + if inastanza: + if not pitchstanza: + newfile.extend(stanza) + stanza=[] + inastanza=1 + pitchstanza=0 + autoline=line.strip().split(" ") + for word in autoline: + if (word == basename) or (word.startswith(basename+":")): + pitchstanza=1 + if not pitchstanza: + stanza+=[line.strip()] + elif line.strip() in (start_mark, end_mark): + if inastanza: + if not pitchstanza: + newfile.extend(stanza) + stanza=[] + inastanza = 0 + pitchstanza = 0 + # Deduplicate markers. + if line != prev_line: + newfile += [line.strip()] + else: + if inastanza: + if not pitchstanza: + stanza+=[line.strip()] + else: + if not pitchstanza: + newfile += [line.strip()] + prev_line=line + +# Include pending stanza if any. +if inastanza and not pitchstanza: + newfile.extend(stanza) + + +def emit(line): + print(line) + output = line + "\n" + os.write(fd, output.encode('utf-8')) + +# Insert the new output at the end and inside the existing markers if found. +emitted = False +fd, path = tempfile.mkstemp() +for line in newfile: + if line == end_mark: + emit("\n".join(output)) + emitted = True + emit(line) +if not emitted: + emit(start_mark) + emit("\n".join(output)) + emit(end_mark) +os.close(fd) + +shutil.copy(path,if_filename) +os.chmod(if_filename,0o644) + +#print("TMPFILE is at: " + path) +#print("Copied file is at: " + if_filename) + +try: + retcode = subprocess.call("ifdown "+basename , shell=True) + if retcode < 0: + print("Child was terminated by signal", -retcode, file=sys.stderr) + else: + print("Child returned", retcode, file=sys.stderr) +except OSError as e: + print("Execution failed:", e, file=sys.stderr) + +try: + retcode = subprocess.call("ifup "+basename , shell=True) + if retcode < 0: + print("Child was terminated by signal", -retcode, file=sys.stderr) + else: + print("Child returned", retcode, file=sys.stderr) +except OSError as e: + print("Execution failed:", e, file=sys.stderr) diff --git a/debian/control.d/bpftool.stub b/debian/control.d/bpftool.stub new file mode 100644 index 00000000000000..de5e84df2c0392 --- /dev/null +++ b/debian/control.d/bpftool.stub @@ -0,0 +1,10 @@ +Package: bpftool +Architecture: amd64 armhf arm64 ppc64el riscv64 s390x +Depends: ${misc:Depends}, ${shlibs:Depends} +Breaks: + linux-tools-common (<< 6.14.0-8~), +Replaces: + linux-tools-common (<< 6.14.0-8~), +Description: Inspection and simple manipulation of BPF programs and maps + The bpftool command allows for inspection and simple modification of + Berkeley Packet Filter (BPF) objects on the system. diff --git a/debian/control.d/flavour-buildinfo.stub b/debian/control.d/flavour-buildinfo.stub new file mode 100644 index 00000000000000..4c7e89d206c11a --- /dev/null +++ b/debian/control.d/flavour-buildinfo.stub @@ -0,0 +1,13 @@ + +Package: linux-buildinfo-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends} +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel buildinfo for version PKGVER + This package contains the Linux kernel buildinfo for version PKGVER. + . + You likely do not want to install this package. + diff --git a/debian/control.d/flavour-module.stub b/debian/control.d/flavour-module.stub new file mode 100644 index 00000000000000..2810f83bb361fd --- /dev/null +++ b/debian/control.d/flavour-module.stub @@ -0,0 +1,19 @@ + +Package: linux-modules-MODULE-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Depends: + ${misc:Depends}, + linux-image-PKGVER-ABINUM-FLAVOUR | linux-image-unsigned-PKGVER-ABINUM-FLAVOUR, +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel MODULE modules for version PKGVER-ABINUM + This package provides the Linux kernel MODULE modules for version + PKGVER-ABINUM. + . + You likely do not want to install this package directly. Instead, install the + one of the linux-modules-MODULE-FLAVOUR* meta-packages, + which will ensure that upgrades work correctly, and that supporting packages are + also installed. + diff --git a/debian/control.d/linux-bpf-dev.stub b/debian/control.d/linux-bpf-dev.stub new file mode 100644 index 00000000000000..2967299aec18aa --- /dev/null +++ b/debian/control.d/linux-bpf-dev.stub @@ -0,0 +1,7 @@ +Package: linux-bpf-dev +Architecture: amd64 armhf arm64 i386 ppc64el riscv64 s390x +Depends: ${misc:Depends} +Multi-Arch: same +Description: Headers for BPF development + The vmlinux.h header is provided to allow userspace to build BPF CO-RE + programs targeting the packaged kernel. diff --git a/debian/control.d/linux-cloud-tools-common.stub b/debian/control.d/linux-cloud-tools-common.stub new file mode 100644 index 00000000000000..724dab9bef002d --- /dev/null +++ b/debian/control.d/linux-cloud-tools-common.stub @@ -0,0 +1,10 @@ +Package: linux-cloud-tools-common +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: kernel +Priority: optional +Depends: ${misc:Depends} +Description: Linux kernel version specific cloud tools for version PKGVER + This package provides the architecture independent parts for kernel + version locked tools for cloud tools for version PKGVER. diff --git a/debian/control.d/linux-libc-dev.stub b/debian/control.d/linux-libc-dev.stub new file mode 100644 index 00000000000000..fb045233d40178 --- /dev/null +++ b/debian/control.d/linux-libc-dev.stub @@ -0,0 +1,12 @@ +Package: linux-libc-dev +Architecture: amd64 armhf arm64 i386 ppc64el riscv64 s390x +Depends: ${misc:Depends} +Conflicts: linux-kernel-headers +Replaces: linux-kernel-headers +Provides: linux-kernel-headers, aufs-dev +Multi-Arch: same +Description: Linux Kernel Headers for development + This package provides headers from the Linux kernel. These headers + are used by the installed headers for GNU glibc and other system + libraries. They are NOT meant to be used to build third-party modules for + your kernel. Use SRCPKGNAME-headers-* packages for that. diff --git a/debian/control.d/linux-perf.stub b/debian/control.d/linux-perf.stub new file mode 100644 index 00000000000000..d93c6ea2210f41 --- /dev/null +++ b/debian/control.d/linux-perf.stub @@ -0,0 +1,8 @@ +Package: linux-perf +Architecture: amd64 armhf arm64 ppc64el riscv64 s390x +Depends: ${misc:Depends}, ${shlibs:Depends} +Breaks: + linux-tools-common (<< 6.14.0-8~), +Replaces: + linux-tools-common (<< 6.14.0-8~), +Description: Performance analysis tools for Linux diff --git a/debian/control.d/linux-source.stub b/debian/control.d/linux-source.stub new file mode 100644 index 00000000000000..aa141d2afb5293 --- /dev/null +++ b/debian/control.d/linux-source.stub @@ -0,0 +1,23 @@ +Package: linux-source-PKGVER +Build-Profiles: +Architecture: all +Section: devel +Priority: optional +Provides: linux-source +Depends: ${misc:Depends}, binutils, bzip2, coreutils +Recommends: libc-dev, gcc, make +Suggests: libncurses-dev | ncurses-dev, kernel-package +Description: Linux kernel source for version PKGVER with Ubuntu patches + This package provides the source code for the Linux kernel version + PKGVER. + . + This package is mainly meant for other packages to use, in order to build + custom flavours. + . + If you wish to use this package to create a custom Linux kernel, then it + is suggested that you investigate the package kernel-package, which has + been designed to ease the task of creating kernel image packages. + . + If you are simply trying to build third-party modules for your kernel, + you do not want this package. Install the appropriate linux-headers + package instead. diff --git a/debian/control.d/linux-tools-common.stub b/debian/control.d/linux-tools-common.stub new file mode 100644 index 00000000000000..4dab643d25e14f --- /dev/null +++ b/debian/control.d/linux-tools-common.stub @@ -0,0 +1,16 @@ +Package: linux-tools-common +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: kernel +Priority: optional +Provides: + linux-cpupower, +Recommends: + bpftool (>= 7.6.0+6.14.0-8~), + linux-perf, +Depends: ${misc:Depends}, lsb-release, hwdata +Description: Linux kernel version specific tools for version PKGVER + This package provides the architecture independent parts for kernel + version locked tools (such as perf and x86_energy_perf_policy) for + version PKGVER. diff --git a/debian/control.d/linux-tools-host.stub b/debian/control.d/linux-tools-host.stub new file mode 100644 index 00000000000000..f2ea6a9f7fff23 --- /dev/null +++ b/debian/control.d/linux-tools-host.stub @@ -0,0 +1,9 @@ +Package: linux-tools-host +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: kernel +Priority: optional +Depends: ${misc:Depends}, python3 +Description: Linux kernel VM host tools + This package provides kernel tools useful for VM hosts. diff --git a/debian/copyright b/debian/copyright new file mode 100644 index 00000000000000..d1d04a6d669749 --- /dev/null +++ b/debian/copyright @@ -0,0 +1,29 @@ +This is the Ubuntu prepackaged version of the Linux kernel. +Linux was written by Linus Torvalds +and others. + +This package was put together by the Ubuntu Kernel Team, from +sources retrieved from upstream linux git. +The sources may be found at most Linux ftp sites, including +ftp://ftp.kernel.org/pub/linux/kernel/ + +This package is currently maintained by the +Ubuntu Kernel Team + +Linux is copyrighted by Linus Torvalds and others. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 dated June, 1991. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +On Ubuntu Linux systems, the complete text of the GNU General +Public License v2 can be found in `/usr/share/common-licenses/GPL-2'. diff --git a/debian/debian.env b/debian/debian.env new file mode 100644 index 00000000000000..127466464b8b7f --- /dev/null +++ b/debian/debian.env @@ -0,0 +1 @@ +DEBIAN=debian.qcom-x1e diff --git a/debian/gbp.conf b/debian/gbp.conf new file mode 100644 index 00000000000000..8ce5fdad0ead70 --- /dev/null +++ b/debian/gbp.conf @@ -0,0 +1,2 @@ +[buildpackage] +debian-tag = Ubuntu-%(version)s diff --git a/debian/linux-cloud-tools-common.hv-fcopy-daemon.service b/debian/linux-cloud-tools-common.hv-fcopy-daemon.service new file mode 100644 index 00000000000000..486ccd52fdf8ac --- /dev/null +++ b/debian/linux-cloud-tools-common.hv-fcopy-daemon.service @@ -0,0 +1,14 @@ +# On Azure/Hyper-V systems start the hv_fcopy_uio_daemon +# +# author "Andy Whitcroft " +[Unit] +Description=Hyper-V File Copy Protocol Daemon +ConditionVirtualization=microsoft +ConditionPathExists=/dev/vmbus/hv_fcopy +BindsTo=sys-devices-virtual-misc-vmbus\x21hv_fcopy.device + +[Service] +ExecStart=/usr/sbin/hv_fcopy_uio_daemon -n + +[Install] +WantedBy=multi-user.target diff --git a/debian/linux-cloud-tools-common.hv-fcopy-daemon.udev b/debian/linux-cloud-tools-common.hv-fcopy-daemon.udev new file mode 100644 index 00000000000000..8f85edb87aeb30 --- /dev/null +++ b/debian/linux-cloud-tools-common.hv-fcopy-daemon.udev @@ -0,0 +1 @@ +SUBSYSTEM=="misc", KERNEL=="vmbus/hv_fcopy", TAG+="systemd", ENV{SYSTEMD_WANTS}+="hv-fcopy-daemon.service" diff --git a/debian/linux-cloud-tools-common.hv-kvp-daemon.service b/debian/linux-cloud-tools-common.hv-kvp-daemon.service new file mode 100644 index 00000000000000..efd0931f749573 --- /dev/null +++ b/debian/linux-cloud-tools-common.hv-kvp-daemon.service @@ -0,0 +1,20 @@ +# On Azure/Hyper-V systems start the hv_kvp_daemon +# +# author "Andy Whitcroft " +[Unit] +Description=Hyper-V KVP Protocol Daemon +ConditionVirtualization=microsoft +ConditionKernelCommandLine=!snapd_recovery_mode +DefaultDependencies=no +BindsTo=sys-devices-virtual-misc-vmbus\x21hv_kvp.device +After=sys-devices-virtual-misc-vmbus\x21hv_kvp.device systemd-remount-fs.service +Before=shutdown.target cloud-init-local.service walinuxagent.service +Conflicts=shutdown.target +RequiresMountsFor=/var/lib/hyperv +ConditionPathExists=/dev/vmbus/hv_kvp + +[Service] +ExecStart=/usr/sbin/hv_kvp_daemon -n + +[Install] +WantedBy=multi-user.target diff --git a/debian/linux-cloud-tools-common.hv-kvp-daemon.udev b/debian/linux-cloud-tools-common.hv-kvp-daemon.udev new file mode 100644 index 00000000000000..0c648f54d4c493 --- /dev/null +++ b/debian/linux-cloud-tools-common.hv-kvp-daemon.udev @@ -0,0 +1 @@ +SUBSYSTEM=="misc", KERNEL=="vmbus/hv_kvp", TAG+="systemd", ENV{SYSTEMD_WANTS}+="hv-kvp-daemon.service" diff --git a/debian/linux-cloud-tools-common.hv-vss-daemon.service b/debian/linux-cloud-tools-common.hv-vss-daemon.service new file mode 100644 index 00000000000000..4ff9e796b3b21f --- /dev/null +++ b/debian/linux-cloud-tools-common.hv-vss-daemon.service @@ -0,0 +1,14 @@ +# On Azure/Hyper-V systems start the hv_vss_daemon +# +# author "Andy Whitcroft " +[Unit] +Description=Hyper-V VSS Protocol Daemon +ConditionVirtualization=microsoft +ConditionPathExists=/dev/vmbus/hv_vss +BindsTo=sys-devices-virtual-misc-vmbus\x21hv_vss.device + +[Service] +ExecStart=/usr/sbin/hv_vss_daemon -n + +[Install] +WantedBy=multi-user.target diff --git a/debian/linux-cloud-tools-common.hv-vss-daemon.udev b/debian/linux-cloud-tools-common.hv-vss-daemon.udev new file mode 100644 index 00000000000000..f4b9a91ad4bfc2 --- /dev/null +++ b/debian/linux-cloud-tools-common.hv-vss-daemon.udev @@ -0,0 +1 @@ +SUBSYSTEM=="misc", KERNEL=="vmbus/hv_vss", TAG+="systemd", ENV{SYSTEMD_WANTS}+="hv-vss-daemon.service" diff --git a/debian/linux-cloud-tools-common.intel-sgx-load-module.service b/debian/linux-cloud-tools-common.intel-sgx-load-module.service new file mode 100644 index 00000000000000..a1882acbda223d --- /dev/null +++ b/debian/linux-cloud-tools-common.intel-sgx-load-module.service @@ -0,0 +1,13 @@ +[Unit] +Description=Install SGX kernel module +DefaultDependencies=false +ConditionVirtualization=microsoft + +[Service] +Type=oneshot +RemainAfterExit=true +ExecStart=/sbin/modprobe intel_sgx +ExecStop=/sbin/modprobe -r intel_sgx + +[Install] +WantedBy=multi-user.target diff --git a/debian/revoked-certs/canonical-uefi-2012-all.pem b/debian/revoked-certs/canonical-uefi-2012-all.pem new file mode 100644 index 00000000000000..4bdd9a3c26afc1 --- /dev/null +++ b/debian/revoked-certs/canonical-uefi-2012-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 1 (0x1) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Apr 12 11:39:08 2012 GMT + Not After : Apr 11 11:39:08 2042 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:c9:5f:9b:62:8f:0b:b0:64:82:ac:be:c9:e2:62: + e3:4b:d2:9f:1e:8a:d5:61:1a:2b:5d:38:f4:b7:ce: + b9:9a:b8:43:b8:43:97:77:ab:4f:7f:0c:70:46:0b: + fc:7f:6d:c6:6d:ea:80:5e:01:d2:b7:66:1e:87:de: + 0d:6d:d0:41:97:a8:a5:af:0c:63:4f:f7:7c:c2:52: + cc:a0:31:a9:bb:89:5d:99:1e:46:6f:55:73:b9:76: + 69:ec:d7:c1:fc:21:d6:c6:07:e7:4f:bd:22:de:e4: + a8:5b:2d:db:95:34:19:97:d6:28:4b:21:4c:ca:bb: + 1d:79:a6:17:7f:5a:f9:67:e6:5c:78:45:3d:10:6d: + b0:17:59:26:11:c5:57:e3:7f:4e:82:ba:f6:2c:4e: + c8:37:4d:ff:85:15:84:47:e0:ed:3b:7c:7f:bc:af: + e9:01:05:a7:0c:6f:c3:e9:8d:a3:ce:be:a6:e3:cd: + 3c:b5:58:2c:9e:c2:03:1c:60:22:37:39:ff:41:02: + c1:29:a4:65:51:ff:33:34:aa:42:15:f9:95:78:fc: + 2d:f5:da:8a:85:7c:82:9d:fb:37:2c:6b:a5:a8:df: + 7c:55:0b:80:2e:3c:b0:63:e1:cd:38:48:89:e8:14: + 06:0b:82:bc:fd:d4:07:68:1b:0f:3e:d9:15:dd:94: + 11:1b + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 61:48:2A:A2:83:0D:0A:B2:AD:5A:F1:0B:72:50:DA:90:33:DD:CE:F0 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 8f:8a:a1:06:1f:29:b7:0a:4a:d5:c5:fd:81:ab:25:ea:c0:7d: + e2:fc:6a:96:a0:79:93:67:ee:05:0e:25:12:25:e4:5a:f6:aa: + 1a:f1:12:f3:05:8d:87:5e:f1:5a:5c:cb:8d:23:73:65:1d:15: + b9:de:22:6b:d6:49:67:c9:a3:c6:d7:62:4e:5c:b5:f9:03:83: + 40:81:dc:87:9c:3c:3f:1c:0d:51:9f:94:65:0a:84:48:67:e4: + a2:f8:a6:4a:f0:e7:cd:cd:bd:94:e3:09:d2:5d:2d:16:1b:05: + 15:0b:cb:44:b4:3e:61:42:22:c4:2a:5c:4e:c5:1d:a3:e2:e0: + 52:b2:eb:f4:8b:2b:dc:38:39:5d:fb:88:a1:56:65:5f:2b:4f: + 26:ff:06:78:10:12:eb:8c:5d:32:e3:c6:45:af:25:9b:a0:ff: + 8e:ef:47:09:a3:e9:8b:37:92:92:69:76:7e:34:3b:92:05:67: + 4e:b0:25:ed:bc:5e:5f:8f:b4:d6:ca:40:ff:e4:e2:31:23:0c: + 85:25:ae:0c:55:01:ec:e5:47:5e:df:5b:bc:14:33:e3:c6:f5: + 18:b6:d9:f7:dd:b3:b4:a1:31:d3:5a:5c:5d:7d:3e:bf:0a:e4: + e4:e8:b4:59:7d:3b:b4:8c:a3:1b:b5:20:a3:b9:3e:84:6f:8c: + 21:00:c3:39 +-----BEGIN CERTIFICATE----- +MIIEIDCCAwigAwIBAgIBATANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xMjA0MTIxMTM5MDhaFw00MjA0MTEx +MTM5MDhaMH8xCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEXMBUG +A1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MSswKQYD +VQQDDCJDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nMIIBIjANBgkq +hkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAyV+bYo8LsGSCrL7J4mLjS9KfHorVYRor +XTj0t865mrhDuEOXd6tPfwxwRgv8f23GbeqAXgHSt2Yeh94NbdBBl6ilrwxjT/d8 +wlLMoDGpu4ldmR5Gb1VzuXZp7NfB/CHWxgfnT70i3uSoWy3blTQZl9YoSyFMyrsd +eaYXf1r5Z+ZceEU9EG2wF1kmEcVX439Ogrr2LE7IN03/hRWER+DtO3x/vK/pAQWn +DG/D6Y2jzr6m4808tVgsnsIDHGAiNzn/QQLBKaRlUf8zNKpCFfmVePwt9dqKhXyC +nfs3LGulqN98VQuALjywY+HNOEiJ6BQGC4K8/dQHaBsPPtkV3ZQRGwIDAQABo4Gg +MIGdMAwGA1UdEwEB/wQCMAAwHwYDVR0lBBgwFgYIKwYBBQUHAwMGCisGAQQBgjcK +AwYwLAYJYIZIAYb4QgENBB8WHU9wZW5TU0wgR2VuZXJhdGVkIENlcnRpZmljYXRl +MB0GA1UdDgQWBBRhSCqigw0Ksq1a8QtyUNqQM93O8DAfBgNVHSMEGDAWgBStkZkL +wiqx9RcEjCO2ZVomjjRaYzANBgkqhkiG9w0BAQsFAAOCAQEAj4qhBh8ptwpK1cX9 +gasl6sB94vxqlqB5k2fuBQ4lEiXkWvaqGvES8wWNh17xWlzLjSNzZR0Vud4ia9ZJ +Z8mjxtdiTly1+QODQIHch5w8PxwNUZ+UZQqESGfkovimSvDnzc29lOMJ0l0tFhsF +FQvLRLQ+YUIixCpcTsUdo+LgUrLr9Isr3Dg5XfuIoVZlXytPJv8GeBAS64xdMuPG +Ra8lm6D/ju9HCaPpizeSkml2fjQ7kgVnTrAl7bxeX4+01spA/+TiMSMMhSWuDFUB +7OVHXt9bvBQz48b1GLbZ992ztKEx01pcXX0+vwrk5Oi0WX07tIyjG7Ugo7k+hG+M +IQDDOQ== +-----END CERTIFICATE----- diff --git a/debian/revoked-certs/canonical-uefi-2017-all.pem b/debian/revoked-certs/canonical-uefi-2017-all.pem new file mode 100644 index 00000000000000..6f722331d14b7b --- /dev/null +++ b/debian/revoked-certs/canonical-uefi-2017-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 2 (0x2) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 26 21:52:11 2017 GMT + Not After : Sep 25 21:52:11 2047 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2017) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:ef:9f:fa:9f:19:3a:9d:38:23:91:cc:c4:f9:42: + e0:f8:54:12:82:dc:97:2c:d6:5b:c1:35:eb:ff:4a: + 74:06:b5:9d:32:aa:7b:f3:fc:31:5a:34:3e:a1:a4: + 44:db:7b:6d:16:af:35:76:e0:9b:99:ad:21:11:c6: + 12:4b:ae:24:8f:bb:d3:b2:00:fe:c5:1d:9b:3a:1a: + 4a:6c:ca:fa:16:37:85:22:f9:ff:22:fc:40:e0:58: + 35:c1:39:27:b4:c6:42:1a:96:d8:a5:c5:95:2e:f7: + c5:1e:21:6e:36:84:f7:a9:a1:e1:f1:03:08:96:65: + 71:f8:eb:83:cf:82:f7:9a:44:58:72:00:14:39:29: + 4b:e9:78:2f:65:20:b3:80:76:3b:ba:0d:2d:46:f6: + 37:05:e7:05:fe:bd:6c:c7:a2:65:b5:06:6e:07:24: + 99:a1:c1:cf:e1:0e:5e:49:41:71:17:a8:50:e7:38: + 99:e5:6e:b6:db:9f:63:db:56:f4:9c:7d:89:f6:d2: + 03:6c:99:83:e0:99:23:39:36:bd:cb:b5:26:7c:7d: + b0:c6:fe:82:7c:52:ed:f9:2c:8f:79:71:3d:a9:2f: + b5:aa:7e:77:a0:fd:69:f9:97:10:a8:b2:c6:7d:88: + 9e:a2:19:bd:31:b8:02:2d:34:4d:9d:98:60:82:ad: + 04:ff + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 24:2A:DE:75:AC:4A:15:E5:0D:50:C8:4B:0D:45:FF:3E:AE:70:7A:03 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 00:b2:b7:57:b5:2b:5d:16:d3:04:88:6a:d7:77:d5:0d:89:f1: + d2:6e:11:d1:8e:f5:62:05:c4:6a:57:df:eb:d2:86:68:f2:fd: + a7:37:11:3c:f4:ce:5d:fe:32:5f:31:a2:6b:3a:da:28:c2:88: + fa:7f:70:b5:25:99:ea:27:9a:56:6a:9d:b2:0f:14:99:e2:b7: + c6:39:1e:8e:a7:76:31:d9:ed:c5:05:8d:48:ae:1b:68:18:14: + 51:a1:7d:f6:c7:df:cb:9d:eb:a4:3b:0b:ff:c2:07:c5:42:bc: + 0d:b2:11:fa:37:17:2b:1c:b5:84:48:2d:f9:31:4a:57:49:8e: + 61:a6:82:11:06:4c:34:ea:9c:2a:47:4d:eb:e0:26:af:da:d2: + c2:08:a0:37:35:7b:73:71:de:0b:c4:ba:c8:34:de:20:04:03: + 6f:46:26:0d:b9:91:02:5b:71:76:cc:45:e4:08:d0:a6:dd:a4: + 50:d3:d9:04:91:2b:d9:5c:34:88:fc:c2:37:fd:c6:d4:3e:57: + f7:6b:ba:7b:d7:02:7a:84:0c:c8:c1:19:cc:bc:fa:52:d5:7f: + b3:35:c4:53:5d:70:0a:f6:44:60:8d:a9:11:7a:1b:7d:ae:7b: + 20:5a:4c:8d:44:f6:c1:a9:61:cb:dc:cb:90:37:d5:28:24:73: + 87:d0:e0:d8 +-----BEGIN CERTIFICATE----- +MIIEKDCCAxCgAwIBAgIBAjANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xNzA5MjYyMTUyMTFaFw00NzA5MjUy +MTUyMTFaMIGGMQswCQYDVQQGEwJHQjEUMBIGA1UECAwLSXNsZSBvZiBNYW4xFzAV +BgNVBAoMDkNhbm9uaWNhbCBMdGQuMRQwEgYDVQQLDAtTZWN1cmUgQm9vdDEyMDAG +A1UEAwwpQ2Fub25pY2FsIEx0ZC4gU2VjdXJlIEJvb3QgU2lnbmluZyAoMjAxNykw +ggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDvn/qfGTqdOCORzMT5QuD4 +VBKC3Jcs1lvBNev/SnQGtZ0yqnvz/DFaND6hpETbe20WrzV24JuZrSERxhJLriSP +u9OyAP7FHZs6GkpsyvoWN4Ui+f8i/EDgWDXBOSe0xkIaltilxZUu98UeIW42hPep +oeHxAwiWZXH464PPgveaRFhyABQ5KUvpeC9lILOAdju6DS1G9jcF5wX+vWzHomW1 +Bm4HJJmhwc/hDl5JQXEXqFDnOJnlbrbbn2PbVvScfYn20gNsmYPgmSM5Nr3LtSZ8 +fbDG/oJ8Uu35LI95cT2pL7Wqfneg/Wn5lxCossZ9iJ6iGb0xuAItNE2dmGCCrQT/ +AgMBAAGjgaAwgZ0wDAYDVR0TAQH/BAIwADAfBgNVHSUEGDAWBggrBgEFBQcDAwYK +KwYBBAGCNwoDBjAsBglghkgBhvhCAQ0EHxYdT3BlblNTTCBHZW5lcmF0ZWQgQ2Vy +dGlmaWNhdGUwHQYDVR0OBBYEFCQq3nWsShXlDVDISw1F/z6ucHoDMB8GA1UdIwQY +MBaAFK2RmQvCKrH1FwSMI7ZlWiaONFpjMA0GCSqGSIb3DQEBCwUAA4IBAQAAsrdX +tStdFtMEiGrXd9UNifHSbhHRjvViBcRqV9/r0oZo8v2nNxE89M5d/jJfMaJrOtoo +woj6f3C1JZnqJ5pWap2yDxSZ4rfGOR6Op3Yx2e3FBY1IrhtoGBRRoX32x9/Lneuk +Owv/wgfFQrwNshH6NxcrHLWESC35MUpXSY5hpoIRBkw06pwqR03r4Cav2tLCCKA3 +NXtzcd4LxLrINN4gBANvRiYNuZECW3F2zEXkCNCm3aRQ09kEkSvZXDSI/MI3/cbU +Plf3a7p71wJ6hAzIwRnMvPpS1X+zNcRTXXAK9kRgjakReht9rnsgWkyNRPbBqWHL +3MuQN9UoJHOH0ODY +-----END CERTIFICATE----- diff --git a/debian/revoked-certs/canonical-uefi-2018-all.pem b/debian/revoked-certs/canonical-uefi-2018-all.pem new file mode 100644 index 00000000000000..4a591b2107b471 --- /dev/null +++ b/debian/revoked-certs/canonical-uefi-2018-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 3 (0x3) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Oct 26 18:31:14 2018 GMT + Not After : Oct 24 18:31:14 2048 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (ESM 2018) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:bf:6a:e5:6d:55:7a:ec:7a:11:37:45:9c:4c:8f: + 6b:2d:56:d3:74:2b:32:ac:84:2d:ba:cb:cc:ec:8d: + 92:22:69:48:a5:d4:f6:75:11:66:2f:cb:b2:fd:9e: + 56:ab:e6:f1:52:8e:75:3e:50:bd:25:b3:50:fc:ef: + 3d:76:f3:3f:7f:03:f6:e2:a1:25:69:5c:14:98:54: + bd:11:bf:e9:a5:ac:46:91:4b:1d:de:b7:18:2b:c8: + 22:83:15:a7:4a:00:8d:9d:e4:c0:da:f7:41:02:fd: + 9f:5f:79:93:56:cc:86:e1:b5:e0:39:0e:3c:a2:5b: + fe:c0:56:f0:92:50:5a:2b:67:67:93:56:d7:7a:75: + 99:6a:25:b4:63:a8:5f:69:7e:3a:49:58:2a:a7:80: + f6:5a:b4:be:b2:be:a8:8c:45:41:c9:f2:fc:76:a8: + 65:ef:99:29:0d:c9:9c:54:6b:0a:f0:4a:0e:61:0d: + ed:99:32:af:12:e2:12:7b:9f:7b:ec:05:c4:e0:b6: + d5:c3:71:28:ae:dd:0b:ba:97:ad:68:0b:76:e9:bf: + e7:01:7e:64:54:39:23:85:36:c8:9d:dd:27:a1:ff: + df:46:36:14:7e:cb:cc:a1:cd:49:0b:6d:c2:0c:45: + 99:56:58:7c:87:0d:59:9a:dc:4a:39:3b:1d:d9:15: + 2e:b5 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 36:51:88:C1:D3:74:D6:B0:7C:3C:8F:24:0F:8E:F7:22:43:3D:6A:8B + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 4c:0f:cd:77:60:b4:6f:53:87:f3:3c:4f:e6:81:5f:a7:1c:cc: + 60:29:b6:34:6c:4d:08:9b:e2:d2:bd:f6:17:1a:62:79:b8:17: + bc:a2:60:59:fd:03:51:c3:b7:6b:de:73:b3:48:95:f5:0b:aa: + b6:3c:b4:34:dc:1d:0b:c4:97:62:87:e7:48:d5:8f:c9:ea:e8: + 91:8f:2a:40:cd:b7:b3:ee:b2:98:9e:fb:37:31:29:e6:8e:2f: + 0a:39:99:1e:c6:aa:b8:05:62:85:d3:a8:3e:60:38:98:0f:f0: + fe:c7:ab:01:a5:6a:a5:7f:70:a6:26:94:76:23:2f:08:89:74: + 97:c2:2a:ca:22:3e:7a:ea:22:22:08:07:f4:bb:f6:bc:69:9c: + 4e:44:33:e2:8e:70:17:b0:9b:cb:33:94:66:6d:ff:9a:7d:e9: + 50:b2:e8:90:14:e4:2b:91:cb:a0:c5:2e:0e:cf:19:ef:44:ef: + 84:f0:bd:57:9e:26:c2:63:3d:df:fc:a1:84:de:5c:d7:5f:3b: + fb:94:61:f0:93:89:1f:cf:c3:b2:d1:90:97:35:7d:b9:8a:ad: + e6:05:f0:e8:3b:a1:7c:af:2b:c4:af:18:33:2e:5e:87:db:9d: + 80:b5:04:fd:00:d0:60:ab:ff:85:77:0f:cb:47:22:c9:b2:85: + a8:48:16:e2 +-----BEGIN CERTIFICATE----- +MIIELDCCAxSgAwIBAgIBAzANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xODEwMjYxODMxMTRaFw00ODEwMjQx +ODMxMTRaMIGKMQswCQYDVQQGEwJHQjEUMBIGA1UECAwLSXNsZSBvZiBNYW4xFzAV +BgNVBAoMDkNhbm9uaWNhbCBMdGQuMRQwEgYDVQQLDAtTZWN1cmUgQm9vdDE2MDQG +A1UEAwwtQ2Fub25pY2FsIEx0ZC4gU2VjdXJlIEJvb3QgU2lnbmluZyAoRVNNIDIw +MTgpMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAv2rlbVV67HoRN0Wc +TI9rLVbTdCsyrIQtusvM7I2SImlIpdT2dRFmL8uy/Z5Wq+bxUo51PlC9JbNQ/O89 +dvM/fwP24qElaVwUmFS9Eb/ppaxGkUsd3rcYK8gigxWnSgCNneTA2vdBAv2fX3mT +VsyG4bXgOQ48olv+wFbwklBaK2dnk1bXenWZaiW0Y6hfaX46SVgqp4D2WrS+sr6o +jEVByfL8dqhl75kpDcmcVGsK8EoOYQ3tmTKvEuISe5977AXE4LbVw3Eort0Lupet +aAt26b/nAX5kVDkjhTbInd0nof/fRjYUfsvMoc1JC23CDEWZVlh8hw1ZmtxKOTsd +2RUutQIDAQABo4GgMIGdMAwGA1UdEwEB/wQCMAAwHwYDVR0lBBgwFgYIKwYBBQUH +AwMGCisGAQQBgjcKAwYwLAYJYIZIAYb4QgENBB8WHU9wZW5TU0wgR2VuZXJhdGVk +IENlcnRpZmljYXRlMB0GA1UdDgQWBBQ2UYjB03TWsHw8jyQPjvciQz1qizAfBgNV +HSMEGDAWgBStkZkLwiqx9RcEjCO2ZVomjjRaYzANBgkqhkiG9w0BAQsFAAOCAQEA +TA/Nd2C0b1OH8zxP5oFfpxzMYCm2NGxNCJvi0r32FxpiebgXvKJgWf0DUcO3a95z +s0iV9Quqtjy0NNwdC8SXYofnSNWPyerokY8qQM23s+6ymJ77NzEp5o4vCjmZHsaq +uAVihdOoPmA4mA/w/serAaVqpX9wpiaUdiMvCIl0l8IqyiI+euoiIggH9Lv2vGmc +TkQz4o5wF7CbyzOUZm3/mn3pULLokBTkK5HLoMUuDs8Z70TvhPC9V54mwmM93/yh +hN5c1187+5Rh8JOJH8/DstGQlzV9uYqt5gXw6DuhfK8rxK8YMy5eh9udgLUE/QDQ +YKv/hXcPy0ciybKFqEgW4g== +-----END CERTIFICATE----- diff --git a/debian/revoked-certs/canonical-uefi-2019-all.pem b/debian/revoked-certs/canonical-uefi-2019-all.pem new file mode 100644 index 00000000000000..c4a89e10eb8e22 --- /dev/null +++ b/debian/revoked-certs/canonical-uefi-2019-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 4 (0x4) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 18 16:10:17 2019 GMT + Not After : Sep 16 16:10:17 2049 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2019) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:e6:47:d8:75:e5:87:59:26:87:83:7d:5b:7a:b8: + 58:3d:7c:ef:36:f8:a0:7a:b7:14:56:58:7d:01:f1: + 1c:3b:8c:e6:5b:03:77:7d:a0:ed:47:0a:45:e6:75: + 5c:de:95:38:0d:38:fa:41:79:89:56:31:87:e7:a3: + 9a:36:70:b6:cf:24:2f:99:26:89:08:39:0e:14:c3: + 35:be:02:8b:52:e1:8e:7b:0c:a6:9d:78:ff:01:60: + d7:f5:c3:d5:f0:5e:dc:e4:23:09:59:72:93:d3:b5: + 22:af:7c:cd:e0:84:0f:af:11:2d:bc:c6:72:42:af: + ea:67:63:c4:10:41:78:02:80:62:0d:43:74:b4:1c: + ed:50:d7:94:f1:b0:bb:f9:57:80:e4:69:0f:83:4b: + a2:e6:2c:4a:9a:e1:7d:7c:62:19:29:27:97:1f:4c: + f1:85:f0:39:f5:31:9f:3a:39:0e:d4:4d:07:3a:40: + 55:4b:a6:6c:9d:04:89:51:2d:7c:b0:ef:40:b5:42: + 29:16:cc:65:73:38:62:21:f6:e3:2c:17:50:9d:74: + 34:4e:df:7c:4a:33:a4:bb:40:cf:d5:e5:ed:05:07: + cd:4c:f9:af:7f:a6:5c:b9:f7:c5:16:45:4e:44:40: + d7:85:32:de:ac:e5:75:ad:9b:d7:c0:26:33:1f:77: + a5:37 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + C0:74:6F:D6:C5:DA:3A:E8:27:86:46:51:AD:66:AE:47:FE:24:B3:E8 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + aa:12:6c:d1:9d:6a:da:f0:ec:7c:17:46:3b:57:b8:d6:76:5f: + 24:e6:06:a2:0a:55:1f:2f:d3:5e:8f:de:cf:02:f2:ff:e0:dd: + d3:c7:bd:75:59:aa:cd:34:f3:28:80:73:cc:28:69:e7:a2:70: + 88:a2:c7:dc:66:f0:92:0e:ff:64:bf:30:04:54:01:1b:96:ad: + 15:c5:61:fd:32:61:d7:5e:b5:ba:91:fd:31:fc:6b:15:df:ee: + 22:d9:e4:1f:f3:cc:8b:0c:9f:f5:e8:f7:e2:62:3f:40:52:c9: + f0:f1:1c:63:fc:6c:90:e1:5b:74:03:b9:df:d1:3e:a8:ec:db: + 2b:6e:83:6f:9f:7f:ba:b4:79:fc:3d:e7:12:2f:4a:e7:17:8c: + 2b:77:a5:90:74:3c:bd:cf:75:83:0d:1a:95:d5:56:ef:07:9b: + a6:b3:31:e3:8c:97:ce:68:11:b5:7b:25:03:72:1c:ea:67:e9: + 7c:3e:73:c7:7c:3e:fc:f5:ae:8a:b2:07:0d:15:6a:66:09:d7: + 23:b9:5d:80:7a:26:d6:b6:22:30:aa:84:af:c0:42:e9:75:c3: + 59:ab:a3:84:87:6b:0c:b7:ab:4e:92:69:ae:2c:82:6f:ab:01: + 24:ab:ff:78:6d:59:85:c2:3b:23:c0:bd:0d:d8:6e:3a:29:82: + e1:c4:5f:db +-----BEGIN CERTIFICATE----- +MIIEKDCCAxCgAwIBAgIBBDANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xOTA5MTgxNjEwMTdaFw00OTA5MTYx +NjEwMTdaMIGGMQswCQYDVQQGEwJHQjEUMBIGA1UECAwLSXNsZSBvZiBNYW4xFzAV +BgNVBAoMDkNhbm9uaWNhbCBMdGQuMRQwEgYDVQQLDAtTZWN1cmUgQm9vdDEyMDAG +A1UEAwwpQ2Fub25pY2FsIEx0ZC4gU2VjdXJlIEJvb3QgU2lnbmluZyAoMjAxOSkw +ggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDmR9h15YdZJoeDfVt6uFg9 +fO82+KB6txRWWH0B8Rw7jOZbA3d9oO1HCkXmdVzelTgNOPpBeYlWMYfno5o2cLbP +JC+ZJokIOQ4UwzW+AotS4Y57DKadeP8BYNf1w9XwXtzkIwlZcpPTtSKvfM3ghA+v +ES28xnJCr+pnY8QQQXgCgGINQ3S0HO1Q15TxsLv5V4DkaQ+DS6LmLEqa4X18Yhkp +J5cfTPGF8Dn1MZ86OQ7UTQc6QFVLpmydBIlRLXyw70C1QikWzGVzOGIh9uMsF1Cd +dDRO33xKM6S7QM/V5e0FB81M+a9/ply598UWRU5EQNeFMt6s5XWtm9fAJjMfd6U3 +AgMBAAGjgaAwgZ0wDAYDVR0TAQH/BAIwADAfBgNVHSUEGDAWBggrBgEFBQcDAwYK +KwYBBAGCNwoDBjAsBglghkgBhvhCAQ0EHxYdT3BlblNTTCBHZW5lcmF0ZWQgQ2Vy +dGlmaWNhdGUwHQYDVR0OBBYEFMB0b9bF2jroJ4ZGUa1mrkf+JLPoMB8GA1UdIwQY +MBaAFK2RmQvCKrH1FwSMI7ZlWiaONFpjMA0GCSqGSIb3DQEBCwUAA4IBAQCqEmzR +nWra8Ox8F0Y7V7jWdl8k5gaiClUfL9Nej97PAvL/4N3Tx711WarNNPMogHPMKGnn +onCIosfcZvCSDv9kvzAEVAEblq0VxWH9MmHXXrW6kf0x/GsV3+4i2eQf88yLDJ/1 +6PfiYj9AUsnw8Rxj/GyQ4Vt0A7nf0T6o7NsrboNvn3+6tHn8PecSL0rnF4wrd6WQ +dDy9z3WDDRqV1VbvB5umszHjjJfOaBG1eyUDchzqZ+l8PnPHfD789a6KsgcNFWpm +CdcjuV2AeibWtiIwqoSvwELpdcNZq6OEh2sMt6tOkmmuLIJvqwEkq/94bVmFwjsj +wL0N2G46KYLhxF/b +-----END CERTIFICATE----- diff --git a/debian/revoked-certs/canonical-uefi-2021v1-all.pem b/debian/revoked-certs/canonical-uefi-2021v1-all.pem new file mode 100644 index 00000000000000..a573a2cb7ebf93 --- /dev/null +++ b/debian/revoked-certs/canonical-uefi-2021v1-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 6 (0x6) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 23 19:29:32 2021 GMT + Not After : Sep 22 19:29:32 2051 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v1) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:aa:b8:34:5b:b6:ae:44:bf:41:e1:78:11:b9:7a: + c8:88:b3:b0:26:50:10:9c:98:d1:f3:98:9f:23:50: + 64:f6:39:dd:50:3a:23:44:53:65:fc:f3:9f:f5:a5: + 8b:ae:8b:df:47:9f:e9:d5:a0:92:19:f1:21:ea:cc: + 59:3a:74:df:45:71:bc:de:64:15:a5:f6:db:ca:71: + fa:19:d4:44:0d:12:ec:47:3a:43:e2:f2:dd:8b:fe: + 0d:7b:dc:4d:db:53:06:22:61:e5:8b:35:49:b6:33: + c4:0a:69:5f:5b:81:09:84:6b:42:33:18:09:9d:a0: + 35:f7:9c:1e:de:6e:de:90:69:1a:e8:32:e4:49:ad: + c3:31:e9:f8:4a:a2:28:1d:db:0d:29:b6:48:0a:44: + 93:86:41:62:8f:73:97:60:10:8a:74:46:66:55:fe: + a0:95:35:9e:ef:9f:af:11:fa:5b:a3:7c:c2:35:64: + 11:67:28:1e:14:0a:7d:68:61:9c:cd:c7:46:39:30: + 31:79:94:56:b3:45:16:9a:b5:77:66:fe:41:43:0f: + 00:48:6e:99:dd:0c:d4:47:2c:86:8c:50:04:61:20: + dd:aa:8e:73:4f:21:b4:ee:09:4d:d3:40:01:d0:f2: + a7:5b:7d:05:3d:c1:e7:65:26:aa:8c:9a:58:5a:7c: + 6d:6f + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + A8:D5:4B:BB:38:25:CF:B9:4F:A1:3C:9F:8A:59:4A:19:5C:10:7B:8D + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 24:25:25:7e:01:a5:c8:3d:54:8c:1b:05:73:d1:06:d8:db:d4: + 3a:71:d5:19:9d:97:1c:85:3c:ca:38:5a:0c:25:25:39:1a:67: + bc:6c:9d:98:6c:f3:7d:5f:b7:40:f9:73:a0:f5:7b:40:a8:66: + a5:f1:53:b1:78:80:24:3f:19:50:2f:02:09:ec:a1:8a:e6:0d: + df:c4:ae:24:9e:69:0d:5c:dc:44:4c:38:3a:53:4e:4b:a1:4b: + 92:9f:43:a4:9d:1e:76:33:18:1b:bf:62:e5:f5:bc:93:3c:4e: + 21:d5:5b:20:69:11:28:c1:c5:93:b5:8e:96:1d:1b:ca:72:79: + 24:de:67:2a:50:9d:ce:8b:41:dd:3e:82:dd:a5:04:75:54:fb: + 35:70:98:87:b4:f3:ea:41:23:23:80:0e:99:d7:03:16:ee:7e: + 11:e2:c8:29:ab:73:c5:6d:5c:a8:2f:32:03:9f:8e:66:d6:cb: + 54:84:55:75:ab:9a:dd:95:fd:05:1e:11:85:37:1e:63:d2:f4: + 7f:34:64:32:a1:63:91:91:50:39:14:1a:ea:54:78:e6:0d:04: + 23:c7:83:51:c5:25:27:07:6c:f8:65:b7:da:95:89:76:83:cc: + f3:7e:06:74:d3:6c:ef:e9:17:de:29:1e:ab:5c:d7:ec:df:f1: + 98:b8:e9:66 +-----BEGIN CERTIFICATE----- +MIIELTCCAxWgAwIBAgIBBjANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMTA5MjMxOTI5MzJaGA8yMDUxMDky +MjE5MjkzMlowgYkxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MTUw +MwYDVQQDDCxDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nICgyMDIx +IHYxKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAKq4NFu2rkS/QeF4 +Ebl6yIizsCZQEJyY0fOYnyNQZPY53VA6I0RTZfzzn/Wli66L30ef6dWgkhnxIerM +WTp030VxvN5kFaX228px+hnURA0S7Ec6Q+Ly3Yv+DXvcTdtTBiJh5Ys1SbYzxApp +X1uBCYRrQjMYCZ2gNfecHt5u3pBpGugy5EmtwzHp+EqiKB3bDSm2SApEk4ZBYo9z +l2AQinRGZlX+oJU1nu+frxH6W6N8wjVkEWcoHhQKfWhhnM3HRjkwMXmUVrNFFpq1 +d2b+QUMPAEhumd0M1EcshoxQBGEg3aqOc08htO4JTdNAAdDyp1t9BT3B52Umqoya +WFp8bW8CAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQYMBYGCCsGAQUF +BwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NMIEdlbmVyYXRl +ZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUqNVLuzglz7lPoTyfillKGVwQe40wHwYD +VR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcNAQELBQADggEB +ACQlJX4Bpcg9VIwbBXPRBtjb1Dpx1RmdlxyFPMo4WgwlJTkaZ7xsnZhs831ft0D5 +c6D1e0CoZqXxU7F4gCQ/GVAvAgnsoYrmDd/EriSeaQ1c3ERMODpTTkuhS5KfQ6Sd +HnYzGBu/YuX1vJM8TiHVWyBpESjBxZO1jpYdG8pyeSTeZypQnc6LQd0+gt2lBHVU ++zVwmIe08+pBIyOADpnXAxbufhHiyCmrc8VtXKgvMgOfjmbWy1SEVXWrmt2V/QUe +EYU3HmPS9H80ZDKhY5GRUDkUGupUeOYNBCPHg1HFJScHbPhlt9qViXaDzPN+BnTT +bO/pF94pHqtc1+zf8Zi46WY= +-----END CERTIFICATE----- diff --git a/debian/revoked-certs/canonical-uefi-2021v2-all.pem b/debian/revoked-certs/canonical-uefi-2021v2-all.pem new file mode 100644 index 00000000000000..6c68bcc97ae626 --- /dev/null +++ b/debian/revoked-certs/canonical-uefi-2021v2-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 7 (0x7) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 23 19:29:42 2021 GMT + Not After : Sep 22 19:29:42 2051 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v2) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:ba:06:8b:ee:58:b7:8b:49:7b:53:7a:d1:df:02: + e3:f2:d8:b0:8c:03:5c:f4:2d:0b:d8:18:3b:23:fa: + 68:b0:e8:e9:9d:dc:a2:eb:5e:d3:06:a9:28:d4:9f: + 14:b6:1e:1c:1d:ef:69:0e:7f:44:f2:cc:4a:f1:b1: + d0:71:30:6a:50:1e:b0:d3:f8:a4:19:d0:4a:f1:e3: + eb:7a:e5:57:4c:a1:fb:d1:87:b9:48:e0:55:37:52: + f9:de:99:2e:95:85:36:ce:d3:1d:67:2f:14:cb:7f: + 05:82:75:21:b6:aa:a5:14:ac:da:4a:f4:fe:fa:5c: + 33:49:3d:6f:de:fd:9d:75:ba:e2:c4:02:38:b5:69: + f5:ff:a8:67:4b:3a:e0:34:f6:3b:07:03:a5:7e:59: + 6f:3a:d2:28:a4:2f:25:ac:d8:a9:1f:59:52:5d:24: + 36:58:51:b5:f0:12:a8:d3:78:56:57:b1:e0:a9:df: + 14:05:65:7c:b5:a5:00:f0:88:39:14:44:18:85:2d: + 0c:28:69:7b:b9:b4:1c:47:6f:43:66:4c:22:ad:f7: + f6:19:75:e1:14:2c:0d:33:3f:c1:3f:fc:73:56:b2: + 68:05:b5:92:03:9b:65:6b:81:80:92:35:03:9b:66: + 68:58:c5:66:11:b6:8c:7f:05:09:9a:45:a6:0e:5e: + 5f:bf + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 4C:F0:46:89:2D:6F:D3:C9:A5:B0:3F:98:D8:45:F9:08:51:DC:6A:8C + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 93:9d:49:7d:9f:3e:3e:27:79:97:d9:c2:fc:0b:f7:30:b7:f4: + 78:b2:c9:e4:5e:42:d3:27:26:70:cf:88:96:d1:f2:ea:a0:75: + 7e:3c:f6:b7:d2:e7:95:30:e3:a6:67:a7:ee:b9:53:8f:fd:b2: + cb:db:e1:98:32:be:98:79:09:46:c6:63:6a:57:87:4d:b2:26: + 46:f6:34:5e:18:75:ca:82:80:8e:33:c2:1d:c7:76:d7:14:57: + ef:2e:0e:9e:58:5c:81:8e:ed:53:2c:07:46:0a:8a:fc:2f:f5: + b2:c8:58:f5:fa:fa:bb:f9:7d:47:13:39:f0:f2:1c:15:9c:75: + 90:40:bd:08:04:b3:6a:de:c2:cd:34:21:7e:ba:31:48:bc:a1: + 23:bc:ee:93:b2:62:96:27:30:86:c2:d4:f7:b4:e6:3c:71:47: + 37:84:ff:3d:0c:1e:ec:f3:0e:da:6b:dc:64:7a:b8:c0:7e:45: + 13:09:bf:02:b3:b7:5b:6d:09:2d:6a:4e:0b:93:94:29:4c:a6: + c3:c7:05:fa:69:08:04:53:3c:4c:64:c0:7e:89:00:91:1b:a6: + c2:d7:ea:c4:db:86:38:fe:66:03:85:7b:fc:39:24:99:4c:2a: + 3e:10:8b:91:c3:6e:20:9d:0c:ee:51:70:b5:98:58:f3:5c:ac: + 16:98:7b:ce +-----BEGIN CERTIFICATE----- +MIIELTCCAxWgAwIBAgIBBzANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMTA5MjMxOTI5NDJaGA8yMDUxMDky +MjE5Mjk0MlowgYkxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MTUw +MwYDVQQDDCxDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nICgyMDIx +IHYyKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALoGi+5Yt4tJe1N6 +0d8C4/LYsIwDXPQtC9gYOyP6aLDo6Z3coute0wapKNSfFLYeHB3vaQ5/RPLMSvGx +0HEwalAesNP4pBnQSvHj63rlV0yh+9GHuUjgVTdS+d6ZLpWFNs7THWcvFMt/BYJ1 +IbaqpRSs2kr0/vpcM0k9b979nXW64sQCOLVp9f+oZ0s64DT2OwcDpX5ZbzrSKKQv +JazYqR9ZUl0kNlhRtfASqNN4Vlex4KnfFAVlfLWlAPCIORREGIUtDChpe7m0HEdv +Q2ZMIq339hl14RQsDTM/wT/8c1ayaAW1kgObZWuBgJI1A5tmaFjFZhG2jH8FCZpF +pg5eX78CAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQYMBYGCCsGAQUF +BwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NMIEdlbmVyYXRl +ZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUTPBGiS1v08mlsD+Y2EX5CFHcaowwHwYD +VR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcNAQELBQADggEB +AJOdSX2fPj4neZfZwvwL9zC39HiyyeReQtMnJnDPiJbR8uqgdX489rfS55Uw46Zn +p+65U4/9ssvb4Zgyvph5CUbGY2pXh02yJkb2NF4YdcqCgI4zwh3HdtcUV+8uDp5Y +XIGO7VMsB0YKivwv9bLIWPX6+rv5fUcTOfDyHBWcdZBAvQgEs2rews00IX66MUi8 +oSO87pOyYpYnMIbC1Pe05jxxRzeE/z0MHuzzDtpr3GR6uMB+RRMJvwKzt1ttCS1q +TguTlClMpsPHBfppCARTPExkwH6JAJEbpsLX6sTbhjj+ZgOFe/w5JJlMKj4Qi5HD +biCdDO5RcLWYWPNcrBaYe84= +-----END CERTIFICATE----- diff --git a/debian/revoked-certs/canonical-uefi-2021v3-all.pem b/debian/revoked-certs/canonical-uefi-2021v3-all.pem new file mode 100644 index 00000000000000..679684ed768cfc --- /dev/null +++ b/debian/revoked-certs/canonical-uefi-2021v3-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 8 (0x8) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 23 19:30:02 2021 GMT + Not After : Sep 22 19:30:02 2051 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v3) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:d6:29:96:87:ae:07:42:45:bb:65:09:b2:9b:de: + 5d:8e:78:61:10:d5:6d:ae:ae:26:08:6a:06:ec:4a: + dd:2b:e7:1a:a9:ad:78:e3:fc:cf:8f:d1:47:bd:1e: + 33:d8:7a:e3:66:9b:e9:73:c1:5f:42:e2:fe:bc:c3: + 41:f7:cd:d7:85:d7:42:c9:ea:31:e5:47:b1:93:5b: + 43:2b:07:51:b8:75:08:ad:0f:e7:0d:81:38:5a:21: + df:b1:43:5b:db:37:c5:ac:aa:14:3a:33:19:6a:26: + e0:05:fe:cd:41:31:af:5d:a8:ab:31:77:44:fc:da: + 00:e2:7a:44:33:c3:a7:ed:13:54:9f:19:5d:c9:98: + a2:3b:af:4d:0d:87:29:9c:90:9e:42:9e:9a:06:6a: + 70:27:c5:aa:f7:a2:f2:88:e0:b9:66:9a:72:a0:f6: + 61:7e:30:8f:14:9f:44:0d:dd:54:ae:47:c8:82:ba: + d2:b2:db:6f:24:c1:f4:0a:81:07:90:47:49:5f:57: + d6:3f:bf:2a:73:98:f2:f6:24:1a:74:03:d7:35:f0: + 42:d8:14:c5:94:27:5d:3c:49:0c:b0:f0:7a:61:1b: + d7:5a:e3:a3:40:57:e9:a4:07:ee:02:a3:32:27:94: + bb:f3:36:c5:5f:ef:d3:07:04:3a:80:4c:9c:0a:b7: + 88:9f + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 10:04:37:BB:6D:E6:E4:69:B5:81:E6:1C:D6:6B:CE:3E:F4:ED:53:AF + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 3b:37:d6:a8:8d:cd:d2:df:13:35:ac:8c:92:d6:b0:ac:d1:38: + a8:00:97:47:59:b8:4a:84:8c:80:a5:1d:c7:29:bf:00:66:e5: + 10:40:26:2e:31:f5:e1:13:c0:1b:29:f3:0b:7e:2d:71:d8:db: + e1:32:8f:79:8e:e3:97:0c:40:a9:a0:12:c1:fc:c2:50:88:72: + 44:c5:bc:8b:45:6e:28:fd:d2:37:d6:db:17:cf:4e:61:33:08: + 5a:5d:08:94:73:44:e2:76:00:44:1b:b8:00:a1:86:00:64:8a: + f1:42:32:3c:28:11:67:7c:8b:aa:06:34:74:58:e8:b3:3a:36: + 8d:f6:04:5d:37:f5:66:52:c9:48:b0:a7:6f:34:09:dd:60:2a: + 86:b9:14:f1:09:f6:06:16:56:e0:51:b1:e8:75:7f:fa:37:dc: + e0:98:a7:69:ae:7b:1a:73:89:0d:06:67:cc:01:ef:80:31:45: + 9e:bb:03:2a:eb:89:70:d6:19:b2:c7:ce:bc:81:df:da:c8:6f: + a9:4b:2d:d7:a7:e1:af:c6:e8:fb:f0:61:c9:cd:d2:91:cd:8b: + c2:6c:ef:e0:b6:7f:f1:c4:81:f9:bb:76:9c:26:e3:fa:a1:a0: + cd:5e:05:de:ee:f9:1b:5b:50:0a:8b:0f:47:e3:90:32:ac:2a: + e7:65:02:80 +-----BEGIN CERTIFICATE----- +MIIELTCCAxWgAwIBAgIBCDANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMTA5MjMxOTMwMDJaGA8yMDUxMDky +MjE5MzAwMlowgYkxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MTUw +MwYDVQQDDCxDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nICgyMDIx +IHYzKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBANYploeuB0JFu2UJ +spveXY54YRDVba6uJghqBuxK3SvnGqmteOP8z4/RR70eM9h642ab6XPBX0Li/rzD +QffN14XXQsnqMeVHsZNbQysHUbh1CK0P5w2BOFoh37FDW9s3xayqFDozGWom4AX+ +zUExr12oqzF3RPzaAOJ6RDPDp+0TVJ8ZXcmYojuvTQ2HKZyQnkKemgZqcCfFqvei +8ojguWaacqD2YX4wjxSfRA3dVK5HyIK60rLbbyTB9AqBB5BHSV9X1j+/KnOY8vYk +GnQD1zXwQtgUxZQnXTxJDLDwemEb11rjo0BX6aQH7gKjMieUu/M2xV/v0wcEOoBM +nAq3iJ8CAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQYMBYGCCsGAQUF +BwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NMIEdlbmVyYXRl +ZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUEAQ3u23m5Gm1geYc1mvOPvTtU68wHwYD +VR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcNAQELBQADggEB +ADs31qiNzdLfEzWsjJLWsKzROKgAl0dZuEqEjIClHccpvwBm5RBAJi4x9eETwBsp +8wt+LXHY2+Eyj3mO45cMQKmgEsH8wlCIckTFvItFbij90jfW2xfPTmEzCFpdCJRz +ROJ2AEQbuAChhgBkivFCMjwoEWd8i6oGNHRY6LM6No32BF039WZSyUiwp280Cd1g +Koa5FPEJ9gYWVuBRseh1f/o33OCYp2muexpziQ0GZ8wB74AxRZ67AyrriXDWGbLH +zryB39rIb6lLLden4a/G6PvwYcnN0pHNi8Js7+C2f/HEgfm7dpwm4/qhoM1eBd7u ++RtbUAqLD0fjkDKsKudlAoA= +-----END CERTIFICATE----- diff --git a/debian/revoked-certs/canonical-uefi-uc2019-all.pem b/debian/revoked-certs/canonical-uefi-uc2019-all.pem new file mode 100644 index 00000000000000..1424ebb7a1bb52 --- /dev/null +++ b/debian/revoked-certs/canonical-uefi-uc2019-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 3 (0x3) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Mar 4 10:27:14 2020 GMT + Not After : Mar 3 10:27:14 2050 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (Ubuntu Core 2019) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:b9:10:47:2e:75:5d:f3:10:23:bb:a0:75:d2:fa: + 02:2d:ff:22:df:c1:e6:cd:38:7c:36:0f:ae:74:15: + 6e:a5:34:52:2b:c3:a4:3a:60:d7:06:ee:1d:99:93: + ff:66:91:a3:18:52:2c:8c:58:e6:b4:2f:4b:c5:fb: + 83:e6:f3:19:bd:1b:ca:23:ec:97:1f:d8:f1:9a:f1: + 04:da:da:10:04:53:4b:ec:1d:b6:26:47:7c:bb:8f: + a7:0a:6e:2e:e8:91:e6:c4:bb:64:34:78:3c:fa:09: + 15:1c:8f:9e:eb:04:99:36:22:c6:8d:07:15:0f:b9: + 69:08:fa:ff:4b:45:bd:ba:2b:cd:01:0e:e7:01:23: + c9:e5:7a:39:3b:91:b0:45:3c:d5:77:ba:ca:f9:29: + 3d:11:3f:1c:6b:5b:8e:6c:4b:3f:c9:29:05:cb:59: + d6:b1:c1:c0:2d:56:88:70:27:fa:73:05:5c:c2:11: + d4:27:11:f7:0b:c2:d5:68:d3:1a:cd:ed:d0:e4:10: + ff:34:cb:b7:45:70:34:2c:23:53:b6:9c:30:70:b4: + 5c:d1:e2:64:18:82:8f:62:b1:5e:aa:0b:d4:89:f2: + 1c:53:c4:32:7d:ef:53:ee:9b:6e:02:ab:78:bd:25: + 67:8b:39:36:d8:84:3b:06:99:02:d6:75:73:4e:f2: + f6:b9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + C1:D5:7B:8F:6B:74:3F:23:EE:41:F4:F7:EE:29:2F:06:EE:CA:DF:B9 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 2d:b5:11:a8:d2:a0:af:81:a0:18:22:18:2c:08:d0:f4:63:e8: + 8f:9a:f4:f5:20:dd:eb:22:77:19:9a:1a:09:3d:7f:aa:7d:c9: + 81:bc:26:98:65:94:46:30:4b:c2:51:7c:f7:21:41:63:87:31: + fc:a4:c9:41:28:c7:2e:2a:2e:d8:a8:75:7a:72:77:3b:1b:9f: + 72:15:0d:0c:96:8d:8b:51:f3:ce:37:b6:ca:9f:ca:59:40:4a: + fc:73:7a:94:12:99:aa:c2:8d:52:ce:91:19:2e:b4:da:ff:e5: + 2c:67:74:d9:58:47:38:2f:61:88:c5:cf:a7:48:e1:08:ba:bc: + ec:d5:3a:47:d9:8c:dc:c3:bc:cb:98:2b:79:7a:02:46:ef:85: + 19:2f:03:4b:05:84:eb:56:98:5f:6d:cf:a5:8b:a2:b6:e5:50: + 51:7c:33:44:bd:7a:94:2e:0d:90:39:39:3e:62:60:ae:3a:e2: + f5:17:fa:f1:94:06:1d:ae:a3:f8:19:20:7f:4b:4c:07:c4:e6: + 2d:0d:e5:94:84:51:6d:6f:0f:c4:c6:79:1d:f0:e8:0e:23:9e: + fd:f9:46:2c:b9:ec:97:38:56:7e:b8:13:f6:d2:e1:8e:a5:93: + 02:7b:6e:dd:33:9a:bf:10:a8:1b:3d:fa:c4:f2:15:f0:27:73: + 26:a6:94:d1 +-----BEGIN CERTIFICATE----- +MIIENjCCAx6gAwIBAgIBAzANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMDAzMDQxMDI3MTRaGA8yMDUwMDMw +MzEwMjcxNFowgZIxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MT4w +PAYDVQQDDDVDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nIChVYnVu +dHUgQ29yZSAyMDE5KTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALkQ +Ry51XfMQI7ugddL6Ai3/It/B5s04fDYPrnQVbqU0UivDpDpg1wbuHZmT/2aRoxhS +LIxY5rQvS8X7g+bzGb0byiPslx/Y8ZrxBNraEARTS+wdtiZHfLuPpwpuLuiR5sS7 +ZDR4PPoJFRyPnusEmTYixo0HFQ+5aQj6/0tFvborzQEO5wEjyeV6OTuRsEU81Xe6 +yvkpPRE/HGtbjmxLP8kpBctZ1rHBwC1WiHAn+nMFXMIR1CcR9wvC1WjTGs3t0OQQ +/zTLt0VwNCwjU7acMHC0XNHiZBiCj2KxXqoL1InyHFPEMn3vU+6bbgKreL0lZ4s5 +NtiEOwaZAtZ1c07y9rkCAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQY +MBYGCCsGAQUFBwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NM +IEdlbmVyYXRlZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUwdV7j2t0PyPuQfT37ikv +Bu7K37kwHwYDVR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcN +AQELBQADggEBAC21EajSoK+BoBgiGCwI0PRj6I+a9PUg3esidxmaGgk9f6p9yYG8 +JphllEYwS8JRfPchQWOHMfykyUEoxy4qLtiodXpydzsbn3IVDQyWjYtR8843tsqf +yllASvxzepQSmarCjVLOkRkutNr/5SxndNlYRzgvYYjFz6dI4Qi6vOzVOkfZjNzD +vMuYK3l6AkbvhRkvA0sFhOtWmF9tz6WLorblUFF8M0S9epQuDZA5OT5iYK464vUX ++vGUBh2uo/gZIH9LTAfE5i0N5ZSEUW1vD8TGeR3w6A4jnv35Riy57Jc4Vn64E/bS +4Y6lkwJ7bt0zmr8QqBs9+sTyFfAncyamlNE= +-----END CERTIFICATE----- diff --git a/debian/rules b/debian/rules new file mode 100755 index 00000000000000..4f87ba2dcf796c --- /dev/null +++ b/debian/rules @@ -0,0 +1,202 @@ +#!/usr/bin/make -f +# +# $(DEBIAN)/rules for Ubuntu linux +# +# Use this however you want, just give credit where credit is due. +# +# Copyright (c) 2007 Ben Collins +# + +# Do not use make's built-in rules and variables +# (this increases performance and avoids hard-to-debug behaviour) +MAKEFLAGS += -rR + +# Allow to run debian/rules directly without root +export DEB_RULES_REQUIRES_ROOT := no + +.NOTPARALLEL: + +DEBIAN=$(shell awk -F= '($$1 == "DEBIAN") { print $$2 }' $@ + sed -i -e 's/PKGVER/$(DEB_VERSION_UPSTREAM)/g' \ + -e 's/ABINUM/$(abinum)/g' \ + -e 's/SRCPKGNAME/$(DEB_SOURCE)/g' \ + -e 's/=SERIES=/$(DEB_DISTRIBUTION)/g' \ + -e 's|\(^Maintainer:.*\)|\1\nXSC-Ubuntu-Compatible-Signing: $(UBUNTU_COMPATIBLE_SIGNING)|g' \ + -e 's/\(^Build-Depends:$$\)/\1\n$(GCC_BUILD_DEPENDS)/g' \ + $@ + +debian/canonical-certs.pem: $(wildcard debian/certs/*.pem $(DEBIAN)/certs/*.pem) + for cert in $(sort $(notdir $^)); \ + do \ + for dir in $(DEBIAN) debian; \ + do \ + if [ -f "$$dir/certs/$$cert" ]; then \ + cat "$$dir/certs/$$cert"; \ + break; \ + fi; \ + done; \ + done >"$@" + +debian/canonical-revoked-certs.pem: $(wildcard debian/revoked-certs/*.pem $(DEBIAN)/revoked-certs/*.pem) + for cert in $(sort $(notdir $^)); \ + do \ + for dir in $(DEBIAN) debian; \ + do \ + if [ -f "$$dir/revoked-certs/$$cert" ]; then \ + cat "$$dir/revoked-certs/$$cert"; \ + break; \ + fi; \ + done; \ + done >"$@" + +# delete partially updated (i.e. corrupted) files on error +.DELETE_ON_ERROR: + +# Add FORCE to the prerequisites of a target to force it to be always rebuilt. +.PHONY: FORCE debian/canonical-certs.pem debian/canonical-revoked-certs.pem diff --git a/debian/rules.d/0-common-vars.mk b/debian/rules.d/0-common-vars.mk new file mode 100644 index 00000000000000..60d162b22237ff --- /dev/null +++ b/debian/rules.d/0-common-vars.mk @@ -0,0 +1,225 @@ +gcc:=gcc-15 +# Used when you need to 'escape' a comma. +comma = , +empty := +space := $(empty) $(empty) + +# We cannot include /usr/share/dpkg/pkg-info.mk because the variables defined +# here depend on the $(DEBIAN) directory, which can vary between kernels. +# Instead, this file will define the same variables but using the $(DEBIAN) +# variable to use the correct files. + +# The source package name will be the first token from $(DEBIAN)/changelog +DEB_SOURCE := $(shell dpkg-parsechangelog -l$(DEBIAN)/changelog -S source) + +# Get the series +DEB_DISTRIBUTION := $(shell dpkg-parsechangelog -l$(DEBIAN)/changelog -S distribution | sed -e 's/-\(security\|updates\|proposed\)$$//') + +# Get some version info +DEB_VERSION := $(shell dpkg-parsechangelog -l$(DEBIAN)/changelog -S version) +DEB_REVISION ?= $(lastword $(subst -,$(space),$(DEB_VERSION))) +DEB_VERSION_UPSTREAM := $(patsubst %-$(DEB_REVISION),%,$(DEB_VERSION)) + +DEB_VERSION_PREV ?= $(shell dpkg-parsechangelog -l$(DEBIAN)/changelog -o1 -c1 -S version) +DEB_REVISION_PREV := $(lastword 0.0 $(subst -,$(space),$(DEB_VERSION_PREV))) + +# Get upstream version info +upstream_version := $(shell sed -n 's/^VERSION = \(.*\)$$/\1/p' Makefile) +upstream_patchlevel := $(shell sed -n 's/^PATCHLEVEL = \(.*\)$$/\1/p' Makefile) +upstream_tag := "v$(upstream_version).$(upstream_patchlevel)" + +# Get the kernels own extra version to be added to the release signature. +raw_kernelversion := $(shell make -s kernelversion) + +packages_enabled := $(shell dh_listpackages 2>/dev/null) +define if_package +$(if $(filter $(1),$(packages_enabled)),$(2)) +endef + +stamp = [ -d $(dir $@) ] || mkdir $(dir $@); touch $@ + +# +# do_full_build -- are we doing a full buildd style build, i.e., are we +# building in a PPA +# +ifeq ($(wildcard /CurrentlyBuilding),) + do_full_build ?= false +else + do_full_build ?= true +endif + +# +# The debug packages are ginormous, so you probably want to skip +# building them (as a developer). +# +do_dbgsym_package = true +ifeq ($(do_full_build),false) + do_dbgsym_package = false +endif +ifeq ($(filter $(DEB_BUILD_OPTIONS),noautodbgsym),noautodbgsym) + # Disable debug package builds if we're building in a PPA that has the + # 'Build debug symbols' option disabled + do_dbgsym_package = false +endif + +abinum := $(firstword $(subst .,$(space),$(DEB_REVISION))) +abi_release := $(DEB_VERSION_UPSTREAM)-$(abinum) + +uploadnum := $(patsubst $(abinum).%,%,$(DEB_REVISION)) +ifneq ($(do_full_build),false) + uploadnum := $(uploadnum)-Ubuntu +endif + +DEB_HOST_MULTIARCH ?= $(shell dpkg-architecture -qDEB_HOST_MULTIARCH) +DEB_HOST_GNU_TYPE ?= $(shell dpkg-architecture -qDEB_HOST_GNU_TYPE) +DEB_BUILD_GNU_TYPE ?= $(shell dpkg-architecture -qDEB_BUILD_GNU_TYPE) +DEB_HOST_ARCH ?= $(shell dpkg-architecture -qDEB_HOST_ARCH) +DEB_BUILD_ARCH ?= $(shell dpkg-architecture -qDEB_BUILD_ARCH) + +# +# Detect invocations of the form 'fakeroot debian/rules binary arch=armhf' +# within an x86'en schroot. This only gets you part of the way since the +# packaging phase fails, but you can at least compile the kernel quickly. +# +arch := $(DEB_HOST_ARCH) +CROSS_COMPILE ?= $(DEB_HOST_GNU_TYPE)- + +# +# Set consistent toolchain +# If a given kernel wants to change this, they can do so via their own +# $(DEBIAN)/rules.d/hooks.mk and $(DEBIAN)/rules.d/$(arch).mk files +# +export gcc?=gcc +export rustc?=rustc +export rustfmt?=rustfmt +export bindgen?=bindgen +GCC_BUILD_DEPENDS=\ $(gcc):native, $(gcc)-aarch64-linux-gnu [arm64] , $(gcc)-arm-linux-gnueabihf [armhf] , $(gcc)-powerpc64le-linux-gnu [ppc64el] , $(gcc)-riscv64-linux-gnu [riscv64] , $(gcc)-s390x-linux-gnu [s390x] , $(gcc)-x86-64-linux-gnu [amd64] , + +builddir := $(CURDIR)/debian/build +stampdir := $(CURDIR)/debian/stamps + +# +# The binary package name always starts with linux-image-$KVER-$ABI.$UPLOAD_NUM. There +# are places that you'll find linux-image hard coded, but I guess thats OK since the +# assumption that the binary package always starts with linux-image will never change. +# +bin_pkg_name_signed=linux-image-$(abi_release) +bin_pkg_name_unsigned=linux-image-unsigned-$(abi_release) +mods_pkg_name=linux-modules-$(abi_release) +bldinfo_pkg_name=linux-buildinfo-$(abi_release) +hdrs_pkg_name=linux-headers-$(abi_release) +rust_pkg_name=linux-lib-rust-$(abi_release) +indep_hdrs_pkg_name=$(DEB_SOURCE)-headers-$(abi_release) + +# +# Similarly with the linux-source package, you need not build it as a developer. Its +# somewhat I/O intensive and utterly useless. +# +do_source_package=true +do_source_package_content=true +ifeq ($(do_full_build),false) +do_source_package_content=false +endif + +# common headers normally is built as an indep package, but may be arch +do_common_headers_indep=true + +# build tools +ifneq ($(wildcard $(CURDIR)/tools),) + do_tools?=true +else + do_tools?=false +endif +bpftool_pkg_name=bpftool +perf_pkg_name=linux-perf +tools_pkg_name=$(DEB_SOURCE)-tools-$(abi_release) +tools_common_pkg_name=linux-tools-common +tools_flavour_pkg_name=linux-tools-$(abi_release) +cloud_pkg_name=$(DEB_SOURCE)-cloud-tools-$(abi_release) +cloud_common_pkg_name=linux-cloud-tools-common +cloud_flavour_pkg_name=linux-cloud-tools-$(abi_release) +hosttools_pkg_name=linux-tools-host + +# The general flavour specific image package. +do_flavour_image_package=true + +# The general flavour specific header package. +do_flavour_header_package=true + +# DTBs +do_dtbs=false + +# Stubble +do_stubble=false + +# ZSTD compressed kernel modules +do_zstd_ko=true +ifeq ($(DEB_DISTRIBUTION),jammy) +do_zstd_ko= +endif + +# Support parallel= in DEB_BUILD_OPTIONS (see #209008) +# +# These 2 environment variables set the -j value of the kernel build. For example, +# CONCURRENCY_LEVEL=16 fakeroot $(DEBIAN)/rules binary-debs +# or +# DEB_BUILD_OPTIONS=parallel=16 fakeroot $(DEBIAN)/rules binary-debs +# +# The default is to use the number of CPUs. +# +COMMA=, +DEB_BUILD_OPTIONS_PARA = $(subst parallel=,,$(filter parallel=%,$(subst $(COMMA), ,$(DEB_BUILD_OPTIONS)))) +ifneq (,$(DEB_BUILD_OPTIONS_PARA)) + CONCURRENCY_LEVEL := $(DEB_BUILD_OPTIONS_PARA) +endif + +ifeq ($(CONCURRENCY_LEVEL),) + # Check the environment + CONCURRENCY_LEVEL := $(shell echo $$CONCURRENCY_LEVEL) + # No? Then build with the number of CPUs on the host. + ifeq ($(CONCURRENCY_LEVEL),) + CONCURRENCY_LEVEL := $(shell expr `getconf _NPROCESSORS_ONLN` \* 1) + endif + # Oh hell, give 'em one + ifeq ($(CONCURRENCY_LEVEL),) + CONCURRENCY_LEVEL := 1 + endif +endif + +conc_level = -j$(CONCURRENCY_LEVEL) + +PYTHON ?= $(firstword $(wildcard /usr/bin/python3) $(wildcard /usr/bin/python2) $(wildcard /usr/bin/python)) + +HOSTCC ?= $(DEB_BUILD_GNU_TYPE)-$(gcc) + +# $* is the flavour name which is filled in for each step +kmake = make ARCH=$(build_arch) \ + CROSS_COMPILE=$(CROSS_COMPILE) \ + HOSTCC=$(HOSTCC) \ + CC=$(CROSS_COMPILE)$(gcc) \ + RUSTC=$(rustc) \ + HOSTRUSTC=$(rustc) \ + RUSTFMT=$(rustfmt) \ + BINDGEN=$(bindgen) \ + KERNELRELEASE=$(abi_release)-$* \ + CONFIG_DEBUG_SECTION_MISMATCH=y \ + KBUILD_BUILD_VERSION="$(uploadnum)" \ + CFLAGS_MODULE="-DPKG_ABI=$(abinum)" \ + PYTHON=$(PYTHON) +ifneq ($(LOCAL_ENV_CC),) +kmake += CC="$(LOCAL_ENV_CC)" DISTCC_HOSTS="$(LOCAL_ENV_DISTCC_HOSTS)" +endif + +# Locking is required in parallel builds to prevent loss of contents +# of the debian/files. +lockme = flock -w 60 $(CURDIR)/debian/.LOCK + +# Don't fail if a link already exists. +LN = ln -sf + +# Checks if a var is overriden by the custom rules. Called with var and +# flavour as arguments. +custom_override = $(or $($(1)_$(2)),$($(1))) + +# selftests that Ubuntu cares about +ubuntu_selftests = breakpoints cpu-hotplug efivarfs memfd memory-hotplug mount net ptrace seccomp timers powerpc user ftrace diff --git a/debian/rules.d/1-maintainer.mk b/debian/rules.d/1-maintainer.mk new file mode 100644 index 00000000000000..63b39201d7756d --- /dev/null +++ b/debian/rules.d/1-maintainer.mk @@ -0,0 +1,135 @@ +# The following targets are for the maintainer only! do not run if you don't +# know what they do. + +.PHONY: help +help: + @echo "These are the targets in addition to the normal $(DEBIAN) ones:" + @echo + @echo " printenv : Print some variables used in the build" + @echo " updateconfigs : Update core arch configs" + @echo " defaultconfigs : Update core arch configs using defaults" + @echo " genconfigs : Generate core arch configs in CONFIGS/*" + @echo " editconfigs : Edit core arch configs" + @echo " printchanges : Print the current changelog entries (from git)" + @echo " insertchanges : Insert current changelog entries (from git)" + @echo " compileselftests : Only compile the selftests listed on ubuntu_selftests variable" + @echo " runselftests : Run the selftests listed on ubuntu_selftests variable" + @echo + @echo "Environment variables:" + @echo + @echo " CONCURRENCY_LEVEL=X : Use -jX for kernel compile" + +.PHONY: printdebian +printdebian: + @echo "$(DEBIAN)" + +configs-targets := updateconfigs defaultconfigs genconfigs editconfigs + +.PHONY: $(configs-targets) +$(configs-targets): + dh_testdir + kmake='$(kmake)' skip_checks=$(do_skip_checks) conc_level=$(conc_level) \ + $(SHELL) debian/scripts/misc/kernelconfig $@ + +.PHONY: printenv +printenv: + @dh_testdir + @echo "DEB_SOURCE = $(DEB_SOURCE)" + @echo "DEB_DISTRIBUTION = $(DEB_DISTRIBUTION)" + @echo "DEB_VERSION_UPSTREAM = $(DEB_VERSION_UPSTREAM)" + @echo "DEB_REVISION = $(DEB_REVISION)" + @echo "uploadnum = $(uploadnum)" + @echo "abinum = $(abinum)" + @echo "upstream_tag = $(upstream_tag)" + @echo "flavours = $(flavours)" + @echo "bin_pkg_name = $(bin_pkg_name)" + @echo "hdr_pkg_name = $(hdrs_pkg_name)" + @echo "rust_pkg_name = $(rust_pkg_name)" + @echo "ubuntu_selftests = $(ubuntu_selftests)" + @echo "arch = $(arch)" + @echo "kmake = $(kmake)" + @echo + @echo "CONCURRENCY_LEVEL = $(CONCURRENCY_LEVEL)" + @echo "DEB_HOST_GNU_TYPE = $(DEB_HOST_GNU_TYPE)" + @echo "DEB_BUILD_GNU_TYPE = $(DEB_BUILD_GNU_TYPE)" + @echo "DEB_HOST_ARCH = $(DEB_HOST_ARCH)" + @echo "DEB_BUILD_ARCH = $(DEB_BUILD_ARCH)" + @echo + @echo "any_signed = $(any_signed)" + @echo " uefi_signed = $(uefi_signed)" + @echo " opal_signed = $(opal_signed)" + @echo " sipl_signed = $(sipl_signed)" + @echo + @echo "do_skip_checks = $(do_skip_checks)" + @echo "do_full_build = $(do_full_build)" + @echo "do_mainline_build = $(do_mainline_build)" + @echo "do_stubble" = $(do_stubble)" + @echo "do_dbgsym_package = $(do_dbgsym_package)" + @echo "do_dtbs = $(do_dtbs)" + @echo "do_source_package = $(do_source_package)" + @echo "do_source_package_content = $(do_source_package_content)" + @echo "do_flavour_image_package = $(do_flavour_image_package)" + @echo "do_flavour_header_package = $(do_flavour_header_package)" + @echo "do_common_headers_indep = $(do_common_headers_indep)" + @echo "do_lib_rust = $(do_lib_rust)" + @echo "do_tools = $(do_tools)" + @echo "do_tools_common = $(do_tools_common)" + @echo "do_any_tools = $(do_any_tools)" + @echo "do_linux_tools = $(do_linux_tools)" + @echo " do_tools_acpidbg = $(do_tools_acpidbg)" + @echo " do_tools_bpftool = $(do_tools_bpftool)" + @echo " do_tools_cpupower = $(do_tools_cpupower)" + @echo " do_tools_host = $(do_tools_host)" + @echo " do_tools_perf = $(do_tools_perf)" + @echo " do_tools_perf_jvmti = $(do_tools_perf_jvmti)" + @echo " do_tools_perf_python = $(do_tools_perf_python)" + @echo " do_tools_rtla = $(do_tools_rtla)" + @echo " do_tools_usbip = $(do_tools_usbip)" + @echo " do_tools_x86 = $(do_tools_x86)" + @echo "do_cloud_tools = $(do_cloud_tools)" + @echo " do_tools_hyperv = $(do_tools_hyperv)" + @echo + @echo "all_dkms_modules = $(all_dkms_modules)" + @$(foreach mod,$(all_dkms_modules),$(foreach var,$(do_$(mod)),\ + printf " %-24s = %s\n" "do_$(mod)" "$(var)";)) + +.PHONY: printchanges +printchanges: + @baseCommit=$$(git log --pretty=format:'%H %s' | \ + gawk '/UBUNTU: '".*Ubuntu-.*`echo $(DEB_VERSION_PREV) | sed 's/+/\\\\+/'`"'(~.*)?$$/ { print $$1; exit }'); \ + if [ -z "$$baseCommit" ]; then \ + echo "WARNING: couldn't find a commit for the previous version. Using the lastest one." >&2; \ + baseCommit=$$(git log --pretty=format:'%H %s' | \ + gawk '/UBUNTU:\s*Ubuntu-.*$$/ { print $$1; exit }'); \ + fi; \ + git log "$$baseCommit"..HEAD | \ + debian/scripts/misc/git-ubuntu-log + +.PHONY: insertchanges +insertchanges: autoreconstruct finalchecks + debian/scripts/misc/insert-changes debian $(DEBIAN) + +.PHONY: autoreconstruct +autoreconstruct: + # No need for reconstruct for -rc kernels since we don't upload an + # orig tarball, so just remove it. + if grep -q "^EXTRAVERSION = -rc[0-9]\+$$" Makefile; then \ + echo "exit 0" >$(DEBIAN)/reconstruct; \ + else \ + debian/scripts/misc/gen-auto-reconstruct $(upstream_tag) $(DEBIAN)/reconstruct debian/source/options; \ + fi + +.PHONY: finalchecks +finalchecks: debian/control + debian/scripts/checks/final-checks "$(DEBIAN)" "$(DEB_VERSION_PREV)" $(do_skip_checks) + +.PHONY: compileselftests +compileselftests: + # a loop is needed here to fail on errors + for test in $(ubuntu_selftests); do \ + $(kmake) -C tools/testing/selftests TARGETS="$$test"; \ + done; + +.PHONY: runselftests +runselftests: + $(kmake) -C tools/testing/selftests TARGETS="$(ubuntu_selftests)" run_tests diff --git a/debian/rules.d/2-binary-arch.mk b/debian/rules.d/2-binary-arch.mk new file mode 100644 index 00000000000000..135baab28fe141 --- /dev/null +++ b/debian/rules.d/2-binary-arch.mk @@ -0,0 +1,775 @@ +# We don't want make removing intermediary stamps +.SECONDARY : + +# Per-flavor variables (evaluated at runtime) +abi_dir = $(builddir)/abi-$* +build_dir = $(builddir)/build-$* + +# TODO this is probably wrong, and should be using $(DEB_HOST_MULTIARCH) +shlibdeps_opts = $(if $(CROSS_COMPILE),-- -l$(CROSS_COMPILE:%-=/usr/%)/lib) + +# These are used by binary-perarch target. +BPFTOOL_VERSION_MAJOR = $(shell sed -ne \ + 's,^#define LIBBPF_MAJOR_VERSION \(.*\)$$,\1,p' \ + tools/lib/bpf/libbpf_version.h) +BPFTOOL_VERSION_MINOR = $(shell sed -ne \ + 's,^#define LIBBPF_MINOR_VERSION \(.*\)$$,\1,p' \ + tools/lib/bpf/libbpf_version.h) +BPFTOOL_VERSION_PATCH = $(shell sed -ne \ + 's,^#define BPFTOOL_PATCH_VERSION \(.*\)$$,\1,p' \ + tools/bpf/bpftool/main.c) +BPFTOOL_VERSION = $(shell expr $(BPFTOOL_VERSION_MAJOR) + 6).$(BPFTOOL_VERSION_MINOR).$(BPFTOOL_VERSION_PATCH) +BPFTOOL_GENCONTROL_ARGS = -v$(BPFTOOL_VERSION)+$(DEB_VERSION) +ifneq ($(DEB_HOST_ARCH),$(DEB_BUILD_ARCH)) +# Use system bpftool when cross-building +BPFTOOL_PATH = /usr/sbin/bpftool +else +BPFTOOL_PATH = $(builddirpa)/tools/bpf/bpftool/bpftool +endif + +# Pick LLVM version from the build-depends +LLVM_VERSION = $(shell sed -n -r '/^Build/,/^$$/s/.*llvm-([0-9]+)-dev.*/\1/p' debian/control) + +debian/scripts/fix-filenames: debian/scripts/fix-filenames.c + $(HOSTCC) $^ -o $@ + +$(stampdir)/stamp-prepare-%: debian/scripts/fix-filenames + @echo Debug: $@ + install -d $(build_dir) + touch $(build_dir)/ubuntu-build + python3 debian/scripts/misc/annotations --export --arch $(arch) --flavour $* > $(build_dir)/.config + sed -i 's/.*CONFIG_VERSION_SIGNATURE.*/CONFIG_VERSION_SIGNATURE="Ubuntu $(DEB_VERSION_UPSTREAM)-$(DEB_REVISION)-$* $(raw_kernelversion)"/' $(build_dir)/.config + find $(build_dir) -name "*.ko" | xargs rm -f + $(kmake) O=$(build_dir) $(conc_level) rustavailable || true + $(kmake) O=$(build_dir) $(conc_level) olddefconfig +ifneq ($(do_skip_checks),true) + python3 debian/scripts/misc/annotations -f $(CURDIR)/$(DEBIAN)/config/annotations \ + --arch $(arch) --flavour $* --check $(build_dir)/.config +endif + $(stamp) + +# Used by developers as a shortcut to prepare a tree for compilation. +prepare-%: $(stampdir)/stamp-prepare-% + @echo Debug: $@ +# Used by developers to allow efficient pre-building without fakeroot. +build-%: $(stampdir)/stamp-install-% + @echo Debug: $@ + +# Do the actual build, including image and modules +$(stampdir)/stamp-build-%: bldimg = $(call custom_override,build_image,$*) +$(stampdir)/stamp-build-%: $(stampdir)/stamp-build-perarch $(stampdir)/stamp-prepare-% + @echo Debug: $@ build_image $(build_image) bldimg $(bldimg) + $(kmake) O=$(build_dir) $(conc_level) $(bldimg) modules $(if $(filter true,$(do_dtbs)),dtbs) + +ifeq ($(do_dbgsym_package),true) + # The target scripts_gdb is part of "all", so we need to call it manually + if grep -q CONFIG_GDB_SCRIPTS=y $(build_dir)/.config; then \ + $(kmake) O=$(build_dir) $(conc_level) scripts_gdb ; \ + fi +endif + +ifeq ($(do_linux_tools),true) + ifeq ($(do_tools_bpftool),true) + ifeq ($(do_tools_bpftool_stub),true) + echo '#error "Kernel does not support CONFIG_DEBUG_INFO_BTF"' > $(build_dir)/vmlinux.h + else + $(BPFTOOL_PATH) btf dump file $(build_dir)/vmlinux format c > $(build_dir)/vmlinux.h + endif + endif +endif + $(stamp) + +define build_dkms_sign = + $(shell set -x; if grep -q CONFIG_MODULE_SIG=y $(1)/.config; then + echo $(1)/scripts/sign-file $(MODHASHALGO) $(MODSECKEY) $(MODPUBKEY); + else + echo "-"; + fi + ) +endef +define build_dkms = + rc=0; unset MAKEFLAGS; ARCH=$(build_arch) CROSS_COMPILE=$(CROSS_COMPILE) $(SHELL) debian/scripts/dkms-build $(dkms_dir) $(abi_release)-$* '$(call build_dkms_sign,$(build_dir))' $(1) $(2) $(3) $(4) $(5) || rc=$$?; if [ "$$rc" = "9" -o "$$rc" = "77" ]; then echo do_$(4)_$*=false >> $(builddir)/skipped-dkms.mk; rc=0; fi; if [ "$$rc" != "0" ]; then exit $$rc; fi +endef + +define install_control = + for which in $(3); \ + do \ + template="debian/templates/$(2).$$which.in"; \ + script="debian/$(1).$$which"; \ + sed -e 's/@abiname@/$(abi_release)/g' \ + -e 's/@localversion@/-$*/g' \ + -e 's/@image-stem@/$(instfile)/g' \ + <"$$template" >"$$script"; \ + done +endef + +# Ensure the directory prefix is exactly 140 characters long so pathnames are the +# exact same length in any binary files produced by the builds. These will be +# commonised later. +dkms_20d=.................... +dkms_140d=$(dkms_20d)$(dkms_20d)$(dkms_20d)$(dkms_20d)$(dkms_20d)$(dkms_20d)$(dkms_20d) +dkms_140c=$(shell echo '$(dkms_140d)' | sed -e 's/\./_/g') +define dkms_dir_prefix = +$(shell echo $(1)/$(dkms_140c) | \ + sed -e 's/\($(dkms_140d)\).*/\1/' -e 's/^\(.*\)....$$/\1dkms/') +endef + +# Install the finished build +$(stampdir)/stamp-install-%: pkgdir_bin = $(CURDIR)/debian/$(bin_pkg_name)-$* +$(stampdir)/stamp-install-%: pkgdir = $(CURDIR)/debian/$(mods_pkg_name)-$* +$(stampdir)/stamp-install-%: pkgdir_bldinfo = $(CURDIR)/debian/$(bldinfo_pkg_name)-$* +$(stampdir)/stamp-install-%: bindoc = $(pkgdir)/usr/share/doc/$(bin_pkg_name)-$* +$(stampdir)/stamp-install-%: dbgpkgdir = $(CURDIR)/debian/$(bin_pkg_name)-$*-dbgsym +$(stampdir)/stamp-install-%: signingv = $(CURDIR)/debian/$(bin_pkg_name)-signing/$(DEB_VERSION_UPSTREAM)-$(DEB_REVISION) +$(stampdir)/stamp-install-%: toolspkgdir = $(CURDIR)/debian/$(tools_flavour_pkg_name)-$* +$(stampdir)/stamp-install-%: cloudpkgdir = $(CURDIR)/debian/$(cloud_flavour_pkg_name)-$* +$(stampdir)/stamp-install-%: bpfdevpkgdir = $(CURDIR)/debian/linux-bpf-dev +$(stampdir)/stamp-install-%: bpftoolpkgdir = $(CURDIR)/debian/$(bpftool_pkg_name) +$(stampdir)/stamp-install-%: perfpkgdir = $(CURDIR)/debian/$(perf_pkg_name) +$(stampdir)/stamp-install-%: basepkg = $(hdrs_pkg_name) +$(stampdir)/stamp-install-%: baserustpkg = $(rust_pkg_name) +$(stampdir)/stamp-install-%: indeppkg = $(indep_hdrs_pkg_name) +$(stampdir)/stamp-install-%: kernfile = $(call custom_override,kernel_file,$*) +$(stampdir)/stamp-install-%: instfile = $(call custom_override,install_file,$*) +$(stampdir)/stamp-install-%: hdrdir = $(CURDIR)/debian/$(basepkg)-$*/usr/src/$(basepkg)-$* +$(stampdir)/stamp-install-%: rustdir = $(CURDIR)/debian/$(baserustpkg)-$*/usr/src/$(baserustpkg)-$* +$(stampdir)/stamp-install-%: MODHASHALGO=sha512 +$(stampdir)/stamp-install-%: MODSECKEY=$(build_dir)/certs/signing_key.pem +$(stampdir)/stamp-install-%: MODPUBKEY=$(build_dir)/certs/signing_key.x509 +$(stampdir)/stamp-install-%: dkms_dir=$(call dkms_dir_prefix,$(build_dir)) +$(stampdir)/stamp-install-%: STUBBLEDTBS = $(shell /usr/libexec/stubble/finddtbs.py $(build_dir)/arch/arm64/boot/dts /usr/share/stubble/hwids 2>/dev/null | sed 's|.*|--devicetree-auto=&|' | tr '\n' ' ') +$(foreach _m,$(all_dkms_modules), \ + $(eval $$(stampdir)/stamp-install-%: enable_$(_m) = $$(filter true,$$(call custom_override,do_$(_m),$$*))) \ + $(eval $$(stampdir)/stamp-install-%: dkms_$(_m)_pkgdir = $$(CURDIR)/debian/$(dkms_$(_m)_pkg_name)-$$*) \ +) +$(stampdir)/stamp-install-%: dbgpkgdir_dkms = $(if $(filter true,$(do_dbgsym_package)),$(dbgpkgdir)/usr/lib/debug/usr/lib/modules/$(abi_release)-$*/kernel,"") +$(stampdir)/stamp-install-%: $(stampdir)/stamp-install-headers $(stampdir)/stamp-build-% + @echo Debug: $@ kernel_file $(kernel_file) kernfile $(kernfile) install_file $(install_file) instfile $(instfile) + dh_testdir + dh_prep -p$(bin_pkg_name)-$* + dh_prep -p$(mods_pkg_name)-$* + dh_prep -p$(hdrs_pkg_name)-$* +ifeq ($(do_lib_rust),true) + dh_prep -p$(rust_pkg_name)-$* +endif + $(foreach _m,$(all_standalone_dkms_modules), \ + $(if $(enable_$(_m)),dh_prep -p$(dkms_$(_m)_pkg_name)-$*;)\ + ) +ifeq ($(do_dbgsym_package),true) + dh_prep -p$(bin_pkg_name)-$*-dbgsym +endif +ifeq ($(do_linux_tools),true) + ifeq ($(do_tools_bpftool),true) + ifneq ($(filter linux-bpf-dev,$(packages_enabled)),) + # Do this only for the primary (first) flavor + # linux-bpf-dev is broken: It provides vmlinux.h which is a flavored header file! + if [ $* = $(firstword $(flavours)) ] ; then \ + dh_prep -plinux-bpf-dev ; \ + fi + endif + endif +endif + + install -d $(pkgdir)/boot + install -m644 $(build_dir)/.config \ + $(pkgdir)/boot/config-$(abi_release)-$* + install -m600 $(build_dir)/System.map \ + $(pkgdir)/boot/System.map-$(abi_release)-$* + +ifeq ($(do_stubble),true) + # Build kernel+stub image + /usr/bin/ukify build --linux=$(build_dir)/$(kernfile) \ + --stub=/usr/lib/stubble/stubble.efi \ + --hwids=/usr/share/stubble/hwids \ + --sbat="@/usr/share/stubble/sbat" \ + $(STUBBLEDTBS) \ + --output=$(build_dir)/$(kernfile).stubble + + # The main image + install -m600 -D $(build_dir)/$(kernfile).stubble \ + $(pkgdir)/boot/$(instfile)-$(abi_release)-$* +else + # The main image + install -m600 -D $(build_dir)/$(kernfile) \ + $(pkgdir_bin)/boot/$(instfile)-$(abi_release)-$* +endif + +ifeq ($(do_dtbs),true) + $(kmake) O=$(build_dir) $(conc_level) dtbs_install \ + INSTALL_DTBS_PATH=$(pkgdir)/usr/lib/firmware/$(abi_release)-$*/device-tree +endif + +ifeq ($(no_dumpfile),) + makedumpfile -g $(pkgdir)/boot/vmcoreinfo-$(abi_release)-$* \ + -x $(build_dir)/vmlinux + chmod 0600 $(pkgdir)/boot/vmcoreinfo-$(abi_release)-$* +endif + + $(kmake) O=$(build_dir) $(conc_level) modules_install $(vdso) \ + INSTALL_MOD_STRIP=1 INSTALL_MOD_PATH=$(pkgdir)/usr + + # + # Build module blacklists: + # - blacklist all watchdog drivers (LP:1432837) + # + install -d $(pkgdir)/usr/lib/modprobe.d + echo "# Kernel supplied blacklist for $(DEB_SOURCE) $(abi_release)-$* $(arch)" \ + >$(pkgdir)/usr/lib/modprobe.d/blacklist_$(DEB_SOURCE)_$(abi_release)-$*.conf + for conf in $(arch)-$* $(arch) common.conf; do \ + if [ -f $(DEBIAN)/modprobe.d/$$conf ]; then \ + echo "# modprobe.d/$$conf"; \ + cat $(DEBIAN)/modprobe.d/$$conf; \ + fi; \ + done >>$(pkgdir)/usr/lib/modprobe.d/blacklist_$(DEB_SOURCE)_$(abi_release)-$*.conf + echo "# Autogenerated watchdog blacklist" \ + >>$(pkgdir)/usr/lib/modprobe.d/blacklist_$(DEB_SOURCE)_$(abi_release)-$*.conf + ls -1 $(pkgdir)/usr/lib/modules/$(abi_release)-$*/kernel/drivers/watchdog/ | \ + grep -v '^bcm2835_wdt.ko$$' | \ + grep -v '^sbsa_gwdt.ko$$' | \ + sed -e 's/^/blacklist /' -e 's/.ko$$//' | \ + sort -u \ + >>$(pkgdir)/usr/lib/modprobe.d/blacklist_$(DEB_SOURCE)_$(abi_release)-$*.conf + +ifeq ($(no_dumpfile),) + makedumpfile -g $(pkgdir)/boot/vmcoreinfo-$(abi_release)-$* \ + -x $(build_dir)/vmlinux + chmod 0600 $(pkgdir)/boot/vmcoreinfo-$(abi_release)-$* +endif + rm -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/build + rm -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/source + + # Some initramfs-tools specific modules + install -d $(pkgdir)/usr/lib/modules/$(abi_release)-$*/initrd + if [ -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/kernel/drivers/video/vesafb.ko ]; then\ + $(LN) $(pkgdir)/usr/lib/modules/$(abi_release)-$*/kernel/drivers/video/vesafb.ko \ + $(pkgdir)/usr/lib/modules/$(abi_release)-$*/initrd/; \ + fi + + echo "interest linux-update-$(abi_release)-$*" >"debian/$(bin_pkg_name)-$*.triggers" + install -d $(pkgdir_bin)/usr/lib/linux/triggers + $(call install_control,$(bin_pkg_name)-$*,image,postinst postrm preinst prerm) + install -d $(pkgdir)/usr/lib/linux/triggers + $(call install_control,$(mods_pkg_name)-$*,extra,postinst postrm) + $(foreach _m,$(all_standalone_dkms_modules), \ + $(if $(enable_$(_m)), \ + install -d $(dkms_$(_m)_pkgdir)/usr/lib/linux/triggers; \ + $(call install_control,$(dkms_$(_m)_pkg_name)-$*,extra,postinst postrm); \ + ) \ + ) + +ifeq ($(do_dbgsym_package),true) + # Debug image is simple + install -m644 -D $(build_dir)/vmlinux \ + $(dbgpkgdir)/usr/lib/debug/boot/vmlinux-$(abi_release)-$* + if [ -d $(build_dir)/scripts/gdb/linux ]; then \ + install -m644 -D $(build_dir)/vmlinux-gdb.py \ + $(dbgpkgdir)/usr/share/gdb/auto-load/boot/vmlinux-$(abi_release)-$*/vmlinuz-$(abi_release)-$*-gdb.py; \ + fi + $(kmake) O=$(build_dir) modules_install $(vdso) \ + INSTALL_MOD_PATH=$(dbgpkgdir)/usr/lib/debug + # Add .gnu_debuglink sections only after all/DKMS modules are built. + rm -f $(dbgpkgdir)/usr/lib/debug/usr/lib/modules/$(abi_release)-$*/build + rm -f $(dbgpkgdir)/usr/lib/debug/usr/lib/modules/$(abi_release)-$*/source + rm -f $(dbgpkgdir)/usr/lib/debug/usr/lib/modules/$(abi_release)-$*/modules.* + rm -fr $(dbgpkgdir)/usr/lib/debug/lib/firmware +endif + + # The flavour specific headers image + # TODO: Would be nice if we didn't have to dupe the original builddir + install -d -m755 $(hdrdir) + cp $(build_dir)/.config $(hdrdir) + chmod 644 $(hdrdir)/.config + $(kmake) O=$(hdrdir) -j1 syncconfig prepare scripts + # Makefile may need per-arch-flavour CC settings, which are + # normally set via $(kmake) during build + rm -f $(hdrdir)/Makefile + cp -a $(indep_hdrdir)/Makefile $(hdrdir)/Makefile + sed -i 's|\(^HOSTCC = \)gcc$$|\1$(gcc)|' $(hdrdir)/Makefile + sed -i 's|\(^CC = $$(CROSS_COMPILE)\)gcc$$|\1$(gcc)|' $(hdrdir)/Makefile + # Quick check for successful substitutions + grep '^HOSTCC .*$(gcc)$$' $(hdrdir)/Makefile + grep '^CC .*$(gcc)$$' $(hdrdir)/Makefile + rm -rf $(hdrdir)/include2 $(hdrdir)/source + # Copy over the compilation version. + cp "$(build_dir)/include/generated/compile.h" \ + "$(hdrdir)/include/generated/compile.h" + # Add UTS_UBUNTU_RELEASE_ABI since UTS_RELEASE is difficult to parse. + echo "#define UTS_UBUNTU_RELEASE_ABI $(abinum)" >> $(hdrdir)/include/generated/utsrelease.h + # powerpc kernel arch seems to need some .o files for external module linking. Add them in. +ifeq ($(build_arch),powerpc) + mkdir -p $(hdrdir)/arch/powerpc/lib + cp $(build_dir)/arch/powerpc/lib/*.o $(hdrdir)/arch/powerpc/lib +endif +ifeq ($(build_arch),s390) + if [ -n "$$(find $(build_dir)/arch/s390/lib/expoline -maxdepth 1 -name '*.o' -print -quit)" ]; then \ + mkdir -p $(hdrdir)/arch/s390/lib/expoline/; \ + cp $(build_dir)/arch/s390/lib/expoline/*.o $(hdrdir)/arch/s390/lib/expoline/; \ + fi +endif + # Copy over scripts/module.lds for building external modules + cp $(build_dir)/scripts/module.lds $(hdrdir)/scripts + # Script to symlink everything up + $(SHELL) debian/scripts/link-headers "$(hdrdir)" "$(indeppkg)" "$*" + # The build symlink + install -d debian/$(basepkg)-$*/usr/lib/modules/$(abi_release)-$* + $(LN) /usr/src/$(basepkg)-$* \ + debian/$(basepkg)-$*/usr/lib/modules/$(abi_release)-$*/build + # And finally the symvers + install -m644 $(build_dir)/Module.symvers \ + $(hdrdir)/Module.symvers + + # Now the header scripts + $(call install_control,$(hdrs_pkg_name)-$*,headers,postinst) + + # At the end of the package prep, run the module signature check + debian/scripts/checks/module-signature-check "$*" "$(pkgdir)" $(do_skip_checks) + + # + # Remove files which are generated at installation by postinst, + # except for modules.order and modules.builtin + # + # NOTE: need to keep this list in sync with postrm + # + mkdir $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_ + mv $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.order \ + $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_ + if [ -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin ] ; then \ + mv $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin \ + $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_; \ + fi + if [ -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin.modinfo ] ; then \ + mv $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin.modinfo \ + $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_; \ + fi + rm -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.* + mv $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_/* \ + $(pkgdir)/usr/lib/modules/$(abi_release)-$* + rmdir $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_ + +ifeq ($(do_linux_tools),true) + # Create the linux-tools tool link + install -d $(toolspkgdir)/usr/lib/linux-tools + $(LN) ../$(DEB_SOURCE)-tools-$(abi_release) $(toolspkgdir)/usr/lib/linux-tools/$(abi_release)-$* + ifeq ($(do_tools_bpftool),true) + ifneq ($(filter linux-bpf-dev,$(packages_enabled)),) + # Do this only for the primary (first) flavor + # linux-bpf-dev is broken: It provides vmlinux.h which is a flavored header file! + if [ $* = $(firstword $(flavours)) ] ; then \ + install -d -m755 $(bpfdevpkgdir)/usr/include/$(DEB_HOST_MULTIARCH)/linux/bpf/ ; \ + install -m644 $(build_dir)/vmlinux.h \ + $(bpfdevpkgdir)/usr/include/$(DEB_HOST_MULTIARCH)/linux/bpf/ ; \ + fi + endif + endif +endif + +ifeq ($(do_cloud_tools),true) + ifeq ($(do_tools_hyperv),true) + # Create the linux-hyperv tool link + install -d $(cloudpkgdir)/usr/lib/linux-tools + $(LN) ../$(DEB_SOURCE)-tools-$(abi_release) $(cloudpkgdir)/usr/lib/linux-tools/$(abi_release)-$* + endif +endif + + # Build a temporary "installed headers" directory. + install -d $(dkms_dir) $(dkms_dir)/headers $(dkms_dir)/build $(dkms_dir)/source + cp -rp "$(hdrdir)" "$(indep_hdrdir)" "$(dkms_dir)/headers" + + $(foreach _m,$(all_dkms_modules), \ + $(if $(enable_$(_m)), \ + $(call build_dkms,$(dkms_$(_m)_pkg_name)-$*,$(dkms_$(_m)_pkgdir)/usr/lib/modules/$(abi_release)-$*/$(dkms_$(_m)_subdir),$(dbgpkgdir_dkms),$(_m),$(dkms_$(_m)_debpath)); \ + ) \ + ) + + +ifeq ($(do_dbgsym_package),true) + # Add .gnu_debuglink sections to each stripped .ko + # pointing to unstripped verson + find $(pkgdir) \ + -name '*.ko' | while read path_module ; do \ + module="/usr/lib/modules/$${path_module#*/usr/lib/modules/}"; \ + if [[ -f "$(dbgpkgdir)/usr/lib/debug/$$module" ]] ; then \ + while IFS= read -r -d '' signature < <(tail -c 28 "$$path_module"); do \ + break; \ + done; \ + $(CROSS_COMPILE)objcopy \ + --add-gnu-debuglink=$(dbgpkgdir)/usr/lib/debug/$$module \ + $$path_module; \ + if grep -q CONFIG_MODULE_SIG=y $(build_dir)/.config && \ + [ "$$signature" = $$'~Module signature appended~\n' ]; then \ + $(build_dir)/scripts/sign-file $(MODHASHALGO) \ + $(MODSECKEY) \ + $(MODPUBKEY) \ + $$path_module; \ + fi; \ + else \ + echo "WARNING: Missing debug symbols for module '$$module'."; \ + fi; \ + done +endif + + # Build the final ABI information. + install -d $(abi_dir) + sed -e 's/^\(.\+\)[[:space:]]\+\(.\+\)[[:space:]]\(.\+\)$$/\3 \2 \1/' \ + $(build_dir)/Module.symvers | sort > $(abi_dir)/$* + + # Build the final ABI modules information. + find $(pkgdir_bin) $(pkgdir) \( -name '*.ko' -o -name '*.ko.*' \) | \ + sed -e 's/.*\/\([^\/]*\)\.ko.*/\1/' | sort > $(abi_dir)/$*.modules + + # Build the final ABI built-in modules information. + if [ -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin ] ; then \ + sed -e 's/.*\/\([^\/]*\)\.ko/\1/' $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin | \ + sort > $(abi_dir)/$*.modules.builtin; \ + fi + + # Build the final ABI firmware information. + find $(pkgdir_bin) $(pkgdir) -name \*.ko | \ + while read ko; do \ + /sbin/modinfo $$ko | grep ^firmware || true; \ + done | sort -u >$(abi_dir)/$*.fwinfo + + # Build the final ABI built-in firmware information. + if [ -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin.modinfo ] ; then \ + cat $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin.modinfo | \ + tr '\0' '\n' | sed -n 's/^.*firmware=/firmware: /p' | \ + sort -u > $(abi_dir)/$*.fwinfo.builtin; \ + fi + + # Build the final ABI compiler information. + ko=$$(find $(pkgdir_bin) $(pkgdir) -name \*.ko | head -1); \ + readelf -p .comment "$$ko" | gawk ' \ + ($$1 == "[") { \ + printf("%s", $$3); \ + for (n=4; n<=NF; n++) { \ + printf(" %s", $$n); \ + } \ + print "" \ + }' | sort -u >$(abi_dir)/$*.compiler + + # Build the buildinfo package content. + install -d $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$* + install -m644 $(build_dir)/.config \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/config + install -m644 $(abi_dir)/$* \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/abi + install -m644 $(abi_dir)/$*.modules \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/modules + install -m644 $(abi_dir)/$*.fwinfo \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/fwinfo + install -m644 $(abi_dir)/$*.compiler \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/compiler + if [ -f $(abi_dir)/$*.modules.builtin ] ; then \ + install -m644 $(abi_dir)/$*.modules.builtin \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/modules.builtin; \ + fi + if [ -f $(abi_dir)/$*.fwinfo.builtin ] ; then \ + install -m644 $(abi_dir)/$*.fwinfo.builtin \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/fwinfo.builtin; \ + fi + install -m644 debian/canonical-certs.pem $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/canonical-certs.pem + install -m644 debian/canonical-revoked-certs.pem $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/canonical-revoked-certs.pem + + # Get rid of .o and .cmd artifacts in headers + find $(hdrdir) -name \*.o -or -name \*.cmd -exec rm -f {} \; + # Strip .so files (e.g., rust/libmacros.so) to reduce size even more + find $(hdrdir) -name libmacros.so -exec strip -s {} \; + +ifeq ($(do_lib_rust),true) + # Generate Rust lib files + install -d -m755 $(rustdir) + mv $(hdrdir)/rust $(rustdir) + # Generate symlink for Rust lib directory in headers + $(SHELL) debian/scripts/link-lib-rust "$(hdrdir)" "$(indeppkg)" "$*" +endif + +ifneq ($(do_full_build),false) + # Clean out this flavours build directory. + rm -rf $(build_dir) + rm -rf $(abi_dir) +endif + $(stamp) + +headers_dir := $(CURDIR)/debian/linux-libc-dev + +$(stampdir)/stamp-install-arch-headers: headers_tmp = $(CURDIR)/debian/tmp-headers +$(stampdir)/stamp-install-arch-headers: + @echo Debug: $@ + dh_testdir + dh_testroot + $(call if_package, linux-libc-dev, dh_prep -plinux-libc-dev) + rm -rf $(headers_tmp) $(headers_dir) + $(kmake) O=$(headers_tmp) INSTALL_HDR_PATH=$(headers_dir)/usr $(conc_level) headers_install + mkdir $(headers_dir)/usr/include/$(DEB_HOST_MULTIARCH) + mv $(headers_dir)/usr/include/asm $(headers_dir)/usr/include/$(DEB_HOST_MULTIARCH)/ + rm -rf $(headers_tmp) + $(stamp) + +define dh_all + dh_installchangelogs -p$(1) + dh_installdocs -p$(1) + dh_compress -p$(1) + # Compress kernel modules, on mantic+ + $(if $(do_zstd_ko),find debian/$(1) -name '*.ko' -print0 | xargs -0 -n1 -P $(CONCURRENCY_LEVEL) -r zstd -19 --quiet --rm, true) + dh_fixperms -p$(1) -X/boot/ + dh_shlibdeps -p$(1) $(shlibdeps_opts) + dh_installdeb -p$(1) + dh_installdebconf -p$(1) + $(lockme) dh_gencontrol -p$(1) -- -Vlinux:rprovides='$(rprovides)' $(2) + dh_md5sums -p$(1) + dh_builddeb -p$(1) +endef +define newline + + +endef +define dh_all_inline + $(subst ${newline},; \${newline},$(call dh_all,$(1),$(2))) +endef + +.PHONY: binary-arch-headers +binary-arch-headers: $(stampdir)/stamp-install-arch-headers + @echo Debug: $@ + dh_testdir + dh_testroot + $(call if_package, linux-libc-dev, $(call dh_all,linux-libc-dev)) + +-include $(builddir)/skipped-dkms.mk +binary-%: pkgimg = $(bin_pkg_name)-$* +binary-%: pkgimg_mods = $(mods_pkg_name)-$* +binary-%: pkgbldinfo = $(bldinfo_pkg_name)-$* +binary-%: pkghdr = $(hdrs_pkg_name)-$* +binary-%: pkgrust = $(rust_pkg_name)-$* +binary-%: dbgpkg = $(bin_pkg_name)-$*-dbgsym +binary-%: dbgpkgdir = $(CURDIR)/debian/$(bin_pkg_name)-$*-dbgsym +binary-%: pkgtools = $(tools_flavour_pkg_name)-$* +binary-%: pkgcloud = $(cloud_flavour_pkg_name)-$* +$(foreach _m,$(all_dkms_modules), \ + $(eval binary-%: enable_$(_m) = $$(filter true,$$(call custom_override,do_$(_m),$$*))) \ +) +binary-%: rprovides = $(foreach _m,$(all_built-in_dkms_modules),$(if $(enable_$(_m)),$(foreach _r,$(dkms_$(_m)_rprovides),$(_r)$(comma) ))) +binary-%: $(stampdir)/stamp-install-% + @echo Debug: $@ + dh_testdir + dh_testroot + + $(call dh_all,$(pkgimg)) -- -Znone + $(call dh_all,$(pkgimg_mods))$(if $(do_zstd_ko), -- -Znone) + + $(foreach _m,$(all_standalone_dkms_modules), \ + $(if $(enable_$(_m)),$(call dh_all,$(dkms_$(_m)_pkg_name)-$*)$(if $(do_zstd_ko), -- -Znone);)\ + ) + + $(call dh_all,$(pkgbldinfo)) + $(call dh_all,$(pkghdr)) +ifeq ($(do_lib_rust),true) + $(call dh_all,$(pkgrust)) +endif + +ifeq ($(do_dbgsym_package),true) + $(call dh_all,$(dbgpkg)) -- -Zxz + + # Hokay...here's where we do a little twiddling... + # Renaming the debug package prevents it from getting into + # the primary archive, and therefore prevents this very large + # package from being mirrored. It is instead, through some + # archive admin hackery, copied to http://ddebs.ubuntu.com. + # + mv ../$(dbgpkg)_$(DEB_VERSION_UPSTREAM)-$(DEB_REVISION)_$(arch).deb \ + ../$(dbgpkg)_$(DEB_VERSION_UPSTREAM)-$(DEB_REVISION)_$(arch).ddeb + $(lockme) sed -i '/^$(dbgpkg)_/s/\.deb /.ddeb /' debian/files + # Now, the package wont get into the archive, but it will get put + # into the debug system. + + # Clean out the debugging package source directory. + rm -rf $(dbgpkgdir) +endif + +ifeq ($(do_linux_tools),true) + $(call dh_all,$(pkgtools)) +endif +ifeq ($(do_cloud_tools),true) + $(call dh_all,$(pkgcloud)) +endif +ifeq ($(do_linux_tools),true) + ifeq ($(do_tools_bpftool),true) + ifneq ($(filter linux-bpf-dev,$(packages_enabled)),) + # Do this only for the primary (first) flavor + # linux-bpf-dev is broken: It provides vmlinux.h which is a flavored header file! + if [ $* = $(firstword $(flavours)) ] ; then \ + $(call dh_all_inline,linux-bpf-dev) ; \ + fi + endif + endif +endif + +# +# per-architecture packages +# +builddirpa = $(builddir)/tools-perarch + +$(stampdir)/stamp-prepare-perarch: + @echo Debug: $@ +ifeq ($(do_any_tools),true) + rm -rf $(builddirpa) + install -d $(builddirpa) + rsync -a --exclude debian --exclude debian.master --exclude $(DEBIAN) --exclude .git -a ./ $(builddirpa)/ +endif + $(stamp) + +$(stampdir)/stamp-build-perarch: $(stampdir)/stamp-install-arch-headers $(stampdir)/stamp-prepare-perarch + @echo Debug: $@ +ifeq ($(do_linux_tools),true) +ifeq ($(do_tools_usbip),true) + chmod 755 $(builddirpa)/tools/usb/usbip/autogen.sh + cd $(builddirpa)/tools/usb/usbip && ./autogen.sh + chmod 755 $(builddirpa)/tools/usb/usbip/configure + cd $(builddirpa)/tools/usb/usbip && ./configure --host=$(DEB_HOST_GNU_TYPE) --prefix=$(builddirpa)/tools/usb/usbip/bin + cd $(builddirpa)/tools/usb/usbip && make install CFLAGS="-g -O2 -static" CROSS_COMPILE=$(CROSS_COMPILE) +endif +ifeq ($(do_tools_acpidbg),true) + cd $(builddirpa)/tools/power/acpi && make clean && make CFLAGS="-g -O2 -static -I$(builddirpa)/include" CROSS_COMPILE=$(CROSS_COMPILE) acpidbg +endif +ifeq ($(do_tools_rtla),true) + cd $(builddirpa) && $(kmake) -C tools/tracing/rtla clean && $(kmake) LD=$(CROSS_COMPILE)ld HOSTLD=ld -C tools/tracing/rtla static +endif +ifeq ($(do_tools_cpupower),true) + make -C $(builddirpa)/tools/power/cpupower \ + CROSS_COMPILE=$(CROSS_COMPILE) \ + CROSS=$(CROSS_COMPILE) \ + STATIC=true \ + CPUFREQ_BENCH=false +endif +ifeq ($(do_tools_perf),true) + cd $(builddirpa)/tools/perf && \ + LLVM_CONFIG=llvm-config-$(LLVM_VERSION) $(kmake) prefix=/usr HAVE_CPLUS_DEMANGLE_SUPPORT=1 CROSS_COMPILE=$(CROSS_COMPILE) NO_LIBPERL=1 WERROR=0 +endif +ifeq ($(do_tools_bpftool),true) + $(kmake) CROSS_COMPILE=$(CROSS_COMPILE) -C $(builddirpa)/tools/bpf/bpftool +endif +ifeq ($(do_tools_x86),true) + cd $(builddirpa)/tools/power/x86/x86_energy_perf_policy && make CROSS_COMPILE=$(CROSS_COMPILE) + cd $(builddirpa)/tools/power/x86/turbostat && make CROSS_COMPILE=$(CROSS_COMPILE) + cd $(builddirpa)/tools/power/x86/intel-speed-select && make CROSS_COMPILE=$(CROSS_COMPILE) +endif +endif +ifeq ($(do_cloud_tools),true) +ifeq ($(do_tools_hyperv),true) + cd $(builddirpa)/tools/hv && make CFLAGS="-I$(headers_dir)/usr/include -I$(headers_dir)/usr/include/$(DEB_HOST_MULTIARCH)" CROSS_COMPILE=$(CROSS_COMPILE) hv_kvp_daemon hv_vss_daemon +ifneq ($(build_arch),arm64) + cd $(builddirpa)/tools/hv && make CFLAGS="-I$(headers_dir)/usr/include -I$(headers_dir)/usr/include/$(DEB_HOST_MULTIARCH)" CROSS_COMPILE=$(CROSS_COMPILE) hv_fcopy_uio_daemon +endif +endif +endif + $(stamp) + +.PHONY: install-perarch +install-perarch: toolspkgdir = $(CURDIR)/debian/$(tools_pkg_name) +install-perarch: cloudpkgdir = $(CURDIR)/debian/$(cloud_pkg_name) +install-perarch: bpftoolpkgdir = $(CURDIR)/debian/$(bpftool_pkg_name) +install-perarch: perfpkgdir = $(CURDIR)/debian/$(perf_pkg_name) +install-perarch: $(stampdir)/stamp-build-perarch + @echo Debug: $@ + # Add the tools. +ifeq ($(do_linux_tools),true) + install -d $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +ifeq ($(do_tools_usbip),true) + install -m755 $(addprefix $(builddirpa)/tools/usb/usbip/bin/sbin/, usbip usbipd) \ + $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +endif +ifeq ($(do_tools_acpidbg),true) + install -m755 $(builddirpa)/tools/power/acpi/acpidbg \ + $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +endif +ifeq ($(do_tools_cpupower),true) + install -m755 $(builddirpa)/tools/power/cpupower/cpupower \ + $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +endif +ifeq ($(do_tools_rtla),true) + install -m755 $(builddirpa)/tools/tracing/rtla/rtla-static \ + $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release)/rtla +endif +ifeq ($(do_tools_perf),true) + install -d $(perfpkgdir)/usr/bin + install -m755 $(builddirpa)/tools/perf/perf \ + $(perfpkgdir)/usr/bin/perf +ifeq ($(do_tools_perf_jvmti),true) + install -d $(perfpkgdir)/usr/lib + install -m644 $(builddirpa)/tools/perf/libperf-jvmti.so \ + $(perfpkgdir)/usr/lib/ +endif +ifeq ($(do_tools_perf_python),true) + install -d $(perfpkgdir)/usr/lib/python3/dist-packages + install -m644 $(builddirpa)/tools/perf/python/perf.*.so \ + $(perfpkgdir)/usr/lib/python3/dist-packages/ +endif +endif # do_tools_perf +ifeq ($(do_tools_bpftool),true) + install -d $(bpftoolpkgdir)/usr/sbin + install -m755 $(builddirpa)/tools/bpf/bpftool/bpftool \ + $(bpftoolpkgdir)/usr/sbin/bpftool +endif +ifeq ($(do_tools_x86),true) + install -m755 $(addprefix $(builddirpa)/tools/power/x86/, x86_energy_perf_policy/x86_energy_perf_policy turbostat/turbostat intel-speed-select/intel-speed-select) \ + $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +endif +endif # do_linux_tools +ifeq ($(do_cloud_tools),true) +ifeq ($(do_tools_hyperv),true) + install -d $(cloudpkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) + install -m755 $(addprefix $(builddirpa)/tools/hv/, hv_kvp_daemon hv_vss_daemon lsvmbus) \ + $(cloudpkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +ifneq ($(build_arch),arm64) + install -m755 $(addprefix $(builddirpa)/tools/hv/, hv_fcopy_uio_daemon) \ + $(cloudpkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +endif +endif # do_tools_hyperv +endif # do_cloud_tools + +.PHONY: binary-perarch +binary-perarch: toolspkg = $(tools_pkg_name) +binary-perarch: cloudpkg = $(cloud_pkg_name) +binary-perarch: bpftoolpkg = $(bpftool_pkg_name) +binary-perarch: perfpkg = $(perf_pkg_name) +binary-perarch: install-perarch + @echo Debug: $@ +ifeq ($(do_linux_tools),true) + $(call dh_all,$(toolspkg)) +endif +ifeq ($(do_cloud_tools),true) + $(call dh_all,$(cloudpkg)) +endif +ifeq ($(do_linux_tools),true) + ifeq ($(do_tools_bpftool),true) + ifneq ($(filter $(bpftool_pkg_name),$(packages_enabled)),) + $(call dh_all_inline,$(bpftoolpkg),$(BPFTOOL_GENCONTROL_ARGS)) + endif + endif + ifeq ($(do_tools_perf),true) + ifneq ($(filter $(perf_pkg_name),$(packages_enabled)),) + $(call dh_all_inline,$(perfpkg)) + endif + endif +endif + +binary-debs-deps-$(do_flavour_image_package) += $(addprefix binary-,$(flavours)) + +.PHONY: binary-debs +binary-debs: binary-perarch $(binary-debs-deps-true) + @echo Debug: $@ + +build-arch-deps-$(do_flavour_image_package) += $(addprefix $(stampdir)/stamp-install-,$(flavours)) + +.PHONY: build-arch +build-arch: $(build-arch-deps-true) + @echo Debug: $@ + +binary-arch-deps-true += binary-debs binary-arch-headers +ifneq ($(do_common_headers_indep),true) +binary-arch-deps-$(do_flavour_header_package) += binary-headers +endif + +.PHONY: binary-arch +binary-arch: $(binary-arch-deps-true) + @echo Debug: $@ + diff --git a/debian/rules.d/3-binary-indep.mk b/debian/rules.d/3-binary-indep.mk new file mode 100644 index 00000000000000..27dbe1e7f05722 --- /dev/null +++ b/debian/rules.d/3-binary-indep.mk @@ -0,0 +1,233 @@ +.PHONY: build-indep +build-indep: + @echo Debug: $@ + +# The binary-indep dependency chain is: +# +# install-headers <- install-source <- install-tools <- install-indep <- binary-indep +# install-headers <- binary-headers +# +indep_hdrpkg = $(indep_hdrs_pkg_name) +indep_hdrdir = $(CURDIR)/debian/$(indep_hdrpkg)/usr/src/$(indep_hdrpkg) + +$(stampdir)/stamp-install-headers: + @echo Debug: $@ + dh_testdir + dh_prep -p$(indep_hdrpkg) + +ifeq ($(do_flavour_header_package),true) + install -d $(indep_hdrdir) + find . -path './debian' -prune -o -path './$(DEBIAN)' -prune \ + -o -path './include/*' -prune \ + -o -path './scripts/*' -prune -o -type f \ + \( -name 'Makefile*' -o -name 'Kconfig*' -o -name 'Kbuild*' -o \ + -name '*.sh' -o -name '*.pl' -o -name '*.lds' \) \ + -print | cpio -pd --preserve-modification-time $(indep_hdrdir) + cp -a scripts include $(indep_hdrdir) + (find arch -name include -type d -print | \ + xargs -n1 -i: find : -type f) | \ + cpio -pd --preserve-modification-time $(indep_hdrdir) + # Do not ship .o and .cmd artifacts in headers + find $(indep_hdrdir) -name \*.o -or -name \*.cmd -exec rm -f {} \; +endif + $(stamp) + +srcpkg = linux-source-$(DEB_VERSION_UPSTREAM) +srcdir = $(CURDIR)/debian/$(srcpkg)/usr/src/$(srcpkg) +balldir = $(CURDIR)/debian/$(srcpkg)/usr/src/$(srcpkg)/$(srcpkg) +install-source: + @echo Debug: $@ +ifeq ($(do_source_package),true) + dh_prep -p$(srcpkg) + + install -d $(srcdir) +ifeq ($(do_source_package_content),true) + find . -path './debian' -prune -o -path './$(DEBIAN)' -prune -o \ + -path './.*' -prune -o -print | \ + cpio -pd --preserve-modification-time $(balldir) + (cd $(srcdir); tar cf - $(srcpkg)) | bzip2 -9c > \ + $(srcdir)/$(srcpkg).tar.bz2 + rm -rf $(balldir) + $(LN) $(srcpkg)/$(srcpkg).tar.bz2 $(srcdir)/.. +endif +endif + +.PHONY: install-tools +install-tools: bpftoolpkg = $(bpftool_pkg_name) +install-tools: bpftoolsbin = $(CURDIR)/debian/$(bpftoolpkg)/usr/sbin +install-tools: bpftoolman = $(CURDIR)/debian/$(bpftoolpkg)/usr/share/man +install-tools: bpftoolbashcomp = $(CURDIR)/debian/$(bpftoolpkg)/usr/share/bash-completion/completions +install-tools: perfpkg = $(perf_pkg_name) +install-tools: perfbin = $(CURDIR)/debian/$(perfpkg)/usr/bin +install-tools: perfman = $(CURDIR)/debian/$(perfpkg)/usr/share/man +install-tools: toolspkg = $(tools_common_pkg_name) +install-tools: toolsbin = $(CURDIR)/debian/$(toolspkg)/usr/bin +install-tools: toolssbin = $(CURDIR)/debian/$(toolspkg)/usr/sbin +install-tools: toolsman = $(CURDIR)/debian/$(toolspkg)/usr/share/man +install-tools: toolsbashcomp = $(CURDIR)/debian/$(toolspkg)/usr/share/bash-completion/completions +install-tools: hosttoolspkg = $(hosttools_pkg_name) +install-tools: hosttoolsbin = $(CURDIR)/debian/$(hosttoolspkg)/usr/bin +install-tools: hosttoolsman = $(CURDIR)/debian/$(hosttoolspkg)/usr/share/man +install-tools: hosttoolssystemd = $(CURDIR)/debian/$(hosttoolspkg)/lib/systemd/system +install-tools: cloudpkg = $(cloud_common_pkg_name) +install-tools: cloudbin = $(CURDIR)/debian/$(cloudpkg)/usr/bin +install-tools: cloudsbin = $(CURDIR)/debian/$(cloudpkg)/usr/sbin +install-tools: cloudman = $(CURDIR)/debian/$(cloudpkg)/usr/share/man +install-tools: $(stampdir)/stamp-build-perarch + @echo Debug: $@ + +ifeq ($(do_tools_common),true) + dh_prep -p$(toolspkg) + dh_prep -p$(perfpkg) + + rm -rf $(builddir)/tools + install -d $(builddir)/tools + for i in *; do $(LN) $(CURDIR)/$$i $(builddir)/tools/; done + rm $(builddir)/tools/tools + rsync -a tools/ $(builddir)/tools/tools/ + + install -d $(toolsbin) + install -d $(toolssbin) + install -d $(toolsman)/man1 + install -d $(toolsman)/man8 + install -d $(toolsbashcomp) + install -d $(perfbin) + install -d $(perfman)/man1 + + install -m755 debian/tools/generic $(toolsbin)/usbip + install -m755 debian/tools/generic $(toolsbin)/usbipd + install -m644 $(CURDIR)/tools/usb/usbip/doc/*.8 $(toolsman)/man8/ + + install -m755 debian/tools/generic $(toolsbin)/cpupower + install -m644 $(CURDIR)/tools/power/cpupower/man/*.1 $(toolsman)/man1/ + + install -m755 debian/tools/generic $(toolsbin)/rtla + + install -m755 debian/tools/generic $(toolsbin)/x86_energy_perf_policy + install -m755 debian/tools/generic $(toolsbin)/turbostat + + cd $(builddir)/tools/tools/perf && make man + install -m644 $(builddir)/tools/tools/perf/Documentation/*.1 \ + $(perfman)/man1 + + install -m644 $(CURDIR)/tools/power/x86/x86_energy_perf_policy/*.8 $(toolsman)/man8 + install -m644 $(CURDIR)/tools/power/x86/turbostat/*.8 $(toolsman)/man8 + +ifeq ($(do_cloud_tools),true) +ifeq ($(do_tools_hyperv),true) + dh_prep -p$(cloudpkg) + + install -d $(cloudsbin) + install -m755 debian/tools/generic $(cloudsbin)/hv_kvp_daemon + install -m755 debian/tools/generic $(cloudsbin)/hv_vss_daemon +ifneq ($(build_arch),arm64) + install -m755 debian/tools/generic $(cloudsbin)/hv_fcopy_uio_daemon +endif + install -m755 debian/tools/generic $(cloudsbin)/lsvmbus + install -m755 debian/cloud-tools/hv_get_dhcp_info $(cloudsbin) + install -m755 debian/cloud-tools/hv_get_dns_info $(cloudsbin) + install -m755 debian/cloud-tools/hv_set_ifconfig $(cloudsbin) + + install -d $(cloudman)/man8 + install -m644 $(CURDIR)/tools/hv/*.8 $(cloudman)/man8 +endif +endif + +ifeq ($(do_tools_acpidbg),true) + install -m755 debian/tools/generic $(toolsbin)/acpidbg +endif + +endif + +ifeq ($(do_tools_host),true) + dh_prep -p$(hosttoolspkg) + + install -d $(hosttoolsbin) + install -d $(hosttoolsman)/man1 + install -d $(hosttoolssystemd) + + install -m 755 $(CURDIR)/tools/kvm/kvm_stat/kvm_stat $(hosttoolsbin)/ + install -m 644 $(CURDIR)/tools/kvm/kvm_stat/kvm_stat.service \ + $(hosttoolssystemd)/ + + cd $(builddir)/tools/tools/kvm/kvm_stat && make man + install -m644 $(builddir)/tools/tools/kvm/kvm_stat/*.1 \ + $(hosttoolsman)/man1 +endif + +ifeq ($(do_linux_tools),true) + ifeq ($(do_tools_bpftool),true) + dh_prep -p$(bpftoolpkg) + + install -d $(bpftoolsbin) + install -d $(bpftoolman)/man8 + install -d $(bpftoolbashcomp) + make -C $(builddir)/tools/tools/bpf/bpftool doc + install -m644 $(builddir)/tools/tools/bpf/bpftool/Documentation/*.8 \ + $(bpftoolman)/man8 + install -m644 $(builddir)/tools/tools/bpf/bpftool/bash-completion/bpftool \ + $(bpftoolbashcomp) + endif +endif + +.PHONY: install-indep +install-indep: $(stampdir)/stamp-install-headers install-source install-tools + @echo Debug: $@ + +# This is just to make it easy to call manually. Normally done in +# binary-indep target during builds. +.PHONY: binary-headers +binary-headers: $(stampdir)/stamp-install-headers + @echo Debug: $@ + dh_installchangelogs -p$(indep_hdrpkg) + dh_installdocs -p$(indep_hdrpkg) + dh_compress -p$(indep_hdrpkg) + dh_fixperms -p$(indep_hdrpkg) + dh_installdeb -p$(indep_hdrpkg) + $(lockme) dh_gencontrol -p$(indep_hdrpkg) + dh_md5sums -p$(indep_hdrpkg) + dh_builddeb -p$(indep_hdrpkg) + +binary-indep: cloudpkg = $(cloud_common_pkg_name) +binary-indep: hosttoolspkg = $(hosttools_pkg_name) +binary-indep: install-indep + @echo Debug: $@ + dh_installchangelogs -i + dh_installdocs -i + dh_compress -i + dh_fixperms -i +ifeq ($(do_tools_common),true) +ifeq ($(do_cloud_tools),true) +ifeq ($(do_tools_hyperv),true) + dh_installinit -p$(cloudpkg) -n --name hv-kvp-daemon + dh_installinit -p$(cloudpkg) -n --name hv-vss-daemon +ifneq ($(build_arch),arm64) + dh_installinit -p$(cloudpkg) -n --name hv-fcopy-daemon +endif + dh_installudev -p$(cloudpkg) -n --name hv-kvp-daemon + dh_installudev -p$(cloudpkg) -n --name hv-vss-daemon +ifneq ($(build_arch),arm64) + dh_installudev -p$(cloudpkg) -n --name hv-fcopy-daemon +endif + dh_systemd_enable -p$(cloudpkg) + dh_installinit -p$(cloudpkg) -o --name hv-kvp-daemon + dh_installinit -p$(cloudpkg) -o --name hv-vss-daemon +ifneq ($(build_arch),arm64) + dh_installinit -p$(cloudpkg) -o --name hv-fcopy-daemon +endif + dh_systemd_start -p$(cloudpkg) +endif + # Keep intel_sgx service disabled by default, so add it after dh_systemd_enable + # and dh_systemd_start are called: + dh_installinit -p$(cloudpkg) --no-start --no-enable --name intel-sgx-load-module +endif +endif +ifeq ($(do_tools_host),true) + # Keep kvm_stat.service disabled by default (after dh_systemd_enable + # and dh_systemd_start: + dh_installinit -p$(hosttoolspkg) --no-enable --no-start --name kvm_stat +endif + dh_installdeb -i + $(lockme) dh_gencontrol -i + dh_md5sums -i + dh_builddeb -i diff --git a/debian/scripts/.gitignore b/debian/scripts/.gitignore new file mode 100644 index 00000000000000..74ecc022a5fbe9 --- /dev/null +++ b/debian/scripts/.gitignore @@ -0,0 +1 @@ +/fix-filenames diff --git a/debian/scripts/checks/final-checks b/debian/scripts/checks/final-checks new file mode 100755 index 00000000000000..98986b341bdab5 --- /dev/null +++ b/debian/scripts/checks/final-checks @@ -0,0 +1,47 @@ +#!/bin/bash + +debian="$1" +abi="$2" + +archs=$(awk '/^Architecture:/ { $1=""; for (i=1; i<=NF; i++) { if ($i != "all") { print $i }}}' debian/control | sort -u) + +fail=0 + +failure() +{ + echo "EE: $*" 1>&2 + fail=1 +} + +for arch in $archs +do + if [ ! -f "$debian/rules.d/$arch.mk" ]; then + continue + fi + + image_pkg=$(awk -F '\\s*=\\s*' '$1 == "do_flavour_image_package" { print $2 }' "$debian/rules.d/$arch.mk") + if [ "$image_pkg" = "false" ]; then + continue + fi + + flavours=$( + awk '/^\s*flavours\s*=/{ + sub(/^\s*flavours\s*=\s*/, ""); + print + }' "$debian/rules.d/$arch.mk") + for flavour in $flavours + do + if [ -d debian/certs ]; then + if ! python3 debian/scripts/misc/annotations --export -c CONFIG_SYSTEM_TRUSTED_KEYS --arch "$arch" --flavour "$flavour" | grep -q '^CONFIG_SYSTEM_TRUSTED_KEYS="debian/canonical-certs.pem"$' ; then + failure "'CONFIG_SYSTEM_TRUSTED_KEYS=\"debian/canonical-certs.pem\"' is required" + fi + fi + if [ -d debian/revoked-certs ]; then + if ! python3 debian/scripts/misc/annotations --export -c CONFIG_SYSTEM_REVOCATION_KEYS --arch "$arch" --flavour "$flavour" | grep -q '^CONFIG_SYSTEM_REVOCATION_KEYS="debian/canonical-revoked-certs.pem"$' ; then + failure "'CONFIG_SYSTEM_REVOCATION_KEYS=\"debian/canonical-revoked-certs.pem\"' is required" + fi + fi + done +done + +exit "$fail" diff --git a/debian/scripts/checks/module-signature-check b/debian/scripts/checks/module-signature-check new file mode 100755 index 00000000000000..039e4d0069c5c2 --- /dev/null +++ b/debian/scripts/checks/module-signature-check @@ -0,0 +1,2 @@ +#!/bin/sh +exit 0 diff --git a/debian/scripts/control-create b/debian/scripts/control-create new file mode 100755 index 00000000000000..bd5a876656d145 --- /dev/null +++ b/debian/scripts/control-create @@ -0,0 +1,109 @@ +#!/bin/bash + +set -e +shopt -s nullglob + +DEB_SOURCE=$1 + +. debian/debian.env + +if [ -z "${DEBIAN}" ]; then + echo "DEBIAN is empty" >&2 + exit 1 +fi + +gen_common () { + local stubs=("${DEBIAN}/control.stub.in") + + if [ "${DEB_SOURCE}" = linux ]; then + stubs+=( + debian/control.d/linux-libc-dev.stub + debian/control.d/linux-tools-common.stub + debian/control.d/linux-cloud-tools-common.stub + debian/control.d/linux-tools-host.stub + debian/control.d/linux-source.stub + debian/control.d/linux-bpf-dev.stub + debian/control.d/bpftool.stub + debian/control.d/linux-perf.stub + ) + fi + + for f in "${stubs[@]}" + do + cat "${f}" + echo "" + done +} + +gen_per_flavour () { + local arch bootloader conflicts flavour provides supported target + local sed_common_patterns signed_arch unsigned_arch depends + + var=$1 + + flavour=${var##*.} + + . "${var}" + + if [ "$provides" != '' ]; then + provides+=", " + fi + + if [ "$depends" != '' ]; then + depends+=", " + fi + + for a in ${arch} + do + # This is a makefile, so grepping... + if grep -q -E '(uefi|opal|sipl)_signed[[:space:]]*=[[:space:]]*true' "${DEBIAN}/rules.d/${a}.mk"; then + signed_arch+=("${a}") + else + unsigned_arch+=("${a}") + fi + done + + sed_common_patterns=( + -e "/^#/d" + -e "s/=DEPENDS=/${depends}/g" + -e "s/BOOTLOADER/${bootloader}/g" + -e "s/=CONFLICTS=/${conflicts}/g" + -e "s/FLAVOUR/${flavour}/g" + -e "s/=PROVIDES=/${provides}/g" + -e "s/SUPPORTED/${supported}/g" + -e "s/TARGET/${target}/g" + ) + + if [ "${#signed_arch[@]}" != 0 ]; then + sed "${sed_common_patterns[@]}" \ + -e "s/ARCH/${signed_arch[*]}/g" \ + -e "s/=SIGN-ME-PKG=/-unsigned/g" \ + -e "s/=SIGN-ME-TXT=/ unsigned/g" \ + -e "s/=SIGN-PEER-PKG=//g" \ + "${DEBIAN}/control.d/flavour-signed-control.stub" + fi + + if [ "${#unsigned_arch[@]}" != 0 ]; then + sed "${sed_common_patterns[@]}" \ + -e "s/ARCH/${unsigned_arch[*]}/g" \ + -e "s/=SIGN-ME-PKG=//g" \ + -e "s/=SIGN-ME-TXT=//g" \ + -e "s/=SIGN-PEER-PKG=/-unsigned/g" \ + "${DEBIAN}/control.d/flavour-signed-control.stub" + fi + + sed "${sed_common_patterns[@]}" \ + -e "s/ARCH/${arch}/g" \ + "${DEBIAN}/control.d/flavour-control.stub" + + sed "${sed_common_patterns[@]}" \ + -e "s/ARCH/${arch}/g" \ + "debian/control.d/flavour-buildinfo.stub" +} + +gen_common + +for v in "${DEBIAN}"/control.d/vars.* +do + gen_per_flavour "${v}" +done diff --git a/debian/scripts/dkms-build b/debian/scripts/dkms-build new file mode 100755 index 00000000000000..8e9adc56f03de2 --- /dev/null +++ b/debian/scripts/dkms-build @@ -0,0 +1,281 @@ +#!/bin/sh +set -e + +dkms_dir="$1" +abi_flavour="$2" +sign="$3" +pkgname="$4" +pkgdir="$5" +dbgpkgdir="$6" +package="$7" +shift 7 + +here=$(dirname "$(readlink -f "${0}")") + +srcdir=$(pwd) +cd "$dkms_dir" || exit 1 + +built_using_record() +{ + local subst="$1" + local built_using="$2" + if [ ! -f "$subst" ]; then + touch "$subst" + fi + if ! grep -q -s "^linux:BuiltUsing=" "$subst"; then + echo "linux:BuiltUsing=" >>"$subst" + fi + sed -i -e "s/^\(linux:BuiltUsing=.*\)/\1$built_using, /" "$subst" +} + +# ABI: returns present in $? and located path in lpackage_path when found. +package_present() +{ + for lpackage_path in "$1"_*.deb + do + break + done + [ -f "$lpackage_path" ] +} + +# Download and extract the DKMS package -- note there may be more +# than one package to install. +for package_path in "$@" +do + package_file=$(basename "$package_path") + echo "II: dkms-build downloading $package ($package_file)" + rpackage=$( echo "$package_path" | sed -e 's@.*/@@' -e 's@_.*@@' ) + lpackage=$( echo "$rpackage" | sed -e 's@=.*@@' ) + + while true + do + if package_present "$lpackage"; then + break + fi + case "$package_path" in + pool/*) + # Attempt download from the launchpad librarian first. + "$here/file-downloader" "https://launchpad.net/ubuntu/+archive/primary/+files/$package_file" || true + if package_present "$lpackage"; then + break + fi + + # Get pools from *.list files. + slist_files="/etc/apt/sources.list $( find /etc/apt/sources.list.d/ -type f -name "*.list" | xargs )" + slist_pools=$( grep -h '^deb ' $slist_files | awk '{print $2}' ) + + # Get pools from *.sources (deb822-style) files. + deb822_files=$( find /etc/apt/sources.list.d/ -type f -name "*.sources" | xargs ) + # Split stanzas on empty lines and only select deb pools, then get the URIs. + # Since RS != \n, regex is not line-by-line so the newline matching is more explicit. + deb822_pools=$( awk -v RS= '/(^|\n)Types:[^\n]* deb($|\s)/' $deb822_files | sed -n 's/^URIs: //p' ) + + # Download from the available pools. + for pool in $( echo $slist_pools $deb822_pools | xargs -n1 | sort -u ) + do + if package_present "$lpackage"; then + break + fi + url="$pool/$package_path" + "$here/file-downloader" "$url" && break || true + # No components in PPAs. + url=$(echo "$url" | sed -e 's@/pool/[^/]*/@/pool/main/@') + "$here/file-downloader" "$url" && break || true + done + ;; + http*:*) + "$here/file-downloader" "$package_path" + ;; + */*) + cp -p "$package_path" . + ;; + *) + apt-get download "$rpackage" + ;; + esac + break + done + if ! package_present "$lpackage"; then + echo "EE: $lpackage not found" + exit 1 + fi + + dpkg -x "$lpackage"_*.deb "$package" + + lversion=$( echo "$lpackage_path" | sed -e 's@.*/@@' -e 's@_[^_]*$@@' -e 's@.*_@@') + #built_using_record "$srcdir/debian/$pkgname.substvars" "$built_using$lpackage (= $lversion)" +done + +# Pick out the package/version from the dkms.conf. +for dkms_conf in "$package/usr/src"/*/"dkms.conf" +do + break +done + +# It seems some packages have a # in the name which works fine if the +# package is installed directly, but not so much if we build it out +# of the normal location. +sed -i -e '/^PACKAGE_NAME=/ s/#//g' "$dkms_conf" + +# Run any dkms-package specfic configuration steps +dkms_config_specific="$srcdir/$0-configure--$package" +dkms_config_generic=$(echo "$dkms_config_specific" | sed -e 's/-[0-9][0-9]*$/-N/') +for dkms_config in "$dkms_config_specific" "$dkms_config_generic" +do + if [ -z "$dkms_config" -o ! -e "$dkms_config" ]; then + continue + fi + echo "II: dkms-build-configure $(basename "$dkms_config") found, executing" + "$dkms_config" \ + "$srcdir" \ + "$dkms_conf" \ + "$dkms_dir" \ + "$abi_flavour" \ + "$sign" \ + "$pkgname" \ + "$pkgdir" \ + "$dbgpkgdir" \ + "$package" \ + "$@" || exit 1 + break +done + +cat - <<'EOF' >>"$dkms_conf" +POST_BUILD="ubuntu-save-objects ${dkms_tree}/${PACKAGE_NAME}/${PACKAGE_VERSION}/build ${dkms_tree}/${PACKAGE_NAME}/${PACKAGE_VERSION}/objects $POST_BUILD" +EOF +ubuntu_script="$(dirname "$dkms_conf")/ubuntu-save-objects" +cat - <<'EOF' >"$ubuntu_script" +#!/bin/sh +from="$1" +to="$2" +script="$3" +shift 2 + +# Copy the objects. +echo "II: copying objects to '$to'" +mkdir -p "$to" +(cd "$from" && find -name \*.o -o -name \*.mod | cpio -Lpd "$to") + +# Call the original post_install script if there is one. +[ "$script" = '' ] && exit 0 + +shift +exec "$(dirname "$0")/$script" "$@" +EOF +chmod +x "$ubuntu_script" +dkms_package=$( sed -ne 's/PACKAGE_NAME="\(.*\)"/\1/p' "$dkms_conf" ) +dkms_version=$( sed -ne 's/PACKAGE_VERSION="\(.*\)"/\1/p' "$dkms_conf" ) + +# Build the DKMS binaries. +echo "II: dkms-build building $package" +fakeroot="" +[ $(id -u) -ne 0 ] && fakeroot="/usr/bin/fakeroot" +rc=0 +$fakeroot /usr/sbin/dkms build --no-prepare-kernel --no-clean-kernel \ + -k "$abi_flavour" ${ARCH:+-a $ARCH} \ + --sourcetree "$dkms_dir/source" \ + --dkmstree "$dkms_dir/build" \ + --kernelsourcedir "$dkms_dir/headers/linux-headers-$abi_flavour" \ + "$dkms_conf" || rc=$? + +# Find the log and add it to our own. +for log in "$dkms_dir/build/$dkms_package/$dkms_version/$abi_flavour"/*/"log/make.log" "$dkms_dir/build/$dkms_package/$dkms_version/build/make.log" +do + if [ -f "$log" ]; then + sed -e "s@$dkms_dir@<>@g" <"$log" + break + fi +done + +# If this build failed then exit here. +[ "$rc" != 0 ] && exit "$rc" + +# Install the modules with debug symbols we possibly built, +# and strip the original modules for the next install step. +if [ -n "$dbgpkgdir" ]; then + dbgpkgdir="$dbgpkgdir/$package" + echo "II: dkms-build installing $package into $dbgpkgdir (debug symbols)" + install -d "$dbgpkgdir" + find "$dkms_dir/build/$dkms_package/$dkms_version/$abi_version" -name \*.ko | + while read module; do + vmodule=$( basename "$module" ) + + # Check for '.debug_info' section in order to copy module. + # Useful if debug symbols are requested but not built for + # any reason (including not yet supported by DKMS package). + # Strip module just in case even if section isn't present. + if ${CROSS_COMPILE}objdump -h -j '.debug_info' "$module" >/dev/null 2>&1 + then + echo "copying $vmodule" + cp "$module" "$dbgpkgdir" + else + echo "ignoring $vmodule (missing debug symbols)" + fi + + # Just 'strip -g' as '/usr/sbin/dkms' does. + echo "stripping $vmodule" + strip -g "$module" + done +fi + +# Install and optionally sign the modules we have built. +pkgdir="$pkgdir/$package" +echo "II: dkms-build installing $package into $pkgdir" +install -d "$pkgdir" +find "$dkms_dir/build/$dkms_package/$dkms_version/$abi_version" -name \*.ko | +while read module; do + vmodule=$( basename "$module" ) + case "$sign" in + --*) + echo "copying $vmodule" + cp "$module" "$pkgdir" + ;; + *) + echo "signing $vmodule" + $sign "$module" "$pkgdir/$vmodule" + ;; + esac +done + +find "$dkms_dir/build/$dkms_package/$dkms_version/objects" -name \*.o -print | \ +while read object +do + "$srcdir/debian/scripts/fix-filenames" "$object" "$dkms_dir" +done + +# This assumes that .mod files are in the top level build tree +# If there are ever .mod files in sub-directories, the dirname of objectlist needs to be stripped as well +find "$dkms_dir/build/$dkms_package/$dkms_version/objects" -name \*.mod -print | \ +while read objectlist +do + sed "s|^$dkms_dir/build/$dkms_package/$dkms_version/build/||" -i $objectlist +done + +# Finally see if there is a dkms-package specific post processor present. Hand +# it the original source directory, destination package directory, the objects +# as squirreled away, and the log in case it is useful. Finally pass a formed +# signing command line in case we need to do that. +dkms_build_specific="$srcdir/$0--$package" +dkms_build_generic=$(echo "$dkms_build_specific" | sed -n -e 's/-[0-9][0-9]*[a-z]*$/-N/p') +for dkms_build in "$dkms_build_specific" "$dkms_build_generic" +do + if [ -z "$dkms_build" -o ! -e "$dkms_build" ]; then + continue + fi + echo "II: dkms-build override $(basename "$dkms_build") found, executing" + "$dkms_build" \ + "$srcdir" \ + "$dkms_dir/build/$dkms_package/$dkms_version/objects" \ + "$log" \ + "$dkms_dir" \ + "$abi_flavour" \ + "$sign" \ + "$pkgname" \ + "$pkgdir" \ + "$dbgpkgdir" \ + "$package" \ + "$@" || exit 1 + break +done + +echo "II: dkms-build build $package complete" diff --git a/debian/scripts/dkms-build--nvidia-N b/debian/scripts/dkms-build--nvidia-N new file mode 100755 index 00000000000000..1b30c46b7213bd --- /dev/null +++ b/debian/scripts/dkms-build--nvidia-N @@ -0,0 +1,113 @@ +#!/bin/sh +set -e + +srcdir="$1" +objects="$2" +log="$3" +shift 3 + +dkms_dir="$1" +abi_flavour="$2" +sign="$3" +pkgname="$4" +pkgdir="$5" +dbgpkgdir="$6" +package="$7" +shift 7 + +build="$( dirname "$objects" )/build" + +# Copy over the objects ready for reconstruction. The objects copy +# contains the *.o files. For our purposes we only want the *.o files, +# elide the rest. And .mod files for ld linking in recentish kernels. +mkdir -p "$pkgdir/bits/scripts" +( + gcc_variant1=$(gcc --version | head -1 | sed -e 's/^gcc/GCC:/') + gcc_variant2=$(gcc --version | head -1 | sed -e 's/^\(gcc\) \((.*)\) \(.*\)$/\1 version \3 \2/') + cd "$objects" || exit 1 + find -name \*.o -o -name \*.mod | \ + while read file + do + cp --parents "$file" "$pkgdir/bits" + "$srcdir/debian/scripts/fix-filenames" "$pkgdir/bits/$file" "$gcc_variant1" + "$srcdir/debian/scripts/fix-filenames" "$pkgdir/bits/$file" "$gcc_variant2" + done +) + +# Install the support files we need. +echo "II: copying support files ..." +for lds_src in \ + "$dkms_dir/headers/linux-headers-$abi_flavour/scripts/module.lds" \ + "/usr/src/linux-headers-$abi_flavour/scripts/module.lds" \ + "$dkms_dir/headers/linux-headers-$abi_flavour/scripts/module-common.lds" \ + "/usr/src/linux-headers-$abi_flavour/scripts/module-common.lds" +do + [ ! -f "$lds_src" ] && continue + echo "II: copying support files ... found $lds_src" + cp "$lds_src" "$pkgdir/bits/scripts" + break +done + +# Build helper scripts. +cat - <<'EOL' >"$pkgdir/bits/BUILD" +[ "$1" = "unsigned" ] && { signed_only=:; shift; } +[ "$1" = "nocheck" ] && { check_only=:; shift; } +EOL +echo "export ELF_PACKAGE_METADATA='${ELF_PACKAGE_METADATA}'" >>"$pkgdir/bits/BUILD" +grep /usr/bin/ld.bfd "$log" | grep -v scripts/genksyms/genksyms | grep -v "warning:\|NOTE:" | sed -e "s@$build/@@g" -e 's@/build/[^ ]*/scripts/module.lds@scripts/module.lds@' >>"$pkgdir/bits/BUILD" +sed -e 's/.*-o *\([^ ]*\) .*/rm -f \1/g' <"$pkgdir/bits/BUILD" >"$pkgdir/bits/CLEAN" + +# As the builds contain the absolute filenames as used. Use RECONSTRUCT to +# rebuild the .ko's, sign them, pull off the signatures and then finally clean +# up again. +( + cd "$pkgdir/bits" + + # Add checksum check. + echo "\$check_only sha256sum -c SHA256SUMS || exit 1" >>"$pkgdir/bits/BUILD" + + # Add .ko handling to the CLEAN/BUILD dance. + for ko in "$pkgdir"/*.ko + do + ko=$(basename "$ko") + echo "\$signed_only cat '$ko' '$ko.sig' >'../$ko'" >>"$pkgdir/bits/BUILD" + echo "\$signed_only rm -f '$ko'" >>"$pkgdir/bits/BUILD" + echo "rm -f '../$ko'" >>"$pkgdir/bits/CLEAN" + done + + # Clear out anything we are not going to distribute and build unsigned .kos. + sh ./CLEAN + sh ./BUILD unsigned nocheck + + if [ "$sign" = "--custom" ]; then + # We are building for and archive custom signing upload. Keep everything. + : + elif [ "$sign" = "--lrm" ]; then + # We are in the LRM build; grab sha256 checksums and clean up. + sha256sum -b *.ko >"SHA256SUMS" + sh ./CLEAN + + else + # We are in the main kernel, put the .kos together as we will + # on the users machine, sign them, and keep just the signature. + : >"SHA256SUMS" + for ko in *.ko + do + echo "detached-signature $ko" + $sign "$ko" "$ko.signed" + length=$( stat --format %s "$ko" ) + dd if="$ko.signed" of="$ko.sig" bs=1 skip="$length" 2>/dev/null + + rm -f "$ko.signed" + # Keep a checksum of the pre-signed object so we can check it is + # built correctly in LRM. + sha256sum -b "$ko" >>"SHA256SUMS" + done + + # Clean out anything which not a signature. + mv "$pkgdir/bits/"*.sig "$pkgdir" + mv "$pkgdir/bits/SHA256SUMS" "$pkgdir" + find "$pkgdir" -name \*.sig -prune -o -name SHA256SUMS -prune -o -type f -print | xargs rm -f + find "$pkgdir" -depth -type d -print | xargs rmdir --ignore-fail-on-non-empty + fi +) diff --git a/debian/scripts/dkms-build-configure--zfs b/debian/scripts/dkms-build-configure--zfs new file mode 100755 index 00000000000000..09db28802ee72e --- /dev/null +++ b/debian/scripts/dkms-build-configure--zfs @@ -0,0 +1,24 @@ +#!/bin/sh +set -e + +srcdir="$1" +dkms_conf="$2" +shift 2 + +dkms_dir="$1" +abi_flavour="$2" +sign="$3" +pkgname="$4" +pkgdir="$5" +dbgpkgdir="$6" +package="$7" +shift 7 + +# ZFS debug symbols are enabled in dkms.conf via PACKAGE_CONFIG file. +if [ -n "$dbgpkgdir" ]; then + echo "enable zfs debug symbols" + pkg_cfg="$(dirname "$dkms_conf")/pkg_cfg" + echo 'ZFS_DKMS_ENABLE_DEBUGINFO=yes' >"$pkg_cfg" + echo 'ZFS_DKMS_DISABLE_STRIP=yes' >>"$pkg_cfg" + sed -i "s,^\(PACKAGE_CONFIG=\).*,\1$pkg_cfg," $dkms_conf +fi diff --git a/debian/scripts/file-downloader b/debian/scripts/file-downloader new file mode 100755 index 00000000000000..0ebfb4de24194b --- /dev/null +++ b/debian/scripts/file-downloader @@ -0,0 +1,34 @@ +#!/bin/sh + +if [ "$#" -ne 1 ]; then + echo "Usage: $0 " 1>&2 + exit 1 +fi +url="$1" + +to=$(basename "$url") + +count=0 +what='fetching' +while : +do + if [ "$count" -eq 20 ]; then + echo "EE: excessive redirects" 1>&2 + exit 1 + fi + count=$(($count+1)) + + echo "II: $what $url" + + curl --silent --fail --show-error "$url" -o "$to" -D "$to.hdr" || exit 1 + redirect=$(awk '/^Location: / {gsub(/^[[:space:]]+|[[:space:]]+$/,"",$2); print $2;}' "$to.hdr") + [ -z "$redirect" ] && break + what=' following' + + url=$(echo "$redirect" | sed -e 's@https://launchpadlibrarian.net/@http://launchpadlibrarian.net/@') + if [ "$redirect" != "$url" ]; then + echo "II: fixing $redirect" + fi +done + +exit 0 diff --git a/debian/scripts/fix-filenames.c b/debian/scripts/fix-filenames.c new file mode 100644 index 00000000000000..9bd144a6efa8c0 --- /dev/null +++ b/debian/scripts/fix-filenames.c @@ -0,0 +1,80 @@ +/* + * fix-filenames: find a specified pathname prefix and remove it from + * C strings. + * + * Copyright (C) 2018 Canonical Ltd. + * Author: Andy Whitcroft + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int +main(int argc, char *argv[]) +{ + int rc; + char *in_name; + char *prefix; + int prefix_len; + int in_fd; + struct stat in_info; + char *in; + off_t size; + int length; + + if (argc != 3) { + fprintf(stderr, "Usage: %s \n", argv[0]); + exit(1); + } + in_name = argv[1]; + prefix = argv[2]; + prefix_len = strlen(prefix); + + in_fd = open(in_name, O_RDWR); + if (in_fd < 0) { + perror("open input failed"); + exit(1); + } + + rc = fstat(in_fd, &in_info); + if (rc < 0) { + perror("fstat input failed"); + exit(1); + } + size = in_info.st_size; + + in = mmap((void *)0, size, PROT_READ|PROT_WRITE, MAP_SHARED, in_fd, (off_t)0); + if (!in) { + perror("mmap failed"); + exit(1); + } + + for (; size > 0; size--, in++) { + if (*in != *prefix) + continue; + if (strncmp(in, prefix, prefix_len) != 0) + continue; + /* In the case of an exact match there there is nothing to move. */ + if (in[prefix_len] == '\0') + length = 0; + /* If this is a filename, strip the leading slash. */ + else if (in[prefix_len] == '/') + length = strlen(in + prefix_len + 1) + 1; + /* Otherwise just keep the suffix. */ + else + length = strlen(in + prefix_len) + 1; + + /* + * Copy the suffix portion down to the start and clear + * the remainder of the space to 0. + */ + memmove(in, in + prefix_len + 1, length); + memset(in + length, '\0', prefix_len); + } +} diff --git a/debian/scripts/link-headers b/debian/scripts/link-headers new file mode 100755 index 00000000000000..fb42dbd12e4df2 --- /dev/null +++ b/debian/scripts/link-headers @@ -0,0 +1,42 @@ +#!/bin/bash -e + +. debian/debian.env + +hdrdir="$1" +symdir="$2" +flavour="$3" + +echo "Symlinking and copying headers for $flavour..." + +excludes="( -path ./debian -prune -o -path ./${DEBIAN} -prune -o -path ./.git ) -prune -o" + +( +find . $excludes -type f \ + \( -name 'Makefile*' -o -name 'Kconfig*' -o -name 'Kbuild*' -o \ + -name '*.sh' -o -name '*.pl' -o -name '*.lds' \) -print +find ./include ./scripts -name .gitignore -prune -o -type f -print +find ./include -mindepth 1 -maxdepth 1 $excludes -type d -print +) | ( +while read file; do + dir=$file + lastdir=$file + + if [ -e "$hdrdir/$file" -o -L "$hdrdir/$file" ]; then + continue + fi + + while [ ! -e "$hdrdir/$dir" -a ! -L "$hdrdir/$dir" ]; do + lastdir=$dir + dir=`dirname $dir` + done + # If the last item to exist is a symlink we assume all is good + if [ ! -L "$hdrdir/$dir" ]; then + # Turns things like "./foo" into "../" + deref="`echo -n $lastdir | sed -e 's/^\.//' -e's,/[^/]*,../,g'`" + item="`echo -n $lastdir | sed -e 's/^\.\///'`" + ln -s $deref$symdir/$item $hdrdir/$item + fi +done +) + +exit diff --git a/debian/scripts/link-lib-rust b/debian/scripts/link-lib-rust new file mode 100755 index 00000000000000..0bea9729431d2e --- /dev/null +++ b/debian/scripts/link-lib-rust @@ -0,0 +1,17 @@ +#!/bin/bash -e + +. debian/debian.env + +hdrdir="$1" +symdir="$2" +flavour="$3" + +echo "Symlinking and copying Rust files for $flavour..." + +# Symlink Rust folder +item=rust +relpath=$(echo $symdir | sed s/headers/lib-rust/)-$flavour/$item +echo ln -s ../$relpath $hdrdir/$item +ln -s ../$relpath $hdrdir/$item + +exit diff --git a/debian/scripts/misc/annotations b/debian/scripts/misc/annotations new file mode 100755 index 00000000000000..6c1cf810ff4b1a --- /dev/null +++ b/debian/scripts/misc/annotations @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 +# -*- mode: python -*- + +# This file is not installed; it's just to run annotations from inside a source +# distribution without installing it in the system. + +import sys + +# Prevent generating .pyc files on import +# +# We may end up adding these files to our git repos by mistake, so simply +# prevent generating them in advance. +# +# There's a tiny performance penalty with this, because python needs to +# re-generate the bytecode on-the-fly every time the script is executed, but +# this overhead is absolutely negligible compared the rest of the kernel build +# time. +sys.dont_write_bytecode = True + +import os # noqa: E402 Import not at top of file + +from kconfig import run # noqa: E402 Import not at top of file + + +# Update PATH to make sure that annotations can be executed directly from the +# source directory. +def update_path(): + script_dir = os.path.dirname(os.path.abspath(__file__)) + current_path = os.environ.get("PATH", "") + new_path = f"{script_dir}:{current_path}" + os.environ["PATH"] = new_path + + +update_path() +exit(run.main()) diff --git a/debian/scripts/misc/find-dtbs.py b/debian/scripts/misc/find-dtbs.py new file mode 120000 index 00000000000000..9584132ed83dbd --- /dev/null +++ b/debian/scripts/misc/find-dtbs.py @@ -0,0 +1 @@ +/home/jglathe/src/stubble/hwids/finddtbs.py \ No newline at end of file diff --git a/debian/scripts/misc/find-missing-sauce.sh b/debian/scripts/misc/find-missing-sauce.sh new file mode 100755 index 00000000000000..2bdcf72607bb7c --- /dev/null +++ b/debian/scripts/misc/find-missing-sauce.sh @@ -0,0 +1,15 @@ +#!/bin/bash +# +# Find the 'UBUNTU: SAUCE:' patches that have been dropped from +# the previous release. +# +PREV_REL=focal +PREV_REPO=git://kernel.ubuntu.com/ubuntu/ubuntu-${PREV_REL}.git + +git fetch ${PREV_REPO} master-next +git log --pretty=oneline FETCH_HEAD|grep SAUCE|while read c m;do echo $m;done |sort > $$.prev-rel +git log --pretty=oneline |grep SAUCE|while read c m;do echo $m;done |sort > $$.curr-rel + +diff -u $$.prev-rel $$.curr-rel |grep "^-" +rm -f $$.prev-rel $$.curr-rel + diff --git a/debian/scripts/misc/gen-auto-reconstruct b/debian/scripts/misc/gen-auto-reconstruct new file mode 100755 index 00000000000000..2746d27d4c5f0c --- /dev/null +++ b/debian/scripts/misc/gen-auto-reconstruct @@ -0,0 +1,89 @@ +#!/bin/bash + +if [ "$#" -ne 3 ]; then + echo "Usage: $0 | " 1>&2 + exit 1 +fi +tag="$1" +reconstruct="$2" +options="$3" + +case "$tag" in +v*) ;; +*) tag="v${tag%.*}" ;; +esac + +# Validate the tag. +count=$( git tag -l "$tag" | wc -l ) +if [ "$count" != 1 ]; then + echo "$0: $tag: tag invalid" 1>&2 + exit 1 +fi + +#git ls-tree -r --full-tree HEAD | grep ^120 | \ +#while read mode type blobid name + +( + # Identify all new symlinks since the proffered tag. + echo "# Recreate any symlinks created since the orig." + git diff "$tag.." --raw --no-renames | awk '(/^:000000 120000/ && $5 == "A") { print $NF }' | \ + while read name + do + link=$( readlink "$name" ) + + echo "[ ! -L '$name' ] && ln -sf '$link' '$name'" + done + + # Identify files with execute permissions added since the proffered tag. + git diff "$tag.." --raw --no-renames | awk -F '[: \t]' '{print $2, $3, $NF }' | \ + while IFS=" " read old new name + do + old=$( printf "0%s" $old ) + new=$( printf "0%s" $new ) + changed=$(( (old ^ new) & 0111 )) + if [ "$changed" -ne 0 ]; then + added=$(( new & 0111 )) + if [ "$added" -ne 0 ]; then + echo "chmod +x '$name'" + elif [ "$new" -ne 0 ]; then + echo "chmod -x '$name'" + fi + fi + done + + # Identify all removed files since the proffered tag. + echo "# Remove any files deleted from the orig." + git diff "$tag.." --raw --no-renames | awk '(/^:/ && $5 == "D") { print $NF }' | \ + while read name + do + echo "rm -f '$name'" + done + + # All done, make sure this does not complete in error. + echo "exit 0" +) >"$reconstruct" + +( + # Identify all new symlinks since the proffered tag. + echo "# Ignore any symlinks created since the orig which are rebuilt by reconstruct." + git diff "$tag.." --raw --no-renames | awk '(/^:000000 120000/ && $5 == "A") { print $NF }' | \ + while read name + do + echo "extend-diff-ignore=^$name\$" + done +) >"$options.update" + + +head='^## autoreconstruct -- begin$' +foot='^## autoreconstruct -- end$' +sed -i -e " + /$head/,/$foot/{ + /$head/{ + p; + r $options.update + }; + /$foot/p; + d + } +" "$options" +rm -f "$options.update" diff --git a/debian/scripts/misc/git-ubuntu-log b/debian/scripts/misc/git-ubuntu-log new file mode 100755 index 00000000000000..dc1cd74c4a6761 --- /dev/null +++ b/debian/scripts/misc/git-ubuntu-log @@ -0,0 +1,163 @@ +#!/usr/bin/env python3 + +import codecs +import json +import sys +import textwrap +import urllib.request + +sys.stdin = codecs.getreader("utf-8")(sys.stdin.detach()) +sys.stdout = codecs.getwriter("utf-8")(sys.stdout.detach()) + +entries = [] + + +def add_entry(entry): + global tracking_bug + + if entry and "ignore" not in entry: + combo = [] + for bug in set(entry.get("bugs", [])): + combo.append(bug) + for cve in set(entry.get("cves", [])): + combo.append(cve) + combo = sorted(combo) + + if len(combo) == 0: + if entry.get("subject", "").startswith("UBUNTU"): + combo = "__packaging__" + else: + combo = "__mainline__" + else: + if entry.get("subject", "") == "UBUNTU: link-to-tracker: update tracking bug": + tracking_bug = combo + if combo not in keys: + keys.append(combo) + + entry["key"] = combo + entries.append(entry) + + +# Suck up the git log output and extract the information we need. +keys = [] +tracking_bug = None +entry = None +subject_wait = False +for line in sys.stdin: + if line.startswith("commit "): + add_entry(entry) + entry = {} + subject_wait = True + + elif line.startswith("Author: "): + bits = line.strip().split(maxsplit=1) + entry["author"] = bits[1] + + elif subject_wait and line.startswith(" "): + subject_wait = False + entry["subject"] = line.strip() + + elif line.startswith(" BugLink: "): + bits = line.strip().split(maxsplit=2) + if len(bits) > 2: + # There is text after the URL, so use that (after stripping the + # enclosing characters) + entry.setdefault("bugs", []).append(bits[2][1:-1]) + elif "launchpad.net" in bits[1]: + # Extract the bug number from the launchpad URL + bits = bits[1].split("/") + entry.setdefault("bugs", []).append(bits[-1]) + + elif line.startswith(" CVE-"): + entry.setdefault("cves", []).append(line.strip()) + + elif line.startswith(" Ignore:"): + entry["ignore"] = True + + elif line.startswith(" Properties:"): + for prop in line.strip().split()[1:]: + if prop in ("ignore", "no-changelog"): + entry["ignore"] = True + +add_entry(entry) + +entries.reverse() + +# Go through the entries and clear out authors for upstream commits. +for entry in entries: + if entry["subject"].startswith("UBUNTU:"): + entry["subject"] = entry["subject"][7:].strip() + else: + del entry["author"] + +# Lump everything without a bug at the bottom. +keys.append("__packaging__") +keys.append("__mainline__") + +# Ensure we list the tracking bug updates first. +if tracking_bug is not None: + keys.remove(tracking_bug) + keys.insert(0, tracking_bug) + +emit_nl = False +for key in keys: + if key == "__packaging__": + title_set = ["Miscellaneous Ubuntu changes"] + elif key == "__mainline__": + title_set = ["Miscellaneous upstream changes"] + else: + title_set = [] + for bug in key: + if bug.startswith("CVE-"): + title_set.append(bug) + elif bug.isdigit(): + # Assume that it is an LP bug number if 'bug' contains only digits + bug_info = None + + try: + # urllib.request.urlcleanup() + request = urllib.request.Request("https://api.launchpad.net/devel/bugs/" + bug) + request.add_header("Cache-Control", "no-cache") + with urllib.request.urlopen(request) as response: + data = response.read() + bug_info = json.loads(data.decode("utf-8")) + + title = bug_info["title"] + if "description" in bug_info: + for line in bug_info["description"].split("\n"): + if line.startswith("Kernel-Description:"): + title = line.split(" ", 1)[1] + + except urllib.error.HTTPError: + title = "INVALID or PRIVATE BUG" + + title += " (LP###" + bug + ")" + title_set.append(title) + else: + # Finally treat 'bug' itself as the title + title_set.append(bug) + + emit_title = True + for entry in entries: + if entry["key"] != key: + continue + + if emit_title: + if emit_nl: + print("") + emit_nl = True + + title_lines = textwrap.wrap("#// ".join(title_set), 76) + print(" * " + title_lines[0].replace("LP###", "LP: #").replace("#//", " //")) + for line in title_lines[1:]: + line = line.replace("LP###", "LP: #").replace("#//", " //") + print(" " + line) + + emit_title = False + + if key != tracking_bug or (key == tracking_bug and entry["subject"] != "link-to-tracker: update tracking bug"): + title_lines = textwrap.wrap(entry["subject"], 76) + print(" - " + title_lines[0]) + for line in title_lines[1:]: + line = line.replace("LP###", "LP: #") + print(" " + line) diff --git a/debian/scripts/misc/insert-changes b/debian/scripts/misc/insert-changes new file mode 100755 index 00000000000000..e21aaa409884fc --- /dev/null +++ b/debian/scripts/misc/insert-changes @@ -0,0 +1,42 @@ +#!/usr/bin/python3 + +import os +import sys + +from subprocess import check_output + +droot = 'debian' +if len(sys.argv) > 1: + droot = sys.argv[1] + +debian = 'debian.master' +if len(sys.argv) > 2: + debian = sys.argv[2] + +rules = os.path.join(droot, 'rules') +changelog = os.path.join(debian, 'changelog') +changelog_new = os.path.join(debian, 'changelog.new') + +# Generate the list of new changes +changes = check_output(['make', '-s', '-f', rules, 'printchanges']).decode('UTF-8') + +# Insert the new changes into the changelog +with open(changelog) as orig, open(changelog_new, 'w') as new: + printed = False + skip_newline = False + for line in orig: + if line.startswith(' CHANGELOG: '): + if not printed: + printed = True + if changes == '': + skip_newline = True + continue + new.write(changes) + else: + if skip_newline and line.strip() == '': + skip_newline = False + continue + new.write(line) + +# Replace the original changelog with the new one +os.rename(changelog_new, changelog) diff --git a/debian/scripts/misc/insert-ubuntu-changes b/debian/scripts/misc/insert-ubuntu-changes new file mode 100755 index 00000000000000..557d4e2d0b8c69 --- /dev/null +++ b/debian/scripts/misc/insert-ubuntu-changes @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 + +import re +import os +import sys + +def version_cmp(a, b): + a = re.split(r"[\.-]+", a) + b = re.split(r"[\.-]+", b) + i = 0 + while True: + if len(a) <= i: + if len(b) <= i: + return 0 + return -1 + if len(b) <= i: + return 1 + if int(a[i]) < int(b[i]): + return -1 + if int(a[i]) > int(b[i]): + return 1 + i += 1 + +if len(sys.argv) == 4: + sys.argv.append("debian.master/changelog") + +if len(sys.argv) == 5: + changelog, end, start, source_changelog = sys.argv[1:] +else: + print("Usage: insert-ubuntu-changes []") + sys.exit(1) + +changes = [] +output = False +with open(source_changelog) as fh: + for line in fh: + m = re.match(r"^\S+\s+\((.*)\)", line) + if m: + if version_cmp(m.group(1), end) <= 0: + break + if m.group(1) == start: + output = True + if output: + changes.append("\n") + changes.append(" [ Ubuntu: {} ]\n".format(m.group(1))) + changes.append("\n") + continue + + if output and re.match(r"^( * | | )\S", line): + changes.append(line) + +printed = 3 +with open(changelog + ".new", "w") as fh_new: + with open(changelog) as fh: + for line in fh: + if line.startswith(" CHANGELOG: "): + printed -= 1 + fh_new.write(line) + if printed == 0: + fh_new.write("".join(changes)) + continue + fh_new.write(line) + +os.rename(changelog + ".new", changelog) diff --git a/debian/scripts/misc/kconfig/__init__.py b/debian/scripts/misc/kconfig/__init__.py new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/debian/scripts/misc/kconfig/annotations.py b/debian/scripts/misc/kconfig/annotations.py new file mode 100644 index 00000000000000..5f34410d4ef879 --- /dev/null +++ b/debian/scripts/misc/kconfig/annotations.py @@ -0,0 +1,521 @@ +# -*- mode: python -*- +# python module to manage Ubuntu kernel .config and annotations +# Copyright © 2022 Canonical Ltd. + +import json +import re +import shutil +import tempfile +from abc import abstractmethod +from ast import literal_eval +from os.path import abspath, dirname + +from kconfig.version import ANNOTATIONS_FORMAT_VERSION + + +class Config: + def __init__(self, fname, do_include=True): + """ + Basic configuration file object + """ + self.fname = fname + self.config = {} + self.do_include = do_include + + raw_data = self._load(fname) + self._parse(raw_data) + + @staticmethod + def _load(fname: str) -> str: + with open(fname, "rt", encoding="utf-8") as fd: + data = fd.read() + return data.rstrip() + + def __str__(self): + """Return a JSON representation of the config""" + return json.dumps(self.config, indent=4) + + @abstractmethod + def _parse(self, data: str): + pass + + +class KConfig(Config): + """ + Parse a .config file, individual config options can be accessed via + .config[] + """ + + def _parse(self, data: str): + self.config = {} + for line in data.splitlines(): + m = re.match(r"^# (CONFIG_.*) is not set$", line) + if m: + self.config[m.group(1)] = literal_eval("'n'") + continue + m = re.match(r"^(CONFIG_[A-Za-z0-9_]+)=(.*)$", line) + if m: + self.config[m.group(1)] = literal_eval("'" + m.group(2) + "'") + continue + + +class Annotation(Config): + """ + Parse body of annotations file + """ + + def __init__(self, fname, do_include=True, do_json=False): + self.do_json = do_json + super().__init__(fname, do_include=True) + + def _parse_body(self, data: str, parent=True): + for line in data.splitlines(): + # Replace tabs with spaces, squeeze multiple into singles and + # remove leading and trailing spaces + line = line.replace("\t", " ") + line = re.sub(r" +", " ", line) + line = line.strip() + + # Ignore empty lines + if not line: + continue + + # Catpure flavors of included files + if line.startswith("# FLAVOUR: "): + self.include_flavour += line.split(" ")[2:] + continue + + # Ignore comments + if line.startswith("#"): + continue + + # Handle includes (recursively) + m = re.match(r'^include\s+"?([^"]*)"?', line) + if m: + if parent: + self.include.append(m.group(1)) + if self.do_include: + include_fname = dirname(abspath(self.fname)) + "/" + m.group(1) + include_data = self._load(include_fname) + self._parse_body(include_data, parent=False) + continue + + # Handle policy and note lines + if re.match(r".* (policy|note)<", line): + try: + conf = line.split(" ")[0] + if conf in self.config: + entry = self.config[conf] + else: + entry = {"policy": {}} + + match = False + m = re.match(r".* policy<(.*?)>", line) + if m: + match = True + # Update the previous entry considering potential overrides: + # - if the new entry is adding a rule for a new + # arch/flavour, simply add that + # - if the new entry is overriding a previous + # arch-flavour item, then overwrite that item + # - if the new entry is overriding a whole arch, then + # remove all the previous flavour rules of that arch + new_entry = literal_eval(m.group(1)) + for key in new_entry: + if key in self.arch: + for flavour_key in list(entry["policy"].keys()): + if flavour_key.startswith(key): + del entry["policy"][flavour_key] + entry["policy"][key] = new_entry[key] + else: + entry["policy"][key] = new_entry[key] + + m = re.match(r".* note<(.*?)>", line) + if m: + entry["oneline"] = match + match = True + entry["note"] = "'" + m.group(1).replace("'", "") + "'" + + if not match: + raise SyntaxError("syntax error") + self.config[conf] = entry + except Exception as e: + raise SyntaxError(str(e) + f", line = {line}") from e + continue + + # Invalid line + raise SyntaxError(f"invalid line: {line}") + + def _legacy_parse(self, data: str): + """ + Parse main annotations file, individual config options can be accessed + via self.config[] + """ + self.config = {} + self.arch = [] + self.flavour = [] + self.flavour_dep = {} + self.include = [] + self.header = "" + self.include_flavour = [] + + # Parse header (only main header will considered, headers in includes + # will be treated as comments) + for line in data.splitlines(): + if re.match(r"^#.*", line): + m = re.match(r"^# ARCH: (.*)", line) + if m: + self.arch = list(m.group(1).split(" ")) + m = re.match(r"^# FLAVOUR: (.*)", line) + if m: + self.flavour = list(m.group(1).split(" ")) + m = re.match(r"^# FLAVOUR_DEP: (.*)", line) + if m: + self.flavour_dep = literal_eval(m.group(1)) + self.header += line + "\n" + else: + break + + # Return an error if architectures are not defined + if not self.arch: + raise SyntaxError("ARCH not defined in annotations") + # Return an error if flavours are not defined + if not self.flavour: + raise SyntaxError("FLAVOUR not defined in annotations") + + # Parse body + self._parse_body(data) + + # Sanity check: Verify that all FLAVOUR_DEP flavors are valid + if self.do_include: + for src, tgt in self.flavour_dep.items(): + if src not in self.flavour: + raise SyntaxError(f"Invalid source flavour in FLAVOUR_DEP: {src}") + if tgt not in self.include_flavour: + raise SyntaxError(f"Invalid target flavour in FLAVOUR_DEP: {tgt}") + + def _json_parse(self, data, is_included=False): + data = json.loads(data) + + # Check if version is supported + version = data["attributes"]["_version"] + if version > ANNOTATIONS_FORMAT_VERSION: + raise SyntaxError(f"annotations format version {version} not supported") + + # Check for top-level annotations vs imported annotations + if not is_included: + self.config = data["config"] + self.arch = data["attributes"]["arch"] + self.flavour = data["attributes"]["flavour"] + self.flavour_dep = data["attributes"]["flavour_dep"] + self.include = data["attributes"]["include"] + self.include_flavour = [] + else: + # We are procesing an imported annotations, so merge all the + # configs and attributes. + try: + self.config = data["config"] | self.config + except TypeError: + self.config = {**self.config, **data["config"]} + self.arch = list(set(self.arch) | set(data["attributes"]["arch"])) + self.flavour = list(set(self.flavour) | set(data["attributes"]["flavour"])) + self.include_flavour = list(set(self.include_flavour) | set(data["attributes"]["flavour"])) + self.flavour_dep = self.flavour_dep | data["attributes"]["flavour_dep"] + + # Handle recursive inclusions + if self.do_include: + for f in data["attributes"]["include"]: + include_fname = dirname(abspath(self.fname)) + "/" + f + data = self._load(include_fname) + self._json_parse(data, is_included=True) + + def _parse(self, data: str): + if self.do_json: + self._json_parse(data, is_included=False) + else: + self._legacy_parse(data) + + def _remove_entry(self, config: str): + if self.config[config]: + del self.config[config] + + def remove(self, config: str, arch: str = None, flavour: str = None): + if config not in self.config: + return + if arch is not None: + if flavour is not None: + flavour = f"{arch}-{flavour}" + else: + flavour = arch + del self.config[config]["policy"][flavour] + if not self.config[config]["policy"]: + self._remove_entry(config) + else: + self._remove_entry(config) + + def set( + self, + config: str, + arch: str = None, + flavour: str = None, + value: str = None, + note: str = None, + ): + if value is not None: + if config not in self.config: + self.config[config] = {"policy": {}} + if arch is not None: + if flavour is not None: + flavour = f"{arch}-{flavour}" + else: + flavour = arch + self.config[config]["policy"][flavour] = value + else: + for a in self.arch: + self.config[config]["policy"][a] = value + if note is not None: + self.config[config]["note"] = "'" + note.replace("'", "") + "'" + + def update(self, c: KConfig, arch: str, flavour: str = None, configs: list = None): + """Merge configs from a Kconfig object into Annotation object""" + + # Determine if we need to import all configs or a single config + if not configs: + configs = c.config.keys() + try: + configs |= self.search_config(arch=arch, flavour=flavour).keys() + except TypeError: + configs = { + **configs, + **self.search_config(arch=arch, flavour=flavour).keys(), + } + + # Import configs from the Kconfig object into Annotations + flavour_arg = flavour + if flavour is not None: + flavour = arch + f"-{flavour}" + else: + flavour = arch + for conf in configs: + if conf in c.config: + val = c.config[conf] + else: + val = "-" + if conf in self.config: + if "policy" in self.config[conf]: + # Add a TODO if a config with a note is changing and print + # a warning + old_val = self.search_config(config=conf, arch=arch, flavour=flavour_arg) + if old_val: + old_val = old_val[conf] + if val != old_val and "note" in self.config[conf]: + self.config[conf]["note"] = "TODO: update note" + print(f"WARNING: {conf} changed from {old_val} to {val}, updating note") + self.config[conf]["policy"][flavour] = val + else: + self.config[conf]["policy"] = {flavour: val} + else: + self.config[conf] = {"policy": {flavour: val}} + + def _compact(self): + # Try to remove redundant settings: if the config value of a flavour is + # the same as the one of the main arch simply drop it. + for conf in self.config.copy(): + if "policy" not in self.config[conf]: + continue + for flavour in self.flavour: + if flavour not in self.config[conf]["policy"]: + continue + m = re.match(r"^(.*?)-(.*)$", flavour) + if not m: + continue + arch = m.group(1) + if arch in self.config[conf]["policy"]: + if self.config[conf]["policy"][flavour] == self.config[conf]["policy"][arch]: + del self.config[conf]["policy"][flavour] + continue + if flavour not in self.flavour_dep: + continue + generic = self.flavour_dep[flavour] + if generic in self.config[conf]["policy"]: + if self.config[conf]["policy"][flavour] == self.config[conf]["policy"][generic]: + del self.config[conf]["policy"][flavour] + continue + # Remove rules for flavours / arches that are not supported (not + # listed in the annotations header). + for flavour in self.config[conf]["policy"].copy(): + if flavour not in list(set(self.arch + self.flavour)): + del self.config[conf]["policy"][flavour] + # Remove configs that are all undefined across all arches/flavours + # (unless we have includes) + if not self.include: + if "policy" in self.config[conf]: + if list(set(self.config[conf]["policy"].values())) == ["-"]: + self.config[conf]["policy"] = {} + # Drop empty rules + if not self.config[conf]["policy"]: + del self.config[conf] + else: + # Compact same value across all flavour within the same arch + for arch in self.arch: + arch_flavours = [i for i in self.flavour if i.startswith(arch)] + value = None + for flavour in arch_flavours: + if flavour not in self.config[conf]["policy"]: + break + if value is None: + value = self.config[conf]["policy"][flavour] + elif value != self.config[conf]["policy"][flavour]: + break + else: + for flavour in arch_flavours: + del self.config[conf]["policy"][flavour] + self.config[conf]["policy"][arch] = value + # After the first round of compaction we may end up having configs that + # are undefined across all arches, so do another round of compaction to + # drop these settings that are not needed anymore + # (unless we have includes). + if not self.include: + for conf in self.config.copy(): + # Remove configs that are all undefined across all arches/flavours + if "policy" in self.config[conf]: + if list(set(self.config[conf]["policy"].values())) == ["-"]: + self.config[conf]["policy"] = {} + # Drop empty rules + if not self.config[conf]["policy"]: + del self.config[conf] + + @staticmethod + def _sorted(config): + """Sort configs alphabetically but return configs with a note first""" + w_note = [] + wo_note = [] + for c in sorted(config): + if "note" in config[c]: + w_note.append(c) + else: + wo_note.append(c) + return w_note + wo_note + + def save(self, fname: str): + """Save annotations data to the annotation file""" + # Compact annotations structure + self._compact() + + # Save annotations to disk + with tempfile.NamedTemporaryFile(mode="w+t", delete=False) as tmp: + # Write header + tmp.write(self.header + "\n") + + # Write includes + for i in self.include: + tmp.write(f'include "{i}"\n') + if self.include: + tmp.write("\n") + + # Write config annotations and notes + tmp.flush() + shutil.copy(tmp.name, fname) + tmp_a = Annotation(fname) + + # Only save local differences (preserve includes) + marker = False + for conf in self._sorted(self.config): + new_val = self.config[conf] + if "policy" not in new_val: + continue + + # If new_val is a subset of old_val, skip it unless there are + # new notes that are different than the old ones. + old_val = tmp_a.config.get(conf) + if old_val and "policy" in old_val: + try: + can_skip = old_val["policy"] == old_val["policy"] | new_val["policy"] + except TypeError: + can_skip = old_val["policy"] == { + **old_val["policy"], + **new_val["policy"], + } + if can_skip: + if "note" not in new_val: + continue + if "note" in old_val and "note" in new_val: + if old_val["note"] == new_val["note"]: + continue + + # Write out the policy (and note) line(s) + val = dict(sorted(new_val["policy"].items())) + line = f"{conf: <47} policy<{val}>" + if "note" in new_val: + val = new_val["note"] + if new_val.get("oneline", False): + # Single line + line += f" note<{val}>" + else: + # Separate policy and note lines, + # followed by an empty line + line += f"\n{conf: <47} note<{val}>\n" + elif not marker: + # Write out a marker indicating the start of annotations + # without notes + tmp.write("\n# ---- Annotations without notes ----\n\n") + marker = True + tmp.write(line + "\n") + + # Replace annotations with the updated version + tmp.flush() + shutil.move(tmp.name, fname) + + def search_config(self, config: str = None, arch: str = None, flavour: str = None) -> dict: + """Return config value of a specific config option or architecture""" + if flavour is None: + flavour = "generic" + flavour = f"{arch}-{flavour}" + if flavour in self.flavour_dep: + generic = self.flavour_dep[flavour] + else: + generic = flavour + if config is None and arch is None: + # Get all config options for all architectures + return self.config + if config is None and arch is not None: + # Get config options of a specific architecture + ret = {} + for c, val in self.config.items(): + if "policy" not in val: + continue + if flavour in val["policy"]: + ret[c] = val["policy"][flavour] + elif generic != flavour and generic in val["policy"]: + ret[c] = val["policy"][generic] + elif arch in val["policy"]: + ret[c] = val["policy"][arch] + return ret + if config is not None and arch is None: + # Get a specific config option for all architectures + return self.config[config] if config in self.config else None + if config is not None and arch is not None: + # Get a specific config option for a specific architecture + if config in self.config: + if "policy" in self.config[config]: + if flavour in self.config[config]["policy"]: + return {config: self.config[config]["policy"][flavour]} + if generic != flavour and generic in self.config[config]["policy"]: + return {config: self.config[config]["policy"][generic]} + if arch in self.config[config]["policy"]: + return {config: self.config[config]["policy"][arch]} + return None + + @staticmethod + def to_config(data: dict) -> str: + """Convert annotations data to .config format""" + s = "" + for c in data: + v = data[c] + if v == "n": + s += f"# {c} is not set\n" + elif v == "-": + pass + else: + s += f"{c}={v}\n" + return s.rstrip() diff --git a/debian/scripts/misc/kconfig/run.py b/debian/scripts/misc/kconfig/run.py new file mode 100644 index 00000000000000..c8505b76a1d1a1 --- /dev/null +++ b/debian/scripts/misc/kconfig/run.py @@ -0,0 +1,375 @@ +# -*- mode: python -*- +# Manage Ubuntu kernel .config and annotations +# Copyright © 2022 Canonical Ltd. + +import argparse +import json +import os +import sys +from signal import SIG_DFL, SIGPIPE, signal + +try: + from argcomplete import autocomplete +except ModuleNotFoundError: + # Allow to run this program also when argcomplete is not available + def autocomplete(_unused): + pass + + +from kconfig.annotations import Annotation, KConfig # noqa: E402 Import not at top of file +from kconfig.utils import arg_fail, autodetect_annotations # noqa: E402 Import not at top of file +from kconfig.version import ANNOTATIONS_FORMAT_VERSION, VERSION # noqa: E402 Import not at top of file + +SKIP_CONFIGS = ( + # CONFIG_VERSION_SIGNATURE is dynamically set during the build + "CONFIG_VERSION_SIGNATURE", + # Allow to use a different versions of toolchain tools + "CONFIG_GCC_VERSION", + "CONFIG_CC_VERSION_TEXT", + "CONFIG_AS_VERSION", + "CONFIG_LD_VERSION", + "CONFIG_LLD_VERSION", + "CONFIG_CLANG_VERSION", + "CONFIG_PAHOLE_VERSION", + "CONFIG_RUSTC_VERSION_TEXT", + "CONFIG_BINDGEN_VERSION_TEXT", +) + + +def removeprefix(data, prefix): + if data[: len(prefix)] == prefix: + data = data[len(prefix) :] + return data + + +def make_parser(): + parser = argparse.ArgumentParser( + description="Manage Ubuntu kernel .config and annotations", + ) + parser.add_argument("--version", "-v", action="version", version=f"%(prog)s {VERSION}") + + parser.add_argument( + "--file", + "-f", + action="store", + help="Pass annotations or .config file to be parsed", + ) + parser.add_argument("--arch", "-a", action="store", help="Select architecture") + parser.add_argument("--flavour", "-l", action="store", help='Select flavour (default is "generic")') + parser.add_argument("--config", "-c", action="store", help="Select a specific config option") + parser.add_argument("--query", "-q", action="store_true", help="Query annotations") + parser.add_argument( + "--note", + "-n", + action="store", + help="Write a specific note to a config option in annotations", + ) + parser.add_argument( + "--autocomplete", + action="store_true", + help="Enable config bash autocomplete: `source <(annotations --autocomplete)`", + ) + parser.add_argument( + "--source", + "-t", + action="store_true", + help="Jump to a config definition in the kernel source code", + ) + parser.add_argument( + "--no-include", + action="store_true", + help="Do not process included annotations (stop at the main file)", + ) + parser.add_argument( + "--json", + action="store_true", + help="Try to parse annotations file in pure JSON format", + ) + + ga = parser.add_argument_group(title="Action").add_mutually_exclusive_group(required=False) + ga.add_argument( + "--write", + "-w", + action="store", + metavar="VALUE", + dest="value", + help="Set a specific config value in annotations (use 'null' to remove)", + ) + ga.add_argument( + "--export", + "-e", + action="store_true", + help="Convert annotations to .config format", + ) + ga.add_argument( + "--import", + "-i", + action="store", + metavar="FILE", + dest="import_file", + help="Import a full .config for a specific arch and flavour into annotations", + ) + ga.add_argument( + "--update", + "-u", + action="store", + metavar="FILE", + dest="update_file", + help="Import a partial .config into annotations (only resync configs specified in FILE)", + ) + ga.add_argument( + "--check", + "-k", + action="store", + metavar="FILE", + dest="check_file", + help="Validate kernel .config with annotations", + ) + return parser + + +_ARGPARSER = make_parser() + + +def export_result(data): + # Dump metadata / attributes first + out = '{\n "attributes": {\n' + for key, value in sorted(data["attributes"].items()): + out += f' "{key}": {json.dumps(value)},\n' + out = out.rstrip(",\n") + out += "\n }," + print(out) + + configs_with_note = {key: value for key, value in data["config"].items() if "note" in value} + configs_without_note = {key: value for key, value in data["config"].items() if "note" not in value} + + # Dump configs, sorted alphabetically, showing items with a note first + out = ' "config": {\n' + for key in sorted(configs_with_note) + sorted(configs_without_note): + policy = data["config"][key]["policy"] + if "note" in data["config"][key]: + note = data["config"][key]["note"] + out += f' "{key}": {{"policy": {json.dumps(policy)}, "note": {json.dumps(note)}}},\n' + else: + out += f' "{key}": {{"policy": {json.dumps(policy)}}},\n' + out = out.rstrip(",\n") + out += "\n }\n}" + print(out) + + +def print_result(config, data): + if data is not None and config is not None and config not in data: + data = {config: data} + print(json.dumps(data, sort_keys=True, indent=2)) + + +def do_query(args): + if args.arch is None and args.flavour is not None: + arg_fail(_ARGPARSER, "error: --flavour requires --arch") + a = Annotation(args.file, do_include=(not args.no_include), do_json=args.json) + res = a.search_config(config=args.config, arch=args.arch, flavour=args.flavour) + # If no arguments are specified dump the whole annotations structure + if args.config is None and args.arch is None and args.flavour is None: + res = { + "attributes": { + "arch": a.arch, + "flavour": a.flavour, + "flavour_dep": a.flavour_dep, + "include": a.include, + "_version": ANNOTATIONS_FORMAT_VERSION, + }, + "config": res, + } + export_result(res) + else: + print_result(args.config, res) + + +def do_autocomplete(args): + a = Annotation(args.file) + res = (removeprefix(c, "CONFIG_") for c in a.search_config()) + res_str = " ".join(res) + print(f'complete -W "{res_str}" annotations') + + +def do_source(args): + if args.config is None: + arg_fail(_ARGPARSER, "error: --source requires --config") + if not os.path.exists("tags"): + print("tags not found in the current directory, try: `make tags`") + sys.exit(1) + os.system(f"vim -t {args.config}") + + +def do_note(args): + if args.config is None: + arg_fail(_ARGPARSER, "error: --note requires --config") + + # Set the note in annotations + a = Annotation(args.file) + a.set(args.config, note=args.note) + + # Save back to annotations + a.save(args.file) + + # Query and print back the value + a = Annotation(args.file) + res = a.search_config(config=args.config) + print_result(args.config, res) + + +def do_write(args): + if args.config is None: + arg_fail(_ARGPARSER, "error: --write requires --config") + + # Set the value in annotations ('null' means remove) + a = Annotation(args.file) + if args.value == "null": + a.remove(args.config, arch=args.arch, flavour=args.flavour) + else: + a.set( + args.config, + arch=args.arch, + flavour=args.flavour, + value=args.value, + note=args.note, + ) + + # Save back to annotations + a.save(args.file) + + # Query and print back the value + a = Annotation(args.file) + res = a.search_config(config=args.config) + print_result(args.config, res) + + +def do_export(args): + if args.arch is None: + arg_fail(_ARGPARSER, "error: --export requires --arch") + a = Annotation(args.file) + conf = a.search_config(config=args.config, arch=args.arch, flavour=args.flavour) + if conf: + print(a.to_config(conf)) + + +def do_import(args): + if args.arch is None: + arg_fail(_ARGPARSER, "error: --arch is required with --import") + if args.flavour is None: + arg_fail(_ARGPARSER, "error: --flavour is required with --import") + if args.config is not None: + arg_fail(_ARGPARSER, "error: --config cannot be used with --import (try --update)") + + # Merge with the current annotations + a = Annotation(args.file) + c = KConfig(args.import_file) + a.update(c, arch=args.arch, flavour=args.flavour) + + # Save back to annotations + a.save(args.file) + + +def do_update(args): + if args.arch is None: + arg_fail(_ARGPARSER, "error: --arch is required with --update") + + # Merge with the current annotations + a = Annotation(args.file) + c = KConfig(args.update_file) + if args.config is None: + configs = list(set(c.config.keys()) - set(SKIP_CONFIGS)) + if configs: + a.update(c, arch=args.arch, flavour=args.flavour, configs=configs) + + # Save back to annotations + a.save(args.file) + + +def do_check(args): + # Determine arch and flavour + if args.arch is None: + arg_fail(_ARGPARSER, "error: --arch is required with --check") + + print(f"check-config: loading annotations from {args.file}") + total = good = ret = 0 + + # Load annotations settings + a = Annotation(args.file) + a_configs = a.search_config(arch=args.arch, flavour=args.flavour).keys() + + # Parse target .config + c = KConfig(args.check_file) + c_configs = c.config.keys() + + # Validate .config against annotations + for conf in sorted(a_configs | c_configs): + if conf in SKIP_CONFIGS: + continue + entry = a.search_config(config=conf, arch=args.arch, flavour=args.flavour) + expected = entry[conf] if entry else "-" + value = c.config[conf] if conf in c.config else "-" + if value != expected: + policy = a.config[conf] if conf in a.config else "undefined" + if "policy" in policy: + policy = f"policy<{policy['policy']}>" + print(f"check-config: {conf} changed from {expected} to {value}: {policy})") + ret = 1 + else: + good += 1 + total += 1 + + num = total - good + if ret: + if os.path.exists(".git"): + print(f"check-config: {num} config options have been changed, review them with `git diff`") + else: + print(f"check-config: {num} config options have changed") + else: + print("check-config: all good") + sys.exit(ret) + + +def main(): + # Prevent broken pipe errors when showing output in pipe to other tools + # (less for example) + signal(SIGPIPE, SIG_DFL) + + # Main annotations program + autocomplete(_ARGPARSER) + args = _ARGPARSER.parse_args() + + if args.file is None: + args.file = autodetect_annotations() + if args.file is None: + arg_fail( + _ARGPARSER, + "error: could not determine DEBDIR, try using: --file/-f", + show_usage=False, + ) + + if args.config and not args.config.startswith("CONFIG_"): + args.config = "CONFIG_" + args.config + + if args.value: + do_write(args) + elif args.note: + do_note(args) + elif args.export: + do_export(args) + elif args.import_file: + do_import(args) + elif args.update_file: + do_update(args) + elif args.check_file: + do_check(args) + elif args.autocomplete: + do_autocomplete(args) + elif args.source: + do_source(args) + else: + do_query(args) + + +if __name__ == "__main__": + main() diff --git a/debian/scripts/misc/kconfig/utils.py b/debian/scripts/misc/kconfig/utils.py new file mode 100644 index 00000000000000..f4ced6b33f4a04 --- /dev/null +++ b/debian/scripts/misc/kconfig/utils.py @@ -0,0 +1,20 @@ +# -*- mode: python -*- +# Misc helpers for Kconfig and annotations +# Copyright © 2023 Canonical Ltd. + +import sys + + +def autodetect_annotations(): + try: + with open("debian/debian.env", "rt", encoding="utf-8") as fd: + return fd.read().rstrip().split("=")[1] + "/config/annotations" + except (FileNotFoundError, IndexError): + return None + + +def arg_fail(parser, message, show_usage=True): + print(message) + if show_usage: + parser.print_usage() + sys.exit(1) diff --git a/debian/scripts/misc/kconfig/version.py b/debian/scripts/misc/kconfig/version.py new file mode 100644 index 00000000000000..833ffa34654bb6 --- /dev/null +++ b/debian/scripts/misc/kconfig/version.py @@ -0,0 +1,10 @@ +# -*- mode: python -*- +# version of annotations module +# Copyright © 2022 Canonical Ltd. + +VERSION = "0.1" + +ANNOTATIONS_FORMAT_VERSION = 5 + +if __name__ == "__main__": + print(VERSION) diff --git a/debian/scripts/misc/kernelconfig b/debian/scripts/misc/kernelconfig new file mode 100755 index 00000000000000..035426762f8a7e --- /dev/null +++ b/debian/scripts/misc/kernelconfig @@ -0,0 +1,178 @@ +#!/bin/bash -u +# +# Manage kernel config annotations +# +# Supported environment variales: +# conc_level : Concurrency level for upstream make (-jX) +# skip_checks : Skip config checks if set to 'true' +# gcc : Default gcc to use (mandatory) +# + +function cleanup() +{ + rm -rf build "${TMP_DIR}" +} + +# We have to be in the top level Ubuntu kernel source directory +if ! [ -e debian/debian.env ] ; then + echo "ERROR: This is not an Ubuntu kernel source directory" >&2 + exit 1 +fi + +if [ -z "${gcc:-}" ] ; then + echo "ERROR: 'gcc' environment variable must be set" >&2 + exit 1 +fi + +if [ ${#} -ne 1 ] ; then + echo "Usage: $0 updateconfigs|defaultconfigs|genconfigs|editconfigs" + exit 2 +fi + +mode=${1} + +case "${mode}" in + updateconfigs) target="syncconfig" ;; + defaultconfigs) target="olddefconfig" ;; + genconfigs) target="oldconfig" ;; + editconfigs) ;; # Target is set later based on user input + *) echo "ERROR: Invalid mode: ${1}" >&2 + exit 1 ;; +esac + +. debian/debian.env + +annotations_file=${DEBIAN}/config/annotations +warning_partial=() + +TMP_DIR=$(mktemp -d) +trap cleanup EXIT + +# Use annotations to generate configs +FLAVOURS=$(sed -ne 's/^# FLAVOUR: //p' "${annotations_file}") + +for arch_flavour in ${FLAVOURS} ; do + arch=${arch_flavour%%-*} + flavour=${arch_flavour#*-} + tmp_conf_file=${TMP_DIR}/${arch}-config.flavour.${flavour} + + # Map debian archs to kernel archs + case "${arch}" in + amd64) kern_arch="x86_64" ;; + arm64) kern_arch="arm64" ;; + armhf) kern_arch="arm" ;; + ppc64el) kern_arch="powerpc" ;; + riscv64) kern_arch="riscv" ;; + s390x) kern_arch="s390" ;; + *) echo "WARNING: Unsupported architecture: ${arch}" + warning_partial+=("${arch}") + continue ;; + esac + + # Determine cross toolchain to use for Kconfig compiler tests + cross_compile="$(dpkg-architecture -qDEB_HOST_GNU_TYPE -a"${arch}" 2>/dev/null)-" + + # Arch-specific compiler, if any + arch_gcc=$(cat < build/.config + + # Environment variables for 'make *config' + env=(ARCH="${kern_arch}" + DEB_ARCH="${arch}" + CROSS_COMPILE="${cross_compile}" + CC="${gcc_path}") + + # Concurrency level + if [ -n "${conc_level:-}" ] ; then + env+=("${conc_level}") + fi + + # Call config target + echo + echo "* Run ${target} on ${arch}/${flavour} ..." + ${kmake} O=build "${env[@]}" "${target}" + + # Move config for further processing + mv build/.config "${tmp_conf_file}" +done + +rc=0 + +if [ "${skip_checks:-}" = "true" ] ; then + echo + echo "Skipping config-check (skip_checks=${skip_checks}) ..." +else + echo + echo "Running config-check for all configurations ..." + fail=0 + for arch_flavour in ${FLAVOURS} ; do + arch=${arch_flavour%%-*} + flavour=${arch_flavour#*-} + tmp_conf_file=${TMP_DIR}/${arch}-config.flavour.${flavour} + + echo + echo "* Run config-check for ${arch}-${flavour} ..." + python3 debian/scripts/misc/annotations -f "${annotations_file}" \ + --arch "${arch}" --flavour "${flavour}" --check "${tmp_conf_file}" || \ + fail=$((fail + 1)) + done + + if [ ${fail} -gt 0 ] ; then + rc=1 + echo "ERROR: ${fail} config-check failures detected" >&2 + fi +fi + +if [ ${#warning_partial[@]} -gt 0 ] ; then + rc=1 + echo "ERROR: Config operation not applied to all architectures (skipped ${warning_partial[*]})" >&2 +fi + +# Recreate the annotations file +if [ "${mode}" = "genconfigs" ] ; then + rm -rf CONFIGS + mv "${TMP_DIR}" CONFIGS +else + echo + echo "Importing all configurations ..." + echo + for arch_flavour in ${FLAVOURS} ; do + arch=${arch_flavour%%-*} + flavour=${arch_flavour#*-} + tmp_conf_file=${TMP_DIR}/${arch}-config.flavour.${flavour} + + echo "* Import configs for ${arch}-${flavour} ..." + python3 debian/scripts/misc/annotations -f "${annotations_file}" \ + --arch "${arch}" --flavour "${flavour}" --import "${tmp_conf_file}" + done +fi + +exit "${rc}" diff --git a/debian/scripts/sign-module b/debian/scripts/sign-module new file mode 100755 index 00000000000000..03ce543de7f8e3 --- /dev/null +++ b/debian/scripts/sign-module @@ -0,0 +1,40 @@ +#!/bin/bash -eu +# +# Staging drivers must not be signed if they are not listed in a +# signature-inclusion file to prevent loading of 'unsafe' drivers in a +# Secure Boot environment. +# +# Exit with status 0 if the provided module needs to be signed, 1 otherwise +# + +mod=${1} + +# Sign the module if not a staging driver +if [ "${mod/\/drivers\/staging\//}" = "${mod}" ] ; then + exit 0 +fi + +root=$(dirname "$(realpath -e "${0}")")/../.. +. "${root}"/debian/debian.env + +# Collect the signature-inclusion files +sig_incls=() +for d in debian "${DEBIAN}" ; do + if [ -f "${root}"/"${d}"/signature-inclusion ] ; then + sig_incls+=("${root}"/"${d}"/signature-inclusion) + fi +done + +# Sign the module if no signature-inclusion files +if [ ${#sig_incls[@]} -eq 0 ] ; then + exit 0 +fi + +# Sign the module if listed in signature-inclusion files +if grep -qFx "${mod##*/}" "${sig_incls[@]}" ; then + exit 0 +fi + +# Don't sign the module +echo "UBUNTU: Not signing ${1}" +exit 1 diff --git a/debian/scripts/ubuntu-compatible-signing b/debian/scripts/ubuntu-compatible-signing new file mode 100644 index 00000000000000..53a1f152f6f8d4 --- /dev/null +++ b/debian/scripts/ubuntu-compatible-signing @@ -0,0 +1,7 @@ +#!/bin/sh + +echo $( + grep -qx ' *Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v3)' debian/canonical-revoked-certs.pem && echo ubuntu/4 pro/3 + grep -qx ' *Subject: CN=Canonical Ltd. Live Patch Signing 2025 Kmod' debian/canonical-certs.pem && echo livepatch:2025 + grep -qx ' *Subject: CN=Canonical Ltd. Kernel Module Signing 2025 Kmod' debian/canonical-certs.pem && echo kmod:2025 +) diff --git a/debian/signature-inclusion b/debian/signature-inclusion new file mode 100644 index 00000000000000..f9d40bc736c3b2 --- /dev/null +++ b/debian/signature-inclusion @@ -0,0 +1,6 @@ +# +# This file lists the staging drivers that are safe for signing +# and loading in a secure boot environment with signed module enforcement. +# +intel-ipu7-isys.ko +intel-ipu7.ko diff --git a/debian/snapcraft.mk b/debian/snapcraft.mk new file mode 100644 index 00000000000000..bbccdcc2fecadf --- /dev/null +++ b/debian/snapcraft.mk @@ -0,0 +1,11 @@ +ifeq ($(ARCH),) + arch := $(shell uname -m | sed -e s/i.86/i386/ -e s/x86_64/amd64/ \ + -e s/arm.*/armhf/ -e s/s390/s390x/ -e s/ppc.*/powerpc/ \ + -e s/aarch64.*/arm64/ ) +else ifeq ($(ARCH),arm) + arch := armhf +else + arch := $(ARCH) +endif +config: + python3 debian/scripts/misc/annotations --export --arch $(arch) --flavour $(flavour) >.config diff --git a/debian/source/format b/debian/source/format new file mode 100644 index 00000000000000..d3827e75a5cadb --- /dev/null +++ b/debian/source/format @@ -0,0 +1 @@ +1.0 diff --git a/debian/source/options b/debian/source/options new file mode 100644 index 00000000000000..d32952b597537d --- /dev/null +++ b/debian/source/options @@ -0,0 +1,9 @@ +# Ignore vbox symlinks, we will regenerate these at clean (LP:1426113) +## autoreconstruct -- begin +# Ignore any symlinks created since the orig which are rebuilt by reconstruct. +extend-diff-ignore=^ubuntu/igh-ecat/master/rtdm-ioctl.c$ +## autoreconstruct -- end + +# force "dpkg-source -I -i" behavior +diff-ignore +tar-ignore diff --git a/debian/templates/extra.postinst.in b/debian/templates/extra.postinst.in new file mode 100755 index 00000000000000..c4a556c5a6b947 --- /dev/null +++ b/debian/templates/extra.postinst.in @@ -0,0 +1,20 @@ +#!/bin/sh +set -e + +version=@abiname@@localversion@ +image_path=/boot/@image-stem@-$version + +if [ "$1" != configure ]; then + exit 0 +fi + +depmod -a -F /boot/System.map-$version $version || true +if [ -d /etc/kernel/postinst.d ]; then + cat - >/usr/lib/linux/triggers/$version </dev/null || true +# +# We should be rebuilding the initramfs here on removal to pare down the +# initramfs if it contains any of the objects we just removed. But people +# commonly remove kernels in order to free space in /boot, and rebuilding the +# initramfs now risks ENOSPC when we are trying to make space. The files we +# leave lying about could be confusing, but we trade that against safety on +# removal. +# +#if [ -d /etc/kernel/postinst.d ]; then +# # We want to behave as if linux-image (without us) was installed, therefore +# # we do not want the postinst support to know we are being removed, claim +# # this is an installation event. +# cat - >/usr/lib/linux/triggers/$version </usr/lib/linux/triggers/$version </dev/null; then + linux-update-symlinks remove $version $image_path +fi + +if [ -d /etc/kernel/postrm.d ]; then + # We cannot trigger ourselves as at the end of this we will no longer + # exist and can no longer respond to the trigger. The trigger would + # then become lost. Therefore we clear any pending trigger and apply + # postrm directly. + if [ -f /usr/lib/linux/triggers/$version ]; then + echo "$0 ... removing pending trigger" + rm -f /usr/lib/linux/triggers/$version + fi + DEB_MAINT_PARAMS="$*" run-parts --report --exit-on-error --arg=$version \ + --arg=$image_path /etc/kernel/postrm.d +fi + +if [ "$1" = purge ]; then + for extra_file in modules.dep modules.isapnpmap modules.pcimap \ + modules.usbmap modules.parportmap \ + modules.generic_string modules.ieee1394map \ + modules.ieee1394map modules.pnpbiosmap \ + modules.alias modules.ccwmap modules.inputmap \ + modules.symbols modules.ofmap \ + modules.seriomap modules.\*.bin \ + modules.softdep modules.weakdep modules.devname; do + eval rm -f /usr/lib/modules/$version/$extra_file + done + rmdir /usr/lib/modules/$version || true +fi + +exit 0 diff --git a/debian/templates/image.preinst.in b/debian/templates/image.preinst.in new file mode 100755 index 00000000000000..3b7a47b1f16a2e --- /dev/null +++ b/debian/templates/image.preinst.in @@ -0,0 +1,22 @@ +#!/bin/sh +set -e + +version=@abiname@@localversion@ +image_path=/boot/@image-stem@-$version + +if [ "$1" = abort-upgrade ]; then + exit 0 +fi + +if [ "$1" = install ]; then + # Create a flag file for postinst + mkdir -p /usr/lib/modules/$version + touch /usr/lib/modules/$version/.fresh-install +fi + +if [ -d /etc/kernel/preinst.d ]; then + DEB_MAINT_PARAMS="$*" run-parts --report --exit-on-error --arg=$version \ + --arg=$image_path /etc/kernel/preinst.d +fi + +exit 0 diff --git a/debian/templates/image.prerm.in b/debian/templates/image.prerm.in new file mode 100755 index 00000000000000..347104d6e18240 --- /dev/null +++ b/debian/templates/image.prerm.in @@ -0,0 +1,18 @@ +#!/bin/sh +set -e + +version=@abiname@@localversion@ +image_path=/boot/@image-stem@-$version + +if [ "$1" != remove ]; then + exit 0 +fi + +linux-check-removal $version + +if [ -d /etc/kernel/prerm.d ]; then + DEB_MAINT_PARAMS="$*" run-parts --report --exit-on-error --arg=$version \ + --arg=$image_path /etc/kernel/prerm.d +fi + +exit 0 diff --git a/debian/tests/control b/debian/tests/control new file mode 100644 index 00000000000000..d083d656226131 --- /dev/null +++ b/debian/tests/control @@ -0,0 +1,7 @@ +Tests: rebuild +Depends: @builddeps@, fakeroot +Restrictions: allow-stderr, skippable + +Tests: ubuntu-regression-suite +Depends: build-essential, fakeroot, gcc-multilib [amd64 armhf i386], gdb, git, python3, snapd, fuse-overlayfs +Restrictions: allow-stderr, isolation-machine, breaks-testbed, skippable diff --git a/debian/tests/rebuild b/debian/tests/rebuild new file mode 100755 index 00000000000000..365835c92d9269 --- /dev/null +++ b/debian/tests/rebuild @@ -0,0 +1,20 @@ +#!/bin/sh + +# If we are triggering for just linux or linux-meta we know we have +# just built the kernel and there is no point in repeating that +# build, it just wastes time. (LP: #1498862) +build_needed=0 +for trigger in ${ADT_TEST_TRIGGERS:-force} +do + case "$trigger" in + linux/*|linux-lts-*/*|linux-meta*/*|linux-oem*/*|fakeroot/*|gdb/*|git/*|bzr/*|gcc-multilib/*) ;; + *) build_needed=1 ;; + esac +done +if [ "$build_needed" -eq 0 ]; then + echo "rebuild: short circuiting build for '${ADT_TEST_TRIGGERS}'" + exit 77 +fi + +set -e +dpkg-buildpackage -rfakeroot -us -uc -b -Pautopkgtest diff --git a/debian/tests/ubuntu-regression-suite b/debian/tests/ubuntu-regression-suite new file mode 100755 index 00000000000000..ba820f6102d73a --- /dev/null +++ b/debian/tests/ubuntu-regression-suite @@ -0,0 +1,46 @@ +#!/bin/sh +set -e + +# Only run regression-suite on kernels we can boot in canonistack +source=`dpkg-parsechangelog -SSource` +case $source in + linux|linux-unstable|linux-hwe*|linux-lowlatency*|linux-kvm|linux-oem) + ;; + *) + echo "ubuntu-regression-suite is pointless, if one cannot boot the kernel" + exit 77 + ;; +esac + +# Only run regression-suite if we were requested to +have_meta=0 +for trigger in ${ADT_TEST_TRIGGERS} +do + case "$trigger" in + linux-meta/*|linux-meta-*/*) + have_meta=1 + ;; + esac +done +if [ -n "$ADT_TEST_TRIGGERS" ] && [ "$have_meta" -eq 0 ]; then + echo "ubuntu-regression-suite is not requested, as there is no linux-meta trigger" + exit 77 +fi + +sver=`dpkg-parsechangelog -SVersion` +read x rver x &2 + exit 1 +fi + +git clone --depth=1 -b autotest3 https://git.launchpad.net/~canonical-kernel-team/+git/kernel-testing +git -C kernel-testing/ show HEAD -q +kernel-testing/run-dep8-tests diff --git a/debian/tools/generic b/debian/tools/generic new file mode 100644 index 00000000000000..62e9e2cc0989bc --- /dev/null +++ b/debian/tools/generic @@ -0,0 +1,36 @@ +#!/bin/bash +full_version=`uname -r` + +# First check for a fully qualified version. +this="/usr/lib/linux-tools/$full_version/`basename $0`" +if [ -f "$this" ]; then + exec "$this" "$@" +fi + +# Removing flavour from version i.e. generic or server. +flavour_abi=${full_version#*-} +flavour=${flavour_abi#*-} +version=${full_version%-$flavour} +this="$0_$version" +if [ -f "$this" ]; then + exec "$this" "$@" +fi + +flavour="-$flavour" +cld="" +std="" +lts=":" +# Give them a hint as to what to install. + echo "WARNING: `basename $0` not found for kernel $version" >&2 + echo "" >&2 + echo " You may need to install the following packages for this specific kernel:" >&2 + echo " linux-tools-$version$flavour" >&2 +$cld echo " linux-cloud-tools-$version$flavour" >&2 + echo "" >&2 + echo " You may also want to install one of the following packages to keep up to date:" >&2 +$std echo " linux-tools$flavour" >&2 +$std $cld echo " linux-cloud-tools$flavour" >&2 +$lts echo " linux-tools$flavour-lts-" >&2 +$lts $cld echo " linux-cloud-tools$flavour-lts-" >&2 + +exit 2 diff --git a/devbuildconfig.sh b/devbuildconfig.sh new file mode 100755 index 00000000000000..8b093cf8048049 --- /dev/null +++ b/devbuildconfig.sh @@ -0,0 +1,13 @@ +#!/bin/sh +make -j8 ubuntu_x1e_defconfig +scripts/config --undefine GDB_SCRIPTS +scripts/config --undefine DEBUG_INFO +scripts/config --undefine DEBUG_INFO_SPLIT +scripts/config --undefine DEBUG_INFO_REDUCED +scripts/config --undefine DEBUG_INFO_COMPRESSED +scripts/config --set-val DEBUG_INFO_NONE y +scripts/config --set-val DEBUG_INFO_DWARF5 n +scripts/config --disable DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT +scripts/config --disable SYSTEM_TRUSTED_KEYS +scripts/config --disable SYSTEM_REVOCATION_KEYS +make -j8 menuconfig diff --git a/drivers/Makefile b/drivers/Makefile index 0841ea851847e8..ede1725e801771 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -64,14 +64,9 @@ obj-y += char/ # iommu/ comes before gpu as gpu are using iommu controllers obj-y += iommu/ -# gpu/ comes after char for AGP vs DRM startup and after iommu -obj-y += gpu/ obj-$(CONFIG_CONNECTOR) += connector/ -# i810fb depends on char/agp/ -obj-$(CONFIG_FB_I810) += video/fbdev/i810/ - obj-$(CONFIG_PARPORT) += parport/ obj-y += base/ block/ misc/ mfd/ nfc/ obj-$(CONFIG_LIBNVDIMM) += nvdimm/ @@ -83,6 +78,11 @@ obj-y += macintosh/ obj-y += scsi/ obj-y += nvme/ obj-$(CONFIG_ATA) += ata/ + +# gpu/ comes after char for AGP vs DRM startup and after iommu +obj-y += gpu/ +# i810fb depends on char/agp/ +obj-$(CONFIG_FB_I810) += video/fbdev/i810/ obj-$(CONFIG_TARGET_CORE) += target/ obj-$(CONFIG_MTD) += mtd/ obj-$(CONFIG_SPI) += spi/ diff --git a/drivers/acpi/acpica/dswexec.c b/drivers/acpi/acpica/dswexec.c index 675aaa67101261..a89ddd1ab48cb0 100644 --- a/drivers/acpi/acpica/dswexec.c +++ b/drivers/acpi/acpica/dswexec.c @@ -397,11 +397,11 @@ acpi_status acpi_ds_exec_end_op(struct acpi_walk_state *walk_state) /* Resolve all operands */ + union acpi_operand_object **stack_ptr = NULL; + if (walk_state->num_operands > 0) + stack_ptr = ACPI_WALK_OPERANDS; status = acpi_ex_resolve_operands(walk_state->opcode, - &(walk_state-> - operands - [walk_state-> - num_operands - 1]), + stack_ptr, walk_state); } diff --git a/drivers/acpi/platform_profile.c b/drivers/acpi/platform_profile.c index 79d2e92e5c28d7..4b4600c99c4e28 100644 --- a/drivers/acpi/platform_profile.c +++ b/drivers/acpi/platform_profile.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -15,6 +16,8 @@ #define to_pprof_handler(d) (container_of(d, struct platform_profile_handler, dev)) static DEFINE_MUTEX(profile_lock); +static struct kobject *platform_profile_kobj; +static bool platform_profile_kobj_created; struct platform_profile_handler { const char *name; @@ -216,7 +219,7 @@ static ssize_t profile_store(struct device *dev, return ret; } - sysfs_notify(acpi_kobj, NULL, "platform_profile"); + sysfs_notify(platform_profile_kobj, NULL, "platform_profile"); return count; } @@ -436,7 +439,7 @@ static ssize_t platform_profile_store(struct kobject *kobj, return ret; } - sysfs_notify(acpi_kobj, NULL, "platform_profile"); + sysfs_notify(platform_profile_kobj, NULL, "platform_profile"); return count; } @@ -482,7 +485,7 @@ void platform_profile_notify(struct device *dev) scoped_cond_guard(mutex_intr, return, &profile_lock) { _notify_class_profile(dev, NULL); } - sysfs_notify(acpi_kobj, NULL, "platform_profile"); + sysfs_notify(platform_profile_kobj, NULL, "platform_profile"); } EXPORT_SYMBOL_GPL(platform_profile_notify); @@ -532,7 +535,7 @@ int platform_profile_cycle(void) return err; } - sysfs_notify(acpi_kobj, NULL, "platform_profile"); + sysfs_notify(platform_profile_kobj, NULL, "platform_profile"); return 0; } @@ -605,9 +608,9 @@ struct device *platform_profile_register(struct device *dev, const char *name, goto cleanup_ida; } - sysfs_notify(acpi_kobj, NULL, "platform_profile"); + sysfs_notify(platform_profile_kobj, NULL, "platform_profile"); - err = sysfs_update_group(acpi_kobj, &platform_profile_group); + err = sysfs_update_group(platform_profile_kobj, &platform_profile_group); if (err) goto cleanup_cur; @@ -641,8 +644,8 @@ void platform_profile_remove(struct device *dev) ida_free(&platform_profile_ida, pprof->minor); device_unregister(&pprof->dev); - sysfs_notify(acpi_kobj, NULL, "platform_profile"); - sysfs_update_group(acpi_kobj, &platform_profile_group); + sysfs_notify(platform_profile_kobj, NULL, "platform_profile"); + sysfs_update_group(platform_profile_kobj, &platform_profile_group); } EXPORT_SYMBOL_GPL(platform_profile_remove); @@ -690,24 +693,50 @@ static int __init platform_profile_init(void) { int err; - if (acpi_disabled) - return -EOPNOTSUPP; + /* + * The legacy sysfs interface at /sys/firmware/acpi/platform_profile + * is expected by userspace (power-profiles-daemon). On systems where + * ACPI is disabled (e.g. device-tree based ARM64 platforms such as + * the Surface Pro 11), the "acpi" directory is never created by the + * ACPI subsystem, so create it here to keep the interface available. + */ + if (acpi_kobj) { + platform_profile_kobj = acpi_kobj; + } else { + platform_profile_kobj = kobject_create_and_add("acpi", firmware_kobj); + if (!platform_profile_kobj) + return -ENOMEM; + platform_profile_kobj_created = true; + } err = class_register(&platform_profile_class); if (err) - return err; + goto err_kobj; - err = sysfs_create_group(acpi_kobj, &platform_profile_group); + err = sysfs_create_group(platform_profile_kobj, &platform_profile_group); if (err) - class_unregister(&platform_profile_class); + goto err_class; + + return 0; +err_class: + class_unregister(&platform_profile_class); +err_kobj: + if (platform_profile_kobj_created) { + kobject_put(platform_profile_kobj); + platform_profile_kobj = NULL; + } return err; } static void __exit platform_profile_exit(void) { - sysfs_remove_group(acpi_kobj, &platform_profile_group); + sysfs_remove_group(platform_profile_kobj, &platform_profile_group); class_unregister(&platform_profile_class); + if (platform_profile_kobj_created) { + kobject_put(platform_profile_kobj); + platform_profile_kobj = NULL; + } } module_init(platform_profile_init); module_exit(platform_profile_exit); diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 9a7ac2eb9ce0b8..9d9b1af371977e 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -859,9 +859,8 @@ static const char * const acpi_honor_dep_ids[] = { "INTC1095", /* IVSC (ADL) driver must be loaded to allow i2c access to camera sensors */ "INTC100A", /* IVSC (RPL) driver must be loaded to allow i2c access to camera sensors */ "INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to camera sensors */ - "INTC10DE", /* CVS (LNL) driver must be loaded to allow camera streaming */ - "INTC10E0", /* CVS (ARL) driver must be loaded to allow camera streaming */ - "INTC10E1", /* CVS (PTL) driver must be loaded to allow camera streaming */ + "INTC10DE", /* IVSC (LNL) driver must be loaded to allow i2c access to camera sensors */ + "INTC10E0", /* IVSC (ARL) driver must be loaded to allow i2c access to camera sensors */ "RSCV0001", /* RISC-V PLIC */ "RSCV0002", /* RISC-V APLIC */ "RSCV0005", /* RISC-V SBI MPXY MBOX */ diff --git a/drivers/android/Kconfig b/drivers/android/Kconfig index e2e402c9d1759c..20c985de667e13 100644 --- a/drivers/android/Kconfig +++ b/drivers/android/Kconfig @@ -2,7 +2,7 @@ menu "Android" config ANDROID_BINDER_IPC - bool "Android Binder IPC Driver" + tristate "Android Binder IPC Driver" depends on MMU depends on NET default n @@ -28,8 +28,8 @@ config ANDROID_BINDER_IPC_RUST between said processes. config ANDROID_BINDERFS - bool "Android Binderfs filesystem" - depends on ANDROID_BINDER_IPC + tristate "Android Binderfs filesystem" + depends on (ANDROID_BINDER_IPC=y) || (ANDROID_BINDER_IPC=m && m) default n help Binderfs is a pseudo-filesystem for the Android Binder IPC driver diff --git a/drivers/android/Makefile b/drivers/android/Makefile index e0c650d3898ede..81ac0681fa1b2d 100644 --- a/drivers/android/Makefile +++ b/drivers/android/Makefile @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only ccflags-y += -I$(src) # needed for trace events -obj-$(CONFIG_ANDROID_BINDERFS) += binderfs.o -obj-$(CONFIG_ANDROID_BINDER_IPC) += binder.o binder_alloc.o binder_netlink.o -obj-$(CONFIG_ANDROID_BINDER_ALLOC_KUNIT_TEST) += tests/ -obj-$(CONFIG_ANDROID_BINDER_IPC_RUST) += binder/ +binder_linux-y := binder.o binder_alloc.o binder_netlink.o +obj-$(CONFIG_ANDROID_BINDER_IPC) += binder_linux.o +binder_linux-$(CONFIG_ANDROID_BINDERFS) += binderfs.o +binder_linux-$(CONFIG_ANDROID_BINDER_ALLOC_KUNIT_TEST) += binder_alloc_selftest.o +binder_linux-$(CONFIG_ANDROID_BINDER_IPC_RUST) += binder/ diff --git a/drivers/android/binder.c b/drivers/android/binder.c index 8f2ef1bd539f18..38912216ae2255 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -7180,7 +7180,20 @@ static int __init binder_init(void) return ret; } -device_initcall(binder_init); +module_init(binder_init); +/* + * binder will have no exit function since binderfs instances can be mounted + * multiple times and also in user namespaces finding and destroying them all + * is not feasible without introducing insane locking. Just ignoring existing + * instances on module unload also wouldn't work since we would loose track of + * what major numer was dynamically allocated and also what minor numbers are + * already given out. So this would get us into all kinds of issues with device + * number reuse. So simply don't allow unloading unless we are forced to do so. + */ + +MODULE_AUTHOR("Google, Inc."); +MODULE_DESCRIPTION("Driver for Android binder device"); +MODULE_LICENSE("GPL v2"); #define CREATE_TRACE_POINTS #include "binder_trace.h" diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c index e4488ad86a6557..2675b4e4446dcd 100644 --- a/drivers/android/binder_alloc.c +++ b/drivers/android/binder_alloc.c @@ -39,8 +39,7 @@ enum { }; static uint32_t binder_alloc_debug_mask = BINDER_DEBUG_USER_ERROR; -module_param_named(debug_mask, binder_alloc_debug_mask, - uint, 0644); +module_param_named(alloc_debug_mask, binder_alloc_debug_mask, uint, 0644); #define binder_alloc_debug(mask, x...) \ do { \ diff --git a/drivers/android/binder_alloc.h b/drivers/android/binder_alloc.h index d6f1f6f2d00e7c..7edae3eb50f595 100644 --- a/drivers/android/binder_alloc.h +++ b/drivers/android/binder_alloc.h @@ -6,6 +6,7 @@ #ifndef _LINUX_BINDER_ALLOC_H #define _LINUX_BINDER_ALLOC_H +#include #include #include #include diff --git a/drivers/android/binder_internal.h b/drivers/android/binder_internal.h index 342574bfd28a88..a723f845bd6aca 100644 --- a/drivers/android/binder_internal.h +++ b/drivers/android/binder_internal.h @@ -4,6 +4,7 @@ #define _LINUX_BINDER_INTERNAL_H #include +#include #include #include #include @@ -76,7 +77,7 @@ extern const struct file_operations binder_fops; extern char *binder_devices_param; -#ifdef CONFIG_ANDROID_BINDERFS +#if IS_ENABLED(CONFIG_ANDROID_BINDERFS) extern bool is_binderfs_device(const struct inode *inode); extern struct dentry *binderfs_create_file(struct dentry *dir, const char *name, const struct file_operations *fops, @@ -95,7 +96,7 @@ static inline struct dentry *binderfs_create_file(struct dentry *dir, } #endif -#ifdef CONFIG_ANDROID_BINDERFS +#if IS_ENABLED(CONFIG_ANDROID_BINDERFS) extern int __init init_binderfs(void); #else static inline int __init init_binderfs(void) diff --git a/drivers/android/binderfs.c b/drivers/android/binderfs.c index 361d69f756f50e..e0de8a3a9091af 100644 --- a/drivers/android/binderfs.c +++ b/drivers/android/binderfs.c @@ -123,7 +123,7 @@ static int binderfs_binder_device_create(struct inode *ref_inode, struct super_block *sb = ref_inode->i_sb; struct binderfs_info *info = sb->s_fs_info; #if defined(CONFIG_IPC_NS) - bool use_reserve = (info->ipc_ns == &init_ipc_ns); + bool use_reserve = (info->ipc_ns == show_init_ipc_ns()); #else bool use_reserve = true; #endif @@ -391,7 +391,7 @@ static int binderfs_binder_ctl_create(struct super_block *sb) struct dentry *root = sb->s_root; struct binderfs_info *info = sb->s_fs_info; #if defined(CONFIG_IPC_NS) - bool use_reserve = (info->ipc_ns == &init_ipc_ns); + bool use_reserve = (info->ipc_ns == show_init_ipc_ns()); #else bool use_reserve = true; #endif @@ -643,7 +643,7 @@ static int binderfs_fill_super(struct super_block *sb, struct fs_context *fc) return -ENOMEM; info = sb->s_fs_info; - info->ipc_ns = get_ipc_ns(current->nsproxy->ipc_ns); + info->ipc_ns = get_ipc_ns_exported(current->nsproxy->ipc_ns); info->root_gid = make_kgid(sb->s_user_ns, 0); if (!gid_valid(info->root_gid)) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 70701d3bc81c6f..fa2567dab722e6 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -63,6 +63,9 @@ bool last_level_cache_is_valid(unsigned int cpu) if (!cache_leaves(cpu) || !per_cpu_cacheinfo(cpu)) return false; + if (!per_cpu_cacheinfo(cpu)) + return false; + llc = per_cpu_cacheinfo_idx(cpu, cache_leaves(cpu) - 1); return (llc->attributes & CACHE_ID) || !!llc->fw_token; diff --git a/drivers/base/platform.c b/drivers/base/platform.c index fb9120b0bcfe0e..a76338cef7017c 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -1426,9 +1426,11 @@ static int platform_probe(struct device *_dev) if (unlikely(drv->probe == platform_probe_fail)) return -ENXIO; - ret = of_clk_set_defaults(_dev->of_node, false); - if (ret < 0) - return ret; + if (!drv->driver_managed_clk_defaults) { + ret = of_clk_set_defaults(_dev->of_node, false); + if (ret < 0) + return ret; + } ret = dev_pm_domain_attach(_dev, PD_FLAG_ATTACH_POWER_ON | PD_FLAG_DETACH_POWER_OFF); diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c index 1f1c2810f6ee35..81ce9cd01da924 100644 --- a/drivers/block/rbd.c +++ b/drivers/block/rbd.c @@ -89,7 +89,7 @@ static int atomic_dec_return_safe(atomic_t *v) #define RBD_MINORS_PER_MAJOR 256 #define RBD_SINGLE_MAJOR_PART_SHIFT 4 -#define RBD_MAX_PARENT_CHAIN_LEN 16 +#define RBD_MAX_PARENT_CHAIN_LEN 128 #define RBD_SNAP_DEV_NAME_PREFIX "snap_" #define RBD_MAX_SNAP_NAME_LEN \ diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c index 184e95c1625e57..a5de6ccf915821 100644 --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -3045,6 +3046,35 @@ static int btusb_set_bdaddr_marvell(struct hci_dev *hdev, return 0; } +#define BTUSB_EDGE_LED_COMMAND 0xfc77 + +static void btusb_edge_set_led(struct hci_dev *hdev, bool state) +{ + struct sk_buff *skb; + u8 config_led[] = { 0x09, 0x00, 0x01, 0x01 }; + + if (state) + config_led[1] = 0x01; + + skb = __hci_cmd_sync(hdev, BTUSB_EDGE_LED_COMMAND, sizeof(config_led), config_led, HCI_INIT_TIMEOUT); + if (IS_ERR(skb)) + BT_ERR("%s fail to set LED (%ld)", hdev->name, PTR_ERR(skb)); + else + kfree_skb(skb); +} + +static int btusb_edge_post_init(struct hci_dev *hdev) +{ + btusb_edge_set_led(hdev, true); + return 0; +} + +static int btusb_edge_shutdown(struct hci_dev *hdev) +{ + btusb_edge_set_led(hdev, false); + return 0; +} + static int btusb_set_bdaddr_ath3012(struct hci_dev *hdev, const bdaddr_t *bdaddr) { @@ -4255,8 +4285,18 @@ static int btusb_probe(struct usb_interface *intf, btintel_set_flag(hdev, INTEL_BROKEN_SHUTDOWN_LED); } - if (id->driver_info & BTUSB_MARVELL) + if (id->driver_info & BTUSB_MARVELL) { + struct pci_dev *pdev; hdev->set_bdaddr = btusb_set_bdaddr_marvell; + pdev = pci_get_subsys(PCI_ANY_ID, PCI_ANY_ID, 0x1028, 0x0720, NULL); + if (!pdev) + pdev = pci_get_subsys(PCI_ANY_ID, PCI_ANY_ID, 0x1028, 0x0733, NULL); + if (pdev) { + pci_dev_put(pdev); + hdev->post_init = btusb_edge_post_init; + hdev->shutdown = btusb_edge_shutdown; + } + } if (IS_ENABLED(CONFIG_BT_HCIBTUSB_MTK) && (id->driver_info & BTUSB_MEDIATEK)) { diff --git a/drivers/bluetooth/hci_qca.c b/drivers/bluetooth/hci_qca.c index 1222f97800f4a1..edc9e3f9cc71ee 100644 --- a/drivers/bluetooth/hci_qca.c +++ b/drivers/bluetooth/hci_qca.c @@ -1227,7 +1227,14 @@ static int qca_recv_event(struct hci_dev *hdev, struct sk_buff *skb) * vendor command). */ - if (hdr->evt == HCI_EV_VENDOR) + /* For the WCN6750/WCN6855/WCN7850, like the WCN3990, the + * vendor command for a baudrate change command isn't sent as + * synchronous HCI command, the controller sends the corresponding + * command complete event with the new baudrate. The event is + * received and properly decoded after changing the baudrate of + * the host port. It needs to be dropped. + */ + if (hdr->evt == HCI_EV_VENDOR || hdr->evt == HCI_EV_CMD_COMPLETE) complete(&qca->drop_ev_comp); kfree_skb(skb); @@ -1522,6 +1529,9 @@ static int qca_set_speed(struct hci_uart *hu, enum qca_speed_type speed_type) switch (soc_type) { case QCA_WCN3990: + case QCA_WCN6750: + case QCA_WCN6855: + case QCA_WCN7850: reinit_completion(&qca->drop_ev_comp); set_bit(QCA_DROP_VENDOR_EVENT, &qca->flags); break; @@ -1557,6 +1567,9 @@ static int qca_set_speed(struct hci_uart *hu, enum qca_speed_type speed_type) switch (soc_type) { case QCA_WCN3990: + case QCA_WCN6750: + case QCA_WCN6855: + case QCA_WCN7850: /* Wait for the controller to send the vendor event * for the baudrate change command. */ diff --git a/drivers/cdrom/cdrom.c b/drivers/cdrom/cdrom.c index 4f1fd389260f53..1e0d772ad7c016 100644 --- a/drivers/cdrom/cdrom.c +++ b/drivers/cdrom/cdrom.c @@ -282,7 +282,7 @@ static bool debug; /* default compatibility mode */ static bool autoclose=1; static bool autoeject; -static bool lockdoor = 1; +static bool lockdoor = 0; /* will we ever get to use this... sigh. */ static bool check_media_type; /* automatically restart mrw format */ diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 048adfa86a5d0f..ab3f8becda0c81 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1442,14 +1442,39 @@ static void clk_core_disable_unprepare(struct clk_core *core) clk_core_unprepare_lock(core); } -static void __init clk_unprepare_unused_subtree(struct clk_core *core) +/* + * Returns true if @core should be skipped during an unused-clock sweep for + * @dev. When @dev is NULL the sweep is the global late_initcall pass; when + * @dev is non-NULL the sweep is a per-device sync_state pass. + */ +static bool clk_core_skip_unused(struct clk_core *core, struct device *dev) +{ + /* + * At late_initcall, skip clocks that belong to a device — they will be + * handled at sync_state time. + */ + if (!dev && core->dev) + return true; + + /* When called from sync_state, only process clocks for this device. */ + if (dev && core->dev != dev) + return true; + + return false; +} + +static void clk_unprepare_unused_subtree(struct clk_core *core, + struct device *dev) { struct clk_core *child; lockdep_assert_held(&prepare_lock); hlist_for_each_entry(child, &core->children, child_node) - clk_unprepare_unused_subtree(child); + clk_unprepare_unused_subtree(child, dev); + + if (clk_core_skip_unused(core, dev)) + return; if (core->prepare_count) return; @@ -1467,7 +1492,8 @@ static void __init clk_unprepare_unused_subtree(struct clk_core *core) } } -static void __init clk_disable_unused_subtree(struct clk_core *core) +static void clk_disable_unused_subtree(struct clk_core *core, + struct device *dev) { struct clk_core *child; unsigned long flags; @@ -1475,7 +1501,10 @@ static void __init clk_disable_unused_subtree(struct clk_core *core) lockdep_assert_held(&prepare_lock); hlist_for_each_entry(child, &core->children, child_node) - clk_disable_unused_subtree(child); + clk_disable_unused_subtree(child, dev); + + if (clk_core_skip_unused(core, dev)) + return; if (core->flags & CLK_OPS_PARENT_ENABLE) clk_core_prepare_enable(core->parent); @@ -1508,7 +1537,7 @@ static void __init clk_disable_unused_subtree(struct clk_core *core) clk_core_disable_unprepare(core->parent); } -static bool clk_ignore_unused __initdata; +static bool clk_ignore_unused; static int __init clk_ignore_unused_setup(char *__unused) { clk_ignore_unused = true; @@ -1516,7 +1545,7 @@ static int __init clk_ignore_unused_setup(char *__unused) } __setup("clk_ignore_unused", clk_ignore_unused_setup); -static int __init clk_disable_unused(void) +static int __clk_disable_unused(struct device *dev) { struct clk_core *core; int ret; @@ -1526,7 +1555,10 @@ static int __init clk_disable_unused(void) return 0; } - pr_info("clk: Disabling unused clocks\n"); + if (dev) + dev_info(dev, "clk: Disabling unused clocks\n"); + else + pr_info("clk: Disabling unused clocks not associated with a device\n"); ret = clk_pm_runtime_get_all(); if (ret) @@ -1538,16 +1570,16 @@ static int __init clk_disable_unused(void) clk_prepare_lock(); hlist_for_each_entry(core, &clk_root_list, child_node) - clk_disable_unused_subtree(core); + clk_disable_unused_subtree(core, dev); hlist_for_each_entry(core, &clk_orphan_list, child_node) - clk_disable_unused_subtree(core); + clk_disable_unused_subtree(core, dev); hlist_for_each_entry(core, &clk_root_list, child_node) - clk_unprepare_unused_subtree(core); + clk_unprepare_unused_subtree(core, dev); hlist_for_each_entry(core, &clk_orphan_list, child_node) - clk_unprepare_unused_subtree(core); + clk_unprepare_unused_subtree(core, dev); clk_prepare_unlock(); @@ -1555,8 +1587,19 @@ static int __init clk_disable_unused(void) return 0; } + +static int __init clk_disable_unused(void) +{ + return __clk_disable_unused(NULL); +} late_initcall_sync(clk_disable_unused); +void clk_sync_state(struct device *dev) +{ + __clk_disable_unused(dev); +} +EXPORT_SYMBOL_GPL(clk_sync_state); + static int clk_core_determine_round_nolock(struct clk_core *core, struct clk_rate_request *req) { @@ -4339,8 +4382,16 @@ __clk_register(struct device *dev, struct device_node *np, struct clk_hw *hw) core->dev = dev; clk_pm_runtime_init(core); core->of_node = np; - if (dev && dev->driver) + if (dev && dev->driver) { core->owner = dev->driver->owner; + + /* + * If a clk provider sets their own sync_state, then it needs to + * also call clk_sync_state(). dev_set_drv_sync_state() won't + * overwrite the sync_state callback. + */ + dev_set_drv_sync_state(dev, clk_sync_state); + } core->hw = hw; core->flags = init->flags; core->num_parents = init->num_parents; diff --git a/drivers/clk/qcom/apss-ipq5424.c b/drivers/clk/qcom/apss-ipq5424.c index 1662c83058bcb1..70991c3a9a58ea 100644 --- a/drivers/clk/qcom/apss-ipq5424.c +++ b/drivers/clk/qcom/apss-ipq5424.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -248,7 +247,7 @@ static struct platform_driver apss_ipq5424_driver = { .driver = { .name = "apss-ipq5424-clk", .of_match_table = apss_ipq5424_match_table, - .sync_state = icc_sync_state, + .sync_state = qcom_cc_sync_state, }, }; diff --git a/drivers/clk/qcom/clk-cbf-8996.c b/drivers/clk/qcom/clk-cbf-8996.c index 0b40ed601f9a52..6abc70ebf6f193 100644 --- a/drivers/clk/qcom/clk-cbf-8996.c +++ b/drivers/clk/qcom/clk-cbf-8996.c @@ -6,11 +6,11 @@ #include #include #include -#include #include #include #include #include +#include "common.h" #include @@ -249,7 +249,7 @@ static void qcom_msm8996_cbf_icc_remove(struct platform_device *pdev) icc_clk_unregister(provider); } -#define qcom_msm8996_cbf_icc_sync_state icc_sync_state +#define qcom_msm8996_cbf_icc_sync_state qcom_cc_sync_state #else static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct clk_hw *cbf_hw) { @@ -258,7 +258,7 @@ static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct c return 0; } #define qcom_msm8996_cbf_icc_remove(pdev) { } -#define qcom_msm8996_cbf_icc_sync_state NULL +#define qcom_msm8996_cbf_icc_sync_state clk_sync_state #endif static int qcom_msm8996_cbf_probe(struct platform_device *pdev) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index eec369d2173b5c..31382c49c948dc 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -3,12 +3,14 @@ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. */ +#include #include #include #include #include #include #include +#include #include #include #include @@ -464,5 +466,12 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index, } EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index); +void qcom_cc_sync_state(struct device *dev) +{ + icc_sync_state(dev); + clk_sync_state(dev); +} +EXPORT_SYMBOL_GPL(qcom_cc_sync_state); + MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("QTI Common Clock module"); diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 6f2406f8839e8f..ee448163b1fcc5 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -88,5 +88,6 @@ extern int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc); extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index, const struct qcom_cc_desc *desc); +extern void qcom_cc_sync_state(struct device *dev); #endif diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index ecd9ebeed7549c..37f717d51fb9bd 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -3306,7 +3307,7 @@ static struct platform_driver gcc_ipq5332_driver = { .driver = { .name = "gcc-ipq5332", .of_match_table = gcc_ipq5332_match_table, - .sync_state = icc_sync_state, + .sync_state = qcom_cc_sync_state, }, }; diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c index 35af6ffeeb8554..9bf3bb6f890431 100644 --- a/drivers/clk/qcom/gcc-ipq5424.c +++ b/drivers/clk/qcom/gcc-ipq5424.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -3322,7 +3321,7 @@ static struct platform_driver gcc_ipq5424_driver = { .driver = { .name = "qcom,gcc-ipq5424", .of_match_table = gcc_ipq5424_match_table, - .sync_state = icc_sync_state, + .sync_state = qcom_cc_sync_state, }, }; diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 6dc86e686de466..9edcfd8afb77f0 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include @@ -4134,7 +4133,7 @@ static struct platform_driver gcc_ipq9574_driver = { .driver = { .name = "qcom,gcc-ipq9574", .of_match_table = gcc_ipq9574_match_table, - .sync_state = icc_sync_state, + .sync_state = qcom_cc_sync_state, }, }; diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c index 8c146d62c07798..b0efdb4e3f9bed 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -5195,7 +5195,7 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { .halt_reg = 0x7702c, - .halt_check = BRANCH_HALT_DELAY, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x7702c, .enable_mask = BIT(0), @@ -5213,7 +5213,7 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { .halt_reg = 0x770cc, - .halt_check = BRANCH_HALT_DELAY, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x770cc, .enable_mask = BIT(0), @@ -5231,7 +5231,7 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { .halt_reg = 0x77028, - .halt_check = BRANCH_HALT_DELAY, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x77028, .enable_mask = BIT(0), diff --git a/drivers/clk/qcom/nsscc-ipq5424.c b/drivers/clk/qcom/nsscc-ipq5424.c index 5893c714618007..253d625ebf3568 100644 --- a/drivers/clk/qcom/nsscc-ipq5424.c +++ b/drivers/clk/qcom/nsscc-ipq5424.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -1331,7 +1330,7 @@ static struct platform_driver nss_cc_ipq5424_driver = { .name = "qcom,ipq5424-nsscc", .of_match_table = nss_cc_ipq5424_match_table, .pm = &nss_cc_ipq5424_pm_ops, - .sync_state = icc_sync_state, + .sync_state = qcom_cc_sync_state, }, }; module_platform_driver(nss_cc_ipq5424_driver); diff --git a/drivers/clk/qcom/nsscc-ipq9574.c b/drivers/clk/qcom/nsscc-ipq9574.c index c8b11b04a7c225..be8fbf5edda43c 100644 --- a/drivers/clk/qcom/nsscc-ipq9574.c +++ b/drivers/clk/qcom/nsscc-ipq9574.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -3100,7 +3099,7 @@ static struct platform_driver nss_cc_ipq9574_driver = { .name = "qcom,nsscc-ipq9574", .of_match_table = nss_cc_ipq9574_match_table, .pm = &nss_cc_ipq9574_pm_ops, - .sync_state = icc_sync_state, + .sync_state = qcom_cc_sync_state, }, }; diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index a5055a6273af62..ab216ed3b36ad5 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -14,14 +14,26 @@ #include #include #include +#include #include "../dmaengine.h" #include "../virt-dma.h" +static bool sp11_qspi_trace; +module_param_named(sp11_qspi_trace, sp11_qspi_trace, bool, 0644); +MODULE_PARM_DESC(sp11_qspi_trace, + "enable high-volume SP11 QSPI ring and event diagnostics"); + #define TRE_TYPE_DMA 0x10 #define TRE_TYPE_IMMEDIATE_DMA 0x11 #define TRE_TYPE_GO 0x20 #define TRE_TYPE_CONFIG0 0x22 +#define TRE_QSPI_GO_FLAG BIT(29) +#define TRE_QSPI_CONFIG0_DW0 0x03000004 +#define TRE_QSPI_CONFIG0_DW2 0x00010001 +#define TRE_QSPI_GO_TX_DW0 0x20000001 +#define TRE_QSPI_GO_BIDI_DW0 0x20000007 + /* TRE flags */ #define TRE_FLAGS_CHAIN BIT(0) #define TRE_FLAGS_IEOB BIT(8) @@ -214,6 +226,9 @@ enum CNTXT_OFFS { (FIELD_PREP(GPII_n_CH_k_SCRATCH_0_PAIR, pair) | \ FIELD_PREP(GPII_n_CH_k_SCRATCH_0_PROTO, proto) | \ FIELD_PREP(GPII_n_CH_k_SCRATCH_0_SEID, seid)) +#define GPII_n_CH_k_SCRATCH_0_QSPI_TX 0x16010092 +#define GPII_n_CH_k_SCRATCH_0_QSPI_RX 0x17000092 +#define GPII_n_CH_k_SCRATCH_2_QSPI 0x00000002 #define GPII_n_CH_k_SCRATCH_1_OFFS(n, k) (0x20064 + (0x4000 * (n)) + (0x80 * (k))) #define GPII_n_CH_k_SCRATCH_2_OFFS(n, k) (0x20068 + (0x4000 * (n)) + (0x80 * (k))) #define GPII_n_CH_k_SCRATCH_3_OFFS(n, k) (0x2006C + (0x4000 * (n)) + (0x80 * (k))) @@ -238,6 +253,25 @@ enum msm_gpi_tce_code { #define EV_FACTOR (2) #define REQ_OF_DMA_ARGS (5) /* # of arguments required from client */ #define CHAN_TRES 64 +#define SP11_WINDOWS_CHAN_TRES 16 +#define SP11_WINDOWS_EVENT_TRES 32 + +/* Exact qcspi/qcgpi ring geometry, isolated to the Windows-parity laboratory. */ +static bool sp11_windows_ring_layout; +module_param(sp11_windows_ring_layout, bool, 0444); +MODULE_PARM_DESC(sp11_windows_ring_layout, + "Use the captured Windows SP11 QSPI transfer/event ring sizes"); + +/* + * Phase 84 proved that removing LINK together with the Windows ring geometry + * leaves Linux's pre-doorbelled RX channel stalled at the first bidirectional + * transfer. Keep the captured geometry while allowing the one Linux channel- + * coupling adaptation to be selected independently. + */ +static bool sp11_qspi_linux_link; +module_param(sp11_qspi_linux_link, bool, 0444); +MODULE_PARM_DESC(sp11_qspi_linux_link, + "Add Linux-required LINK to a bidirectional SP11 QSPI GO"); struct __packed xfer_compl_event { u64 ptr; @@ -516,6 +550,15 @@ struct gpii { enum gpi_cmd gpi_cmd; u32 cntxt_type_irq_msk; bool ieob_set; + struct virt_dma_desc *qspi_deferred_vd; + struct gchan *qspi_deferred_gchan; + struct dmaengine_result qspi_deferred_result; + struct timer_list qspi_deferred_timer; + bool qspi_deferred_grace_elapsed; + u32 qspi_event_seq; + u32 qspi_code_count[MAX_CHANNELS_PER_GPII][17]; + u32 qspi_bytes[MAX_CHANNELS_PER_GPII]; + phys_addr_t qspi_last_ptr[MAX_CHANNELS_PER_GPII]; }; #define MAX_TRE 3 @@ -548,6 +591,75 @@ static inline struct gpi_desc *to_gpi_desc(struct virt_dma_desc *vd) return container_of(vd, struct gpi_desc, vd); } +static bool gpii_has_active_qspi(struct gpii *gpii) +{ + int i; + + for (i = 0; i < MAX_CHANNELS_PER_GPII; i++) + if (gpii->gchan[i].protocol == QCOM_GPI_QSPI && + gpii->gchan[i].pm_state == ACTIVE_STATE) + return true; + + return false; +} + +static const char *gpi_qspi_side_name(u32 chid) +{ + if (chid == GPI_TX_CHAN) + return "TX"; + if (chid == GPI_RX_CHAN) + return "RX"; + return "?"; +} + +static void gpi_qspi_reset_progress(struct gpii *gpii) +{ + memset(gpii->qspi_code_count, 0, sizeof(gpii->qspi_code_count)); + memset(gpii->qspi_bytes, 0, sizeof(gpii->qspi_bytes)); + memset(gpii->qspi_last_ptr, 0, sizeof(gpii->qspi_last_ptr)); + gpii->qspi_event_seq = 0; +} + +static void gpi_qspi_trace_progress(struct gchan *gchan, + struct xfer_compl_event *event, + const char *where) +{ + struct gpii *gpii = gchan->gpii; + struct gpi_ring *ring = &gchan->ch_ring; + phys_addr_t ring_base = ring->phys_addr; + phys_addr_t ring_end = ring->phys_addr + ring->len; + phys_addr_t ev_ptr = event->ptr; + u32 chid = event->chid; + u32 code = event->code; + u32 slot = U32_MAX; + + if (chid >= MAX_CHANNELS_PER_GPII) + chid = gchan->chid; + + if (code < ARRAY_SIZE(gpii->qspi_code_count[chid])) + gpii->qspi_code_count[chid][code]++; + gpii->qspi_bytes[chid] += event->length; + gpii->qspi_last_ptr[chid] = ev_ptr; + gpii->qspi_event_seq++; + + if (ev_ptr >= ring_base && ev_ptr < ring_end) + slot = div_u64(ev_ptr - ring_base, ring->el_size); + + dev_dbg_ratelimited(gpii->gpi_dev->dev, + "SP11 QSPI %s ev#%u side:%s chid:%u type:%02x code:%u len:%u ptr:%pa slot:%u ring:%pa-%pa tx[c2:%u c4:%u bytes:%u last:%pa] rx[c2:%u c4:%u bytes:%u last:%pa]\n", + where, gpii->qspi_event_seq, gpi_qspi_side_name(chid), + event->chid, event->type, event->code, event->length, + &ev_ptr, slot, &ring_base, &ring_end, + gpii->qspi_code_count[GPI_TX_CHAN][MSM_GPI_TCE_EOT], + gpii->qspi_code_count[GPI_TX_CHAN][MSM_GPI_TCE_EOB], + gpii->qspi_bytes[GPI_TX_CHAN], + &gpii->qspi_last_ptr[GPI_TX_CHAN], + gpii->qspi_code_count[GPI_RX_CHAN][MSM_GPI_TCE_EOT], + gpii->qspi_code_count[GPI_RX_CHAN][MSM_GPI_TCE_EOB], + gpii->qspi_bytes[GPI_RX_CHAN], + &gpii->qspi_last_ptr[GPI_RX_CHAN]); +} + static inline phys_addr_t to_physical(const struct gpi_ring *const ring, void *addr) { @@ -559,11 +671,108 @@ static inline void *to_virtual(const struct gpi_ring *const ring, phys_addr_t ad return ring->base + (addr - ring->phys_addr); } +static void gpi_qspi_complete_deferred(struct gpii *gpii, + struct qup_notif_event *notif) +{ + struct virt_dma_desc *vd = gpii->qspi_deferred_vd; + struct gchan *gchan = gpii->qspi_deferred_gchan; + struct gpi_desc *gpi_desc; + struct dmaengine_result result = gpii->qspi_deferred_result; + unsigned long flags; + + if (!vd || !gchan) + return; + + gpi_desc = to_gpi_desc(vd); + timer_delete(&gpii->qspi_deferred_timer); + gpii->qspi_deferred_vd = NULL; + gpii->qspi_deferred_gchan = NULL; + WRITE_ONCE(gpii->qspi_deferred_grace_elapsed, false); + + if (notif) + dev_dbg(gpii->gpi_dev->dev, + "SP11 QSPI completing deferred TX after QUP notification status:%#x count:%u residue:%u\n", + notif->status, notif->count, result.residue); + else + dev_dbg(gpii->gpi_dev->dev, + "SP11 QSPI completing TX-only descriptor after grace period residue:%u\n", + result.residue); + + dma_cookie_complete(&vd->tx); + dmaengine_desc_get_callback_invoke(&vd->tx, &result); + + spin_lock_irqsave(&gchan->vc.lock, flags); + list_del(&vd->node); + spin_unlock_irqrestore(&gchan->vc.lock, flags); + kfree(gpi_desc); +} + static inline u32 gpi_read_reg(struct gpii *gpii, void __iomem *addr) { return readl_relaxed(addr); } +static phys_addr_t gpi_read_ev_rp(struct gpii *gpii) +{ + u32 lsb = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); + u32 msb = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg + 4); + + return ((phys_addr_t)msb << 32) | lsb; +} + +static void gpi_sp11_dump_state(struct gpii *gpii, struct gchan *gchan, + const char *tag, u32 cmd) +{ + if (!READ_ONCE(sp11_qspi_trace)) + return; + + u32 id = gpii->gpii_id; + u32 chid = gchan ? gchan->chid : 0; + u32 ch0 = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_CNTXT_0_OFFS(id, 0)); + u32 ch1 = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_CNTXT_0_OFFS(id, 1)); + u32 ev0 = gpi_read_reg(gpii, gpii->regs + GPII_n_EV_CH_k_CNTXT_0_OFFS(id, 0)); + u32 type = gpi_read_reg(gpii, gpii->regs + GPII_n_CNTXT_TYPE_IRQ_OFFS(id)); + u32 type_msk = gpi_read_reg(gpii, gpii->regs + GPII_n_CNTXT_TYPE_IRQ_MSK_OFFS(id)); + u32 ch_irq = gpi_read_reg(gpii, gpii->regs + GPII_n_CNTXT_SRC_GPII_CH_IRQ_OFFS(id)); + u32 ch_irq_msk = gpi_read_reg(gpii, gpii->regs + GPII_n_CNTXT_SRC_CH_IRQ_MSK_OFFS(id)); + u32 ev_irq = gpi_read_reg(gpii, gpii->regs + GPII_n_CNTXT_SRC_EV_CH_IRQ_OFFS(id)); + u32 ev_irq_msk = gpi_read_reg(gpii, gpii->regs + GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(id)); + u32 glob = gpi_read_reg(gpii, gpii->regs + GPII_n_CNTXT_GLOB_IRQ_STTS_OFFS(id)); + u32 gpii_sts = gpi_read_reg(gpii, gpii->regs + GPII_n_CNTXT_GPII_IRQ_STTS_OFFS(id)); + u32 err = gpi_read_reg(gpii, gpii->regs + GPII_n_ERROR_LOG_OFFS(id)); + u32 tx_rp_l = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_CNTXT_0_OFFS(id, 0) + CNTXT_4_RING_RP_LSB); + u32 tx_rp_h = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_CNTXT_0_OFFS(id, 0) + CNTXT_5_RING_RP_MSB); + u32 tx_wp_l = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_CNTXT_0_OFFS(id, 0) + CNTXT_6_RING_WP_LSB); + u32 tx_wp_h = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_CNTXT_0_OFFS(id, 0) + CNTXT_7_RING_WP_MSB); + u32 rx_rp_l = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_CNTXT_0_OFFS(id, 1) + CNTXT_4_RING_RP_LSB); + u32 rx_rp_h = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_CNTXT_0_OFFS(id, 1) + CNTXT_5_RING_RP_MSB); + u32 rx_wp_l = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_CNTXT_0_OFFS(id, 1) + CNTXT_6_RING_WP_LSB); + u32 rx_wp_h = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_CNTXT_0_OFFS(id, 1) + CNTXT_7_RING_WP_MSB); + u32 tx_s0 = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_0_OFFS(id, 0)); + u32 tx_s1 = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_1_OFFS(id, 0)); + u32 tx_s2 = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_2_OFFS(id, 0)); + u32 tx_s3 = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_3_OFFS(id, 0)); + u32 rx_s0 = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_0_OFFS(id, 1)); + u32 rx_s1 = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_1_OFFS(id, 1)); + u32 rx_s2 = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_2_OFFS(id, 1)); + u32 rx_s3 = gpi_read_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_3_OFFS(id, 1)); + + dev_dbg(gpii->gpi_dev->dev, + "SP11 diag %s gpii:%u chid:%u irq:%d seid:%u proto:%u pm:%s cmd:0x%08x\n", + tag, id, chid, gpii->irq, gchan ? gchan->seid : 0, + gchan ? gchan->protocol : 0, TO_GPI_PM_STR(gpii->pm_state), cmd); + dev_dbg(gpii->gpi_dev->dev, + "SP11 diag gpii:%u ch0:0x%08x ch1:0x%08x ev0:0x%08x type:0x%08x type_msk:0x%08x glob:0x%08x gpii_sts:0x%08x ch_irq:0x%08x ch_msk:0x%08x ev_irq:0x%08x ev_msk:0x%08x err:0x%08x\n", + id, ch0, ch1, ev0, type, type_msk, glob, gpii_sts, + ch_irq, ch_irq_msk, ev_irq, ev_irq_msk, err); + dev_dbg(gpii->gpi_dev->dev, + "SP11 QSPI ctx tx_rp:%08x:%08x tx_wp:%08x:%08x rx_rp:%08x:%08x rx_wp:%08x:%08x scratch tx:%08x/%08x/%08x/%08x rx:%08x/%08x/%08x/%08x\n", + tx_rp_h, tx_rp_l, tx_wp_h, tx_wp_l, + rx_rp_h, rx_rp_l, rx_wp_h, rx_wp_l, + tx_s0, tx_s1, tx_s2, tx_s3, + rx_s0, rx_s1, rx_s2, rx_s3); +} + static inline void gpi_write_reg(struct gpii *gpii, void __iomem *addr, u32 val) { writel_relaxed(val, addr); @@ -695,8 +904,11 @@ static int gpi_send_cmd(struct gpii *gpii, struct gchan *gchan, timeout = wait_for_completion_timeout(&gpii->cmd_completion, msecs_to_jiffies(CMD_TIMEOUT_MS)); if (!timeout) { - dev_err(gpii->gpi_dev->dev, "cmd: %s completion timeout:%u\n", - TO_GPI_CMD_STR(gpi_cmd), chid); + dev_err(gpii->gpi_dev->dev, + "cmd: %s completion timeout:%u gpii:%u irq:%d cmd:0x%08x\n", + TO_GPI_CMD_STR(gpi_cmd), chid, gpii->gpii_id, + gpii->irq, cmd); + gpi_sp11_dump_state(gpii, gchan, TO_GPI_CMD_STR(gpi_cmd), cmd); return -EIO; } @@ -721,7 +933,15 @@ static inline void gpi_write_ch_db(struct gchan *gchan, phys_addr_t p_wp; p_wp = to_physical(ring, wp); - gpi_write_reg(gpii, gchan->ch_cntxt_db_reg, p_wp); + if (gchan->protocol == QCOM_GPI_QSPI) + dev_dbg(gpii->gpi_dev->dev, + "SP11 QSPI doorbell side:%s chid:%u wp:%pa hi:%08x lo:%08x\n", + gpi_qspi_side_name(gchan->chid), gchan->chid, &p_wp, + upper_32_bits(p_wp), lower_32_bits(p_wp)); + gpi_write_reg(gpii, gchan->ch_cntxt_db_reg + 4, upper_32_bits(p_wp)); + /* The high doorbell half must be visible before the low half commits it. */ + wmb(); + gpi_write_reg(gpii, gchan->ch_cntxt_db_reg, lower_32_bits(p_wp)); } /* program event ring DB register */ @@ -731,7 +951,10 @@ static inline void gpi_write_ev_db(struct gpii *gpii, phys_addr_t p_wp; p_wp = ring->phys_addr + (wp - ring->base); - gpi_write_reg(gpii, gpii->ev_cntxt_db_reg, p_wp); + gpi_write_reg(gpii, gpii->ev_cntxt_db_reg + 4, upper_32_bits(p_wp)); + /* The high doorbell half must be visible before the low half commits it. */ + wmb(); + gpi_write_reg(gpii, gpii->ev_cntxt_db_reg, lower_32_bits(p_wp)); } /* process transfer completion interrupt */ @@ -826,6 +1049,7 @@ static irqreturn_t gpi_handle_irq(int irq, void *data) u32 gpii_id = gpii->gpii_id; u32 type, offset; unsigned long flags; + bool qspi_drain_events = false; read_lock_irqsave(&gpii->pm_lock, flags); @@ -838,6 +1062,7 @@ static irqreturn_t gpi_handle_irq(int irq, void *data) TO_GPI_PM_STR(gpii->pm_state)); goto exit_irq; } + qspi_drain_events = gpii_has_active_qspi(gpii); offset = GPII_n_CNTXT_TYPE_IRQ_OFFS(gpii->gpii_id); type = gpi_read_reg(gpii, gpii->regs + offset); @@ -904,6 +1129,9 @@ static irqreturn_t gpi_handle_irq(int irq, void *data) type = gpi_read_reg(gpii, gpii->regs + offset); } while (type); + if (qspi_drain_events) + tasklet_hi_schedule(&gpii->ev_task); + exit_irq: read_unlock_irqrestore(&gpii->pm_lock, flags); @@ -1003,7 +1231,6 @@ static void gpi_process_xfer_compl_event(struct gchan *gchan, struct gpi_desc *gpi_desc; struct dmaengine_result result; unsigned long flags; - u32 chid; /* only process events on active channel */ if (unlikely(gchan->pm_state != ACTIVE_STATE)) { @@ -1018,6 +1245,21 @@ static void gpi_process_xfer_compl_event(struct gchan *gchan, struct gpi_ere *gpi_ere; spin_unlock_irqrestore(&gchan->vc.lock, flags); + /* + * QSPI can deliver a late duplicate EOT after the matching + * descriptor has already been retired by its QUP notification. + * There is no work left to complete, so this is expected ring + * housekeeping rather than a channel error. + */ + if (gchan->protocol == QCOM_GPI_QSPI && + compl_event->code == MSM_GPI_TCE_EOT) { + dev_dbg_ratelimited(gpii->gpi_dev->dev, + "discarding late QSPI EOT side:%s ptr:%pa len:%u\n", + gpi_qspi_side_name(gchan->chid), + &compl_event->ptr, + compl_event->length); + return; + } dev_err(gpii->gpi_dev->dev, "Event without a pending descriptor!\n"); gpi_ere = (struct gpi_ere *)compl_event; dev_err(gpii->gpi_dev->dev, @@ -1030,6 +1272,34 @@ static void gpi_process_xfer_compl_event(struct gchan *gchan, gpi_desc = to_gpi_desc(vd); spin_unlock_irqrestore(&gchan->vc.lock, flags); + if (gchan->protocol == QCOM_GPI_QSPI) + gpi_qspi_trace_progress(gchan, compl_event, "xfer"); + + /* + * TX-only QSPI produces a late duplicate EOT whose pointer is one TRE + * beyond the descriptor's DMA TRE. If the next descriptor has already + * been queued, that address aliases its first CONFIG TRE. Never attribute + * such an event to the new descriptor or advance its software ring RP. + */ + if (gchan->protocol == QCOM_GPI_QSPI && + compl_event->code == MSM_GPI_TCE_EOT) { + void *last_tre = gpi_desc->db; + phys_addr_t last_tre_phys; + + if (last_tre == ch_ring->base) + last_tre = ch_ring->base + ch_ring->len; + last_tre -= ch_ring->el_size; + last_tre_phys = to_physical(ch_ring, last_tre); + if (compl_event->ptr != last_tre_phys) { + dev_dbg_ratelimited(gpii->gpi_dev->dev, + "SP11 QSPI ignoring non-terminal EOT side:%s ptr:%pa expected:%pa len:%u pending_len:%zu\n", + gpi_qspi_side_name(gchan->chid), + &compl_event->ptr, &last_tre_phys, + compl_event->length, gpi_desc->len); + return; + } + } + /* * RP pointed by Event is to last TRE processed, * we need to update ring rp to ev_rp + 1 @@ -1042,12 +1312,19 @@ static void gpi_process_xfer_compl_event(struct gchan *gchan, /* update must be visible to other cores */ smp_wmb(); - chid = compl_event->chid; - if (compl_event->code == MSM_GPI_TCE_EOT && gpii->ieob_set) { - if (chid == GPI_RX_CHAN) - goto gpi_free_desc; - else - return; + if (gchan->protocol == QCOM_GPI_QSPI && + compl_event->code == MSM_GPI_TCE_EOB) { + gpii->ieob_set = true; + dev_dbg(gpii->gpi_dev->dev, + "QSPI EOB received before EOT, keeping descriptor pending\n"); + return; + } + + if (gchan->protocol == QCOM_GPI_QSPI && + compl_event->code == MSM_GPI_TCE_EOT && gpii->ieob_set) { + gpii->ieob_set = false; + dev_dbg(gpii->gpi_dev->dev, + "QSPI EOT after EOB, completing real channel descriptor\n"); } if (compl_event->code == MSM_GPI_TCE_UNEXP_ERR) { @@ -1057,13 +1334,40 @@ static void gpi_process_xfer_compl_event(struct gchan *gchan, dev_dbg(gpii->gpi_dev->dev, "Transaction Success\n"); result.result = DMA_TRANS_NOERROR; } - result.residue = gpi_desc->len - compl_event->length; + result.residue = compl_event->length < gpi_desc->len ? + gpi_desc->len - compl_event->length : 0; dev_dbg(gpii->gpi_dev->dev, "Residue %d\n", result.residue); + /* + * A QSPI TX data EOT precedes the matching QUP command-completion + * notification. Completing the DMA cookie here lets the SPI client ring + * the next command while the previous command is still retiring, which + * wedges both channels. The SP11 code already carries a single deferred + * descriptor slot; populate it and let QUP_NOTIF_EV_TYPE retire it. + */ + if (gchan->protocol == QCOM_GPI_QSPI && + gchan->chid == GPI_TX_CHAN && + compl_event->code == MSM_GPI_TCE_EOT) { + if (gpii->qspi_deferred_vd) { + dev_warn(gpii->gpi_dev->dev, + "SP11 QSPI ignoring duplicate TX EOT while completion is deferred\n"); + return; + } + + gpii->qspi_deferred_vd = vd; + gpii->qspi_deferred_gchan = gchan; + gpii->qspi_deferred_result = result; + WRITE_ONCE(gpii->qspi_deferred_grace_elapsed, false); + mod_timer(&gpii->qspi_deferred_timer, jiffies + 1); + dev_dbg(gpii->gpi_dev->dev, + "SP11 QSPI deferring TX EOT until QUP notification residue:%u\n", + result.residue); + return; + } + dma_cookie_complete(&vd->tx); dmaengine_desc_get_callback_invoke(&vd->tx, &result); -gpi_free_desc: spin_lock_irqsave(&gchan->vc.lock, flags); list_del(&vd->node); spin_unlock_irqrestore(&gchan->vc.lock, flags); @@ -1081,8 +1385,20 @@ static void gpi_process_events(struct gpii *gpii) struct gchan *gchan; u32 chid, type; - cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); + cntxt_rp = gpi_read_ev_rp(gpii); rp = to_virtual(ev_ring, cntxt_rp); + if (gpii_has_active_qspi(gpii)) { + union gpi_event *raw = ev_ring->rp; + + dev_dbg_ratelimited(gpii->gpi_dev->dev, + "SP11 QSPI EV scan phys:%pa sw_rp:%pa sw_wp:%pa hw_rp:%pa raw:%08x:%08x:%08x:%08x\n", + &ev_ring->phys_addr, + &(phys_addr_t){ to_physical(ev_ring, ev_ring->rp) }, + &(phys_addr_t){ to_physical(ev_ring, ev_ring->wp) }, + &cntxt_rp, + raw->gpi_ere.dword[0], raw->gpi_ere.dword[1], + raw->gpi_ere.dword[2], raw->gpi_ere.dword[3]); + } do { while (rp != ev_ring->rp) { @@ -1095,6 +1411,24 @@ static void gpi_process_events(struct gpii *gpii) chid, type, gpi_event->gpi_ere.dword[0], gpi_event->gpi_ere.dword[1], gpi_event->gpi_ere.dword[2], gpi_event->gpi_ere.dword[3]); + if (gpii_has_active_qspi(gpii)) { + dev_dbg(gpii->gpi_dev->dev, + "SP11 QSPI event chid:%u type:%02x code:%u len:%u ptr:%pa\n", + chid, type, gpi_event->xfer_compl_event.code, + gpi_event->xfer_compl_event.length, + &(phys_addr_t){ + gpi_event->xfer_compl_event.ptr }); + dev_dbg(gpii->gpi_dev->dev, + "SP11 QSPI raw %08x:%08x:%08x:%08x\n", + gpi_event->gpi_ere.dword[0], + gpi_event->gpi_ere.dword[1], + gpi_event->gpi_ere.dword[2], + gpi_event->gpi_ere.dword[3]); + gpi_sp11_dump_state(gpii, + chid < MAX_CHANNELS_PER_GPII ? + &gpii->gchan[chid] : NULL, + "event", 0); + } switch (type) { case XFER_COMPLETE_EV_TYPE: @@ -1111,7 +1445,23 @@ static void gpi_process_events(struct gpii *gpii) &gpi_event->immediate_data_event); break; case QUP_NOTIF_EV_TYPE: - dev_dbg(gpii->gpi_dev->dev, "QUP_NOTIF_EV_TYPE\n"); + if (gpii_has_active_qspi(gpii)) { + dev_dbg(gpii->gpi_dev->dev, + "SP11 QSPI QUP notif status:%#x time:%#x count:%u chid:%u raw:%08x:%08x:%08x:%08x\n", + gpi_event->qup_notif_event.status, + gpi_event->qup_notif_event.time, + gpi_event->qup_notif_event.count, + gpi_event->qup_notif_event.chid, + gpi_event->gpi_ere.dword[0], + gpi_event->gpi_ere.dword[1], + gpi_event->gpi_ere.dword[2], + gpi_event->gpi_ere.dword[3]); + gpi_sp11_dump_state(gpii, NULL, "qup-notif", 0); + gpi_qspi_complete_deferred(gpii, + &gpi_event->qup_notif_event); + } else { + dev_dbg(gpii->gpi_dev->dev, "QUP_NOTIF_EV_TYPE\n"); + } break; default: dev_dbg(gpii->gpi_dev->dev, @@ -1124,7 +1474,7 @@ static void gpi_process_events(struct gpii *gpii) /* clear pending IEOB events */ gpi_write_reg(gpii, gpii->ieob_clr_reg, BIT(0)); - cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); + cntxt_rp = gpi_read_ev_rp(gpii); rp = to_virtual(ev_ring, cntxt_rp); } while (rp != ev_ring->rp); @@ -1145,24 +1495,40 @@ static void gpi_ev_tasklet(unsigned long data) /* process the events */ gpi_process_events(gpii); + if (READ_ONCE(gpii->qspi_deferred_grace_elapsed) && + READ_ONCE(gpii->qspi_deferred_vd)) + gpi_qspi_complete_deferred(gpii, NULL); /* enable IEOB, switching back to interrupts */ gpi_config_interrupts(gpii, MASK_IEOB_SETTINGS, 1); read_unlock(&gpii->pm_lock); } +static void gpi_qspi_deferred_timer(struct timer_list *timer) +{ + struct gpii *gpii = timer_container_of(gpii, timer, + qspi_deferred_timer); + + if (READ_ONCE(gpii->qspi_deferred_vd)) { + WRITE_ONCE(gpii->qspi_deferred_grace_elapsed, true); + dev_dbg(gpii->gpi_dev->dev, + "SP11 QSPI grace period elapsed; rescheduling deferred TX\n"); + tasklet_schedule(&gpii->ev_task); + } +} + /* marks all pending events for the channel as stale */ static void gpi_mark_stale_events(struct gchan *gchan) { struct gpii *gpii = gchan->gpii; struct gpi_ring *ev_ring = &gpii->ev_ring; - u32 cntxt_rp, local_rp; + phys_addr_t cntxt_rp, local_rp; void *ev_rp; - cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); + cntxt_rp = gpi_read_ev_rp(gpii); ev_rp = ev_ring->rp; - local_rp = (u32)to_physical(ev_ring, ev_rp); + local_rp = to_physical(ev_ring, ev_rp); while (local_rp != cntxt_rp) { union gpi_event *gpi_event = ev_rp; u32 chid = gpi_event->xfer_compl_event.chid; @@ -1172,8 +1538,8 @@ static void gpi_mark_stale_events(struct gchan *gchan) ev_rp += ev_ring->el_size; if (ev_rp >= (ev_ring->base + ev_ring->len)) ev_rp = ev_ring->base; - cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); - local_rp = (u32)to_physical(ev_ring, ev_rp); + cntxt_rp = gpi_read_ev_rp(gpii); + local_rp = to_physical(ev_ring, ev_rp); } } @@ -1275,10 +1641,22 @@ static int gpi_alloc_chan(struct gchan *chan, bool send_alloc_cmd) upper_32_bits(ring->phys_addr)); gpi_write_reg(gpii, chan->ch_cntxt_db_reg + CNTXT_5_RING_RP_MSB - CNTXT_4_RING_RP_LSB, upper_32_bits(ring->phys_addr)); - gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_0_OFFS(id, chid), - GPII_n_CH_k_SCRATCH_0(pair_chid, chan->protocol, chan->seid)); - gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_1_OFFS(id, chid), 0); - gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_2_OFFS(id, chid), 0); + if (chan->protocol == QCOM_GPI_QSPI) { + u32 scratch0 = chid == GPI_TX_CHAN ? + GPII_n_CH_k_SCRATCH_0_QSPI_TX : + GPII_n_CH_k_SCRATCH_0_QSPI_RX; + + gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_0_OFFS(id, chid), + scratch0); + gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_1_OFFS(id, chid), 0); + gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_2_OFFS(id, chid), + GPII_n_CH_k_SCRATCH_2_QSPI); + } else { + gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_0_OFFS(id, chid), + GPII_n_CH_k_SCRATCH_0(pair_chid, chan->protocol, chan->seid)); + gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_1_OFFS(id, chid), 0); + gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_2_OFFS(id, chid), 0); + } gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_3_OFFS(id, chid), 0); gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_QOS_OFFS(id, chid), 1); @@ -1454,6 +1832,20 @@ static void gpi_queue_xfer(struct gpii *gpii, struct gchan *gchan, *wp = ch_tre; } +static void gpi_qspi_clear_deferred(struct gpii *gpii) +{ + if (!gpii->qspi_deferred_vd) + return; + timer_delete_sync(&gpii->qspi_deferred_timer); + + dev_warn(gpii->gpi_dev->dev, + "SP11 QSPI clearing stale deferred TX completion on terminate/reset\n"); + + gpii->qspi_deferred_vd = NULL; + gpii->qspi_deferred_gchan = NULL; + WRITE_ONCE(gpii->qspi_deferred_grace_elapsed, false); +} + /* reset and restart transfer channel */ static int gpi_terminate_all(struct dma_chan *chan) { @@ -1464,6 +1856,9 @@ static int gpi_terminate_all(struct dma_chan *chan) mutex_lock(&gpii->ctrl_lock); + if (gchan->protocol == QCOM_GPI_QSPI) + gpi_qspi_clear_deferred(gpii); + /* * treat both channels as a group if its protocol is not UART * STOP, RESET, or START needs to be in lockstep @@ -1715,44 +2110,83 @@ static int gpi_create_spi_tre(struct gchan *chan, struct gpi_desc *desc, tre = &desc->tre[tre_idx]; tre_idx++; - tre->dword[0] = u32_encode_bits(spi->word_len, TRE_SPI_C0_WORD_SZ); - tre->dword[0] |= u32_encode_bits(spi->loopback_en, TRE_SPI_C0_LOOPBACK); - tre->dword[0] |= u32_encode_bits(spi->clock_pol_high, TRE_SPI_C0_CPOL); - tre->dword[0] |= u32_encode_bits(spi->data_pol_high, TRE_SPI_C0_CPHA); - tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_TX_PACK); - tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_RX_PACK); + if (spi->qspi) { + tre->dword[0] = TRE_QSPI_CONFIG0_DW0; + } else { + tre->dword[0] = u32_encode_bits(spi->word_len, TRE_SPI_C0_WORD_SZ); + tre->dword[0] |= u32_encode_bits(spi->loopback_en, TRE_SPI_C0_LOOPBACK); + tre->dword[0] |= u32_encode_bits(spi->clock_pol_high, TRE_SPI_C0_CPOL); + tre->dword[0] |= u32_encode_bits(spi->data_pol_high, TRE_SPI_C0_CPHA); + tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_TX_PACK); + tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_RX_PACK); + } tre->dword[1] = 0; - tre->dword[2] = u32_encode_bits(spi->clk_div, TRE_C0_CLK_DIV); - tre->dword[2] |= u32_encode_bits(spi->clk_src, TRE_C0_CLK_SRC); + if (spi->qspi) { + tre->dword[2] = TRE_QSPI_CONFIG0_DW2; + } else { + tre->dword[2] = u32_encode_bits(spi->clk_div, TRE_C0_CLK_DIV); + tre->dword[2] |= u32_encode_bits(spi->clk_src, TRE_C0_CLK_SRC); + } tre->dword[3] = u32_encode_bits(TRE_TYPE_CONFIG0, TRE_FLAGS_TYPE); tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); + if (spi->qspi) + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB); } - /* create the GO tre for Tx */ + /* + * SP11 QSPI Windows ring captures show TX uses CONFIG0/GO/DMA, while + * RX ring entries are DMA-only. Do not synthesize a GO TRE on RX. + */ if (direction == DMA_MEM_TO_DEV) { tre = &desc->tre[tre_idx]; tre_idx++; - tre->dword[0] = u32_encode_bits(spi->fragmentation, TRE_SPI_GO_FRAG); - tre->dword[0] |= u32_encode_bits(spi->cs, TRE_SPI_GO_CS); - tre->dword[0] |= u32_encode_bits(spi->cmd, TRE_SPI_GO_CMD); + if (spi->qspi) { + /* + * qcspi8380 emits raw QGPI command 1 for QSPI TX-only and + * command 7 when TX and RX both participate. Command 5 was + * an incorrect interpretation of the Windows builder and is + * rejected before the TX DMA TRE is consumed. + */ + tre->dword[0] = spi->rx_len ? TRE_QSPI_GO_BIDI_DW0 : + TRE_QSPI_GO_TX_DW0; + } else { + tre->dword[0] = u32_encode_bits(spi->fragmentation, TRE_SPI_GO_FRAG); + tre->dword[0] |= u32_encode_bits(spi->cs, TRE_SPI_GO_CS); + tre->dword[0] |= u32_encode_bits(spi->cmd, TRE_SPI_GO_CMD); + } tre->dword[1] = 0; + /* qcspi8380 places only the receive length in QSPI GO dword 2. */ tre->dword[2] = u32_encode_bits(spi->rx_len, TRE_RX_LEN); tre->dword[3] = u32_encode_bits(TRE_TYPE_GO, TRE_FLAGS_TYPE); - if (spi->cmd == SPI_RX) { + if (spi->qspi) { + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB); + /* + * Windows QGPI couples its channel contexts implicitly. The + * Linux GPI context needs LINK on a bidirectional QSPI GO or + * the pre-doorbelled RX ring never advances. + */ + if (spi->rx_len && + (!sp11_windows_ring_layout || sp11_qspi_linux_link)) + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK); + } else if (spi->cmd == SPI_RX) { tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB); tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK); } else if (spi->cmd == SPI_TX) { tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); } else { /* SPI_DUPLEX */ tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); - tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK); + if (!spi->rx_len) + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK); + else + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB); } } @@ -1764,7 +2198,7 @@ static int gpi_create_spi_tre(struct gchan *chan, struct gpi_desc *desc, len = sg_dma_len(sgl); /* Support Immediate dma for write transfers for data length up to 8 bytes */ - if (direction == DMA_MEM_TO_DEV && len <= 2 * sizeof(tre->dword[0])) { + if (!spi->qspi && direction == DMA_MEM_TO_DEV && len <= 2 * sizeof(tre->dword[0])) { /* * For Immediate dma, data length may not always be length of 8 bytes, * it can be length less than 8, hence initialize both dword's with 0 @@ -1783,12 +2217,20 @@ static int gpi_create_spi_tre(struct gchan *chan, struct gpi_desc *desc, tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); } - tre->dword[3] |= u32_encode_bits(direction == DMA_MEM_TO_DEV, + tre->dword[3] |= u32_encode_bits(spi->qspi || direction == DMA_MEM_TO_DEV, TRE_FLAGS_IEOT); for (i = 0; i < tre_idx; i++) - dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0], - desc->tre[i].dword[1], desc->tre[i].dword[2], desc->tre[i].dword[3]); + if (spi->qspi) + dev_dbg_ratelimited(dev, "SP11 QSPI TRE:%d %08x:%08x:%08x:%08x\n", + i, desc->tre[i].dword[0], + desc->tre[i].dword[1], + desc->tre[i].dword[2], + desc->tre[i].dword[3]); + else + dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0], + desc->tre[i].dword[1], desc->tre[i].dword[2], + desc->tre[i].dword[3]); return tre_idx; } @@ -1841,7 +2283,7 @@ gpi_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, return NULL; /* create TREs for xfer */ - if (gchan->protocol == QCOM_GPI_SPI) { + if (gchan->protocol == QCOM_GPI_SPI || gchan->protocol == QCOM_GPI_QSPI) { i = gpi_create_spi_tre(gchan, gpi_desc, sgl, direction); } else if (gchan->protocol == QCOM_GPI_I2C) { i = gpi_create_i2c_tre(gchan, gpi_desc, sgl, direction, flags); @@ -1887,13 +2329,37 @@ static void gpi_issue_pending(struct dma_chan *chan) } gpi_desc = to_gpi_desc(vd); + + if (gchan->protocol == QCOM_GPI_QSPI && gchan->chid == GPI_RX_CHAN) + gpi_qspi_reset_progress(gpii); + for (i = 0; i < gpi_desc->num_tre; i++) { + phys_addr_t tre_phys; + tre = &gpi_desc->tre[i]; gpi_queue_xfer(gpii, gchan, tre, &wp); + if (gchan->protocol == QCOM_GPI_QSPI && wp) { + tre_phys = to_physical(ch_ring, wp); + dev_dbg_ratelimited(gpii->gpi_dev->dev, + "SP11 QSPI submit side:%s chid:%u tre:%d/%u phys:%pa ring_base:%pa rp:%pa wp:%pa d:%08x:%08x:%08x:%08x\n", + gpi_qspi_side_name(gchan->chid), + gchan->chid, i, gpi_desc->num_tre, + &tre_phys, &ch_ring->phys_addr, + &(phys_addr_t){ to_physical(ch_ring, ch_ring->rp) }, + &(phys_addr_t){ to_physical(ch_ring, ch_ring->wp) }, + gpi_desc->tre[i].dword[0], + gpi_desc->tre[i].dword[1], + gpi_desc->tre[i].dword[2], + gpi_desc->tre[i].dword[3]); + } } gpi_desc->db = ch_ring->wp; + if (gchan->protocol == QCOM_GPI_QSPI) + gpi_sp11_dump_state(gpii, gchan, "qspi-before-db", 0); gpi_write_ch_db(gchan, &gchan->ch_ring, gpi_desc->db); + if (gchan->protocol == QCOM_GPI_QSPI) + gpi_sp11_dump_state(gpii, gchan, "qspi-after-db", 0); read_unlock_irqrestore(&gpii->pm_lock, pm_lock_flags); } @@ -1920,7 +2386,11 @@ static int gpi_ch_init(struct gchan *gchan) } /* allocate memory for event ring */ - elements = CHAN_TRES << ev_factor; + if (sp11_windows_ring_layout && + gpii->gchan[0].protocol == QCOM_GPI_QSPI) + elements = SP11_WINDOWS_EVENT_TRES; + else + elements = CHAN_TRES << ev_factor; ret = gpi_alloc_ring(&gpii->ev_ring, elements, sizeof(union gpi_event), gpii); if (ret) @@ -2028,6 +2498,7 @@ static void gpi_free_chan_resources(struct dma_chan *chan) write_unlock_irq(&gpii->pm_lock); /* wait for threads to complete out */ + timer_delete_sync(&gpii->qspi_deferred_timer); tasklet_kill(&gpii->ev_task); /* send command to de allocate event ring */ @@ -2054,12 +2525,15 @@ static int gpi_alloc_chan_resources(struct dma_chan *chan) { struct gchan *gchan = to_gchan(chan); struct gpii *gpii = gchan->gpii; + u32 elements = CHAN_TRES; int ret; mutex_lock(&gpii->ctrl_lock); /* allocate memory for transfer ring */ - ret = gpi_alloc_ring(&gchan->ch_ring, CHAN_TRES, + if (sp11_windows_ring_layout && gchan->protocol == QCOM_GPI_QSPI) + elements = SP11_WINDOWS_CHAN_TRES; + ret = gpi_alloc_ring(&gchan->ch_ring, elements, sizeof(struct gpi_tre), gpii); if (ret) goto xfer_alloc_err; @@ -2155,6 +2629,9 @@ static struct dma_chan *gpi_of_dma_xlate(struct of_phandle_args *args, gchan->seid = seid; gchan->protocol = args->args[2]; + dev_dbg(gpi_dev->dev, "SP11 diag xlate chid:%u seid:%u proto:%u -> gpii:%d\n", + chid, seid, gchan->protocol, gpii); + return dma_get_slave_channel(&gchan->vc.chan); } @@ -2194,6 +2671,11 @@ static int gpi_probe(struct platform_device *pdev) gpi_dev->ev_factor = EV_FACTOR; + dev_dbg(gpi_dev->dev, + "SP11 diag probe max_gpii:%u mask:0x%x ee_offset:0x%x coherent:%d\n", + gpi_dev->max_gpii, gpi_dev->gpii_mask, ee_offset, + device_get_dma_attr(gpi_dev->dev) == DEV_DMA_COHERENT); + ret = dma_set_mask(gpi_dev->dev, DMA_BIT_MASK(64)); if (ret) { dev_err(gpi_dev->dev, "Error setting dma_mask to 64, ret:%d\n", ret); @@ -2227,6 +2709,9 @@ static int gpi_probe(struct platform_device *pdev) return ret; gpii->irq = ret; + dev_dbg(gpi_dev->dev, "SP11 diag setup gpii:%u irq:%d\n", + i, gpii->irq); + /* set up channel specific register info */ for (chan = 0; chan < MAX_CHANNELS_PER_GPII; chan++) { struct gchan *gchan = &gpii->gchan[chan]; @@ -2249,6 +2734,8 @@ static int gpi_probe(struct platform_device *pdev) rwlock_init(&gpii->pm_lock); tasklet_init(&gpii->ev_task, gpi_ev_tasklet, (unsigned long)gpii); + timer_setup(&gpii->qspi_deferred_timer, + gpi_qspi_deferred_timer, 0); init_completion(&gpii->cmd_completion); gpii->gpii_id = i; gpii->regs = gpi_dev->ee_base; @@ -2260,7 +2747,6 @@ static int gpi_probe(struct platform_device *pdev) /* clear and Set capabilities */ dma_cap_zero(gpi_dev->dma_device.cap_mask); dma_cap_set(DMA_SLAVE, gpi_dev->dma_device.cap_mask); - dma_cap_set(DMA_PRIVATE, gpi_dev->dma_device.cap_mask); /* configure dmaengine apis */ gpi_dev->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); diff --git a/drivers/firmware/efi/Makefile b/drivers/firmware/efi/Makefile index 8efbcf699e4ff9..96d5a1ca981df8 100644 --- a/drivers/firmware/efi/Makefile +++ b/drivers/firmware/efi/Makefile @@ -25,6 +25,7 @@ subdir-$(CONFIG_EFI_STUB) += libstub obj-$(CONFIG_EFI_BOOTLOADER_CONTROL) += efibc.o obj-$(CONFIG_EFI_TEST) += test/ obj-$(CONFIG_EFI_DEV_PATH_PARSER) += dev-path-parser.o +obj-$(CONFIG_EFI) += secureboot.o obj-$(CONFIG_APPLE_PROPERTIES) += apple-properties.o obj-$(CONFIG_EFI_RCI2_TABLE) += rci2-table.o obj-$(CONFIG_EFI_EMBEDDED_FIRMWARE) += embedded-firmware.o diff --git a/drivers/firmware/efi/efi-init.c b/drivers/firmware/efi/efi-init.c index 6103b1a082d247..c203c9f3bc46b1 100644 --- a/drivers/firmware/efi/efi-init.c +++ b/drivers/firmware/efi/efi-init.c @@ -20,6 +20,7 @@ #include #include #include +#include #include @@ -258,6 +259,13 @@ void __init efi_init(void) return; } + efi_set_secure_boot(efi_get__secure_boot()); + +#ifdef CONFIG_LOCK_DOWN_IN_SECURE_BOOT + if (efi_enabled(EFI_SECURE_BOOT)) + security_lock_kernel_down("EFI Secure Boot mode", LOCKDOWN_INTEGRITY_MAX); +#endif + reserve_regions(); /* * For memblock manipulation, the cap should come after the memblock_add(). diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c index 0327a39d31fa5d..5b5332b4de7824 100644 --- a/drivers/firmware/efi/efi.c +++ b/drivers/firmware/efi/efi.c @@ -33,6 +33,7 @@ #include #include #include +#include #include @@ -1017,40 +1018,101 @@ int efi_mem_type(unsigned long phys_addr) return md.type; } +struct efi_error_code { + efi_status_t status; + int errno; + const char *description; +}; + +static const struct efi_error_code efi_error_codes[] = { + { EFI_SUCCESS, 0, "Success"}, +#if 0 + { EFI_LOAD_ERROR, -EPICK_AN_ERRNO, "Load Error"}, +#endif + { EFI_INVALID_PARAMETER, -EINVAL, "Invalid Parameter"}, + { EFI_UNSUPPORTED, -ENOSYS, "Unsupported"}, + { EFI_BAD_BUFFER_SIZE, -ENOSPC, "Bad Buffer Size"}, + { EFI_BUFFER_TOO_SMALL, -ENOSPC, "Buffer Too Small"}, + { EFI_NOT_READY, -EAGAIN, "Not Ready"}, + { EFI_DEVICE_ERROR, -EIO, "Device Error"}, + { EFI_WRITE_PROTECTED, -EROFS, "Write Protected"}, + { EFI_OUT_OF_RESOURCES, -ENOMEM, "Out of Resources"}, +#if 0 + { EFI_VOLUME_CORRUPTED, -EPICK_AN_ERRNO, "Volume Corrupt"}, + { EFI_VOLUME_FULL, -EPICK_AN_ERRNO, "Volume Full"}, + { EFI_NO_MEDIA, -EPICK_AN_ERRNO, "No Media"}, + { EFI_MEDIA_CHANGED, -EPICK_AN_ERRNO, "Media changed"}, +#endif + { EFI_NOT_FOUND, -ENOENT, "Not Found"}, +#if 0 + { EFI_ACCESS_DENIED, -EPICK_AN_ERRNO, "Access Denied"}, + { EFI_NO_RESPONSE, -EPICK_AN_ERRNO, "No Response"}, + { EFI_NO_MAPPING, -EPICK_AN_ERRNO, "No mapping"}, + { EFI_TIMEOUT, -EPICK_AN_ERRNO, "Time out"}, + { EFI_NOT_STARTED, -EPICK_AN_ERRNO, "Not started"}, + { EFI_ALREADY_STARTED, -EPICK_AN_ERRNO, "Already started"}, +#endif + { EFI_ABORTED, -EINTR, "Aborted"}, +#if 0 + { EFI_ICMP_ERROR, -EPICK_AN_ERRNO, "ICMP Error"}, + { EFI_TFTP_ERROR, -EPICK_AN_ERRNO, "TFTP Error"}, + { EFI_PROTOCOL_ERROR, -EPICK_AN_ERRNO, "Protocol Error"}, + { EFI_INCOMPATIBLE_VERSION, -EPICK_AN_ERRNO, "Incompatible Version"}, +#endif + { EFI_SECURITY_VIOLATION, -EACCES, "Security Policy Violation"}, +#if 0 + { EFI_CRC_ERROR, -EPICK_AN_ERRNO, "CRC Error"}, + { EFI_END_OF_MEDIA, -EPICK_AN_ERRNO, "End of Media"}, + { EFI_END_OF_FILE, -EPICK_AN_ERRNO, "End of File"}, + { EFI_INVALID_LANGUAGE, -EPICK_AN_ERRNO, "Invalid Languages"}, + { EFI_COMPROMISED_DATA, -EPICK_AN_ERRNO, "Compromised Data"}, + + // warnings + { EFI_WARN_UNKOWN_GLYPH, -EPICK_AN_ERRNO, "Warning Unknown Glyph"}, + { EFI_WARN_DELETE_FAILURE, -EPICK_AN_ERRNO, "Warning Delete Failure"}, + { EFI_WARN_WRITE_FAILURE, -EPICK_AN_ERRNO, "Warning Write Failure"}, + { EFI_WARN_BUFFER_TOO_SMALL, -EPICK_AN_ERRNO, "Warning Buffer Too Small"}, +#endif +}; + +static int +efi_status_cmp_bsearch(const void *key, const void *item) +{ + u64 status = (u64)(uintptr_t)key; + struct efi_error_code *code = (struct efi_error_code *)item; + + if (status < code->status) + return -1; + if (status > code->status) + return 1; + return 0; +} + int efi_status_to_err(efi_status_t status) { - int err; - - switch (status) { - case EFI_SUCCESS: - err = 0; - break; - case EFI_INVALID_PARAMETER: - err = -EINVAL; - break; - case EFI_OUT_OF_RESOURCES: - err = -ENOSPC; - break; - case EFI_DEVICE_ERROR: - err = -EIO; - break; - case EFI_WRITE_PROTECTED: - err = -EROFS; - break; - case EFI_SECURITY_VIOLATION: - err = -EACCES; - break; - case EFI_NOT_FOUND: - err = -ENOENT; - break; - case EFI_ABORTED: - err = -EINTR; - break; - default: - err = -EINVAL; - } + struct efi_error_code *found; + size_t num = sizeof(efi_error_codes) / sizeof(struct efi_error_code); - return err; + found = bsearch((void *)(uintptr_t)status, efi_error_codes, + num, sizeof(struct efi_error_code), + efi_status_cmp_bsearch); + if (!found) + return -EINVAL; + return found->errno; +} + +const char * +efi_status_to_str(efi_status_t status) +{ + struct efi_error_code *found; + size_t num = sizeof(efi_error_codes) / sizeof(struct efi_error_code); + + found = bsearch((void *)(uintptr_t)status, efi_error_codes, + num, sizeof(struct efi_error_code), + efi_status_cmp_bsearch); + if (!found) + return "Unknown error code"; + return found->description; } EXPORT_SYMBOL_GPL(efi_status_to_err); diff --git a/drivers/firmware/efi/fdtparams.c b/drivers/firmware/efi/fdtparams.c index b815d2a754eef3..c0b3cdfce67e54 100644 --- a/drivers/firmware/efi/fdtparams.c +++ b/drivers/firmware/efi/fdtparams.c @@ -16,16 +16,24 @@ enum { MMSIZE, DCSIZE, DCVERS, + SCBOOT, PARAMCOUNT }; +static u32 __secure_boot __initdata = efi_secureboot_mode_unset; +u32 __init efi_get__secure_boot(void) +{ + return __secure_boot; +} + static __initconst const char name[][22] = { [SYSTAB] = "System Table ", [MMBASE] = "MemMap Address ", [MMSIZE] = "MemMap Size ", [DCSIZE] = "MemMap Desc. Size ", [DCVERS] = "MemMap Desc. Version ", + [SCBOOT] = "Secure Boot Enabled ", }; static __initconst const struct { @@ -53,6 +61,7 @@ static __initconst const struct { [MMSIZE] = "linux,uefi-mmap-size", [DCSIZE] = "linux,uefi-mmap-desc-size", [DCVERS] = "linux,uefi-mmap-desc-ver", + [SCBOOT] = "linux,uefi-secure-boot", } } }; @@ -95,6 +104,7 @@ u64 __init efi_get_fdt_params(struct efi_memory_map_data *mm) [MMSIZE] = { &mm->size, sizeof(mm->size) }, [DCSIZE] = { &mm->desc_size, sizeof(mm->desc_size) }, [DCVERS] = { &mm->desc_version, sizeof(mm->desc_version) }, + [SCBOOT] = { &__secure_boot, sizeof(__secure_boot) }, }; BUILD_BUG_ON(ARRAY_SIZE(target) != ARRAY_SIZE(name)); diff --git a/drivers/firmware/efi/libstub/efi-stub-helper.c b/drivers/firmware/efi/libstub/efi-stub-helper.c index f27f2e1f001997..a9efe118525e5a 100644 --- a/drivers/firmware/efi/libstub/efi-stub-helper.c +++ b/drivers/firmware/efi/libstub/efi-stub-helper.c @@ -411,6 +411,15 @@ char *efi_convert_cmdline(efi_loaded_image_t *image) return (char *)cmdline_addr; } +#ifdef CONFIG_ARM64 +#define EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES \ + EFI_GUID(0x8be0e274, 0x3970, 0x4b44, 0x80, 0xc5, 0x1a, 0xb9, 0x50, 0x2f, 0x3b, 0xfc) + +static void efi_before_ebs_notify(efi_event_t event, void *context) +{ +} +#endif + /** * efi_exit_boot_services() - Exit boot services * @handle: handle of the exiting image @@ -431,10 +440,31 @@ efi_status_t efi_exit_boot_services(void *handle, void *priv, { struct efi_boot_memmap *map; efi_status_t status; +#ifdef CONFIG_ARM64 + efi_guid_t guid = EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES; + efi_event_t event; +#endif if (efi_disable_pci_dma) efi_pci_disable_bridge_busmaster(); +#ifdef CONFIG_ARM64 + status = efi_bs_call(create_event_ex, EFI_EVT_NOTIFY_SIGNAL, + EFI_TPL_CALLBACK, efi_before_ebs_notify, NULL, + &guid, &event); + if (status == EFI_SUCCESS) { + status = efi_bs_call(signal_event, event); + if (status != EFI_SUCCESS) + efi_err("%s - signal event failed: %02lx\n", __func__, status); + + status = efi_bs_call(close_event, event); + if (status != EFI_SUCCESS) + efi_err("%s - close event failed: %02lx\n", __func__, status); + } else { + efi_err("%s - create event ex failed: %02lx\n", __func__, status); + } +#endif + status = efi_get_memory_map(&map, true); if (status != EFI_SUCCESS) return status; diff --git a/drivers/firmware/efi/libstub/efistub.h b/drivers/firmware/efi/libstub/efistub.h index fd91fc15ec810b..f12e98a9dd53e5 100644 --- a/drivers/firmware/efi/libstub/efistub.h +++ b/drivers/firmware/efi/libstub/efistub.h @@ -276,7 +276,7 @@ union efi_boot_services { efi_status_t (__efiapi *wait_for_event)(unsigned long, efi_event_t *, unsigned long *); - void *signal_event; + efi_status_t (__efiapi *signal_event)(efi_event_t); efi_status_t (__efiapi *close_event)(efi_event_t); void *check_event; void *install_protocol_interface; @@ -328,7 +328,7 @@ union efi_boot_services { void *calculate_crc32; void (__efiapi *copy_mem)(void *, const void *, unsigned long); void (__efiapi *set_mem)(void *, unsigned long, unsigned char); - void *create_event_ex; + efi_status_t (__efiapi *create_event_ex)(u32, int, void *, void *, void *, efi_event_t *); }; struct { efi_table_hdr_t hdr; diff --git a/drivers/firmware/efi/libstub/fdt.c b/drivers/firmware/efi/libstub/fdt.c index 23b3543d3041b0..d4fea86bd38078 100644 --- a/drivers/firmware/efi/libstub/fdt.c +++ b/drivers/firmware/efi/libstub/fdt.c @@ -132,6 +132,12 @@ static efi_status_t update_fdt(void *orig_fdt, unsigned long orig_fdt_size, } } + fdt_val32 = cpu_to_fdt32(efi_get_secureboot()); + status = fdt_setprop(fdt, node, "linux,uefi-secure-boot", + &fdt_val32, sizeof(fdt_val32)); + if (status) + goto fdt_set_fail; + /* Shrink the FDT back to its minimum size: */ fdt_pack(fdt); diff --git a/drivers/firmware/efi/secureboot.c b/drivers/firmware/efi/secureboot.c new file mode 100644 index 00000000000000..de0a3714a5d448 --- /dev/null +++ b/drivers/firmware/efi/secureboot.c @@ -0,0 +1,38 @@ +/* Core kernel secure boot support. + * + * Copyright (C) 2017 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include + +/* + * Decide what to do when UEFI secure boot mode is enabled. + */ +void __init efi_set_secure_boot(enum efi_secureboot_mode mode) +{ + if (efi_enabled(EFI_BOOT)) { + switch (mode) { + case efi_secureboot_mode_disabled: + pr_info("Secure boot disabled\n"); + break; + case efi_secureboot_mode_enabled: + set_bit(EFI_SECURE_BOOT, &efi.flags); + pr_info("Secure boot enabled\n"); + break; + default: + pr_warn("Secure boot could not be determined (mode %u)\n", + mode); + break; + } + } +} diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 6b601a4b89dbf0..ee7154e1d51a22 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2287,6 +2287,8 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_send); + any potential issues with this, only allow validated machines for now. */ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { + { .compatible = "acer,swift-sf14-11" }, + { .compatible = "acer,swift-go14-01" }, { .compatible = "asus,vivobook-s15" }, { .compatible = "asus,vivobook-s15-x1p4" }, { .compatible = "asus,zenbook-a14-ux3407qa" }, @@ -2295,11 +2297,17 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "dell,latitude-7455" }, { .compatible = "dell,xps13-9345" }, { .compatible = "ecs,liva-qc710" }, + { .compatible = "hp,elitebook-6-g1q" }, { .compatible = "hp,elitebook-ultra-g1q" }, + { .compatible = "hp,omnibook-5" }, { .compatible = "hp,omnibook-x14" }, + { .compatible = "hp,omnibook-x14-fe1" }, { .compatible = "huawei,gaokun3" }, { .compatible = "lenovo,flex-5g" }, { .compatible = "lenovo,ideacentre-mini-01q8x10" }, + { .compatible = "lenovo,ideapad-5-2in1" }, + { .compatible = "lenovo,ideapad-slim3" }, + { .compatible = "lenovo,ideapad-slim5x" }, { .compatible = "lenovo,thinkbook-16" }, { .compatible = "lenovo,thinkpad-t14s" }, { .compatible = "lenovo,thinkpad-x13s", }, diff --git a/drivers/firmware/qcom/qcom_tzmem.c b/drivers/firmware/qcom/qcom_tzmem.c index 0635cbeacfc8e6..d800c29c325b6a 100644 --- a/drivers/firmware/qcom/qcom_tzmem.c +++ b/drivers/firmware/qcom/qcom_tzmem.c @@ -71,9 +71,12 @@ static void qcom_tzmem_cleanup_area(struct qcom_tzmem_area *area) #include #include +#define QCOM_SHM_BRIDGE_SELF_OWNER BIT(1) +#define QCOM_SHM_BRIDGE_SELF_OWNER_PERM_SHIFT 2 #define QCOM_SHM_BRIDGE_NUM_VM_SHIFT 9 static bool qcom_tzmem_using_shm_bridge; +static u32 qcom_tzmem_vmid = QCOM_SCM_VMID_HLOS; /* List of machines that are known to not support SHM bridge correctly. */ static const char *const qcom_tzmem_blacklist[] = { @@ -91,9 +94,15 @@ static int qcom_tzmem_init(void) const char *const *platform; int ret; - for (platform = qcom_tzmem_blacklist; *platform; platform++) { - if (of_machine_is_compatible(*platform)) - goto notsupp; + device_property_read_u32(qcom_tzmem_dev, "qcom,shm-bridge-vmid", + &qcom_tzmem_vmid); + + /* Skip blocklist if self owner is requested */ + if (qcom_tzmem_vmid != QCOM_SCM_VMID_SELF_OWNER) { + for (platform = qcom_tzmem_blacklist; *platform; platform++) { + if (of_machine_is_compatible(*platform)) + goto notsupp; + } } ret = qcom_scm_shm_bridge_enable(qcom_tzmem_dev); @@ -125,6 +134,7 @@ static int qcom_tzmem_init(void) int qcom_tzmem_shm_bridge_create(phys_addr_t paddr, size_t size, u64 *handle) { u64 pfn_and_ns_perm, ipfn_and_s_perm, size_and_flags; + u64 ns_vmids = qcom_tzmem_vmid; int ret; if (!qcom_tzmem_using_shm_bridge) @@ -134,9 +144,15 @@ int qcom_tzmem_shm_bridge_create(phys_addr_t paddr, size_t size, u64 *handle) ipfn_and_s_perm = paddr | QCOM_SCM_PERM_RW; size_and_flags = size | (1 << QCOM_SHM_BRIDGE_NUM_VM_SHIFT); + if (qcom_tzmem_vmid == QCOM_SCM_VMID_SELF_OWNER) { + size_and_flags = size | QCOM_SHM_BRIDGE_SELF_OWNER | + (QCOM_SCM_PERM_RW << QCOM_SHM_BRIDGE_SELF_OWNER_PERM_SHIFT); + ns_vmids = 0; + } + + ret = qcom_scm_shm_bridge_create(pfn_and_ns_perm, ipfn_and_s_perm, - size_and_flags, QCOM_SCM_VMID_HLOS, - handle); + size_and_flags, ns_vmids, handle); if (ret) { dev_err(qcom_tzmem_dev, "SHM Bridge failed: ret %d paddr 0x%pa, size %zu\n", diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 28cf6d2e83c279..ea24477106b3ff 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1811,6 +1811,18 @@ endmenu menu "PCI GPIO expanders" depends on PCI +config GPIO_AAEON + tristate "AAEON GPIO support" + depends on ASUS_WMI + depends on UBUNTU_ODM_DRIVERS + select MFD_AAEON + help + Say yes here to support GPIO pins on Single Board Computers produced + by AAEON. + + This driver leverages the ASUS WMI interface to access device + resources. + config GPIO_AMD8111 tristate "AMD 8111 GPIO driver" depends on X86 || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 4d0e900402fcf9..b3e3a76adef06b 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_GPIO_104_IDI_48) += gpio-104-idi-48.o obj-$(CONFIG_GPIO_104_IDIO_16) += gpio-104-idio-16.o obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o obj-$(CONFIG_GPIO_74XX_MMIO) += gpio-74xx-mmio.o +obj-$(CONFIG_GPIO_AAEON) += gpio-aaeon.o obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o obj-$(CONFIG_GPIO_ADP5585) += gpio-adp5585.o diff --git a/drivers/gpio/gpio-aaeon.c b/drivers/gpio/gpio-aaeon.c new file mode 100644 index 00000000000000..e57f41eed3ec0a --- /dev/null +++ b/drivers/gpio/gpio-aaeon.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AAEON GPIO driver + * Copyright (c) 2021, AAEON Ltd. + * + * Author: Edward Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRVNAME "gpio_aaeon" +#define ASUS_NB_WMI_EVENT_GUID "0B3CBB35-E3C2-45ED-91C2-4C5A6D195D1C" +#define AAEON_WMI_MGMT_GUID "97845ED0-4E6D-11DE-8A39-0800200C9A66" + +#define GET_GPIO_NUMBER_ID 0x00010000 +#define GET_LEVEL_METHOD_ID 0x00010001 +#define SET_LEVEL_METHOD_ID 0x00010002 +#define GET_DIRECTION_METHOD_ID 0x00010003 +#define SET_DIRECTION_METHOD_ID 0x00010004 +#define GET_SIO_NUMBER_METHOD_ID 0xF0010 + +struct aaeon_gpio_bank { + struct gpio_chip chip; + unsigned int regbase; + struct aaeon_gpio_data *data; +}; + +struct aaeon_gpio_data { + int nr_bank; + struct aaeon_gpio_bank *bank; +}; + +static int aaeon_gpio_get_number(void); +static int aaeon_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset); +static int aaeon_gpio_output_set_direction(struct gpio_chip *chip, + unsigned int offset, int value); +static int aaeon_gpio_input_set_direction(struct gpio_chip *chip, + unsigned int offset); +static int aaeon_gpio_get(struct gpio_chip *chip, + unsigned int offset); +static int aaeon_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value); + +#define AAEON_GPIO_BANK(_base, _ngpio, _regbase) \ +{ \ + .chip = { \ + .label = DRVNAME, \ + .owner = THIS_MODULE, \ + .get_direction = aaeon_gpio_get_direction, \ + .direction_input = aaeon_gpio_input_set_direction, \ + .direction_output = aaeon_gpio_output_set_direction, \ + .get = aaeon_gpio_get, \ + .set = aaeon_gpio_set, \ + .base = _base, \ + .ngpio = _ngpio, \ + .can_sleep = true, \ + }, \ + .regbase = _regbase, \ +} + +static struct aaeon_gpio_bank aaeon_gpio_bank[] = { + AAEON_GPIO_BANK(0, 0, 0xF0), +}; + +static int aaeon_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + int err, retval; + u32 dev_id = 0x0; + + dev_id |= offset; + err = asus_wmi_evaluate_method(GET_DIRECTION_METHOD_ID, dev_id, + 0, &retval); + if (err) + return err; + + return retval; +} + +static int aaeon_gpio_input_set_direction(struct gpio_chip *chip, + unsigned int offset) +{ + int err, retval; + u32 dev_id; + + dev_id = BIT(16) | offset; + err = asus_wmi_evaluate_method(SET_DIRECTION_METHOD_ID, dev_id, + 0, &retval); + if (err) + return err; + + return retval; +} + +static int aaeon_gpio_output_set_direction(struct gpio_chip *chip, + unsigned int offset, int value) +{ + int err, retval; + u32 dev_id = 0x0; + + dev_id |= offset; + err = asus_wmi_evaluate_method(SET_DIRECTION_METHOD_ID, dev_id, + 0, &retval); + if (err) + return err; + + return retval; +} + +static int aaeon_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + int err, retval; + u32 dev_id = 0x0; + + dev_id |= offset; + err = asus_wmi_evaluate_method(GET_LEVEL_METHOD_ID, dev_id, 0, &retval); + if (err) + return err; + + return retval; +} + +static int aaeon_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + int retval; + u32 dev_id = offset; + + if (value) + dev_id = BIT(16) | dev_id; + + return asus_wmi_evaluate_method(SET_LEVEL_METHOD_ID, dev_id, 0, &retval); +} + +static int aaeon_gpio_get_number(void) +{ + int err, retval; + + err = asus_wmi_evaluate_method(GET_GPIO_NUMBER_ID, + GET_SIO_NUMBER_METHOD_ID, + 0, &retval); + if (err) + return err; + + return retval; +} + +static int __init aaeon_gpio_probe(struct platform_device *pdev) +{ + int err, i; + int dio_number = 0; + struct aaeon_gpio_data *data; + struct aaeon_gpio_bank *bank; + + /* Prevent other drivers adding this platfom device */ + if (!wmi_has_guid(AAEON_WMI_MGMT_GUID)) { + pr_debug("AAEON Management GUID not found\n"); + return -ENODEV; + } + + dio_number = aaeon_gpio_get_number(); + if (dio_number < 0) + return -ENODEV; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->nr_bank = ARRAY_SIZE(aaeon_gpio_bank); + data->bank = aaeon_gpio_bank; + platform_set_drvdata(pdev, data); + bank = &data->bank[0]; + bank->chip.parent = &pdev->dev; + bank->chip.ngpio = dio_number; + bank->data = data; + err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank); + if (err) + pr_debug("Failed to register gpiochip %d: %d\n", i, err); + + return err; +} + +static struct platform_driver aaeon_gpio_driver = { + .driver = { + .name = "gpio-aaeon", + }, +}; + +module_platform_driver_probe(aaeon_gpio_driver, aaeon_gpio_probe); + +MODULE_ALIAS("platform:gpio-aaeon"); +MODULE_DESCRIPTION("AAEON GPIO Driver"); +MODULE_AUTHOR("Edward Lin "); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("ASUS_WMI"); diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index e623ccb4c1d8ab..a75ce4ef44db3f 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -42,6 +42,7 @@ #include #include #include +#include #include "drm_dp_helper_internal.h" @@ -4399,6 +4400,17 @@ drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_inf } pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + /* === DEBUG: ATNA40CT01 / eDP backlight bit count reporting === */ + drm_info(aux->drm_dev, + "[eDP BL DEBUG] PWMGEN_BIT_COUNT (0x724) raw=0x%02x (Pn=%u), " + "CAP_MIN (0x725)=0x%02x (min=%u), CAP_MAX (0x726)=0x%02x (max=%u)\n", + bit_count, bit_count, + pn_min, pn_min, + pn_max, pn_max); + if (unlikely(pn_min > pn_max)) { + drm_info(aux->drm_dev, "[eDP BL DEBUG] Invalid CAP_MIN > CAP_MAX!\n"); + } + if (unlikely(pn_min > pn_max)) { drm_dbg_kms(aux->drm_dev, "%s: Invalid pwmgen bit count cap min/max returned: %d %d\n", aux->name, pn_min, pn_max); @@ -4418,6 +4430,42 @@ drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_inf pn = clamp(bit_count, pn_min, pn_max); bl->max = (1 << pn) - 1; + + /* Allow DT to override the DPCD-reported brightness range + * (e.g. Samsung ATNA40CT01 reports 16-bit but only implements 2047 levels). + */ + struct device_node *np = aux->dev->of_node; + struct device_node *target_np = np; + + if (np) { + struct device_node *auxbus = of_get_child_by_name(np, "aux-bus"); + if (auxbus) { + struct device_node *panel = of_get_child_by_name(auxbus, "panel"); + if (panel) { + target_np = panel; + of_node_put(panel); + } + of_node_put(auxbus); + } + } + + if (target_np) { + u32 val; + if (!of_property_read_u32(target_np, "max-brightness", &val)) { + dev_info(aux->dev, "%s: found max-brightness=%u on %s\n", + aux->name, val, target_np->full_name); + /* === your override logic goes here === */ + if (val > 0) { + bl->max = val; + pn = ilog2(val + 1); + drm_dbg_kms(aux->drm_dev, "%s: using DT max-brightness = %u (pn=%u)\n", + aux->name, val, pn); + } + } else { + dev_info(aux->dev, "%s: no max-brightness property found\n", aux->name); + } + } + if (!driver_pwm_freq_hz) { if (pn != bit_count) goto bit_count_write_back; diff --git a/drivers/gpu/drm/display/drm_hdmi_audio_helper.c b/drivers/gpu/drm/display/drm_hdmi_audio_helper.c index 7d78b02c144621..6ca1c7ad0632f3 100644 --- a/drivers/gpu/drm/display/drm_hdmi_audio_helper.c +++ b/drivers/gpu/drm/display/drm_hdmi_audio_helper.c @@ -130,6 +130,7 @@ EXPORT_SYMBOL(drm_connector_hdmi_audio_plugged_notify); static const struct hdmi_codec_ops drm_connector_hdmi_audio_ops = { .audio_startup = drm_connector_hdmi_audio_startup, + .hw_params = drm_connector_hdmi_audio_prepare, .prepare = drm_connector_hdmi_audio_prepare, .audio_shutdown = drm_connector_hdmi_audio_shutdown, .mute_stream = drm_connector_hdmi_audio_mute_stream, diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 5e939004b6463c..40a9234e6e5dc6 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -3,7 +3,6 @@ config DRM_I915 tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics" depends on DRM depends on X86 && PCI - depends on !PREEMPT_RT select INTEL_GTT if X86 select INTERVAL_TREE # we need shmfs for the swappable backing store, and in particular diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 7ce2b52297d172..1ef8c9e90c9b02 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -633,7 +633,8 @@ void intel_pipe_update_start(struct intel_atomic_state *state, */ intel_psr_wait_for_idle_locked(new_crtc_state); - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); crtc->debug.min_vbl = evade.min; crtc->debug.max_vbl = evade.max; @@ -651,7 +652,8 @@ void intel_pipe_update_start(struct intel_atomic_state *state, return; irq_disable: - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); } #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE) @@ -798,7 +800,8 @@ void intel_pipe_update_end(struct intel_atomic_state *state, !new_crtc_state->vrr.enable)) intel_vrr_send_push(NULL, new_crtc_state); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_parent_vgpu_active(display)) goto out; diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 52347668f27d6d..97b6c7c533b74c 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -919,13 +919,15 @@ intel_legacy_cursor_update(struct drm_plane *_plane, */ intel_psr_wait_for_idle_locked(crtc_state); - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); intel_vblank_evade(&evade); drm_crtc_vblank_put(&crtc->base); } else { - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); } if (new_plane_state->uapi.visible) { @@ -935,7 +937,8 @@ intel_legacy_cursor_update(struct drm_plane *_plane, intel_plane_disable_arm(NULL, plane, crtc_state); } - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); intel_psr_unlock(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display_trace.h b/drivers/gpu/drm/i915/display/intel_display_trace.h index 504d105935bc06..a974fedc9692f8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@ -13,6 +13,10 @@ #if !defined(__INTEL_DISPLAY_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) #define __INTEL_DISPLAY_TRACE_H__ +#if defined(CONFIG_PREEMPT_RT) && !defined(NOTRACE) +#define NOTRACE +#endif + #include #include #include diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 28d81199792efd..a329e938d9cffe 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -316,6 +316,21 @@ static void intel_vblank_section_exit(struct intel_display *display) struct intel_uncore *uncore = to_intel_uncore(display->drm); spin_unlock(&uncore->lock); } + +static void intel_vblank_section_enter_irqf(struct intel_display *display, unsigned long *flags) +__acquires(i915->uncore.lock) +{ + struct intel_uncore *uncore = to_intel_uncore(display->drm); + spin_lock_irqsave(&uncore->lock, *flags); +} + +static void intel_vblank_section_exit_irqf(struct intel_display *display, unsigned long flags) +__releases(i915->uncore.lock) +{ + struct intel_uncore *uncore = to_intel_uncore(display->drm); + spin_unlock_irqrestore(&uncore->lock, flags); +} + #else static void intel_vblank_section_enter(struct intel_display *display) { @@ -324,6 +339,17 @@ static void intel_vblank_section_enter(struct intel_display *display) static void intel_vblank_section_exit(struct intel_display *display) { } + +static void intel_vblank_section_enter_irqf(struct intel_display *display, unsigned long *flags) +{ + *flags = 0; +} + +static void intel_vblank_section_exit_irqf(struct intel_display *display, unsigned long flags) +{ + if (flags) + return; +} #endif static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, @@ -360,10 +386,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, * timing critical raw register reads, potentially with * preemption disabled, so the following code must not block. */ - local_irq_save(irqflags); - intel_vblank_section_enter(display); + intel_vblank_section_enter_irqf(display, &irqflags); - /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ + if (IS_ENABLED(CONFIG_PREEMPT_RT)) + preempt_disable(); /* Get optional system timestamp before query. */ if (stime) @@ -427,10 +453,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, if (etime) *etime = ktime_get(); - /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ + if (IS_ENABLED(CONFIG_PREEMPT_RT)) + preempt_enable(); - intel_vblank_section_exit(display); - local_irq_restore(irqflags); + intel_vblank_section_exit_irqf(display, irqflags); /* * While in vblank, position will be negative @@ -468,13 +494,11 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc) unsigned long irqflags; int position; - local_irq_save(irqflags); - intel_vblank_section_enter(display); + intel_vblank_section_enter_irqf(display, &irqflags); position = __intel_get_crtc_scanline(crtc); - intel_vblank_section_exit(display); - local_irq_restore(irqflags); + intel_vblank_section_exit_irqf(display, irqflags); return position; } @@ -764,11 +788,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade) break; } - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); timeout = schedule_timeout(timeout); - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); } finish_wait(wq, &wait); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c0fd349a4600c6..9dd9665128caa1 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1607,7 +1607,7 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) static unsigned long stop_timeout(const struct intel_engine_cs *engine) { - if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ + if (in_atomic() || irqs_disabled() || rcu_preempt_depth()) /* inside atomic preempt-reset? */ return 0; /* diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index e693b0c9d2a3e2..841f7193267565 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1300,7 +1300,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * and context switches) submission. */ - spin_lock(&sched_engine->lock); + spin_lock_irq(&sched_engine->lock); /* * If the queue is higher priority than the last @@ -1400,7 +1400,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * Even if ELSP[1] is occupied and not worthy * of timeslices, our queue might be. */ - spin_unlock(&sched_engine->lock); + spin_unlock_irq(&sched_engine->lock); return; } } @@ -1426,7 +1426,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last && !can_merge_rq(last, rq)) { spin_unlock(&ve->base.sched_engine->lock); - spin_unlock(&engine->sched_engine->lock); + spin_unlock_irq(&engine->sched_engine->lock); return; /* leave this for another sibling */ } @@ -1588,7 +1588,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) */ sched_engine->queue_priority_hint = queue_prio(sched_engine); i915_sched_engine_reset_on_empty(sched_engine); - spin_unlock(&sched_engine->lock); + spin_unlock_irq(&sched_engine->lock); /* * We can skip poking the HW if we ended up with exactly the same set @@ -1614,13 +1614,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine) } } -static void execlists_dequeue_irq(struct intel_engine_cs *engine) -{ - local_irq_disable(); /* Suspend interrupts across request submission */ - execlists_dequeue(engine); - local_irq_enable(); /* flush irq_work (e.g. breadcrumb enabling) */ -} - static void clear_ports(struct i915_request **ports, int count) { memset_p((void **)ports, NULL, count); @@ -2475,7 +2468,7 @@ static void execlists_submission_tasklet(struct tasklet_struct *t) } if (!engine->execlists.pending[0]) { - execlists_dequeue_irq(engine); + execlists_dequeue(engine); start_timeslice(engine); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index 053780f562c1af..b25fa8f4dc4bde 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -362,7 +362,7 @@ static inline int intel_guc_send_busy_loop(struct intel_guc *guc, { int err; unsigned int sleep_period_ms = 1; - bool not_atomic = !in_atomic() && !irqs_disabled(); + bool not_atomic = !in_atomic() && !irqs_disabled() && !rcu_preempt_depth(); /* * FIXME: Have caller pass in if we are in an atomic context to avoid diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index d2c7b1090df081..f66f8efc70629a 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -610,7 +610,6 @@ bool __i915_request_submit(struct i915_request *request) RQ_TRACE(request, "\n"); - GEM_BUG_ON(!irqs_disabled()); lockdep_assert_held(&engine->sched_engine->lock); /* @@ -719,7 +718,6 @@ void __i915_request_unsubmit(struct i915_request *request) */ RQ_TRACE(request, "\n"); - GEM_BUG_ON(!irqs_disabled()); lockdep_assert_held(&engine->sched_engine->lock); /* diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index 7ed41ce9b7085f..6b87ef6005c695 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -6,6 +6,10 @@ #if !defined(_I915_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ) #define _I915_TRACE_H_ +#if defined(CONFIG_PREEMPT_RT) && !defined(NOTRACE) +#define NOTRACE +#endif + #include #include #include diff --git a/drivers/gpu/drm/i915/intel_uncore_trace.h b/drivers/gpu/drm/i915/intel_uncore_trace.h index f13ff71edf2db8..3c67e267fb602d 100644 --- a/drivers/gpu/drm/i915/intel_uncore_trace.h +++ b/drivers/gpu/drm/i915/intel_uncore_trace.h @@ -7,6 +7,10 @@ #if !defined(__INTEL_UNCORE_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) #define __INTEL_UNCORE_TRACE_H__ +#if defined(CONFIG_PREEMPT_RT) && !defined(NOTRACE) +#define NOTRACE +#endif + #include "i915_reg_defs.h" #include diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 2e5d7b53a0c380..d9d10f5a7f2cd9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2105,7 +2105,7 @@ void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on) pm_runtime_put(&gpu->pdev->dev); } -void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) +static void a6xx_gmu_destroy(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct a6xx_gmu *gmu = &a6xx_gpu->gmu; @@ -2185,7 +2185,7 @@ static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_si return ret; } -int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) +static int a6xx_gmu_wrapper_pdev_bind(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { struct platform_device *pdev = of_find_device_by_node(node); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; @@ -2238,7 +2238,8 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) goto err_mmio; } - if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) { + if (!device_link_add(gmu->dev, gmu->cxpd, + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS)) { ret = -ENODEV; goto detach_cxpd; } @@ -2254,6 +2255,8 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) goto err_mmio; } + mutex_init(&gmu->lock); + gmu->initialized = true; return 0; @@ -2271,7 +2274,7 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) return ret; } -int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) +static int a6xx_gmu_pdev_bind(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { struct platform_device *pdev = of_find_device_by_node(node); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; @@ -2424,7 +2427,8 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) goto err_mmio; } - link = device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME); + link = device_link_add(gmu->dev, gmu->cxpd, + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); if (!link) { ret = -ENODEV; goto detach_cxpd; @@ -2460,6 +2464,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) /* Initialize RPMh */ a6xx_gmu_rpmh_init(gmu); + mutex_init(&gmu->lock); gmu->initialized = true; return 0; @@ -2489,3 +2494,64 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) return ret; } + +static int a6xx_gmu_bind(struct device *dev, struct device *master, void *data) +{ + int (*bind)(struct a6xx_gpu *gpu, struct device_node *node) = of_device_get_match_data(dev); + struct a6xx_gpu *a6xx_gpu = dev_get_drvdata(dev); + + if (WARN_ON(!a6xx_gpu)) + return -ENODEV; + + return bind(a6xx_gpu, dev->of_node); +} + +static void a6xx_gmu_unbind(struct device *dev, struct device *master, void *data) +{ + struct a6xx_gpu *a6xx_gpu = dev_get_drvdata(dev); + + a6xx_gmu_destroy(a6xx_gpu); + dev_set_drvdata(dev, NULL); +} + +static const struct component_ops a6xx_gmu_bind_ops = { + .bind = a6xx_gmu_bind, + .unbind = a6xx_gmu_unbind, +}; + +static int a6xx_gmu_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &a6xx_gmu_bind_ops); +} + +static void a6xx_gmu_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &a6xx_gmu_bind_ops); +} + +static const struct of_device_id a6xx_gmu_dt_match[] = { + { .compatible = "qcom,adreno-gmu", .data = a6xx_gmu_pdev_bind }, + { .compatible = "qcom,adreno-rgmu", .data = a6xx_gmu_wrapper_pdev_bind }, + { .compatible = "qcom,adreno-gmu-wrapper", .data = a6xx_gmu_wrapper_pdev_bind }, + { } +}; +MODULE_DEVICE_TABLE(of, a6xx_gmu_dt_match); + +static struct platform_driver adreno_gmu_driver = { + .probe = a6xx_gmu_probe, + .remove = a6xx_gmu_remove, + .driver = { + .name = "adreno_gmu", + .of_match_table = a6xx_gmu_dt_match, + }, +}; + +void __init adreno_gmu_register(void) +{ + platform_driver_register(&adreno_gmu_driver); +} + +void __exit adreno_gmu_unregister(void) +{ + platform_driver_unregister(&adreno_gmu_driver); +} diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 8b3bb2fd433bab..c3ec636461cdf6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -2312,8 +2313,6 @@ static void a6xx_destroy(struct msm_gpu *gpu) a6xx_llc_slices_destroy(a6xx_gpu); - a6xx_gmu_remove(a6xx_gpu); - adreno_gpu_cleanup(adreno_gpu); kfree(a6xx_gpu); @@ -2661,6 +2660,8 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) struct adreno_platform_config *config = pdev->dev.platform_data; const struct adreno_info *info = config->info; struct device_node *phandle; + struct device_node *node; + struct platform_device *gmu_pdev; struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; @@ -2695,13 +2696,10 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->registers = NULL; - /* Check if there is a GMU phandle and set it up */ - struct device_node *node __free(device_node) = - of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); - /* FIXME: How do we gracefully handle this? */ - BUG_ON(!node); - - adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); + node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); + WARN_ON(!node); + adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, + "qcom,adreno-gmu-wrapper"); adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); @@ -2754,15 +2752,6 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) priv->gpu_clamp_to_idle = true; - if (adreno_has_gmu_wrapper(adreno_gpu) || adreno_has_rgmu(adreno_gpu)) - ret = a6xx_gmu_wrapper_init(a6xx_gpu, node); - else - ret = a6xx_gmu_init(a6xx_gpu, node); - if (ret) { - a6xx_destroy(&(a6xx_gpu->base.base)); - return ERR_PTR(ret); - } - adreno_gpu->uche_trap_base = 0x1fffffffff000ull; msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu, @@ -2777,6 +2766,13 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* Set up the preemption specific bits and pieces for each ringbuffer */ a6xx_preempt_init(gpu); + gmu_pdev = of_find_device_by_node(node); + of_node_put(node); + if (gmu_pdev) { + platform_set_drvdata(gmu_pdev, a6xx_gpu); + put_device(&gmu_pdev->dev); + } + return gpu; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index b50c57f427b44d..cb53de26a79b2f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -278,9 +278,6 @@ bool a6xx_gmu_isidle(struct a6xx_gmu *gmu); int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); -int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); -int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); -void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on); void a6xx_preempt_init(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 7f20320ef66af3..bbed7ee14c6d71 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -271,21 +271,26 @@ static const struct component_ops a3xx_ops = { static int adreno_probe(struct platform_device *pdev) { - if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") || - msm_gpu_no_components()) - return msm_gpu_probe(pdev, &a3xx_ops); + int ret; + + if (msm_gpu_use_separate_drm_dev(pdev)) { + ret = msm_gpu_probe(pdev); + if (ret) + return ret; + } - return component_add(&pdev->dev, &a3xx_ops); + ret = component_add(&pdev->dev, &a3xx_ops); + if (ret && msm_gpu_use_separate_drm_dev(pdev)) + msm_gpu_remove(pdev); + + return ret; } static void adreno_remove(struct platform_device *pdev) { - struct msm_drm_private *priv = platform_get_drvdata(pdev); - - if (priv->kms_init) - component_del(&pdev->dev, &a3xx_ops); - else - msm_gpu_remove(pdev, &a3xx_ops); + component_del(&pdev->dev, &a3xx_ops); + if (msm_gpu_use_separate_drm_dev(pdev)) + msm_gpu_remove(pdev); } static void adreno_shutdown(struct platform_device *pdev) @@ -422,6 +427,7 @@ void __init adreno_register(void) return; platform_driver_register(&adreno_driver); + adreno_gmu_register(); } void __exit adreno_unregister(void) @@ -429,5 +435,6 @@ void __exit adreno_unregister(void) if (skip_gpu) return; + adreno_gmu_unregister(); platform_driver_unregister(&adreno_driver); } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 1f201322cb6eab..d01f163b0e4ed0 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -642,7 +642,8 @@ int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state); int adreno_gpu_state_put(struct msm_gpu_state *state); void adreno_show_object(struct drm_printer *p, void **ptr, int len, bool *encoded); - +void adreno_gmu_register(void); +void adreno_gmu_unregister(void); /* * Common helper function to initialize the default address space for arm-smmu * attached targets diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 7b3febf8742d72..72ce8a119bb154 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -85,28 +85,28 @@ static const struct dpu_sspp_cfg x1e80100_sspp[] = { }, { .name = "sspp_8", .id = SSPP_DMA0, .base = 0x24000, .len = 0x344, - .features = DMA_SDM845_MASK_SDMA, + .features = DMA_CURSOR_SDM845_MASK_SDMA, .sblk = &dpu_dma_sblk, .xin_id = 1, .type = SSPP_TYPE_DMA, }, { .name = "sspp_9", .id = SSPP_DMA1, .base = 0x26000, .len = 0x344, - .features = DMA_SDM845_MASK_SDMA, + .features = DMA_CURSOR_SDM845_MASK_SDMA, .sblk = &dpu_dma_sblk, .xin_id = 5, .type = SSPP_TYPE_DMA, }, { .name = "sspp_10", .id = SSPP_DMA2, .base = 0x28000, .len = 0x344, - .features = DMA_SDM845_MASK_SDMA, + .features = DMA_CURSOR_SDM845_MASK_SDMA, .sblk = &dpu_dma_sblk, .xin_id = 9, .type = SSPP_TYPE_DMA, }, { .name = "sspp_11", .id = SSPP_DMA3, .base = 0x2a000, .len = 0x344, - .features = DMA_SDM845_MASK_SDMA, + .features = DMA_CURSOR_SDM845_MASK_SDMA, .sblk = &dpu_dma_sblk, .xin_id = 13, .type = SSPP_TYPE_DMA, @@ -407,7 +407,7 @@ static const struct dpu_perf_cfg x1e80100_perf_data = { {.rd_enable = 1, .wr_enable = 1}, {.rd_enable = 1, .wr_enable = 0} }, - .clk_inefficiency_factor = 105, + .clk_inefficiency_factor = 104, .bw_inefficiency_factor = 120, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 13cc658065c56a..6524531bd8bdc3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -394,6 +394,10 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, trace_dpu_core_perf_update_clk(kms->dev, !crtc->enabled, clk_rate); + /* If we're going offline, PM callbacks will disable the clocks instead */ + if (!clk_rate) + return 0; + clk_rate = min(clk_rate, kms->perf.max_core_clk_rate); ret = dev_pm_opp_set_rate(&kms->pdev->dev, clk_rate); if (ret) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 42d0a529b4d515..005c128d17f020 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1535,8 +1535,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); /* don't reallocate resources if only ACTIVE has beeen changed */ - if (crtc_state->mode_changed || crtc_state->connectors_changed || - crtc_state->color_mgmt_changed) { + if (crtc_state->mode_changed || crtc_state->connectors_changed) { rc = dpu_crtc_assign_resources(crtc, crtc_state); if (rc < 0) return rc; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index ba810f26ea3099..c3a275ffaa195f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -86,7 +86,7 @@ static void drm_mode_to_intf_timing_params( timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0; timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; timing->border_clr = 0; - timing->underflow_clr = 0xff; + timing->underflow_clr = 0xffc0cb; timing->hsync_skew = mode->hskew; /* DSI controller cannot handle active-low sync signals. */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index da3556eb6ecc25..23e0a5b2ca22c1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1454,6 +1454,7 @@ static int __maybe_unused dpu_runtime_resume(struct device *dev) struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); struct drm_encoder *encoder; struct drm_device *ddev; + unsigned long core_rate; ddev = dpu_kms->dev; @@ -1463,6 +1464,24 @@ static int __maybe_unused dpu_runtime_resume(struct device *dev) return rc; } + /* + * Runtime suspend can drop the power-domain performance state even when + * the clock framework still reports the previously programmed rate. + * Re-assert the current core clock rate so OPP required-opps are restored + * before touching DPU registers. + */ + core_rate = dpu_kms_get_clk_rate(dpu_kms, "core"); + if (core_rate) { + core_rate = min_t(unsigned long, core_rate, dpu_kms->perf.max_core_clk_rate); + rc = dev_pm_opp_set_rate(&dpu_kms->pdev->dev, core_rate); + if (rc) { + DPU_ERROR("failed to restore core clock rate %lu: %d\n", + core_rate, rc); + return rc; + } + dpu_kms->perf.core_clk_rate = core_rate; + } + dpu_vbif_init_memtypes(dpu_kms); drm_for_each_encoder(encoder, ddev) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_audio.c index 41018e82efa10e..af7b72dd896c7a 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -277,17 +277,12 @@ int msm_dp_audio_prepare(struct drm_bridge *bridge, msm_dp_display = to_dp_bridge(bridge)->msm_dp_display; /* - * there could be cases where sound card can be opened even - * before OR even when DP is not connected . This can cause - * unclocked access as the audio subsystem relies on the DP - * driver to maintain the correct state of clocks. To protect - * such cases check for connection status and bail out if not - * connected. + * Userspace can probe DP PCMs while the connector is unplugged or + * disabled. The controller clocks are off then, so skip register + * programming; jack and ELD state still report sink availability. */ - if (!msm_dp_display->power_on) { - rc = -EINVAL; - goto end; - } + if (!msm_dp_display->power_on) + return 0; audio = msm_dp_audio_get_data(msm_dp_display); if (IS_ERR(audio)) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 86ef8c89ad4437..86df6d92afd456 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -140,6 +141,7 @@ struct msm_dp_ctrl_private { bool core_clks_on; bool link_clks_on; bool stream_clks_on; + bool clk_defaults_set; }; static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) @@ -1803,6 +1805,14 @@ static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl) phy_configure(phy, &ctrl->phy_opts); phy_power_on(phy); + if (!ctrl->clk_defaults_set) { + ret = of_clk_set_defaults(ctrl->dev->of_node, false); + if (ret) + return ret; + + ctrl->clk_defaults_set = true; + } + dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); ret = msm_dp_ctrl_link_clk_enable(&ctrl->msm_dp_ctrl); if (ret) @@ -1855,6 +1865,15 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) if (!ctrl->panel->psr_cap.version) return; + /* + * PSR SDPs must be flushed directly. The peripheral flush path can + * complete normally while the sink captures an invalid frame. + */ + cfg = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + cfg &= ~DP_MAINLINK_CTRL_FLUSH_MODE_MASK; + cfg |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, cfg); + /* enable PSR1 function */ cfg = msm_dp_read_link(ctrl, REG_PSR_CONFIG); cfg |= PSR1_SUPPORTED; @@ -1950,13 +1969,12 @@ static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) msm_dp_ctrl_mainlink_disable(ctrl); ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; phy_configure(phy, &ctrl->phy_opts); + /* * Disable and re-enable the mainlink clock since the * link clock might have been adjusted as part of the * link maintenance. */ - dev_pm_opp_set_rate(ctrl->dev, 0); - msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); phy_power_off(phy); @@ -1982,7 +2000,6 @@ static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); - dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); phy_power_off(phy); @@ -2548,8 +2565,11 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train mainlink_ready = msm_dp_ctrl_mainlink_ready(ctrl); drm_dbg_dp(ctrl->drm_dev, "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); + return ret; end: + drm_dbg_dp(ctrl->drm_dev, + "preempted exit: mainlink %s, ret = %x\n", mainlink_ready ? "READY" : "NOT READY", ret); return ret; } @@ -2573,7 +2593,6 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl) ctrl->stream_clks_on = false; } - dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); phy_power_off(phy); @@ -2602,7 +2621,6 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) ctrl->stream_clks_on = false; } - dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); phy_power_off(phy); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index dc6f33809ca5f0..38bdcc13197e50 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1259,6 +1259,8 @@ static struct platform_driver msm_dp_display_driver = { .suppress_bind_attrs = true, .pm = &msm_dp_pm_ops, }, + /* Apply clock parents after PHY is fully initialized */ + .driver_managed_clk_defaults = true, }; int __init msm_dp_register(void) diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index b659d22f5f284d..c03b546180f353 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -49,6 +49,17 @@ static void msm_dp_bridge_debugfs_init(struct drm_bridge *bridge, struct dentry msm_dp_display_debugfs_init(dp, root, false); } +static int msm_dp_audio_startup(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct msm_dp *msm_dp_display = to_dp_bridge(bridge)->msm_dp_display; + + if (!msm_dp_display->power_on) + return -ENOTSUPP; + + return 0; +} + static const struct drm_bridge_funcs msm_dp_bridge_ops = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, @@ -65,6 +76,7 @@ static const struct drm_bridge_funcs msm_dp_bridge_ops = { .hpd_notify = msm_dp_bridge_hpd_notify, .debugfs_init = msm_dp_bridge_debugfs_init, + .dp_audio_startup = msm_dp_audio_startup, .dp_audio_prepare = msm_dp_audio_prepare, .dp_audio_shutdown = msm_dp_audio_shutdown, }; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 6bb021820d7c53..17a0e7855419db 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -12,6 +12,8 @@ #include #include +#include + #include #include #include @@ -99,6 +101,17 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel) if (rc) return rc; + /* + * for some reason the ATNA30DW01-1 OLED panel in the Surface Pro 11 + * reports a max link rate of 0 in the DPCD. Fix it to match the + * EDPOverrideDPCDCaps string found in the ACPI DSDT + */ + if (dpcd[DP_MAX_LINK_RATE] == 0 && + dmi_match(DMI_SYS_VENDOR, "Microsoft Corporation") && + dmi_match(DMI_PRODUCT_NAME, "Microsoft Surface Pro, 11th Edition")) { + dpcd[1] = DP_LINK_BW_8_1; + } + msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); link_info = &msm_dp_panel->link_info; link_info->revision = dpcd[DP_DPCD_REV]; @@ -332,8 +345,10 @@ int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, return -EINVAL; } - if (msm_dp_panel->drm_edid) + if (msm_dp_panel->drm_edid) { + drm_edid_connector_update(connector, msm_dp_panel->drm_edid); return drm_edid_connector_add_modes(connector); + } return 0; } diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 982abaaac00d53..d4727836052c88 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -549,8 +549,6 @@ int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) { - /* Drop the performance state vote */ - dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); clk_disable_unprepare(msm_host->esc_clk); clk_disable_unprepare(msm_host->pixel_clk); clk_disable_unprepare(msm_host->byte_intf_clk); diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index a8babf1dbe0d33..9d3561d4bb606a 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -196,7 +196,9 @@ int msm_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state) for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if ((old_crtc_state->ctm && !new_crtc_state->ctm) || - (!old_crtc_state->ctm && new_crtc_state->ctm)) { + (!old_crtc_state->ctm && new_crtc_state->ctm) || + (old_crtc_state->gamma_lut && !new_crtc_state->gamma_lut) || + (!old_crtc_state->gamma_lut && new_crtc_state->gamma_lut)) { new_crtc_state->mode_changed = true; state->allow_modeset = true; } diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 32d5ebea2596f2..d5bcc78380281f 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -61,9 +61,12 @@ module_param(separate_gpu_kms, bool, 0400); DECLARE_FAULT_ATTR(fail_gem_alloc); DECLARE_FAULT_ATTR(fail_gem_iova); -bool msm_gpu_no_components(void) +bool msm_gpu_use_separate_drm_dev(struct platform_device *pdev) { - return separate_gpu_kms; + if (!pdev) + return separate_gpu_kms; + + return of_device_is_compatible(pdev->dev.of_node, "amd,imageon") || separate_gpu_kms; } static int msm_drm_uninit(struct device *dev, const struct component_ops *gpu_ops) @@ -1017,7 +1020,7 @@ static const struct of_device_id msm_gpu_match[] = { static int add_gpu_components(struct device *dev, struct component_match **matchptr) { - struct device_node *np; + struct device_node *np, *gmu_np; np = of_find_matching_node(NULL, msm_gpu_match); if (!np) @@ -1026,6 +1029,11 @@ static int add_gpu_components(struct device *dev, if (of_device_is_available(np) && adreno_has_gpu(np)) drm_of_component_match_add(dev, matchptr, component_compare_of, np); + gmu_np = of_parse_phandle(np, "qcom,gmu", 0); + if (of_device_is_available(gmu_np)) + drm_of_component_match_add(dev, matchptr, component_compare_of, gmu_np); + + of_node_put(gmu_np); of_node_put(np); return 0; @@ -1034,7 +1042,7 @@ static int add_gpu_components(struct device *dev, static int msm_drm_bind(struct device *dev) { return msm_drm_init(dev, - msm_gpu_no_components() ? + msm_gpu_use_separate_drm_dev(NULL) ? &msm_kms_driver : &msm_driver, NULL); @@ -1073,7 +1081,7 @@ int msm_drv_probe(struct device *master_dev, return ret; } - if (!msm_gpu_no_components()) { + if (!msm_gpu_use_separate_drm_dev(NULL)) { ret = add_gpu_components(master_dev, &match); if (ret) return ret; @@ -1093,10 +1101,25 @@ int msm_drv_probe(struct device *master_dev, return 0; } -int msm_gpu_probe(struct platform_device *pdev, - const struct component_ops *ops) +static int msm_gpu_drm_bind(struct device *dev) +{ + return msm_drm_init(dev, &msm_gpu_driver, NULL); +} + +static void msm_gpu_drm_unbind(struct device *dev) +{ + msm_drm_uninit(dev, NULL); +} + +static const struct component_master_ops msm_gpu_drm_ops = { + .bind = msm_gpu_drm_bind, + .unbind = msm_gpu_drm_unbind, +}; + +int msm_gpu_probe(struct platform_device *pdev) { struct msm_drm_private *priv; + struct component_match *match = NULL; int ret; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); @@ -1112,13 +1135,17 @@ int msm_gpu_probe(struct platform_device *pdev, if (ret) return ret; - return msm_drm_init(&pdev->dev, &msm_gpu_driver, ops); + ret = add_gpu_components(&pdev->dev, &match); + if (ret) + return ret; + + return component_master_add_with_match(&pdev->dev, &msm_gpu_drm_ops, + match); } -void msm_gpu_remove(struct platform_device *pdev, - const struct component_ops *ops) +void msm_gpu_remove(struct platform_device *pdev) { - msm_drm_uninit(&pdev->dev, ops); + component_master_del(&pdev->dev, &msm_gpu_drm_ops); } static int __init msm_drm_register(void) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 3787db8770adae..17a036bf292d33 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -540,10 +540,8 @@ extern const struct component_master_ops msm_drm_ops; int msm_kms_pm_prepare(struct device *dev); void msm_kms_pm_complete(struct device *dev); -int msm_gpu_probe(struct platform_device *pdev, - const struct component_ops *ops); -void msm_gpu_remove(struct platform_device *pdev, - const struct component_ops *ops); +int msm_gpu_probe(struct platform_device *pdev); +void msm_gpu_remove(struct platform_device *pdev); int msm_drv_probe(struct device *dev, int (*kms_init)(struct drm_device *dev), struct msm_kms *kms); @@ -551,6 +549,6 @@ void msm_kms_shutdown(struct platform_device *pdev); bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); -bool msm_gpu_no_components(void); +bool msm_gpu_use_separate_drm_dev(struct platform_device *pdev); #endif /* __MSM_DRV_H__ */ diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 3eac4d0f88bc7e..f2177aea2329e4 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -868,6 +868,19 @@ config DRM_PANEL_SAMSUNG_ATNA33XC20 be handled by the DRM_PANEL_SIMPLE driver because its power sequencing is non-standard. +config DRM_PANEL_SAMSUNG_ATNA40CT01 + tristate "Samsung ATNA40CT01 eDP panel" + depends on OF + depends on BACKLIGHT_CLASS_DEVICE + depends on PM + select DRM_DISPLAY_DP_HELPER + select DRM_DISPLAY_HELPER + select DRM_DISPLAY_DP_AUX_BUS + help + DRM panel driver for the Samsung ATNA40CT01 panel. This panel can't + be handled by the DRM_PANEL_SIMPLE driver because its power + sequencing is non-standard. + config DRM_PANEL_SAMSUNG_DB7430 tristate "Samsung DB7430-based DPI panels" depends on OF && SPI && GPIOLIB diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index c2c5cf81711633..7ba77350021682 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -83,6 +83,7 @@ obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01) += panel-samsung-ams581vf01.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08) += panel-samsung-ams639rq08.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20) += panel-samsung-atna33xc20.o +obj-$(CONFIG_DRM_PANEL_SAMSUNG_ATNA40CT01) += panel-samsung-atna40ct01.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) += panel-samsung-db7430.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_LTL106HL02) += panel-samsung-ltl106hl02.o diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c index aa27d6cd932e82..0d8792de7747a7 100644 --- a/drivers/gpu/drm/panel/panel-edp.c +++ b/drivers/gpu/drm/panel/panel-edp.c @@ -1999,6 +1999,7 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('B', 'O', 'E', 0x090d, &delay_200_500_e50, "NT140WHM-N4T"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x09c3, &delay_200_500_e50, "NT116WHM-N21,836X2"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x094b, &delay_200_500_e50, "NT116WHM-N21"), + EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cc9, &delay_200_500_e80, "NE120DRM-N28"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0951, &delay_200_500_e80, "NV116WHM-N47"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x095f, &delay_200_500_e50, "NE135FBM-N41 v8.1"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0964, &delay_200_500_e50, "NV133WUM-N61"), @@ -2024,6 +2025,7 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b43, &delay_200_500_e200, "NV140FHM-T09"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b56, &delay_200_500_e80, "NT140FHM-N47"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b66, &delay_200_500_e80, "NE140WUM-N6G"), + EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b76, &delay_200_500_e80, "Unknown"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b85, &delay_200_500_e50, "NT140WHM-T05"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0c20, &delay_200_500_e80, "NT140FHM-N47"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0c26, &delay_200_500_p2e200, "NV140WUM-T08"), @@ -2031,6 +2033,7 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('B', 'O', 'E', 0x0c93, &delay_200_500_e200, "Unknown"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cb6, &delay_200_500_e200, "NT116WHM-N44"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cc9, &delay_200_500_e50, "NE120DRM-N28"), + EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cea, &delay_200_500_e80, "NV153WUM-N41"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cf2, &delay_200_500_e200, "NV156FHM-N4S"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cf6, &delay_200_500_e200_d100, "NV140WUM-N64"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cfa, &delay_200_500_e50, "NV116WHM-A4D"), @@ -2068,6 +2071,7 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('C', 'M', 'N', 0x1441, &delay_200_500_e80_d50, "N140JCA-ELK"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x144f, &delay_200_500_e80_d50, "N140HGA-EA1"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x1468, &delay_200_500_e80, "N140HGA-EA1"), + EDP_PANEL_ENTRY('C', 'M', 'N', 0x1476, &delay_200_500_e80_d50, "N140JCE-EL1"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x148f, &delay_200_500_e80, "N140HCA-EAC"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x14a8, &delay_200_500_e80, "N140JCA-ELP"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x14c7, &delay_200_500_e80, "N140HCA-EEK"), @@ -2145,6 +2149,9 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('S', 'H', 'P', 0x158f, &delay_200_500_p2e100, "LQ134Z1"), EDP_PANEL_ENTRY('S', 'H', 'P', 0x1593, &delay_200_500_p2e100, "LQ134N1"), + EDP_PANEL_ENTRY('S', 'D', 'C', 0x4187, &delay_200_500_e80_d50, "ATNA40CT01"), + EDP_PANEL_ENTRY('S', 'D', 'C', 0x4213, &delay_200_500_e80_d50, "ATNA40KW02"), + EDP_PANEL_ENTRY('S', 'T', 'A', 0x0004, &delay_200_500_e200, "116KHD024006"), EDP_PANEL_ENTRY('S', 'T', 'A', 0x0009, &delay_200_500_e250, "116QHD024002"), EDP_PANEL_ENTRY('S', 'T', 'A', 0x0100, &delay_100_500_e200, "2081116HHD028001-51D"), diff --git a/drivers/gpu/drm/panel/panel-samsung-atna40ct01.c b/drivers/gpu/drm/panel/panel-samsung-atna40ct01.c new file mode 100644 index 00000000000000..c2acde06b50037 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-samsung-atna40ct01.c @@ -0,0 +1,298 @@ +/* + * DRM driver for Samsung ATNA40CT01 eDP OLED panel + * + * Copyright 2025 xAI (based on panel-samsung-atna33xc20.c) + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct atna40ct01 { + struct drm_panel panel; + struct regulator *supply; + struct gpio_desc *enable_gpio; + struct drm_dp_aux *aux; + bool prepared; + bool enabled; +}; + +static inline struct atna40ct01 *to_atna40ct01(struct drm_panel *panel) +{ + return container_of(panel, struct atna40ct01, panel); +} + +static int atna40ct01_suspend(struct device *dev) +{ + struct atna40ct01 *ctx = dev_get_drvdata(dev); + + if (!ctx->enable_gpio || !ctx->supply) { + dev_err(dev, "Invalid GPIO or regulator in suspend\n"); + return -EINVAL; + } + + gpiod_set_value_cansleep(ctx->enable_gpio, 0); + regulator_disable(ctx->supply); + + return 0; +} + +static int atna40ct01_resume(struct device *dev) +{ + struct atna40ct01 *ctx = dev_get_drvdata(dev); + int ret; + + if (!ctx->enable_gpio || !ctx->supply) { + dev_err(dev, "Invalid GPIO or regulator in resume\n"); + return -EINVAL; + } + + dev_info(dev, "Enabling regulator\n"); + ret = regulator_enable(ctx->supply); + if (ret) { + dev_err(dev, "Failed to enable regulator: %d\n", ret); + return ret; + } + + dev_info(dev, "Waiting 1ms after regulator enable\n"); + msleep(1); + + dev_info(dev, "Setting enable GPIO high\n"); + gpiod_set_value_cansleep(ctx->enable_gpio, 1); + + dev_info(dev, "Waiting 200ms after GPIO enable\n"); + msleep(200); + + return 0; +} + +static int atna40ct01_prepare(struct drm_panel *panel) +{ + struct atna40ct01 *ctx = to_atna40ct01(panel); + int ret; + + if (ctx->prepared) + return 0; + + dev_info(ctx->panel.dev, "Preparing panel\n"); + + ret = pm_runtime_get_sync(panel->dev); + if (ret < 0) { + dev_err(panel->dev, "Failed to resume in prepare: %d\n", ret); + pm_runtime_put_autosuspend(panel->dev); + return ret; + } + + ctx->prepared = true; + return 0; +} + +static int atna40ct01_unprepare(struct drm_panel *panel) +{ + struct atna40ct01 *ctx = to_atna40ct01(panel); + + if (!ctx->prepared) + return 0; + + pm_runtime_put_autosuspend(panel->dev); + + ctx->prepared = false; + return 0; +} + +static int atna40ct01_enable(struct drm_panel *panel) +{ + struct atna40ct01 *ctx = to_atna40ct01(panel); + + if (ctx->enabled) + return 0; + + dev_info(ctx->panel.dev, "Enabling panel\n"); + + if (ctx->panel.backlight) { + backlight_enable(ctx->panel.backlight); + backlight_update_status(ctx->panel.backlight); + } else { + dev_warn(ctx->panel.dev, "No backlight available\n"); + } + + ctx->enabled = true; + return 0; +} + +static int atna40ct01_disable(struct drm_panel *panel) +{ + struct atna40ct01 *ctx = to_atna40ct01(panel); + + if (!ctx->enabled) + return 0; + + if (ctx->panel.backlight) { + backlight_disable(ctx->panel.backlight); + } + + ctx->enabled = false; + return 0; +} + +static int atna40ct01_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct atna40ct01 *ctx = to_atna40ct01(panel); + struct drm_display_mode *mode; + int ret; + + ret = pm_runtime_get_sync(panel->dev); + if (ret < 0) { + dev_err(panel->dev, "Failed to resume in get_modes: %d\n", ret); + return ret; + } + + mode = drm_mode_create(connector->dev); + if (!mode) { + ret = -ENOMEM; + goto put; + } + + mode->clock = 154250; + mode->hdisplay = 1920; + mode->hsync_start = 1920 + 48; + mode->hsync_end = 1920 + 48 + 32; + mode->htotal = 1920 + 48 + 32 + 80; + mode->vdisplay = 1200; + mode->vsync_start = 1200 + 8; + mode->vsync_end = 1200 + 8 + 8; + mode->vtotal = 1200 + 8 + 8 + 20; + mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; + mode->width_mm = 302; + mode->height_mm = 189; + + drm_mode_set_name(mode); + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + drm_mode_probed_add(connector, mode); + + ret = 1; + +put: + pm_runtime_mark_last_busy(panel->dev); + pm_runtime_put_autosuspend(panel->dev); + return ret; +} + +static const struct drm_panel_funcs atna40ct01_funcs = { + .prepare = atna40ct01_prepare, + .unprepare = atna40ct01_unprepare, + .enable = atna40ct01_enable, + .disable = atna40ct01_disable, + .get_modes = atna40ct01_get_modes, +}; + +static int atna40ct01_probe(struct dp_aux_ep_device *aux_ep) +{ + struct device *dev = &aux_ep->dev; + struct atna40ct01 *ctx; + int ret; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + dev_set_drvdata(dev, ctx); // Moved here to fix NULL ctx in resume + + ctx->aux = aux_ep->aux; + + ctx->supply = devm_regulator_get(dev, "power"); + if (IS_ERR(ctx->supply)) { + ret = PTR_ERR(ctx->supply); + dev_err_probe(dev, ret, "Failed to get power supply\n"); + return ret; + } + + ctx->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(ctx->enable_gpio)) { + ret = PTR_ERR(ctx->enable_gpio); + dev_err_probe(dev, ret, "Failed to get enable GPIO\n"); + return ret; + } + + drm_panel_init(&ctx->panel, dev, &atna40ct01_funcs, DRM_MODE_CONNECTOR_eDP); + + pm_runtime_enable(dev); + pm_runtime_set_autosuspend_delay(dev, 2000); + pm_runtime_use_autosuspend(dev); + + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to resume in probe: %d\n", ret); + pm_runtime_put_noidle(dev); + pm_runtime_disable(dev); + return ret; + } + + ret = drm_panel_dp_aux_backlight(&ctx->panel, ctx->aux); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + if (ret) + dev_warn(dev, "Failed to register dp aux backlight: %d\n", ret); + + drm_panel_add(&ctx->panel); + + dev_info(dev, "Probed panel-samsung-atna40ct01\n"); + return 0; +} + +static void atna40ct01_remove(struct dp_aux_ep_device *aux_ep) +{ + struct device *dev = &aux_ep->dev; + struct atna40ct01 *ctx = dev_get_drvdata(dev); + + drm_panel_remove(&ctx->panel); + pm_runtime_disable(dev); +} + +static const struct of_device_id atna40ct01_of_match[] = { + { .compatible = "samsung,atna40ct01" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, atna40ct01_of_match); + +static const struct dev_pm_ops atna40ct01_pm_ops = { + SET_RUNTIME_PM_OPS(atna40ct01_suspend, atna40ct01_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) +}; + +static struct dp_aux_ep_driver atna40ct01_driver = { + .driver = { + .name = "panel-samsung-atna40ct01", + .of_match_table = atna40ct01_of_match, + .pm = &atna40ct01_pm_ops, + }, + .probe = atna40ct01_probe, + .remove = atna40ct01_remove, +}; + +static int __init atna40ct01_init(void) +{ + return dp_aux_dp_driver_register(&atna40ct01_driver); +} +module_init(atna40ct01_init); + +static void __exit atna40ct01_exit(void) +{ + dp_aux_dp_driver_unregister(&atna40ct01_driver); +} +module_exit(atna40ct01_exit); + +MODULE_AUTHOR("xAI"); +MODULE_DESCRIPTION("DRM driver for Samsung ATNA40CT01 eDP OLED panel"); +MODULE_LICENSE("GPL"); diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig index f9bcaeb66385b6..954074915029ea 100644 --- a/drivers/hid/Kconfig +++ b/drivers/hid/Kconfig @@ -1480,6 +1480,8 @@ source "drivers/hid/bpf/Kconfig" source "drivers/hid/i2c-hid/Kconfig" +source "drivers/hid/spi-hid/Kconfig" + source "drivers/hid/intel-ish-hid/Kconfig" source "drivers/hid/amd-sfh-hid/Kconfig" diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile index 23e6e3dd0c56a2..562f19b64d5f94 100644 --- a/drivers/hid/Makefile +++ b/drivers/hid/Makefile @@ -175,6 +175,8 @@ obj-$(CONFIG_USB_KBD) += usbhid/ obj-$(CONFIG_I2C_HID_CORE) += i2c-hid/ +obj-$(CONFIG_SPI_HID_CORE) += spi-hid/ + obj-$(CONFIG_INTEL_ISH_HID) += intel-ish-hid/ obj-$(CONFIG_AMD_SFH_HID) += amd-sfh-hid/ diff --git a/drivers/hid/bpf/progs/hid_bpf_helpers.h b/drivers/hid/bpf/progs/hid_bpf_helpers.h index 0fd8e7d9074275..9fb66282ad329e 100644 --- a/drivers/hid/bpf/progs/hid_bpf_helpers.h +++ b/drivers/hid/bpf/progs/hid_bpf_helpers.h @@ -169,6 +169,7 @@ DEFINE_GUARD(bpf_spin, struct bpf_spin_lock, bpf_spin_lock, bpf_spin_unlock); #define HID_GROUP_STEAM 0x0103 #define HID_GROUP_LOGITECH_27MHZ_DEVICE 0x0104 #define HID_GROUP_VIVALDI 0x0105 +#define HID_GROUP_MSHW0485_IPTS 0x0106 /* include/linux/mod_devicetable.h defines as (~0), but that gives us negative size arrays */ #define HID_VID_ANY 0x0000 diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index cf123347a2af7b..63d0be7e126e30 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -2370,6 +2370,9 @@ int hid_connect(struct hid_device *hdev, unsigned int connect_mask) case BUS_I2C: bus = "I2C"; break; + case BUS_SPI: + bus = "SPI"; + break; case BUS_SDW: bus = "SOUNDWIRE"; break; diff --git a/drivers/hid/spi-hid/Kconfig b/drivers/hid/spi-hid/Kconfig new file mode 100644 index 00000000000000..76a2cd587a3ec9 --- /dev/null +++ b/drivers/hid/spi-hid/Kconfig @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (c) 2021 Microsoft Corporation +# + +menuconfig SPI_HID + tristate "SPI HID support" + default y + depends on SPI + +if SPI_HID + +config SPI_HID_ACPI + tristate "HID over SPI transport layer ACPI driver" + depends on ACPI + select SPI_HID_CORE + help + Say Y here if you use a keyboard, a touchpad, a touchscreen, or any + other HID based devices which are connected to your computer via SPI. + This driver supports ACPI-based systems. + + If unsure, say N. + + This support is also available as a module. If so, the module + will be called spi-hid-acpi. It will also build/depend on the + module spi-hid. + +config SPI_HID_OF + tristate "HID over SPI transport layer Open Firmware driver" + depends on OF + select SPI_HID_CORE + help + Say Y here if you use a keyboard, a touchpad, a touchscreen, or any + other HID based devices which are connected to your computer via SPI. + This driver supports Open Firmware (Device Tree)-based systems. + + If unsure, say N. + + This support is also available as a module. If so, the module + will be called spi-hid-of. It will also build/depend on the + module spi-hid. + +config SPI_HID_CORE + tristate +endif diff --git a/drivers/hid/spi-hid/Makefile b/drivers/hid/spi-hid/Makefile new file mode 100644 index 00000000000000..31192e71edae12 --- /dev/null +++ b/drivers/hid/spi-hid/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for the SPI HID input drivers +# +# Copyright (c) 2021 Microsoft Corporation +# + +obj-$(CONFIG_SPI_HID_CORE) += spi-hid.o +spi-hid-objs = spi-hid-core.o +CFLAGS_spi-hid-core.o := -I$(src) +obj-$(CONFIG_SPI_HID_ACPI) += spi-hid-acpi.o +obj-$(CONFIG_SPI_HID_OF) += spi-hid-of.o diff --git a/drivers/hid/spi-hid/spi-hid-acpi.c b/drivers/hid/spi-hid/spi-hid-acpi.c new file mode 100644 index 00000000000000..15cfc4e6cc2f75 --- /dev/null +++ b/drivers/hid/spi-hid/spi-hid-acpi.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * HID over SPI protocol, ACPI related code + * + * Copyright (c) 2021 Microsoft Corporation + * Copyright (c) 2026 Google LLC + * + * This code was forked out of the HID over SPI core code, which is partially + * based on "HID over I2C protocol implementation: + * + * Copyright (c) 2012 Benjamin Tissoires + * Copyright (c) 2012 Ecole Nationale de l'Aviation Civile, France + * Copyright (c) 2012 Red Hat, Inc + * + * which in turn is partially based on "USB HID support for Linux": + * + * Copyright (c) 1999 Andreas Gal + * Copyright (c) 2000-2005 Vojtech Pavlik + * Copyright (c) 2005 Michael Haboustak for Concept2, Inc + * Copyright (c) 2007-2008 Oliver Neukum + * Copyright (c) 2006-2010 Jiri Kosina + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "spi-hid.h" + +/* Config structure is filled with data from ACPI */ +struct spi_hid_acpi_config { + struct spihid_ops ops; + + struct spi_hid_conf property_conf; + u32 post_power_on_delay_ms; + u32 minimal_reset_delay_ms; + struct acpi_device *adev; +}; + +/* HID SPI Device: 6e2ac436-0fcf41af-a265-b32a220dcfab */ +static guid_t spi_hid_guid = + GUID_INIT(0x6E2AC436, 0x0FCF, 0x41AF, + 0xA2, 0x65, 0xB3, 0x2A, 0x22, 0x0D, 0xCF, 0xAB); + +static int spi_hid_acpi_populate_config(struct spi_hid_acpi_config *conf, + struct acpi_device *adev) +{ + acpi_handle handle = acpi_device_handle(adev); + union acpi_object *obj; + + conf->adev = adev; + + /* Revision 3 for HID over SPI V1, see specification. */ + obj = acpi_evaluate_dsm_typed(handle, &spi_hid_guid, 3, 1, NULL, + ACPI_TYPE_INTEGER); + if (!obj) { + acpi_handle_err(handle, + "Error _DSM call to get HID input report header address failed"); + return -ENODEV; + } + conf->property_conf.input_report_header_address = obj->integer.value; + ACPI_FREE(obj); + + obj = acpi_evaluate_dsm_typed(handle, &spi_hid_guid, 3, 2, NULL, + ACPI_TYPE_INTEGER); + if (!obj) { + acpi_handle_err(handle, + "Error _DSM call to get HID input report body address failed"); + return -ENODEV; + } + conf->property_conf.input_report_body_address = obj->integer.value; + ACPI_FREE(obj); + + obj = acpi_evaluate_dsm_typed(handle, &spi_hid_guid, 3, 3, NULL, + ACPI_TYPE_INTEGER); + if (!obj) { + acpi_handle_err(handle, + "Error _DSM call to get HID output report header address failed"); + return -ENODEV; + } + conf->property_conf.output_report_address = obj->integer.value; + ACPI_FREE(obj); + + obj = acpi_evaluate_dsm_typed(handle, &spi_hid_guid, 3, 4, NULL, + ACPI_TYPE_BUFFER); + if (!obj) { + acpi_handle_err(handle, + "Error _DSM call to get HID read opcode failed"); + return -ENODEV; + } + if (obj->buffer.length == 1) { + conf->property_conf.read_opcode = obj->buffer.pointer[0]; + } else { + acpi_handle_err(handle, + "Error _DSM call to get HID read opcode, too long buffer"); + ACPI_FREE(obj); + return -ENODEV; + } + ACPI_FREE(obj); + + obj = acpi_evaluate_dsm_typed(handle, &spi_hid_guid, 3, 5, NULL, + ACPI_TYPE_BUFFER); + if (!obj) { + acpi_handle_err(handle, + "Error _DSM call to get HID write opcode failed"); + return -ENODEV; + } + if (obj->buffer.length == 1) { + conf->property_conf.write_opcode = obj->buffer.pointer[0]; + } else { + acpi_handle_err(handle, + "Error _DSM call to get HID write opcode, too long buffer"); + ACPI_FREE(obj); + return -ENODEV; + } + ACPI_FREE(obj); + + /* Value not provided in ACPI,*/ + conf->post_power_on_delay_ms = 5; + conf->minimal_reset_delay_ms = 150; + + if (!acpi_has_method(handle, "_RST")) { + acpi_handle_err(handle, "No reset method for acpi handle"); + return -EINVAL; + } + + /* FIXME: not reading hid-over-spi-flags, multi-SPI not supported */ + + return 0; +} + +static int spi_hid_acpi_power_none(struct spihid_ops *ops) +{ + return 0; +} + +static int spi_hid_acpi_power_down(struct spihid_ops *ops) +{ + struct spi_hid_acpi_config *conf = container_of(ops, + struct spi_hid_acpi_config, + ops); + + return acpi_device_set_power(conf->adev, ACPI_STATE_D3); +} + +static int spi_hid_acpi_power_up(struct spihid_ops *ops) +{ + struct spi_hid_acpi_config *conf = container_of(ops, + struct spi_hid_acpi_config, + ops); + int error; + + error = acpi_device_set_power(conf->adev, ACPI_STATE_D0); + if (error) { + dev_err(&conf->adev->dev, "Error could not power up ACPI device: %d.", error); + return error; + } + + if (conf->post_power_on_delay_ms) + msleep(conf->post_power_on_delay_ms); + + return 0; +} + +static int spi_hid_acpi_assert_reset(struct spihid_ops *ops) +{ + return 0; +} + +static int spi_hid_acpi_deassert_reset(struct spihid_ops *ops) +{ + struct spi_hid_acpi_config *conf = container_of(ops, + struct spi_hid_acpi_config, + ops); + + return device_reset(&conf->adev->dev); +} + +static void spi_hid_acpi_sleep_minimal_reset_delay(struct spihid_ops *ops) +{ + struct spi_hid_acpi_config *conf = container_of(ops, + struct spi_hid_acpi_config, + ops); + fsleep(1000 * conf->minimal_reset_delay_ms); +} + +static int spi_hid_acpi_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct acpi_device *adev; + struct spi_hid_acpi_config *config; + int error; + + adev = ACPI_COMPANION(dev); + if (!adev) { + dev_err(dev, "Error could not get ACPI device."); + return -ENODEV; + } + + config = devm_kzalloc(dev, sizeof(struct spi_hid_acpi_config), + GFP_KERNEL); + if (!config) + return -ENOMEM; + + if (acpi_device_power_manageable(adev)) { + config->ops.power_up = spi_hid_acpi_power_up; + config->ops.power_down = spi_hid_acpi_power_down; + } else { + config->ops.power_up = spi_hid_acpi_power_none; + config->ops.power_down = spi_hid_acpi_power_none; + } + config->ops.assert_reset = spi_hid_acpi_assert_reset; + config->ops.deassert_reset = spi_hid_acpi_deassert_reset; + config->ops.sleep_minimal_reset_delay = + spi_hid_acpi_sleep_minimal_reset_delay; + + error = spi_hid_acpi_populate_config(config, adev); + if (error) { + dev_err(dev, "%s: unable to populate config data.", __func__); + return error; + } + + return spi_hid_core_probe(spi, &config->ops, &config->property_conf); +} + +static const struct acpi_device_id spi_hid_acpi_match[] = { + { "ACPI0C51", 0 }, + { "PNP0C51", 0 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, spi_hid_acpi_match); + +static struct spi_driver spi_hid_acpi_driver = { + .driver = { + .name = "spi_hid_acpi", + .owner = THIS_MODULE, + .pm = &spi_hid_core_pm, + .acpi_match_table = spi_hid_acpi_match, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + .dev_groups = spi_hid_groups, + }, + .probe = spi_hid_acpi_probe, + .remove = spi_hid_core_remove, +}; + +module_spi_driver(spi_hid_acpi_driver); + +MODULE_DESCRIPTION("HID over SPI ACPI transport driver"); +MODULE_AUTHOR("Angela Czubak "); +MODULE_LICENSE("GPL"); diff --git a/drivers/hid/spi-hid/spi-hid-core.c b/drivers/hid/spi-hid/spi-hid-core.c new file mode 100644 index 00000000000000..27f25d95ed2808 --- /dev/null +++ b/drivers/hid/spi-hid/spi-hid-core.c @@ -0,0 +1,1521 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * HID over SPI protocol implementation + * + * Copyright (c) 2021 Microsoft Corporation + * Copyright (c) 2026 Google LLC + * + * This code is partly based on "HID over I2C protocol implementation: + * + * Copyright (c) 2012 Benjamin Tissoires + * Copyright (c) 2012 Ecole Nationale de l'Aviation Civile, France + * Copyright (c) 2012 Red Hat, Inc + * + * which in turn is partly based on "USB HID support for Linux": + * + * Copyright (c) 1999 Andreas Gal + * Copyright (c) 2000-2005 Vojtech Pavlik + * Copyright (c) 2005 Michael Haboustak for Concept2, Inc + * Copyright (c) 2007-2008 Oliver Neukum + * Copyright (c) 2006-2010 Jiri Kosina + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "spi-hid.h" +#include "spi-hid-core.h" + +#define CREATE_TRACE_POINTS +#include "spi-hid-trace.h" + +/* Protocol constants */ +#define SPI_HID_READ_APPROVAL_CONSTANT 0xff +#define SPI_HID_INPUT_HEADER_SYNC_BYTE 0x5a +#define SPI_HID_INPUT_HEADER_VERSION 0x03 +#define SPI_HID_SUPPORTED_VERSION 0x0300 + +#define SPI_HID_OUTPUT_REPORT_CONTENT_ID_DESC_REQUEST 0x00 + +#define SPI_HID_MAX_RESET_ATTEMPTS 3 +#define SPI_HID_RESP_TIMEOUT 1000 + +/* Protocol message size constants */ +#define SPI_HID_READ_APPROVAL_LEN 5 +#define SPI_HID_OUTPUT_HEADER_LEN 8 + +/* flags */ +/* + * ready flag indicates that the FW is ready to accept commands and + * requests. The FW becomes ready after sending the report descriptor. + */ +#define SPI_HID_READY 0 +/* + * refresh_in_progress is set to true while the refresh_device worker + * thread is destroying and recreating the hidraw device. When this flag + * is set to true, the ll_close and ll_open functions will not cause + * power state changes. + */ +#define SPI_HID_REFRESH_IN_PROGRESS 1 +/* + * reset_pending indicates that the device is being reset. When this flag + * is set to true, garbage interrupts triggered during reset will be + * dropped and will not cause error handling. + */ +#define SPI_HID_RESET_PENDING 2 +#define SPI_HID_RESET_RESPONSE 3 +#define SPI_HID_CREATE_DEVICE 4 +#define SPI_HID_ERROR 5 + +/* Processed data from input report header */ +struct spi_hid_input_header { + u8 version; + u16 report_length; + u8 last_fragment_flag; + u8 sync_const; +}; + +/* Processed data from an input report */ +struct spi_hid_input_report { + u8 report_type; + u16 content_length; + u8 content_id; + u8 *content; +}; + +/* Data necessary to send an output report */ +struct spi_hid_output_report { + u8 report_type; + u16 content_length; + u8 content_id; + u8 *content; +}; + +static struct hid_ll_driver spi_hid_ll_driver; + +static void spi_hid_populate_read_approvals(const struct spi_hid_conf *conf, + u8 *header_buf, u8 *body_buf) +{ + header_buf[0] = conf->read_opcode; + put_unaligned_be24(conf->input_report_header_address, &header_buf[1]); + header_buf[4] = SPI_HID_READ_APPROVAL_CONSTANT; + + body_buf[0] = conf->read_opcode; + put_unaligned_be24(conf->input_report_body_address, &body_buf[1]); + body_buf[4] = SPI_HID_READ_APPROVAL_CONSTANT; +} + +static void spi_hid_parse_dev_desc(const struct hidspi_dev_descriptor *raw, + struct spi_hid_device_descriptor *desc) +{ + desc->hid_version = le16_to_cpu(raw->bcd_ver); + desc->report_descriptor_length = le16_to_cpu(raw->rep_desc_len); + desc->max_input_length = le16_to_cpu(raw->max_input_len); + desc->max_output_length = le16_to_cpu(raw->max_output_len); + + /* FIXME: multi-fragment not supported, field below not used */ + desc->max_fragment_length = le16_to_cpu(raw->max_frag_len); + + desc->vendor_id = le16_to_cpu(raw->vendor_id); + desc->product_id = le16_to_cpu(raw->product_id); + desc->version_id = le16_to_cpu(raw->version_id); + desc->no_output_report_ack = le16_to_cpu(raw->flags) & BIT(0); +} + +static void spi_hid_populate_input_header(const u8 *buf, + struct spi_hid_input_header *header) +{ + header->version = buf[0] & 0xf; + header->report_length = (get_unaligned_le16(&buf[1]) & 0x3fff) * 4; + header->last_fragment_flag = (buf[2] & 0x40) >> 6; + header->sync_const = buf[3]; +} + +static void spi_hid_populate_input_body(const u8 *buf, + struct input_report_body_header *body) +{ + body->input_report_type = buf[0]; + body->content_len = get_unaligned_le16(&buf[1]); + body->content_id = buf[3]; +} + +static void spi_hid_input_report_prepare(struct spi_hid_input_buf *buf, + struct spi_hid_input_report *report) +{ + struct spi_hid_input_header header; + struct input_report_body_header body; + + spi_hid_populate_input_header(buf->header, &header); + spi_hid_populate_input_body(buf->body, &body); + report->report_type = body.input_report_type; + report->content_length = body.content_len; + report->content_id = body.content_id; + report->content = buf->content; +} + +static void spi_hid_populate_output_header(u8 *buf, + const struct spi_hid_conf *conf, + const struct spi_hid_output_report *report) +{ + buf[0] = conf->write_opcode; + put_unaligned_be24(conf->output_report_address, &buf[1]); + buf[4] = report->report_type; + put_unaligned_le16(report->content_length, &buf[5]); + buf[7] = report->content_id; +} + +static int spi_hid_input_sync(struct spi_hid *shid, void *buf, u16 length, + bool is_header) +{ + int error; + + shid->input_transfer[0].tx_buf = is_header ? + shid->read_approval_header : + shid->read_approval_body; + shid->input_transfer[0].len = SPI_HID_READ_APPROVAL_LEN; + + shid->input_transfer[1].rx_buf = buf; + shid->input_transfer[1].len = length; + + spi_message_init_with_transfers(&shid->input_message, + shid->input_transfer, 2); + + trace_spi_hid_input_sync(shid, shid->input_transfer[0].tx_buf, + shid->input_transfer[0].len, + shid->input_transfer[1].rx_buf, + shid->input_transfer[1].len, 0); + + error = spi_sync(shid->spi, &shid->input_message); + if (error) { + dev_err(&shid->spi->dev, "Error starting sync transfer: %d\n", error); + shid->bus_error_count++; + shid->bus_last_error = error; + return error; + } + + return 0; +} + +static int spi_hid_output(struct spi_hid *shid, const void *buf, u16 length) +{ + int error; + + error = spi_write(shid->spi, buf, length); + + if (error) { + shid->bus_error_count++; + shid->bus_last_error = error; + } + + return error; +} + +static const char *spi_hid_power_mode_string(enum hidspi_power_state power_state) +{ + switch (power_state) { + case HIDSPI_ON: + return "d0"; + case HIDSPI_SLEEP: + return "d2"; + case HIDSPI_OFF: + return "d3"; + default: + return "unknown"; + } +} + +static int spi_hid_suspend(struct spi_hid *shid) +{ + int error; + struct device *dev = &shid->spi->dev; + + guard(mutex)(&shid->power_lock); + if (shid->power_state == HIDSPI_OFF) + return 0; + + if (shid->hid) { + error = hid_driver_suspend(shid->hid, PMSG_SUSPEND); + if (error) { + dev_err(dev, "%s failed to suspend hid driver: %d\n", + __func__, error); + return error; + } + } + + disable_irq(shid->spi->irq); + + if (!device_may_wakeup(dev)) { + set_bit(SPI_HID_RESET_PENDING, &shid->flags); + + shid->ops->assert_reset(shid->ops); + + error = shid->ops->power_down(shid->ops); + if (error) { + dev_err(dev, "%s: could not power down\n", __func__); + shid->regulator_error_count++; + shid->regulator_last_error = error; + /* Undo partial suspend before returning error */ + shid->ops->deassert_reset(shid->ops); + clear_bit(SPI_HID_RESET_PENDING, &shid->flags); + enable_irq(shid->spi->irq); + if (shid->hid) + hid_driver_reset_resume(shid->hid); + return error; + } + + shid->power_state = HIDSPI_OFF; + } + return 0; +} + +static int spi_hid_resume(struct spi_hid *shid) +{ + int error; + struct device *dev = &shid->spi->dev; + + guard(mutex)(&shid->power_lock); + + if (!device_may_wakeup(dev)) { + if (shid->power_state == HIDSPI_OFF) { + shid->ops->assert_reset(shid->ops); + + shid->ops->sleep_minimal_reset_delay(shid->ops); + + error = shid->ops->power_up(shid->ops); + if (error) { + dev_err(dev, "%s: could not power up\n", __func__); + shid->regulator_error_count++; + shid->regulator_last_error = error; + return error; + } + shid->power_state = HIDSPI_ON; + shid->ops->deassert_reset(shid->ops); + } + } + + enable_irq(shid->spi->irq); + + if (shid->hid) { + error = hid_driver_reset_resume(shid->hid); + if (error) { + dev_err(dev, "%s: failed to reset resume hid driver: %d\n", + __func__, error); + /* Undo partial resume before returning error */ + disable_irq(shid->spi->irq); + if (!device_may_wakeup(dev)) { + set_bit(SPI_HID_RESET_PENDING, &shid->flags); + shid->ops->assert_reset(shid->ops); + shid->ops->power_down(shid->ops); + shid->power_state = HIDSPI_OFF; + } + return error; + } + } + return 0; +} + +static void spi_hid_stop_hid(struct spi_hid *shid) +{ + struct hid_device *hid; + + scoped_guard(mutex, &shid->io_lock) { + hid = shid->hid; + shid->hid = NULL; + clear_bit(SPI_HID_READY, &shid->flags); + } + + if (hid) + hid_destroy_device(hid); +} + +static void spi_hid_error_handler(struct spi_hid *shid) +{ + struct device *dev = &shid->spi->dev; + int error; + + trace_spi_hid_error_handler(shid); + + guard(mutex)(&shid->power_lock); + if (shid->power_state == HIDSPI_OFF) + return; + + guard(disable_irq)(&shid->spi->irq); + + if (shid->reset_attempts++ >= SPI_HID_MAX_RESET_ATTEMPTS) { + dev_err(dev, "unresponsive device, aborting\n"); + spi_hid_stop_hid(shid); + shid->ops->assert_reset(shid->ops); + error = shid->ops->power_down(shid->ops); + if (error) { + dev_err(dev, "failed to disable regulator\n"); + shid->regulator_error_count++; + shid->regulator_last_error = error; + } + return; + } + + clear_bit(SPI_HID_READY, &shid->flags); + set_bit(SPI_HID_RESET_PENDING, &shid->flags); + + shid->ops->assert_reset(shid->ops); + + shid->power_state = HIDSPI_OFF; + + /* + * We want to cancel pending reset work as the device is being reset + * to recover from an error. cancel_work_sync will put us in a deadlock + * because this function is scheduled in 'reset_work' and we should + * avoid waiting for itself. + */ + cancel_work(&shid->reset_work); + + shid->ops->sleep_minimal_reset_delay(shid->ops); + + shid->power_state = HIDSPI_ON; + + shid->ops->deassert_reset(shid->ops); +} + +static int __spi_hid_send_output_report(struct spi_hid *shid, + struct spi_hid_output_report *report) +{ + struct spi_hid_output_buf *buf = shid->output; + struct device *dev = &shid->spi->dev; + u16 report_length; + u16 padded_length; + u8 padding; + int error; + + if (report->content_length > shid->desc.max_output_length || + report->content_length > shid->bufsize) { + dev_err(dev, "Output report too big, content_length 0x%x\n", + report->content_length); + return -E2BIG; + } + + guard(mutex)(&shid->io_lock); + spi_hid_populate_output_header(buf->header, shid->conf, report); + + if (report->content_length) + memcpy(&buf->content, report->content, report->content_length); + + report_length = sizeof(buf->header) + report->content_length; + padded_length = round_up(report_length, 4); + padding = padded_length - report_length; + memset(&buf->content[report->content_length], 0, padding); + + error = spi_hid_output(shid, buf, padded_length); + if (error) + dev_err(dev, "Failed output transfer: %d\n", error); + + return error; +} + +static int spi_hid_send_output_report(struct spi_hid *shid, + struct spi_hid_output_report *report) +{ + guard(mutex)(&shid->output_lock); + return __spi_hid_send_output_report(shid, report); +} + +static int spi_hid_sync_request(struct spi_hid *shid, + struct spi_hid_output_report *report) +{ + struct device *dev = &shid->spi->dev; + int error; + + guard(mutex)(&shid->output_lock); + + reinit_completion(&shid->output_done); + + error = __spi_hid_send_output_report(shid, report); + if (error) + return error; + + error = wait_for_completion_interruptible_timeout(&shid->output_done, + msecs_to_jiffies(SPI_HID_RESP_TIMEOUT)); + if (error == 0) { + dev_err(dev, "Response timed out\n"); + return -ETIMEDOUT; + } + if (error < 0) + return error; + + return 0; +} + +/* + * Handle the reset response from the FW by sending a request for the device + * descriptor. + */ +static void spi_hid_reset_response(struct spi_hid *shid) +{ + struct device *dev = &shid->spi->dev; + struct spi_hid_output_report report = { + .report_type = DEVICE_DESCRIPTOR, + .content_length = 0x0, + .content_id = SPI_HID_OUTPUT_REPORT_CONTENT_ID_DESC_REQUEST, + .content = NULL, + }; + int error; + + trace_spi_hid_reset_response(shid); + + if (test_bit(SPI_HID_READY, &shid->flags)) { + dev_err(dev, "Spontaneous FW reset!\n"); + clear_bit(SPI_HID_READY, &shid->flags); + shid->dir_count++; + } + + if (shid->power_state == HIDSPI_OFF) + return; + + error = spi_hid_sync_request(shid, &report); + if (error) { + dev_WARN_ONCE(dev, true, + "Failed to send device descriptor request: %d\n", error); + set_bit(SPI_HID_ERROR, &shid->flags); + schedule_work(&shid->reset_work); + } +} + +static int spi_hid_input_report_handler(struct spi_hid *shid, + struct spi_hid_input_buf *buf) +{ + struct device *dev = &shid->spi->dev; + struct spi_hid_input_report r; + int error = 0; + + guard(mutex)(&shid->io_lock); + trace_spi_hid_input_report_handler(shid); + + if (!test_bit(SPI_HID_READY, &shid->flags) || + test_bit(SPI_HID_REFRESH_IN_PROGRESS, &shid->flags) || !shid->hid) { + dev_err(dev, "HID not ready\n"); + return 0; + } + + spi_hid_input_report_prepare(buf, &r); + + error = hid_input_report(shid->hid, HID_INPUT_REPORT, + r.content - 1, r.content_length + 1, 1); + + if (error == -ENODEV || error == -EBUSY) { + dev_err(dev, "ignoring report --> %d\n", error); + return 0; + } else if (error) { + dev_err(dev, "Bad input report: %d\n", error); + } + + return error; +} + +static void spi_hid_response_handler(struct spi_hid *shid, + struct input_report_body_header *body) +{ + trace_spi_hid_response_handler(shid); + + shid->response_length = body->content_len; + /* completion_done returns 0 if there are waiters, otherwise 1 */ + if (completion_done(&shid->output_done)) { + dev_err(&shid->spi->dev, "Unexpected response report\n"); + } else { + if (body->input_report_type == REPORT_DESCRIPTOR_RESPONSE || + body->input_report_type == GET_FEATURE_RESPONSE) { + memcpy(shid->response->body, shid->input->body, + sizeof(shid->input->body)); + memcpy(shid->response->content, shid->input->content, + body->content_len); + } + complete(&shid->output_done); + } +} + +/* + * This function returns the length of the report descriptor, or a negative + * error code if something went wrong. + */ +static int spi_hid_report_descriptor_request(struct spi_hid *shid) +{ + struct device *dev = &shid->spi->dev; + struct spi_hid_output_report report = { + .report_type = REPORT_DESCRIPTOR, + .content_length = 0, + .content_id = SPI_HID_OUTPUT_REPORT_CONTENT_ID_DESC_REQUEST, + .content = NULL, + }; + int ret; + + ret = spi_hid_sync_request(shid, &report); + if (ret) { + dev_err(dev, + "Expected report descriptor not received: %d\n", ret); + set_bit(SPI_HID_ERROR, &shid->flags); + schedule_work(&shid->reset_work); + return ret; + } + + ret = shid->response_length; + if (ret != shid->desc.report_descriptor_length) { + ret = min_t(unsigned int, ret, shid->desc.report_descriptor_length); + dev_err(dev, "Received report descriptor length doesn't match device descriptor field, using min of the two: %d\n", + ret); + } + + return ret; +} + +static int spi_hid_create_device(struct spi_hid *shid) +{ + struct hid_device *hid; + struct device *dev = &shid->spi->dev; + int error; + + trace_spi_hid_create_device(shid); + + hid = hid_allocate_device(); + error = PTR_ERR_OR_ZERO(hid); + if (error) { + dev_err(dev, "Failed to allocate hid device: %d\n", error); + return error; + } + + hid->driver_data = shid->spi; + hid->ll_driver = &spi_hid_ll_driver; + hid->dev.parent = &shid->spi->dev; + hid->bus = BUS_SPI; + hid->version = shid->desc.hid_version; + hid->vendor = shid->desc.vendor_id; + hid->product = shid->desc.product_id; + + snprintf(hid->name, sizeof(hid->name), "spi %04X:%04X", + hid->vendor, hid->product); + strscpy(hid->phys, dev_name(&shid->spi->dev), sizeof(hid->phys)); + + scoped_guard(mutex, &shid->io_lock) { + shid->hid = hid; + } + + error = hid_add_device(hid); + if (error) { + dev_err(dev, "Failed to add hid device: %d\n", error); + /* + * We likely got here because report descriptor request timed + * out. Let's disconnect and destroy the hid_device structure. + */ + spi_hid_stop_hid(shid); + return error; + } + + return 0; +} + +static void spi_hid_refresh_device(struct spi_hid *shid) +{ + struct device *dev = &shid->spi->dev; + u32 new_crc32 = 0; + int error = 0; + + trace_spi_hid_refresh_device(shid); + + error = spi_hid_report_descriptor_request(shid); + if (error < 0) { + dev_err(dev, + "%s: failed report descriptor request: %d\n", + __func__, error); + return; + } + new_crc32 = crc32_le(0, (unsigned char const *)shid->response->content, + (size_t)error); + + /* Same report descriptor, so no need to create a new hid device. */ + if (new_crc32 == shid->report_descriptor_crc32) { + set_bit(SPI_HID_READY, &shid->flags); + return; + } + + shid->report_descriptor_crc32 = new_crc32; + + set_bit(SPI_HID_REFRESH_IN_PROGRESS, &shid->flags); + + spi_hid_stop_hid(shid); + + error = spi_hid_create_device(shid); + if (error) { + dev_err(dev, "%s: Failed to create hid device: %d\n", __func__, error); + return; + } + + clear_bit(SPI_HID_REFRESH_IN_PROGRESS, &shid->flags); +} + +static void spi_hid_reset_work(struct work_struct *work) +{ + struct spi_hid *shid = + container_of(work, struct spi_hid, reset_work); + struct device *dev = &shid->spi->dev; + int error = 0; + bool resched = false; + + if (test_and_clear_bit(SPI_HID_RESET_RESPONSE, &shid->flags)) { + spi_hid_reset_response(shid); + resched = true; + } else if (test_and_clear_bit(SPI_HID_CREATE_DEVICE, &shid->flags)) { + guard(mutex)(&shid->power_lock); + if (shid->power_state != HIDSPI_OFF) { + if (!shid->hid) { + error = spi_hid_create_device(shid); + if (error) { + dev_err(dev, "%s: Failed to create hid device: %d\n", + __func__, error); + } + } else { + spi_hid_refresh_device(shid); + } + } else { + dev_err(dev, "%s: Powered off, returning\n", __func__); + } + resched = true; + } else if (test_and_clear_bit(SPI_HID_ERROR, &shid->flags)) { + spi_hid_error_handler(shid); + } + + /* + * If other flags are still pending, safely reschedule ourselves + * to process them in the next workqueue cycle. + */ + if (resched && (shid->flags & (BIT(SPI_HID_RESET_RESPONSE) | + BIT(SPI_HID_CREATE_DEVICE) | + BIT(SPI_HID_ERROR)))) { + schedule_work(&shid->reset_work); + } +} + +static int spi_hid_process_input_report(struct spi_hid *shid, + struct spi_hid_input_buf *buf) +{ + struct spi_hid_input_header header; + struct input_report_body_header body; + struct device *dev = &shid->spi->dev; + struct hidspi_dev_descriptor *raw; + + trace_spi_hid_process_input_report(shid); + + spi_hid_populate_input_header(buf->header, &header); + spi_hid_populate_input_body(buf->body, &body); + + if (HIDSPI_INPUT_BODY_SIZE(body.content_len) > header.report_length) { + dev_err(dev, "Bad body length %zu > %u\n", HIDSPI_INPUT_BODY_SIZE(body.content_len), + header.report_length); + return -EPROTO; + } + + switch (body.input_report_type) { + case DATA: + return spi_hid_input_report_handler(shid, buf); + case RESET_RESPONSE: + clear_bit(SPI_HID_RESET_PENDING, &shid->flags); + set_bit(SPI_HID_RESET_RESPONSE, &shid->flags); + schedule_work(&shid->reset_work); + break; + case DEVICE_DESCRIPTOR_RESPONSE: + /* Mark the completion done to avoid timeout */ + spi_hid_response_handler(shid, &body); + + /* Reset attempts at every device descriptor fetch */ + shid->reset_attempts = 0; + raw = (struct hidspi_dev_descriptor *)buf->content; + + /* Validate device descriptor length before parsing */ + if (body.content_len != HIDSPI_DEVICE_DESCRIPTOR_SIZE) { + dev_err(dev, "Invalid content length %d, expected %zu\n", + body.content_len, + HIDSPI_DEVICE_DESCRIPTOR_SIZE); + return -EPROTO; + } + + if (le16_to_cpu(raw->dev_desc_len) != + HIDSPI_DEVICE_DESCRIPTOR_SIZE) { + dev_err(dev, + "Invalid wDeviceDescLength %d, expected %zu\n", + le16_to_cpu(raw->dev_desc_len), + HIDSPI_DEVICE_DESCRIPTOR_SIZE); + return -EPROTO; + } + + spi_hid_parse_dev_desc(raw, &shid->desc); + + if (shid->desc.hid_version != SPI_HID_SUPPORTED_VERSION) { + dev_err(dev, + "Unsupported device descriptor version %4x\n", + shid->desc.hid_version); + return -EPROTONOSUPPORT; + } + + set_bit(SPI_HID_CREATE_DEVICE, &shid->flags); + schedule_work(&shid->reset_work); + + break; + case OUTPUT_REPORT_RESPONSE: + if (shid->desc.no_output_report_ack) { + dev_err(dev, "Unexpected output report response\n"); + break; + } + fallthrough; + case GET_FEATURE_RESPONSE: + case SET_FEATURE_RESPONSE: + case REPORT_DESCRIPTOR_RESPONSE: + spi_hid_response_handler(shid, &body); + break; + /* + * FIXME: sending GET_INPUT and COMMAND reports not supported, thus + * throw away responses to those, they should never come. + */ + case GET_INPUT_REPORT_RESPONSE: + case COMMAND_RESPONSE: + dev_err(dev, "Not a supported report type: 0x%x\n", + body.input_report_type); + break; + default: + dev_err(dev, "Unknown input report: 0x%x\n", body.input_report_type); + return -EPROTO; + } + + return 0; +} + +static int spi_hid_bus_validate_header(struct spi_hid *shid, + struct spi_hid_input_header *header) +{ + struct device *dev = &shid->spi->dev; + + if (header->version != SPI_HID_INPUT_HEADER_VERSION) { + dev_err(dev, "Unknown input report version (v 0x%x)\n", + header->version); + return -EINVAL; + } + + if (shid->desc.max_input_length != 0 && + header->report_length > shid->desc.max_input_length) { + dev_err(dev, "Input report body size %u > max expected of %u\n", + header->report_length, shid->desc.max_input_length); + return -EMSGSIZE; + } + + if (header->last_fragment_flag != 1) { + dev_err(dev, "Multi-fragment reports not supported\n"); + return -EOPNOTSUPP; + } + + if (header->sync_const != SPI_HID_INPUT_HEADER_SYNC_BYTE) { + dev_err(dev, "Invalid input report sync constant (0x%x)\n", + header->sync_const); + return -EINVAL; + } + + return 0; +} + +static int spi_hid_get_request(struct spi_hid *shid, u8 content_id) +{ + struct device *dev = &shid->spi->dev; + struct spi_hid_output_report report = { + .report_type = GET_FEATURE, + .content_length = 0, + .content_id = content_id, + .content = NULL, + }; + int error; + + error = spi_hid_sync_request(shid, &report); + if (error) { + dev_err(dev, + "Expected get request response not received! Error %d\n", + error); + set_bit(SPI_HID_ERROR, &shid->flags); + schedule_work(&shid->reset_work); + return error; + } + + return 0; +} + +static int spi_hid_set_request(struct spi_hid *shid, u8 *arg_buf, u16 arg_len, + u8 content_id) +{ + struct spi_hid_output_report report = { + .report_type = SET_FEATURE, + .content_length = arg_len, + .content_id = content_id, + .content = arg_buf, + }; + + return spi_hid_sync_request(shid, &report); +} + +static irqreturn_t spi_hid_dev_irq(int irq, void *_shid) +{ + struct spi_hid *shid = _shid; + struct device *dev = &shid->spi->dev; + struct spi_hid_input_header header; + int error = 0; + + trace_spi_hid_dev_irq(shid, irq); + trace_spi_hid_header_transfer(shid); + + scoped_guard(mutex, &shid->io_lock) { + if (shid->power_state == HIDSPI_OFF) { + dev_warn(dev, "Device is off, ignoring interrupt\n"); + goto out; + } + + error = spi_hid_input_sync(shid, shid->input->header, + sizeof(shid->input->header), true); + if (error) { + dev_err(dev, "Failed to transfer header: %d\n", error); + goto err; + } + + trace_spi_hid_input_header_complete(shid, + shid->input_transfer[0].tx_buf, + shid->input_transfer[0].len, + shid->input_transfer[1].rx_buf, + shid->input_transfer[1].len, + shid->input_message.status); + + if (shid->input_message.status < 0) { + dev_warn(dev, "Error reading header: %d\n", + shid->input_message.status); + shid->bus_error_count++; + shid->bus_last_error = shid->input_message.status; + goto err; + } + + spi_hid_populate_input_header(shid->input->header, &header); + + error = spi_hid_bus_validate_header(shid, &header); + if (error) { + if (!test_bit(SPI_HID_RESET_PENDING, &shid->flags)) { + dev_err(dev, "Failed to validate header: %d\n", error); + print_hex_dump(KERN_ERR, "spi_hid: header buffer: ", + DUMP_PREFIX_NONE, 16, 1, shid->input->header, + sizeof(shid->input->header), false); + shid->bus_error_count++; + shid->bus_last_error = error; + goto err; + } + goto out; + } + + error = spi_hid_input_sync(shid, shid->input->body, header.report_length, + false); + if (error) { + dev_err(dev, "Failed to transfer body: %d\n", error); + goto err; + } + + if (shid->power_state == HIDSPI_OFF) { + dev_warn(dev, "Device is off after body was received\n"); + goto out; + } + + trace_spi_hid_input_body_complete(shid, shid->input_transfer[0].tx_buf, + shid->input_transfer[0].len, + shid->input_transfer[1].rx_buf, + shid->input_transfer[1].len, + shid->input_message.status); + + if (shid->input_message.status < 0) { + dev_warn(dev, "Error reading body: %d\n", + shid->input_message.status); + shid->bus_error_count++; + shid->bus_last_error = shid->input_message.status; + goto err; + } + } + + error = spi_hid_process_input_report(shid, shid->input); + if (error) { + dev_err(dev, "Failed to process input report: %d\n", error); + goto err; + } + +out: + return IRQ_HANDLED; + +err: + set_bit(SPI_HID_ERROR, &shid->flags); + schedule_work(&shid->reset_work); + return IRQ_HANDLED; +} + +static int spi_hid_alloc_buffers(struct spi_hid *shid, size_t report_size) +{ + struct device *dev = &shid->spi->dev; + int inbufsize = round_up(sizeof(shid->input->header) + + sizeof(shid->input->body) + report_size, 4); + int outbufsize = round_up(sizeof(shid->output->header) + report_size, 4); + void *tmp; + + tmp = devm_krealloc(dev, shid->output, outbufsize, GFP_KERNEL | __GFP_ZERO); + if (!tmp) + return -ENOMEM; + shid->output = tmp; + + tmp = devm_krealloc(dev, shid->input, inbufsize, GFP_KERNEL | __GFP_ZERO); + if (!tmp) + return -ENOMEM; + shid->input = tmp; + + tmp = devm_krealloc(dev, shid->response, inbufsize, GFP_KERNEL | __GFP_ZERO); + if (!tmp) + return -ENOMEM; + shid->response = tmp; + + if (!shid->output || !shid->input || !shid->response) + return -ENOMEM; + + shid->bufsize = report_size; + + return 0; +} + +static int spi_hid_get_report_length(struct hid_report *report) +{ + return DIV_ROUND_UP(report->size, 8) + + report->device->report_enum[report->type].numbered + 2; +} + +/* + * Traverse the supplied list of reports and find the longest + */ +static void spi_hid_find_max_report(struct hid_device *hid, u32 type, + u16 *max) +{ + struct hid_report *report; + u16 size; + + /* + * We should not rely on wMaxInputLength, as some devices may set it to + * a wrong length. + */ + list_for_each_entry(report, &hid->report_enum[type].report_list, list) { + size = spi_hid_get_report_length(report); + if (*max < size) + *max = size; + } +} + +/* hid_ll_driver interface functions */ + +static int spi_hid_ll_start(struct hid_device *hid) +{ + struct spi_device *spi = hid->driver_data; + struct spi_hid *shid = spi_get_drvdata(spi); + int error = 0; + u16 bufsize = 0; + + spi_hid_find_max_report(hid, HID_INPUT_REPORT, &bufsize); + spi_hid_find_max_report(hid, HID_OUTPUT_REPORT, &bufsize); + spi_hid_find_max_report(hid, HID_FEATURE_REPORT, &bufsize); + + if (bufsize < HID_MIN_BUFFER_SIZE) { + dev_err(&spi->dev, + "HID_MIN_BUFFER_SIZE > max_input_length (%d)\n", + bufsize); + return -EINVAL; + } + + if (bufsize > shid->bufsize) { + guard(disable_irq)(&shid->spi->irq); + + error = spi_hid_alloc_buffers(shid, bufsize); + if (error) + return error; + } + + return 0; +} + +static void spi_hid_ll_stop(struct hid_device *hid) +{ + hid->claimed = 0; +} + +static int spi_hid_ll_open(struct hid_device *hid) +{ + struct spi_device *spi = hid->driver_data; + struct spi_hid *shid = spi_get_drvdata(spi); + + set_bit(SPI_HID_READY, &shid->flags); + return 0; +} + +static void spi_hid_ll_close(struct hid_device *hid) +{ + struct spi_device *spi = hid->driver_data; + struct spi_hid *shid = spi_get_drvdata(spi); + + clear_bit(SPI_HID_READY, &shid->flags); + shid->reset_attempts = 0; +} + +static int spi_hid_ll_power(struct hid_device *hid, int level) +{ + struct spi_device *spi = hid->driver_data; + struct spi_hid *shid = spi_get_drvdata(spi); + int error = 0; + + guard(mutex)(&shid->output_lock); + if (!shid->hid) + error = -ENODEV; + + return error; +} + +static int spi_hid_ll_parse(struct hid_device *hid) +{ + struct spi_device *spi = hid->driver_data; + struct spi_hid *shid = spi_get_drvdata(spi); + struct device *dev = &spi->dev; + unsigned int rsize = shid->desc.report_descriptor_length; + int error, len; + + if (rsize > HID_MAX_DESCRIPTOR_SIZE) { + dev_err(dev, + "Report descriptor size %d is greater than HID_MAX_DESCRIPTOR_SIZE %d\n", + rsize, HID_MAX_DESCRIPTOR_SIZE); + return -EINVAL; + } + + if (rsize > shid->bufsize) { + error = spi_hid_alloc_buffers(shid, rsize); + if (error) + return error; + } + + len = spi_hid_report_descriptor_request(shid); + if (len < 0) { + dev_err(dev, "Report descriptor request failed, %d\n", len); + return len; + } + + /* + * FIXME: below call returning 0 doesn't mean that the report descriptor + * is good. We might be caching a crc32 of a corrupted r. d. or who + * knows what the FW sent. Need to have a feedback loop about r. d. + * being ok and only then cache it. + */ + error = hid_parse_report(hid, (u8 *)shid->response->content, len); + if (error) { + dev_err(dev, "failed parsing report: %d\n", error); + return error; + } + shid->report_descriptor_crc32 = crc32_le(0, + (unsigned char const *)shid->response->content, + len); + + return 0; +} + +static int spi_hid_ll_raw_request(struct hid_device *hid, + unsigned char reportnum, __u8 *buf, + size_t len, unsigned char rtype, int reqtype) +{ + struct spi_device *spi = hid->driver_data; + struct spi_hid *shid = spi_get_drvdata(spi); + struct device *dev = &spi->dev; + int ret; + + switch (reqtype) { + case HID_REQ_SET_REPORT: + if (buf[0] != reportnum) { + dev_err(dev, "report id mismatch\n"); + return -EINVAL; + } + + ret = spi_hid_set_request(shid, &buf[1], len - 1, + reportnum); + if (ret) { + dev_err(dev, "failed to set report\n"); + return ret; + } + + ret = len; + break; + case HID_REQ_GET_REPORT: + ret = spi_hid_get_request(shid, reportnum); + if (ret) { + dev_err(dev, "failed to get report\n"); + return ret; + } + + ret = min_t(size_t, len, + (shid->response->body[1] | (shid->response->body[2] << 8)) + 1); + buf[0] = shid->response->body[3]; + memcpy(&buf[1], &shid->response->content, ret); + break; + default: + dev_err(dev, "invalid request type\n"); + return -EIO; + } + + return ret; +} + +static int spi_hid_ll_output_report(struct hid_device *hid, __u8 *buf, + size_t len) +{ + struct spi_device *spi = hid->driver_data; + struct spi_hid *shid = spi_get_drvdata(spi); + struct device *dev = &spi->dev; + struct spi_hid_output_report report = { + .report_type = OUTPUT_REPORT, + .content_length = len - 1, + .content_id = buf[0], + .content = &buf[1], + }; + int error; + + if (!test_bit(SPI_HID_READY, &shid->flags)) { + dev_err(dev, "%s called in unready state\n", __func__); + return -ENODEV; + } + + if (shid->desc.no_output_report_ack) { + scoped_guard(mutex, &shid->output_lock) { + error = spi_hid_send_output_report(shid, &report); + } + } else { + error = spi_hid_sync_request(shid, &report); + } + + if (error) { + dev_err(dev, "failed to send output report\n"); + return error; + } + + return len; +} + +static struct hid_ll_driver spi_hid_ll_driver = { + .start = spi_hid_ll_start, + .stop = spi_hid_ll_stop, + .open = spi_hid_ll_open, + .close = spi_hid_ll_close, + .power = spi_hid_ll_power, + .parse = spi_hid_ll_parse, + .output_report = spi_hid_ll_output_report, + .raw_request = spi_hid_ll_raw_request, +}; + +static ssize_t bus_error_count_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct spi_hid *shid = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%u (%d)\n", + shid->bus_error_count, shid->bus_last_error); +} +static DEVICE_ATTR_RO(bus_error_count); + +static ssize_t regulator_error_count_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct spi_hid *shid = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%u (%d)\n", + shid->regulator_error_count, + shid->regulator_last_error); +} +static DEVICE_ATTR_RO(regulator_error_count); + +static ssize_t device_initiated_reset_count_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct spi_hid *shid = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%u\n", shid->dir_count); +} +static DEVICE_ATTR_RO(device_initiated_reset_count); + +static struct attribute *spi_hid_attrs[] = { + &dev_attr_bus_error_count.attr, + &dev_attr_regulator_error_count.attr, + &dev_attr_device_initiated_reset_count.attr, + NULL /* Terminator */ +}; + +static const struct attribute_group spi_hid_group = { + .attrs = spi_hid_attrs, +}; + +const struct attribute_group *spi_hid_groups[] = { + &spi_hid_group, + NULL +}; +EXPORT_SYMBOL_GPL(spi_hid_groups); + +/* + * At the end of probe we initialize the device: + * 0) assert reset, bias the interrupt line + * 1) sleep minimal reset delay + * 2) power up the device + * 3) deassert reset (high) + * After this we expect an IRQ with a reset response. + */ +static int spi_hid_dev_init(struct spi_hid *shid) +{ + struct spi_device *spi = shid->spi; + struct device *dev = &spi->dev; + int error; + + shid->ops->assert_reset(shid->ops); + + shid->ops->sleep_minimal_reset_delay(shid->ops); + + error = shid->ops->power_up(shid->ops); + if (error) { + dev_err(dev, "%s: could not power up\n", __func__); + shid->regulator_error_count++; + shid->regulator_last_error = error; + return error; + } + + shid->ops->deassert_reset(shid->ops); + + enable_irq(spi->irq); + + return 0; +} + +static void spi_hid_panel_follower_work(struct work_struct *work) +{ + struct spi_hid *shid = container_of(work, struct spi_hid, + panel_follower_work); + int error; + + if (!shid->desc.hid_version) + error = spi_hid_dev_init(shid); + else + error = spi_hid_resume(shid); + if (error) + dev_warn(&shid->spi->dev, "Power on failed: %d\n", error); + else + WRITE_ONCE(shid->panel_follower_work_finished, true); +} + +static int spi_hid_panel_follower_resume(struct drm_panel_follower *follower) +{ + struct spi_hid *shid = container_of(follower, struct spi_hid, panel_follower); + + /* + * Powering on a touchscreen can be a slow process. Queue the work to + * the system workqueue so we don't block the panel's power up. + */ + WRITE_ONCE(shid->panel_follower_work_finished, false); + schedule_work(&shid->panel_follower_work); + + return 0; +} + +static int spi_hid_panel_follower_suspend(struct drm_panel_follower *follower) +{ + struct spi_hid *shid = container_of(follower, struct spi_hid, panel_follower); + + cancel_work_sync(&shid->panel_follower_work); + + if (!READ_ONCE(shid->panel_follower_work_finished)) + return 0; + + return spi_hid_suspend(shid); +} + +static const struct drm_panel_follower_funcs + spi_hid_panel_follower_prepare_funcs = { + .panel_prepared = spi_hid_panel_follower_resume, + .panel_unpreparing = spi_hid_panel_follower_suspend, +}; + +static int spi_hid_register_panel_follower(struct spi_hid *shid) +{ + struct device *dev = &shid->spi->dev; + + shid->panel_follower.funcs = &spi_hid_panel_follower_prepare_funcs; + + /* + * If we're not in control of our own power up/power down then we can't + * do the logic to manage wakeups. Give a warning if a user thought + * that was possible then force the capability off. + */ + if (device_can_wakeup(dev)) { + dev_warn(dev, "Can't wakeup if following panel\n"); + device_set_wakeup_capable(dev, false); + } + + return drm_panel_add_follower(dev, &shid->panel_follower); +} + +int spi_hid_core_probe(struct spi_device *spi, struct spihid_ops *ops, + struct spi_hid_conf *conf) +{ + struct device *dev = &spi->dev; + struct spi_hid *shid; + int error; + + if (spi->irq <= 0) + return dev_err_probe(dev, spi->irq ?: -EINVAL, "Missing IRQ\n"); + + shid = devm_kzalloc(dev, sizeof(*shid), GFP_KERNEL); + if (!shid) + return -ENOMEM; + + shid->spi = spi; + shid->power_state = HIDSPI_ON; + shid->ops = ops; + shid->conf = conf; + set_bit(SPI_HID_RESET_PENDING, &shid->flags); + shid->is_panel_follower = drm_is_panel_follower(&spi->dev); + + spi_set_drvdata(spi, shid); + + /* Using now populated conf let's pre-calculate the read approvals */ + spi_hid_populate_read_approvals(shid->conf, shid->read_approval_header, + shid->read_approval_body); + + mutex_init(&shid->output_lock); + mutex_init(&shid->power_lock); + mutex_init(&shid->io_lock); + init_completion(&shid->output_done); + + INIT_WORK(&shid->reset_work, spi_hid_reset_work); + INIT_WORK(&shid->panel_follower_work, spi_hid_panel_follower_work); + + /* + * We need to allocate the buffer without knowing the maximum + * size of the reports. Let's use SZ_2K, then we do the + * real computation later. + */ + error = spi_hid_alloc_buffers(shid, SZ_2K); + if (error) + return error; + + error = devm_request_threaded_irq(dev, spi->irq, NULL, spi_hid_dev_irq, + IRQF_ONESHOT | IRQF_NO_AUTOEN, dev_name(&spi->dev), shid); + if (error) { + dev_err(dev, "%s: unable to request threaded IRQ\n", __func__); + return error; + } + if (device_may_wakeup(dev)) { + error = dev_pm_set_wake_irq(dev, spi->irq); + if (error) { + dev_err(dev, "%s: failed to set wake IRQ\n", __func__); + return error; + } + } + + if (shid->is_panel_follower) { + error = spi_hid_register_panel_follower(shid); + if (error) { + dev_err_probe(dev, error, + "Failed to register panel follower"); + goto err_wake_irq; + } + } else { + error = spi_hid_dev_init(shid); + if (error) + goto err_wake_irq; + } + + dev_dbg(dev, "%s: d3 -> %s\n", __func__, + spi_hid_power_mode_string(shid->power_state)); + + return 0; + +err_wake_irq: + if (device_may_wakeup(dev)) + dev_pm_clear_wake_irq(dev); + return error; +} +EXPORT_SYMBOL_GPL(spi_hid_core_probe); + +void spi_hid_core_remove(struct spi_device *spi) +{ + struct spi_hid *shid = spi_get_drvdata(spi); + struct device *dev = &spi->dev; + int error; + + if (shid->is_panel_follower) + drm_panel_remove_follower(&shid->panel_follower); + else + disable_irq(spi->irq); + + cancel_work_sync(&shid->reset_work); + + spi_hid_stop_hid(shid); + + if (shid->power_state != HIDSPI_OFF) { + shid->ops->assert_reset(shid->ops); + error = shid->ops->power_down(shid->ops); + if (error) + dev_err(dev, "failed to disable regulator\n"); + } + + if (device_may_wakeup(dev)) + dev_pm_clear_wake_irq(dev); +} +EXPORT_SYMBOL_GPL(spi_hid_core_remove); + +static int spi_hid_core_pm_suspend(struct device *dev) +{ + struct spi_hid *shid = dev_get_drvdata(dev); + + if (shid->is_panel_follower) + return 0; + + return spi_hid_suspend(shid); +} + +static int spi_hid_core_pm_resume(struct device *dev) +{ + struct spi_hid *shid = dev_get_drvdata(dev); + + if (shid->is_panel_follower) + return 0; + + return spi_hid_resume(shid); +} + +const struct dev_pm_ops spi_hid_core_pm = { + SYSTEM_SLEEP_PM_OPS(spi_hid_core_pm_suspend, spi_hid_core_pm_resume) +}; +EXPORT_SYMBOL_GPL(spi_hid_core_pm); + +MODULE_DESCRIPTION("HID over SPI transport driver"); +MODULE_AUTHOR("Dmitry Antipov "); +MODULE_LICENSE("GPL"); diff --git a/drivers/hid/spi-hid/spi-hid-core.h b/drivers/hid/spi-hid/spi-hid-core.h new file mode 100644 index 00000000000000..261b2fd7f33290 --- /dev/null +++ b/drivers/hid/spi-hid/spi-hid-core.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Microsoft Corporation + * Copyright (c) 2026 Google LLC + */ + +#ifndef SPI_HID_CORE_H +#define SPI_HID_CORE_H + +#include +#include + +#include + +/* Protocol message size constants */ +#define SPI_HID_READ_APPROVAL_LEN 5 +#define SPI_HID_OUTPUT_HEADER_LEN 8 + +/* Raw input buffer with data from the bus */ +struct spi_hid_input_buf { + u8 header[HIDSPI_INPUT_HEADER_SIZE]; + u8 body[HIDSPI_INPUT_BODY_HEADER_SIZE]; + u8 content[]; +}; + +/* Raw output report buffer to be put on the bus */ +struct spi_hid_output_buf { + u8 header[SPI_HID_OUTPUT_HEADER_LEN]; + u8 content[]; +}; + +/* Processed data from a device descriptor */ +struct spi_hid_device_descriptor { + u16 hid_version; + u16 report_descriptor_length; + u16 max_input_length; + u16 max_output_length; + u16 max_fragment_length; + u16 vendor_id; + u16 product_id; + u16 version_id; + u8 no_output_report_ack; +}; + +/* Driver context */ +struct spi_hid { + struct spi_device *spi; /* spi device. */ + struct hid_device *hid; /* pointer to corresponding HID dev. */ + + struct spi_transfer input_transfer[2]; /* Transfer buffer for read and write. */ + struct spi_message input_message; /* used to execute a sequence of spi transfers. */ + + struct spihid_ops *ops; + struct spi_hid_conf *conf; + + struct spi_hid_device_descriptor desc; /* HID device descriptor. */ + struct spi_hid_output_buf *output; /* Output buffer. */ + struct spi_hid_input_buf *input; /* Input buffer. */ + struct spi_hid_input_buf *response; /* Response buffer. */ + + struct drm_panel_follower panel_follower; + bool is_panel_follower; + bool panel_follower_work_finished; + + u16 response_length; + u16 bufsize; + + enum hidspi_power_state power_state; + + u8 reset_attempts; /* The number of reset attempts. */ + + unsigned long flags; /* device flags. */ + + struct work_struct reset_work; + struct work_struct panel_follower_work; + + /* Control lock to ensure complete output transaction. */ + struct mutex output_lock; + /* Power lock to make sure one power state change at a time. */ + struct mutex power_lock; + /* I/O lock to prevent concurrent output writes during the input read. */ + struct mutex io_lock; + + struct completion output_done; + + u8 read_approval_header[SPI_HID_READ_APPROVAL_LEN]; + u8 read_approval_body[SPI_HID_READ_APPROVAL_LEN]; + + u32 report_descriptor_crc32; /* HID report descriptor crc32 checksum. */ + + u32 regulator_error_count; + int regulator_last_error; + u32 bus_error_count; + int bus_last_error; + u32 dir_count; /* device initiated reset count. */ +}; + +#endif /* SPI_HID_CORE_H */ diff --git a/drivers/hid/spi-hid/spi-hid-of.c b/drivers/hid/spi-hid/spi-hid-of.c new file mode 100644 index 00000000000000..561cf453e44ace --- /dev/null +++ b/drivers/hid/spi-hid/spi-hid-of.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * HID over SPI protocol, Open Firmware related code + * + * Copyright (c) 2021 Microsoft Corporation + * + * This code was forked out of the HID over SPI core code, which is partially + * based on "HID over I2C protocol implementation: + * + * Copyright (c) 2012 Benjamin Tissoires + * Copyright (c) 2012 Ecole Nationale de l'Aviation Civile, France + * Copyright (c) 2012 Red Hat, Inc + * + * which in turn is partially based on "USB HID support for Linux": + * + * Copyright (c) 1999 Andreas Gal + * Copyright (c) 2000-2005 Vojtech Pavlik + * Copyright (c) 2005 Michael Haboustak for Concept2, Inc + * Copyright (c) 2007-2008 Oliver Neukum + * Copyright (c) 2006-2010 Jiri Kosina + */ + +#include +#include +#include +#include +#include + +#include "spi-hid.h" + +struct spi_hid_timing_data { + u32 post_power_on_delay_ms; + u32 minimal_reset_delay_ms; +}; + +/* Config structure is filled with data from Device Tree */ +struct spi_hid_of_config { + struct spihid_ops ops; + + struct spi_hid_conf property_conf; + const struct spi_hid_timing_data *timing_data; + + struct gpio_desc *reset_gpio; + struct regulator *supply; + bool supply_enabled; + u16 hid_over_spi_flags; +}; + +static const struct spi_hid_timing_data timing_data = { + .post_power_on_delay_ms = 10, + .minimal_reset_delay_ms = 100, +}; + +static int spi_hid_of_populate_config(struct spi_hid_of_config *conf, + struct device *dev) +{ + int error; + u32 val; + + error = device_property_read_u32(dev, "input-report-header-address", + &val); + if (error) { + dev_err(dev, "Input report header address not provided."); + return -ENODEV; + } + conf->property_conf.input_report_header_address = val; + + error = device_property_read_u32(dev, "input-report-body-address", &val); + if (error) { + dev_err(dev, "Input report body address not provided."); + return -ENODEV; + } + conf->property_conf.input_report_body_address = val; + + error = device_property_read_u32(dev, "output-report-address", &val); + if (error) { + dev_err(dev, "Output report address not provided."); + return -ENODEV; + } + conf->property_conf.output_report_address = val; + + error = device_property_read_u32(dev, "read-opcode", &val); + if (error) { + dev_err(dev, "Read opcode not provided."); + return -ENODEV; + } + conf->property_conf.read_opcode = val; + + error = device_property_read_u32(dev, "write-opcode", &val); + if (error) { + dev_err(dev, "Write opcode not provided."); + return -ENODEV; + } + conf->property_conf.write_opcode = val; + + conf->supply = devm_regulator_get(dev, "vdd"); + if (IS_ERR(conf->supply)) { + if (PTR_ERR(conf->supply) != -EPROBE_DEFER) + dev_err(dev, "Failed to get regulator: %ld.", + PTR_ERR(conf->supply)); + return PTR_ERR(conf->supply); + } + conf->supply_enabled = false; + + conf->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(conf->reset_gpio)) { + dev_err(dev, "%s: error getting reset GPIO.", __func__); + return PTR_ERR(conf->reset_gpio); + } + + return 0; +} + +static int spi_hid_of_power_down(struct spihid_ops *ops) +{ + struct spi_hid_of_config *conf = container_of(ops, + struct spi_hid_of_config, + ops); + int error; + + if (!conf->supply_enabled) + return 0; + + error = regulator_disable(conf->supply); + if (error == 0) + conf->supply_enabled = false; + + return error; +} + +static int spi_hid_of_power_up(struct spihid_ops *ops) +{ + struct spi_hid_of_config *conf = container_of(ops, + struct spi_hid_of_config, + ops); + int error; + + if (conf->supply_enabled) + return 0; + + error = regulator_enable(conf->supply); + + if (error == 0) { + conf->supply_enabled = true; + fsleep(1000 * conf->timing_data->post_power_on_delay_ms); + } + + return error; +} + +static int spi_hid_of_assert_reset(struct spihid_ops *ops) +{ + struct spi_hid_of_config *conf = container_of(ops, + struct spi_hid_of_config, + ops); + + gpiod_set_value(conf->reset_gpio, 1); + return 0; +} + +static int spi_hid_of_deassert_reset(struct spihid_ops *ops) +{ + struct spi_hid_of_config *conf = container_of(ops, + struct spi_hid_of_config, + ops); + + gpiod_set_value(conf->reset_gpio, 0); + return 0; +} + +static void spi_hid_of_sleep_minimal_reset_delay(struct spihid_ops *ops) +{ + struct spi_hid_of_config *conf = container_of(ops, + struct spi_hid_of_config, + ops); + fsleep(1000 * conf->timing_data->minimal_reset_delay_ms); +} + +static int spi_hid_of_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct spi_hid_of_config *config; + int error; + + config = devm_kzalloc(dev, sizeof(struct spi_hid_of_config), + GFP_KERNEL); + if (!config) + return -ENOMEM; + + config->ops.power_up = spi_hid_of_power_up; + config->ops.power_down = spi_hid_of_power_down; + config->ops.assert_reset = spi_hid_of_assert_reset; + config->ops.deassert_reset = spi_hid_of_deassert_reset; + config->ops.sleep_minimal_reset_delay = + spi_hid_of_sleep_minimal_reset_delay; + + config->timing_data = device_get_match_data(dev); + if (!config->timing_data) + config->timing_data = &timing_data; + + /* + * FIXME: hid_over_spi_flags could be retrieved from spi mode. + * It is always 0 because multi-SPI not supported. + */ + config->hid_over_spi_flags = 0; + + error = spi_hid_of_populate_config(config, dev); + if (error) { + dev_err(dev, "%s: unable to populate config data.", __func__); + return error; + } + + return spi_hid_core_probe(spi, &config->ops, &config->property_conf); +} + +static const struct of_device_id spi_hid_of_match[] = { + { .compatible = "hid-over-spi", .data = &timing_data }, + {} +}; +MODULE_DEVICE_TABLE(of, spi_hid_of_match); + +static const struct spi_device_id spi_hid_of_id_table[] = { + { "hid", 0 }, + { "hid-over-spi", 0 }, + { } +}; +MODULE_DEVICE_TABLE(spi, spi_hid_of_id_table); + +static struct spi_driver spi_hid_of_driver = { + .driver = { + .name = "spi_hid_of", + .owner = THIS_MODULE, + .pm = &spi_hid_core_pm, + .of_match_table = spi_hid_of_match, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + .dev_groups = spi_hid_groups, + }, + .probe = spi_hid_of_probe, + .remove = spi_hid_core_remove, + .id_table = spi_hid_of_id_table, +}; + +module_spi_driver(spi_hid_of_driver); + +MODULE_DESCRIPTION("HID over SPI OF transport driver"); +MODULE_AUTHOR("Dmitry Antipov "); +MODULE_LICENSE("GPL"); diff --git a/drivers/hid/spi-hid/spi-hid-trace.h b/drivers/hid/spi-hid/spi-hid-trace.h new file mode 100644 index 00000000000000..841ec491826d33 --- /dev/null +++ b/drivers/hid/spi-hid/spi-hid-trace.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Microsoft Corporation + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM spi_hid + +#if !defined(_SPI_HID_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _SPI_HID_TRACE_H + +#include +#include +#include "spi-hid-core.h" + +DECLARE_EVENT_CLASS(spi_hid_transfer, + TP_PROTO(struct spi_hid *shid, const void *tx_buf, int tx_len, + const void *rx_buf, u16 rx_len, int ret), + + TP_ARGS(shid, tx_buf, tx_len, rx_buf, rx_len, ret), + + TP_STRUCT__entry( + __field(int, bus_num) + __field(int, chip_select) + __field(int, ret) + __dynamic_array(u8, rx_buf, rx_len) + __dynamic_array(u8, tx_buf, tx_len) + ), + + TP_fast_assign( + __entry->bus_num = shid->spi->controller->bus_num; + __entry->chip_select = spi_get_chipselect(shid->spi, 0); + __entry->ret = ret; + + memcpy(__get_dynamic_array(tx_buf), tx_buf, tx_len); + memcpy(__get_dynamic_array(rx_buf), rx_buf, rx_len); + ), + + TP_printk("spi%d.%d: len=%d tx=[%*phD] rx=[%*phD] --> %d", + __entry->bus_num, __entry->chip_select, + __get_dynamic_array_len(tx_buf) + __get_dynamic_array_len(rx_buf), + __get_dynamic_array_len(tx_buf), __get_dynamic_array(tx_buf), + __get_dynamic_array_len(rx_buf), __get_dynamic_array(rx_buf), + __entry->ret) +); + +DEFINE_EVENT(spi_hid_transfer, spi_hid_input_sync, + TP_PROTO(struct spi_hid *shid, const void *tx_buf, int tx_len, + const void *rx_buf, u16 rx_len, int ret), + TP_ARGS(shid, tx_buf, tx_len, rx_buf, rx_len, ret)); + +DEFINE_EVENT(spi_hid_transfer, spi_hid_input_header_complete, + TP_PROTO(struct spi_hid *shid, const void *tx_buf, int tx_len, + const void *rx_buf, u16 rx_len, int ret), + TP_ARGS(shid, tx_buf, tx_len, rx_buf, rx_len, ret)); + +DEFINE_EVENT(spi_hid_transfer, spi_hid_input_body_complete, + TP_PROTO(struct spi_hid *shid, const void *tx_buf, int tx_len, + const void *rx_buf, u16 rx_len, int ret), + TP_ARGS(shid, tx_buf, tx_len, rx_buf, rx_len, ret)); + +DECLARE_EVENT_CLASS(spi_hid_irq, + TP_PROTO(struct spi_hid *shid, int irq), + + TP_ARGS(shid, irq), + + TP_STRUCT__entry( + __field(int, bus_num) + __field(int, chip_select) + __field(int, irq) + ), + + TP_fast_assign( + __entry->bus_num = shid->spi->controller->bus_num; + __entry->chip_select = spi_get_chipselect(shid->spi, 0); + __entry->irq = irq; + ), + + TP_printk("spi%d.%d: IRQ %d", + __entry->bus_num, __entry->chip_select, __entry->irq) +); + +DEFINE_EVENT(spi_hid_irq, spi_hid_dev_irq, + TP_PROTO(struct spi_hid *shid, int irq), TP_ARGS(shid, irq)); + +DECLARE_EVENT_CLASS(spi_hid, + TP_PROTO(struct spi_hid *shid), + + TP_ARGS(shid), + + TP_STRUCT__entry( + __field(int, bus_num) + __field(int, chip_select) + __field(int, power_state) + __field(u32, flags) + + __field(int, vendor_id) + __field(int, product_id) + __field(int, max_input_length) + __field(int, max_output_length) + __field(u16, hid_version) + __field(u16, report_descriptor_length) + __field(u16, version_id) + ), + + TP_fast_assign( + __entry->bus_num = shid->spi->controller->bus_num; + __entry->chip_select = spi_get_chipselect(shid->spi, 0); + __entry->power_state = shid->power_state; + __entry->flags = shid->flags; + + __entry->vendor_id = shid->desc.vendor_id; + __entry->product_id = shid->desc.product_id; + __entry->max_input_length = shid->desc.max_input_length; + __entry->max_output_length = shid->desc.max_output_length; + __entry->hid_version = shid->desc.hid_version; + __entry->report_descriptor_length = + shid->desc.report_descriptor_length; + __entry->version_id = shid->desc.version_id; + ), + + TP_printk("spi%d.%d: (%04x:%04x v%d) HID v%d.%d state p:%d len i:%d o:%d r:%d flags 0x%08x", + __entry->bus_num, __entry->chip_select, + __entry->vendor_id, __entry->product_id, __entry->version_id, + __entry->hid_version >> 8, __entry->hid_version & 0xff, + __entry->power_state, __entry->max_input_length, + __entry->max_output_length, __entry->report_descriptor_length, + __entry->flags) +); + +DEFINE_EVENT(spi_hid, spi_hid_header_transfer, TP_PROTO(struct spi_hid *shid), + TP_ARGS(shid)); + +DEFINE_EVENT(spi_hid, spi_hid_process_input_report, + TP_PROTO(struct spi_hid *shid), TP_ARGS(shid)); + +DEFINE_EVENT(spi_hid, spi_hid_input_report_handler, + TP_PROTO(struct spi_hid *shid), TP_ARGS(shid)); + +DEFINE_EVENT(spi_hid, spi_hid_reset_response, TP_PROTO(struct spi_hid *shid), + TP_ARGS(shid)); + +DEFINE_EVENT(spi_hid, spi_hid_create_device, TP_PROTO(struct spi_hid *shid), + TP_ARGS(shid)); + +DEFINE_EVENT(spi_hid, spi_hid_refresh_device, TP_PROTO(struct spi_hid *shid), + TP_ARGS(shid)); + +DEFINE_EVENT(spi_hid, spi_hid_response_handler, TP_PROTO(struct spi_hid *shid), + TP_ARGS(shid)); + +DEFINE_EVENT(spi_hid, spi_hid_error_handler, TP_PROTO(struct spi_hid *shid), + TP_ARGS(shid)); + +#endif /* _SPI_HID_TRACE_H */ + +/* + * The following must be outside the protection of the above #if block. + */ +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_PATH . + +/* + * It is required that the TRACE_INCLUDE_FILE be the same + * as this file without the ".h". + */ +#define TRACE_INCLUDE_FILE spi-hid-trace +#include diff --git a/drivers/hid/spi-hid/spi-hid.h b/drivers/hid/spi-hid/spi-hid.h new file mode 100644 index 00000000000000..17b2fdf192ed2c --- /dev/null +++ b/drivers/hid/spi-hid/spi-hid.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Microsoft Corporation + * Copyright (c) 2026 Google LLC + */ + +#ifndef SPI_HID_H +#define SPI_HID_H + +#include +#include + +/* struct spi_hid_conf - Conf provided to the core */ +struct spi_hid_conf { + u32 input_report_header_address; + u32 input_report_body_address; + u32 output_report_address; + u8 read_opcode; + u8 write_opcode; +}; + +/** + * struct spihid_ops - Ops provided to the core + * @power_up: do sequencing to power up the device + * @power_down: do sequencing to power down the device + * @assert_reset: do sequencing to assert the reset line + * @deassert_reset: do sequencing to deassert the reset line + * @sleep_minimal_reset_delay: minimal sleep delay during reset + */ +struct spihid_ops { + int (*power_up)(struct spihid_ops *ops); + int (*power_down)(struct spihid_ops *ops); + int (*assert_reset)(struct spihid_ops *ops); + int (*deassert_reset)(struct spihid_ops *ops); + void (*sleep_minimal_reset_delay)(struct spihid_ops *ops); +}; + +int spi_hid_core_probe(struct spi_device *spi, struct spihid_ops *ops, + struct spi_hid_conf *conf); + +void spi_hid_core_remove(struct spi_device *spi); + +extern const struct attribute_group *spi_hid_groups[]; +extern const struct dev_pm_ops spi_hid_core_pm; + +#endif /* SPI_HID_H */ diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 2bfbcc033d599c..2f6ab547fb24de 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -38,6 +38,18 @@ config HWMON_DEBUG_CHIP comment "Native drivers" +config SENSORS_AAEON + tristate "AAEON hwmon driver" + depends on X86 + depends on UBUNTU_ODM_DRIVERS + select MFD_AAEON + help + This hwmon driver adds support for reporting temperature or fan + speed and voltage on Single Board Computers produced by AAEON. + + This driver leverages the ASUS WMI interface to access device + resources. + config SENSORS_ABITUGURU tristate "Abit uGuru (rev 1 & 2)" depends on (X86 && DMI) || COMPILE_TEST && HAS_IOPORT @@ -2386,6 +2398,16 @@ config SENSORS_SPD5118_DETECT If unsure, say Y. +config SENSORS_T14S_FAN_CTRL + tristate "Lenovo T14s Gen6 Snapdragon Fan Controller" + depends on I2C + help + If you say yes here you get support for the fan controller in the + Lenovo T14s Gen6 Snapdragon laptop. + + This driver can also be built as a module. If so, the module + will be called lenovo-thinkpad-t14s-fan-ctrl. + config SENSORS_TC74 tristate "Microchip TC74" depends on I2C diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 63effc0ab8d113..511d9e178eb6c5 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_SENSORS_HP_WMI) += hp-wmi-sensors.o # Native drivers # asb100, then w83781d go first, as they can override other drivers' addresses. +obj-$(CONFIG_SENSORS_AAEON) += hwmon-aaeon.o obj-$(CONFIG_SENSORS_ASB100) += asb100.o obj-$(CONFIG_SENSORS_W83627HF) += w83627hf.o obj-$(CONFIG_SENSORS_W83773G) += w83773g.o @@ -228,6 +229,7 @@ obj-$(CONFIG_SENSORS_SURFACE_FAN)+= surface_fan.o obj-$(CONFIG_SENSORS_SURFACE_TEMP)+= surface_temp.o obj-$(CONFIG_SENSORS_SY7636A) += sy7636a-hwmon.o obj-$(CONFIG_SENSORS_AMC6821) += amc6821.o +obj-$(CONFIG_SENSORS_T14S_FAN_CTRL) += lenovo-thinkpad-t14s-fan-ctrl.o obj-$(CONFIG_SENSORS_TC74) += tc74.o obj-$(CONFIG_SENSORS_THMC50) += thmc50.o obj-$(CONFIG_SENSORS_TMP102) += tmp102.o diff --git a/drivers/hwmon/hwmon-aaeon.c b/drivers/hwmon/hwmon-aaeon.c new file mode 100644 index 00000000000000..ea6df3c61a05f1 --- /dev/null +++ b/drivers/hwmon/hwmon-aaeon.c @@ -0,0 +1,569 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AAEON HWMON driver + * Copyright (c) 2021, AAEON Ltd. + * + * Author: Edward Lin + * Author: Kunyang Fan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRVNAME "hwmon-aaeon" + +#define AAEON_WMI_MGMT_GUID "97845ED0-4E6D-11DE-8A39-0800200C9A66" + +#define AAEON_VERSION_METHOD_ID 0x00000000 +#define HWM_INFORMATION_METHOD_ID 0x00030000 +#define HWM_METHOD_ID 0x00030001 + +#define BITMAP_TEMP_ARG 0x12 +#define BITMAP_FAN_ARG 0x13 +#define BITMAP_VOLTAGE_ARG 0x14 + +#define SENSOR_TEMP_NUMBER 0 +#define SENSOR_FAN_NUMBER 1 +#define SENSOR_VOLTAGE_NUMBER 2 +#define SENSOR_MAX_NUMBER 2 + +static ssize_t aaeon_show_sensor(struct device *dev, + struct device_attribute *devattr, char *buf); +static ssize_t aaeon_show_sensor_name(struct device *dev, + struct device_attribute *devattr, + char *buf); +static ssize_t aaeon_show_version(struct device *dev, + struct device_attribute *devattr, char *buf); +static ssize_t name_show(struct device *dev, struct device_attribute *devattr, + char *buf); +static int aaeon_get_version(void); +static int aaeon_hwmon_probe(struct platform_device *pdev); +static void aaeon_hwmon_remove(struct platform_device *pdev); + +static const char * const temp_sensors_name_table[] = { + "CPU_Temp", + "SYS1_Temp", + "SYS2_Temp", +}; + +static const char * const temp_sensors_name_table_V3[] = { + "SYS_Temp", + "CPU_Temp", +}; + +static const char * const fan_sensors_name_table[] = { + "CPU_FAN", + "SYS1_FAN", + "SYS2_FAN", + "Chasis1_FAN", + "Chasis2_FAN", +}; + +static const char * const fan_sensors_name_table_V3[] = { + "Chasis_FAN", + "CPU_FAN", +}; + +static const char * const voltage_sensors_name_table[] = { + "VCORE_Voltage", + "VMEM_Voltage", + "+12_Voltage", + "+5_Voltage", + "+3.3_Voltage", + "+1.8_Voltage", + "5VSB_Voltage", + "3VSB_Voltage", + "VBAT_Voltage", +}; + +static const char * const voltage_sensors_name_table_V3[] = { + "VCORE_Voltage", + "+5_Voltage", + "AVCC_Voltage", + "+3.3_Voltage", + "+12_Voltage", + "VCOREREFIN_Voltage", + "VIN4_Voltage", + "3VSB_Voltage", + "VBAT_Voltage", +}; + +struct aaeon_hwmon_data { + struct device *hwmon_dev; + int bfpi_version; + u32 temp_bitmap; + u32 fan_bitmap; + u32 voltage_bitmap; + unsigned int sensors_number[SENSOR_MAX_NUMBER + 1]; + const char * const *temp_names; + const char * const *fan_names; + const char * const *voltage_names; +}; + +/* Temperature attributes */ +static struct sensor_device_attribute_2 temp_sys_nodes_atts[] = { + SENSOR_ATTR_2(temp1_input, 0444, aaeon_show_sensor, NULL, + SENSOR_TEMP_NUMBER, 0), + SENSOR_ATTR_2(temp1_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_TEMP_NUMBER, 0), + SENSOR_ATTR_2(temp2_input, 0444, aaeon_show_sensor, NULL, + SENSOR_TEMP_NUMBER, 1), + SENSOR_ATTR_2(temp2_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_TEMP_NUMBER, 1), + SENSOR_ATTR_2(temp3_input, 0444, aaeon_show_sensor, NULL, + SENSOR_TEMP_NUMBER, 2), + SENSOR_ATTR_2(temp3_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_TEMP_NUMBER, 2), +}; + +/* Cooler Fan attributes */ +static struct sensor_device_attribute_2 fan_sys_nodes_atts[] = { + SENSOR_ATTR_2(fan1_input, 0444, aaeon_show_sensor, NULL, + SENSOR_FAN_NUMBER, 0), + SENSOR_ATTR_2(fan1_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_FAN_NUMBER, 0), + SENSOR_ATTR_2(fan2_input, 0444, aaeon_show_sensor, NULL, + SENSOR_FAN_NUMBER, 1), + SENSOR_ATTR_2(fan2_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_FAN_NUMBER, 1), + SENSOR_ATTR_2(fan3_input, 0444, aaeon_show_sensor, NULL, + SENSOR_FAN_NUMBER, 2), + SENSOR_ATTR_2(fan3_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_FAN_NUMBER, 2), + SENSOR_ATTR_2(fan4_input, 0444, aaeon_show_sensor, NULL, + SENSOR_FAN_NUMBER, 3), + SENSOR_ATTR_2(fan4_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_FAN_NUMBER, 3), + SENSOR_ATTR_2(fan5_input, 0444, aaeon_show_sensor, NULL, + SENSOR_FAN_NUMBER, 4), + SENSOR_ATTR_2(fan5_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_FAN_NUMBER, 4), +}; + +/* Voltage attributes */ +static struct sensor_device_attribute_2 voltage_sys_nodes_atts[] = { + SENSOR_ATTR_2(in1_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 0), + SENSOR_ATTR_2(in1_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 0), + SENSOR_ATTR_2(in2_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 1), + SENSOR_ATTR_2(in2_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 1), + SENSOR_ATTR_2(in3_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 2), + SENSOR_ATTR_2(in3_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 2), + SENSOR_ATTR_2(in4_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 3), + SENSOR_ATTR_2(in4_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 3), + SENSOR_ATTR_2(in5_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 4), + SENSOR_ATTR_2(in5_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 4), + SENSOR_ATTR_2(in6_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 5), + SENSOR_ATTR_2(in6_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 5), + SENSOR_ATTR_2(in7_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 6), + SENSOR_ATTR_2(in7_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 6), + SENSOR_ATTR_2(in8_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 7), + SENSOR_ATTR_2(in8_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 7), + SENSOR_ATTR_2(in9_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 8), + SENSOR_ATTR_2(in9_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 8), + +}; + +static struct sensor_device_attribute_2 info_sys_nodes_atts[] = { + /* WMI version Information */ + SENSOR_ATTR_2(AAEON_VERSION, 0444, aaeon_show_version, NULL, 0, 0), +}; + +DEVICE_ATTR_RO(name); +static ssize_t name_show(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + return sprintf(buf, "%s\n", DRVNAME); +} + +static ssize_t aaeon_show_version(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct aaeon_hwmon_data *data = + (struct aaeon_hwmon_data *)dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", data->bfpi_version); +} + +static ssize_t aaeon_show_sensor_name(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + u8 nr = to_sensor_dev_attr_2(devattr)->nr; + u8 index = to_sensor_dev_attr_2(devattr)->index; + struct aaeon_hwmon_data *data = + (struct aaeon_hwmon_data *)dev_get_drvdata(dev); + + if (nr > SENSOR_MAX_NUMBER || index >= data->sensors_number[nr]) { + pr_debug("Can not check the device"); + return -1; + } + + switch (nr) { + case SENSOR_TEMP_NUMBER: + return sprintf(buf, "%s\n", data->temp_names[index]); + case SENSOR_FAN_NUMBER: + return sprintf(buf, "%s\n", data->fan_names[index]); + case SENSOR_VOLTAGE_NUMBER: + return sprintf(buf, "%s\n", data->voltage_names[index]); + default: + break; + } + + return 0; +} + +static ssize_t aaeon_show_sensor(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + u8 nr = to_sensor_dev_attr_2(devattr)->nr; + u8 index = to_sensor_dev_attr_2(devattr)->index; + u32 dev_id; + int retval, err; + struct aaeon_hwmon_data *data = + (struct aaeon_hwmon_data *)dev_get_drvdata(dev); + + if (nr > SENSOR_MAX_NUMBER || index >= data->sensors_number[nr]) { + pr_debug("Can not check the device"); + return -1; + } + + /* For the V3 version, index need offset */ + if (data->bfpi_version == 0x03 && nr != SENSOR_VOLTAGE_NUMBER) + index++; + + dev_id = (index << 12) | (nr << 8); + err = asus_wmi_evaluate_method(HWM_METHOD_ID, dev_id, 0, &retval); + if (err) + return err; + + /* For the V3 version, need to convert the raw value*/ + if (nr == SENSOR_VOLTAGE_NUMBER && data->bfpi_version == 0x03) { + switch (index) { + case 0: /* VCORE */ + retval = retval * 16; + break; + case 1: /* +5V */ + retval = (retval * 2008) / 50; + break; + case 2: /* AVCC */ + retval = retval * 16; + break; + case 3: /* +3.3V */ + retval = retval * 16; + break; + case 4: /* +12V */ + retval = retval * 96; + break; + case 5: /* VCOREREFIN */ + retval = (retval * 552) / 41; + break; + case 6: /* VIN4 */ + retval = retval * 8; + break; + case 7: /* 3VSB */ + retval = retval * 16; + break; + case 8: /* VBAT */ + retval = retval * 16; + break; + default: + break; + } + } else if (nr == SENSOR_TEMP_NUMBER && data->bfpi_version == 0x03) + retval = retval * 1000; + + return sprintf(buf, "%d\n", retval); +} + +static int aaeon_hwmon_create_sub_sysfs_fs(struct platform_device *pdev, + struct sensor_device_attribute_2 *attr, + int sensor_number, + u32 sensor_mask, + int bfpi_version) +{ + int i, err = 0; + + for (i = 0; i < sensor_number; i++) { + if (bfpi_version == 0x03 || sensor_mask & BIT(i)) { + err = device_create_file(&pdev->dev, &attr[2 * i].dev_attr); + if (err) + break; + err = device_create_file(&pdev->dev, &attr[2 * i + 1].dev_attr); + if (err) + break; + } + } + + return err; +} + +static int +aaeon_hwmon_create_sysfs_files(struct platform_device *pdev, struct aaeon_hwmon_data *data) +{ + int err; + + /* register sysfs interface files */ + err = device_create_file(&pdev->dev, &dev_attr_name); + if (err) + return err; + + /* registe sysfs to dump sensors BFPI version */ + err = device_create_file(&pdev->dev, &info_sys_nodes_atts[0].dev_attr); + if (err) + return err; + + /* create temperature name and value node */ + err = aaeon_hwmon_create_sub_sysfs_fs(pdev, temp_sys_nodes_atts, + data->sensors_number[SENSOR_TEMP_NUMBER], + data->temp_bitmap, data->bfpi_version); + if (err) + return err; + + /* create fan name and value node */ + err = aaeon_hwmon_create_sub_sysfs_fs(pdev, fan_sys_nodes_atts, + data->sensors_number[SENSOR_FAN_NUMBER], + data->fan_bitmap, data->bfpi_version); + if (err) + return err; + + /* create voltage name and value node */ + err = aaeon_hwmon_create_sub_sysfs_fs(pdev, voltage_sys_nodes_atts, + data->sensors_number[SENSOR_VOLTAGE_NUMBER], + data->voltage_bitmap, data->bfpi_version); + if (err) + return err; + + return 0; +} + +static void aaeon_hwmon_remove_sub_sysfs_fs(struct platform_device *pdev, + struct sensor_device_attribute_2 *attr, + int sensor_number, + u32 sensor_mask, + int bfpi_version) +{ + int i; + + for (i = 0; i < sensor_number; i++) { + if (bfpi_version == 0x03 || sensor_mask & BIT(i)) { + device_remove_file(&pdev->dev, &attr[2 * i].dev_attr); + device_remove_file(&pdev->dev, &attr[2 * i + 1].dev_attr); + } + } +} + +static void +aaeon_hwmon_remove_sysfs_files(struct platform_device *pdev, + struct aaeon_hwmon_data *data) +{ + /* degister sysfs interface files */ + device_remove_file(&pdev->dev, &dev_attr_name); + + /* degiste sysfs to dump sensors BFPI version */ + device_remove_file(&pdev->dev, &info_sys_nodes_atts[0].dev_attr); + + /* remove temperature name and value node */ + aaeon_hwmon_remove_sub_sysfs_fs(pdev, temp_sys_nodes_atts, + data->sensors_number[SENSOR_TEMP_NUMBER], + data->temp_bitmap, + data->bfpi_version); + + /* remove fan name and value node */ + aaeon_hwmon_remove_sub_sysfs_fs(pdev, fan_sys_nodes_atts, + data->sensors_number[SENSOR_FAN_NUMBER], + data->fan_bitmap, + data->bfpi_version); + + /* remove voltage name and value node */ + aaeon_hwmon_remove_sub_sysfs_fs(pdev, voltage_sys_nodes_atts, + data->sensors_number[SENSOR_VOLTAGE_NUMBER], + data->voltage_bitmap, + data->bfpi_version); +} + +static void aaeon_hwmon_remove(struct platform_device *pdev) +{ + struct aaeon_hwmon_data *data = platform_get_drvdata(pdev); + + if (data->hwmon_dev) + hwmon_device_unregister(data->hwmon_dev); + + aaeon_hwmon_remove_sysfs_files(pdev, data); + + return; +} + +static int aaeon_get_version(void) +{ + int err, retval; + u32 dev_id = 0x00; + + err = asus_wmi_evaluate_method(AAEON_VERSION_METHOD_ID, dev_id, 0, + &retval); + if (err) + return err; + + return retval; +} + +static int aaeon_hwmon_init_drv_data(struct aaeon_hwmon_data *data) +{ + int err; + + data->bfpi_version = aaeon_get_version(); + if (data->bfpi_version < 0) { + pr_debug("Error BFPI verion\n"); + return -1; + } + + if (data->bfpi_version == 0x03) { + /* set the number of bits in temp bitmap */ + data->sensors_number[SENSOR_TEMP_NUMBER] = + ARRAY_SIZE(temp_sensors_name_table_V3); + data->temp_names = temp_sensors_name_table_V3; + + /* set the number of bits in fan bitmap */ + data->sensors_number[SENSOR_FAN_NUMBER] = + ARRAY_SIZE(fan_sensors_name_table_V3); + data->fan_names = fan_sensors_name_table_V3; + + /* set the number of bits in voltage bitmap */ + data->sensors_number[SENSOR_VOLTAGE_NUMBER] = + ARRAY_SIZE(voltage_sensors_name_table_V3); + data->voltage_names = voltage_sensors_name_table_V3; + } else { + /* set the number of bits in temp bitmap */ + data->sensors_number[SENSOR_TEMP_NUMBER] = + ARRAY_SIZE(temp_sensors_name_table); + data->temp_names = temp_sensors_name_table; + + /* set the number of bits in fan bitmap */ + data->sensors_number[SENSOR_FAN_NUMBER] = + ARRAY_SIZE(fan_sensors_name_table); + data->fan_names = fan_sensors_name_table; + + /* set the number of bits in voltage bitmap */ + data->sensors_number[SENSOR_VOLTAGE_NUMBER] = + ARRAY_SIZE(voltage_sensors_name_table); + data->voltage_names = voltage_sensors_name_table; + } + + /* get temp supported bitmap */ + err = asus_wmi_evaluate_method(HWM_INFORMATION_METHOD_ID, + BITMAP_TEMP_ARG, 0, &data->temp_bitmap); + if (err) + return err; + + /* get fan supported bitmap */ + err = asus_wmi_evaluate_method(HWM_INFORMATION_METHOD_ID, + BITMAP_FAN_ARG, 0, &data->fan_bitmap); + if (err) + return err; + + /* get voltage supported bitmap */ + err = asus_wmi_evaluate_method(HWM_INFORMATION_METHOD_ID, + BITMAP_VOLTAGE_ARG, 0, &data->voltage_bitmap); + if (err) + return err; + + return 0; +} + +static int aaeon_hwmon_probe(struct platform_device *pdev) +{ + int err; + struct aaeon_hwmon_data *data; + + pr_debug("aaeon hwomon device probe (support V3)!\n"); + if (!wmi_has_guid(AAEON_WMI_MGMT_GUID)) { + pr_info("AAEON Management GUID not found\n"); + return -ENODEV; + } + + data = devm_kzalloc(&pdev->dev, sizeof(struct aaeon_hwmon_data), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + err = aaeon_hwmon_init_drv_data(data); + if (err) { + pr_info("Error to get sensor support bitmap\n"); + goto exit; + } + + if (data->bfpi_version != 0x03 && data->temp_bitmap == 0 && + data->fan_bitmap == 0 && data->voltage_bitmap == 0) { + pr_debug("No sensors found\n"); + err = -ENODEV; + goto exit; + } + + platform_set_drvdata(pdev, data); + err = aaeon_hwmon_create_sysfs_files(pdev, data); + if (err) + goto exit; + + data->hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, + "AAEON_HWM", + data, + NULL, + NULL); + if (IS_ERR(data->hwmon_dev)) { + err = PTR_ERR(data->hwmon_dev); + data->hwmon_dev = NULL; + goto exit_unregister_sysfs; + } + + return 0; + +exit_unregister_sysfs: + aaeon_hwmon_remove(pdev); +exit: + return err; +} + +static struct platform_driver aaeon_hwmon_driver = { + .driver = { + .name = DRVNAME, + .owner = THIS_MODULE, + }, + .probe = aaeon_hwmon_probe, + .remove = aaeon_hwmon_remove, +}; + +module_platform_driver_probe(aaeon_hwmon_driver, aaeon_hwmon_probe); + +MODULE_ALIAS("platform:hwmon-aaeon"); +MODULE_DESCRIPTION("AAEON Hardware Monitoring Driver"); +MODULE_AUTHOR("Edward Lin "); +MODULE_AUTHOR("Kunyang Fan "); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("ASUS_WMI"); diff --git a/drivers/hwmon/lenovo-thinkpad-t14s-fan-ctrl.c b/drivers/hwmon/lenovo-thinkpad-t14s-fan-ctrl.c new file mode 100644 index 00000000000000..31c21c869567e7 --- /dev/null +++ b/drivers/hwmon/lenovo-thinkpad-t14s-fan-ctrl.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025-2026 Sebastian Reichel + */ + +#include +#include +#include + +struct t14s_fan_ctrl { + struct i2c_client *i2c; + struct device *dev; +}; + +enum t14s_fan_ctrl_fan { + FAN1 = 0x01, + FAN2 = 0x02, +}; + +enum t14s_fan_ctrl_thermistor { + THERMISTOR1 = 0x29, // TZ39 + THERMISTOR2 = 0x2a, // TZ40 + THERMISTOR3 = 0x2b, // TZ41 + THERMISTOR4 = 0x2c, // TZ42 + THERMISTOR5 = 0x2d, // TZ43 + THERMISTOR6 = 0x2e, // TZ44 + THERMISTOR7 = 0x2f, // TZ45 (always 0x00) +}; + +static const char * const t14s_fan_labels[] = { + "System", +}; + +static int t14s_fan_ctrl_blk_transfer(struct t14s_fan_ctrl *t14s_fan_ctrl, u8 cmd, u8 arg, void *databuf, u8 len) +{ + struct i2c_client *client = t14s_fan_ctrl->i2c; + u8 cmdbuf[2] = {cmd, arg}; + struct i2c_msg msgs[2] = { + { .addr = client->addr, .len = sizeof(cmdbuf), .buf = (u8 *) &cmdbuf }, + { .addr = client->addr, .len = len, .buf = databuf, + .flags = I2C_M_RD } }; + int ret; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret < 0) + dev_err(t14s_fan_ctrl->dev, "command 0x%02x 0x%02x failed: %d\n", cmd, arg, ret); + return ret; +} + +static int t14s_fan_ctrl_fan_status(struct t14s_fan_ctrl *t14s_fan_ctrl, enum t14s_fan_ctrl_fan fan) +{ + u8 databuf[1]; + int ret; + + // sudo i2ctransfer -y 5 w2@0x36 0x21 0x01 r1 + ret = t14s_fan_ctrl_blk_transfer(t14s_fan_ctrl, 0x21, fan, databuf, sizeof(databuf)); + if (ret < 0) + return ret; + + return databuf[0]; // 0 = off, 1 = on +} + +static int t14s_fan_ctrl_fan_speed(struct t14s_fan_ctrl *t14s_fan_ctrl, enum t14s_fan_ctrl_fan fan) +{ + u8 databuf[3]; + int ret; + + // sudo i2ctransfer -y 5 w2@0x36 0x22 0x01 r3 + ret = t14s_fan_ctrl_blk_transfer(t14s_fan_ctrl, 0x22, fan, databuf, sizeof(databuf)); + if (ret < 0) + return ret; + + return databuf[2] << 8 | databuf[1]; // RPM +} + +static int t14s_fan_ctrl_thermistor(struct t14s_fan_ctrl *t14s_fan_ctrl, enum t14s_fan_ctrl_thermistor thermistor) +{ + s32 ret; + + // sudo i2ctransfer -y 5 w2@0x36 r1 + ret = i2c_smbus_read_byte_data(t14s_fan_ctrl->i2c, thermistor); + if (ret < 0) + return ret; + + return ret * 1000; // milli-Celsius +} + +static int +t14s_fan_do_read_fan(struct t14s_fan_ctrl *t14s_fan_ctrl, u32 attr, int channel, long *val) +{ + int ret; + + switch (attr) { + case hwmon_fan_enable: + ret = t14s_fan_ctrl_fan_status(t14s_fan_ctrl, channel); + if (ret < 0) + return ret; + *val = ret; + return 0; + case hwmon_fan_input: + ret = t14s_fan_ctrl_fan_speed(t14s_fan_ctrl, channel); + if (ret < 0) + return ret; + *val = ret; + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int +t14s_fan_do_read_thermistor(struct t14s_fan_ctrl *t14s_fan_ctrl, u32 attr, int channel, long *val) +{ + enum t14s_fan_ctrl_thermistor id; + int ret; + + switch (channel) { + case 1: + id = THERMISTOR1; + break; + case 2: + id = THERMISTOR2; + break; + case 3: + id = THERMISTOR3; + break; + case 4: + id = THERMISTOR4; + break; + case 5: + id = THERMISTOR5; + break; + case 6: + id = THERMISTOR6; + break; + case 7: + id = THERMISTOR7; + break; + default: + return -EINVAL; + } + + switch (attr) { + case hwmon_temp_input: + ret = t14s_fan_ctrl_thermistor(t14s_fan_ctrl, channel + THERMISTOR1 - 1); + if (ret < 0) + return ret; + *val = ret; + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int +t14s_fan_hwmon_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct t14s_fan_ctrl *t14s_fan_ctrl = dev_get_drvdata(dev); + channel++; + + switch (type) { + case hwmon_fan: + return t14s_fan_do_read_fan(t14s_fan_ctrl, attr, channel, val); + case hwmon_temp: + return t14s_fan_do_read_thermistor(t14s_fan_ctrl, attr, channel, val); + default: + return -EOPNOTSUPP; + } +} + +static umode_t +t14s_fan_hwmon_is_visible(const void *data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_fan: + if (attr == hwmon_fan_input || attr == hwmon_fan_label) + return 0444; + return 0; + case hwmon_temp: + if (attr == hwmon_temp_input) + return 0444; + return 0; + default: + return 0; + } +} + +static int +t14s_fan_hwmon_read_string(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + switch (type) { + case hwmon_fan: + *str = t14s_fan_labels[channel]; + return 0; + default: + return -EOPNOTSUPP; + } +} + +static const struct hwmon_ops t14s_fan_hwmon_ops = { + .is_visible = t14s_fan_hwmon_is_visible, + .read = t14s_fan_hwmon_read, + .read_string = t14s_fan_hwmon_read_string, +}; + +static const struct hwmon_channel_info *t14s_fan_hwmon_info[] = { + HWMON_CHANNEL_INFO(fan, + HWMON_F_ENABLE | HWMON_F_INPUT | HWMON_F_LABEL), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT, + HWMON_T_INPUT, + HWMON_T_INPUT, + HWMON_T_INPUT, + HWMON_T_INPUT, + HWMON_T_INPUT), + NULL +}; + +static struct hwmon_chip_info t14s_fan_chip_info = { + .ops = &t14s_fan_hwmon_ops, + .info = t14s_fan_hwmon_info, +}; + +static int t14s_fan_ctrl_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct t14s_fan_ctrl *t14s_fan_ctrl; + struct device *hwdev; + + t14s_fan_ctrl = devm_kzalloc(dev, sizeof(*t14s_fan_ctrl), GFP_KERNEL); + if (!t14s_fan_ctrl) + return -ENOMEM; + + t14s_fan_ctrl->i2c = client; + t14s_fan_ctrl->dev = dev; + + hwdev = devm_hwmon_device_register_with_info(dev, "fan-controller", + t14s_fan_ctrl, + &t14s_fan_chip_info, NULL); + + return PTR_ERR_OR_ZERO(hwdev); +} + +static const struct i2c_device_id t14s_fan_ctrl_id_table[] = { + { "tp-t14s-fan-ctrl" }, + {} +}; +MODULE_DEVICE_TABLE(i2c, t14s_fan_ctrl_id_table); + +static const struct of_device_id of_t14s_fan_ctrl_match_table[] = { + { .compatible = "lenovo,thinkpad-t14s-fan-controller", }, + {} +}; +MODULE_DEVICE_TABLE(of, of_t14s_fan_ctrl_match_table); + +static struct i2c_driver t14s_fan_ctrl_driver = { + .probe = t14s_fan_ctrl_probe, + .id_table = t14s_fan_ctrl_id_table, + .driver = { + .name = "t14s_fan_ctrl", + .of_match_table = of_t14s_fan_ctrl_match_table, + }, +}; +module_i2c_driver(t14s_fan_ctrl_driver); + +MODULE_AUTHOR("Sebastian Reichel "); +MODULE_DESCRIPTION("Thinkpad T14s Gen6 Snapdragon fan controller driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index b29c99ed388393..c8e0ebe58e374a 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c @@ -988,6 +988,14 @@ static void i801_disable_host_notify(struct i801_priv *priv) iowrite8(priv->original_slvcmd, SMBSLVCMD(priv)); } +static inline __maybe_unused void __i801_register_spd(struct i801_priv *priv) +{ + if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) + i2c_register_spd_write_disable(&priv->adapter); + else + i2c_register_spd_write_enable(&priv->adapter); +} + static const struct i2c_algorithm smbus_algorithm = { .smbus_xfer = i801_access, .functionality = i801_func, @@ -1170,6 +1178,19 @@ static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) } } +#ifdef CONFIG_I2C_I801_MUX +static void i801_register_spd(struct i801_priv *priv) +{ + if (!priv->mux_pdev) + __i801_register_spd(priv); +} +#else +static void i801_register_spd(struct i801_priv *priv) +{ + __i801_register_spd(priv); +} +#endif + /* Register optional targets */ static void i801_probe_optional_targets(struct i801_priv *priv) { @@ -1190,10 +1211,7 @@ static void i801_probe_optional_targets(struct i801_priv *priv) dmi_walk(dmi_check_onboard_devices, &priv->adapter); /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ -#ifdef CONFIG_I2C_I801_MUX - if (!priv->mux_pdev) -#endif - i2c_register_spd_write_enable(&priv->adapter); + i801_register_spd(priv); } #else static void __init input_apanel_init(void) {} @@ -1296,7 +1314,7 @@ static int i801_notifier_call(struct notifier_block *nb, unsigned long action, return NOTIFY_DONE; /* Call i2c_register_spd for muxed child segments */ - i2c_register_spd_write_enable(to_i2c_adapter(dev)); + __i801_register_spd(priv); return NOTIFY_OK; } diff --git a/drivers/input/mouse/cypress_ps2.c b/drivers/input/mouse/cypress_ps2.c index 309063d07b4d00..f42f18b6d3fcad 100644 --- a/drivers/input/mouse/cypress_ps2.c +++ b/drivers/input/mouse/cypress_ps2.c @@ -348,7 +348,9 @@ static int cypress_set_input_params(struct input_dev *input, if (error) return error; +#if ( CYPRESS_SIMULATED_MT != 1 ) __set_bit(INPUT_PROP_SEMI_MT, input->propbit); +#endif input_abs_set_res(input, ABS_X, cytp->tp_res_x); input_abs_set_res(input, ABS_Y, cytp->tp_res_y); @@ -435,6 +437,22 @@ static int cypress_parse_packet(struct psmouse *psmouse, ((packet[5] & 0x0f) << 8) | packet[7]; if (cytp->mode & CYTP_BIT_ABS_PRESSURE) report_data->contacts[1].z = report_data->contacts[0].z; +#if ( CYPRESS_SIMULATED_MT == 1 ) + /* simulate contact positions for >2 fingers */ + if ( report_data->contact_cnt >= 3 ) { + int i; + for ( i=1; icontact_cnt; i++ ) { + report_data->contacts[i].x = + report_data->contacts[0].x + + 100*(i)*((i%2)?-1:1); + report_data->contacts[i].y = + report_data->contacts[0].y; + if (cytp->mode & CYTP_BIT_ABS_PRESSURE) + report_data->contacts[i].z = + report_data->contacts[0].z; + } + } +#endif } report_data->left = (header_byte & BTN_LEFT_BIT) ? 1 : 0; diff --git a/drivers/input/mouse/cypress_ps2.h b/drivers/input/mouse/cypress_ps2.h index 47d538a490898d..d17078978b4795 100644 --- a/drivers/input/mouse/cypress_ps2.h +++ b/drivers/input/mouse/cypress_ps2.h @@ -125,7 +125,18 @@ #define RESP_REMOTE_BIT 0x40 #define RESP_SMBUS_BIT 0x80 -#define CYTP_MAX_MT_SLOTS 2 +/* + * CYPRESS_SIMULATED_MT + * set to 1 for simulated multitouch (up to 5 contact points) + * set to 0 for SEMI_MT (only 2 corner points, and count of fingers) + */ +#define CYPRESS_SIMULATED_MT 1 + +#if ( CYPRESS_SIMULATED_MT == 1 ) +# define CYTP_MAX_MT_SLOTS 5 +#else +# define CYTP_MAX_MT_SLOTS 2 +#endif struct cytp_contact { int x; diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c index 8bcce11cb7ce3d..316e9506f26171 100644 --- a/drivers/input/serio/i8042.c +++ b/drivers/input/serio/i8042.c @@ -23,6 +23,7 @@ #include #include #include +#include #include @@ -183,6 +184,24 @@ static bool i8042_handle_data(int irq); static i8042_filter_t i8042_platform_filter; static void *i8042_platform_filter_context; +static int __init i8042_set_noaux(const struct dmi_system_id *dmi) +{ + i8042_noaux = true; + return 1; +} + +static const struct dmi_system_id i8042_quirks[] = { + { + .callback = i8042_set_noaux, + .ident = "Dell laptop", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Precision 5550"), + }, + }, + {}, +}; + void i8042_lock_chip(void) { mutex_lock(&i8042_mutex); @@ -622,7 +641,7 @@ static int i8042_enable_kbd_port(void) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { i8042_ctr &= ~I8042_CTR_KBDINT; i8042_ctr |= I8042_CTR_KBDDIS; - pr_err("Failed to enable KBD port\n"); + pr_info("Failed to enable KBD port\n"); return -EIO; } @@ -641,7 +660,7 @@ static int i8042_enable_aux_port(void) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { i8042_ctr &= ~I8042_CTR_AUXINT; i8042_ctr |= I8042_CTR_AUXDIS; - pr_err("Failed to enable AUX port\n"); + pr_info("Failed to enable AUX port\n"); return -EIO; } @@ -733,7 +752,7 @@ static int i8042_check_mux(void) i8042_ctr &= ~I8042_CTR_AUXINT; if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { - pr_err("Failed to disable AUX port, can't use MUX\n"); + pr_info("Failed to disable AUX port, can't use MUX\n"); return -EIO; } @@ -942,25 +961,28 @@ static int i8042_controller_selftest(void) { unsigned char param; int i = 0; + int ret; /* * We try this 5 times; on some really fragile systems this does not * take the first time... */ - do { + while (i++ < 5) { - if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { - pr_err("i8042 controller selftest timeout\n"); - return -ENODEV; - } - - if (param == I8042_RET_CTL_TEST) + ret = i8042_command(¶m, I8042_CMD_CTL_TEST); + if (ret) + pr_info("i8042 controller selftest timeout (%d/5)\n", i); + else if (param == I8042_RET_CTL_TEST) return 0; + else + dbg("i8042 controller selftest: %#x != %#x\n", + param, I8042_RET_CTL_TEST); - dbg("i8042 controller selftest: %#x != %#x\n", - param, I8042_RET_CTL_TEST); msleep(50); - } while (i++ < 5); + } + + if (ret) + return -ENODEV; #ifdef CONFIG_X86 /* @@ -972,7 +994,7 @@ static int i8042_controller_selftest(void) pr_info("giving up on controller selftest, continuing anyway...\n"); return 0; #else - pr_err("i8042 controller selftest failed\n"); + pr_info("i8042 controller selftest failed\n"); return -EIO; #endif } @@ -1553,6 +1575,8 @@ static int i8042_probe(struct platform_device *dev) i8042_dritek_enable(); #endif + dmi_check_system(i8042_quirks); + if (!i8042_noaux) { error = i8042_setup_aux(); if (error && error != -ENODEV && error != -EBUSY) diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 9b9ae8ac3f7fd3..92b8b9c46c5ad5 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -1414,4 +1414,16 @@ config TOUCHSCREEN_HIMAX_HX83112B To compile this driver as a module, choose M here: the module will be called himax_hx83112b. +config TOUCHSCREEN_MSHW0485 + tristate "Microsoft Surface G6 MSHW0485 touchscreen" + depends on SPI && HID && HIDRAW + help + Say Y here to enable support for the Microsoft Surface G6 (MSHW0485) + touchscreen found on the Surface Pro 11 X1E/OLED and X1P/LCD variants. + The driver also exposes the native DFT stream through a HIDRAW-only + compatibility device for iptsd stylus processing on both variants. + + To compile this driver as a module, choose M here: the module will be + called mshw0485_touch. + endif diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index bfd9de83389d88..4eded5ef8057ee 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_TOUCHSCREEN_MELFAS_MIP4) += melfas_mip4.o obj-$(CONFIG_TOUCHSCREEN_MIGOR) += migor_ts.o obj-$(CONFIG_TOUCHSCREEN_MMS114) += mms114.o obj-$(CONFIG_TOUCHSCREEN_MSG2638) += msg2638.o +obj-$(CONFIG_TOUCHSCREEN_MSHW0485) += mshw0485_touch.o obj-$(CONFIG_TOUCHSCREEN_MTOUCH) += mtouch.o obj-$(CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS) += novatek-nvt-ts.o obj-$(CONFIG_TOUCHSCREEN_HP600) += hp680_ts_input.o diff --git a/drivers/input/touchscreen/g6ts_classifier_profile.h b/drivers/input/touchscreen/g6ts_classifier_profile.h new file mode 100644 index 00000000000000..b95ab191b243f9 --- /dev/null +++ b/drivers/input/touchscreen/g6ts_classifier_profile.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Generated by tools/generate_classifier_header.py; do not edit. */ +#ifndef _G6TS_CLASSIFIER_PROFILE_H +#define _G6TS_CLASSIFIER_PROFILE_H + +#define G6TS_CLASS_COUNT 4U +#define G6TS_FEATURE_COUNT 10U +#define G6TS_CLASSIFIER_SHIFT 12U + +struct g6ts_classifier_model { + u16 max_points; + s32 score_offset_q12; + s32 means_q12[G6TS_FEATURE_COUNT]; + s32 transform_q12[G6TS_FEATURE_COUNT][G6TS_FEATURE_COUNT]; +}; + +static const struct g6ts_classifier_model g6ts_classifier_models[] = { + { + .max_points = 25, + .score_offset_q12 = 69201, + .means_q12 = { + 23673, 15143, 11507, 9733, 4096, 4210, 4314, 5825, 4248, 1257, + }, + .transform_q12 = { + { 4436, -4353, -552, -403, 0, -6991, -1734, -11172, 31879, 2290 }, + { 0, 4722, -4650, -402, 0, -21389, -3782, -1423, 4129, -683 }, + { 0, 0, 6558, -6653, 0, 16454, -18713, -2170, 4013, -2251 }, + { 0, 0, 0, 3411, 0, 673, 2973, -4213, 10377, -8562 }, + { 0, 0, 0, 0, 12952689, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 34310, -14872, -2125, 1078, 205 }, + { 0, 0, 0, 0, 0, 0, 19755, -7406, 5165, -4256 }, + { 0, 0, 0, 0, 0, 0, 0, 18819, -25979, -4623 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 21619, -2922 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 17268 }, + }, + }, + { + .max_points = 9999, + .score_offset_q12 = 22537, + .means_q12 = { + 44522, 26295, 20014, 16012, 4290, 4502, 4878, 9293, 5060, 6484, + }, + .transform_q12 = { + { 2651, -2405, -791, -287, -7039, -765, -1487, -10236, 21680, 2919 }, + { 0, 3189, -3490, -145, 3092, -6707, -2049, -2082, 2032, 651 }, + { 0, 0, 3720, -4152, -1126, 6598, -9724, -1214, -110, -525 }, + { 0, 0, 0, 1699, 38, 1352, 1558, -6660, 5435, -2881 }, + { 0, 0, 0, 0, 21196, -3134, -583, -511, -3286, 157 }, + { 0, 0, 0, 0, 0, 15050, -5342, -295, -1551, 679 }, + { 0, 0, 0, 0, 0, 0, 8604, -2753, -3285, 297 }, + { 0, 0, 0, 0, 0, 0, 0, 12285, -20929, 2906 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 18123, -3031 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 9982 }, + }, + }, + { + .max_points = 30, + .score_offset_q12 = 20818, + .means_q12 = { + 49521, 31956, 23366, 17379, 4602, 5687, 6891, 12408, 6246, 3383, + }, + .transform_q12 = { + { 3114, -2822, -403, -341, -4259, -401, -869, -15060, 38505, 1502 }, + { 0, 3100, -2802, -323, 8054, -5654, -399, 497, -3197, 691 }, + { 0, 0, 3909, -3577, 590, 9073, -7027, 399, -4118, -315 }, + { 0, 0, 0, 2544, 2168, 1200, 4596, -3374, 3258, -2384 }, + { 0, 0, 0, 0, 12320, -3800, 597, -1647, 1344, 1258 }, + { 0, 0, 0, 0, 0, 8543, -4070, -1598, 923, 1229 }, + { 0, 0, 0, 0, 0, 0, 5923, -990, -3679, 2912 }, + { 0, 0, 0, 0, 0, 0, 0, 17840, -40118, 859 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 15241, -2536 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 13165 }, + }, + }, + { + .max_points = 50, + .score_offset_q12 = 15612, + .means_q12 = { + 73118, 15909, 11125, 8869, 12805, 13176, 12635, 20448, 12870, 2737, + }, + .transform_q12 = { + { 2283, -2597, -257, -722, -13265, -2680, -428, 181, 4916, 282 }, + { 0, 4070, -2869, -598, 6445, -4628, -233, 317, -1793, 675 }, + { 0, 0, 6301, -4724, 133, 550, -1225, 278, 240, 169 }, + { 0, 0, 0, 5560, -774, 462, -806, -5, 2343, -2665 }, + { 0, 0, 0, 0, 12494, -6339, -1114, 782, -5492, -331 }, + { 0, 0, 0, 0, 0, 10192, -5053, 688, -6344, 549 }, + { 0, 0, 0, 0, 0, 0, 7047, -332, -5038, -792 }, + { 0, 0, 0, 0, 0, 0, 0, 4286, -5370, 2891 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 4363, -8900 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 11001 }, + }, + }, +}; + +#endif /* _G6TS_CLASSIFIER_PROFILE_H */ diff --git a/drivers/input/touchscreen/g6ts_lifecycle_profile.h b/drivers/input/touchscreen/g6ts_lifecycle_profile.h new file mode 100644 index 00000000000000..fcb343a560eeec --- /dev/null +++ b/drivers/input/touchscreen/g6ts_lifecycle_profile.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Generated by tools/generate_lifecycle_header.py; do not edit. */ +#ifndef _G6TS_LIFECYCLE_PROFILE_H +#define _G6TS_LIFECYCLE_PROFILE_H + +#define G6TS_WINDOWS_UNCLASSIFIED 4U +#define G6TS_WINDOWS_HISTORY_CAPACITY 10U +#define G6TS_WINDOWS_SCORE_SHIFT 24U +#define G6TS_WINDOWS_RUNTIME_OFFSET_Q24 -177430463LL +#define G6TS_WINDOWS_SCORE3_PRIMARY_Q24 838860800LL +#define G6TS_WINDOWS_SCORE3_SINGLE_Q24 335544320LL +#define G6TS_WINDOWS_ASSIGN_X_SCALE_Q24 68082944U +#define G6TS_WINDOWS_ASSIGN_Y_SCALE_Q24 67306464U +#define G6TS_WINDOWS_ASSIGN_RADIUS 5U + +struct g6ts_transition_rule { + s32 history_margins[G6TS_CLASS_COUNT]; + s32 current_margins[G6TS_CLASS_COUNT]; + s16 absolute_minimum; + s8 context_score_bias; + u8 history_depth; + u8 initial_age_limit; + u8 context_allowed; + u8 context_extra_history; +}; + +static const u16 g6ts_class_point_minimums[G6TS_CLASS_COUNT] = { 0, 6, 4, 4 }; +static const u16 g6ts_class_point_maximums[G6TS_CLASS_COUNT] = { 20, 9999, 50, 100 }; + +static const struct g6ts_transition_rule g6ts_transition_rules[] = { + /* 0 -> 0 */ + { + .history_margins = { 0, 0, 0, 0 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = 0, + .context_score_bias = 2, + .history_depth = 0, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 0 -> 1 */ + { + .history_margins = { 20, 0, 10, 30 }, + .current_margins = { 100, 0, 10, 30 }, + .absolute_minimum = -500, + .context_score_bias = 2, + .history_depth = 5, + .initial_age_limit = 3, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 0 -> 2 */ + { + .history_margins = { 2, 30, 0, 30 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -25, + .context_score_bias = 2, + .history_depth = 2, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 0 -> 3 */ + { + .history_margins = { 200, 15, 7, 0 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -45, + .context_score_bias = 2, + .history_depth = 1, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 1 -> 0 */ + { + .history_margins = { 0, 5, 5, 40 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -2, + .context_score_bias = 2, + .history_depth = 8, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 1 -> 1 */ + { + .history_margins = { 0, 0, 0, 0 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = 0, + .context_score_bias = 2, + .history_depth = 0, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 1 -> 2 */ + { + .history_margins = { 1, 30, 0, 40 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -25, + .context_score_bias = 2, + .history_depth = 4, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 1 -> 3 */ + { + .history_margins = { 30, 30, 30, 0 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -20, + .context_score_bias = 2, + .history_depth = 30, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 2 -> 0 */ + { + .history_margins = { 0, 15, 1, 15 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -25, + .context_score_bias = 2, + .history_depth = 2, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 2 -> 1 */ + { + .history_margins = { 40, 0, 80, 30 }, + .current_margins = { 100, 0, 80, 80 }, + .absolute_minimum = -500, + .context_score_bias = 2, + .history_depth = 5, + .initial_age_limit = 3, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 2 -> 2 */ + { + .history_margins = { 0, 0, 0, 0 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = 0, + .context_score_bias = 2, + .history_depth = 0, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 2 -> 3 */ + { + .history_margins = { 50, 10, 30, 0 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -15, + .context_score_bias = 2, + .history_depth = 4, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 3 -> 0 */ + { + .history_margins = { 0, 15, 1, 15 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -25, + .context_score_bias = 2, + .history_depth = 1, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 3 -> 1 */ + { + .history_margins = { 20, 0, 40, 100 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -40, + .context_score_bias = 2, + .history_depth = 5, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 3 -> 2 */ + { + .history_margins = { 2, 12, 0, 30 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -25, + .context_score_bias = 2, + .history_depth = 3, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 3 -> 3 */ + { + .history_margins = { 0, 0, 0, 0 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = 0, + .context_score_bias = 2, + .history_depth = 0, + .initial_age_limit = 0, + .context_allowed = 1, + .context_extra_history = 0, + }, + /* 4 -> 0 */ + { + .history_margins = { 0, 6, 1, 30 }, + .current_margins = { 0, 10, 1, 30 }, + .absolute_minimum = -3, + .context_score_bias = 0, + .history_depth = 2, + .initial_age_limit = 3, + .context_allowed = 0, + .context_extra_history = 3, + }, + /* 4 -> 1 */ + { + .history_margins = { 22, 0, 15, 15 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -9999, + .context_score_bias = 2, + .history_depth = 2, + .initial_age_limit = 0, + .context_allowed = 0, + .context_extra_history = 0, + }, + /* 4 -> 2 */ + { + .history_margins = { 1, 3, 0, 8 }, + .current_margins = { 255, 255, 255, 255 }, + .absolute_minimum = -8, + .context_score_bias = 2, + .history_depth = 4, + .initial_age_limit = 3, + .context_allowed = 0, + .context_extra_history = 2, + }, + /* 4 -> 3 */ + { + .history_margins = { 100, 7, 8, 0 }, + .current_margins = { 100, 30, 10, 0 }, + .absolute_minimum = -20, + .context_score_bias = 2, + .history_depth = 3, + .initial_age_limit = 3, + .context_allowed = 1, + .context_extra_history = 0, + }, +}; + +#endif /* _G6TS_LIFECYCLE_PROFILE_H */ diff --git a/drivers/input/touchscreen/mshw0485_touch.c b/drivers/input/touchscreen/mshw0485_touch.c new file mode 100644 index 00000000000000..23b002f6dbfd40 --- /dev/null +++ b/drivers/input/touchscreen/mshw0485_touch.c @@ -0,0 +1,4741 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microsoft Surface G6 Touch (MSHW0485) touchscreen driver. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "g6ts_classifier_profile.h" +#include "g6ts_lifecycle_profile.h" + +#define G6TS_NAME "mshw0485-touch" +#define G6TS_SPI_HZ 40000000U +#define G6TS_MAX_BODY 8192U +#define G6TS_HEADER_SYNC 0x5a +#define G6TS_HEADER_VERSION 0x03 +#define G6TS_FEATURE_RESPONSE_LIMIT 64U +#define G6TS_IRQ_DRAIN_LIMIT 128U +#define G6TS_HEAT_QUEUE_CAPACITY 64U +#define G6TS_HEATMAP_REPORT_ID 0x12 +#define G6TS_RAW_SIDEBAND_REPORT_07 0x07 +#define G6TS_RAW_HEAT_REPORT_0B 0x0b +#define G6TS_RAW_HEAT_REPORT_0C 0x0c +#define G6TS_RAW_HEAT_REPORT_0D 0x0d +#define G6TS_RAW_HEAT_REPORT_1A 0x1a +#define G6TS_RAW_SIDEBAND_REPORT_6E 0x6e +#define G6TS_IPTS_MODE_REPORT_ID 0x05 +#define G6TS_IPTS_METADATA_REPORT_ID 0x06 +#define G6TS_IPTS_METADATA_LEN 119U +#define G6TS_PEN_REPORT_ID 0x01 +#define G6TS_PEN_REPORT_LEN 15U +#define G6TS_PEN_X_MAX 9600U +#define G6TS_PEN_Y_MAX 7200U +#define G6TS_PEN_PRESSURE_MAX 4096U +#define G6TS_PEN_TILT_RAW_MAX 18000U +#define G6TS_PEN_TILT_CENTER 9000 +#define G6TS_PEN_X_RESOLUTION 35U +#define G6TS_PEN_Y_RESOLUTION 39U +#define G6TS_PEN_TILT_RESOLUTION 5730U +#define G6TS_PEN_IN_RANGE BIT(0) +#define G6TS_PEN_TIP_SWITCH BIT(1) +#define G6TS_PEN_BARREL_SWITCH BIT(2) +#define G6TS_PEN_INVERT BIT(3) +#define G6TS_PEN_ERASER BIT(4) +#define G6TS_MODE_ATTEMPT_LIMIT 3U +#define G6TS_RECOVERY_DELAY_MS 100U +#define G6TS_RECOVERY_RETRY_MS 500U +#define G6TS_RECOVERY_LIMIT 3U +#define G6TS_HID_REBIND_STABLE_MS 250U +#define G6TS_HID_REBIND_RETRY_MS 1000U +#define G6TS_HID_REBIND_RETRY_LIMIT 2U +#define G6TS_RESET_STORM_WINDOW_MS 5000U +#define G6TS_RESET_STORM_LIMIT 3U +#define G6TS_HEAT_ROWS 46U +#define G6TS_HEAT_COLS 68U +#define G6TS_HEAT_SAMPLES (G6TS_HEAT_ROWS * G6TS_HEAT_COLS) +#define G6TS_HEAT_SECTION 0x0100 +#define G6TS_METADATA_SECTION 0xff00 +#define G6TS_NSR_BINS 16U +#define G6TS_NSR_CUTOFF 655U +/* + * TouchPenProcessor0C83.dll converts a calibrated byte through a linear + * lookup whose zero crossing is approximately 180. The SP11 configuration + * is inferred to start a candidate at raw <= 171. Its scan-line union joins + * only edge-adjacent cells. One- and two-cell candidates survive only when + * their peak is stronger than the secondary detector threshold (approximately + * raw <= 162); all candidates of three or more cells continue downstream. + */ +#define G6TS_HEAT_SIGNAL_ZERO 180U +#define G6TS_HEAT_THRESHOLD 9U +#define G6TS_HEAT_ACTIVE_MAX (G6TS_HEAT_SIGNAL_ZERO - G6TS_HEAT_THRESHOLD) +#define G6TS_HEAT_STRONG_MAX 162U +#define G6TS_HEAT_MIN_PIXELS 3U +#define G6TS_HEAT_PALM_PIXELS 48U +#define G6TS_HEAT_PALM_SPAN 12U +#define G6TS_MAX_CONTACTS 10U +#define G6TS_LOGICAL_MAX 32767U +#define G6TS_TRACK_MATCH_MAX 4096U +#define G6TS_CONTACT_HOLD_FRAMES 6U +#define G6TS_TRACK_CONFIRM_NORMAL 3U +#define G6TS_TRACK_CONFIRM_WEAK 5U +#define G6TS_TRACK_CONFIRM_SPLIT 8U +#define G6TS_TRACK_SPLIT_RADIUS 2048U +#define G6TS_BEHAVIOR_CONFIRM_NORMAL 2U +#define G6TS_WINDOWS_CENTROID_BASELINE 171U +#define G6TS_SMOOTH_STATIONARY_MAX 64U +#define G6TS_SMOOTH_SLOW_MAX 256U +#define G6TS_SIGNAL_INTERCEPT_Q24 6710886 +#define G6TS_SIGNAL_STEP_Q24 37251 +#define G6TS_SECONDARY_A_Q12 645663 +#define G6TS_SECONDARY_NOISE_Q12 36895 +#define G6TS_SECONDARY_SEED_Q12 225 +#define G6TS_LOCAL_PEAK_FLOOR_Q12 164 +#define G6TS_LOCAL_PEAK_CAPACITY 10U +#define G6TS_AXIS_SCALE_Q12 18919 +#define G6TS_SPREAD_SCALE_Q12 25736 +#define G6TS_HALO_RATIO_Q12 614 +#define G6TS_HALO_UNAVAILABLE_Q12 (100U << G6TS_CLASSIFIER_SHIFT) +#define G6TS_ASSIGN_MAX (G6TS_MAX_CONTACTS * 2U) +#define G6TS_ASSIGN_UNMATCHED_COST 1000000 +#define G6TS_ASSIGN_INVALID_COST 3000000 + +/* Exact SP11 descriptor values shared by the supported X1E and X1P panels. */ +#define G6TS_SP11_REPORT_DESCRIPTOR_LEN 1484U +#define G6TS_SP11_MAX_INPUT_LEN 8192U +#define G6TS_SP11_MAX_OUTPUT_LEN 512U +#define G6TS_SP11_MAX_FRAGMENT_LEN 8192U +#define G6TS_SP11_VENDOR_ID 0x045eU +#define G6TS_SP11_X1E_PRODUCT_ID 0x0c83U +#define G6TS_SP11_X1P_PRODUCT_ID 0x0c80U +#define G6TS_SP11_VERSION_ID 0x0004U +#define G6TS_SP11_DESCRIPTOR_FLAGS 0x0001U +#define G6TS_WINDOWS_FEEDBACK_LEN 63U +#define G6TS_WINDOWS_REPORT56_ID_LEN 6U +#define G6TS_WINDOWS_CONFIG_DELAY_MS 470U +#define G6TS_WINDOWS_CFU_DELAY_MS 825U +#define G6TS_WINDOWS_FINAL_CONFIG_DELAY_MS 600U +#define G6TS_WINDOWS_CFU_OFFER_LEN 16U +#define G6TS_WINDOWS_CFU_VERSION_LEN 60U +#define G6TS_WINDOWS_CFU_TOKEN 0xa0U +#define G6TS_WINDOWS_HEADER_BODY_MIN_US 490U +#define G6TS_WINDOWS_HEADER_BODY_MAX_US 550U + +enum g6ts_initialization_stage { + G6TS_INIT_IDLE, + G6TS_INIT_WINDOWS_POWER_PS0, + G6TS_INIT_WINDOWS_RESET_METHOD, + G6TS_INIT_RESET_RESPONSE, + G6TS_INIT_DEVICE_DESCRIPTOR, + G6TS_INIT_REPORT_DESCRIPTOR, + G6TS_INIT_WINDOWS_EARLY_FEATURE73, + G6TS_INIT_WINDOWS_HEAT_CAPS06, + G6TS_INIT_WINDOWS_FEEDBACK_REQUIRED, + G6TS_INIT_WINDOWS_FEEDBACK_A1, + G6TS_INIT_WINDOWS_FEEDBACK_A5, + G6TS_INIT_WINDOWS_SET_FEATURE05, + G6TS_INIT_WINDOWS_CONFIG_OWNER_REQUIRED, + G6TS_INIT_WINDOWS_GET_FEATURE70, + G6TS_INIT_WINDOWS_SET_FEATURE70, + G6TS_INIT_WINDOWS_SET_FEATURE56, + G6TS_INIT_WINDOWS_CFU_OWNER_REQUIRED, + G6TS_INIT_WINDOWS_CFU_GET_VERSION, + G6TS_INIT_WINDOWS_CFU_START_TRANSACTION, + G6TS_INIT_WINDOWS_CFU_START_LIST, + G6TS_INIT_WINDOWS_CFU_OFFER, + G6TS_INIT_WINDOWS_CFU_BRANCH_REQUIRED, + G6TS_INIT_WINDOWS_CFU_END_LIST, + G6TS_INIT_WINDOWS_FINAL_FEATURE73, + G6TS_INIT_WINDOWS_HEAT_OWNER_REQUIRED, + G6TS_INIT_SET_FEATURE05, + G6TS_INIT_GET_FEATURE70, + G6TS_INIT_SET_FEATURE70, + G6TS_INIT_SET_FEATURE56, + G6TS_INIT_WAIT_HEAT, +}; + +#define G6TS_INIT_STAGE_COUNT (G6TS_INIT_WAIT_HEAT + 1) + +/* + * Phase 70 keeps the hardware-validated Phase 68 policy as the default. The + * recovered Windows profile is opt-in until its provider-owned frame flags + * have live ground truth. Read-only prevents switching policy under active + * contacts and mixing two incompatible track coordinate spaces. + */ +static bool g6ts_windows_orchestrator; +module_param_named(windows_orchestrator, g6ts_windows_orchestrator, bool, 0444); +MODULE_PARM_DESC(windows_orchestrator, + "Use the experimental recovered Windows frame profile (default: false)"); + +static bool g6ts_heat_feedback; +module_param_named(heat_feedback, g6ts_heat_feedback, bool, 0444); +MODULE_PARM_DESC(heat_feedback, + "Enable the per-heat-cycle Windows V06 feedback stream (report 0x09); " + "requires parity_fast_host_id=0..65535 (default: false)"); + +/* + * Expose the native descriptor and DFT reports for both supported SP11 panel + * identities through a HIDRAW-only sibling so the established iptsd decoder + * can provide the stylus input device. X1E/OLED (0x0c83) is live-qualified; + * X1P/LCD (0x0c80) selects the same bounded descriptor validation and DFT + * contract but remains pending target hardware qualification. The custom + * driver remains the sole owner of panel mode and touch processing. + */ +static bool g6ts_ipts_hid_bridge = true; +module_param_named(ipts_hid_bridge, g6ts_ipts_hid_bridge, bool, 0444); +MODULE_PARM_DESC(ipts_hid_bridge, + "Expose a HIDRAW-only IPTS compatibility device (default: true)"); + +/* + * Phase 83 isolates the private post-mode feature exchanges from the + * HID-over-SPI sequence used by the known-working SP11 IPTS stack. X1E target + * validation with the HIDRAW bridge established this as the production pen + * path: stop after iptsd's SET_FEATURE 0x05 mode command, while retaining the + * read-only parameter as a load-time fallback to the Phase 72 mode tail. + */ +static bool g6ts_ipts_minimal_init = true; +module_param_named(ipts_minimal_init, g6ts_ipts_minimal_init, bool, 0444); +MODULE_PARM_DESC(ipts_minimal_init, + "Use SET_FEATURE 0x05-only IPTS initialization; requires ipts_hid_bridge (default: true)"); + +/* + * Phase 84 matches the generic Linux HID-over-SPI runtime IRQ contract: + * service one complete response per level-low threaded interrupt. X1E target + * validation established exact IRQ/response accounting with the IPTS pen + * stream. Make this the module-wide default for both supported product IDs + * while retaining a load-time fallback; X1P live qualification remains + * pending. Keep the IRQ masked while the custom driver owns synchronous + * initialization and recovery, and add no Windows-only delay between header + * and body reads. + */ +static bool g6ts_ipts_irq_cadence = true; +module_param_named(ipts_irq_cadence, g6ts_ipts_irq_cadence, bool, 0444); +MODULE_PARM_DESC(ipts_irq_cadence, + "Service one response per level-low IRQ without the Windows header/body delay; " + "requires ipts_minimal_init, ready_quiesce, and host_fault_recovery (default: true)"); + +/* + * Phase 76 isolates the behavior-only changes from the hardware-validated + * Phase 75 transport and recovery path. It enables three independently + * proven ordinary-finger pieces without enabling the incomplete Windows + * lifecycle: sensor-space assignment, direct output coordinates, and the + * project-0x0c83 normal expanded-centroid baseline. Strong contacts use the + * previously tested two-frame admission window; weak and nearby split + * candidates retain their longer gates. + */ +static bool g6ts_behavior_v2; +module_param_named(behavior_v2, g6ts_behavior_v2, bool, 0444); +MODULE_PARM_DESC(behavior_v2, + "Use Phase 76 low-latency Windows-derived contact behavior (default: false)"); + +/* + * Phase 72 hardware-validated a coupled experiment: append the Linux panel's + * GET_FEATURE 0x70 content to SET_FEATURE 0x70 and emit a short report 0x09. + * A later transfer-length audit disproved the original claim that this mirrors + * Windows: captured Windows SET_FEATURE 0x70 content is one byte and its report + * 0x09 content is 63 bytes. Keep the proven Linux sequence until isolated + * experiments identify which element prevents the reset storm. + */ +static bool g6ts_mode_config_fix = true; +module_param_named(mode_config_fix, g6ts_mode_config_fix, bool, 0444); +MODULE_PARM_DESC(mode_config_fix, + "Use validated Phase 72 SET 0x70 + short 0x09 sequence (default: true)"); + +/* + * Phase 79 isolates the first known Phase 72 divergence. Windows declares + * one logical SET_FEATURE 0x70 content byte (01); Linux appends the panel's + * GET_FEATURE result (02). Keep the short Phase 72 report 0x09 unchanged so + * this switch changes exactly one logical feature byte. + */ +static bool g6ts_feature70_one_byte; +module_param_named(feature70_one_byte, g6ts_feature70_one_byte, bool, 0444); +MODULE_PARM_DESC(feature70_one_byte, + "Use Windows-length one-byte SET_FEATURE 0x70 with short report 0x09 (default: false)"); + +/* + * Phase 77 keeps cold initialization and the Phase 75 mode exchange intact, + * but does not force a second hardware reset after the panel has already sent + * RESET_RESPONSE. The device-reset path re-enumerates in place, gates Linux + * input until a complete Heat frame validates the restored stream, and falls + * back to the cold hardware path if software recovery itself fails. + */ +static bool g6ts_reset_recovery_v2; +module_param_named(reset_recovery_v2, g6ts_reset_recovery_v2, bool, 0444); +MODULE_PARM_DESC(reset_recovery_v2, + "Use Phase 77 gated software recovery after panel reset (default: false)"); + +/* + * Phase 78 bounds the Phase 77 fast path. A real hardware run proved that + * software re-enumeration can succeed repeatedly while the panel continues + * issuing RESET_RESPONSE. Three closely spaced resets therefore escalate + * the current attempt to the existing cold hardware power/reset path. + */ +static bool g6ts_reset_storm_breaker; +module_param_named(reset_storm_breaker, g6ts_reset_storm_breaker, bool, 0444); +MODULE_PARM_DESC(reset_storm_breaker, + "Escalate a rapid Phase 77 reset loop to hardware recovery (default: false)"); + +/* + * The July KDNET capture proves that Windows does not leave the collection + * inert after a host-side HID-SPI timeout: it enters ResetDevice, observes the + * reset response, and enumerates the descriptors again. The Linux IRQ path + * historically just broke out after a transport or framing failure, leaving + * mode_enabled set with no recovery work queued. Phase 80 makes that recovery + * explicit and observable. It uses the already proven cold hardware path; + * it does not invent another panel command sequence. + */ +static bool g6ts_host_fault_recovery = true; +module_param_named(host_fault_recovery, g6ts_host_fault_recovery, bool, 0444); +MODULE_PARM_DESC(host_fault_recovery, + "Recover with a cold re-enumeration after an IRQ transport/protocol fault (default: true)"); + +/* + * Phase 80 live evidence found invalid second headers immediately after valid + * Heat bodies. GPIO51 can remain logically ready until the completed body + * transaction has propagated through the panel. Phase 81 waits once, then + * treats an invalid header as an empty trailing read only if ready deasserted; + * a still-asserted line remains a real protocol fault handled by Phase 80. + */ +static bool g6ts_ready_quiesce = true; +module_param_named(ready_quiesce, g6ts_ready_quiesce, bool, 0444); +MODULE_PARM_DESC(ready_quiesce, + "Ignore one invalid trailing header after GPIO51 deasserts (default: true)"); + +/* + * Evidence-only cold-attach path. It follows the byte-exact Windows cold + * sequence through each operation whose owner and contents are known. Dynamic + * A1/A5 feedback and report-0x56 identity inputs are unavailable by default; + * when explicitly supplied, the path advances through the device-config + * owner and stops before independent CFU traffic. Heat remains disabled + * unless the separate parity_heat_input gate is selected together with the + * complete bounded CFU inventory path. + */ +static bool g6ts_windows_init_parity; +module_param_named(windows_init_parity, g6ts_windows_init_parity, bool, 0444); +MODULE_PARM_DESC(windows_init_parity, + "Run evidence-gated Windows cold initialization (default: false)"); + +/* + * Isolate the ACPI-derived Windows _PS0 + _RST ordering from the remainder of + * the parity chronology. Phase 90 selects the hardware-proven Phase 75 power + * sequence while leaving every later Windows-parity operation unchanged. + */ +static bool g6ts_parity_linux_power; +module_param_named(parity_linux_power, g6ts_parity_linux_power, bool, 0444); +MODULE_PARM_DESC(parity_linux_power, + "Use the Phase 75 power/reset sequence in Windows parity mode"); + +/* + * The stable Windows SPB trace never chains another header from the still- + * asserted GPIO level. It waits about 500 us between header and body and + * services one complete response per interrupt. Phase 91 isolates that + * measured cadence from all initialization and contact-processing choices. + */ +static bool g6ts_windows_read_cadence; +module_param_named(windows_read_cadence, g6ts_windows_read_cadence, bool, 0444); +MODULE_PARM_DESC(windows_read_cadence, + "Use measured Windows header/body and one-response IRQ cadence"); + +/* + * Provider inputs are deliberately invalid by default. The Windows producer + * obtains these from display/posture state and persistent storage; an isolated + * parity boot may supply captured values for this exact machine, but the driver + * must never silently manufacture them. + */ +static int g6ts_parity_display_bitmap = -1; +module_param_named(parity_display_bitmap, g6ts_parity_display_bitmap, int, 0444); +MODULE_PARM_DESC(parity_display_bitmap, + "Windows A1 display bitmap; required by windows_init_parity (-1: unavailable)"); + +static int g6ts_parity_stitching_flag = -1; +module_param_named(parity_stitching_flag, g6ts_parity_stitching_flag, int, 0444); +MODULE_PARM_DESC(parity_stitching_flag, + "Windows A1 stitching flag; required by windows_init_parity (-1: unavailable)"); + +static int g6ts_parity_hinge_angle = -1; +module_param_named(parity_hinge_angle, g6ts_parity_hinge_angle, int, 0444); +MODULE_PARM_DESC(parity_hinge_angle, + "Windows A1 hinge-angle value; required by windows_init_parity (-1: unavailable)"); + +static int g6ts_parity_fast_host_id = -1; +module_param_named(parity_fast_host_id, g6ts_parity_fast_host_id, int, 0444); +MODULE_PARM_DESC(parity_fast_host_id, + "Windows feedback FastHostId (0..65535, -1: unavailable)"); + +/* + * Report 0x56 carries six bytes of device identity (Usage 0x03) and one + * boolean (Usage 0x09). The six bytes are repeated in GET_FEATURE 0x60 at + * offsets 20,24,28,32,36,40, but Windows sends 0x56 before its CFU owner + * requests 0x60. Require the owning platform value rather than changing the + * observed ordering or silently borrowing one machine's identity. + */ +static u8 g6ts_parity_report56_identity[G6TS_WINDOWS_REPORT56_ID_LEN]; +static unsigned int g6ts_parity_report56_identity_count; +module_param_array_named(parity_report56_identity, + g6ts_parity_report56_identity, byte, + &g6ts_parity_report56_identity_count, 0444); +MODULE_PARM_DESC(parity_report56_identity, + "Six Windows report-0x56 Usage-0x03 identity bytes"); + +static int g6ts_parity_report56_flag = -1; +module_param_named(parity_report56_flag, g6ts_parity_report56_flag, int, 0444); +MODULE_PARM_DESC(parity_report56_flag, + "Windows report-0x56 Usage-0x09 boolean (-1: unavailable)"); + +/* + * SurfaceCFUOverHid owns report 0x60/0x65 independently. Phase 84 leaves this + * false and stops before CFU. A later laboratory entry may enable the bounded + * inventory-only transaction after supplying the exact installed offer. + * There is deliberately no firmware-payload parameter or implementation. + */ +static bool g6ts_parity_cfu_inventory; +module_param_named(parity_cfu_inventory, g6ts_parity_cfu_inventory, bool, 0444); +MODULE_PARM_DESC(parity_cfu_inventory, + "Run Windows CFU inventory/offer check without payload transfer"); + +static u8 g6ts_parity_cfu_offer[G6TS_WINDOWS_CFU_OFFER_LEN]; +static unsigned int g6ts_parity_cfu_offer_count; +module_param_array_named(parity_cfu_offer, g6ts_parity_cfu_offer, byte, + &g6ts_parity_cfu_offer_count, 0444); +MODULE_PARM_DESC(parity_cfu_offer, + "Exact 16-byte installed Windows CFU offer (token byte is provider-owned)"); + +/* + * Phase 86 is the first end-to-end laboratory entry. It may admit Heat only + * after the evidence-gated Windows cold attach and bounded CFU inventory have + * both completed through the captured final report-0x73 boundary. Keeping + * this separate from windows_init_parity preserves Phase 84/85 as diagnostic + * stop points and prevents a partial attach from being mistaken for input + * readiness. + */ +static bool g6ts_parity_heat_input; +module_param_named(parity_heat_input, g6ts_parity_heat_input, bool, 0444); +MODULE_PARM_DESC(parity_heat_input, + "Admit Heat/input only after complete Windows init+CFU parity"); + +enum g6ts_recovery_path { + G6TS_RECOVERY_HARDWARE, + G6TS_RECOVERY_SOFTWARE, +}; + +static const u8 g6ts_header_cmd[8] = { + 0xeb, 0x00, 0x10, 0x00, 0xff, 0xff, 0xff, 0xff, +}; + +static const u8 g6ts_body_cmd[8] = { + 0xeb, 0x00, 0x10, 0x04, 0xff, 0xff, 0xff, 0xff, +}; + +/* Windows HID-over-SPI DEVICE_DESCRIPTOR request captured in ETW. */ +static const u8 g6ts_device_descriptor_cmd[8] = { + 0xe2, 0x00, 0x20, 0x00, DEVICE_DESCRIPTOR, 0x00, 0x00, 0x00, +}; + +static const u8 g6ts_report_descriptor_cmd[8] = { + 0xe2, 0x00, 0x20, 0x00, REPORT_DESCRIPTOR, 0x00, 0x00, 0x00, +}; + +static const u8 g6ts_mode_enable[] = { 0x01 }; +/* SHA-256 fc5772d4...0bd58af; metadata only, never a firmware payload. */ +static const u8 g6ts_sp11_cfu_offer[G6TS_WINDOWS_CFU_OFFER_LEN] = { + 0x00, 0x00, 0x12, 0x00, 0x89, 0x14, 0x00, 0x3f, + 0xff, 0xff, 0xff, 0xff, 0x04, 0x04, 0x75, 0x00, +}; + +static const u8 g6ts_mode_handshake[] = { + 0xbc, 0xe6, 0x4a, 0x2e, 0x86, 0x78, 0x00, +}; + +/* TouchPenProcessor project-0x0c83 sensor-row to NSR-bin mapping. */ +static const u8 g6ts_nsr_row_to_bin[G6TS_HEAT_ROWS] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, +}; + +struct g6ts_heat_frame { + struct g6ts_heat_record_header header; + u8 content[G6TS_HEAT_MAX_CONTENT_SIZE]; +}; + +static_assert(sizeof(struct g6ts_heat_record_header) == + G6TS_HEAT_RECORD_HEADER_SIZE); +static_assert(sizeof(struct g6ts_heat_info) == 48); +static_assert(sizeof(struct g6ts_heat_stats) == 112); + +struct g6ts_heat_device { + struct miscdevice miscdev; + /* Protects queue data and device lifetime state. */ + struct mutex lock; + wait_queue_head_t read_wait; + struct kref ref; + struct g6ts_heat_frame *frames; + unsigned int head; + unsigned int count; + u32 generation; + u32 sequence; + u64 records_enqueued; + u64 records_dropped; + u64 queue_flushes; + u64 oversize_drops; + u64 report_counts[4]; + atomic_t opened; + bool dead; +}; + +struct g6ts_a5_live_state { + u16 fast_host_id; + u8 sequence; + bool fast_host_id_valid; + bool cycle_saw_0x0d; +}; + +struct g6ts_contact { + u64 weighted_x; + u64 weighted_y; + u32 strength; + u32 sensor_x_q24; + u32 sensor_y_q24; + u16 pixels; + u16 x; + u16 y; + u16 output_x; + u16 output_y; + u8 peak_value; + u8 min_col; + u8 max_col; + u8 min_row; + u8 max_row; + s32 features_q12[G6TS_FEATURE_COUNT]; + s64 scores_q24[G6TS_CLASS_COUNT]; + u8 local_peak_count; + u8 strong_local_peak_count; + u8 shape_class; + bool shape_allowed; +}; + +struct g6ts_track { + u32 strength; + u16 raw_x; + u16 raw_y; + u16 output_x; + u16 output_y; + u16 pixels; + u32 sensor_x_q24; + u32 sensor_y_q24; + s32 sensor_velocity_x_q24; + s32 sensor_velocity_y_q24; + s16 velocity_x; + s16 velocity_y; + u16 age; + s64 score_history_q24[G6TS_WINDOWS_HISTORY_CAPACITY][G6TS_CLASS_COUNT]; + u8 missed; + u8 evidence; + u8 required_evidence; + u8 shape_class; + u8 windows_class; + u8 score_history_count; + bool active; + bool confirmed; +}; + +struct g6ts_assignment_workspace { + int cost[G6TS_ASSIGN_MAX][G6TS_ASSIGN_MAX]; + int u[G6TS_ASSIGN_MAX + 1]; + int v[G6TS_ASSIGN_MAX + 1]; + int p[G6TS_ASSIGN_MAX + 1]; + int way[G6TS_ASSIGN_MAX + 1]; + int minv[G6TS_ASSIGN_MAX + 1]; + bool used[G6TS_ASSIGN_MAX + 1]; + int active_slots[G6TS_MAX_CONTACTS]; +}; + +struct g6ts { + struct spi_device *spi; + struct input_dev *input; + struct g6ts_heat_device *heat; + struct hid_device *ipts_hid; + struct input_dev *pen_input; + struct touchscreen_properties prop; + struct touchscreen_properties pen_prop; + /* Serializes transport, initialization, recovery, and power changes. */ + struct mutex io_lock; + /* Serializes the Phase 84 IRQ enable depth across recovery and PM. */ + struct mutex irq_state_lock; + struct gpio_desc *interrupt_gpio; + struct gpio_desc *power_gpio; + struct gpio_desc *reset_gpio; + u8 *body; + u8 heatmap[G6TS_HEAT_SAMPLES]; + u8 heat_seen[G6TS_HEAT_SAMPLES]; + u8 heat_component[G6TS_HEAT_SAMPLES]; + u8 heat_work[G6TS_HEAT_SAMPLES]; + u16 heat_queue[G6TS_HEAT_SAMPLES]; + u16 nsr_bins[G6TS_NSR_BINS]; + struct g6ts_contact contacts[G6TS_MAX_CONTACTS]; + struct g6ts_track tracks[G6TS_MAX_CONTACTS]; + struct g6ts_assignment_workspace assignment; + struct delayed_work recovery_work; + struct delayed_work hid_rebind_work; + u8 last_header[HIDSPI_INPUT_HEADER_SIZE]; + u8 report_descriptor[G6TS_SP11_REPORT_DESCRIPTOR_LEN]; + u8 ipts_metadata[G6TS_IPTS_METADATA_LEN]; + u8 last_class; + u16 last_content_len; + u16 expected_report_descriptor_len; + u16 hid_product_id; + u8 last_content_id; + u32 hid_target_generation; + u32 hid_bound_generation; + u8 hid_rebind_failures; + /* Phase 72 Linux response content used by the combined experimental path. */ + u8 mode_config[G6TS_FEATURE_RESPONSE_LIMIT]; + u8 mode_config_len; + bool mode_config_valid; + int interrupt_irq; + atomic64_t interrupt_edges; + s64 handled_interrupt_edges; + u64 reset_notifications; + u64 recovery_successes; + u64 recovery_failures; + u64 hardware_recovery_attempts; + u64 software_recovery_attempts; + u64 software_recovery_fallbacks; + u64 reset_storm_escalations; + u64 host_fault_recoveries; + u64 irq_transport_errors; + u64 irq_protocol_errors; + u64 irq_drain_overflows; + u64 quiesced_empty_reads; + u64 cadence_single_response_irqs; + u64 ready_heat_frames; + u64 ready_verification_failures; + u64 report_counts[U8_MAX + 1]; + struct g6ts_a5_live_state a5; + u64 heat_feedback_sent; + u64 heat_feedback_phase_a; + u64 heat_feedback_phase_b; + u64 heat_frames; + u64 heat_errors; + u64 component_total; + u64 contact_total; + u64 weak_rejections; + u64 nsr_rejections; + u64 palm_rejections; + u64 assignment_matches; + u64 new_tracks; + u64 output_frames; + u64 output_contacts; + u64 processing_ns_total; + u64 processing_ns_max; + unsigned long last_reset_jiffies; + u8 nsr_bin_count; + enum g6ts_initialization_stage initialization_stage; + u8 recovery_fail_streak; + u8 rapid_reset_streak; + int last_host_fault; + enum g6ts_recovery_path recovery_path; + bool nsr_valid; + bool report_descriptor_valid; + bool ipts_metadata_valid; + bool ipts_hid_ready; + bool awaiting_ready_heat; + bool mode_enabled; + bool irq_enabled; + bool fatal_transport_error; + bool stopping; + bool quiescing; + bool parity_feedback_required; + bool parity_config_owner_required; + bool parity_cfu_owner_required; + bool parity_cfu_branch_required; + bool parity_heat_owner_required; + u8 parity_feature73_early[2]; + u8 parity_feature73_late[2]; + u8 parity_feature06_prefix[16]; + u8 parity_cfu_version_prefix[12]; + u8 parity_cfu_offer_response[G6TS_WINDOWS_CFU_OFFER_LEN]; + bool init_get_feature_dumped[G6TS_INIT_STAGE_COUNT]; +}; + +static bool g6ts_is_quiescing(const struct g6ts *ts) +{ + return READ_ONCE(ts->stopping) || READ_ONCE(ts->quiescing); +} + +static bool g6ts_is_raw_export_report(u8 report_id) +{ + switch (report_id) { + case G6TS_RAW_SIDEBAND_REPORT_07: + case G6TS_RAW_HEAT_REPORT_0B: + case G6TS_RAW_HEAT_REPORT_0C: + case G6TS_RAW_HEAT_REPORT_0D: + case G6TS_RAW_HEAT_REPORT_1A: + case G6TS_RAW_SIDEBAND_REPORT_6E: + return true; + default: + return false; + } +} + +/* + * iptsd consumes only the four core DFT reports. Keep sideband reports on the + * diagnostic ABI: report 0x6e can contain a device or pen identifier and is + * not needed by the stylus decoder. + */ +static bool g6ts_is_ipts_hid_report(u8 report_id) +{ + switch (report_id) { + case G6TS_RAW_HEAT_REPORT_0B: + case G6TS_RAW_HEAT_REPORT_0C: + case G6TS_RAW_HEAT_REPORT_0D: + case G6TS_RAW_HEAT_REPORT_1A: + return true; + default: + return false; + } +} + +/* io_lock is held by every transport-generation caller. */ +static void g6ts_hid_generation_boundary(struct g6ts *ts) +{ + ts->hid_target_generation++; + if (!ts->hid_target_generation) + ts->hid_target_generation = 1; + ts->hid_rebind_failures = 0; + + /* Never destroy hidraw from a feature ioctl or IRQ/reset call stack. */ + mod_delayed_work(system_wq, &ts->hid_rebind_work, 0); +} + +static void g6ts_heat_device_release(struct kref *ref) +{ + struct g6ts_heat_device *heat = + container_of(ref, struct g6ts_heat_device, ref); + + kvfree(heat->frames); + kfree(heat); +} + +static void g6ts_heat_enqueue_locked(struct g6ts_heat_device *heat, + u8 report_id, u8 flags, + const u8 *content, u16 content_len) +{ + struct g6ts_heat_frame *frame; + unsigned int tail; + + if (heat->count == G6TS_HEAT_QUEUE_CAPACITY) { + heat->head = (heat->head + 1) % G6TS_HEAT_QUEUE_CAPACITY; + heat->count--; + heat->records_dropped++; + } + + tail = (heat->head + heat->count) % G6TS_HEAT_QUEUE_CAPACITY; + frame = &heat->frames[tail]; + frame->header.magic = cpu_to_le32(G6TS_HEAT_RECORD_MAGIC); + frame->header.abi_version = cpu_to_le16(G6TS_HEAT_ABI_VERSION); + frame->header.header_len = cpu_to_le16(sizeof(frame->header)); + frame->header.record_len = + cpu_to_le32(sizeof(frame->header) + content_len); + frame->header.generation = cpu_to_le32(heat->generation); + frame->header.timestamp_ns = cpu_to_le64(ktime_get_ns()); + frame->header.sequence = cpu_to_le32(heat->sequence++); + frame->header.content_len = cpu_to_le16(content_len); + frame->header.report_id = report_id; + frame->header.flags = flags; + if (content_len) + memcpy(frame->content, content, content_len); + + heat->count++; + heat->records_enqueued++; + switch (report_id) { + case G6TS_RAW_HEAT_REPORT_0B: + heat->report_counts[0]++; + break; + case G6TS_RAW_HEAT_REPORT_0C: + heat->report_counts[1]++; + break; + case G6TS_RAW_HEAT_REPORT_0D: + heat->report_counts[2]++; + break; + case G6TS_RAW_HEAT_REPORT_1A: + heat->report_counts[3]++; + break; + } +} + +static void g6ts_heat_enqueue(struct g6ts *ts, u8 report_id, + const u8 *content, u16 content_len) +{ + struct g6ts_heat_device *heat = ts->heat; + + if (!heat) + return; + + mutex_lock(&heat->lock); + if (heat->dead) { + mutex_unlock(&heat->lock); + return; + } + if (content_len > G6TS_HEAT_MAX_CONTENT_SIZE) { + heat->oversize_drops++; + mutex_unlock(&heat->lock); + return; + } + g6ts_heat_enqueue_locked(heat, report_id, 0, content, content_len); + mutex_unlock(&heat->lock); + wake_up_interruptible(&heat->read_wait); +} + +static void g6ts_heat_generation_boundary(struct g6ts *ts, u8 flags) +{ + struct g6ts_heat_device *heat = ts->heat; + + ts->a5.cycle_saw_0x0d = false; + g6ts_hid_generation_boundary(ts); + if (!heat) + return; + + mutex_lock(&heat->lock); + if (heat->dead) { + mutex_unlock(&heat->lock); + return; + } + heat->generation++; + if (!heat->generation) + heat->generation = 1; + heat->head = 0; + heat->count = 0; + heat->queue_flushes++; + g6ts_heat_enqueue_locked(heat, 0, flags, NULL, 0); + mutex_unlock(&heat->lock); + wake_up_interruptible(&heat->read_wait); +} + +static bool g6ts_heat_read_ready(struct g6ts_heat_device *heat) +{ + return READ_ONCE(heat->count) || READ_ONCE(heat->dead); +} + +static int g6ts_heat_open(struct inode *inode, struct file *file) +{ + struct miscdevice *miscdev = file->private_data; + struct g6ts_heat_device *heat = + container_of(miscdev, struct g6ts_heat_device, miscdev); + + if (!kref_get_unless_zero(&heat->ref)) + return -ENODEV; + if (atomic_cmpxchg(&heat->opened, 0, 1)) { + kref_put(&heat->ref, g6ts_heat_device_release); + return -EBUSY; + } + + mutex_lock(&heat->lock); + if (heat->dead) { + mutex_unlock(&heat->lock); + atomic_set(&heat->opened, 0); + kref_put(&heat->ref, g6ts_heat_device_release); + return -ENODEV; + } + file->private_data = heat; + mutex_unlock(&heat->lock); + return nonseekable_open(inode, file); +} + +static int g6ts_heat_release(struct inode *inode, struct file *file) +{ + struct g6ts_heat_device *heat = file->private_data; + + atomic_set(&heat->opened, 0); + kref_put(&heat->ref, g6ts_heat_device_release); + return 0; +} + +static ssize_t g6ts_heat_read(struct file *file, char __user *buffer, + size_t size, loff_t *offset) +{ + struct g6ts_heat_device *heat = file->private_data; + struct g6ts_heat_frame *frame; + size_t content_len; + size_t record_len; + int ret; + + for (;;) { + if (!(file->f_flags & O_NONBLOCK)) { + ret = wait_event_interruptible(heat->read_wait, + g6ts_heat_read_ready(heat)); + if (ret) + return ret; + } + + mutex_lock(&heat->lock); + if (heat->count) + break; + if (heat->dead) { + mutex_unlock(&heat->lock); + return 0; + } + mutex_unlock(&heat->lock); + if (file->f_flags & O_NONBLOCK) + return -EAGAIN; + } + + frame = &heat->frames[heat->head]; + record_len = le32_to_cpu(frame->header.record_len); + content_len = le16_to_cpu(frame->header.content_len); + if (size < record_len) { + ret = -EMSGSIZE; + goto out_unlock; + } + if (copy_to_user(buffer, &frame->header, sizeof(frame->header)) || + (content_len && + copy_to_user(buffer + sizeof(frame->header), frame->content, + content_len))) { + ret = -EFAULT; + goto out_unlock; + } + + heat->head = (heat->head + 1) % G6TS_HEAT_QUEUE_CAPACITY; + heat->count--; + mutex_unlock(&heat->lock); + return record_len; + +out_unlock: + mutex_unlock(&heat->lock); + return ret; +} + +static __poll_t g6ts_heat_poll(struct file *file, poll_table *wait) +{ + struct g6ts_heat_device *heat = file->private_data; + __poll_t mask = 0; + + poll_wait(file, &heat->read_wait, wait); + mutex_lock(&heat->lock); + if (heat->count) + mask |= EPOLLIN | EPOLLRDNORM; + if (heat->dead) + mask |= EPOLLHUP; + mutex_unlock(&heat->lock); + return mask; +} + +static long g6ts_heat_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct g6ts_heat_device *heat = file->private_data; + void __user *argp = (void __user *)arg; + + switch (cmd) { + case G6TS_HEAT_IOC_GET_INFO: { + struct g6ts_heat_info info = { + .abi_version = cpu_to_le16(G6TS_HEAT_ABI_VERSION), + .struct_size = cpu_to_le16(sizeof(info)), + .record_header_size = + cpu_to_le16(sizeof(struct g6ts_heat_record_header)), + .max_content_size = + cpu_to_le32(G6TS_HEAT_MAX_CONTENT_SIZE), + .queue_capacity = + cpu_to_le32(G6TS_HEAT_QUEUE_CAPACITY), + .supported_record_flags = + cpu_to_le64(G6TS_HEAT_RECORD_F_RESET | + G6TS_HEAT_RECORD_F_SUSPEND | + G6TS_HEAT_RECORD_F_TRANSPORT_FAULT), + }; + + return copy_to_user(argp, &info, sizeof(info)) ? -EFAULT : 0; + } + case G6TS_HEAT_IOC_GET_STATS: { + struct g6ts_heat_stats stats = { + .abi_version = cpu_to_le16(G6TS_HEAT_ABI_VERSION), + .struct_size = cpu_to_le16(sizeof(stats)), + .queue_capacity = + cpu_to_le32(G6TS_HEAT_QUEUE_CAPACITY), + }; + + mutex_lock(&heat->lock); + stats.generation = cpu_to_le32(heat->generation); + stats.queued_records = cpu_to_le32(heat->count); + stats.records_enqueued = cpu_to_le64(heat->records_enqueued); + stats.records_dropped = cpu_to_le64(heat->records_dropped); + stats.queue_flushes = cpu_to_le64(heat->queue_flushes); + stats.oversize_drops = cpu_to_le64(heat->oversize_drops); + stats.report_0b = cpu_to_le64(heat->report_counts[0]); + stats.report_0c = cpu_to_le64(heat->report_counts[1]); + stats.report_0d = cpu_to_le64(heat->report_counts[2]); + stats.report_1a = cpu_to_le64(heat->report_counts[3]); + mutex_unlock(&heat->lock); + + return copy_to_user(argp, &stats, sizeof(stats)) ? -EFAULT : 0; + } + default: + return -ENOTTY; + } +} + +static const struct file_operations g6ts_heat_fops = { + .owner = THIS_MODULE, + .open = g6ts_heat_open, + .release = g6ts_heat_release, + .read = g6ts_heat_read, + .poll = g6ts_heat_poll, + .unlocked_ioctl = g6ts_heat_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = compat_ptr_ioctl, +#endif +}; + +static void g6ts_heat_unregister(void *data) +{ + struct g6ts_heat_device *heat = data; + + misc_deregister(&heat->miscdev); + mutex_lock(&heat->lock); + heat->dead = true; + heat->head = 0; + heat->count = 0; + mutex_unlock(&heat->lock); + wake_up_interruptible(&heat->read_wait); + kref_put(&heat->ref, g6ts_heat_device_release); +} + +static int g6ts_heat_register(struct g6ts *ts) +{ + struct g6ts_heat_device *heat; + int ret; + + heat = kzalloc_obj(*heat); + if (!heat) + return -ENOMEM; + heat->frames = kvcalloc(G6TS_HEAT_QUEUE_CAPACITY, + sizeof(*heat->frames), GFP_KERNEL); + if (!heat->frames) { + kfree(heat); + return -ENOMEM; + } + + mutex_init(&heat->lock); + init_waitqueue_head(&heat->read_wait); + kref_init(&heat->ref); + atomic_set(&heat->opened, 0); + heat->generation = 1; + heat->sequence = 1; + heat->miscdev.minor = MISC_DYNAMIC_MINOR; + heat->miscdev.name = "g6ts-heat"; + heat->miscdev.fops = &g6ts_heat_fops; + heat->miscdev.parent = &ts->spi->dev; + + ret = misc_register(&heat->miscdev); + if (ret) { + kref_put(&heat->ref, g6ts_heat_device_release); + return ret; + } + ts->heat = heat; + ret = devm_add_action_or_reset(&ts->spi->dev, g6ts_heat_unregister, + heat); + if (ret) + ts->heat = NULL; + return ret; +} + +static const char * +g6ts_initialization_stage_name(enum g6ts_initialization_stage stage) +{ + switch (stage) { + case G6TS_INIT_IDLE: + return "idle"; + case G6TS_INIT_WINDOWS_POWER_PS0: + return "windows-power-ps0"; + case G6TS_INIT_WINDOWS_RESET_METHOD: + return "windows-reset-method"; + case G6TS_INIT_RESET_RESPONSE: + return "reset-response"; + case G6TS_INIT_DEVICE_DESCRIPTOR: + return "device-descriptor"; + case G6TS_INIT_REPORT_DESCRIPTOR: + return "report-descriptor"; + case G6TS_INIT_WINDOWS_EARLY_FEATURE73: + return "windows-early-feature73"; + case G6TS_INIT_WINDOWS_HEAT_CAPS06: + return "windows-heat-caps06"; + case G6TS_INIT_WINDOWS_FEEDBACK_REQUIRED: + return "windows-feedback-required"; + case G6TS_INIT_WINDOWS_FEEDBACK_A1: + return "windows-feedback-a1"; + case G6TS_INIT_WINDOWS_FEEDBACK_A5: + return "windows-feedback-a5"; + case G6TS_INIT_WINDOWS_SET_FEATURE05: + return "windows-set-feature05"; + case G6TS_INIT_WINDOWS_CONFIG_OWNER_REQUIRED: + return "windows-config-owner-required"; + case G6TS_INIT_WINDOWS_GET_FEATURE70: + return "windows-get-feature70"; + case G6TS_INIT_WINDOWS_SET_FEATURE70: + return "windows-set-feature70"; + case G6TS_INIT_WINDOWS_SET_FEATURE56: + return "windows-set-feature56"; + case G6TS_INIT_WINDOWS_CFU_OWNER_REQUIRED: + return "windows-cfu-owner-required"; + case G6TS_INIT_WINDOWS_CFU_GET_VERSION: + return "windows-cfu-get-version"; + case G6TS_INIT_WINDOWS_CFU_START_TRANSACTION: + return "windows-cfu-start-transaction"; + case G6TS_INIT_WINDOWS_CFU_START_LIST: + return "windows-cfu-start-list"; + case G6TS_INIT_WINDOWS_CFU_OFFER: + return "windows-cfu-offer"; + case G6TS_INIT_WINDOWS_CFU_BRANCH_REQUIRED: + return "windows-cfu-branch-required"; + case G6TS_INIT_WINDOWS_CFU_END_LIST: + return "windows-cfu-end-list"; + case G6TS_INIT_WINDOWS_FINAL_FEATURE73: + return "windows-final-feature73"; + case G6TS_INIT_WINDOWS_HEAT_OWNER_REQUIRED: + return "windows-heat-owner-required"; + case G6TS_INIT_SET_FEATURE05: + return "set-feature05"; + case G6TS_INIT_GET_FEATURE70: + return "get-feature70"; + case G6TS_INIT_SET_FEATURE70: + return "set-feature70"; + case G6TS_INIT_SET_FEATURE56: + return "set-feature56"; + case G6TS_INIT_WAIT_HEAT: + return "wait-heat"; + } + + return "invalid"; +} + +static const char *g6ts_profile_name(void) +{ + if (g6ts_windows_init_parity) + return "windows-init-parity"; + if (g6ts_ipts_irq_cadence) + return "phase84-ipts-irq-cadence"; + if (g6ts_ipts_minimal_init) + return "phase83-ipts-minimal"; + if (g6ts_ready_quiesce && g6ts_feature70_one_byte) + return "phase82"; + if (g6ts_ready_quiesce) + return "phase81"; + if (g6ts_host_fault_recovery) + return "phase80"; + if (g6ts_feature70_one_byte) + return "phase79"; + if (g6ts_reset_storm_breaker) + return "phase78"; + if (g6ts_reset_recovery_v2) + return "phase77"; + if (g6ts_behavior_v2) + return "phase76"; + if (g6ts_windows_orchestrator) + return "windows-orchestrator"; + return "phase75"; +} + +static ssize_t behavior_stats_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct g6ts *ts = dev_get_drvdata(dev); + u64 average_ns; + ssize_t length; + + mutex_lock(&ts->io_lock); + average_ns = ts->heat_frames ? + div64_u64(ts->processing_ns_total, ts->heat_frames) : 0; + length = sysfs_emit(buf, + "profile=%s\n" + "ipts_minimal_init=%u\n" + "ipts_irq_cadence=%u\n" + "irq_enabled=%u\n" + "irq_trigger_type=%u\n" + "interrupt_irqs=%lld\n" + "handled_interrupt_irqs=%lld\n" + "parity_linux_power=%u\n" + "windows_read_cadence=%u\n" + "initialization_stage=%s\n" + "parity_feedback_required=%u\n" + "parity_config_owner_required=%u\n" + "parity_cfu_owner_required=%u\n" + "parity_cfu_branch_required=%u\n" + "parity_heat_owner_required=%u\n" + "parity_feature73_early=%*ph\n" + "parity_feature73_late=%*ph\n" + "parity_feature06_prefix=%*ph\n" + "parity_cfu_version_prefix=%*ph\n" + "parity_cfu_offer_response=%*ph\n" + "last_header=%4ph\n" + "last_class=%u\n" + "last_content_id=%u\n" + "last_content_len=%u\n" + "mode_enabled=%u\n" + "awaiting_ready_heat=%u\n" + "heat_frames=%llu\n" + "heat_errors=%llu\n" + "components=%llu\n" + "accepted_contacts=%llu\n" + "weak_rejections=%llu\n" + "nsr_rejections=%llu\n" + "palm_rejections=%llu\n" + "assignment_matches=%llu\n" + "new_tracks=%llu\n" + "output_frames=%llu\n" + "output_contacts=%llu\n" + "processing_average_ns=%llu\n" + "processing_max_ns=%llu\n" + "panel_resets=%llu\n" + "recovery_successes=%llu\n" + "recovery_failures=%llu\n" + "hardware_recovery_attempts=%llu\n" + "software_recovery_attempts=%llu\n" + "software_recovery_fallbacks=%llu\n" + "reset_storm_escalations=%llu\n" + "rapid_reset_streak=%u\n" + "host_fault_recoveries=%llu\n" + "irq_transport_errors=%llu\n" + "irq_protocol_errors=%llu\n" + "irq_drain_overflows=%llu\n" + "quiesced_empty_reads=%llu\n" + "cadence_single_response_irqs=%llu\n" + "last_host_fault=%d\n" + "ready_heat_frames=%llu\n" + "ready_verification_failures=%llu\n", + g6ts_profile_name(), g6ts_ipts_minimal_init, + g6ts_ipts_irq_cadence, + READ_ONCE(ts->irq_enabled), + irq_get_trigger_type(ts->interrupt_irq), + atomic64_read(&ts->interrupt_edges), + ts->handled_interrupt_edges, + g6ts_parity_linux_power, + g6ts_windows_read_cadence, + g6ts_initialization_stage_name(ts->initialization_stage), + ts->parity_feedback_required, + ts->parity_config_owner_required, + ts->parity_cfu_owner_required, + ts->parity_cfu_branch_required, + ts->parity_heat_owner_required, + (int)sizeof(ts->parity_feature73_early), + ts->parity_feature73_early, + (int)sizeof(ts->parity_feature73_late), + ts->parity_feature73_late, + (int)sizeof(ts->parity_feature06_prefix), + ts->parity_feature06_prefix, + (int)sizeof(ts->parity_cfu_version_prefix), + ts->parity_cfu_version_prefix, + (int)sizeof(ts->parity_cfu_offer_response), + ts->parity_cfu_offer_response, + ts->last_header, ts->last_class, + ts->last_content_id, ts->last_content_len, + READ_ONCE(ts->mode_enabled), ts->awaiting_ready_heat, + ts->heat_frames, ts->heat_errors, + ts->component_total, ts->contact_total, + ts->weak_rejections, ts->nsr_rejections, + ts->palm_rejections, ts->assignment_matches, + ts->new_tracks, ts->output_frames, + ts->output_contacts, average_ns, + ts->processing_ns_max, ts->reset_notifications, + ts->recovery_successes, ts->recovery_failures, + ts->hardware_recovery_attempts, + ts->software_recovery_attempts, + ts->software_recovery_fallbacks, + ts->reset_storm_escalations, + ts->rapid_reset_streak, + ts->host_fault_recoveries, + ts->irq_transport_errors, + ts->irq_protocol_errors, + ts->irq_drain_overflows, + ts->quiesced_empty_reads, + ts->cadence_single_response_irqs, + ts->last_host_fault, + ts->ready_heat_frames, + ts->ready_verification_failures); + mutex_unlock(&ts->io_lock); + + return length; +} +static DEVICE_ATTR_RO(behavior_stats); + +static ssize_t report_counts_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct g6ts *ts = dev_get_drvdata(dev); + ssize_t length = 0; + unsigned int report_id; + + mutex_lock(&ts->io_lock); + for (report_id = 0; report_id <= U8_MAX; report_id++) { + if (!ts->report_counts[report_id]) + continue; + length += sysfs_emit_at(buf, length, "0x%02x %llu\n", + report_id, ts->report_counts[report_id]); + if (length >= PAGE_SIZE - 1) + break; + } + mutex_unlock(&ts->io_lock); + + return length; +} +static DEVICE_ATTR_RO(report_counts); + +static ssize_t feedback_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct g6ts *ts = dev_get_drvdata(dev); + ssize_t length; + + mutex_lock(&ts->io_lock); + length = sysfs_emit(buf, + "seq %u\n" + "sent %llu phase_a %llu phase_b %llu\n", + ts->a5.sequence, ts->heat_feedback_sent, + ts->heat_feedback_phase_a, + ts->heat_feedback_phase_b); + mutex_unlock(&ts->io_lock); + + return length; +} +static DEVICE_ATTR_RO(feedback_state); + +static struct attribute *g6ts_attributes[] = { + &dev_attr_behavior_stats.attr, + &dev_attr_report_counts.attr, + &dev_attr_feedback_state.attr, + NULL, +}; + +static const struct attribute_group g6ts_attribute_group = { + .attrs = g6ts_attributes, +}; + +static int g6ts_acpi_method(struct device *dev, const char *method) +{ + acpi_handle handle = ACPI_HANDLE(dev); + acpi_status status; + + if (!handle) + return -ENODEV; + status = acpi_evaluate_object(handle, (char *)method, NULL, NULL); + return ACPI_FAILURE(status) ? -EIO : 0; +} + +static int g6ts_power_on(struct g6ts *ts) +{ + int ret; + + if (ts->power_gpio && ts->reset_gpio) { + gpiod_set_value_cansleep(ts->reset_gpio, 0); + gpiod_set_value_cansleep(ts->power_gpio, 1); + msleep(500); + gpiod_set_value_cansleep(ts->reset_gpio, 1); + msleep(300); + return 0; + } + + ret = g6ts_acpi_method(&ts->spi->dev, "_PS0"); + if (ret) + return dev_err_probe(&ts->spi->dev, ret, + "ACPI _PS0 failed\n"); + + ret = g6ts_acpi_method(&ts->spi->dev, "_RST"); + if (ret) { + g6ts_acpi_method(&ts->spi->dev, "_PS3"); + return dev_err_probe(&ts->spi->dev, ret, + "ACPI _RST failed\n"); + } + + return 0; +} + +/* + * Reproduce the GPIO effects and delays in the SP11 GTCH _PS0 followed by + * _RST. The production helper above retains its hardware-validated sequence; + * only the input-disabled parity path uses this ACPI-derived ordering. + */ +static int g6ts_windows_power_on(struct g6ts *ts) +{ + int ret; + + if (!ts->power_gpio || !ts->reset_gpio) { + ts->initialization_stage = G6TS_INIT_WINDOWS_POWER_PS0; + ret = g6ts_acpi_method(&ts->spi->dev, "_PS0"); + if (ret) + return dev_err_probe(&ts->spi->dev, ret, + "ACPI _PS0 failed\n"); + + ts->initialization_stage = G6TS_INIT_WINDOWS_RESET_METHOD; + ret = g6ts_acpi_method(&ts->spi->dev, "_RST"); + if (ret) { + g6ts_acpi_method(&ts->spi->dev, "_PS3"); + return dev_err_probe(&ts->spi->dev, ret, + "ACPI _RST failed\n"); + } + return 0; + } + + ts->initialization_stage = G6TS_INIT_WINDOWS_POWER_PS0; + gpiod_set_value_cansleep(ts->power_gpio, 1); + msleep(500); + gpiod_set_value_cansleep(ts->reset_gpio, 1); + + ts->initialization_stage = G6TS_INIT_WINDOWS_RESET_METHOD; + gpiod_set_value_cansleep(ts->reset_gpio, 0); + msleep(300); + gpiod_set_value_cansleep(ts->reset_gpio, 1); + return 0; +} + +static int g6ts_power_off(struct g6ts *ts) +{ + if (ts->power_gpio && ts->reset_gpio) { + gpiod_set_value_cansleep(ts->reset_gpio, 0); + usleep_range(10000, 12000); + gpiod_set_value_cansleep(ts->power_gpio, 0); + return 0; + } + + return g6ts_acpi_method(&ts->spi->dev, "_PS3"); +} + +/* + * Submit RX first and TX second through the controller's SP11 QSPI pairing + * path. The ordering and 1-4-4 lane selection match the Windows GPI capture. + */ +static int g6ts_dma_read_pair(struct g6ts *ts, const u8 cmd[8], + void *rx, size_t rx_len) +{ + struct spi_transfer xfers[2] = { + { + .tx_buf = cmd, + .len = 8, + .speed_hz = G6TS_SPI_HZ, + .bits_per_word = 8, + .tx_nbits = SPI_NBITS_QUAD, + }, { + .rx_buf = rx, + .len = rx_len, + .speed_hz = G6TS_SPI_HZ, + .bits_per_word = 8, + .rx_nbits = SPI_NBITS_QUAD, + }, + }; + struct spi_message msg; + + spi_message_init_with_transfers(&msg, xfers, ARRAY_SIZE(xfers)); + return spi_sync(ts->spi, &msg); +} + +static int g6ts_dma_output(struct g6ts *ts, const void *buf, size_t len) +{ + struct spi_transfer xfer = { + .tx_buf = buf, + .len = len, + .speed_hz = G6TS_SPI_HZ, + .bits_per_word = 8, + .tx_nbits = SPI_NBITS_QUAD, + }; + struct spi_message msg; + + spi_message_init_with_transfers(&msg, &xfer, 1); + return spi_sync(ts->spi, &msg); +} + +static int g6ts_dma_hidspi_output(struct g6ts *ts, u8 report_type, + u8 content_id, const u8 *content, + size_t content_len) +{ + u8 packet[72] = { 0xe2, 0x00, 0x20, 0x00 }; + size_t packet_len; + + if (content_len > sizeof(packet) - 8) + return -E2BIG; + + packet[4] = report_type; + put_unaligned_le16(content_len, &packet[5]); + packet[7] = content_id; + if (content_len) + memcpy(&packet[8], content, content_len); + packet_len = round_up(8 + content_len, 4); + + dev_dbg(&ts->spi->dev, + "G6TS DMA output type=%u id=%#02x content_len=%zu wire=%*ph\n", + report_type, content_id, content_len, (int)packet_len, packet); + return g6ts_dma_output(ts, packet, packet_len); +} + +static int g6ts_pending(struct g6ts *ts) +{ + return gpiod_get_value_cansleep(ts->interrupt_gpio); +} + +static bool g6ts_has_unread_response(struct g6ts *ts) +{ + int pending = g6ts_pending(ts); + + return pending > 0 || + atomic64_read(&ts->interrupt_edges) > ts->handled_interrupt_edges; +} + +static irqreturn_t g6ts_interrupt_edge(int irq, void *data) +{ + struct g6ts *ts = data; + + atomic64_inc(&ts->interrupt_edges); + return IRQ_WAKE_THREAD; +} + +/* Phase 84 owns one IRQ-disable depth while initialization is synchronous. */ +static void g6ts_ipts_irq_disable_nosync(struct g6ts *ts) +{ + if (!g6ts_ipts_irq_cadence) + return; + + mutex_lock(&ts->irq_state_lock); + if (ts->irq_enabled) { + ts->irq_enabled = false; + disable_irq_nosync(ts->interrupt_irq); + } + mutex_unlock(&ts->irq_state_lock); +} + +/* Never call this synchronous form from either IRQ handler. */ +static void g6ts_ipts_irq_disable_sync(struct g6ts *ts) +{ + if (!g6ts_ipts_irq_cadence) + return; + + g6ts_ipts_irq_disable_nosync(ts); + synchronize_irq(ts->interrupt_irq); +} + +static void g6ts_ipts_irq_enable_runtime(struct g6ts *ts) +{ + if (!g6ts_ipts_irq_cadence) + return; + + mutex_lock(&ts->irq_state_lock); + if (!ts->irq_enabled && READ_ONCE(ts->mode_enabled) && + !g6ts_is_quiescing(ts)) { + /* Publish ownership before the level-low IRQ can wake its thread. */ + ts->irq_enabled = true; + enable_irq(ts->interrupt_irq); + } + mutex_unlock(&ts->irq_state_lock); +} + +static int g6ts_wait_pending(struct g6ts *ts, unsigned int timeout_ms) +{ + unsigned long deadline = jiffies + msecs_to_jiffies(timeout_ms); + int value; + + do { + value = g6ts_pending(ts); + if (value < 0 || value || + atomic64_read(&ts->interrupt_edges) > + ts->handled_interrupt_edges) + return value < 0 ? value : 0; + usleep_range(1000, 2000); + } while (time_before(jiffies, deadline)); + + return -ETIMEDOUT; +} + +static void g6ts_clear_last_response(struct g6ts *ts) +{ + ts->last_class = 0xff; + ts->last_content_len = 0; + ts->last_content_id = 0xff; +} + +static int g6ts_extract_nsr_metadata(struct g6ts *ts, const u8 *section, + size_t section_len) +{ + size_t position = 7; + + /* Windows starts its nested metadata dispatcher at section byte seven. */ + while (position < section_len) { + size_t payload_len, record_end; + const u8 *record; + unsigned int count, i; + + if (section_len - position < 4) + return -EPROTO; + record = section + position; + payload_len = get_unaligned_le16(record + 2); + if (payload_len > section_len - position - 4) + return -EPROTO; + record_end = position + 4 + payload_len; + + if (record[0] == 0x04) { + if (ts->nsr_valid || payload_len < 4) + return -EPROTO; + count = record[4]; + if (count > G6TS_NSR_BINS || + count > (payload_len - 4) / 4) + return -EPROTO; + memset(ts->nsr_bins, 0, sizeof(ts->nsr_bins)); + for (i = 0; i < count; i++) { + u16 value = get_unaligned_le16(record + 8 + i * 4); + + ts->nsr_bins[i] = value; + } + ts->nsr_bin_count = count; + ts->nsr_valid = true; + } + position = record_end; + } + + return 0; +} + +static int g6ts_extract_heatmap(struct g6ts *ts, const u8 *content, + size_t content_len) +{ + size_t container_end, offset; + u32 container_len; + bool found = false; + + /* + * Report 0x12 begins with a two-byte scan time, followed by a Heat + * container. Its seven-byte container header is followed by length- + * prefixed sections. Windows asks IHeatFrameRawData for section 0x0100. + */ + if (content_len < 9) + return -EMSGSIZE; + container_len = get_unaligned_le32(content + 2); + if (container_len < 7 || container_len > content_len - 2) + return -EPROTO; + container_end = 2 + container_len; + offset = 9; + ts->nsr_valid = false; + ts->nsr_bin_count = 0; + + while (offset < container_end) { + const u8 *section = content + offset; + size_t section_end, position; + u32 section_len; + u16 section_type; + u32 written = 0; + + if (container_end - offset < 8) + return -EPROTO; + section_len = get_unaligned_le32(section); + if (section_len < 8 || section_len > container_end - offset) + return -EPROTO; + section_end = offset + section_len; + section_type = get_unaligned_le16(section + 4); + + if (section_type == G6TS_METADATA_SECTION) { + int ret = g6ts_extract_nsr_metadata(ts, section, + section_len); + + if (ret) + return ret; + offset = section_end; + continue; + } + if (section_type != G6TS_HEAT_SECTION) { + offset = section_end; + continue; + } + if (found || section[6] != 1 || section[7] != 8) + return -EPROTO; + + memset(ts->heatmap, 0, sizeof(ts->heatmap)); + memset(ts->heat_seen, 0, sizeof(ts->heat_seen)); + position = offset + 8; + while (position < section_end) { + u32 destination, count; + u32 i; + + if (section_end - position < 8) + return -EPROTO; + destination = get_unaligned_le32(content + position); + count = get_unaligned_le32(content + position + 4); + position += 8; + if (count > section_end - position || + count > G6TS_HEAT_SAMPLES || + destination > G6TS_HEAT_SAMPLES - count) + return -EPROTO; + for (i = 0; i < count; i++) { + if (ts->heat_seen[destination + i]) + return -EPROTO; + ts->heat_seen[destination + i] = 1; + } + memcpy(ts->heatmap + destination, content + position, count); + written += count; + position += count; + } + if (written != G6TS_HEAT_SAMPLES) + return -EPROTO; + found = true; + offset = section_end; + } + + return found ? 0 : -ENOENT; +} + +static bool g6ts_heat_active(const struct g6ts *ts, unsigned int index) +{ + return ts->heatmap[index] <= G6TS_HEAT_ACTIVE_MAX; +} + +static void g6ts_store_contact(struct g6ts *ts, + const struct g6ts_contact *contact, + unsigned int *contact_count) +{ + unsigned int weakest = 0; + unsigned int i; + + if (*contact_count < G6TS_MAX_CONTACTS) { + ts->contacts[(*contact_count)++] = *contact; + return; + } + + for (i = 1; i < G6TS_MAX_CONTACTS; i++) + if (ts->contacts[i].strength < ts->contacts[weakest].strength) + weakest = i; + if (contact->strength > ts->contacts[weakest].strength) + ts->contacts[weakest] = *contact; +} + +static s32 g6ts_signal_q12(u8 value) +{ + s32 signal_q24 = G6TS_SIGNAL_INTERCEPT_Q24 - + value * G6TS_SIGNAL_STEP_Q24; + + return (signal_q24 + BIT(G6TS_CLASSIFIER_SHIFT - 1)) >> + G6TS_CLASSIFIER_SHIFT; +} + +/* + * FUN_180047078 recomputes the normal output centroid relative to project + * baseline index 171. On the ordinary zero-context path captured for project + * 0x0c83, empty cells outside the thresholded component cannot have positive + * weight against that baseline. The expanded-window traversal therefore + * reduces exactly to this component-local weighted centroid. Keep the + * detector centroid in contact->x/y for assignment and place this later + * output-stage position in contact->output_x/y. + */ +static void g6ts_phase76_output_centroid(struct g6ts *ts, + struct g6ts_contact *contact) +{ + u64 weighted_x = 0, weighted_y = 0; + u64 weight_total = 0; + unsigned int index; + + for (index = 0; index < G6TS_HEAT_SAMPLES; index++) { + u8 value; + u32 weight; + + if (!ts->heat_component[index]) + continue; + value = ts->heatmap[index]; + if (value >= G6TS_WINDOWS_CENTROID_BASELINE) + continue; + weight = G6TS_WINDOWS_CENTROID_BASELINE - value; + weight_total += weight; + weighted_x += (u64)(index % G6TS_HEAT_COLS) * weight; + weighted_y += (u64)(index / G6TS_HEAT_COLS) * weight; + } + if (!weight_total) + return; + + contact->output_x = div_u64(weighted_x * G6TS_LOGICAL_MAX, + weight_total * (G6TS_HEAT_COLS - 1)); + contact->output_y = div_u64(weighted_y * G6TS_LOGICAL_MAX, + weight_total * (G6TS_HEAT_ROWS - 1)); +} + +/* + * Mirror FUN_180040438's candidate +0x4d local-maximum producer and + * FUN_180041fd8's +0x4e strict 0.04 filter. The DLL's equality epsilon is + * 0.0001 while adjacent byte lookup values differ by about 0.00222, so Q12 + * ordering is identical for this byte-input path. + */ +static void g6ts_local_peak_counts(const struct g6ts *ts, + struct g6ts_contact *contact) +{ + static const s8 neighbours[][2] = { + { -1, 0 }, { 1, 0 }, { 0, -1 }, { 0, 1 }, + }; + unsigned int index; + + contact->local_peak_count = 0; + contact->strong_local_peak_count = 0; + for (index = 0; index < G6TS_HEAT_SAMPLES; index++) { + unsigned int row, col, equal_index = UINT_MAX; + s32 current_signal, equal_signal = 0; + unsigned int lower = 0, near_equal = 0, n; + bool selected; + + if (!ts->heat_component[index]) + continue; + row = index / G6TS_HEAT_COLS; + col = index % G6TS_HEAT_COLS; + current_signal = g6ts_signal_q12(ts->heatmap[index]); + for (n = 0; n < ARRAY_SIZE(neighbours); n++) { + int neighbour_col = col + neighbours[n][0]; + int neighbour_row = row + neighbours[n][1]; + unsigned int neighbour_index; + s32 neighbour_signal; + + if (neighbour_row < 0 || neighbour_row >= G6TS_HEAT_ROWS || + neighbour_col < 0 || neighbour_col >= G6TS_HEAT_COLS) { + neighbour_index = UINT_MAX; + neighbour_signal = 0; + } else { + neighbour_index = neighbour_row * G6TS_HEAT_COLS + + neighbour_col; + neighbour_signal = + g6ts_signal_q12(ts->heatmap[neighbour_index]); + } + if (current_signal > neighbour_signal) { + lower++; + } else if (current_signal == neighbour_signal) { + near_equal++; + equal_index = neighbour_index; + equal_signal = neighbour_signal; + } + } + + selected = lower == 4; + if (lower == 3 && near_equal == 1) + selected = equal_signal < current_signal || + (equal_signal == current_signal && + index < equal_index); + if (!selected || + contact->local_peak_count >= G6TS_LOCAL_PEAK_CAPACITY) + continue; + contact->local_peak_count++; + if (current_signal > G6TS_LOCAL_PEAK_FLOOR_Q12) + contact->strong_local_peak_count++; + } +} + +static u8 g6ts_secondary_cutoff(u8 peak_value, unsigned int pass) +{ + static const u16 fractions_q12[] = { 2048, 3072, 3584 }; + u32 fraction = fractions_q12[pass]; + u64 cutoff_q24; + u32 cutoff_q12; + + cutoff_q24 = (u64)((1U << G6TS_CLASSIFIER_SHIFT) - fraction) * + G6TS_SECONDARY_A_Q12; + cutoff_q24 += (u64)fraction * + ((peak_value << G6TS_CLASSIFIER_SHIFT) + + G6TS_SECONDARY_NOISE_Q12); + cutoff_q12 = (cutoff_q24 + BIT(G6TS_CLASSIFIER_SHIFT - 1)) >> + G6TS_CLASSIFIER_SHIFT; + return min_t(u32, U8_MAX, + (cutoff_q12 + BIT(G6TS_CLASSIFIER_SHIFT - 1)) >> + G6TS_CLASSIFIER_SHIFT); +} + +static bool g6ts_secondary_neighbour(const struct g6ts *ts, int row, int col, + u8 cutoff) +{ + unsigned int index; + + if (row < 0 || row >= G6TS_HEAT_ROWS || + col < 0 || col >= G6TS_HEAT_COLS) + return false; + index = row * G6TS_HEAT_COLS + col; + return ts->heat_component[index] && !ts->heat_work[index] && + ts->heatmap[index] <= cutoff; +} + +static void g6ts_secondary_features(struct g6ts *ts, + struct g6ts_contact *contact) +{ + static const s8 neighbours[][2] = { + { -1, 0 }, { 0, -1 }, { 1, 0 }, { 0, 1 }, + }; + unsigned int area = (contact->max_col - contact->min_col + 1) * + (contact->max_row - contact->min_row + 1); + unsigned int pass; + + for (pass = 0; pass < 3; pass++) { + contact->features_q12[1 + pass] = + contact->pixels << G6TS_CLASSIFIER_SHIFT; + contact->features_q12[4 + pass] = 1U << G6TS_CLASSIFIER_SHIFT; + } + /* FUN_180041fd8 only reruns bounded candidates above 0.05 + 0.02. */ + if (area >= 0x4e3 || g6ts_signal_q12(contact->peak_value) <= 287) + return; + + for (pass = 0; pass < 3; pass++) { + u8 cutoff = g6ts_secondary_cutoff(contact->peak_value, pass); + unsigned int accepted = 0, largest = 0, start; + + memset(ts->heat_work, 0, sizeof(ts->heat_work)); + for (start = 0; start < G6TS_HEAT_SAMPLES; start++) { + unsigned int head = 0, tail = 0, pixels = 0; + u8 peak = U8_MAX; + + if (!ts->heat_component[start] || ts->heat_work[start] || + ts->heatmap[start] > cutoff) + continue; + ts->heat_work[start] = 1; + ts->heat_queue[tail++] = start; + while (head < tail) { + unsigned int index = ts->heat_queue[head++]; + unsigned int row = index / G6TS_HEAT_COLS; + unsigned int col = index % G6TS_HEAT_COLS; + unsigned int n; + + pixels++; + peak = min_t(u8, peak, ts->heatmap[index]); + for (n = 0; n < ARRAY_SIZE(neighbours); n++) { + int nr = row + neighbours[n][1]; + int nc = col + neighbours[n][0]; + unsigned int neighbour; + + if (!g6ts_secondary_neighbour(ts, nr, nc, cutoff)) + continue; + neighbour = nr * G6TS_HEAT_COLS + nc; + ts->heat_work[neighbour] = 1; + ts->heat_queue[tail++] = neighbour; + } + } + if (pixels <= 2 && + g6ts_signal_q12(peak) <= G6TS_SECONDARY_SEED_Q12) + continue; + accepted++; + largest = max(largest, pixels); + } + contact->features_q12[1 + pass] = + largest << G6TS_CLASSIFIER_SHIFT; + contact->features_q12[4 + pass] = + accepted << G6TS_CLASSIFIER_SHIFT; + } +} + +static void g6ts_geometry_features(struct g6ts *ts, + struct g6ts_contact *contact) +{ + u64 sum = 0, sum_x = 0, sum_y = 0; + u64 sum_xx = 0, sum_yy = 0, sum_xy = 0; + s64 var_x, var_y, covariance, trace, delta, discriminant; + u64 denominator; + u32 major_axis, minor_axis; + unsigned int index; + + for (index = 0; index < G6TS_HEAT_SAMPLES; index++) { + u32 row, col; + s32 signal; + + if (!ts->heat_component[index]) + continue; + row = index / G6TS_HEAT_COLS; + col = index % G6TS_HEAT_COLS; + signal = g6ts_signal_q12(ts->heatmap[index]); + if (signal <= 0) + continue; + sum += signal; + sum_x += (u64)signal * col; + sum_y += (u64)signal * row; + sum_xx += (u64)signal * col * col; + sum_yy += (u64)signal * row * row; + sum_xy += (u64)signal * col * row; + } + if (!sum) { + contact->features_q12[7] = 1U << G6TS_CLASSIFIER_SHIFT; + contact->features_q12[8] = 1U << G6TS_CLASSIFIER_SHIFT; + return; + } + + denominator = sum * sum; + var_x = div64_s64(((s64)(sum_xx * sum) - (s64)(sum_x * sum_x)) * + (1U << G6TS_CLASSIFIER_SHIFT), denominator); + var_y = div64_s64(((s64)(sum_yy * sum) - (s64)(sum_y * sum_y)) * + (1U << G6TS_CLASSIFIER_SHIFT), denominator); + covariance = div64_s64(((s64)(sum_xy * sum) - (s64)(sum_x * sum_y)) * + (1U << G6TS_CLASSIFIER_SHIFT), denominator); + trace = max_t(s64, 0, var_x + var_y); + delta = var_x - var_y; + discriminant = int_sqrt64(delta * delta + 4 * covariance * covariance); + major_axis = int_sqrt64(((trace + discriminant) / 2) << + G6TS_CLASSIFIER_SHIFT); + minor_axis = int_sqrt64(max_t(s64, 0, (trace - discriminant) / 2) << + G6TS_CLASSIFIER_SHIFT); + major_axis = max_t(u32, 1U << G6TS_CLASSIFIER_SHIFT, + ((u64)major_axis * G6TS_AXIS_SCALE_Q12) >> + G6TS_CLASSIFIER_SHIFT); + minor_axis = max_t(u32, 1U << G6TS_CLASSIFIER_SHIFT, + ((u64)minor_axis * G6TS_AXIS_SCALE_Q12) >> + G6TS_CLASSIFIER_SHIFT); + contact->features_q12[7] = div_u64((u64)major_axis << + G6TS_CLASSIFIER_SHIFT, minor_axis); + if (contact->pixels < 2) { + contact->features_q12[8] = 1U << G6TS_CLASSIFIER_SHIFT; + } else { + s64 spread = trace * G6TS_SPREAD_SCALE_Q12; + u32 samples = (1U << G6TS_CLASSIFIER_SHIFT) * + (contact->pixels - 1); + + contact->features_q12[8] = div64_s64(spread, samples); + } +} + +static s32 g6ts_halo_feature(struct g6ts *ts, + const struct g6ts_contact *contact) +{ + static const s8 neighbours[][2] = { + { -1, 0 }, { 0, -1 }, { 1, 0 }, { 0, 1 }, + }; + u8 state[16][16]; + int origin_col = contact->min_col - 3; + int origin_row = contact->min_row - 3; + s32 peak = g6ts_signal_q12(contact->peak_value); + s32 peak_threshold = peak / 4; + s64 halo = 0; + unsigned int radius, n; + int row, col; + + if (contact->max_col - contact->min_col + 1 >= 11 || + contact->max_row - contact->min_row + 1 >= 11 || peak <= 0) + return G6TS_HALO_UNAVAILABLE_Q12; + memset(state, 5, sizeof(state)); + for (row = max(0, origin_row); row <= + min_t(int, G6TS_HEAT_ROWS - 1, contact->max_row + 3); row++) { + for (col = max(0, origin_col); col <= + min_t(int, G6TS_HEAT_COLS - 1, contact->max_col + 3); col++) { + unsigned int index = row * G6TS_HEAT_COLS + col; + + if (ts->heat_component[index]) + state[row - origin_row][col - origin_col] = 0; + else if (!g6ts_heat_active(ts, index)) + state[row - origin_row][col - origin_col] = 4; + } + } + for (row = contact->min_row; row <= contact->max_row; row++) { + for (col = contact->min_col; col <= contact->max_col; col++) { + if (state[row - origin_row][col - origin_col]) + continue; + for (n = 0; n < ARRAY_SIZE(neighbours); n++) { + int nc = col + neighbours[n][0]; + int nr = row + neighbours[n][1]; + + if (nr < 0 || nr >= G6TS_HEAT_ROWS || nc < 0 || + nc >= G6TS_HEAT_COLS || + state[nr - origin_row][nc - origin_col] != 4) + continue; + if (g6ts_signal_q12(ts->heatmap[nr * G6TS_HEAT_COLS + nc]) > + peak_threshold) + state[nr - origin_row][nc - origin_col] = 1; + } + } + } + for (radius = 1; radius <= 2; radius++) { + for (row = max_t(int, 0, contact->min_row - radius); row <= + min_t(int, G6TS_HEAT_ROWS - 1, contact->max_row + radius); row++) { + for (col = max_t(int, 0, contact->min_col - radius); col <= + min_t(int, G6TS_HEAT_COLS - 1, contact->max_col + radius); col++) { + unsigned int current_index; + s32 current_signal; + + if (state[row - origin_row][col - origin_col] > radius) + continue; + current_index = row * G6TS_HEAT_COLS + col; + current_signal = g6ts_signal_q12(ts->heatmap[current_index]); + for (n = 0; n < ARRAY_SIZE(neighbours); n++) { + int nc = col + neighbours[n][0]; + int nr = row + neighbours[n][1]; + unsigned int next_index; + s32 next; + + if (nr < 0 || nr >= G6TS_HEAT_ROWS || nc < 0 || + nc >= G6TS_HEAT_COLS || + state[nr - origin_row][nc - origin_col] != 4) + continue; + next_index = nr * G6TS_HEAT_COLS + nc; + next = g6ts_signal_q12(ts->heatmap[next_index]); + if (next < peak_threshold && current_signal > next && + current_signal > 0 && + (s64)next << G6TS_CLASSIFIER_SHIFT > + (s64)current_signal * G6TS_HALO_RATIO_Q12) { + state[nr - origin_row][nc - origin_col] = + radius + 1; + halo += next; + } + } + } + } + } + return div64_s64(halo << G6TS_CLASSIFIER_SHIFT, peak); +} + +static u8 g6ts_classify_contact(struct g6ts_contact *contact) +{ + s64 best_score = S64_MIN; + u8 best_class = 0; + unsigned int class, row, col; + + for (class = 0; class < ARRAY_SIZE(g6ts_classifier_models); class++) { + const struct g6ts_classifier_model *model = + &g6ts_classifier_models[class]; + s64 distance = 0; + + contact->scores_q24[class] = + -9999LL * (1LL << G6TS_WINDOWS_SCORE_SHIFT); + if (contact->pixels > model->max_points) + continue; + for (row = 0; row < G6TS_FEATURE_COUNT; row++) { + s64 transformed = 0; + + for (col = row; col < G6TS_FEATURE_COUNT; col++) { + s32 residual; + + if (col == 9 && contact->features_q12[col] == + G6TS_HALO_UNAVAILABLE_Q12) + residual = 0; + else + residual = contact->features_q12[col] - + model->means_q12[col]; + transformed += (s64)residual * + model->transform_q12[row][col]; + } + transformed >>= G6TS_CLASSIFIER_SHIFT; + if (transformed > INT_MAX || transformed < -INT_MAX || + distance > S64_MAX - transformed * transformed) { + distance = S64_MAX; + break; + } + distance += transformed * transformed; + } + if (distance != S64_MAX) { + s64 score = ((s64)model->score_offset_q12 << + G6TS_CLASSIFIER_SHIFT) - distance / 2 + + G6TS_WINDOWS_RUNTIME_OFFSET_Q24; + + contact->scores_q24[class] = score; + } + } + if (g6ts_windows_orchestrator) { + /* FUN_180049638 applies these in strict if/else-if order. */ + if (contact->local_peak_count == 1) + contact->scores_q24[3] -= + G6TS_WINDOWS_SCORE3_PRIMARY_Q24; + else if (contact->strong_local_peak_count == 1) + contact->scores_q24[3] -= + G6TS_WINDOWS_SCORE3_SINGLE_Q24; + } + for (class = 0; class < G6TS_CLASS_COUNT; class++) { + if (contact->scores_q24[class] > best_score) { + best_score = contact->scores_q24[class]; + best_class = class; + } + } + return best_class; +} + +static unsigned int g6ts_find_contacts(struct g6ts *ts) +{ + unsigned int contact_count = 0; + unsigned int start; + + memset(ts->heat_seen, 0, sizeof(ts->heat_seen)); + + for (start = 0; start < G6TS_HEAT_SAMPLES; start++) { + struct g6ts_contact contact = { + .min_col = G6TS_HEAT_COLS - 1, + .min_row = G6TS_HEAT_ROWS - 1, + .peak_value = U8_MAX, + }; + unsigned int head = 0, tail = 0; + + if (ts->heat_seen[start] || !g6ts_heat_active(ts, start)) + continue; + ts->heat_seen[start] = 1; + ts->heat_queue[tail++] = start; + + while (head < tail) { + unsigned int index = ts->heat_queue[head++]; + unsigned int row = index / G6TS_HEAT_COLS; + unsigned int col = index % G6TS_HEAT_COLS; + unsigned int strength = G6TS_HEAT_SIGNAL_ZERO - + ts->heatmap[index]; + int dr, dc; + + contact.pixels++; + contact.strength += strength; + contact.weighted_x += (u64)col * strength; + contact.weighted_y += (u64)row * strength; + contact.min_col = min_t(u8, contact.min_col, col); + contact.max_col = max_t(u8, contact.max_col, col); + contact.min_row = min_t(u8, contact.min_row, row); + contact.max_row = max_t(u8, contact.max_row, row); + contact.peak_value = min_t(u8, contact.peak_value, + ts->heatmap[index]); + + for (dr = -1; dr <= 1; dr++) { + for (dc = -1; dc <= 1; dc++) { + int neighbour_row = row + dr; + int neighbour_col = col + dc; + unsigned int neighbour; + + if (abs(dr) + abs(dc) != 1 || + neighbour_row < 0 || + neighbour_row >= G6TS_HEAT_ROWS || + neighbour_col < 0 || + neighbour_col >= G6TS_HEAT_COLS) + continue; + neighbour = neighbour_row * G6TS_HEAT_COLS + + neighbour_col; + if (ts->heat_seen[neighbour] || + !g6ts_heat_active(ts, neighbour)) + continue; + ts->heat_seen[neighbour] = 1; + ts->heat_queue[tail++] = neighbour; + } + } + } + + ts->component_total++; + if (contact.pixels < G6TS_HEAT_MIN_PIXELS && + contact.peak_value > G6TS_HEAT_STRONG_MAX) { + ts->weak_rejections++; + continue; + } + if (ts->nsr_valid) { + unsigned int sensor_row = div_u64(contact.weighted_y + + contact.strength / 2, + contact.strength); + + if (sensor_row < ARRAY_SIZE(g6ts_nsr_row_to_bin)) { + u8 bin = g6ts_nsr_row_to_bin[sensor_row]; + + if (bin < ts->nsr_bin_count && + ts->nsr_bins[bin] > G6TS_NSR_CUTOFF) { + ts->nsr_rejections++; + continue; + } + } + } + if (contact.pixels > G6TS_HEAT_PALM_PIXELS || + contact.max_col - contact.min_col + 1 > G6TS_HEAT_PALM_SPAN || + contact.max_row - contact.min_row + 1 > G6TS_HEAT_PALM_SPAN) { + ts->palm_rejections++; + continue; + } + contact.x = div_u64(contact.weighted_x * G6TS_LOGICAL_MAX, + (u64)contact.strength * (G6TS_HEAT_COLS - 1)); + contact.y = div_u64(contact.weighted_y * G6TS_LOGICAL_MAX, + (u64)contact.strength * (G6TS_HEAT_ROWS - 1)); + contact.output_x = contact.x; + contact.output_y = contact.y; + contact.sensor_x_q24 = div_u64(contact.weighted_x << 24, + contact.strength); + contact.sensor_y_q24 = div_u64(contact.weighted_y << 24, + contact.strength); + memset(ts->heat_component, 0, sizeof(ts->heat_component)); + while (tail) + ts->heat_component[ts->heat_queue[--tail]] = 1; + if (g6ts_behavior_v2) + g6ts_phase76_output_centroid(ts, &contact); + g6ts_local_peak_counts(ts, &contact); + contact.features_q12[0] = + contact.pixels << G6TS_CLASSIFIER_SHIFT; + g6ts_secondary_features(ts, &contact); + g6ts_geometry_features(ts, &contact); + contact.features_q12[9] = g6ts_halo_feature(ts, &contact); + contact.shape_class = g6ts_classify_contact(&contact); + /* FUN_180049458 permits the classifier's classes zero and two. */ + contact.shape_allowed = contact.shape_class == 0 || + contact.shape_class == 2; + dev_dbg(&ts->spi->dev, + "candidate class=%u allowed=%u pixels=%u peaks=%u/%u halo_q12=%d scores=[%lld,%lld,%lld,%lld]\n", + contact.shape_class, contact.shape_allowed, contact.pixels, + contact.local_peak_count, contact.strong_local_peak_count, + contact.features_q12[9], contact.scores_q24[0], + contact.scores_q24[1], contact.scores_q24[2], + contact.scores_q24[3]); + memset(ts->heat_component, 0, sizeof(ts->heat_component)); + g6ts_store_contact(ts, &contact, &contact_count); + } + + ts->contact_total += contact_count; + return contact_count; +} + +static bool +g6ts_transition_current_passes(const struct g6ts_transition_rule *rule, + u8 candidate, + const s64 scores[G6TS_CLASS_COUNT]) +{ + s64 selected = scores[candidate]; + unsigned int class; + + for (class = 0; class < G6TS_CLASS_COUNT; class++) { + s64 margin; + + if (class == candidate) + continue; + margin = (s64)rule->current_margins[class] * + (1LL << G6TS_WINDOWS_SCORE_SHIFT); + if (selected - scores[class] < margin) + return false; + } + return selected >= (s64)rule->absolute_minimum * + (1LL << G6TS_WINDOWS_SCORE_SHIFT); +} + +static bool +g6ts_transition_history_passes(const struct g6ts_track *track, + const struct g6ts_transition_rule *rule, + u8 candidate) +{ + unsigned int sample, class; + + if (rule->history_depth > G6TS_WINDOWS_HISTORY_CAPACITY || + track->score_history_count < rule->history_depth) + return false; + for (sample = 0; sample < rule->history_depth; sample++) { + s64 selected = track->score_history_q24[sample][candidate]; + + for (class = 0; class < G6TS_CLASS_COUNT; class++) { + s64 margin; + + if (class == candidate) + continue; + margin = (s64)rule->history_margins[class] * + (1LL << G6TS_WINDOWS_SCORE_SHIFT); + if (selected - track->score_history_q24[sample][class] < + margin) + return false; + } + if (selected < (s64)rule->absolute_minimum * + (1LL << G6TS_WINDOWS_SCORE_SHIFT)) + return false; + } + return true; +} + +/* + * Bounded ordinary-finger subset of FUN_180041150. Context bias, the + * candidate +0x4d/+0x4e score-three producer, and the later output override + * remain outside this opt-in path until their live provider fields exist. + */ +static void g6ts_windows_update_class(struct g6ts_track *track, + const struct g6ts_contact *contact) +{ + const struct g6ts_transition_rule *rule; + unsigned int sample, class; + u8 candidate = 0; + bool accepted = false; + + for (sample = min_t(unsigned int, track->score_history_count, + G6TS_WINDOWS_HISTORY_CAPACITY - 1); + sample > 0; sample--) + memcpy(track->score_history_q24[sample], + track->score_history_q24[sample - 1], + sizeof(track->score_history_q24[sample])); + memcpy(track->score_history_q24[0], contact->scores_q24, + sizeof(track->score_history_q24[0])); + if (track->score_history_count < G6TS_WINDOWS_HISTORY_CAPACITY) + track->score_history_count++; + + for (class = 1; class < G6TS_CLASS_COUNT; class++) { + if (contact->scores_q24[candidate] < contact->scores_q24[class]) + candidate = class; + } + if (track->windows_class == candidate) { + accepted = true; + } else { + rule = &g6ts_transition_rules[track->windows_class * + G6TS_CLASS_COUNT + candidate]; + if (track->age == 1 || track->age <= rule->initial_age_limit) + accepted = g6ts_transition_current_passes(rule, candidate, + contact->scores_q24); + if (!accepted && track->age > 1) + accepted = g6ts_transition_history_passes(track, rule, + candidate); + if (accepted && + (contact->pixels < g6ts_class_point_minimums[candidate] || + contact->pixels > g6ts_class_point_maximums[candidate])) + accepted = false; + } + if (accepted) + track->windows_class = candidate; + track->confirmed = track->windows_class == 0 || + track->windows_class == 2; +} + +static u16 g6ts_windows_assignment_coordinate(u32 position_q24, u32 scale_q24) +{ + u64 scaled = (u64)position_q24 * scale_q24; + + return min_t(u64, (scaled + BIT_ULL(47)) >> 48, S16_MAX); +} + +static u16 g6ts_filter_coordinate(u16 previous, u16 sample) +{ + unsigned int delta = previous > sample ? previous - sample : + sample - previous; + + /* + * TouchPenProcessor uses output = alpha * previous + + * (1 - alpha) * sample. The project-tuning table selecting alpha is + * not recovered, so these two bands are explicit SP11 fits: suppress + * stationary sensor jitter, reduce lag for slow motion, and pass fast + * motion through unchanged. + */ + if (delta <= G6TS_SMOOTH_STATIONARY_MAX) + return (3U * previous + sample + 2U) / 4U; + if (delta <= G6TS_SMOOTH_SLOW_MAX) + return (previous + 3U * sample + 2U) / 4U; + return sample; +} + +static unsigned int g6ts_track_distance(const struct g6ts_track *track, + const struct g6ts_contact *contact) +{ + if (g6ts_windows_orchestrator || g6ts_behavior_v2) { + const u32 x_scale = G6TS_WINDOWS_ASSIGN_X_SCALE_Q24; + const u32 y_scale = G6TS_WINDOWS_ASSIGN_Y_SCALE_Q24; + s64 predicted_x = clamp_t(s64, + (s64)track->sensor_x_q24 + track->sensor_velocity_x_q24, + 0, (s64)(G6TS_HEAT_COLS - 1) << 24); + s64 predicted_y = clamp_t(s64, + (s64)track->sensor_y_q24 + track->sensor_velocity_y_q24, + 0, (s64)(G6TS_HEAT_ROWS - 1) << 24); + s32 track_x = g6ts_windows_assignment_coordinate(predicted_x, + x_scale); + s32 track_y = g6ts_windows_assignment_coordinate(predicted_y, + y_scale); + s32 candidate_x = g6ts_windows_assignment_coordinate(contact->sensor_x_q24, + x_scale); + s32 candidate_y = g6ts_windows_assignment_coordinate(contact->sensor_y_q24, + y_scale); + s32 dx = track_x - candidate_x; + s32 dy = track_y - candidate_y; + u32 squared = dx * dx + dy * dy; + + if (squared >= G6TS_WINDOWS_ASSIGN_RADIUS * + G6TS_WINDOWS_ASSIGN_RADIUS) + return G6TS_ASSIGN_INVALID_COST; + return squared; + } + + s32 predicted_x = clamp_t(s32, (s32)track->raw_x + track->velocity_x, + 0, G6TS_LOGICAL_MAX); + s32 predicted_y = clamp_t(s32, (s32)track->raw_y + track->velocity_y, + 0, G6TS_LOGICAL_MAX); + s32 dx = predicted_x - contact->x; + s32 dy = predicted_y - contact->y; + u64 squared = (s64)dx * dx + (s64)dy * dy; + + if (squared > (u64)G6TS_TRACK_MATCH_MAX * G6TS_TRACK_MATCH_MAX) + return G6TS_ASSIGN_INVALID_COST; + return int_sqrt64(squared); +} + +static u8 g6ts_confirmation_requirement(const struct g6ts *ts, + const struct g6ts_contact *contact) +{ + unsigned int i; + u8 required = g6ts_behavior_v2 ? G6TS_BEHAVIOR_CONFIRM_NORMAL : + G6TS_TRACK_CONFIRM_NORMAL; + + /* + * TouchPenProcessor does not expose a blob immediately. Its recovered + * lifecycle keeps a per-track class history and uses transition-specific + * evidence windows. The proprietary four-class score coefficients are + * intentionally not copied here; use observable component quality to + * select the same short, medium, and long lifecycle windows instead. + */ + if (contact->pixels < G6TS_HEAT_MIN_PIXELS) + required = G6TS_TRACK_CONFIRM_WEAK; + if (!contact->shape_allowed) + required = max_t(u8, required, G6TS_TRACK_CONFIRM_WEAK); + + for (i = 0; i < G6TS_MAX_CONTACTS; i++) { + const struct g6ts_track *track = &ts->tracks[i]; + s32 dx, dy; + u64 squared; + + if (!track->active || !track->confirmed || track->missed) + continue; + dx = (s32)track->raw_x - contact->x; + dy = (s32)track->raw_y - contact->y; + squared = (s64)dx * dx + (s64)dy * dy; + if (squared > (u64)G6TS_TRACK_SPLIT_RADIUS * + G6TS_TRACK_SPLIT_RADIUS) + continue; + + /* + * A new, smaller island beside an established finger is commonly a + * transient split of that finger. Preserve real close multitouch by + * accepting it after sustained evidence rather than deleting it. + */ + required = max_t(u8, required, G6TS_TRACK_CONFIRM_WEAK); + if ((u64)contact->strength * 2 <= track->strength || + (u32)contact->pixels * 2 <= track->pixels) + required = G6TS_TRACK_CONFIRM_SPLIT; + } + + return required; +} + +/* + * Windows builds a predicted-position Euclidean cost matrix and solves a + * global assignment. Use a square matrix with explicit dummy rows/columns + * so a gated-out pairing loses to closing one track and opening another. + */ +static void g6ts_assign_tracks(struct g6ts *ts, unsigned int count, + int contact_slots[G6TS_MAX_CONTACTS]) +{ + struct g6ts_assignment_workspace *work = &ts->assignment; + unsigned int active_count = 0; + unsigned int n, row, col, i, j; + + memset(work, 0, sizeof(*work)); + for (i = 0; i < G6TS_MAX_CONTACTS; i++) + contact_slots[i] = -1; + + for (i = 0; i < G6TS_MAX_CONTACTS; i++) { + if (ts->tracks[i].active) + work->active_slots[active_count++] = i; + } + if (!active_count || !count) + return; + + n = active_count + count; + for (row = 0; row < n; row++) { + for (col = 0; col < n; col++) { + if (row < active_count && col < count) { + struct g6ts_track *track; + + track = &ts->tracks[work->active_slots[row]]; + work->cost[row][col] = + g6ts_track_distance(track, + &ts->contacts[col]); + } else if (row < active_count || col < count) { + work->cost[row][col] = G6TS_ASSIGN_UNMATCHED_COST; + } else { + work->cost[row][col] = 0; + } + } + } + + /* Hungarian minimum-cost assignment, using one-based work arrays. */ + for (i = 1; i <= n; i++) { + int j0 = 0; + + work->p[0] = i; + for (j = 0; j <= n; j++) { + work->minv[j] = INT_MAX; + work->used[j] = false; + } + do { + int i0, delta = INT_MAX, j1 = 0; + + work->used[j0] = true; + i0 = work->p[j0]; + for (j = 1; j <= n; j++) { + int reduced_cost; + + if (work->used[j]) + continue; + reduced_cost = work->cost[i0 - 1][j - 1] - + work->u[i0] - work->v[j]; + if (reduced_cost < work->minv[j]) { + work->minv[j] = reduced_cost; + work->way[j] = j0; + } + if (work->minv[j] < delta) { + delta = work->minv[j]; + j1 = j; + } + } + for (j = 0; j <= n; j++) { + if (work->used[j]) { + work->u[work->p[j]] += delta; + work->v[j] -= delta; + } else if (j) { + work->minv[j] -= delta; + } + } + j0 = j1; + } while (work->p[j0]); + + do { + int j1 = work->way[j0]; + + work->p[j0] = work->p[j1]; + j0 = j1; + } while (j0); + } + + for (j = 1; j <= n; j++) { + row = work->p[j] - 1; + col = j - 1; + if (row < active_count && col < count && + work->cost[row][col] < G6TS_ASSIGN_INVALID_COST && + (g6ts_windows_orchestrator || g6ts_behavior_v2 || + work->cost[row][col] <= G6TS_TRACK_MATCH_MAX)) + contact_slots[col] = work->active_slots[row]; + } + for (i = 0; i < count; i++) + if (contact_slots[i] >= 0) + ts->assignment_matches++; +} + +static void g6ts_update_track(struct g6ts_track *track, + const struct g6ts_contact *contact) +{ + u16 old_x = track->raw_x; + u16 old_y = track->raw_y; + u32 old_sensor_x_q24 = track->sensor_x_q24; + u32 old_sensor_y_q24 = track->sensor_y_q24; + + track->raw_x = contact->x; + track->raw_y = contact->y; + track->velocity_x = (s32)contact->x - old_x; + track->velocity_y = (s32)contact->y - old_y; + track->sensor_x_q24 = contact->sensor_x_q24; + track->sensor_y_q24 = contact->sensor_y_q24; + track->sensor_velocity_x_q24 = (s32)((s64)contact->sensor_x_q24 - + old_sensor_x_q24); + track->sensor_velocity_y_q24 = (s32)((s64)contact->sensor_y_q24 - + old_sensor_y_q24); + if (g6ts_windows_orchestrator) { + /* FUN_18004a330 stores X/Y directly; its alpha blends another scalar. */ + track->output_x = contact->x; + track->output_y = contact->y; + } else if (g6ts_behavior_v2) { + track->output_x = contact->output_x; + track->output_y = contact->output_y; + } else { + track->output_x = g6ts_filter_coordinate(track->output_x, + contact->x); + track->output_y = g6ts_filter_coordinate(track->output_y, + contact->y); + } + track->strength = contact->strength; + track->pixels = contact->pixels; + track->shape_class = contact->shape_class; + if (track->age < U16_MAX) + track->age++; + if (g6ts_windows_orchestrator) { + g6ts_windows_update_class(track, contact); + } else if (!track->confirmed && contact->shape_allowed && + track->evidence < U8_MAX) { + track->evidence++; + if (track->evidence >= track->required_evidence) + track->confirmed = true; + } + track->missed = 0; +} + +static int g6ts_new_track(struct g6ts *ts, + const struct g6ts_contact *contact) +{ + unsigned int slot; + + for (slot = 0; slot < G6TS_MAX_CONTACTS; slot++) { + struct g6ts_track *track = &ts->tracks[slot]; + + if (track->active) + continue; + memset(track, 0, sizeof(*track)); + track->raw_x = contact->x; + track->raw_y = contact->y; + track->output_x = g6ts_behavior_v2 ? contact->output_x : contact->x; + track->output_y = g6ts_behavior_v2 ? contact->output_y : contact->y; + track->sensor_x_q24 = contact->sensor_x_q24; + track->sensor_y_q24 = contact->sensor_y_q24; + track->strength = contact->strength; + track->pixels = contact->pixels; + track->shape_class = contact->shape_class; + track->age = 1; + if (g6ts_windows_orchestrator) { + track->windows_class = G6TS_WINDOWS_UNCLASSIFIED; + g6ts_windows_update_class(track, contact); + } else { + track->evidence = contact->shape_allowed ? 1 : 0; + track->required_evidence = + g6ts_confirmation_requirement(ts, contact); + track->confirmed = track->required_evidence <= 1; + } + track->active = true; + ts->new_tracks++; + return slot; + } + return -ENOSPC; +} + +static void g6ts_advance_unmatched_tracks(struct g6ts *ts, + unsigned long current_slots) +{ + unsigned int i; + + for (i = 0; i < G6TS_MAX_CONTACTS; i++) { + struct g6ts_track *track = &ts->tracks[i]; + + if (!track->active || (current_slots & BIT(i))) + continue; + if (track->missed < G6TS_CONTACT_HOLD_FRAMES) { + track->missed++; + track->velocity_x /= 2; + track->velocity_y /= 2; + track->sensor_velocity_x_q24 /= 2; + track->sensor_velocity_y_q24 /= 2; + } else { + memset(track, 0, sizeof(*track)); + } + } +} + +static unsigned long +g6ts_create_unmatched_tracks(struct g6ts *ts, unsigned int count, + const int contact_slots[G6TS_MAX_CONTACTS], + unsigned long current_slots) +{ + unsigned int i; + + for (i = 0; i < count; i++) { + int slot; + + if (contact_slots[i] >= 0) + continue; + slot = g6ts_new_track(ts, &ts->contacts[i]); + if (slot >= 0) + current_slots |= BIT(slot); + } + return current_slots; +} + +static void g6ts_collect_linux_contacts(struct g6ts *ts, + unsigned long current_slots) +{ + unsigned int reported = 0; + unsigned int i; + + for (i = 0; i < G6TS_MAX_CONTACTS; i++) { + struct g6ts_track *track = &ts->tracks[i]; + + /* Retained tracks remain assignable but never become ghost contacts. */ + if (!track->active || !track->confirmed || + !(current_slots & BIT(i))) + continue; + input_mt_slot(ts->input, i); + input_mt_report_slot_state(ts->input, MT_TOOL_FINGER, true); + touchscreen_report_pos(ts->input, &ts->prop, track->output_x, + track->output_y, true); + reported++; + } + input_mt_sync_frame(ts->input); + input_sync(ts->input); + ts->output_frames++; + ts->output_contacts += reported; +} + +static int g6ts_report_heat_contacts(struct g6ts *ts, const u8 *content, + size_t content_len) +{ + u64 started_ns = ktime_get_ns(); + unsigned long current_slots = 0; + int contact_slots[G6TS_MAX_CONTACTS]; + unsigned int count, i; + int ret; + + ret = g6ts_extract_heatmap(ts, content, content_len); + if (ret) { + ts->heat_errors++; + return ret; + } + count = g6ts_find_contacts(ts); + g6ts_assign_tracks(ts, count, contact_slots); + + for (i = 0; i < count; i++) { + int slot = contact_slots[i]; + + if (slot < 0) + continue; + g6ts_update_track(&ts->tracks[slot], &ts->contacts[i]); + current_slots |= BIT(slot); + } + + /* + * The frame transaction is deliberately explicit and single-threaded: + * assignment -> matched updates -> unmatched lifecycle -> new tracks -> + * final Linux collection. No input event escapes an intermediate stage. + */ + g6ts_advance_unmatched_tracks(ts, current_slots); + current_slots = g6ts_create_unmatched_tracks(ts, count, contact_slots, + current_slots); + g6ts_collect_linux_contacts(ts, current_slots); + ts->heat_frames++; + started_ns = ktime_get_ns() - started_ns; + ts->processing_ns_total += started_ns; + ts->processing_ns_max = max(ts->processing_ns_max, started_ns); + + return 0; +} + +static void g6ts_release_contacts(struct g6ts *ts) +{ + input_mt_sync_frame(ts->input); + input_sync(ts->input); + memset(ts->tracks, 0, sizeof(ts->tracks)); +} + +static void g6ts_release_pen(struct g6ts *ts) +{ + input_report_abs(ts->pen_input, ABS_PRESSURE, 0); + input_report_key(ts->pen_input, BTN_TOUCH, false); + input_report_key(ts->pen_input, BTN_STYLUS, false); + input_report_key(ts->pen_input, BTN_TOOL_PEN, false); + input_report_key(ts->pen_input, BTN_TOOL_RUBBER, false); + input_sync(ts->pen_input); +} + +static void g6ts_release_inputs(struct g6ts *ts) +{ + g6ts_release_contacts(ts); + g6ts_release_pen(ts); +} + +static void g6ts_report_pen(struct g6ts *ts, const u8 *content) +{ + struct input_dev *input = ts->pen_input; + u8 flags = content[0]; + bool in_range = flags & G6TS_PEN_IN_RANGE; + bool touching = flags & (G6TS_PEN_TIP_SWITCH | G6TS_PEN_ERASER); + bool barrel = flags & G6TS_PEN_BARREL_SWITCH; + bool rubber = flags & (G6TS_PEN_INVERT | G6TS_PEN_ERASER); + u16 x, y, pressure, raw_tilt_x, raw_tilt_y; + s16 tilt_x, tilt_y; + + /* Layout and logical ranges come from the report-0x01 HID collection. */ + x = min_t(u16, get_unaligned_le16(&content[1]), G6TS_PEN_X_MAX); + y = min_t(u16, get_unaligned_le16(&content[3]), G6TS_PEN_Y_MAX); + pressure = min_t(u16, get_unaligned_le16(&content[5]), + G6TS_PEN_PRESSURE_MAX); + raw_tilt_x = min_t(u16, get_unaligned_le16(&content[7]), + G6TS_PEN_TILT_RAW_MAX); + raw_tilt_y = min_t(u16, get_unaligned_le16(&content[9]), + G6TS_PEN_TILT_RAW_MAX); + /* + * HID maps logical 0..18000 to physical -9000..9000 at a -2 + * degree exponent. Linux therefore sees signed hundredths of a + * degree, centered at zero, while this dormant native path stays a + * guarded fallback. + */ + tilt_x = raw_tilt_x - G6TS_PEN_TILT_CENTER; + tilt_y = raw_tilt_y - G6TS_PEN_TILT_CENTER; + + touchscreen_report_pos(input, &ts->pen_prop, x, y, false); + input_report_abs(input, ABS_PRESSURE, pressure); + input_report_abs(input, ABS_TILT_X, tilt_x); + input_report_abs(input, ABS_TILT_Y, tilt_y); + input_report_key(input, BTN_TOUCH, touching); + input_report_key(input, BTN_STYLUS, barrel); + input_report_key(input, BTN_TOOL_PEN, in_range && !rubber); + input_report_key(input, BTN_TOOL_RUBBER, in_range && rubber); + input_sync(input); +} + +static void g6ts_send_heat_feedback_a5(struct g6ts *ts, + bool after_heat_group); + +static void g6ts_handle_data_report(struct g6ts *ts) +{ + const u8 *payload = ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE; + u16 x, y; + bool active; + int ret; + + if (ts->last_class != DATA) + return; + ts->report_counts[ts->last_content_id]++; + /* Preserve raw pen measurements before touch-readiness can discard them. */ + if (g6ts_is_raw_export_report(ts->last_content_id)) + g6ts_heat_enqueue(ts, ts->last_content_id, payload, + ts->last_content_len); + /* + * HID-SPI stores the report ID immediately before content, so body + 3 + * is the exact hidraw packet expected by iptsd. The full allocation size + * is supplied because report 0x1a is 4,350 bytes including its ID. + */ + if (ts->ipts_hid_ready && + g6ts_is_ipts_hid_report(ts->last_content_id)) { + ret = hid_safe_input_report(ts->ipts_hid, HID_INPUT_REPORT, + ts->body + 3, G6TS_MAX_BODY - 3, + ts->last_content_len + 1, 1); + if (ret && ret != -ENODEV && ret != -EBUSY) + dev_warn_ratelimited(&ts->spi->dev, + "failed to relay DFT report 0x%02x: %d\n", + ts->last_content_id, ret); + } + switch (ts->last_content_id) { + case 0x1a: + g6ts_send_heat_feedback_a5(ts, true); + break; + case 0x0d: + ts->a5.cycle_saw_0x0d = true; + break; + case 0x0b: + if (ts->a5.cycle_saw_0x0d) { + ts->a5.cycle_saw_0x0d = false; + g6ts_send_heat_feedback_a5(ts, false); + } + break; + } + /* + * Heat is demand-driven on this panel: the first frame may not exist until + * a finger reaches the glass. Phase 77 therefore opens the response path + * after the mode handshake, but suppresses every non-Heat input report + * until a complete Heat frame has passed the normal structural parser. + * Pen input is an independent HID collection and remains usable while + * touch readiness is being established. + */ + if (ts->awaiting_ready_heat && + ts->last_content_id != G6TS_HEATMAP_REPORT_ID && + ts->last_content_id != G6TS_PEN_REPORT_ID) + return; + + if (ts->last_content_id == G6TS_PEN_REPORT_ID) { + if (ts->last_content_len != G6TS_PEN_REPORT_LEN) { + dev_warn_ratelimited(&ts->spi->dev, + "malformed pen report length: %u\n", + ts->last_content_len); + return; + } + g6ts_report_pen(ts, payload); + return; + } + + if (ts->last_content_id == 0x40 && ts->last_content_len == 5) { + active = payload[0] & BIT(0); + x = get_unaligned_le16(&payload[1]); + y = get_unaligned_le16(&payload[3]); + + input_report_key(ts->input, BTN_TOUCH, active); + if (active) + touchscreen_report_pos(ts->input, &ts->prop, x, y, false); + input_sync(ts->input); + return; + } + + if (ts->last_content_id == G6TS_HEATMAP_REPORT_ID && + ts->last_content_len + 1 <= G6TS_MAX_BODY) { + int ret; + + ret = g6ts_report_heat_contacts(ts, payload, ts->last_content_len); + if (ret) { + if (ts->awaiting_ready_heat) + ts->ready_verification_failures++; + g6ts_release_contacts(ts); + dev_warn_ratelimited(&ts->spi->dev, + "malformed Heat frame: %d\n", ret); + } else if (ts->awaiting_ready_heat) { + ts->awaiting_ready_heat = false; + ts->ready_heat_frames++; + dev_info(&ts->spi->dev, + "touch input ready after first valid Heat frame\n"); + } + } +} + +/* Read one complete pending HID-over-SPI response, and never retry. */ +static int g6ts_dma_read_response(struct g6ts *ts) +{ + const struct hidspi_dev_descriptor *descriptor; + s64 interrupt_edges; + size_t body_len; + u16 words; + int pending; + int ret; + + g6ts_clear_last_response(ts); + pending = g6ts_pending(ts); + interrupt_edges = atomic64_read(&ts->interrupt_edges); + if (pending <= 0 && + interrupt_edges <= ts->handled_interrupt_edges) { + return pending < 0 ? pending : -EAGAIN; + } + ts->handled_interrupt_edges = interrupt_edges; + + ret = g6ts_dma_read_pair(ts, g6ts_header_cmd, ts->last_header, + sizeof(ts->last_header)); + if (ret) { + ts->fatal_transport_error = true; + return ret; + } + + if ((ts->last_header[0] & 0x0f) != G6TS_HEADER_VERSION || + ts->last_header[3] != G6TS_HEADER_SYNC) { + if (g6ts_ready_quiesce) { + /* Let the panel retire the body transaction before rechecking. */ + usleep_range(100, 200); + pending = g6ts_pending(ts); + if (!pending) { + ts->quiesced_empty_reads++; + return -EAGAIN; + } + if (pending < 0) + return pending; + } + dev_warn_ratelimited(&ts->spi->dev, + "invalid HID-SPI header=%4ph ready=%d\n", + ts->last_header, g6ts_pending(ts)); + return -EPROTO; + } + + words = get_unaligned_le16(&ts->last_header[1]) & 0x3fff; + body_len = (size_t)words * 4; + if (body_len < HIDSPI_INPUT_BODY_HEADER_SIZE || + body_len > G6TS_MAX_BODY) + return -EMSGSIZE; + if (g6ts_windows_read_cadence) + usleep_range(G6TS_WINDOWS_HEADER_BODY_MIN_US, + G6TS_WINDOWS_HEADER_BODY_MAX_US); + + ret = g6ts_dma_read_pair(ts, g6ts_body_cmd, ts->body, body_len); + if (ret) { + ts->fatal_transport_error = true; + return ret; + } + + ts->last_class = ts->body[0]; + ts->last_content_len = get_unaligned_le16(&ts->body[1]); + ts->last_content_id = ts->body[3]; + if (ts->last_content_len > body_len - HIDSPI_INPUT_BODY_HEADER_SIZE) + return -EPROTO; + + if (ts->last_class == DEVICE_DESCRIPTOR_RESPONSE && + ts->last_content_len == HIDSPI_DEVICE_DESCRIPTOR_SIZE) { + descriptor = (const struct hidspi_dev_descriptor *) + (ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE); + ts->expected_report_descriptor_len = + le16_to_cpu(descriptor->rep_desc_len); + } + /* Recovery consumes and validates replies before reopening Linux input. */ + if (!g6ts_is_quiescing(ts) && READ_ONCE(ts->mode_enabled)) + g6ts_handle_data_report(ts); + return 0; +} + +/* io_lock is held by both the IRQ thread and the recovery worker. */ +static void g6ts_note_panel_reset_locked(struct g6ts *ts, + bool schedule_recovery) +{ + unsigned long now = jiffies; + unsigned long interval_ms = 0; + + if (ts->last_reset_jiffies) + interval_ms = jiffies_to_msecs(now - ts->last_reset_jiffies); + ts->last_reset_jiffies = now; + ts->reset_notifications++; + ts->mode_enabled = false; + g6ts_ipts_irq_disable_nosync(ts); + ts->awaiting_ready_heat = false; + ts->recovery_path = g6ts_reset_recovery_v2 ? + G6TS_RECOVERY_SOFTWARE : G6TS_RECOVERY_HARDWARE; + if (g6ts_reset_storm_breaker) { + if (interval_ms && interval_ms <= G6TS_RESET_STORM_WINDOW_MS) + ts->rapid_reset_streak++; + else + ts->rapid_reset_streak = 1; + + if (ts->rapid_reset_streak >= G6TS_RESET_STORM_LIMIT) { + ts->recovery_path = G6TS_RECOVERY_HARDWARE; + ts->reset_storm_escalations++; + dev_warn(&ts->spi->dev, + "rapid reset circuit breaker #%llu after %u resets\n", + ts->reset_storm_escalations, + ts->rapid_reset_streak); + } + } + g6ts_release_inputs(ts); + g6ts_heat_generation_boundary(ts, G6TS_HEAT_RECORD_F_RESET); + dev_warn(&ts->spi->dev, + "panel reset notification #%llu interval=%lums\n", + ts->reset_notifications, interval_ms); + + if (schedule_recovery && !g6ts_is_quiescing(ts)) + schedule_delayed_work(&ts->recovery_work, + msecs_to_jiffies(G6TS_RECOVERY_DELAY_MS)); +} + +/* io_lock is held and the caller has observed one complete IRQ read failure. */ +static void g6ts_note_host_fault_locked(struct g6ts *ts, int error) +{ + if (error == -EPROTO || error == -EMSGSIZE) + ts->irq_protocol_errors++; + else + ts->irq_transport_errors++; + ts->last_host_fault = error; + g6ts_heat_generation_boundary(ts, + G6TS_HEAT_RECORD_F_TRANSPORT_FAULT); + + if (!g6ts_host_fault_recovery) { + dev_warn_ratelimited(&ts->spi->dev, + "IRQ response read failed: %d\n", error); + return; + } + + /* + * A fresh hardware recovery is allowed to use the transport again. A new + * fatal error during that attempt will still stop the worker, preserving + * the existing bounded-failure behavior. + */ + ts->fatal_transport_error = false; + ts->mode_enabled = false; + g6ts_ipts_irq_disable_nosync(ts); + ts->awaiting_ready_heat = false; + ts->recovery_path = G6TS_RECOVERY_HARDWARE; + ts->rapid_reset_streak = 0; + ts->host_fault_recoveries++; + g6ts_release_inputs(ts); + dev_warn(&ts->spi->dev, + "host HID-SPI fault #%llu ret=%d; scheduling cold recovery\n", + ts->host_fault_recoveries, error); + + if (!g6ts_is_quiescing(ts)) + schedule_delayed_work(&ts->recovery_work, + msecs_to_jiffies(G6TS_RECOVERY_DELAY_MS)); +} + +static irqreturn_t g6ts_interrupt_thread(int irq, void *data) +{ + struct g6ts *ts = data; + unsigned int i; + int ret; + + if (g6ts_is_quiescing(ts) || !READ_ONCE(ts->mode_enabled)) { + g6ts_ipts_irq_disable_nosync(ts); + return IRQ_HANDLED; + } + + mutex_lock(&ts->io_lock); + for (i = 0; i < G6TS_IRQ_DRAIN_LIMIT; i++) { + if (!g6ts_has_unread_response(ts)) + break; + ret = g6ts_dma_read_response(ts); + if (ret) { + if (ret != -EAGAIN) + g6ts_note_host_fault_locked(ts, ret); + break; + } + if (ts->last_class == RESET_RESPONSE) { + g6ts_note_panel_reset_locked(ts, true); + break; + } + if (g6ts_windows_read_cadence || g6ts_ipts_irq_cadence) { + ts->cadence_single_response_irqs++; + break; + } + } + /* + * The default IRQ path drains the edge-triggered stream while GPIO51 still + * advertises an unread packet. Phase 84 uses the firmware's level-low IRQ, + * so returning after one response retriggers while more data is pending. + * Bound only the default drain for safety, then use the same observable + * host-fault recovery as a timed-out Windows transfer. + */ + if (i == G6TS_IRQ_DRAIN_LIMIT && g6ts_has_unread_response(ts)) { + ts->irq_drain_overflows++; + g6ts_note_host_fault_locked(ts, -EOVERFLOW); + } + mutex_unlock(&ts->io_lock); + return IRQ_HANDLED; +} + +static int __g6ts_dma_feature_exchange(struct g6ts *ts, u8 report_type, + u8 content_id, const u8 *content, + size_t content_len, bool dump_response) +{ + char dump_prefix[64]; + u8 expected_class; + unsigned int response_index; + int ret; + + if (report_type == SET_FEATURE) + expected_class = SET_FEATURE_RESPONSE; + else if (report_type == GET_FEATURE) + expected_class = GET_FEATURE_RESPONSE; + else + return -EINVAL; + + ret = g6ts_dma_hidspi_output(ts, report_type, content_id, + content, content_len); + if (ret) { + ts->fatal_transport_error = true; + return ret; + } + + for (response_index = 0; + response_index < G6TS_FEATURE_RESPONSE_LIMIT; + response_index++) { + ret = g6ts_wait_pending(ts, 1000); + if (ret) + return ret; + + ret = g6ts_dma_read_response(ts); + if (ret) + return ret; + + if (ts->last_class == expected_class && + ts->last_content_id == content_id) { + if (dump_response && report_type == GET_FEATURE && + !ts->init_get_feature_dumped[ts->initialization_stage]) { + ts->init_get_feature_dumped[ts->initialization_stage] = true; + scnprintf(dump_prefix, sizeof(dump_prefix), + "%s init GET_FEATURE 0x%02x: ", + dev_name(&ts->spi->dev), content_id); + dev_info(&ts->spi->dev, + "init GET_FEATURE response stage=%s id=0x%02x len=%u\n", + g6ts_initialization_stage_name(ts->initialization_stage), + content_id, ts->last_content_len); + print_hex_dump(KERN_INFO, dump_prefix, + DUMP_PREFIX_OFFSET, 16, 1, + ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE, + ts->last_content_len, false); + } + return 0; + } + if (ts->last_class == RESET_RESPONSE) { + g6ts_note_panel_reset_locked(ts, false); + return -EPIPE; + } + + /* Streaming data can precede a solicited feature response. */ + if (ts->last_class == DATA) + continue; + if (ts->last_class == OUTPUT_REPORT_RESPONSE && + ts->last_content_id == 0x09) + continue; + + return -EPROTO; + } + + return -EOVERFLOW; +} + +static int g6ts_dma_feature_exchange(struct g6ts *ts, u8 report_type, + u8 content_id, const u8 *content, + size_t content_len) +{ + return __g6ts_dma_feature_exchange(ts, report_type, content_id, content, + content_len, true); +} + +static int g6ts_cache_ipts_metadata_locked(struct g6ts *ts) +{ + const u8 *metadata = + ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE; + + if (ts->last_class != GET_FEATURE_RESPONSE || + ts->last_content_id != G6TS_IPTS_METADATA_REPORT_ID || + ts->last_content_len != G6TS_IPTS_METADATA_LEN) + return -EPROTO; + if (ts->ipts_metadata_valid && + memcmp(ts->ipts_metadata, metadata, G6TS_IPTS_METADATA_LEN)) { + dev_err(&ts->spi->dev, + "IPTS metadata changed across transport generation\n"); + return -EPROTO; + } + + memcpy(ts->ipts_metadata, metadata, G6TS_IPTS_METADATA_LEN); + ts->ipts_metadata_valid = true; + return 0; +} + +static int g6ts_ipts_hid_ll_parse(struct hid_device *hid) +{ + struct g6ts *ts = hid->driver_data; + + if (!ts) + return -ENODEV; + + if (!READ_ONCE(ts->report_descriptor_valid)) + return -ENODEV; + + return hid_parse_report(hid, ts->report_descriptor, + G6TS_SP11_REPORT_DESCRIPTOR_LEN); +} + +static int g6ts_ipts_hid_ll_start(struct hid_device *hid) +{ + return 0; +} + +static void g6ts_ipts_hid_ll_stop(struct hid_device *hid) +{ +} + +static int g6ts_ipts_hid_ll_open(struct hid_device *hid) +{ + return 0; +} + +static void g6ts_ipts_hid_ll_close(struct hid_device *hid) +{ +} + +/* + * The custom transport owns mode selection. iptsd's report-0x05 writes are + * therefore acknowledged without reaching the panel; in particular, its + * shutdown write must not switch the shared controller back to singletouch. + * The metadata GET is proxied once and then served from the stable cache. + */ +static int g6ts_ipts_hid_ll_raw_request(struct hid_device *hid, + unsigned char reportnum, u8 *buf, + size_t len, unsigned char rtype, + int reqtype) +{ + struct g6ts *ts = hid->driver_data; + size_t metadata_len; + int ret; + + if (!ts) + return -ENODEV; + if (!buf || len < 2) + return -EINVAL; + if (rtype != HID_FEATURE_REPORT) + return -EOPNOTSUPP; + + mutex_lock(&ts->io_lock); + if (g6ts_is_quiescing(ts) || ts->ipts_hid != hid) { + ret = -ENODEV; + goto out_unlock; + } + + if (reqtype == HID_REQ_SET_REPORT) { + if (reportnum != G6TS_IPTS_MODE_REPORT_ID || + buf[0] != reportnum || len != 2 || buf[1] > 1) { + ret = -EOPNOTSUPP; + goto out_unlock; + } + ret = len; + goto out_unlock; + } + + if (reqtype != HID_REQ_GET_REPORT || + reportnum != G6TS_IPTS_METADATA_REPORT_ID) { + ret = -EOPNOTSUPP; + goto out_unlock; + } + if (!READ_ONCE(ts->mode_enabled)) { + ret = -EHOSTDOWN; + goto out_unlock; + } + + if (!ts->ipts_metadata_valid) { + ret = __g6ts_dma_feature_exchange(ts, GET_FEATURE, + G6TS_IPTS_METADATA_REPORT_ID, + NULL, 0, false); + if (!ret) + ret = g6ts_cache_ipts_metadata_locked(ts); + if (ret) { + if (ret == -EPIPE && !g6ts_is_quiescing(ts)) + schedule_delayed_work(&ts->recovery_work, + msecs_to_jiffies(G6TS_RECOVERY_DELAY_MS)); + goto out_unlock; + } + } + + metadata_len = min_t(size_t, len - 1, G6TS_IPTS_METADATA_LEN); + buf[0] = reportnum; + memcpy(buf + 1, ts->ipts_metadata, metadata_len); + ret = metadata_len + 1; + +out_unlock: + mutex_unlock(&ts->io_lock); + return ret; +} + +static const struct hid_ll_driver g6ts_ipts_hid_ll_driver = { + .parse = g6ts_ipts_hid_ll_parse, + .start = g6ts_ipts_hid_ll_start, + .stop = g6ts_ipts_hid_ll_stop, + .open = g6ts_ipts_hid_ll_open, + .close = g6ts_ipts_hid_ll_close, + .raw_request = g6ts_ipts_hid_ll_raw_request, + .max_buffer_size = G6TS_MAX_BODY, +}; + +static bool g6ts_ipts_hid_desired_locked(const struct g6ts *ts) +{ + return g6ts_ipts_hid_bridge && !g6ts_is_quiescing(ts) && + READ_ONCE(ts->mode_enabled) && + ts->report_descriptor_valid && ts->hid_product_id; +} + +static struct hid_device *g6ts_ipts_hid_detach_locked(struct g6ts *ts) +{ + struct hid_device *hid = ts->ipts_hid; + + ts->ipts_hid = NULL; + ts->ipts_hid_ready = false; + ts->hid_bound_generation = 0; + return hid; +} + +static struct hid_device *g6ts_ipts_hid_allocate(struct g6ts *ts, + u16 product_id) +{ + struct hid_device *hid; + + hid = hid_allocate_device(); + if (IS_ERR(hid)) + return hid; + + /* Low-level transports own driver_data; drvdata belongs to the HID client. */ + hid->driver_data = ts; + hid->ll_driver = &g6ts_ipts_hid_ll_driver; + hid->dev.parent = &ts->spi->dev; + hid->bus = BUS_SPI; + hid->group = HID_GROUP_MSHW0485_IPTS; + hid->vendor = G6TS_SP11_VENDOR_ID; + hid->product = product_id; + hid->version = G6TS_SP11_VERSION_ID; + snprintf(hid->name, sizeof(hid->name), + "Microsoft Surface G6 IPTS %04X:%04X", + G6TS_SP11_VENDOR_ID, product_id); + snprintf(hid->phys, sizeof(hid->phys), "%s/ipts", + dev_name(&ts->spi->dev)); + + return hid; +} + +static bool g6ts_ipts_hid_retry_locked(struct g6ts *ts, u32 generation) +{ + if (!g6ts_ipts_hid_desired_locked(ts) || ts->ipts_hid || + ts->hid_target_generation != generation || + ts->hid_rebind_failures >= G6TS_HID_REBIND_RETRY_LIMIT) + return false; + + ts->hid_rebind_failures++; + return true; +} + +/* + * HID teardown may take hidraw's minors_rwsem for write. Never destroy while + * io_lock is held: a concurrent feature ioctl takes that rwsem for read before + * entering our raw_request callback and acquiring io_lock. + */ +static void g6ts_ipts_hid_rebind_work(struct work_struct *work) +{ + struct g6ts *ts = container_of(to_delayed_work(work), struct g6ts, + hid_rebind_work); + struct hid_device *old_hid = NULL; + struct hid_device *hid; + bool create = false; + bool retry = false; + u32 generation = 0; + u16 product_id = 0; + int ret; + + mutex_lock(&ts->io_lock); + if (ts->ipts_hid && + (!g6ts_ipts_hid_desired_locked(ts) || + ts->hid_bound_generation != ts->hid_target_generation)) + old_hid = g6ts_ipts_hid_detach_locked(ts); + if (!ts->ipts_hid && g6ts_ipts_hid_desired_locked(ts)) { + generation = ts->hid_target_generation; + product_id = ts->hid_product_id; + create = true; + } + mutex_unlock(&ts->io_lock); + + if (old_hid) + hid_destroy_device(old_hid); + if (!create) + return; + + hid = g6ts_ipts_hid_allocate(ts, product_id); + if (IS_ERR(hid)) { + ret = PTR_ERR(hid); + mutex_lock(&ts->io_lock); + retry = g6ts_ipts_hid_retry_locked(ts, generation); + mutex_unlock(&ts->io_lock); + dev_err(&ts->spi->dev, + "failed to allocate IPTS HID device: %d%s\n", ret, + retry ? "; retrying" : ""); + if (retry) + mod_delayed_work(system_wq, &ts->hid_rebind_work, + msecs_to_jiffies(G6TS_HID_REBIND_RETRY_MS)); + return; + } + + mutex_lock(&ts->io_lock); + if (!g6ts_ipts_hid_desired_locked(ts) || ts->ipts_hid || + ts->hid_target_generation != generation || + ts->hid_product_id != product_id) { + mutex_unlock(&ts->io_lock); + hid_destroy_device(hid); + return; + } + ts->ipts_hid = hid; + ts->ipts_hid_ready = false; + ts->hid_bound_generation = generation; + mutex_unlock(&ts->io_lock); + + ret = hid_add_device(hid); + if (!ret && hid->claimed != HID_CLAIMED_HIDRAW) + ret = -ENODEV; + + mutex_lock(&ts->io_lock); + if (!ret && ts->ipts_hid == hid && + g6ts_ipts_hid_desired_locked(ts) && + ts->hid_target_generation == generation) { + ts->ipts_hid_ready = true; + ts->hid_rebind_failures = 0; + mutex_unlock(&ts->io_lock); + dev_info(&ts->spi->dev, + "IPTS HIDRAW bridge ready generation=%u product=%04x\n", + generation, product_id); + return; + } + if (ts->ipts_hid == hid) + g6ts_ipts_hid_detach_locked(ts); + if (ret) + retry = g6ts_ipts_hid_retry_locked(ts, generation); + mutex_unlock(&ts->io_lock); + + if (ret) + dev_err(&ts->spi->dev, + "failed to register HIDRAW-only IPTS device: %d%s\n", + ret, retry ? "; retrying" : ""); + hid_destroy_device(hid); + if (retry) + mod_delayed_work(system_wq, &ts->hid_rebind_work, + msecs_to_jiffies(G6TS_HID_REBIND_RETRY_MS)); +} + +static int g6ts_expect_response(struct g6ts *ts, u8 response_class, + u8 content_id, size_t min_content_len) +{ + if (ts->last_class != response_class || + ts->last_content_id != content_id || + ts->last_content_len < min_content_len) + return -EPROTO; + + return 0; +} + +static int g6ts_validate_sp11_device_descriptor(struct g6ts *ts) +{ + const struct hidspi_dev_descriptor *descriptor; + u16 product_id; + + if (ts->last_class != DEVICE_DESCRIPTOR_RESPONSE || + ts->last_content_id != 0 || + ts->last_content_len != HIDSPI_DEVICE_DESCRIPTOR_SIZE) + return -EPROTO; + + descriptor = (const struct hidspi_dev_descriptor *) + (ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE); + if (le16_to_cpu(descriptor->dev_desc_len) != + HIDSPI_DEVICE_DESCRIPTOR_SIZE || + le16_to_cpu(descriptor->bcd_ver) != 0x0300 || + le16_to_cpu(descriptor->rep_desc_len) != + G6TS_SP11_REPORT_DESCRIPTOR_LEN || + le16_to_cpu(descriptor->max_input_len) != G6TS_SP11_MAX_INPUT_LEN || + le16_to_cpu(descriptor->max_output_len) != G6TS_SP11_MAX_OUTPUT_LEN || + le16_to_cpu(descriptor->max_frag_len) != G6TS_SP11_MAX_FRAGMENT_LEN || + le16_to_cpu(descriptor->vendor_id) != G6TS_SP11_VENDOR_ID || + (le16_to_cpu(descriptor->product_id) != G6TS_SP11_X1E_PRODUCT_ID && + le16_to_cpu(descriptor->product_id) != G6TS_SP11_X1P_PRODUCT_ID) || + le16_to_cpu(descriptor->version_id) != G6TS_SP11_VERSION_ID || + le16_to_cpu(descriptor->flags) != G6TS_SP11_DESCRIPTOR_FLAGS || + le32_to_cpu(descriptor->reserved) != 0) + return -ENODEV; + + product_id = le16_to_cpu(descriptor->product_id); + if (ts->hid_product_id && ts->hid_product_id != product_id) + return -EPROTO; + ts->hid_product_id = product_id; + return 0; +} + +static int g6ts_recovery_read_expected(struct g6ts *ts, u8 response_class, + u8 content_id, size_t min_content_len); + +static bool g6ts_windows_feedback_provider_valid(void) +{ + return g6ts_parity_display_bitmap >= 0 && + g6ts_parity_display_bitmap <= U8_MAX && + (g6ts_parity_stitching_flag == 0 || + g6ts_parity_stitching_flag == 1) && + g6ts_parity_hinge_angle >= 0 && + g6ts_parity_fast_host_id >= 0 && + g6ts_parity_fast_host_id <= U16_MAX; +} + +static bool g6ts_windows_config_provider_valid(void) +{ + return g6ts_parity_report56_identity_count == + G6TS_WINDOWS_REPORT56_ID_LEN && + (g6ts_parity_report56_flag == 0 || + g6ts_parity_report56_flag == 1); +} + +static void g6ts_build_windows_feedback_a1(u8 content[G6TS_WINDOWS_FEEDBACK_LEN]) +{ + memset(content, 0, G6TS_WINDOWS_FEEDBACK_LEN); + content[0] = 0x8e; + content[1] = 0xa1; + content[2] = g6ts_parity_display_bitmap; + content[3] = g6ts_parity_stitching_flag; + put_unaligned_le32(g6ts_parity_hinge_angle, &content[4]); + put_unaligned_le16(g6ts_parity_fast_host_id, &content[40]); +} + +static void g6ts_build_windows_feedback_a5(struct g6ts *ts, + u8 content[G6TS_WINDOWS_FEEDBACK_LEN]) +{ + memset(content, 0, G6TS_WINDOWS_FEEDBACK_LEN); + content[0] = 0x8e; + content[1] = 0xa5; + /* Initial V06 sequence and current-feedback flags with no pen record. */ + content[2] = 0; + content[3] = BIT(1); + put_unaligned_le16(ts->a5.fast_host_id, &content[39]); + /* The V06 sender unconditionally adds validity bit 0x0040. */ + put_unaligned_le16(0x0040, &content[46]); +} + +static void g6ts_send_heat_feedback_a5(struct g6ts *ts, + bool after_heat_group) +{ + /* + * This bounded encoder preserves the hardware-proven V06 timing and wire + * template; only sequence, cycle phase, and configured FastHostId are + * validated live state. Offsets 8..38 and the validity maps remain + * unmapped, so never replay a captured body or accept an opaque userspace + * payload in their place. + */ + u8 content[G6TS_WINDOWS_FEEDBACK_LEN] = { 0 }; + int ret; + + if (!g6ts_heat_feedback) + return; + if (!ts->a5.fast_host_id_valid) { + dev_warn_once(&ts->spi->dev, + "heat feedback disabled: parity_fast_host_id is unavailable or out of range\n"); + return; + } + + content[0] = 0x8e; + content[1] = 0xa5; + content[2] = ts->a5.sequence; + content[3] = 0x02; + put_unaligned_le16(0x1770, &content[12]); + content[34] = 0xff; + content[35] = 0x4c; + put_unaligned_le16(ts->a5.fast_host_id, &content[39]); + content[41] = 0x01; + content[43] = after_heat_group ? 0x04 : 0x02; + content[44] = 0xff; + content[46] = 0x52; + content[47] = 0x43; + content[48] = 0xff; + content[49] = 0x02; + content[50] = 0x01; + + ret = g6ts_dma_hidspi_output(ts, OUTPUT_REPORT, 0x09, content, + sizeof(content)); + if (ret) { + dev_warn_ratelimited(&ts->spi->dev, + "failed to send heat feedback phase %#02x: %d\n", + content[43], ret); + return; + } + + /* Advance only after a successful write; u8 wrap is the wire behavior. */ + ts->a5.sequence++; + ts->heat_feedback_sent++; + if (after_heat_group) + ts->heat_feedback_phase_a++; + else + ts->heat_feedback_phase_b++; +} + +static bool g6ts_windows_cfu_provider_valid(void) +{ + /* Force-immediate and force-ignore-version are development-only bits. */ + return g6ts_parity_cfu_offer_count == G6TS_WINDOWS_CFU_OFFER_LEN && + !(g6ts_parity_cfu_offer[1] & (BIT(6) | BIT(7))) && + !memcmp(g6ts_parity_cfu_offer, g6ts_sp11_cfu_offer, + G6TS_WINDOWS_CFU_OFFER_LEN); +} + +static void +g6ts_build_windows_cfu_info(u8 content[G6TS_WINDOWS_CFU_OFFER_LEN], + u8 information_code) +{ + memset(content, 0, G6TS_WINDOWS_CFU_OFFER_LEN); + content[0] = information_code; + content[2] = 0xff; + content[3] = G6TS_WINDOWS_CFU_TOKEN; +} + +static bool g6ts_windows_cfu_response_well_formed(const u8 *content) +{ + return content[0] == 0 && content[1] == 0 && content[2] == 0 && + content[3] == G6TS_WINDOWS_CFU_TOKEN && + get_unaligned_le32(&content[4]) == 0 && + content[9] == 0 && content[10] == 0 && content[11] == 0 && + content[13] == 0 && content[14] == 0 && content[15] == 0; +} + +static int g6ts_windows_cfu_send_locked(struct g6ts *ts, const u8 *content) +{ + int ret; + + ret = g6ts_dma_hidspi_output(ts, OUTPUT_REPORT, 0x65, content, + G6TS_WINDOWS_CFU_OFFER_LEN); + if (ret) + return ret; + + ret = g6ts_recovery_read_expected(ts, DATA, 0x65, + G6TS_WINDOWS_CFU_OFFER_LEN); + if (ret || ts->last_content_len != G6TS_WINDOWS_CFU_OFFER_LEN) + return ret ? ret : -EPROTO; + + content = ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE; + if (!g6ts_windows_cfu_response_well_formed(content)) + return -EPROTO; + + return 0; +} + +static int g6ts_windows_cfu_expect_info_accept(struct g6ts *ts) +{ + const u8 *content = ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE; + + /* The target returns 0xff in the don't-care reject-reason byte. */ + if (content[8] != 0xff || content[12] != 0x01) + return -EPROTO; + + return 0; +} + +static int g6ts_windows_cfu_inventory_locked(struct g6ts *ts) +{ + u8 transaction[G6TS_WINDOWS_CFU_OFFER_LEN]; + const u8 *content; + int ret; + + /* Captured gap between the config owner and CFU collection attach. */ + msleep(G6TS_WINDOWS_CFU_DELAY_MS); + + ts->initialization_stage = G6TS_INIT_WINDOWS_CFU_GET_VERSION; + ret = g6ts_dma_feature_exchange(ts, GET_FEATURE, 0x60, NULL, 0); + if (ret) + return ret; + ret = g6ts_expect_response(ts, GET_FEATURE_RESPONSE, 0x60, + G6TS_WINDOWS_CFU_VERSION_LEN); + if (ret || ts->last_content_len != G6TS_WINDOWS_CFU_VERSION_LEN) + return ret ? ret : -EPROTO; + content = ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE; + memcpy(ts->parity_cfu_version_prefix, content, + sizeof(ts->parity_cfu_version_prefix)); + /* + * Decode only the header and the one declared component. Bytes after the + * component-count boundary are not inputs to the CFU decision. + */ + if (content[0] != 1 || content[1] != 0 || content[2] != 0 || + content[3] != 0x04 || + memcmp(&content[4], &g6ts_parity_cfu_offer[4], 4) || + content[9] != g6ts_parity_cfu_offer[2]) + return -EPROTO; + + ts->initialization_stage = G6TS_INIT_WINDOWS_CFU_START_TRANSACTION; + g6ts_build_windows_cfu_info(transaction, 0); + ret = g6ts_windows_cfu_send_locked(ts, transaction); + if (ret) + return ret; + ret = g6ts_windows_cfu_expect_info_accept(ts); + if (ret) + return ret; + + ts->initialization_stage = G6TS_INIT_WINDOWS_CFU_START_LIST; + g6ts_build_windows_cfu_info(transaction, 1); + ret = g6ts_windows_cfu_send_locked(ts, transaction); + if (ret) + return ret; + ret = g6ts_windows_cfu_expect_info_accept(ts); + if (ret) + return ret; + + ts->initialization_stage = G6TS_INIT_WINDOWS_CFU_OFFER; + memcpy(transaction, g6ts_parity_cfu_offer, sizeof(transaction)); + transaction[3] = G6TS_WINDOWS_CFU_TOKEN; + ret = g6ts_windows_cfu_send_locked(ts, transaction); + if (ret) + return ret; + content = ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE; + memcpy(ts->parity_cfu_offer_response, content, + sizeof(ts->parity_cfu_offer_response)); + if (content[8] != 0 || content[12] != 0x02) { + /* + * Windows branches into payload, replay, or busy handling here. This + * driver intentionally implements none of those firmware-update paths. + */ + ts->initialization_stage = G6TS_INIT_WINDOWS_CFU_BRANCH_REQUIRED; + ts->parity_cfu_branch_required = true; + dev_notice(&ts->spi->dev, + "Windows CFU branch required: reject_reason=%#x status=%#x; no payload sent\n", + content[8], content[12]); + return 0; + } + + ts->initialization_stage = G6TS_INIT_WINDOWS_CFU_END_LIST; + g6ts_build_windows_cfu_info(transaction, 2); + ret = g6ts_windows_cfu_send_locked(ts, transaction); + if (ret) + return ret; + ret = g6ts_windows_cfu_expect_info_accept(ts); + if (ret) + return ret; + + /* Captured gap before the device-config owner's post-CFU query. */ + msleep(G6TS_WINDOWS_FINAL_CONFIG_DELAY_MS); + ts->initialization_stage = G6TS_INIT_WINDOWS_FINAL_FEATURE73; + ret = g6ts_dma_feature_exchange(ts, GET_FEATURE, 0x73, NULL, 0); + if (ret) + return ret; + ret = g6ts_expect_response(ts, GET_FEATURE_RESPONSE, 0x73, 2); + if (ret || ts->last_content_len != 2) + return ret ? ret : -EPROTO; + content = ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE; + memcpy(ts->parity_feature73_late, content, + sizeof(ts->parity_feature73_late)); + + if (!g6ts_parity_heat_input) { + ts->initialization_stage = G6TS_INIT_WINDOWS_HEAT_OWNER_REQUIRED; + ts->parity_heat_owner_required = true; + dev_notice(&ts->spi->dev, + "Windows cold chronology reached Heat boundary: early73=%2ph late73=%2ph; input remains disabled\n", + ts->parity_feature73_early, + ts->parity_feature73_late); + return 0; + } + + /* + * SET_FEATURE 0x05 already activated the Heat collection in the captured + * owner order. Do not send another mode command here: merely open the + * response consumer and require the first complete report 0x12 to pass the + * normal structural parser before declaring input ready. + */ + ts->initialization_stage = G6TS_INIT_WAIT_HEAT; + ts->awaiting_ready_heat = true; + ts->mode_enabled = true; + dev_notice(&ts->spi->dev, + "Windows init+CFU chronology complete: early73=%2ph late73=%2ph; waiting for first valid Heat frame\n", + ts->parity_feature73_early, ts->parity_feature73_late); + return 0; +} + +/* + * Reproduce only the proven, serialized part of the Windows cold collection + * attach. Dynamic values must come from their owning provider. Returning + * success with mode_enabled clear intentionally leaves this diagnostic driver + * bound and observable without claiming that normal touch mode was reached. + */ +static int g6ts_windows_cold_attach_locked(struct g6ts *ts) +{ + u8 feedback[G6TS_WINDOWS_FEEDBACK_LEN]; + u8 report56[G6TS_WINDOWS_REPORT56_ID_LEN + 1]; + const u8 *content; + int ret; + + ts->initialization_stage = G6TS_INIT_WINDOWS_EARLY_FEATURE73; + ret = g6ts_dma_feature_exchange(ts, GET_FEATURE, 0x73, NULL, 0); + if (ret) + return ret; + ret = g6ts_expect_response(ts, GET_FEATURE_RESPONSE, 0x73, 2); + if (ret || ts->last_content_len != 2) + return ret ? ret : -EPROTO; + content = ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE; + memcpy(ts->parity_feature73_early, content, + sizeof(ts->parity_feature73_early)); + if (content[0] != 0xfe || content[1] != 0xff) + return -EPROTO; + + ts->initialization_stage = G6TS_INIT_WINDOWS_HEAT_CAPS06; + ret = g6ts_dma_feature_exchange(ts, GET_FEATURE, + G6TS_IPTS_METADATA_REPORT_ID, NULL, 0); + if (ret) + return ret; + ret = g6ts_expect_response(ts, GET_FEATURE_RESPONSE, + G6TS_IPTS_METADATA_REPORT_ID, + G6TS_IPTS_METADATA_LEN); + if (ret || ts->last_content_len != G6TS_IPTS_METADATA_LEN) + return ret ? ret : -EPROTO; + ret = g6ts_cache_ipts_metadata_locked(ts); + if (ret) + return ret; + content = ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE; + memcpy(ts->parity_feature06_prefix, content, + sizeof(ts->parity_feature06_prefix)); + + if (!g6ts_windows_feedback_provider_valid()) { + ts->initialization_stage = G6TS_INIT_WINDOWS_FEEDBACK_REQUIRED; + ts->parity_feedback_required = true; + ts->mode_enabled = false; + dev_notice(&ts->spi->dev, + "Windows parity boundary reached: early feature73=%2ph; A1/A5 provider inputs are required\n", + ts->parity_feature73_early); + return 0; + } + + ts->initialization_stage = G6TS_INIT_WINDOWS_FEEDBACK_A1; + g6ts_build_windows_feedback_a1(feedback); + ret = g6ts_dma_hidspi_output(ts, OUTPUT_REPORT, 0x09, feedback, + sizeof(feedback)); + if (ret) + return ret; + /* The captured SP11 cold attach acknowledges A1 with DATA report A0={01}. */ + ret = g6ts_recovery_read_expected(ts, DATA, 0xa0, 1); + if (ret || ts->last_content_len != 1 || + ts->body[HIDSPI_INPUT_BODY_HEADER_SIZE] != 0x01) + return ret ? ret : -EPROTO; + + ts->initialization_stage = G6TS_INIT_WINDOWS_FEEDBACK_A5; + g6ts_build_windows_feedback_a5(ts, feedback); + ret = g6ts_dma_hidspi_output(ts, OUTPUT_REPORT, 0x09, feedback, + sizeof(feedback)); + if (ret) + return ret; + + ts->initialization_stage = G6TS_INIT_WINDOWS_SET_FEATURE05; + ret = g6ts_dma_feature_exchange(ts, SET_FEATURE, 0x05, + g6ts_mode_enable, + sizeof(g6ts_mode_enable)); + if (ret) + return ret; + ret = g6ts_expect_response(ts, SET_FEATURE_RESPONSE, 0x05, 0); + if (ret || ts->last_content_len != 0) + return ret ? ret : -EPROTO; + + if (!g6ts_windows_config_provider_valid()) { + ts->initialization_stage = G6TS_INIT_WINDOWS_CONFIG_OWNER_REQUIRED; + ts->parity_config_owner_required = true; + ts->mode_enabled = false; + dev_notice(&ts->spi->dev, + "Windows parity boundary reached: report56 platform identity and flag are required\n"); + return 0; + } + + /* + * The complete cold KDNET trace places 476 ms between the SET_FEATURE 0x05 + * response and the independent config owner's GET_FEATURE 0x70. Preserve + * a conservative 470 ms owner boundary; this is not a panel retry delay. + */ + msleep(G6TS_WINDOWS_CONFIG_DELAY_MS); + + ts->initialization_stage = G6TS_INIT_WINDOWS_GET_FEATURE70; + ret = g6ts_dma_feature_exchange(ts, GET_FEATURE, 0x70, NULL, 0); + if (ret) + return ret; + ret = g6ts_expect_response(ts, GET_FEATURE_RESPONSE, 0x70, 1); + if (ret || ts->last_content_len != 1 || + ts->body[HIDSPI_INPUT_BODY_HEADER_SIZE] != 0x02) + return ret ? ret : -EPROTO; + + ts->initialization_stage = G6TS_INIT_WINDOWS_SET_FEATURE70; + ret = g6ts_dma_feature_exchange(ts, SET_FEATURE, 0x70, + g6ts_mode_enable, + sizeof(g6ts_mode_enable)); + if (ret) + return ret; + ret = g6ts_expect_response(ts, SET_FEATURE_RESPONSE, 0x70, 0); + if (ret || ts->last_content_len != 0) + return ret ? ret : -EPROTO; + + memcpy(report56, g6ts_parity_report56_identity, + G6TS_WINDOWS_REPORT56_ID_LEN); + report56[G6TS_WINDOWS_REPORT56_ID_LEN] = g6ts_parity_report56_flag; + ts->initialization_stage = G6TS_INIT_WINDOWS_SET_FEATURE56; + ret = g6ts_dma_feature_exchange(ts, SET_FEATURE, 0x56, + report56, sizeof(report56)); + if (ret) + return ret; + ret = g6ts_expect_response(ts, SET_FEATURE_RESPONSE, 0x56, 0); + if (ret || ts->last_content_len != 0) + return ret ? ret : -EPROTO; + + /* CFU collection attach is deliberately separate from touch activation. */ + if (!g6ts_parity_cfu_inventory || + !g6ts_windows_cfu_provider_valid()) { + ts->initialization_stage = G6TS_INIT_WINDOWS_CFU_OWNER_REQUIRED; + ts->parity_cfu_owner_required = true; + ts->mode_enabled = false; + dev_notice(&ts->spi->dev, + "Windows parity reached the CFU-owner boundary; inventory opt-in and exact offer are required\n"); + return 0; + } + + return g6ts_windows_cfu_inventory_locked(ts); +} + +static int g6ts_recovery_read_expected(struct g6ts *ts, u8 response_class, + u8 content_id, size_t min_content_len) +{ + unsigned int response_index; + int ret; + + for (response_index = 0; + response_index < G6TS_FEATURE_RESPONSE_LIMIT; + response_index++) { + ret = g6ts_wait_pending(ts, 1000); + if (ret) + return ret; + + ret = g6ts_dma_read_response(ts); + if (ret) + return ret; + if (ts->last_class == response_class && + ts->last_content_id == content_id && + ts->last_content_len >= min_content_len) + return 0; + if (ts->last_class == RESET_RESPONSE) { + g6ts_note_panel_reset_locked(ts, false); + return -EPIPE; + } + + /* Stale input can precede the solicited reply. */ + if (ts->last_class == DATA || + (ts->last_class == OUTPUT_REPORT_RESPONSE && + ts->last_content_id == 0x09)) + continue; + + return -EPROTO; + } + + return -EOVERFLOW; +} + +/* + * Cold startup requires the validated power/reset sequence and its resulting + * RESET_RESPONSE. A panel-originated reset has already completed that part + * and its response was consumed by the IRQ thread, so the Phase 77 path starts + * at host re-enumeration instead of forcing another hardware reset. + */ +static int g6ts_full_reinitialize_locked(struct g6ts *ts, + enum g6ts_recovery_path path) +{ + int ret; + + ts->mode_enabled = false; + ts->awaiting_ready_heat = false; + ts->expected_report_descriptor_len = 0; + ts->initialization_stage = G6TS_INIT_IDLE; + ts->parity_feedback_required = false; + ts->parity_config_owner_required = false; + ts->parity_cfu_owner_required = false; + ts->parity_cfu_branch_required = false; + ts->parity_heat_owner_required = false; + memset(ts->parity_feature73_early, 0, + sizeof(ts->parity_feature73_early)); + memset(ts->parity_feature73_late, 0, + sizeof(ts->parity_feature73_late)); + memset(ts->parity_feature06_prefix, 0, + sizeof(ts->parity_feature06_prefix)); + memset(ts->parity_cfu_version_prefix, 0, + sizeof(ts->parity_cfu_version_prefix)); + memset(ts->parity_cfu_offer_response, 0, + sizeof(ts->parity_cfu_offer_response)); + + if (path == G6TS_RECOVERY_HARDWARE) { + ts->hardware_recovery_attempts++; + ret = g6ts_power_off(ts); + if (ret) + return ret; + msleep(100); + ret = g6ts_windows_init_parity && !g6ts_parity_linux_power ? + g6ts_windows_power_on(ts) : g6ts_power_on(ts); + if (ret) + return ret; + + ts->initialization_stage = G6TS_INIT_RESET_RESPONSE; + ret = g6ts_wait_pending(ts, 1000); + if (ret) + goto out; + ret = g6ts_dma_read_response(ts); + if (ret) + goto out; + ret = g6ts_expect_response(ts, RESET_RESPONSE, 0, 0); + if (ret) + goto out; + } else { + ts->software_recovery_attempts++; + ts->initialization_stage = G6TS_INIT_RESET_RESPONSE; + } + + ts->initialization_stage = G6TS_INIT_DEVICE_DESCRIPTOR; + ret = g6ts_dma_output(ts, g6ts_device_descriptor_cmd, + sizeof(g6ts_device_descriptor_cmd)); + if (ret) { + ts->fatal_transport_error = true; + goto out; + } + ret = g6ts_recovery_read_expected(ts, DEVICE_DESCRIPTOR_RESPONSE, 0, + HIDSPI_DEVICE_DESCRIPTOR_SIZE); + if (ret) + goto out; + ret = g6ts_validate_sp11_device_descriptor(ts); + if (ret) + goto out; + if (!ts->expected_report_descriptor_len || + ts->expected_report_descriptor_len > + G6TS_MAX_BODY - HIDSPI_INPUT_BODY_HEADER_SIZE) { + ret = -EPROTO; + goto out; + } + + ts->initialization_stage = G6TS_INIT_REPORT_DESCRIPTOR; + ret = g6ts_dma_output(ts, g6ts_report_descriptor_cmd, + sizeof(g6ts_report_descriptor_cmd)); + if (ret) { + ts->fatal_transport_error = true; + goto out; + } + ret = g6ts_recovery_read_expected(ts, REPORT_DESCRIPTOR_RESPONSE, 0, + ts->expected_report_descriptor_len); + if (ret || ts->last_content_len != ts->expected_report_descriptor_len) { + if (!ret) + ret = -EPROTO; + goto out; + } + if (ts->report_descriptor_valid) { + if (memcmp(ts->report_descriptor, + ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE, + G6TS_SP11_REPORT_DESCRIPTOR_LEN)) { + dev_err(&ts->spi->dev, + "report descriptor changed across transport generation\n"); + ret = -EPROTO; + goto out; + } + } else { + memcpy(ts->report_descriptor, + ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE, + G6TS_SP11_REPORT_DESCRIPTOR_LEN); + ts->report_descriptor_valid = true; + } + + if (g6ts_windows_init_parity) { + /* A software reset has a different, multi-owner Windows ordering. */ + if (path != G6TS_RECOVERY_HARDWARE) { + ret = -EOPNOTSUPP; + goto out; + } + ret = g6ts_windows_cold_attach_locked(ts); + if (ret) + goto out; + return 0; + } + + /* + * Enter the panel's streaming personality with the smallest sequence + * proven by the Phase 55 through Phase 65 cold boots and reset recoveries. + * Reports 0x60, 0x65, 0x06, 0x09, and 0x73 in the Windows ETW capture + * belong to collection/application setup. Replaying them here prevented + * Heat from starting in both the Phase 66 and Phase 67 hardware trials. + */ + ts->initialization_stage = G6TS_INIT_SET_FEATURE05; + ret = g6ts_dma_feature_exchange(ts, SET_FEATURE, 0x05, + g6ts_mode_enable, + sizeof(g6ts_mode_enable)); + if (ret) + goto out; + ret = g6ts_expect_response(ts, SET_FEATURE_RESPONSE, 0x05, 0); + if (ret) + goto out; + + ts->mode_config_valid = false; + ts->mode_config_len = 0; + if (g6ts_ipts_minimal_init) { + dev_info(&ts->spi->dev, + "IPTS minimal init: SET_FEATURE 0x05 only; skipped feature 0x70/0x56\n"); + goto mode_ready; + } + + ts->initialization_stage = G6TS_INIT_GET_FEATURE70; + ret = g6ts_dma_feature_exchange(ts, GET_FEATURE, 0x70, NULL, 0); + if (ret) + goto out; + ret = g6ts_expect_response(ts, GET_FEATURE_RESPONSE, 0x70, 1); + if (ret) + goto out; + /* + * Capture the Linux panel's GET_FEATURE 0x70 content now, before another + * response overwrites ts->body. Phase 72 used it in the empirically stable + * combined sequence; this is not a byte-for-byte Windows feature exchange. + * Body layout: [0]=class [1..2]=len [3]=id [4..]=content. + */ + if (g6ts_mode_config_fix) { + size_t cfg_len = ts->last_content_len; + + if (cfg_len > sizeof(ts->mode_config)) + cfg_len = sizeof(ts->mode_config); + memcpy(ts->mode_config, + ts->body + HIDSPI_INPUT_BODY_HEADER_SIZE, cfg_len); + ts->mode_config_len = cfg_len; + ts->mode_config_valid = cfg_len > 0; + dev_info(&ts->spi->dev, + "phase72: GET_FEATURE 0x70 config len=%zu bytes=%*ph\n", + cfg_len, (int)cfg_len, ts->mode_config); + } + + ts->initialization_stage = G6TS_INIT_SET_FEATURE70; + if (g6ts_feature70_one_byte) { + dev_info(&ts->spi->dev, + "feature70-one-byte: SET_FEATURE 0x70 len=1 bytes=01\n"); + ret = g6ts_dma_feature_exchange(ts, SET_FEATURE, 0x70, + g6ts_mode_enable, + sizeof(g6ts_mode_enable)); + } else if (g6ts_mode_config_fix && ts->mode_config_valid) { + /* + * Phase 72 Linux sequence: SET_FEATURE 0x70 is 0x01 followed by the + * panel's GET_FEATURE 0x70 content. Windows declares one logical content + * byte for its captured SET_FEATURE 0x70 writes. + */ + u8 mode_setup[1 + sizeof(ts->mode_config)]; + size_t setup_len = 1 + ts->mode_config_len; + + mode_setup[0] = 0x01; + memcpy(&mode_setup[1], ts->mode_config, ts->mode_config_len); + dev_info(&ts->spi->dev, + "phase72: SET_FEATURE 0x70 derived len=%zu bytes=%*ph\n", + setup_len, (int)setup_len, mode_setup); + ret = g6ts_dma_feature_exchange(ts, SET_FEATURE, 0x70, + mode_setup, setup_len); + } else { + ret = g6ts_dma_feature_exchange(ts, SET_FEATURE, 0x70, + g6ts_mode_enable, + sizeof(g6ts_mode_enable)); + } + if (ret) + goto out; + ret = g6ts_expect_response(ts, SET_FEATURE_RESPONSE, 0x70, 0); + if (ret) + goto out; + + /* + * Phase 72 emits a short OUTPUT_REPORT 0x09 containing 0x8e followed by the + * Linux GET_FEATURE 0x70 content. KDNET confirms that Windows uses report + * 0x09 here, but with 63-byte content rather than this short form. This is + * best-effort: the read path already skips OUTPUT_REPORT_RESPONSE, so a + * missing or late acknowledgment does not abort initialization. + */ + if (g6ts_mode_config_fix && ts->mode_config_valid) { + u8 report09[1 + sizeof(ts->mode_config)]; + size_t report_len = 1 + ts->mode_config_len; + + report09[0] = 0x8e; + memcpy(&report09[1], ts->mode_config, ts->mode_config_len); + dev_info(&ts->spi->dev, + "phase72: OUTPUT_REPORT 0x09 len=%zu bytes=%*ph\n", + report_len, (int)report_len, report09); + ret = g6ts_dma_hidspi_output(ts, OUTPUT_REPORT, 0x09, + report09, report_len); + if (ret) { + ts->fatal_transport_error = true; + goto out; + } + } + + ts->initialization_stage = G6TS_INIT_SET_FEATURE56; + ret = g6ts_dma_feature_exchange(ts, SET_FEATURE, 0x56, + g6ts_mode_handshake, + sizeof(g6ts_mode_handshake)); + if (ret) + goto out; + ret = g6ts_expect_response(ts, SET_FEATURE_RESPONSE, 0x56, 0); + if (ret) + goto out; + +mode_ready: + if (g6ts_reset_recovery_v2) { + ts->initialization_stage = G6TS_INIT_WAIT_HEAT; + /* + * Do not synchronously wait here. The panel produces Heat on touch, + * so waiting before enabling the IRQ response path deadlocks startup. + * The first frame is parsed and admitted by g6ts_handle_data_report(). + */ + ts->awaiting_ready_heat = true; + } + + ts->mode_enabled = true; + return 0; +out: + ts->mode_enabled = false; + return ret; +} + +static void g6ts_recovery_work(struct work_struct *work) +{ + struct g6ts *ts = container_of(to_delayed_work(work), struct g6ts, + recovery_work); + enum g6ts_recovery_path path; + bool retry = false; + int ret; + + /* Synchronous recovery owns every response until mode_enabled is restored. */ + g6ts_ipts_irq_disable_sync(ts); + mutex_lock(&ts->io_lock); + if (g6ts_is_quiescing(ts)) { + mutex_unlock(&ts->io_lock); + return; + } + + ts->mode_enabled = false; + g6ts_release_inputs(ts); + path = ts->recovery_path; + ret = g6ts_full_reinitialize_locked(ts, path); + if (!ret) { + ts->recovery_fail_streak = 0; + ts->recovery_successes++; + if (path == G6TS_RECOVERY_HARDWARE) + ts->rapid_reset_streak = 0; + ts->recovery_path = G6TS_RECOVERY_HARDWARE; + if (ts->parity_feedback_required || + ts->parity_config_owner_required || + ts->parity_cfu_owner_required || + ts->parity_cfu_branch_required || + ts->parity_heat_owner_required) + dev_info(&ts->spi->dev, + "Windows parity attach paused at %s; touch input intentionally disabled\n", + g6ts_initialization_stage_name(ts->initialization_stage)); + else + dev_info(&ts->spi->dev, + "touch controller initialized path=%s recoveries=%llu resets=%llu\n", + path == G6TS_RECOVERY_SOFTWARE ? + "software" : "hardware", + ts->recovery_successes, + ts->reset_notifications); + } else { + ts->recovery_failures++; + ts->recovery_fail_streak++; + if (path == G6TS_RECOVERY_SOFTWARE && + !ts->fatal_transport_error) { + ts->software_recovery_fallbacks++; + ts->recovery_path = G6TS_RECOVERY_HARDWARE; + retry = true; + } else { + retry = !ts->fatal_transport_error && + ts->recovery_fail_streak < G6TS_RECOVERY_LIMIT; + } + dev_warn(&ts->spi->dev, + "touch controller initialization failed path=%s stage=%s ret=%d failures=%llu%s\n", + path == G6TS_RECOVERY_SOFTWARE ? "software" : "hardware", + g6ts_initialization_stage_name(ts->initialization_stage), + ret, ts->recovery_failures, + retry ? "; retrying" : ""); + } + mutex_unlock(&ts->io_lock); + if (!ret && READ_ONCE(ts->mode_enabled)) + g6ts_ipts_irq_enable_runtime(ts); + if (!ret && READ_ONCE(ts->mode_enabled) && !g6ts_is_quiescing(ts)) { + mod_delayed_work(system_wq, &ts->hid_rebind_work, + msecs_to_jiffies(G6TS_HID_REBIND_STABLE_MS)); + } else { + mod_delayed_work(system_wq, &ts->hid_rebind_work, 0); + } + + if (retry && !g6ts_is_quiescing(ts)) + schedule_delayed_work(&ts->recovery_work, + msecs_to_jiffies(G6TS_RECOVERY_RETRY_MS)); +} + +static int g6ts_probe(struct spi_device *spi) +{ + struct g6ts *ts; + unsigned long irq_flags; + int ret; + + if (g6ts_behavior_v2 && g6ts_windows_orchestrator) + return dev_err_probe(&spi->dev, -EINVAL, + "behavior_v2 and windows_orchestrator are mutually exclusive\n"); + if (g6ts_ipts_minimal_init && !g6ts_ipts_hid_bridge) + return dev_err_probe(&spi->dev, -EINVAL, + "ipts_minimal_init requires ipts_hid_bridge\n"); + if (g6ts_ipts_minimal_init && g6ts_windows_init_parity) + return dev_err_probe(&spi->dev, -EINVAL, + "ipts_minimal_init and windows_init_parity are mutually exclusive\n"); + if (g6ts_ipts_irq_cadence && !g6ts_ipts_minimal_init) + return dev_err_probe(&spi->dev, -EINVAL, + "ipts_irq_cadence requires ipts_minimal_init\n"); + if (g6ts_ipts_irq_cadence && !g6ts_host_fault_recovery) + return dev_err_probe(&spi->dev, -EINVAL, + "ipts_irq_cadence requires host_fault_recovery\n"); + if (g6ts_ipts_irq_cadence && !g6ts_ready_quiesce) + return dev_err_probe(&spi->dev, -EINVAL, + "ipts_irq_cadence requires ready_quiesce\n"); + if (g6ts_reset_storm_breaker && !g6ts_reset_recovery_v2) + return dev_err_probe(&spi->dev, -EINVAL, + "reset_storm_breaker requires reset_recovery_v2\n"); + if (g6ts_ready_quiesce && !g6ts_host_fault_recovery) + return dev_err_probe(&spi->dev, -EINVAL, + "ready_quiesce requires host_fault_recovery\n"); + if (g6ts_parity_heat_input && + (!g6ts_windows_init_parity || !g6ts_parity_cfu_inventory)) + return dev_err_probe(&spi->dev, -EINVAL, + "parity_heat_input requires windows_init_parity and parity_cfu_inventory\n"); + if (g6ts_windows_read_cadence && !g6ts_windows_init_parity) + return dev_err_probe(&spi->dev, -EINVAL, + "windows_read_cadence requires windows_init_parity\n"); + + ts = devm_kzalloc(&spi->dev, sizeof(*ts), GFP_KERNEL); + if (!ts) + return -ENOMEM; + ts->body = devm_kmalloc(&spi->dev, G6TS_MAX_BODY, GFP_KERNEL); + if (!ts->body) + return -ENOMEM; + ts->spi = spi; + /* + * Initial attach A5 carries sequence zero. Streaming starts at one and + * deliberately survives transport boundaries until evidence says otherwise. + */ + ts->a5.sequence = 1; + if (g6ts_parity_fast_host_id >= 0 && + g6ts_parity_fast_host_id <= U16_MAX) { + ts->a5.fast_host_id = g6ts_parity_fast_host_id; + ts->a5.fast_host_id_valid = true; + } + ts->interrupt_gpio = devm_gpiod_get(&spi->dev, "interrupt", GPIOD_IN); + if (IS_ERR(ts->interrupt_gpio)) + return dev_err_probe(&spi->dev, PTR_ERR(ts->interrupt_gpio), + "failed to get interrupt GPIO\n"); + ts->interrupt_irq = gpiod_to_irq(ts->interrupt_gpio); + if (ts->interrupt_irq < 0) + return dev_err_probe(&spi->dev, ts->interrupt_irq, + "failed to map interrupt GPIO\n"); + ts->power_gpio = + devm_gpiod_get_optional(&spi->dev, "power", GPIOD_OUT_LOW); + if (IS_ERR(ts->power_gpio)) + return dev_err_probe(&spi->dev, PTR_ERR(ts->power_gpio), + "failed to get power GPIO\n"); + ts->reset_gpio = + devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ts->reset_gpio)) + return dev_err_probe(&spi->dev, PTR_ERR(ts->reset_gpio), + "failed to get reset GPIO\n"); + if (!!ts->power_gpio != !!ts->reset_gpio) + return dev_err_probe(&spi->dev, -EINVAL, + "power and reset GPIOs must be paired\n"); + + mutex_init(&ts->io_lock); + mutex_init(&ts->irq_state_lock); + INIT_DELAYED_WORK(&ts->recovery_work, g6ts_recovery_work); + INIT_DELAYED_WORK(&ts->hid_rebind_work, + g6ts_ipts_hid_rebind_work); + ts->hid_target_generation = 1; + spi_set_drvdata(spi, ts); + ret = g6ts_heat_register(ts); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to register raw Heat device\n"); + irq_flags = IRQF_ONESHOT | + (g6ts_ipts_irq_cadence ? + IRQF_TRIGGER_LOW | IRQF_NO_AUTOEN : IRQF_TRIGGER_FALLING); + ret = devm_request_threaded_irq(&spi->dev, ts->interrupt_irq, + g6ts_interrupt_edge, + g6ts_interrupt_thread, + irq_flags, + G6TS_NAME, ts); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to request interrupt\n"); + ts->irq_enabled = !g6ts_ipts_irq_cadence; + ret = devm_device_add_group(&spi->dev, &g6ts_attribute_group); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to create diagnostic attributes\n"); + spi->max_speed_hz = G6TS_SPI_HZ; + spi->bits_per_word = 8; + spi->mode = SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD; + ret = spi_setup(spi); + if (ret) + return dev_err_probe(&spi->dev, ret, "spi_setup failed\n"); + + ts->input = devm_input_allocate_device(&spi->dev); + if (!ts->input) + return -ENOMEM; + ts->input->name = "Microsoft Surface G6 Touch"; + ts->input->id.bustype = BUS_SPI; + ts->input->dev.parent = &spi->dev; + input_set_abs_params(ts->input, ABS_MT_POSITION_X, 0, + G6TS_LOGICAL_MAX, 0, 0); + input_set_abs_params(ts->input, ABS_MT_POSITION_Y, 0, + G6TS_LOGICAL_MAX, 0, 0); + touchscreen_parse_properties(ts->input, true, &ts->prop); + ret = input_mt_init_slots(ts->input, G6TS_MAX_CONTACTS, + INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED | + INPUT_MT_TRACK); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to initialize touch slots\n"); + ret = input_register_device(ts->input); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to register touch input\n"); + + ts->pen_input = devm_input_allocate_device(&spi->dev); + if (!ts->pen_input) + return -ENOMEM; + ts->pen_input->name = "Microsoft Surface G6 Pen"; + ts->pen_input->id.bustype = BUS_SPI; + ts->pen_input->dev.parent = &spi->dev; + input_set_capability(ts->pen_input, EV_KEY, BTN_TOUCH); + input_set_capability(ts->pen_input, EV_KEY, BTN_TOOL_PEN); + input_set_capability(ts->pen_input, EV_KEY, BTN_TOOL_RUBBER); + input_set_capability(ts->pen_input, EV_KEY, BTN_STYLUS); + input_set_abs_params(ts->pen_input, ABS_X, 0, G6TS_PEN_X_MAX, 0, 0); + input_set_abs_params(ts->pen_input, ABS_Y, 0, G6TS_PEN_Y_MAX, 0, 0); + input_set_abs_params(ts->pen_input, ABS_PRESSURE, 0, + G6TS_PEN_PRESSURE_MAX, 0, 0); + input_set_abs_params(ts->pen_input, ABS_TILT_X, + -G6TS_PEN_TILT_CENTER, G6TS_PEN_TILT_CENTER, 0, 0); + input_set_abs_params(ts->pen_input, ABS_TILT_Y, + -G6TS_PEN_TILT_CENTER, G6TS_PEN_TILT_CENTER, 0, 0); + touchscreen_parse_properties(ts->pen_input, false, &ts->pen_prop); + input_abs_set_res(ts->pen_input, ABS_X, ts->pen_prop.swap_x_y ? + G6TS_PEN_Y_RESOLUTION : G6TS_PEN_X_RESOLUTION); + input_abs_set_res(ts->pen_input, ABS_Y, ts->pen_prop.swap_x_y ? + G6TS_PEN_X_RESOLUTION : G6TS_PEN_Y_RESOLUTION); + input_abs_set_res(ts->pen_input, ABS_TILT_X, + G6TS_PEN_TILT_RESOLUTION); + input_abs_set_res(ts->pen_input, ABS_TILT_Y, + G6TS_PEN_TILT_RESOLUTION); + __set_bit(INPUT_PROP_DIRECT, ts->pen_input->propbit); + ret = input_register_device(ts->pen_input); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to register pen input\n"); + + ret = g6ts_power_on(ts); + if (ret) + return ret; + + g6ts_clear_last_response(ts); + ts->recovery_path = G6TS_RECOVERY_HARDWARE; + schedule_delayed_work(&ts->recovery_work, + msecs_to_jiffies(G6TS_RECOVERY_DELAY_MS)); + dev_info(&spi->dev, "touch controller initialization scheduled profile=%s\n", + g6ts_profile_name()); + return 0; +} + +static void g6ts_remove(struct spi_device *spi) +{ + struct g6ts *ts = spi_get_drvdata(spi); + struct hid_device *hid; + + WRITE_ONCE(ts->stopping, true); + WRITE_ONCE(ts->quiescing, true); + WRITE_ONCE(ts->mode_enabled, false); + if (g6ts_ipts_irq_cadence) + g6ts_ipts_irq_disable_sync(ts); + else + disable_irq(ts->interrupt_irq); + cancel_delayed_work_sync(&ts->recovery_work); + cancel_delayed_work_sync(&ts->hid_rebind_work); + mutex_lock(&ts->io_lock); + hid = g6ts_ipts_hid_detach_locked(ts); + g6ts_release_inputs(ts); + mutex_unlock(&ts->io_lock); + /* Drain generation work queued by an in-flight transport caller. */ + cancel_delayed_work_sync(&ts->hid_rebind_work); + if (hid) + hid_destroy_device(hid); + (void)g6ts_power_off(ts); +} + +static int g6ts_suspend(struct device *dev) +{ + struct g6ts *ts = dev_get_drvdata(dev); + struct hid_device *hid; + int ret; + + WRITE_ONCE(ts->quiescing, true); + WRITE_ONCE(ts->mode_enabled, false); + if (g6ts_ipts_irq_cadence) + g6ts_ipts_irq_disable_sync(ts); + else + disable_irq(ts->interrupt_irq); + cancel_delayed_work_sync(&ts->recovery_work); + cancel_delayed_work_sync(&ts->hid_rebind_work); + + mutex_lock(&ts->io_lock); + WRITE_ONCE(ts->mode_enabled, false); + g6ts_heat_generation_boundary(ts, + G6TS_HEAT_RECORD_F_SUSPEND); + hid = g6ts_ipts_hid_detach_locked(ts); + g6ts_release_inputs(ts); + mutex_unlock(&ts->io_lock); + /* The generation boundary queued a teardown pass; the child is detached. */ + cancel_delayed_work_sync(&ts->hid_rebind_work); + if (hid) + hid_destroy_device(hid); + + mutex_lock(&ts->io_lock); + ret = g6ts_power_off(ts); + if (ret) { + WRITE_ONCE(ts->quiescing, false); + ts->recovery_path = G6TS_RECOVERY_HARDWARE; + } + mutex_unlock(&ts->io_lock); + + if (ret) { + if (!g6ts_ipts_irq_cadence) + enable_irq(ts->interrupt_irq); + schedule_delayed_work(&ts->recovery_work, + msecs_to_jiffies(G6TS_RECOVERY_DELAY_MS)); + } + + return ret; +} + +static int g6ts_resume(struct device *dev) +{ + struct g6ts *ts = dev_get_drvdata(dev); + int ret; + + mutex_lock(&ts->io_lock); + ts->fatal_transport_error = false; + ts->recovery_fail_streak = 0; + ts->recovery_path = G6TS_RECOVERY_HARDWARE; + ret = g6ts_power_on(ts); + if (!ret) + WRITE_ONCE(ts->quiescing, false); + mutex_unlock(&ts->io_lock); + if (ret) + return ret; + + if (!g6ts_ipts_irq_cadence) + enable_irq(ts->interrupt_irq); + schedule_delayed_work(&ts->recovery_work, + msecs_to_jiffies(G6TS_RECOVERY_DELAY_MS)); + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(g6ts_pm_ops, g6ts_suspend, g6ts_resume); + +static int g6ts_ipts_hid_probe(struct hid_device *hid, + const struct hid_device_id *id) +{ + int ret; + + ret = hid_parse(hid); + if (ret) + return ret; + + return hid_hw_start(hid, HID_CONNECT_HIDRAW); +} + +static void g6ts_ipts_hid_remove(struct hid_device *hid) +{ + hid_hw_stop(hid); +} + +static const struct hid_device_id g6ts_ipts_hid_ids[] = { + { HID_DEVICE(BUS_SPI, HID_GROUP_MSHW0485_IPTS, + G6TS_SP11_VENDOR_ID, G6TS_SP11_X1E_PRODUCT_ID) }, + { HID_DEVICE(BUS_SPI, HID_GROUP_MSHW0485_IPTS, + G6TS_SP11_VENDOR_ID, G6TS_SP11_X1P_PRODUCT_ID) }, + { } +}; +MODULE_DEVICE_TABLE(hid, g6ts_ipts_hid_ids); + +static struct hid_driver g6ts_ipts_hid_driver = { + .name = "mshw0485-ipts", + .id_table = g6ts_ipts_hid_ids, + .probe = g6ts_ipts_hid_probe, + .remove = g6ts_ipts_hid_remove, +}; + +static const struct acpi_device_id g6ts_acpi_match[] = { + { "MSHW0485", 0 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, g6ts_acpi_match); + +static const struct of_device_id g6ts_of_match[] = { + { .compatible = "microsoft,mshw0485" }, + { } +}; +MODULE_DEVICE_TABLE(of, g6ts_of_match); + +static const struct spi_device_id g6ts_spi_id[] = { + { "mshw0485" }, + { } +}; +MODULE_DEVICE_TABLE(spi, g6ts_spi_id); + +static struct spi_driver g6ts_driver = { + .driver = { + .name = G6TS_NAME, + .acpi_match_table = ACPI_PTR(g6ts_acpi_match), + .of_match_table = g6ts_of_match, + .pm = pm_sleep_ptr(&g6ts_pm_ops), + }, + .id_table = g6ts_spi_id, + .probe = g6ts_probe, + .remove = g6ts_remove, +}; + +static int __init g6ts_init(void) +{ + int ret; + + ret = hid_register_driver(&g6ts_ipts_hid_driver); + if (ret) + return ret; + + ret = spi_register_driver(&g6ts_driver); + if (ret) + hid_unregister_driver(&g6ts_ipts_hid_driver); + + return ret; +} +module_init(g6ts_init); + +static void __exit g6ts_exit(void) +{ + /* Destroy every child HID device before its special driver disappears. */ + spi_unregister_driver(&g6ts_driver); + hid_unregister_driver(&g6ts_ipts_hid_driver); +} +module_exit(g6ts_exit); + +MODULE_DESCRIPTION("Microsoft Surface G6 MSHW0485 touch and IPTS pen bridge"); +MODULE_AUTHOR("SP11 reverse-engineering project"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 849d06dfe1aecf..6a778fb21b97c9 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -37,6 +37,14 @@ #define IS_GFX_DEVICE(pdev) pci_is_display(pdev) #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB) #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) +#define IS_INTEL_IPU(pdev) ((pdev)->vendor == PCI_VENDOR_ID_INTEL && \ + ((pdev)->device == 0xa75d || \ + (pdev)->device == 0x9a19 || \ + (pdev)->device == 0x9a39 || \ + (pdev)->device == 0x7d19 || \ + (pdev)->device == 0x4e19 || \ + (pdev)->device == 0x465d || \ + (pdev)->device == 0x1919)) #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) #define IOAPIC_RANGE_START (0xfee00000) @@ -205,12 +213,14 @@ int intel_iommu_sm = IS_ENABLED(CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON); int intel_iommu_enabled = 0; EXPORT_SYMBOL_GPL(intel_iommu_enabled); +static int dmar_map_ipu = 1; static int intel_iommu_superpage = 1; static int iommu_identity_mapping; static int iommu_skip_te_disable; static int disable_igfx_iommu; #define IDENTMAP_AZALIA 4 +#define IDENTMAP_IPU 8 const struct iommu_ops intel_iommu_ops; @@ -1401,6 +1411,9 @@ static int device_def_domain_type(struct device *dev) if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) return IOMMU_DOMAIN_IDENTITY; + + if ((iommu_identity_mapping & IDENTMAP_IPU) && IS_INTEL_IPU(pdev)) + return IOMMU_DOMAIN_IDENTITY; } return 0; @@ -1691,6 +1704,9 @@ static int __init init_dmars(void) iommu_set_root_entry(iommu); } + if (!dmar_map_ipu) + iommu_identity_mapping |= IDENTMAP_IPU; + check_tylersburg_isoch(); /* @@ -3942,6 +3958,17 @@ static void quirk_iommu_igfx(struct pci_dev *dev) disable_igfx_iommu = 1; } +static void quirk_iommu_ipu(struct pci_dev *dev) +{ + if (!IS_INTEL_IPU(dev)) + return; + + if (risky_device(dev)) + return; + + pci_info(dev, "Passthrough IOMMU for integrated Intel IPU\n"); + dmar_map_ipu = 0; +} /* Q35 integrated gfx dmar support is totally busted. */ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x29b2, quirk_iommu_igfx); @@ -3983,6 +4010,77 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163A, quirk_iommu_igfx); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx); +/* SKL */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1906, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1913, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x190E, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1915, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1902, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x190A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x190B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1917, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1916, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1921, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x191E, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1912, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x191A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x191B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x191D, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1923, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1926, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1927, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x192A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x192B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x192D, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1932, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x193A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x193B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x193D, quirk_iommu_igfx); + +/* KBL */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5902, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5906, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5908, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x590A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x590B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x590E, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5912, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5913, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5915, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5916, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5917, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x591A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x591B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x591D, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x591E, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5921, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5923, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5926, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5927, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x593B, quirk_iommu_igfx); + +/* CML */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9B21, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BA2, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BA4, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BA5, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BA8, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BAA, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BAC, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BC2, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BC4, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BC5, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BC6, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BC8, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BE6, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BF6, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9B41, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BCA, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BCC, quirk_iommu_igfx); + +/* disable IPU dmar support */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_iommu_ipu); + static void quirk_iommu_rwbf(struct pci_dev *dev) { if (risky_device(dev)) diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index f4a0a3c8c8705e..22748404a7f061 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -72,6 +72,18 @@ config LEDS_88PM860X This option enables support for on-chip LED drivers found on Marvell Semiconductor 88PM8606 PMIC. +config LEDS_AAEON + tristate "AAEON LED driver" + depends on X86 + depends on UBUNTU_ODM_DRIVERS + select MFD_AAEON + help + This led driver adds support for LED brightness control on Single + Board Computers produced by AAEON. + + This driver leverages the ASUS WMI interface to access device + resources. + config LEDS_AN30259A tristate "LED support for Panasonic AN30259A" depends on LEDS_CLASS && I2C && OF diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 7db3768912ca5f..1e509604ecaacb 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_LEDS_KUNIT_TEST) += led-test.o # LED Platform Drivers (keep this sorted, M-| sort) obj-$(CONFIG_LEDS_88PM860X) += leds-88pm860x.o +obj-$(CONFIG_LEDS_AAEON) += leds-aaeon.o obj-$(CONFIG_LEDS_ACER_A500) += leds-acer-a500.o obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o obj-$(CONFIG_LEDS_AN30259A) += leds-an30259a.o diff --git a/drivers/leds/leds-aaeon.c b/drivers/leds/leds-aaeon.c new file mode 100644 index 00000000000000..4034dfaba9eab0 --- /dev/null +++ b/drivers/leds/leds-aaeon.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AAEON LED driver + * + * Copyright (c) 2021, AAEON Ltd. + * + * Author: Kunyang Fan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include + +#define DRVNAME "led_aaeon" +#define ASUS_NB_WMI_EVENT_GUID "0B3CBB35-E3C2-45ED-91C2-4C5A6D195D1C" +#define AAEON_WMI_MGMT_GUID "97845ED0-4E6D-11DE-8A39-0800200C9A66" + +#define GET_LED_NUMBER_ID 0x00060000 +#define GET_LED_METHOD_ID 0x00060001 +#define SET_LED_METHOD_ID 0x00060002 +#define GET_LED_NUMBER_METHOD_ID 0x10 + + +struct aaeon_led_data { + int id; + struct led_classdev cdev; +}; + +static int aaeon_led_get_number(void) +{ + int err, retval; + + err = asus_wmi_evaluate_method(GET_LED_NUMBER_ID, + GET_LED_NUMBER_METHOD_ID, + 0, &retval); + if (err) + return err; + + return retval; +} + +static enum led_brightness aaeon_led_brightness_get(struct led_classdev + *cdev) +{ + int err, brightness; + struct aaeon_led_data *led = + container_of(cdev, struct aaeon_led_data, cdev); + u32 arg0; + + arg0 = (u32)(led->id & 0xF); + err = asus_wmi_evaluate_method(GET_LED_METHOD_ID, arg0, 0, &brightness); + if (err) + return err; + + return brightness; +}; + +static void aaeon_led_brightness_set(struct led_classdev *cdev, + enum led_brightness brightness) +{ + int err, retval; + struct aaeon_led_data *led = + container_of(cdev, struct aaeon_led_data, cdev); + u32 arg0; + + arg0 = (u32)(led->id & 0xF); + if (brightness != LED_OFF) + arg0 |= BIT(16); + + err = asus_wmi_evaluate_method(SET_LED_METHOD_ID, arg0, 0, &retval); +}; + +static int __init aaeon_add_led_device(struct platform_device *pdev, + int id) +{ + struct aaeon_led_data *led; + + led = devm_kzalloc(&pdev->dev, sizeof(struct aaeon_led_data), GFP_KERNEL); + if (!led) + return -ENOMEM; + + led->id = id; + led->cdev.brightness_get = aaeon_led_brightness_get; + led->cdev.brightness_set = aaeon_led_brightness_set; + led->cdev.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "led:%d:", id); + + if (!led->cdev.name) + return -ENOMEM; + + return devm_led_classdev_register(&pdev->dev, &led->cdev); +} + +static int aaeon_led_probe(struct platform_device *pdev) +{ + int err = -ENODEV, i; + int led_number = 0; + + pr_debug("aaeon led device probe!\n"); + /* Prevent other drivers adding this platfom device */ + if (!wmi_has_guid(AAEON_WMI_MGMT_GUID)) { + pr_debug("AAEON Management GUID not found\n"); + return -ENODEV; + } + + /* Query the number of led devices board support */ + led_number = aaeon_led_get_number(); + + /* + * If the number is 0 or can't get the number of leds, + * no need to register any led device node. + */ + if (led_number <= 0) + return -ENODEV; + + for (i = 0; i < led_number; i++) { + err = aaeon_add_led_device(pdev, i); + if (err) + break; + } + + return err; +} + +static struct platform_driver aaeon_led_driver = { + .driver = { + .name = "leds-aaeon", + }, +}; + +module_platform_driver_probe(aaeon_led_driver, aaeon_led_probe); + +MODULE_ALIAS("platform:leds-aaeon"); +MODULE_DESCRIPTION("AAEON LED Driver"); +MODULE_AUTHOR("Kunyang Fan "); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("ASUS_WMI"); diff --git a/drivers/md/raid0.c b/drivers/md/raid0.c index 2c000b3a5f4910..00ffba2dabb834 100644 --- a/drivers/md/raid0.c +++ b/drivers/md/raid0.c @@ -268,11 +268,12 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf) default_layout == RAID0_ALT_MULTIZONE_LAYOUT) { conf->layout = default_layout; } else { - pr_err("md/raid0:%s: cannot assemble multi-zone RAID0 with default_layout setting\n", - mdname(mddev)); - pr_err("md/raid0: please set raid0.default_layout to 1 or 2\n"); - err = -EOPNOTSUPP; - goto abort; + conf->layout = RAID0_ALT_MULTIZONE_LAYOUT; + pr_warn("md/raid0:%s: !!! DEFAULTING TO ALTERNATE LAYOUT !!!\n", + mdname(mddev)); + pr_warn("md/raid0: Please set raid0.default_layout to 1 or 2\n"); + pr_warn("md/raid0: Read the following page for more information:\n"); + pr_warn("md/raid0: https://wiki.ubuntu.com/Kernel/Raid0LayoutMigration\n"); } if (conf->layout == RAID0_ORIG_LAYOUT) { diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 5d173e0ecf424f..40c6eafad5cc7e 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -287,6 +287,18 @@ config VIDEO_IMX415 To compile this driver as a module, choose M here: the module will be called imx415. +config VIDEO_IMX681 + tristate "Sony IMX681 sensor support" + depends on OF_GPIO + select V4L2_CCI_I2C + help + This is a Video4Linux2 sensor driver for the Sony IMX681 camera. + It currently supports the 3840x2640 RAW10 C-PHY mode used by the + front-facing camera in the Microsoft Surface Pro 11. + + To compile this driver as a module, choose M here: the + module will be called imx681. + config VIDEO_MAX9271_LIB tristate diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index e45359efe0e41e..2c8605c580876e 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_VIDEO_IMX335) += imx335.o obj-$(CONFIG_VIDEO_IMX355) += imx355.o obj-$(CONFIG_VIDEO_IMX412) += imx412.o obj-$(CONFIG_VIDEO_IMX415) += imx415.o +obj-$(CONFIG_VIDEO_IMX681) += imx681.o obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o obj-$(CONFIG_VIDEO_ISL7998X) += isl7998x.o obj-$(CONFIG_VIDEO_KS0127) += ks0127.o diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 8e25f970fd12c3..d285421d3d4262 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,18 @@ #include #include "ccs.h" +#include "ccs-imx681-init.h" +#include "ccs-imx681-mode.h" +#include "ccs-imx681-vendor.h" + +/* + * Bring-up aid: bit 0 skips lane-mode register 0x0114, bit 1 skips PLL + * registers 0x0300..0x030f, and bit 2 skips the 361-row vendor table. + */ +static unsigned int imx681_mode_skip; +module_param(imx681_mode_skip, uint, 0444); +MODULE_PARM_DESC(imx681_mode_skip, + "Load-time bring-up: IMX681 skip mask, bit0 lane, bit1 PLL, bit2 vendor"); #define CCS_ALIGN_DIM(dim, flags) \ ((flags) & V4L2_SEL_FLAG_GE \ @@ -61,6 +74,37 @@ static const struct ccs_module_ident ccs_module_idents[] = { CCS_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk), }; +struct ccs_sensor_ident { + u16 manufacturer_id; + u16 model_id; + u16 revision; + char *name; + const struct ccs_quirk *quirk; +}; + +#define CCS_IMX681_IDENT(_manufacturer_id) { \ + .manufacturer_id = (_manufacturer_id), \ + .model_id = CCS_IMX681_MODEL_ID, \ + .revision = CCS_IMX681_REVISION, \ + .name = "imx681", \ + .quirk = &ccs_imx681_quirk, \ +} + +static const struct ccs_sensor_ident ccs_sensor_idents[] = { + CCS_IMX681_IDENT(CCS_IMX681_MFR_ID), + CCS_IMX681_IDENT(CCS_IMX681_SP11_MFR_ID), +}; + +static const struct ccs_imx681_mode * +ccs_imx681_current_mode(const struct ccs_sensor *sensor) +{ + if (!ccs_is_imx681(sensor)) + return NULL; + + /* The 3844x2640 mode is the only mode validated on the SP11 C-PHY. */ + return &imx681_mode; +} + #define CCS_DEVICE_FLAG_IS_SMIA BIT(0) struct ccs_device { @@ -597,11 +641,136 @@ static int ccs_pll_update(struct ccs_sensor *sensor) * */ +#define IMX681_EXPOSURE_MIN_TICKS 5000U +#define IMX681_EXPOSURE_MAX_TICKS 2000000U +#define IMX681_EXPOSURE_STEP_TICKS 10U + +static int ccs_imx681_group_write(struct ccs_sensor *sensor, + const struct ccs_reg_8 *regs, + unsigned int num_regs) +{ + struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); + int release_ret; + int ret; + unsigned int i; + + if (!ccs_is_imx681(sensor)) + return -EINVAL; + + ret = ccs_write_addr(sensor, CCI_REG8(0x0104), 1); + if (ret) + return ret; + + for (i = 0; i < num_regs; i++) { + ret = ccs_write_addr(sensor, CCI_REG8(regs[i].reg), regs[i].val); + if (ret) + break; + } + + release_ret = ccs_write_addr(sensor, CCI_REG8(0x0104), 0); + if (release_ret) { + dev_dbg(&client->dev, "IMX681 group hold release failed: %d\n", + release_ret); + if (!ret) + ret = release_ret; + } + + return ret; +} + +static int ccs_imx681_set_exposure(struct ccs_sensor *sensor, u32 exposure) +{ + /* 0x0229 is a 24-bit line count; control bounds are converted to lines. */ + const struct ccs_reg_8 regs[] = { + { 0x0229, (exposure >> 16) & 0xff }, + { 0x022a, (exposure >> 8) & 0xff }, + { 0x022b, exposure & 0xff }, + }; + + return ccs_imx681_group_write(sensor, regs, ARRAY_SIZE(regs)); +} + +static int ccs_imx681_set_digital_gain(struct ccs_sensor *sensor, s32 value) +{ + u16 code = 0x0100 + clamp(value, 0, 960) * 4; + const struct ccs_reg_8 regs[] = { + { 0x020e, code >> 8 }, + { 0x020f, code & 0xff }, + }; + + return ccs_imx681_group_write(sensor, regs, ARRAY_SIZE(regs)); +} + +static int ccs_imx681_set_startup_controls(struct ccs_sensor *sensor, + const struct ccs_imx681_mode *mode) +{ + u32 exposure = sensor->exposure->val; + u16 gain = 0x0100 + clamp(sensor->analogue_gain->val, 0, 960) * 4; + const struct ccs_reg_8 regs[] = { + /* Keep timing and the first exposure coherent when streaming starts. */ + { 0x033d, (mode->frame_length_lines >> 16) & 0xff }, + { 0x033e, (mode->frame_length_lines >> 8) & 0xff }, + { 0x033f, mode->frame_length_lines & 0xff }, + { 0x0229, (exposure >> 16) & 0xff }, + { 0x022a, (exposure >> 8) & 0xff }, + { 0x022b, exposure & 0xff }, + /* Keep the analogue code at the reference sequence's zero value. */ + { 0x0204, 0x00 }, + { 0x0205, 0x00 }, + { 0x020e, gain >> 8 }, + { 0x020f, gain & 0xff }, + }; + + return ccs_imx681_group_write(sensor, regs, ARRAY_SIZE(regs)); +} + +static u32 ccs_imx681_ticks_to_lines(const struct ccs_imx681_mode *mode, + u32 ticks) +{ + return DIV64_U64_ROUND_CLOSEST((u64)ticks * mode->pixel_rate, + 10000000ULL * mode->line_length_pck); +} + +static void ccs_imx681_exposure_range(struct ccs_sensor *sensor, int *min, + int *max, int *step, int *def) +{ + const struct ccs_imx681_mode *mode = ccs_imx681_current_mode(sensor); + u32 margin = max(CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN), + 1U); + u32 mode_max = mode->frame_length_lines > margin ? + mode->frame_length_lines - margin : 1; + u32 min_lines; + u32 max_lines; + u32 step_lines; + u32 default_lines; + + /* + * Windows exposes 100 ns ticks: 5000..2000000, step 10, default + * 5000, with auto exposure enabled. Auto exposure remains userspace + * policy; this control reports the converted manual line bounds. + */ + min_lines = ccs_imx681_ticks_to_lines(mode, IMX681_EXPOSURE_MIN_TICKS); + max_lines = ccs_imx681_ticks_to_lines(mode, IMX681_EXPOSURE_MAX_TICKS); + step_lines = ccs_imx681_ticks_to_lines(mode, IMX681_EXPOSURE_STEP_TICKS); + default_lines = mode->exposure_default; + + *min = clamp_t(u32, min_lines, 1, mode_max); + *max = clamp_t(u32, max_lines, *min, mode_max); + *step = max_t(u32, step_lines, 1); + *def = clamp_t(u32, default_lines, *min, *max); +} + static void __ccs_update_exposure_limits(struct ccs_sensor *sensor, const struct v4l2_rect *pa_src) { struct v4l2_ctrl *ctrl = sensor->exposure; - int max; + int min, max, step, def; + + if (ccs_is_imx681(sensor)) { + ccs_imx681_exposure_range(sensor, &min, &max, &step, &def); + __v4l2_ctrl_modify_range(ctrl, min, max, step, def); + return; + } max = pa_src->height + sensor->vblank->val - CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN); @@ -650,18 +819,23 @@ static const char *pixel_order_str[] = { "GRBG", "RGGB", "BGGR", "GBRG" }; - (unsigned long)ccs_csi_data_formats) \ / sizeof(*ccs_csi_data_formats)) -static u32 ccs_pixel_order(struct ccs_sensor *sensor) +static u8 ccs_image_orientation(struct ccs_sensor *sensor) { - struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); - int flip = 0; + u8 orient = 0; - if (sensor->hflip) { - if (sensor->hflip->val) - flip |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR; + if (sensor->hflip && sensor->hflip->val) + orient |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR; - if (sensor->vflip->val) - flip |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP; - } + if (sensor->vflip && sensor->vflip->val) + orient |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP; + + return orient; +} + +static u32 ccs_pixel_order(struct ccs_sensor *sensor) +{ + struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); + u8 flip = ccs_image_orientation(sensor); dev_dbg(&client->dev, "flip %u\n", flip); return sensor->default_pixel_order ^ flip; @@ -709,7 +883,6 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) struct v4l2_subdev_state *state; const struct v4l2_rect *pa_src = NULL; int pm_status; - u32 orient = 0; unsigned int i; int exposure; int rval; @@ -726,12 +899,6 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) if (sensor->streaming) return -EBUSY; - if (sensor->hflip->val) - orient |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR; - - if (sensor->vflip->val) - orient |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP; - ccs_update_mbus_formats(sensor); break; @@ -773,7 +940,16 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) switch (ctrl->id) { case V4L2_CID_ANALOGUE_GAIN: - rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val); + /* + * The analogue gain register does not affect the Snapdragon IMX681, + * while its global U8.8 digital gain does. Keep the standard + * analogue-gain control that libcamera's simple IPA drives, but map + * it to the effective register on this model. + */ + if (ccs_is_imx681(sensor)) + rval = ccs_imx681_set_digital_gain(sensor, ctrl->val); + else + rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val); break; @@ -820,12 +996,17 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) break; case V4L2_CID_EXPOSURE: - rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val); + if (ccs_is_imx681(sensor)) + rval = ccs_imx681_set_exposure(sensor, ctrl->val); + else + rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, + ctrl->val); break; case V4L2_CID_HFLIP: case V4L2_CID_VFLIP: - rval = ccs_write(sensor, IMAGE_ORIENTATION, orient); + rval = ccs_write(sensor, IMAGE_ORIENTATION, + ccs_image_orientation(sensor)); break; case V4L2_CID_VBLANK: @@ -894,6 +1075,8 @@ static int ccs_init_controls(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); struct v4l2_fwnode_device_properties props; + int exposure_min = 0, exposure_max = 0; + int exposure_step = 1, exposure_def = 0; int rval; rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 19); @@ -911,6 +1094,17 @@ static int ccs_init_controls(struct ccs_sensor *sensor) if (rval) return rval; + if (ccs_is_imx681(sensor)) { + const struct ccs_imx681_mode *mode = + ccs_imx681_current_mode(sensor); + + sensor->analogue_gain = + v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, + &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + 0, 960, 1, mode->gain_default); + goto gain_controls_done; + } + switch (CCS_LIM(sensor, ANALOG_GAIN_CAPABILITY)) { case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL: { struct { @@ -945,13 +1139,14 @@ static int ccs_init_controls(struct ccs_sensor *sensor) &ctrl_cfg, NULL); } - v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, - &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, - CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), - CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX), - max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), - 1U), - CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); + sensor->analogue_gain = + v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, + &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), + CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX), + max(CCS_LIM(sensor, + ANALOG_GAIN_CODE_STEP), 1U), + CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); } break; @@ -999,6 +1194,8 @@ static int ccs_init_controls(struct ccs_sensor *sensor) } } +gain_controls_done: + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) & (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING | CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)) { @@ -1032,22 +1229,29 @@ static int ccs_init_controls(struct ccs_sensor *sensor) &ctrl_cfg, NULL); } - if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == - CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL || - CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == - SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL) - v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, - &ccs_ctrl_ops, V4L2_CID_DIGITAL_GAIN, - CCS_LIM(sensor, DIGITAL_GAIN_MIN), - CCS_LIM(sensor, DIGITAL_GAIN_MAX), - max(CCS_LIM(sensor, DIGITAL_GAIN_STEP_SIZE), - 1U), - 0x100); - - /* Exposure limits will be updated soon, use just something here. */ + if (!ccs_is_imx681(sensor) && + (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == + CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL || + CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == + SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL)) + sensor->digital_gain = + v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, + &ccs_ctrl_ops, V4L2_CID_DIGITAL_GAIN, + CCS_LIM(sensor, DIGITAL_GAIN_MIN), + CCS_LIM(sensor, DIGITAL_GAIN_MAX), + max(CCS_LIM(sensor, + DIGITAL_GAIN_STEP_SIZE), 1U), + 0x100); + + if (ccs_is_imx681(sensor)) + ccs_imx681_exposure_range(sensor, &exposure_min, &exposure_max, + &exposure_step, &exposure_def); + + /* Generic exposure limits will be updated after state initialisation. */ sensor->exposure = v4l2_ctrl_new_std( &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, - V4L2_CID_EXPOSURE, 0, 0, 1, 0); + V4L2_CID_EXPOSURE, exposure_min, exposure_max, exposure_step, + exposure_def); sensor->hflip = v4l2_ctrl_new_std( &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, @@ -1056,6 +1260,11 @@ static int ccs_init_controls(struct ccs_sensor *sensor) &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0); + if (sensor->hflip) + sensor->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; + if (sensor->vflip) + sensor->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; + sensor->vblank = v4l2_ctrl_new_std( &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_VBLANK, 0, 1, 1, 0); @@ -1214,6 +1423,16 @@ static int ccs_get_mbus_formats(struct ccs_sensor *sensor) } } + if (ccs_is_imx681(sensor)) { + for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) { + const struct ccs_csi_data_format *f = + &ccs_csi_data_formats[i]; + + if (f->width != 10 || f->compressed != 10) + sensor->default_mbus_frame_fmts &= ~BIT_U64(i); + } + } + /* Figure out which BPP values can be used with which formats. */ pll->binning_horizontal = 1; pll->binning_vertical = 1; @@ -1296,6 +1515,17 @@ static void ccs_update_blanking(struct ccs_sensor *sensor, u16 min_fll, max_fll, min_llp, max_llp, min_lbp; int min, max; u8 binh, binv; + const struct ccs_imx681_mode *mode; + + mode = ccs_imx681_current_mode(sensor); + if (mode) { + min = mode->frame_length_lines - mode->height; + __v4l2_ctrl_modify_range(vblank, min, min, 1, min); + min = mode->line_length_pck - mode->width; + __v4l2_ctrl_modify_range(hblank, min, min, 1, min); + __ccs_update_exposure_limits(sensor, pa_src); + return; + } ccs_get_binning(sensor, NULL, &binh, &binv); @@ -1851,6 +2081,90 @@ static int ccs_pm_get_init(struct ccs_sensor *sensor) return rval; } +static int ccs_imx681_write_regs(struct ccs_sensor *sensor, + const struct ccs_reg_8 *regs, + unsigned int num_regs, bool mode_regs) +{ + unsigned int i; + int ret; + + if (!ccs_is_imx681(sensor)) + return -EINVAL; + + for (i = 0; i < num_regs; i++) { + u16 reg = regs[i].reg; + + if (mode_regs && (imx681_mode_skip & BIT(0)) && reg == 0x0114) + continue; + if (mode_regs && (imx681_mode_skip & BIT(1)) && + reg >= 0x0300 && reg <= 0x030f) + continue; + + ret = ccs_write_addr(sensor, CCI_REG8(reg), regs[i].val); + if (ret) + return ret; + } + + return 0; +} + +static int ccs_imx681_start_streaming(struct ccs_sensor *sensor) +{ + const struct ccs_imx681_mode *mode = ccs_imx681_current_mode(sensor); + struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); + int ret; + + if (!mode) + return -EINVAL; + + if (!(imx681_mode_skip & BIT(2))) { + ret = ccs_imx681_write_regs(sensor, imx681_vendor_init, + ARRAY_SIZE(imx681_vendor_init), false); + if (ret) + return ret; + } + + ret = ccs_imx681_write_regs(sensor, mode->regs, mode->num_regs, true); + if (ret) + return ret; + + /* The fixed mode table resets 0x0101; restore the requested Bayer layout. */ + ret = ccs_write(sensor, IMAGE_ORIENTATION, + ccs_image_orientation(sensor)); + if (ret) + return ret; + + usleep_range(10000, 11000); + + ret = ccs_imx681_set_startup_controls(sensor, mode); + if (ret) + return ret; + + dev_dbg(&client->dev, "IMX681 mode %ux%u, skip mask %#x\n", + mode->width, mode->height, imx681_mode_skip); + + return 0; +} + +static void ccs_imx681_log_stream_state(struct ccs_sensor *sensor, + const char *phase) +{ + struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); + u32 frame_count = 0; + u32 mode_select = 0; + int frame_ret; + int mode_ret; + + mode_ret = ccs_read_addr_noconv(sensor, CCS_R_MODE_SELECT, + &mode_select); + frame_ret = ccs_read_addr_noconv(sensor, CCS_R_FRAME_COUNT, + &frame_count); + + dev_info(&client->dev, + "IMX681 %s: MODE_SELECT ret=%d val=%#04x FRAME_COUNT ret=%d val=%#04x\n", + phase, mode_ret, mode_select, frame_ret, frame_count); +} + static int ccs_enable_streams(struct v4l2_subdev *subdev, struct v4l2_subdev_state *state, u32 pad, u64 streams_mask) @@ -1870,6 +2184,9 @@ static int ccs_enable_streams(struct v4l2_subdev *subdev, u8 binning_mode, binh, binv; int rval; + if (ccs_is_imx681(sensor) && subdev != &sensor->src->sd) + return 0; + if (pad != CCS_PAD_SRC) return -EINVAL; @@ -1999,7 +2316,24 @@ static int ccs_enable_streams(struct v4l2_subdev *subdev, goto err_pm_put; } + if (ccs_is_imx681(sensor)) { + rval = ccs_imx681_start_streaming(sensor); + if (rval) + goto err_pm_put; + + ccs_imx681_log_stream_state(sensor, "pre-streamon"); + } + rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_STREAMING); + if (rval) + goto err_pm_put; + if (ccs_is_imx681(sensor)) { + ccs_imx681_log_stream_state(sensor, "post-streamon"); + + /* One expected frame is about 64 ms; keep this probe nonfatal. */ + usleep_range(100000, 101000); + ccs_imx681_log_stream_state(sensor, "active-100ms"); + } sensor->streaming |= streams_mask; @@ -2019,6 +2353,9 @@ static int ccs_disable_streams(struct v4l2_subdev *subdev, struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; + if (ccs_is_imx681(sensor) && subdev != &sensor->src->sd) + return 0; + if (pad != CCS_PAD_SRC) return -EINVAL; @@ -2026,13 +2363,20 @@ static int ccs_disable_streams(struct v4l2_subdev *subdev, if (sensor->streaming) return 0; + if (ccs_is_imx681(sensor)) + ccs_imx681_log_stream_state(sensor, "pre-streamoff"); + rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_SOFTWARE_STANDBY); - if (rval) - return rval; + if (rval) { + dev_warn(&client->dev, + "failed to enter standby: %d; scheduling power-down\n", + rval); + } else { + int quirk_rval = ccs_call_quirk(sensor, post_streamoff); - rval = ccs_call_quirk(sensor, post_streamoff); - if (rval) - dev_err(&client->dev, "post_streamoff quirks failed\n"); + if (quirk_rval) + dev_err(&client->dev, "post_streamoff quirks failed\n"); + } pm_runtime_put_autosuspend(&client->dev); @@ -2045,6 +2389,9 @@ static int ccs_pre_streamon(struct v4l2_subdev *subdev, u32 flags) struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; + if (ccs_is_imx681(sensor) && subdev != &sensor->src->sd) + return 0; + if (flags & V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP) { switch (sensor->hwcfg.csi_signalling_mode) { case CCS_CSI_SIGNALING_MODE_CSI_2_DPHY: @@ -2082,6 +2429,9 @@ static int ccs_post_streamoff(struct v4l2_subdev *subdev) struct ccs_sensor *sensor = to_ccs_sensor(subdev); struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); + if (ccs_is_imx681(sensor) && subdev != &sensor->src->sd) + return 0; + pm_runtime_put(&client->dev); return 0; @@ -2147,6 +2497,30 @@ static u32 ccs_get_mbus_code(struct v4l2_subdev *subdev, unsigned int pad) return sensor->internal_csi_format->code; } +static int ccs_enum_frame_size(struct v4l2_subdev *subdev, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct ccs_subdev *ssd = to_ccs_subdev(subdev); + struct ccs_sensor *sensor = ssd->sensor; + const struct ccs_imx681_mode *mode; + + if (!ccs_is_imx681(sensor) || fse->pad != ssd->source_pad || + fse->index) + return -EINVAL; + + if (fse->code != ccs_get_mbus_code(subdev, fse->pad)) + return -EINVAL; + + mode = ccs_imx681_current_mode(sensor); + fse->min_width = mode->width; + fse->max_width = mode->width; + fse->min_height = mode->height; + fse->max_height = mode->height; + + return 0; +} + static int ccs_get_format(struct v4l2_subdev *subdev, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) @@ -2182,6 +2556,17 @@ static void ccs_propagate(struct v4l2_subdev *subdev, CCS_STREAM_PIXEL); fmt->width = comp->width; fmt->height = comp->height; + if (ssd == ssd->sensor->src && ccs_is_imx681(ssd->sensor)) { + const struct ccs_imx681_mode *mode = + ccs_imx681_current_mode(ssd->sensor); + + crop->left = 0; + crop->top = 0; + crop->width = mode->width; + crop->height = mode->height; + fmt->width = mode->width; + fmt->height = mode->height; + } break; default: WARN_ON_ONCE(1); @@ -2586,6 +2971,16 @@ static void ccs_get_native_size(struct ccs_subdev *ssd, struct v4l2_rect *r) r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1; } +static void ccs_get_active_size(struct ccs_subdev *ssd, struct v4l2_rect *r) +{ + ccs_get_native_size(ssd, r); + + if (ccs_is_imx681(ssd->sensor)) { + r->width = 4032; + r->height = 3024; + } +} + static int ccs_get_selection(struct v4l2_subdev *subdev, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_selection *sel) @@ -2605,10 +3000,24 @@ static int ccs_get_selection(struct v4l2_subdev *subdev, CCS_STREAM_PIXEL); switch (sel->target) { - case V4L2_SEL_TGT_CROP_BOUNDS: case V4L2_SEL_TGT_NATIVE_SIZE: if (ssd == sensor->pixel_array) { ccs_get_native_size(ssd, &sel->r); + } else if (sel->pad == ssd->sink_pad) { + struct v4l2_mbus_framefmt *sink_fmt = + v4l2_subdev_state_get_format(sd_state, + ssd->sink_pad); + sel->r.top = 0; + sel->r.left = 0; + sel->r.width = sink_fmt->width; + sel->r.height = sink_fmt->height; + } else { + sel->r = *comp; + } + break; + case V4L2_SEL_TGT_CROP_BOUNDS: + if (ssd == sensor->pixel_array) { + ccs_get_active_size(ssd, &sel->r); } else if (sel->pad == ssd->sink_pad) { struct v4l2_mbus_framefmt *sink_fmt = v4l2_subdev_state_get_format(sd_state, @@ -2920,6 +3329,21 @@ static int ccs_identify_module(struct ccs_sensor *sensor) break; } + /* Sensor identities are distinct from the replaceable module tuple. */ + for (i = 0; i < ARRAY_SIZE(ccs_sensor_idents); i++) { + const struct ccs_sensor_ident *ident = &ccs_sensor_idents[i]; + + if (ident->manufacturer_id != + minfo->sensor_mipi_manufacturer_id || + ident->model_id != minfo->sensor_model_id || + ident->revision != minfo->sensor_revision_number) + continue; + + minfo->name = ident->name; + minfo->quirk = ident->quirk; + break; + } + dev_dbg(&client->dev, "the sensor is called %s\n", minfo->name); return 0; @@ -3080,7 +3504,7 @@ static int ccs_init_state(struct v4l2_subdev *sd, struct v4l2_rect *crop = v4l2_subdev_state_get_crop(sd_state, pad); - ccs_get_native_size(ssd, crop); + ccs_get_active_size(ssd, crop); fmt->width = crop->width; fmt->height = crop->height; @@ -3108,6 +3532,7 @@ static const struct v4l2_subdev_video_ops ccs_video_ops = { static const struct v4l2_subdev_pad_ops ccs_pad_ops = { .enum_mbus_code = ccs_enum_mbus_code, + .enum_frame_size = ccs_enum_frame_size, .get_fmt = ccs_get_format, .set_fmt = ccs_set_format, .get_selection = ccs_get_selection, diff --git a/drivers/media/i2c/ccs/ccs-imx681-init.h b/drivers/media/i2c/ccs/ccs-imx681-init.h new file mode 100644 index 00000000000000..cd0600d31a9159 --- /dev/null +++ b/drivers/media/i2c/ccs/ccs-imx681-init.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Sony IMX681 3844x2640, 969.6-Msymbol/s Linux mode based on the Andre + * Gilerson table from linux-surface-kernel and validated by the Snapdragon + * reference port. It is distinct from the static Windows 3840x2640, + * 1.2-Gsymbol/s mode. Multi-byte registers remain byte-split to preserve the + * proven write order. + */ + +#ifndef __CCS_IMX681_INIT_H__ +#define __CCS_IMX681_INIT_H__ + +static const struct ccs_reg_8 imx681_mode_3844x2640_regs[] = { + /* Software standby and 19.2 MHz external clock. */ + { 0x0100, 0x00 }, + { 0x0136, 0x13 }, + { 0x0137, 0x33 }, + { 0x002c, 0x05 }, + { 0x002d, 0x05 }, + /* C-PHY, RAW10, one trio; the requested orientation is restored later. */ + { 0x0110, 0x00 }, + { 0x0111, 0x03 }, + { 0x0112, 0x0a }, + { 0x0113, 0x0a }, + { 0x0114, 0x00 }, + { 0x0101, 0x00 }, + /* Vendor unlock sequence; ordering is significant. */ + { 0x30eb, 0x05 }, + { 0x30eb, 0x0c }, + { 0x300a, 0xff }, + { 0x300b, 0xff }, + { 0x3532, 0xff }, + { 0x3533, 0xff }, + /* + * LLP 8704 leaves about 13 percent line-idle headroom. The earlier + * 7552 value caused periodic receiver FIFO overruns. + */ + { 0x0342, 0x22 }, + { 0x0343, 0x00 }, + /* Frame length is 3177 lines. */ + { 0x033d, 0x00 }, + { 0x033e, 0x0c }, + { 0x033f, 0x69 }, + /* Analogue crop window from the proven Gilerson sequence. */ + { 0x0345, 0x64 }, + { 0x0346, 0x01 }, + { 0x0347, 0x00 }, + { 0x0349, 0x67 }, + { 0x034a, 0x0b }, + { 0x034b, 0x4f }, + { 0x040d, 0x04 }, + { 0x040e, 0x0a }, + { 0x040f, 0x50 }, + /* The sensor emits 3844x2640; any 3840 crop belongs downstream. */ + { 0x034c, 0x0f }, + { 0x034d, 0x04 }, + { 0x034e, 0x0a }, + { 0x034f, 0x50 }, + /* + * Preserve the branch dividers selected by the CCS PLL calculator and + * override only the multipliers from the hardware-proven Snapdragon + * sequence. The 0097c12-derived complete divider tuple produced no C-PHY + * packets on this device. + */ + { 0x0307, 0xe1 }, + { 0x030d, 0x03 }, + { 0x030e, 0x01 }, + { 0x030f, 0x2f }, + { 0x7e9b, 0x02 }, + { 0x0368, 0x00 }, + { 0xd383, 0x01 }, +}; + +#endif /* __CCS_IMX681_INIT_H__ */ diff --git a/drivers/media/i2c/ccs/ccs-imx681-mode.h b/drivers/media/i2c/ccs/ccs-imx681-mode.h new file mode 100644 index 00000000000000..e81ce293a005ae --- /dev/null +++ b/drivers/media/i2c/ccs/ccs-imx681-mode.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Sony IMX681 mode validated on the Surface Pro 11 C-PHY receiver. */ + +#ifndef __CCS_IMX681_MODE_H__ +#define __CCS_IMX681_MODE_H__ + +struct ccs_imx681_mode { + const struct ccs_reg_8 *regs; + size_t num_regs; + u32 width; + u32 height; + u32 line_length_pck; + u32 frame_length_lines; + u32 pixel_rate; + u32 exposure_default; + u32 gain_default; +}; + +static const struct ccs_imx681_mode imx681_mode = { + .regs = imx681_mode_3844x2640_regs, + .num_regs = ARRAY_SIZE(imx681_mode_3844x2640_regs), + .width = 3844, + .height = 2640, + .line_length_pck = 8704, + .frame_length_lines = 3177, + .pixel_rate = 432000000, + /* Initial values from the hardware-proven Snapdragon stream recipe. */ + .exposure_default = 3100, + /* Control value 192 maps to global U8.8 code 0x0400 (4x). */ + .gain_default = 192, +}; + +#endif /* __CCS_IMX681_MODE_H__ */ diff --git a/drivers/media/i2c/ccs/ccs-imx681-vendor.h b/drivers/media/i2c/ccs/ccs-imx681-vendor.h new file mode 100644 index 00000000000000..c66250e33bd141 --- /dev/null +++ b/drivers/media/i2c/ccs/ccs-imx681-vendor.h @@ -0,0 +1,375 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Full Snapdragon Surface Pro 11 IMX681 manufacturer initialisation from + * com.surface.sensormodule.ffc_imx681.bin. Registers 0x0136, 0x0137 and + * 0x0111 are deliberately supplied by the selected mode table instead. + */ + +#ifndef __CCS_IMX681_VENDOR_H__ +#define __CCS_IMX681_VENDOR_H__ + +static const struct ccs_reg_8 imx681_vendor_init[] = { + { 0x002c, 0x05 }, + { 0x002d, 0x05 }, + { 0x30eb, 0x05 }, + { 0x30eb, 0x0c }, + { 0x300a, 0xff }, + { 0x300b, 0xff }, + { 0x3532, 0xff }, + { 0x3533, 0xff }, + { 0x051e, 0x00 }, + { 0x0905, 0x04 }, + { 0x2029, 0x01 }, + { 0x202a, 0x11 }, + { 0x20a1, 0x00 }, + { 0x20a2, 0x02 }, + { 0x20a3, 0x03 }, + { 0x20ac, 0x01 }, + { 0x20ad, 0x01 }, + { 0x20ae, 0x01 }, + { 0x20af, 0x01 }, + { 0x20b0, 0x00 }, + { 0x20b1, 0x01 }, + { 0x20b2, 0x02 }, + { 0x20b3, 0x03 }, + { 0x706f, 0x00 }, + { 0x7130, 0x08 }, + { 0x7131, 0x08 }, + { 0x7408, 0x89 }, + { 0x7437, 0x3d }, + { 0x7439, 0x29 }, + { 0x7443, 0x38 }, + { 0x7447, 0x55 }, + { 0x744b, 0x00 }, + { 0x7451, 0x8e }, + { 0x746d, 0x29 }, + { 0x747d, 0x68 }, + { 0x7481, 0x60 }, + { 0x7491, 0x2d }, + { 0x7493, 0x31 }, + { 0x74a5, 0x52 }, + { 0x74af, 0x4a }, + { 0x74b5, 0x1f }, + { 0x74b7, 0x31 }, + { 0x74bd, 0x75 }, + { 0x74c5, 0x06 }, + { 0x74c9, 0x52 }, + { 0x74d3, 0x4a }, + { 0x74d9, 0x1f }, + { 0x74db, 0x31 }, + { 0x74e1, 0x75 }, + { 0x74e9, 0x06 }, + { 0x74ed, 0x52 }, + { 0x74f7, 0x4a }, + { 0x74fd, 0x1f }, + { 0x74ff, 0x31 }, + { 0x7505, 0x75 }, + { 0x750d, 0x06 }, + { 0x7537, 0x38 }, + { 0x753d, 0x4a }, + { 0x753f, 0x4a }, + { 0x7541, 0x4a }, + { 0x7549, 0x8e }, + { 0x754f, 0x75 }, + { 0x7551, 0x75 }, + { 0x7553, 0x75 }, + { 0x792b, 0x39 }, + { 0x792d, 0x43 }, + { 0x79d3, 0x25 }, + { 0x79d6, 0x8e }, + { 0x79d7, 0x01 }, + { 0x79d8, 0xe7 }, + { 0x79d9, 0x25 }, + { 0x79db, 0x76 }, + { 0x79dc, 0x8e }, + { 0x79dd, 0x01 }, + { 0x79de, 0xe7 }, + { 0x79df, 0x25 }, + { 0x79e1, 0x76 }, + { 0x79e2, 0x8e }, + { 0x79e3, 0x01 }, + { 0x79e4, 0xe7 }, + { 0x79e5, 0x25 }, + { 0x79e7, 0x76 }, + { 0x79e8, 0x8e }, + { 0x7a01, 0xff }, + { 0x7a29, 0x6c }, + { 0x7a2b, 0xda }, + { 0x7a34, 0x6c }, + { 0x7a37, 0xda }, + { 0x7a40, 0x6c }, + { 0x7a43, 0xda }, + { 0x7b08, 0x00 }, + { 0x7b09, 0x01 }, + { 0x7c03, 0x38 }, + { 0x7c09, 0x4a }, + { 0x7c0b, 0x4a }, + { 0x7c0d, 0x4a }, + { 0x7c13, 0x8e }, + { 0x7c19, 0x75 }, + { 0x7c1b, 0x75 }, + { 0x7c1d, 0x75 }, + { 0x7c90, 0x00 }, + { 0x7c91, 0x00 }, + { 0x7c92, 0x00 }, + { 0x7c9d, 0x01 }, + { 0x7c9e, 0x01 }, + { 0x7c9f, 0x01 }, + { 0x7e9b, 0x07 }, + { 0x7f09, 0x00 }, + { 0x7f36, 0x00 }, + { 0x7f4f, 0x0a }, + { 0x7f50, 0x0a }, + { 0x7f51, 0x0a }, + { 0x7f55, 0x05 }, + { 0x7f56, 0x05 }, + { 0x7f57, 0x05 }, + { 0x7f5b, 0x03 }, + { 0x7f5c, 0x03 }, + { 0x7f5d, 0x03 }, + { 0x7f61, 0x03 }, + { 0x7f62, 0x03 }, + { 0x7f63, 0x03 }, + { 0x7f67, 0x03 }, + { 0x7f68, 0x03 }, + { 0x7f69, 0x03 }, + { 0x7f6a, 0x05 }, + { 0x7f6b, 0x05 }, + { 0x7f6c, 0x05 }, + { 0x7f6d, 0x11 }, + { 0x7f6e, 0x14 }, + { 0x7f6f, 0x14 }, + { 0x7f73, 0x14 }, + { 0x7f74, 0x1c }, + { 0x7f75, 0x14 }, + { 0x7f76, 0x08 }, + { 0x7f79, 0x14 }, + { 0x7f7a, 0x1c }, + { 0x7f7b, 0x14 }, + { 0x7f7f, 0x1c }, + { 0x7f80, 0x1c }, + { 0x7f81, 0x1c }, + { 0x7f85, 0x1c }, + { 0x7f86, 0x1c }, + { 0x7f87, 0x1c }, + { 0x7f9d, 0x09 }, + { 0x7f9e, 0x09 }, + { 0x7f9f, 0x09 }, + { 0x7fa3, 0x09 }, + { 0x7fa4, 0x09 }, + { 0x7fa5, 0x09 }, + { 0x7fac, 0x00 }, + { 0x7fad, 0x00 }, + { 0x7fae, 0x00 }, + { 0x7faf, 0x00 }, + { 0x7fb0, 0x00 }, + { 0x7fb1, 0x00 }, + { 0x7fb2, 0x00 }, + { 0x7fb3, 0x00 }, + { 0x7fb4, 0x00 }, + { 0x7fb5, 0x00 }, + { 0x7fb6, 0x00 }, + { 0x7fb7, 0x00 }, + { 0x7fb8, 0x00 }, + { 0x7fb9, 0x00 }, + { 0x7fba, 0x00 }, + { 0x7fbb, 0x00 }, + { 0x7fbc, 0x00 }, + { 0x7fbd, 0x00 }, + { 0x7fbe, 0x00 }, + { 0x7fbf, 0x00 }, + { 0x7fc0, 0x00 }, + { 0x7fc1, 0x00 }, + { 0x7fc2, 0x00 }, + { 0x7fc3, 0x00 }, + { 0x7fcb, 0x37 }, + { 0x7fcd, 0x37 }, + { 0x7fcf, 0x37 }, + { 0x7fd7, 0x44 }, + { 0x7fd9, 0x44 }, + { 0x7fdb, 0x44 }, + { 0x7fdd, 0x38 }, + { 0x7fe3, 0x4a }, + { 0x7fe5, 0x4a }, + { 0x7fe7, 0x4a }, + { 0x7fef, 0x4a }, + { 0x7ff1, 0x4a }, + { 0x7ff3, 0x4a }, + { 0x7ffb, 0x4a }, + { 0x7ffd, 0x4a }, + { 0x7fff, 0x4a }, + { 0x8007, 0x62 }, + { 0x8009, 0x62 }, + { 0x800b, 0x62 }, + { 0x8013, 0x6f }, + { 0x8015, 0x6f }, + { 0x8017, 0x6f }, + { 0x8019, 0x8e }, + { 0x801f, 0x75 }, + { 0x8021, 0x75 }, + { 0x8023, 0x75 }, + { 0x802b, 0x75 }, + { 0x802d, 0x75 }, + { 0x802f, 0x75 }, + { 0x8037, 0x75 }, + { 0x8039, 0x75 }, + { 0x803b, 0x75 }, + { 0x803c, 0x13 }, + { 0x803d, 0x17 }, + { 0x803e, 0x15 }, + { 0x803f, 0x11 }, + { 0x8040, 0x0a }, + { 0x8041, 0x08 }, + { 0x8047, 0x17 }, + { 0x80f0, 0x24 }, + { 0x80f1, 0x1b }, + { 0x80f2, 0x1a }, + { 0x80f3, 0x14 }, + { 0x80f4, 0x14 }, + { 0x80f5, 0x12 }, + { 0x80f6, 0x25 }, + { 0x80f7, 0x1c }, + { 0x80f8, 0x1b }, + { 0x80f9, 0x18 }, + { 0x80fa, 0x17 }, + { 0x80fb, 0x18 }, + { 0x80fc, 0x26 }, + { 0x80fd, 0x1e }, + { 0x80fe, 0x1d }, + { 0x80ff, 0x1c }, + { 0x8100, 0x1b }, + { 0x8101, 0x1c }, + { 0x8102, 0x27 }, + { 0x8103, 0x1e }, + { 0x8104, 0x1d }, + { 0x8105, 0x1e }, + { 0x8106, 0x1e }, + { 0x8107, 0x1e }, + { 0x8108, 0x27 }, + { 0x8109, 0x1e }, + { 0x810a, 0x1e }, + { 0x810b, 0x1e }, + { 0x810c, 0x1e }, + { 0x810d, 0x1f }, + { 0x810e, 0x00 }, + { 0x8168, 0x0b }, + { 0x8169, 0x0b }, + { 0x816a, 0x09 }, + { 0x816b, 0x0f }, + { 0x816c, 0x0f }, + { 0x816d, 0x0f }, + { 0x816e, 0x0b }, + { 0x816f, 0x0b }, + { 0x8170, 0x0a }, + { 0x8171, 0x0f }, + { 0x8172, 0x0f }, + { 0x8173, 0x0f }, + { 0x8174, 0x0d }, + { 0x8175, 0x0c }, + { 0x8176, 0x09 }, + { 0x8177, 0x0f }, + { 0x8178, 0x0f }, + { 0x8179, 0x0f }, + { 0x817a, 0x0c }, + { 0x817b, 0x0d }, + { 0x817c, 0x09 }, + { 0x817d, 0x0f }, + { 0x817e, 0x0f }, + { 0x817f, 0x0f }, + { 0x8180, 0x0d }, + { 0x8181, 0x0d }, + { 0x8182, 0x09 }, + { 0x8183, 0x0f }, + { 0x8184, 0x0f }, + { 0x8185, 0x0f }, + { 0x81b0, 0x03 }, + { 0x81e3, 0x04 }, + { 0x81e4, 0x04 }, + { 0x81e9, 0x04 }, + { 0x81ea, 0x04 }, + { 0x81ef, 0x04 }, + { 0x81f0, 0x04 }, + { 0x9186, 0x00 }, + { 0xd030, 0x01 }, + { 0xd04c, 0x10 }, + { 0xd123, 0x75 }, + { 0xd144, 0x10 }, + { 0xd1af, 0x08 }, + { 0xd1bd, 0x67 }, + { 0xd1d4, 0x04 }, + { 0xd1d5, 0x04 }, + { 0xd1d6, 0x07 }, + { 0xd1d7, 0x07 }, + { 0xd1d9, 0x40 }, + { 0xd1db, 0x58 }, + { 0xd1dd, 0xd4 }, + { 0xd1df, 0xd4 }, + { 0xd1e1, 0xd4 }, + { 0xd348, 0x0f }, + { 0xd357, 0x00 }, + { 0xd3ae, 0x11 }, + { 0xd3af, 0x44 }, + { 0xd3b1, 0x7d }, + { 0xd803, 0xf0 }, + { 0xd80b, 0xf0 }, + { 0xd813, 0xf1 }, + { 0xd81b, 0xf0 }, + { 0xd843, 0xf1 }, + { 0xd84f, 0xf0 }, + { 0xd934, 0x23 }, + { 0xd935, 0xc8 }, + { 0xd938, 0x27 }, + { 0xd939, 0x10 }, + { 0xd93a, 0x23 }, + { 0xd93b, 0xc8 }, + { 0xd955, 0x07 }, + { 0xd95a, 0x04 }, + { 0xd95b, 0x0a }, + { 0xd95c, 0x1e }, + { 0xd95d, 0x00 }, + { 0xd95e, 0x14 }, + { 0xd95f, 0x21 }, + { 0xd960, 0x00 }, + { 0xd961, 0x00 }, + { 0xd962, 0x0a }, + { 0xd963, 0x50 }, + { 0xd964, 0x0a }, + { 0xd965, 0xa0 }, + { 0xd966, 0x00 }, + { 0xd967, 0x28 }, + { 0xd968, 0x0a }, + { 0xd969, 0x50 }, + { 0xd96a, 0x0a }, + { 0xd96b, 0xa0 }, + { 0xd96c, 0x00 }, + { 0xd96d, 0x00 }, + { 0xd96e, 0x0a }, + { 0xd96f, 0x44 }, + { 0xd970, 0x0a }, + { 0xd971, 0x50 }, + { 0xd972, 0x00 }, + { 0xd973, 0x00 }, + { 0xd974, 0x0a }, + { 0xd975, 0x44 }, + { 0xd976, 0x0a }, + { 0xd977, 0x50 }, + { 0xda10, 0x00 }, + { 0xda11, 0x14 }, + { 0xda12, 0x64 }, + { 0xda13, 0x00 }, + { 0xda14, 0x14 }, + { 0xda15, 0xc8 }, + { 0xda22, 0x00 }, + { 0xda23, 0x56 }, + { 0xda24, 0x00 }, + { 0xda25, 0xb5 }, + { 0xda26, 0x00 }, + { 0xda27, 0xe8 }, + { 0xda28, 0x08 }, + { 0xda29, 0xa6 }, + { 0xda2a, 0x00 }, + { 0xda2b, 0xa2 }, + { 0xda2f, 0x01 }, +}; + +#endif /* __CCS_IMX681_VENDOR_H__ */ diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c index e48a4fa1f5ddaf..bc1ca1042dee1d 100644 --- a/drivers/media/i2c/ccs/ccs-quirk.c +++ b/drivers/media/i2c/ccs/ccs-quirk.c @@ -33,6 +33,74 @@ static int ccs_write_addr_8s(struct ccs_sensor *sensor, return 0; } +struct ccs_limit_override { + unsigned int limit; + u32 value; +}; + +static int imx681_limits(struct ccs_sensor *sensor) +{ + /* + * Embedded equivalent of the IMX681 firmware limits for either + * reported manufacturer ID. Values are raw CCS register encodings, + * including IEEE-754 frequency limits. + */ + static const struct ccs_limit_override overrides[] = { + /* The 0x3b60 variant reports IREAL, but our overrides are IEEE-754. */ + { CCS_L_CLOCK_CAPA_TYPE_CAPABILITY, 0 }, + { CCS_L_MIN_OP_SYS_CLK_FREQ_REV_MHZ, 0x44834000 }, + { CCS_L_MAX_OP_SYS_CLK_FREQ_REV_MHZ, 0x451c4000 }, + { CCS_L_MIN_OP_PIX_CLK_FREQ_REV_MHZ, 0x41960000 }, + { CCS_L_MAX_OP_PIX_CLK_FREQ_REV_MHZ, 0x4332947b }, + { CCS_L_NUM_OF_OP_LANES, 0x00 }, + { CCS_L_OP_BITS_PER_LANE, 0x0a }, + { CCS_L_MIN_PLL_OP_CLK_FREQ_MHZ, 0x4489e600 }, + /* PLL front-branch limits — the 0x3b60 variant reports 0 for these. */ + { CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0x40000000 }, /* 2.0 MHz */ + { CCS_L_MAX_PLL_IP_CLK_FREQ_MHZ, 0x42000000 }, /* 32.0 MHz */ + { CCS_L_MAX_PLL_OP_CLK_FREQ_MHZ, 0x451c4000 }, /* ~2500 MHz */ + { CCS_L_MIN_OP_SYS_CLK_FREQ_MHZ, 0x44834000 }, /* ~1050 MHz */ + { CCS_L_MAX_OP_SYS_CLK_FREQ_MHZ, 0x451c4000 }, /* ~2500 MHz */ + { CCS_L_MIN_OP_PIX_CLK_FREQ_MHZ, 0x41960000 }, /* ~18.75 MHz */ + { CCS_L_MIN_PLL_MULTIPLIER, 1 }, + { CCS_L_MAX_PLL_MULTIPLIER, 511 }, + { CCS_L_MIN_OP_SYS_CLK_DIV, 1 }, + { CCS_L_MAX_OP_SYS_CLK_DIV, 16 }, + { CCS_L_MIN_OP_PIX_CLK_DIV, 1 }, + { CCS_L_MAX_OP_PIX_CLK_DIV, 16 }, + /* + * Bring-up-derived permissive limit. The mode table programs the + * sensor PLL itself; its validated 3844x2640 mode emits a 969.6 + * Msymbol/s C-PHY stream and uses a 387.84 MHz pixel rate. Keep the + * calculator ceiling at 600 MHz so this fixed mode passes probe even + * when the sensor's reported limits are incomplete. + */ + { CCS_L_MAX_OP_PIX_CLK_FREQ_MHZ, 0x44160000 }, /* 600 MHz */ + { CCS_L_MIN_VT_SYS_CLK_DIV, 1 }, + { CCS_L_MAX_VT_SYS_CLK_DIV, 16 }, + { CCS_L_MIN_VT_PIX_CLK_DIV, 1 }, + { CCS_L_MAX_VT_PIX_CLK_DIV, 16 }, + { CCS_L_MIN_VT_SYS_CLK_FREQ_MHZ, 0x44834000 }, /* ~1050 MHz */ + { CCS_L_MAX_VT_SYS_CLK_FREQ_MHZ, 0x451c4000 }, /* ~2500 MHz */ + { CCS_L_MIN_VT_PIX_CLK_FREQ_MHZ, 0x43200000 }, /* 160 MHz */ + { CCS_L_MAX_VT_PIX_CLK_FREQ_MHZ, 0x44160000 }, /* 600 MHz */ + }; + unsigned int i; + + if (!ccs_is_imx681(sensor)) + return 0; + + for (i = 0; i < ARRAY_SIZE(overrides); i++) + ccs_replace_limit(sensor, overrides[i].limit, 0, + overrides[i].value); + + return 0; +} + +const struct ccs_quirk ccs_imx681_quirk = { + .limits = imx681_limits, +}; + static int jt8ew9_limits(struct ccs_sensor *sensor) { if (sensor->minfo.revision_number < 0x0300) diff --git a/drivers/media/i2c/ccs/ccs-quirk.h b/drivers/media/i2c/ccs/ccs-quirk.h index 392c9710961770..156b32605abb78 100644 --- a/drivers/media/i2c/ccs/ccs-quirk.h +++ b/drivers/media/i2c/ccs/ccs-quirk.h @@ -75,5 +75,6 @@ extern const struct ccs_quirk smiapp_jt8ev1_quirk; extern const struct ccs_quirk smiapp_imx125es_quirk; extern const struct ccs_quirk smiapp_jt8ew9_quirk; extern const struct ccs_quirk smiapp_tcm8500md_quirk; +extern const struct ccs_quirk ccs_imx681_quirk; #endif /* __CCS_QUIRK__ */ diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index a0181a5d2f34ce..9e60ef109aeb94 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -48,6 +48,9 @@ static u32 float_to_u32_mul_1000000(struct i2c_client *client, u32 phloat) * have 0 in the high bit) */ exp = ((int32_t)phloat >> 23) - 127; + /* Such small values round down to zero after scaling. */ + if (exp <= -64) + return 0; /* Extract mantissa, add missing '1' bit and it's in MHz */ man = ((phloat & 0x7fffff) | 0x800000) * 1000000ULL; diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index 58952c5bf06b01..1b21f310b4ffdb 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -249,6 +249,8 @@ struct ccs_sensor { /* Pixel array controls */ struct v4l2_ctrl *exposure; + struct v4l2_ctrl *analogue_gain; + struct v4l2_ctrl *digital_gain; struct v4l2_ctrl *hflip; struct v4l2_ctrl *vflip; struct v4l2_ctrl *vblank; @@ -268,6 +270,32 @@ struct ccs_sensor { #define to_ccs_sensor(_sd) \ (to_ccs_subdev(_sd)->sensor) +#define CCS_IMX681_MFR_ID 0x4260 +#define CCS_IMX681_SP11_MFR_ID 0x3b60 +#define CCS_IMX681_MODEL_ID 0x0681 +#define CCS_IMX681_REVISION 0x0010 + +static inline bool ccs_is_imx681_id(u16 manufacturer_id, u16 model_id, + u16 revision) +{ + /* + * This SP11 unit reports manufacturer 0x3b60 (firmware filename + * ccs-sensor-3b60-0681-0010.fw); other units may report 0x4260. + * Both identities are the Sony IMX681. + */ + return (manufacturer_id == CCS_IMX681_MFR_ID || + manufacturer_id == CCS_IMX681_SP11_MFR_ID) && + model_id == CCS_IMX681_MODEL_ID && + revision == CCS_IMX681_REVISION; +} + +static inline bool ccs_is_imx681(const struct ccs_sensor *sensor) +{ + return ccs_is_imx681_id(sensor->minfo.sensor_mipi_manufacturer_id, + sensor->minfo.sensor_model_id, + sensor->minfo.sensor_revision_number); +} + void ccs_replace_limit(struct ccs_sensor *sensor, unsigned int limit, unsigned int offset, u32 val); u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit, diff --git a/drivers/media/i2c/imx681-tables.h b/drivers/media/i2c/imx681-tables.h new file mode 100644 index 00000000000000..b6ec68594490c1 --- /dev/null +++ b/drivers/media/i2c/imx681-tables.h @@ -0,0 +1,455 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Sony IMX681 register tables for the Surface Pro 11 front camera. + * + * These tables are an independently written representation of runtime I2C + * transactions observed on the author's own hardware. The observed + * stream-start order is global initialization, followed by the selected mode. + * Mode: 3840x2640 RAW10, LLP 6752, FLL 3554, C-PHY bus pixel rate + * 548571428 Hz, ONE C-PHY TRIO at 2406 Msym/s. Runtime frame cadence is + * approximately 30 fps; the distinct VT timing clock remains to be measured. + */ +#ifndef __IMX681_TABLES_H +#define __IMX681_TABLES_H + +#include + +static const struct cci_reg_sequence imx681_global_init_table[] = { + { CCI_REG8(0x0136), 0x13 }, + { CCI_REG8(0x0137), 0x33 }, + { CCI_REG8(0x002c), 0x05 }, + { CCI_REG8(0x002d), 0x05 }, + { CCI_REG8(0x0111), 0x03 }, + { CCI_REG8(0x30eb), 0x05 }, + { CCI_REG8(0x30eb), 0x0c }, + { CCI_REG8(0x300a), 0xff }, + { CCI_REG8(0x300b), 0xff }, + { CCI_REG8(0x3532), 0xff }, + { CCI_REG8(0x3533), 0xff }, + { CCI_REG8(0x051e), 0x00 }, + { CCI_REG8(0x0905), 0x04 }, + { CCI_REG8(0x2029), 0x01 }, + { CCI_REG8(0x202a), 0x11 }, + { CCI_REG8(0x20a1), 0x00 }, + { CCI_REG8(0x20a2), 0x02 }, + { CCI_REG8(0x20a3), 0x03 }, + { CCI_REG8(0x20ac), 0x01 }, + { CCI_REG8(0x20ad), 0x01 }, + { CCI_REG8(0x20ae), 0x01 }, + { CCI_REG8(0x20af), 0x01 }, + { CCI_REG8(0x20b0), 0x00 }, + { CCI_REG8(0x20b1), 0x01 }, + { CCI_REG8(0x20b2), 0x02 }, + { CCI_REG8(0x20b3), 0x03 }, + { CCI_REG8(0x706f), 0x00 }, + { CCI_REG8(0x7130), 0x08 }, + { CCI_REG8(0x7131), 0x08 }, + { CCI_REG8(0x7408), 0x89 }, + { CCI_REG8(0x7437), 0x3d }, + { CCI_REG8(0x7439), 0x29 }, + { CCI_REG8(0x7443), 0x38 }, + { CCI_REG8(0x7447), 0x55 }, + { CCI_REG8(0x744b), 0x00 }, + { CCI_REG8(0x7451), 0x8e }, + { CCI_REG8(0x746d), 0x29 }, + { CCI_REG8(0x747d), 0x68 }, + { CCI_REG8(0x7481), 0x60 }, + { CCI_REG8(0x7491), 0x2d }, + { CCI_REG8(0x7493), 0x31 }, + { CCI_REG8(0x74a5), 0x52 }, + { CCI_REG8(0x74af), 0x4a }, + { CCI_REG8(0x74b5), 0x1f }, + { CCI_REG8(0x74b7), 0x31 }, + { CCI_REG8(0x74bd), 0x75 }, + { CCI_REG8(0x74c5), 0x06 }, + { CCI_REG8(0x74c9), 0x52 }, + { CCI_REG8(0x74d3), 0x4a }, + { CCI_REG8(0x74d9), 0x1f }, + { CCI_REG8(0x74db), 0x31 }, + { CCI_REG8(0x74e1), 0x75 }, + { CCI_REG8(0x74e9), 0x06 }, + { CCI_REG8(0x74ed), 0x52 }, + { CCI_REG8(0x74f7), 0x4a }, + { CCI_REG8(0x74fd), 0x1f }, + { CCI_REG8(0x74ff), 0x31 }, + { CCI_REG8(0x7505), 0x75 }, + { CCI_REG8(0x750d), 0x06 }, + { CCI_REG8(0x7537), 0x38 }, + { CCI_REG8(0x753d), 0x4a }, + { CCI_REG8(0x753f), 0x4a }, + { CCI_REG8(0x7541), 0x4a }, + { CCI_REG8(0x7549), 0x8e }, + { CCI_REG8(0x754f), 0x75 }, + { CCI_REG8(0x7551), 0x75 }, + { CCI_REG8(0x7553), 0x75 }, + { CCI_REG8(0x792b), 0x39 }, + { CCI_REG8(0x792d), 0x43 }, + { CCI_REG8(0x79d3), 0x25 }, + { CCI_REG8(0x79d6), 0x8e }, + { CCI_REG8(0x79d7), 0x01 }, + { CCI_REG8(0x79d8), 0xe7 }, + { CCI_REG8(0x79d9), 0x25 }, + { CCI_REG8(0x79db), 0x76 }, + { CCI_REG8(0x79dc), 0x8e }, + { CCI_REG8(0x79dd), 0x01 }, + { CCI_REG8(0x79de), 0xe7 }, + { CCI_REG8(0x79df), 0x25 }, + { CCI_REG8(0x79e1), 0x76 }, + { CCI_REG8(0x79e2), 0x8e }, + { CCI_REG8(0x79e3), 0x01 }, + { CCI_REG8(0x79e4), 0xe7 }, + { CCI_REG8(0x79e5), 0x25 }, + { CCI_REG8(0x79e7), 0x76 }, + { CCI_REG8(0x79e8), 0x8e }, + { CCI_REG8(0x7a01), 0xff }, + { CCI_REG8(0x7a29), 0x6c }, + { CCI_REG8(0x7a2b), 0xda }, + { CCI_REG8(0x7a34), 0x6c }, + { CCI_REG8(0x7a37), 0xda }, + { CCI_REG8(0x7a40), 0x6c }, + { CCI_REG8(0x7a43), 0xda }, + { CCI_REG8(0x7b08), 0x00 }, + { CCI_REG8(0x7b09), 0x01 }, + { CCI_REG8(0x7c03), 0x38 }, + { CCI_REG8(0x7c09), 0x4a }, + { CCI_REG8(0x7c0b), 0x4a }, + { CCI_REG8(0x7c0d), 0x4a }, + { CCI_REG8(0x7c13), 0x8e }, + { CCI_REG8(0x7c19), 0x75 }, + { CCI_REG8(0x7c1b), 0x75 }, + { CCI_REG8(0x7c1d), 0x75 }, + { CCI_REG8(0x7c90), 0x00 }, + { CCI_REG8(0x7c91), 0x00 }, + { CCI_REG8(0x7c92), 0x00 }, + { CCI_REG8(0x7c9d), 0x01 }, + { CCI_REG8(0x7c9e), 0x01 }, + { CCI_REG8(0x7c9f), 0x01 }, + { CCI_REG8(0x7e9b), 0x07 }, + { CCI_REG8(0x7f09), 0x00 }, + { CCI_REG8(0x7f36), 0x00 }, + { CCI_REG8(0x7f4f), 0x0a }, + { CCI_REG8(0x7f50), 0x0a }, + { CCI_REG8(0x7f51), 0x0a }, + { CCI_REG8(0x7f55), 0x05 }, + { CCI_REG8(0x7f56), 0x05 }, + { CCI_REG8(0x7f57), 0x05 }, + { CCI_REG8(0x7f5b), 0x03 }, + { CCI_REG8(0x7f5c), 0x03 }, + { CCI_REG8(0x7f5d), 0x03 }, + { CCI_REG8(0x7f61), 0x03 }, + { CCI_REG8(0x7f62), 0x03 }, + { CCI_REG8(0x7f63), 0x03 }, + { CCI_REG8(0x7f67), 0x03 }, + { CCI_REG8(0x7f68), 0x03 }, + { CCI_REG8(0x7f69), 0x03 }, + { CCI_REG8(0x7f6a), 0x05 }, + { CCI_REG8(0x7f6b), 0x05 }, + { CCI_REG8(0x7f6c), 0x05 }, + { CCI_REG8(0x7f6d), 0x11 }, + { CCI_REG8(0x7f6e), 0x14 }, + { CCI_REG8(0x7f6f), 0x14 }, + { CCI_REG8(0x7f73), 0x14 }, + { CCI_REG8(0x7f74), 0x1c }, + { CCI_REG8(0x7f75), 0x14 }, + { CCI_REG8(0x7f76), 0x08 }, + { CCI_REG8(0x7f79), 0x14 }, + { CCI_REG8(0x7f7a), 0x1c }, + { CCI_REG8(0x7f7b), 0x14 }, + { CCI_REG8(0x7f7f), 0x1c }, + { CCI_REG8(0x7f80), 0x1c }, + { CCI_REG8(0x7f81), 0x1c }, + { CCI_REG8(0x7f85), 0x1c }, + { CCI_REG8(0x7f86), 0x1c }, + { CCI_REG8(0x7f87), 0x1c }, + { CCI_REG8(0x7f9d), 0x09 }, + { CCI_REG8(0x7f9e), 0x09 }, + { CCI_REG8(0x7f9f), 0x09 }, + { CCI_REG8(0x7fa3), 0x09 }, + { CCI_REG8(0x7fa4), 0x09 }, + { CCI_REG8(0x7fa5), 0x09 }, + { CCI_REG8(0x7fac), 0x00 }, + { CCI_REG8(0x7fad), 0x00 }, + { CCI_REG8(0x7fae), 0x00 }, + { CCI_REG8(0x7faf), 0x00 }, + { CCI_REG8(0x7fb0), 0x00 }, + { CCI_REG8(0x7fb1), 0x00 }, + { CCI_REG8(0x7fb2), 0x00 }, + { CCI_REG8(0x7fb3), 0x00 }, + { CCI_REG8(0x7fb4), 0x00 }, + { CCI_REG8(0x7fb5), 0x00 }, + { CCI_REG8(0x7fb6), 0x00 }, + { CCI_REG8(0x7fb7), 0x00 }, + { CCI_REG8(0x7fb8), 0x00 }, + { CCI_REG8(0x7fb9), 0x00 }, + { CCI_REG8(0x7fba), 0x00 }, + { CCI_REG8(0x7fbb), 0x00 }, + { CCI_REG8(0x7fbc), 0x00 }, + { CCI_REG8(0x7fbd), 0x00 }, + { CCI_REG8(0x7fbe), 0x00 }, + { CCI_REG8(0x7fbf), 0x00 }, + { CCI_REG8(0x7fc0), 0x00 }, + { CCI_REG8(0x7fc1), 0x00 }, + { CCI_REG8(0x7fc2), 0x00 }, + { CCI_REG8(0x7fc3), 0x00 }, + { CCI_REG8(0x7fcb), 0x37 }, + { CCI_REG8(0x7fcd), 0x37 }, + { CCI_REG8(0x7fcf), 0x37 }, + { CCI_REG8(0x7fd7), 0x44 }, + { CCI_REG8(0x7fd9), 0x44 }, + { CCI_REG8(0x7fdb), 0x44 }, + { CCI_REG8(0x7fdd), 0x38 }, + { CCI_REG8(0x7fe3), 0x4a }, + { CCI_REG8(0x7fe5), 0x4a }, + { CCI_REG8(0x7fe7), 0x4a }, + { CCI_REG8(0x7fef), 0x4a }, + { CCI_REG8(0x7ff1), 0x4a }, + { CCI_REG8(0x7ff3), 0x4a }, + { CCI_REG8(0x7ffb), 0x4a }, + { CCI_REG8(0x7ffd), 0x4a }, + { CCI_REG8(0x7fff), 0x4a }, + { CCI_REG8(0x8007), 0x62 }, + { CCI_REG8(0x8009), 0x62 }, + { CCI_REG8(0x800b), 0x62 }, + { CCI_REG8(0x8013), 0x6f }, + { CCI_REG8(0x8015), 0x6f }, + { CCI_REG8(0x8017), 0x6f }, + { CCI_REG8(0x8019), 0x8e }, + { CCI_REG8(0x801f), 0x75 }, + { CCI_REG8(0x8021), 0x75 }, + { CCI_REG8(0x8023), 0x75 }, + { CCI_REG8(0x802b), 0x75 }, + { CCI_REG8(0x802d), 0x75 }, + { CCI_REG8(0x802f), 0x75 }, + { CCI_REG8(0x8037), 0x75 }, + { CCI_REG8(0x8039), 0x75 }, + { CCI_REG8(0x803b), 0x75 }, + { CCI_REG8(0x803c), 0x13 }, + { CCI_REG8(0x803d), 0x17 }, + { CCI_REG8(0x803e), 0x15 }, + { CCI_REG8(0x803f), 0x11 }, + { CCI_REG8(0x8040), 0x0a }, + { CCI_REG8(0x8041), 0x08 }, + { CCI_REG8(0x8047), 0x17 }, + { CCI_REG8(0x80f0), 0x24 }, + { CCI_REG8(0x80f1), 0x1b }, + { CCI_REG8(0x80f2), 0x1a }, + { CCI_REG8(0x80f3), 0x14 }, + { CCI_REG8(0x80f4), 0x14 }, + { CCI_REG8(0x80f5), 0x12 }, + { CCI_REG8(0x80f6), 0x25 }, + { CCI_REG8(0x80f7), 0x1c }, + { CCI_REG8(0x80f8), 0x1b }, + { CCI_REG8(0x80f9), 0x18 }, + { CCI_REG8(0x80fa), 0x17 }, + { CCI_REG8(0x80fb), 0x18 }, + { CCI_REG8(0x80fc), 0x26 }, + { CCI_REG8(0x80fd), 0x1e }, + { CCI_REG8(0x80fe), 0x1d }, + { CCI_REG8(0x80ff), 0x1c }, + { CCI_REG8(0x8100), 0x1b }, + { CCI_REG8(0x8101), 0x1c }, + { CCI_REG8(0x8102), 0x27 }, + { CCI_REG8(0x8103), 0x1e }, + { CCI_REG8(0x8104), 0x1d }, + { CCI_REG8(0x8105), 0x1e }, + { CCI_REG8(0x8106), 0x1e }, + { CCI_REG8(0x8107), 0x1e }, + { CCI_REG8(0x8108), 0x27 }, + { CCI_REG8(0x8109), 0x1e }, + { CCI_REG8(0x810a), 0x1e }, + { CCI_REG8(0x810b), 0x1e }, + { CCI_REG8(0x810c), 0x1e }, + { CCI_REG8(0x810d), 0x1f }, + { CCI_REG8(0x810e), 0x00 }, + { CCI_REG8(0x8168), 0x0b }, + { CCI_REG8(0x8169), 0x0b }, + { CCI_REG8(0x816a), 0x09 }, + { CCI_REG8(0x816b), 0x0f }, + { CCI_REG8(0x816c), 0x0f }, + { CCI_REG8(0x816d), 0x0f }, + { CCI_REG8(0x816e), 0x0b }, + { CCI_REG8(0x816f), 0x0b }, + { CCI_REG8(0x8170), 0x0a }, + { CCI_REG8(0x8171), 0x0f }, + { CCI_REG8(0x8172), 0x0f }, + { CCI_REG8(0x8173), 0x0f }, + { CCI_REG8(0x8174), 0x0d }, + { CCI_REG8(0x8175), 0x0c }, + { CCI_REG8(0x8176), 0x09 }, + { CCI_REG8(0x8177), 0x0f }, + { CCI_REG8(0x8178), 0x0f }, + { CCI_REG8(0x8179), 0x0f }, + { CCI_REG8(0x817a), 0x0c }, + { CCI_REG8(0x817b), 0x0d }, + { CCI_REG8(0x817c), 0x09 }, + { CCI_REG8(0x817d), 0x0f }, + { CCI_REG8(0x817e), 0x0f }, + { CCI_REG8(0x817f), 0x0f }, + { CCI_REG8(0x8180), 0x0d }, + { CCI_REG8(0x8181), 0x0d }, + { CCI_REG8(0x8182), 0x09 }, + { CCI_REG8(0x8183), 0x0f }, + { CCI_REG8(0x8184), 0x0f }, + { CCI_REG8(0x8185), 0x0f }, + { CCI_REG8(0x81b0), 0x03 }, + { CCI_REG8(0x81e3), 0x04 }, + { CCI_REG8(0x81e4), 0x04 }, + { CCI_REG8(0x81e9), 0x04 }, + { CCI_REG8(0x81ea), 0x04 }, + { CCI_REG8(0x81ef), 0x04 }, + { CCI_REG8(0x81f0), 0x04 }, + { CCI_REG8(0x9186), 0x00 }, + { CCI_REG8(0xd030), 0x01 }, + { CCI_REG8(0xd04c), 0x10 }, + { CCI_REG8(0xd123), 0x75 }, + { CCI_REG8(0xd144), 0x10 }, + { CCI_REG8(0xd1af), 0x08 }, + { CCI_REG8(0xd1bd), 0x67 }, + { CCI_REG8(0xd1d4), 0x04 }, + { CCI_REG8(0xd1d5), 0x04 }, + { CCI_REG8(0xd1d6), 0x07 }, + { CCI_REG8(0xd1d7), 0x07 }, + { CCI_REG8(0xd1d9), 0x40 }, + { CCI_REG8(0xd1db), 0x58 }, + { CCI_REG8(0xd1dd), 0xd4 }, + { CCI_REG8(0xd1df), 0xd4 }, + { CCI_REG8(0xd1e1), 0xd4 }, + { CCI_REG8(0xd348), 0x0f }, + { CCI_REG8(0xd357), 0x00 }, + { CCI_REG8(0xd3ae), 0x11 }, + { CCI_REG8(0xd3af), 0x44 }, + { CCI_REG8(0xd3b1), 0x7d }, + { CCI_REG8(0xd803), 0xf0 }, + { CCI_REG8(0xd80b), 0xf0 }, + { CCI_REG8(0xd813), 0xf1 }, + { CCI_REG8(0xd81b), 0xf0 }, + { CCI_REG8(0xd843), 0xf1 }, + { CCI_REG8(0xd84f), 0xf0 }, + { CCI_REG8(0xd934), 0x23 }, + { CCI_REG8(0xd935), 0xc8 }, + { CCI_REG8(0xd938), 0x27 }, + { CCI_REG8(0xd939), 0x10 }, + { CCI_REG8(0xd93a), 0x23 }, + { CCI_REG8(0xd93b), 0xc8 }, + { CCI_REG8(0xd955), 0x07 }, + { CCI_REG8(0xd95a), 0x04 }, + { CCI_REG8(0xd95b), 0x0a }, + { CCI_REG8(0xd95c), 0x1e }, + { CCI_REG8(0xd95d), 0x00 }, + { CCI_REG8(0xd95e), 0x14 }, + { CCI_REG8(0xd95f), 0x21 }, + { CCI_REG8(0xd960), 0x00 }, + { CCI_REG8(0xd961), 0x00 }, + { CCI_REG8(0xd962), 0x0a }, + { CCI_REG8(0xd963), 0x50 }, + { CCI_REG8(0xd964), 0x0a }, + { CCI_REG8(0xd965), 0xa0 }, + { CCI_REG8(0xd966), 0x00 }, + { CCI_REG8(0xd967), 0x28 }, + { CCI_REG8(0xd968), 0x0a }, + { CCI_REG8(0xd969), 0x50 }, + { CCI_REG8(0xd96a), 0x0a }, + { CCI_REG8(0xd96b), 0xa0 }, + { CCI_REG8(0xd96c), 0x00 }, + { CCI_REG8(0xd96d), 0x00 }, + { CCI_REG8(0xd96e), 0x0a }, + { CCI_REG8(0xd96f), 0x44 }, + { CCI_REG8(0xd970), 0x0a }, + { CCI_REG8(0xd971), 0x50 }, + { CCI_REG8(0xd972), 0x00 }, + { CCI_REG8(0xd973), 0x00 }, + { CCI_REG8(0xd974), 0x0a }, + { CCI_REG8(0xd975), 0x44 }, + { CCI_REG8(0xd976), 0x0a }, + { CCI_REG8(0xd977), 0x50 }, + { CCI_REG8(0xda10), 0x00 }, + { CCI_REG8(0xda11), 0x14 }, + { CCI_REG8(0xda12), 0x64 }, + { CCI_REG8(0xda13), 0x00 }, + { CCI_REG8(0xda14), 0x14 }, + { CCI_REG8(0xda15), 0xc8 }, + { CCI_REG8(0xda22), 0x00 }, + { CCI_REG8(0xda23), 0x56 }, + { CCI_REG8(0xda24), 0x00 }, + { CCI_REG8(0xda25), 0xb5 }, + { CCI_REG8(0xda26), 0x00 }, + { CCI_REG8(0xda27), 0xe8 }, + { CCI_REG8(0xda28), 0x08 }, + { CCI_REG8(0xda29), 0xa6 }, + { CCI_REG8(0xda2a), 0x00 }, + { CCI_REG8(0xda2b), 0xa2 }, + { CCI_REG8(0xda2f), 0x01 }, +}; + +static const struct cci_reg_sequence imx681_mode_3840x2640[] = { + { CCI_REG8(0x0110), 0x00 }, + { CCI_REG8(0x0112), 0x0a }, + { CCI_REG8(0x0113), 0x0a }, + { CCI_REG8(0x0114), 0x00 }, + { CCI_REG8(0x0342), 0x1a }, + { CCI_REG8(0x0343), 0x60 }, + { CCI_REG8(0x033d), 0x00 }, + { CCI_REG8(0x033e), 0x0d }, + { CCI_REG8(0x033f), 0xe2 }, + { CCI_REG8(0x0344), 0x00 }, + { CCI_REG8(0x0345), 0x68 }, + { CCI_REG8(0x0346), 0x01 }, + { CCI_REG8(0x0347), 0x00 }, + { CCI_REG8(0x0348), 0x0f }, + { CCI_REG8(0x0349), 0x67 }, + { CCI_REG8(0x034a), 0x0b }, + { CCI_REG8(0x034b), 0x4f }, + { CCI_REG8(0x017c), 0x01 }, + { CCI_REG8(0x017d), 0x01 }, + { CCI_REG8(0x017e), 0x00 }, + { CCI_REG8(0x017f), 0x01 }, + { CCI_REG8(0x0180), 0x00 }, + { CCI_REG8(0x038c), 0x13 }, + { CCI_REG8(0x038d), 0x33 }, + { CCI_REG8(0x2000), 0x01 }, + { CCI_REG8(0x0408), 0x00 }, + { CCI_REG8(0x0409), 0x00 }, + { CCI_REG8(0x040a), 0x00 }, + { CCI_REG8(0x040b), 0x00 }, + { CCI_REG8(0x040c), 0x0f }, + { CCI_REG8(0x040d), 0x00 }, + { CCI_REG8(0x040e), 0x0a }, + { CCI_REG8(0x040f), 0x50 }, + { CCI_REG8(0x034c), 0x0f }, + { CCI_REG8(0x034d), 0x00 }, + { CCI_REG8(0x034e), 0x0a }, + { CCI_REG8(0x034f), 0x50 }, + { CCI_REG8(0x0301), 0x06 }, + { CCI_REG8(0x0303), 0x02 }, + { CCI_REG8(0x0305), 0x02 }, + { CCI_REG8(0x0306), 0x00 }, + { CCI_REG8(0x0307), 0xe1 }, + { CCI_REG8(0x030d), 0x03 }, + { CCI_REG8(0x030e), 0x01 }, + { CCI_REG8(0x030f), 0x77 }, + { CCI_REG8(0x0323), 0x00 }, + { CCI_REG8(0x0229), 0x00 }, + { CCI_REG8(0x022a), 0x0d }, + { CCI_REG8(0x022b), 0xda }, + { CCI_REG8(0xd383), 0x01 }, + { CCI_REG8(0x0204), 0x00 }, + { CCI_REG8(0x0205), 0x00 }, + { CCI_REG8(0x020e), 0x01 }, + { CCI_REG8(0x020f), 0x00 }, + { CCI_REG8(0x0210), 0x01 }, + { CCI_REG8(0x0211), 0x00 }, + { CCI_REG8(0x0212), 0x01 }, + { CCI_REG8(0x0213), 0x00 }, + { CCI_REG8(0x0214), 0x01 }, + { CCI_REG8(0x0215), 0x00 }, + { CCI_REG8(0x6a83), 0x03 }, + { CCI_REG8(0x7e9b), 0x02 }, + { CCI_REG8(0xd1ce), 0x00 }, + { CCI_REG8(0xdc3c), 0x01 }, + { CCI_REG8(0x0368), 0x00 }, + { CCI_REG8(0x036a), 0x08 }, + { CCI_REG8(0x036b), 0x70 }, + { CCI_REG8(0x2001), 0x00 }, +}; + +#endif /* __IMX681_TABLES_H */ diff --git a/drivers/media/i2c/imx681.c b/drivers/media/i2c/imx681.c new file mode 100644 index 00000000000000..b963373951de74 --- /dev/null +++ b/drivers/media/i2c/imx681.c @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Sony IMX681 sensor driver (Surface Pro 11 front camera). + * + * The SP11 mode is an independently written representation of register + * transactions observed while operating the author's own camera hardware. + * Single supported mode: + * 3840x2640 RAW10 at ~30 fps over ONE C-PHY TRIO at 2406 Msym/s + * (CSI_SIGNALING_MODE 0x0111=3). This tree carries experimental + * three-phase qcom camss support. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx681-tables.h" + +#define IMX681_REG_MODEL_ID CCI_REG16(0x0016) +#define IMX681_MODEL_ID 0x0681 +#define IMX681_REG_MODE_SELECT CCI_REG8(0x0100) +#define IMX681_MODE_STREAMING 1 +#define IMX681_MODE_STANDBY 0 +#define IMX681_REG_GROUP_HOLD CCI_REG8(0x0104) +#define IMX681_REG_EXPOSURE CCI_REG24(0x0229) +#define IMX681_REG_ANALOG_GAIN CCI_REG16(0x0204) +#define IMX681_REG_DIGITAL_GAIN CCI_REG16(0x020e) +#define IMX681_REG_FRAME_LENGTH CCI_REG16(0x0340) + +#define IMX681_WIDTH 3840 +#define IMX681_HEIGHT 2640 +#define IMX681_LINE_LENGTH 6752 +#define IMX681_FRAME_LENGTH_DEF 2708 +#define IMX681_FRAME_LENGTH_MAX 0xffff +#define IMX681_EXPOSURE_MARGIN 48 +#define IMX681_EXPOSURE_DEF 1600 +#define IMX681_AGAIN_MAX 960 /* gain = 1024 / (1024 - code) */ +#define IMX681_DGAIN_DEF 0x0100 +#define IMX681_PIXEL_RATE 548571428 +/* V4L2 C-PHY link frequency is half the 2406-Msym/s symbol rate. */ +#define IMX681_LINK_FREQ 1203000000 +#define IMX681_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10 + +#define IMX681_XCLR_MIN_DELAY_US 6200 +#define IMX681_XCLR_DELAY_RANGE_US 1000 + +static const char * const imx681_supply_name[] = { + "dovdd", /* IO 1.8 V (PM8010 LDO3_M) */ + "avdd", /* analog 2.8 V (PM8550 LDO7_B) */ +}; + +static const s64 imx681_link_freq_menu[] = { + IMX681_LINK_FREQ, +}; + +struct imx681 { + struct device *dev; + struct regmap *regmap; + struct clk *xclk; + struct gpio_desc *reset_gpio; + struct regulator_bulk_data supplies[ARRAY_SIZE(imx681_supply_name)]; + + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *vblank_ctrl; + struct v4l2_ctrl *expo_ctrl; + struct v4l2_ctrl *again_ctrl; + struct v4l2_ctrl *dgain_ctrl; +}; + +static inline struct imx681 *to_imx681(struct v4l2_subdev *sd) +{ + return container_of(sd, struct imx681, sd); +} + +static int imx681_power_on(struct device *dev) +{ + struct v4l2_subdev *sd = dev_get_drvdata(dev); + struct imx681 *sensor = to_imx681(sd); + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(imx681_supply_name), + sensor->supplies); + if (ret) { + dev_err(dev, "failed to enable regulators: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(sensor->xclk); + if (ret) { + dev_err(dev, "failed to enable xclk: %d\n", ret); + goto disable_reg; + } + + gpiod_set_value_cansleep(sensor->reset_gpio, 0); + usleep_range(IMX681_XCLR_MIN_DELAY_US, + IMX681_XCLR_MIN_DELAY_US + IMX681_XCLR_DELAY_RANGE_US); + return 0; + +disable_reg: + regulator_bulk_disable(ARRAY_SIZE(imx681_supply_name), + sensor->supplies); + return ret; +} + +static int imx681_power_off(struct device *dev) +{ + struct v4l2_subdev *sd = dev_get_drvdata(dev); + struct imx681 *sensor = to_imx681(sd); + + gpiod_set_value_cansleep(sensor->reset_gpio, 1); + clk_disable_unprepare(sensor->xclk); + regulator_bulk_disable(ARRAY_SIZE(imx681_supply_name), + sensor->supplies); + return 0; +} + +static int imx681_identify(struct imx681 *sensor) +{ + u64 id = 0; + int ret; + + ret = cci_read(sensor->regmap, IMX681_REG_MODEL_ID, &id, NULL); + if (ret) { + dev_err(sensor->dev, "model ID read failed: %d\n", ret); + return ret; + } + + dev_info(sensor->dev, "detected model id 0x%04llx%s\n", id, + id == IMX681_MODEL_ID ? " (IMX681)" : " (UNEXPECTED)"); + + return id == IMX681_MODEL_ID ? 0 : -ENODEV; +} + +/* ----------------------------------------------------------- controls */ + +static int imx681_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct imx681 *sensor = + container_of(ctrl->handler, struct imx681, ctrl_handler); + int ret = 0; + + if (ctrl->id == V4L2_CID_VBLANK) { + unsigned int expo_max = IMX681_HEIGHT + ctrl->val - + IMX681_EXPOSURE_MARGIN; + + ret = __v4l2_ctrl_modify_range(sensor->expo_ctrl, + sensor->expo_ctrl->minimum, + expo_max, 1, + min_t(int, IMX681_EXPOSURE_DEF, + expo_max)); + if (ret) + return ret; + } + + if (!pm_runtime_get_if_in_use(sensor->dev)) + return 0; + + cci_write(sensor->regmap, IMX681_REG_GROUP_HOLD, 1, &ret); + switch (ctrl->id) { + case V4L2_CID_VBLANK: + cci_write(sensor->regmap, IMX681_REG_FRAME_LENGTH, + IMX681_HEIGHT + ctrl->val, &ret); + break; + case V4L2_CID_EXPOSURE: + cci_write(sensor->regmap, IMX681_REG_EXPOSURE, ctrl->val, + &ret); + break; + case V4L2_CID_ANALOGUE_GAIN: + cci_write(sensor->regmap, IMX681_REG_ANALOG_GAIN, ctrl->val, + &ret); + break; + case V4L2_CID_DIGITAL_GAIN: + cci_write(sensor->regmap, IMX681_REG_DIGITAL_GAIN, ctrl->val, + &ret); + break; + default: + break; + } + cci_write(sensor->regmap, IMX681_REG_GROUP_HOLD, 0, &ret); + + pm_runtime_put_autosuspend(sensor->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops imx681_ctrl_ops = { + .s_ctrl = imx681_s_ctrl, +}; + +static int imx681_init_controls(struct imx681 *sensor) +{ + struct v4l2_ctrl_handler *hdl = &sensor->ctrl_handler; + const struct v4l2_ctrl_ops *ops = &imx681_ctrl_ops; + struct v4l2_fwnode_device_properties props; + struct v4l2_ctrl *ctrl; + int ret; + + ret = v4l2_fwnode_device_parse(sensor->dev, &props); + if (ret) + return ret; + + /* v4l2_fwnode_device_properties can add two more controls. */ + ret = v4l2_ctrl_handler_init(hdl, 10); + if (ret) + return ret; + + ctrl = v4l2_ctrl_new_int_menu(hdl, ops, V4L2_CID_LINK_FREQ, + ARRAY_SIZE(imx681_link_freq_menu) - 1, 0, + imx681_link_freq_menu); + if (ctrl) + ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + ctrl = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE, + IMX681_PIXEL_RATE, IMX681_PIXEL_RATE, 1, + IMX681_PIXEL_RATE); + if (ctrl) + ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + ctrl = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK, + IMX681_LINE_LENGTH - IMX681_WIDTH, + IMX681_LINE_LENGTH - IMX681_WIDTH, 1, + IMX681_LINE_LENGTH - IMX681_WIDTH); + if (ctrl) + ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + sensor->vblank_ctrl = + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK, + IMX681_EXPOSURE_MARGIN, + IMX681_FRAME_LENGTH_MAX - IMX681_HEIGHT, 1, + IMX681_FRAME_LENGTH_DEF - IMX681_HEIGHT); + sensor->expo_ctrl = + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 8, + IMX681_FRAME_LENGTH_DEF - + IMX681_EXPOSURE_MARGIN, 1, + IMX681_EXPOSURE_DEF); + sensor->again_ctrl = + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN, 0, + IMX681_AGAIN_MAX, 1, 0); + sensor->dgain_ctrl = + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_DIGITAL_GAIN, 0x0100, + 0x0fff, 1, IMX681_DGAIN_DEF); + + v4l2_ctrl_new_fwnode_properties(hdl, ops, &props); + + if (hdl->error) { + ret = hdl->error; + v4l2_ctrl_handler_free(hdl); + return ret; + } + + sensor->sd.ctrl_handler = hdl; + return 0; +} + +/* ------------------------------------------------------------- format */ + +static void imx681_fill_fmt(struct v4l2_mbus_framefmt *fmt) +{ + fmt->code = IMX681_MBUS_CODE; + fmt->width = IMX681_WIDTH; + fmt->height = IMX681_HEIGHT; + fmt->field = V4L2_FIELD_NONE; + fmt->colorspace = V4L2_COLORSPACE_RAW; + fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; + fmt->xfer_func = V4L2_XFER_FUNC_NONE; +} + +static int imx681_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index) + return -EINVAL; + code->code = IMX681_MBUS_CODE; + return 0; +} + +static int imx681_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index || fse->code != IMX681_MBUS_CODE) + return -EINVAL; + fse->min_width = IMX681_WIDTH; + fse->max_width = IMX681_WIDTH; + fse->min_height = IMX681_HEIGHT; + fse->max_height = IMX681_HEIGHT; + return 0; +} + +static int imx681_set_pad_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_format *fmt) +{ + imx681_fill_fmt(&fmt->format); + *v4l2_subdev_state_get_format(state, 0) = fmt->format; + return 0; +} + +static int imx681_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_selection *sel) +{ + switch (sel->target) { + case V4L2_SEL_TGT_CROP: + sel->r = *v4l2_subdev_state_get_crop(state, sel->pad); + break; + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + sel->r.left = 0; + sel->r.top = 0; + sel->r.width = IMX681_WIDTH; + sel->r.height = IMX681_HEIGHT; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int imx681_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + imx681_fill_fmt(v4l2_subdev_state_get_format(state, 0)); + *v4l2_subdev_state_get_crop(state, 0) = (struct v4l2_rect) { + .width = IMX681_WIDTH, + .height = IMX681_HEIGHT, + }; + + return 0; +} + +/* ------------------------------------------------------------ streaming */ + +static int imx681_start_streaming(struct imx681 *sensor) +{ + int ret; + + ret = pm_runtime_resume_and_get(sensor->dev); + if (ret < 0) + return ret; + + ret = cci_multi_reg_write(sensor->regmap, imx681_global_init_table, + ARRAY_SIZE(imx681_global_init_table), NULL); + if (!ret) + ret = cci_multi_reg_write(sensor->regmap, + imx681_mode_3840x2640, + ARRAY_SIZE(imx681_mode_3840x2640), + NULL); + if (!ret) + ret = cci_write(sensor->regmap, IMX681_REG_FRAME_LENGTH, + IMX681_HEIGHT + sensor->vblank_ctrl->val, + NULL); + if (ret) + goto err_rpm_put; + + ret = __v4l2_ctrl_handler_setup(&sensor->ctrl_handler); + if (ret) + goto err_rpm_put; + + ret = cci_write(sensor->regmap, IMX681_REG_MODE_SELECT, + IMX681_MODE_STREAMING, NULL); + if (ret) + goto err_rpm_put; + + dev_dbg(sensor->dev, "streaming started\n"); + return 0; + +err_rpm_put: + dev_err(sensor->dev, "failed to start streaming: %d\n", ret); + pm_runtime_put(sensor->dev); + return ret; +} + +static int imx681_stop_streaming(struct imx681 *sensor) +{ + int ret; + + ret = cci_write(sensor->regmap, IMX681_REG_MODE_SELECT, + IMX681_MODE_STANDBY, NULL); + pm_runtime_put_autosuspend(sensor->dev); + return ret; +} + +static int imx681_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct imx681 *sensor = to_imx681(sd); + + return enable ? imx681_start_streaming(sensor) : + imx681_stop_streaming(sensor); +} + +static const struct v4l2_subdev_video_ops imx681_video_ops = { + .s_stream = imx681_s_stream, +}; + +static const struct v4l2_subdev_pad_ops imx681_pad_ops = { + .enum_mbus_code = imx681_enum_mbus_code, + .enum_frame_size = imx681_enum_frame_size, + .get_fmt = v4l2_subdev_get_fmt, + .set_fmt = imx681_set_pad_fmt, + .get_selection = imx681_get_selection, +}; + +static const struct v4l2_subdev_ops imx681_subdev_ops = { + .video = &imx681_video_ops, + .pad = &imx681_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops imx681_internal_ops = { + .init_state = imx681_init_state, +}; + +static int imx681_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct imx681 *sensor; + unsigned int i; + int ret; + + sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + sensor->dev = dev; + + v4l2_i2c_subdev_init(&sensor->sd, client, &imx681_subdev_ops); + sensor->sd.internal_ops = &imx681_internal_ops; + + for (i = 0; i < ARRAY_SIZE(imx681_supply_name); i++) + sensor->supplies[i].supply = imx681_supply_name[i]; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(imx681_supply_name), + sensor->supplies); + if (ret) + return dev_err_probe(dev, ret, "failed to get regulators\n"); + + sensor->xclk = devm_clk_get(dev, NULL); + if (IS_ERR(sensor->xclk)) + return dev_err_probe(dev, PTR_ERR(sensor->xclk), + "failed to get xclk\n"); + + sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(sensor->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(sensor->reset_gpio), + "failed to get reset gpio\n"); + + sensor->regmap = devm_cci_regmap_init_i2c(client, 16); + if (IS_ERR(sensor->regmap)) + return dev_err_probe(dev, PTR_ERR(sensor->regmap), + "failed to init regmap\n"); + + ret = imx681_power_on(dev); + if (ret) + return ret; + + ret = imx681_identify(sensor); + if (ret) + goto err_power_off; + + ret = imx681_init_controls(sensor); + if (ret) + goto err_power_off; + + sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sensor->pad.flags = MEDIA_PAD_FL_SOURCE; + sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad); + if (ret) + goto err_ctrls; + + ret = v4l2_subdev_init_finalize(&sensor->sd); + if (ret) + goto err_entity; + + pm_runtime_set_active(dev); + pm_runtime_get_noresume(dev); + pm_runtime_enable(dev); + pm_runtime_set_autosuspend_delay(dev, 2000); + pm_runtime_use_autosuspend(dev); + + ret = v4l2_async_register_subdev_sensor(&sensor->sd); + if (ret) { + dev_err(dev, "async subdev register failed: %d\n", ret); + goto err_pm; + } + + pm_runtime_put_autosuspend(dev); + return 0; + +err_pm: + pm_runtime_disable(dev); + pm_runtime_put_noidle(dev); + v4l2_subdev_cleanup(&sensor->sd); +err_entity: + media_entity_cleanup(&sensor->sd.entity); +err_ctrls: + v4l2_ctrl_handler_free(&sensor->ctrl_handler); +err_power_off: + imx681_power_off(dev); + return ret; +} + +static void imx681_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx681 *sensor = to_imx681(sd); + + v4l2_async_unregister_subdev(sd); + v4l2_subdev_cleanup(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(&sensor->ctrl_handler); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + imx681_power_off(&client->dev); + pm_runtime_set_suspended(&client->dev); +} + +static const struct dev_pm_ops imx681_pm_ops = { + SET_RUNTIME_PM_OPS(imx681_power_off, imx681_power_on, NULL) +}; + +static const struct of_device_id imx681_dt_ids[] = { + { .compatible = "sony,imx681" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx681_dt_ids); + +static struct i2c_driver imx681_i2c_driver = { + .driver = { + .name = "imx681", + .of_match_table = imx681_dt_ids, + .pm = &imx681_pm_ops, + }, + .probe = imx681_probe, + .remove = imx681_remove, +}; + +module_i2c_driver(imx681_i2c_driver); + +MODULE_DESCRIPTION("Sony IMX681 sensor driver (Surface Pro 11)"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/ov02c10.c b/drivers/media/i2c/ov02c10.c index cf93d36032e147..e8011c8e062484 100644 --- a/drivers/media/i2c/ov02c10.c +++ b/drivers/media/i2c/ov02c10.c @@ -34,6 +34,7 @@ #define OV02C10_EXPOSURE_MIN 4 #define OV02C10_EXPOSURE_MAX_MARGIN 8 #define OV02C10_EXPOSURE_STEP 1 +#define OV02C10_EXPOSURE_DEFAULT 0x046c /* Analog gain controls from sensor */ #define OV02C10_REG_ANALOG_GAIN CCI_REG16(0x3508) @@ -545,7 +546,8 @@ static int ov02c10_init_controls(struct ov02c10 *ov02c10) OV02C10_EXPOSURE_MIN, exposure_max, OV02C10_EXPOSURE_STEP, - exposure_max); + min_t(s64, exposure_max, + OV02C10_EXPOSURE_DEFAULT)); v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0); @@ -755,6 +757,39 @@ static int ov02c10_enum_frame_size(struct v4l2_subdev *sd, return 0; } +static int ov02c10_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_selection *sel) +{ + struct v4l2_rect bounds = { + .left = 0, + .top = 0, + .width = supported_modes[0].width, + .height = supported_modes[0].height, + }; + struct v4l2_rect crop = { + .left = 0, + .top = 0, + .width = supported_modes[0].width, + .height = supported_modes[0].height, + }; + + if (sel->pad != 0) + return -EINVAL; + + switch (sel->target) { + case V4L2_SEL_TGT_CROP: + case V4L2_SEL_TGT_CROP_DEFAULT: + sel->r = crop; + return 0; + case V4L2_SEL_TGT_CROP_BOUNDS: + sel->r = bounds; + return 0; + default: + return -EINVAL; + } +} + static int ov02c10_init_state(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state) { @@ -764,6 +799,35 @@ static int ov02c10_init_state(struct v4l2_subdev *sd, return 0; } +#ifdef CONFIG_VIDEO_ADV_DEBUG +static int ov02c10_get_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) +{ + struct ov02c10 *ov02c10 = to_ov02c10(sd); + int ret; + u64 val; + + if (reg->reg & ~0xffff) + return -EINVAL; + + reg->size = 1; + + ret = cci_read(ov02c10->regmap, CCI_REG8(reg->reg), &val, NULL); + if (ret) + return ret; + + reg->val = (__u64)val; + + return 0; +} +#endif + +static const struct v4l2_subdev_core_ops ov02c10_core_ops = { +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = ov02c10_get_register, +#endif +}; + static const struct v4l2_subdev_video_ops ov02c10_video_ops = { .s_stream = v4l2_subdev_s_stream_helper, }; @@ -773,11 +837,13 @@ static const struct v4l2_subdev_pad_ops ov02c10_pad_ops = { .get_fmt = v4l2_subdev_get_fmt, .enum_mbus_code = ov02c10_enum_mbus_code, .enum_frame_size = ov02c10_enum_frame_size, + .get_selection = ov02c10_get_selection, .enable_streams = ov02c10_enable_streams, .disable_streams = ov02c10_disable_streams, }; static const struct v4l2_subdev_ops ov02c10_subdev_ops = { + .core = &ov02c10_core_ops, .video = &ov02c10_video_ops, .pad = &ov02c10_pad_ops, }; diff --git a/drivers/media/pci/intel/ipu-bridge.c b/drivers/media/pci/intel/ipu-bridge.c index 88581a4c081d6b..897bf1275b8484 100644 --- a/drivers/media/pci/intel/ipu-bridge.c +++ b/drivers/media/pci/intel/ipu-bridge.c @@ -99,6 +99,8 @@ static const struct ipu_sensor_config ipu_supported_sensors[] = { IPU_SENSOR_CONFIG("SONY471A", 1, 200000000), /* Toshiba T4KA3 */ IPU_SENSOR_CONFIG("XMCC0003", 1, 321468000), + /* Sony IMX471 */ + IPU_SENSOR_CONFIG("SONY471A", 1, 200000000), }; /* diff --git a/drivers/media/platform/qcom/camss/Kconfig b/drivers/media/platform/qcom/camss/Kconfig index 4eda48cb1adf04..1edc5e5a1829e0 100644 --- a/drivers/media/platform/qcom/camss/Kconfig +++ b/drivers/media/platform/qcom/camss/Kconfig @@ -7,3 +7,4 @@ config VIDEO_QCOM_CAMSS select VIDEO_V4L2_SUBDEV_API select VIDEOBUF2_DMA_SG select V4L2_FWNODE + select PHY_QCOM_MIPI_CSI2 diff --git a/drivers/media/platform/qcom/camss/camss-csid-680.c b/drivers/media/platform/qcom/camss/camss-csid-680.c index 345a67c8fb947d..edac181505b572 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-680.c +++ b/drivers/media/platform/qcom/camss/camss-csid-680.c @@ -105,6 +105,7 @@ #define CSI2_RX_CFG0_PHY_TYPE_SEL 24 #define CSI2_RX_CFG0_TPG_MUX_EN BIT(27) #define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28) +#define CSI2_RX_CFG0_TPG_NUM_SEL BIT(28) #define CSID_CSI2_RX_CFG1 0x204 #define CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN BIT(0) @@ -160,6 +161,7 @@ #define CSID_RDI_FRM_DROP_PERIOD(rdi) (0x544 + 0x100 * (rdi)) #define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (0x548 + 0x100 * (rdi)) #define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (0x54c + 0x100 * (rdi)) +#define CSID_RDI_RPP_HCROP(rdi) (0x550 + 0x100 * (rdi)) #define CSID_RDI_PIX_DROP_PATTERN(rdi) (0x558 + 0x100 * (rdi)) #define CSID_RDI_PIX_DROP_PERIOD(rdi) (0x55c + 0x100 * (rdi)) #define CSID_RDI_LINE_DROP_PATTERN(rdi) (0x560 + 0x100 * (rdi)) @@ -190,8 +192,17 @@ static void __csid_configure_rx(struct csid_device *csid, struct camss *camss; camss = csid->camss; - val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; - val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + if (phy->bus_type == V4L2_MBUS_CSI2_CPHY) { + /* CSID selects a C-PHY trio by the first wire index divided by two. */ + u8 trio = phy->lane_cnt ? (phy->lane_assign & 0xf) / 2 : 0; + + /* Zero active-lanes encodes one active C-PHY trio. */ + val = trio << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |= BIT(CSI2_RX_CFG0_PHY_TYPE_SEL); + } else { + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + } if (camss->tpg && csid->tpg_linked && camss->tpg[phy->csiphy_id].testgen.mode != TPG_PAYLOAD_MODE_DISABLED) { @@ -200,6 +211,16 @@ static void __csid_configure_rx(struct csid_device *csid, } else { val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0_PHY_NUM_SEL; + + /* + * Same-machine SP11 Windows programs TPG_NUM_SEL=1 for the + * CSIPHY2 one-trio C-PHY receiver while leaving the TPG mux + * disabled. Preserve that otherwise-inert field on X1E80100 so + * the front-camera receiver uses RX_CFG0 == 0x11300000. + */ + if (camss->res->version == CAMSS_X1E80100 && + phy->bus_type == V4L2_MBUS_CSI2_CPHY) + val |= CSI2_RX_CFG0_TPG_NUM_SEL; } writel(val, csid->base + CSID_CSI2_RX_CFG0); @@ -234,9 +255,11 @@ static void __csid_configure_top(struct csid_device *csid) static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc) { struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port]; + struct v4l2_mbus_framefmt *sink_format = &csid->fmt[MSM_CSID_PAD_SINK]; const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats, csid->res->formats->nformats, input_format->code); + bool crop = csid_is_cphy_raw10_3844(csid, sink_format); u8 lane_cnt = csid->phy.lane_cnt; u8 dt_id; u32 val; @@ -244,9 +267,6 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 if (!lane_cnt) lane_cnt = 4; - val = 0; - writel(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(port)); - /* * DT_ID is a two bit bitfield that is concatenated with * the four least significant bits of the five bit VC @@ -260,9 +280,13 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 * CID : VC 3:0 << 2 | DT_ID 1:0 */ dt_id = port & 0x03; + val = 0; - /* note: for non-RDI path, this should be format->decode_format */ - val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + /* Decoding is required for the explicitly selected receiver crop. */ + if (crop) + val |= format->decode_format << RDI_CFG0_DECODE_FORMAT; + else + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; val |= format->data_type << RDI_CFG0_DATA_TYPE; val |= vc << RDI_CFG0_VIRTUAL_CHANNEL; val |= dt_id << RDI_CFG0_DT_ID; @@ -271,14 +295,23 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 val = RDI_CFG1_TIMESTAMP_STB_FRAME; val |= RDI_CFG1_BYTE_CNTR_EN; val |= RDI_CFG1_TIMESTAMP_EN; - val |= RDI_CFG1_DROP_H_EN; - val |= RDI_CFG1_DROP_V_EN; - val |= RDI_CFG1_CROP_H_EN; - val |= RDI_CFG1_CROP_V_EN; val |= RDI_CFG1_PACKING_MIPI; + if (crop) { + /* C-PHY RAW10 3844 is the IMX681 route: crop to 4800-byte rows. */ + writel(3839 << 16, csid->base + CSID_RDI_RPP_HCROP(port)); + val |= RDI_CFG1_CROP_H_EN; + } writel(val, csid->base + CSID_RDI_CFG1(port)); + /* Program an explicit keep-all state for every drop engine. */ + writel(1, csid->base + CSID_RDI_FRM_DROP_PERIOD(port)); + writel(0, csid->base + CSID_RDI_FRM_DROP_PATTERN(port)); + writel(1, csid->base + CSID_RDI_PIX_DROP_PERIOD(port)); + writel(0, csid->base + CSID_RDI_PIX_DROP_PATTERN(port)); + writel(1, csid->base + CSID_RDI_LINE_DROP_PERIOD(port)); + writel(0, csid->base + CSID_RDI_LINE_DROP_PATTERN(port)); + val = 0; writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(port)); @@ -296,6 +329,44 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 writel(val, csid->base + CSID_RDI_CFG0(port)); } +static void csid_log_status(struct csid_device *csid) +{ + struct v4l2_mbus_framefmt *sink_format = + &csid->fmt[MSM_CSID_PAD_SINK]; + int i; + + if (csid->camss->res->version != CAMSS_X1E80100 || + !csid_is_sp11_imx681_format(csid, sink_format)) + return; + + dev_info(csid->camss->dev, + "CSID%u IMX681 stop: RX_CFG0=%#010x RX_CFG1=%#010x TOTAL_PKTS=%u ECC=%u CRC=%u\n", + csid->id, readl(csid->base + CSID_CSI2_RX_CFG0), + readl(csid->base + CSID_CSI2_RX_CFG1), + readl(csid->base + CSID_CSI2_RX_TOTAL_PKTS_RCVD), + readl(csid->base + CSID_CSI2_RX_STATS_ECC), + readl(csid->base + CSID_CSI2_RX_CRC_ERRORS)); + dev_info(csid->camss->dev, + "CSID%u IMX681 IRQ: TOP=%#010x BUF_DONE=%#010x RX=%#010x\n", + csid->id, readl(csid->base + CSID_TOP_IRQ_STATUS), + readl(csid->base + CSID_BUF_DONE_IRQ_STATUS), + readl(csid->base + CSID_CSI2_RX_IRQ_STATUS)); + + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) { + if (!(csid->phy.en_vc & BIT(i))) + continue; + + dev_info(csid->camss->dev, + "CSID%u IMX681 linked RDI%d: IRQ=%#010x CFG0=%#010x CTRL=%#010x CFG1=%#010x HCROP=%#010x\n", + csid->id, i, + readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)), + readl(csid->base + CSID_RDI_CFG0(i)), + readl(csid->base + CSID_RDI_CTRL(i)), + readl(csid->base + CSID_RDI_CFG1(i)), + readl(csid->base + CSID_RDI_RPP_HCROP(i))); + } +} + static void csid_configure_stream(struct csid_device *csid, u8 enable) { int i; @@ -425,6 +496,7 @@ static void csid_subdev_init(struct csid_device *csid) {} const struct csid_hw_ops csid_ops_680 = { .configure_testgen_pattern = NULL, .configure_stream = csid_configure_stream, + .log_status = csid_log_status, .hw_version = csid_hw_version, .isr = csid_isr, .reset = csid_reset, diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index 48459b46a981bc..1388e948adeacd 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -532,6 +532,27 @@ const struct csid_format_info *csid_get_fmt_entry(const struct csid_format_info return &formats[0]; } +bool csid_is_cphy_raw10_3844(struct csid_device *csid, + const struct v4l2_mbus_framefmt *format) +{ + return format->width == 3844 && + csid_is_sp11_imx681_format(csid, format); +} + +bool csid_is_sp11_imx681_format(struct csid_device *csid, + const struct v4l2_mbus_framefmt *format) +{ + const struct csid_format_info *fmt; + + fmt = csid_get_fmt_entry(csid->res->formats->formats, + csid->res->formats->nformats, format->code); + + /* These explicit transport/geometry signatures are unique to the IMX681. */ + return csid->phy.bus_type == V4L2_MBUS_CSI2_CPHY && + (format->width == 3840 || format->width == 3844) && + format->height == 2640 && fmt->data_type == MIPI_CSI2_DT_RAW10; +} + /* * csid_set_clock_rates - Calculate and set clock rates on CSID module * @csiphy: CSID device @@ -557,7 +578,10 @@ static int csid_set_clock_rates(struct csid_device *csid) if (!strcmp(clock->name, "csi0") || !strcmp(clock->name, "csi1") || !strcmp(clock->name, "csi2") || - !strcmp(clock->name, "csi3")) { + !strcmp(clock->name, "csi3") || + (csid->camss->res->version == CAMSS_X1E80100 && + (!strcmp(clock->name, "csid") || + !strcmp(clock->name, "csid_csiphy_rx")))) { u64 min_rate = link_freq / 4; long rate; @@ -777,6 +801,10 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable) return -ENOLINK; } + /* Sample status before pipeline PM turns the CSID clocks off. */ + if (!enable && csid->res->hw_ops->log_status) + csid->res->hw_ops->log_status(csid); + if (csid->phy.need_vc_update) { csid->res->hw_ops->configure_stream(csid, enable); csid->phy.need_vc_update = false; @@ -845,13 +873,17 @@ static void csid_try_format(struct csid_device *csid, case MSM_CSID_PAD_SRC: if (csid->testgen.nmodes == CSID_PAYLOAD_MODE_DISABLED || csid->testgen_mode->cur.val == 0) { - /* Test generator is disabled, */ - /* keep pad formats in sync */ + const struct v4l2_mbus_framefmt *sink_format; u32 code = fmt->code; - *fmt = *__csid_get_format(csid, sd_state, - MSM_CSID_PAD_SINK, which); + /* Test generator is disabled, */ + /* keep pad formats in sync */ + sink_format = __csid_get_format(csid, sd_state, + MSM_CSID_PAD_SINK, which); + *fmt = *sink_format; fmt->code = csid->res->hw_ops->src_pad_code(csid, fmt->code, 0, code); + if (csid_is_cphy_raw10_3844(csid, sink_format)) + fmt->width = 3840; } else { /* Test generator is enabled, set format on source */ /* pad to allow test generator usage */ @@ -1275,6 +1307,7 @@ static int csid_link_setup(struct media_entity *entity, if (sd->grp_id == TPG_GRP_ID) { tpg = v4l2_get_subdevdata(sd); + csid->phy.bus_type = V4L2_MBUS_CSI2_DPHY; csid->phy.lane_cnt = tpg->res->lane_cnt; csid->phy.csiphy_id = tpg->id; csid->phy.lane_assign = csid_get_lane_assign(NULL, csid->phy.lane_cnt); @@ -1288,6 +1321,7 @@ static int csid_link_setup(struct media_entity *entity, return -EPERM; csid->phy.csiphy_id = csiphy->id; + csid->phy.bus_type = csiphy->cfg.csi2->bus_type; lane_cfg = &csiphy->cfg.csi2->lane_cfg; csid->phy.lane_cnt = lane_cfg->num_data; diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index 5296b10f6bac83..7a91ff319ae966 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -65,6 +65,7 @@ struct csid_testgen_config { }; struct csid_phy_config { + enum v4l2_mbus_type bus_type; u8 csiphy_id; u8 lane_cnt; u32 lane_assign; @@ -81,6 +82,12 @@ struct csid_hw_ops { */ void (*configure_stream)(struct csid_device *csid, u8 enable); + /* + * log_status - Log a read-only hardware status snapshot while powered + * @csid: CSID device + */ + void (*log_status)(struct csid_device *csid); + /* * configure_testgen_pattern - Validates and configures output pattern mode * of test pattern generator @@ -196,6 +203,11 @@ const struct csid_format_info *csid_get_fmt_entry(const struct csid_format_info unsigned int nformats, u32 code); +bool csid_is_cphy_raw10_3844(struct csid_device *csid, + const struct v4l2_mbus_framefmt *format); +bool csid_is_sp11_imx681_format(struct csid_device *csid, + const struct v4l2_mbus_framefmt *format); + int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, const struct camss_subdev_resources *res, u8 id); diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c index 539ac4888b608b..88a0e465c5d144 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -131,10 +132,10 @@ static u8 csiphy_get_bpp(const struct csiphy_format_info *formats, } /* - * csiphy_set_clock_rates - Calculate and set clock rates on CSIPHY module + * csiphy_set_clock_rates_legacy - Calculate and set clock rates on CSIPHY module * @csiphy: CSIPHY device */ -static int csiphy_set_clock_rates(struct csiphy_device *csiphy) +static int csiphy_set_clock_rates_legacy(struct csiphy_device *csiphy) { struct device *dev = csiphy->camss->dev; s64 link_freq; @@ -200,7 +201,7 @@ static int csiphy_set_clock_rates(struct csiphy_device *csiphy) * * Return 0 on success or a negative error code otherwise */ -static int csiphy_set_power(struct v4l2_subdev *sd, int on) +static int csiphy_set_power_legacy(struct v4l2_subdev *sd, int on) { struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); struct device *dev = csiphy->camss->dev; @@ -219,7 +220,7 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on) return ret; } - ret = csiphy_set_clock_rates(csiphy); + ret = csiphy_set_clock_rates_legacy(csiphy); if (ret < 0) { regulator_bulk_disable(csiphy->num_supplies, csiphy->supplies); @@ -254,7 +255,7 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on) } /* - * csiphy_stream_on - Enable streaming on CSIPHY module + * csiphy_stream_on_legacy - Enable streaming on CSIPHY module * @csiphy: CSIPHY device * * Helper function to enable streaming on CSIPHY module. @@ -262,7 +263,7 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on) * * Return 0 on success or a negative error code otherwise */ -static int csiphy_stream_on(struct csiphy_device *csiphy) +static int csiphy_stream_on_legacy(struct csiphy_device *csiphy) { struct csiphy_config *cfg = &csiphy->cfg; s64 link_freq; @@ -300,6 +301,93 @@ static int csiphy_stream_on(struct csiphy_device *csiphy) return 0; } +/* + * eam_off - Disable streaming on CSIPHY module + * @csiphy: CSIPHY device + * + * Helper function to disable streaming on CSIPHY module + */ +static void csiphy_stream_off_legacy(struct csiphy_device *csiphy) +{ + csiphy->res->hw_ops->lanes_disable(csiphy, &csiphy->cfg); +} + +/* + * csiphy_stream_on - Enable streaming on CSIPHY module + * @csiphy: CSIPHY device + * + * Helper function to enable streaming on CSIPHY module. + * Main configuration of CSIPHY module is also done here. + * + * Return 0 on success or a negative error code otherwise + */ +static int csiphy_stream_on(struct csiphy_device *csiphy) +{ + u8 bpp = csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->formats->nformats, + csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); + u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; + struct phy_configure_opts_mipi_dphy *dphy_cfg; + union phy_configure_opts dphy_opts = { 0 }; + struct device *dev = csiphy->camss->dev; + bool is_cphy = csiphy->cfg.csi2->bus_type == V4L2_MBUS_CSI2_CPHY; + s64 link_freq; + int ret; + + dphy_cfg = &dphy_opts.mipi_dphy; + + if (is_cphy) + link_freq = camss_get_link_freq(&csiphy->subdev.entity, 0, 0); + else + link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + + if (link_freq < 0) { + dev_err(dev, + "Cannot get CSI2 transmitter's link frequency\n"); + return -EINVAL; + } + + if (is_cphy) { + if (!num_lanes) + return -EINVAL; + + /* + * V4L2 exposes half the C-PHY symbol rate as LINK_FREQ. Until + * generic C-PHY options exist, carry the actual symbol rate to the + * X1E PHY in hs_clk_rate and the physical trio in the PHY submode. + */ + dphy_cfg->hs_clk_rate = link_freq * 2; + dphy_cfg->lanes = num_lanes; + + ret = phy_set_mode_ext(csiphy->phy, PHY_MODE_MIPI_CPHY, + csiphy->cfg.csi2->lane_cfg.data[0].pos); + if (ret) { + dev_err(dev, "failed to set MIPI C-PHY mode\n"); + goto error; + } + + ret = phy_configure(csiphy->phy, &dphy_opts); + if (ret) { + dev_err(dev, "failed to configure MIPI C-PHY\n"); + goto error; + } + } else { + phy_mipi_dphy_get_default_config_for_hsclk(link_freq, num_lanes, dphy_cfg); + + phy_set_mode(csiphy->phy, PHY_MODE_MIPI_DPHY); + + ret = phy_configure(csiphy->phy, &dphy_opts); + if (ret) { + dev_err(dev, "failed to configure MIPI D-PHY\n"); + goto error; + } + } + + return phy_power_on(csiphy->phy); + +error: + return ret; +} + /* * csiphy_stream_off - Disable streaming on CSIPHY module * @csiphy: CSIPHY device @@ -308,9 +396,28 @@ static int csiphy_stream_on(struct csiphy_device *csiphy) */ static void csiphy_stream_off(struct csiphy_device *csiphy) { - csiphy->res->hw_ops->lanes_disable(csiphy, &csiphy->cfg); + phy_power_off(csiphy->phy); } +/* + * csiphy_set_stream - Enable/disable streaming on CSIPHY module + * @sd: CSIPHY V4L2 subdevice + * @enable: Requested streaming state + * + * Return 0 on success or a negative error code otherwise + */ +static int csiphy_set_stream_legacy(struct v4l2_subdev *sd, int enable) +{ + struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); + int ret = 0; + + if (enable) + ret = csiphy_stream_on_legacy(csiphy); + else + csiphy_stream_off_legacy(csiphy); + + return ret; +} /* * csiphy_set_stream - Enable/disable streaming on CSIPHY module @@ -572,16 +679,16 @@ csiphy_match_clock_name(const char *clock_name, const char *format, ...) } /* - * msm_csiphy_subdev_init - Initialize CSIPHY device structure and resources + * msm_csiphy_subdev_init_legacy - Initialize CSIPHY device structure and resources * @csiphy: CSIPHY device * @res: CSIPHY module resources table * @id: CSIPHY module id * * Return 0 on success or a negative error code otherwise */ -int msm_csiphy_subdev_init(struct camss *camss, - struct csiphy_device *csiphy, - const struct camss_subdev_resources *res, u8 id) +int msm_csiphy_subdev_init_legacy(struct camss *camss, + struct csiphy_device *csiphy, + const struct camss_subdev_resources *res, u8 id) { struct device *dev = camss->dev; struct platform_device *pdev = to_platform_device(dev); @@ -709,6 +816,43 @@ int msm_csiphy_subdev_init(struct camss *camss, return ret; } +/* + * msm_csiphy_subdev_init - Initialize CSIPHY device structure and resources + * @csiphy: CSIPHY device + * @res: CSIPHY module resources table + * @id: CSIPHY module id + * + * Return 0 on success or a negative error code otherwise + */ +int msm_csiphy_subdev_init(struct camss *camss, + struct csiphy_device *csiphy, + const struct camss_subdev_resources *res, u8 id) +{ + struct device *dev = camss->dev; + int ret; + + csiphy->camss = camss; + csiphy->id = id; + csiphy->cfg.combo_mode = 0; + csiphy->res = &res->csiphy; + + snprintf(csiphy->name, ARRAY_SIZE(csiphy->name), "csiphy%d", + csiphy->id); + + csiphy->phy = devm_phy_get(dev, csiphy->name); + + if (IS_ERR(csiphy->phy)) { + dev_err(dev, "failed to get phy %s %d\n", csiphy->name, ret); + return PTR_ERR(csiphy->phy); + } + + ret = phy_init(csiphy->phy); + if (ret) + dev_err(dev, "phy %s init fail %d\n", csiphy->name, ret); + + return ret; +} + /* * csiphy_link_setup - Setup CSIPHY connections * @entity: Pointer to media entity structure @@ -743,8 +887,12 @@ static int csiphy_link_setup(struct media_entity *entity, return 0; } -static const struct v4l2_subdev_core_ops csiphy_core_ops = { - .s_power = csiphy_set_power, +static const struct v4l2_subdev_core_ops csiphy_core_ops_legacy = { + .s_power = csiphy_set_power_legacy, +}; + +static const struct v4l2_subdev_video_ops csiphy_video_ops_legacy = { + .s_stream = csiphy_set_stream_legacy, }; static const struct v4l2_subdev_video_ops csiphy_video_ops = { @@ -758,8 +906,13 @@ static const struct v4l2_subdev_pad_ops csiphy_pad_ops = { .set_fmt = csiphy_set_format, }; +static const struct v4l2_subdev_ops csiphy_v4l2_ops_legacy = { + .core = &csiphy_core_ops_legacy, + .video = &csiphy_video_ops_legacy, + .pad = &csiphy_pad_ops, +}; + static const struct v4l2_subdev_ops csiphy_v4l2_ops = { - .core = &csiphy_core_ops, .video = &csiphy_video_ops, .pad = &csiphy_pad_ops, }; @@ -788,7 +941,11 @@ int msm_csiphy_register_entity(struct csiphy_device *csiphy, struct device *dev = csiphy->camss->dev; int ret; - v4l2_subdev_init(sd, &csiphy_v4l2_ops); + if (IS_ERR(csiphy->phy)) + v4l2_subdev_init(sd, &csiphy_v4l2_ops_legacy); + else + v4l2_subdev_init(sd, &csiphy_v4l2_ops); + sd->internal_ops = &csiphy_v4l2_internal_ops; sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h index 9d9657b82f748d..7c29a71b6c7100 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -41,6 +42,7 @@ struct csiphy_lanes_cfg { }; struct csiphy_csi2_cfg { + enum v4l2_mbus_type bus_type; struct csiphy_lanes_cfg lane_cfg; }; @@ -97,6 +99,7 @@ struct csiphy_device_regs { struct csiphy_device { struct camss *camss; + struct phy *phy; u8 id; struct v4l2_subdev subdev; struct media_pad pads[MSM_CSIPHY_PADS_NUM]; @@ -104,6 +107,7 @@ struct csiphy_device { void __iomem *base_clk_mux; u32 irq; char irq_name[30]; + char name[16]; struct camss_clock *clock; bool *rate_set; int nclocks; @@ -118,6 +122,10 @@ struct csiphy_device { struct camss_subdev_resources; +int msm_csiphy_subdev_init_legacy(struct camss *camss, + struct csiphy_device *csiphy, + const struct camss_subdev_resources *res, u8 id); + int msm_csiphy_subdev_init(struct camss *camss, struct csiphy_device *csiphy, const struct camss_subdev_resources *res, u8 id); diff --git a/drivers/media/platform/qcom/camss/camss-vfe-680.c b/drivers/media/platform/qcom/camss/camss-vfe-680.c index 99036e7c1e763a..db1c0e0d296c78 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-680.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-680.c @@ -38,6 +38,7 @@ #define VFE_BUS_WRITE_CLIENT_CFG(vfe, c) ((vfe_is_lite(vfe) ? 0x400 : 0xe00) + (c) * 0x100) #define VFE_BUS_WRITE_CLIENT_CFG_EN BIT(0) +#define VFE_BUS_WRITE_CLIENT_CFG_MODE_MIPI_RAW BIT(16) #define VFE_BUS_IMAGE_ADDR(vfe, c) ((vfe_is_lite(vfe) ? 0x404 : 0xe04) + (c) * 0x100) #define VFE_BUS_FRAME_INCR(vfe, c) ((vfe_is_lite(vfe) ? 0x408 : 0xe08) + (c) * 0x100) #define VFE_BUS_IMAGE_CFG0(vfe, c) ((vfe_is_lite(vfe) ? 0x40c : 0xe0c) + (c) * 0x100) @@ -186,17 +187,57 @@ static void vfe_wm_start(struct vfe_device *vfe, u8 rdi, struct vfe_line *line) vfe_disable_irq(vfe); /* Enable WM */ - writel(VFE_BUS_WRITE_CLIENT_CFG_EN, + writel(VFE_BUS_WRITE_CLIENT_CFG_EN | + VFE_BUS_WRITE_CLIENT_CFG_MODE_MIPI_RAW, vfe->base + VFE_BUS_WRITE_CLIENT_CFG(vfe, wm)); dev_dbg(vfe->camss->dev, "RDI%d WM:%d width %d height %d stride %d\n", rdi, wm, pix->width, pix->height, stride); } +static bool vfe_is_imx681_raw(struct vfe_device *vfe, u8 rdi) +{ + struct v4l2_pix_format_mplane *pix; + + if (vfe->camss->res->version != CAMSS_X1E80100 || + vfe_is_lite(vfe) || rdi >= vfe->res->line_num) + return false; + + pix = &vfe->line[rdi].video_out.active_fmt.fmt.pix_mp; + + return pix->pixelformat == V4L2_PIX_FMT_SRGGB10P && + pix->width == 3840 && pix->height == 2640 && + pix->plane_fmt[0].bytesperline == 4800; +} + static void vfe_wm_stop(struct vfe_device *vfe, u8 rdi) { u8 wm = RDI_WM(rdi); + if (vfe_is_imx681_raw(vfe, rdi)) { + dev_info(vfe->camss->dev, + "VFE%u IMX681 RDI%u WM%u stop: CFG=%#010x ADDR=%#010x INCR=%#010x IMG=%#010x/%#010x/%#010x PACKER=%#010x\n", + vfe->id, rdi, wm, + readl(vfe->base + VFE_BUS_WRITE_CLIENT_CFG(vfe, wm)), + readl(vfe->base + VFE_BUS_IMAGE_ADDR(vfe, wm)), + readl(vfe->base + VFE_BUS_FRAME_INCR(vfe, wm)), + readl(vfe->base + VFE_BUS_IMAGE_CFG0(vfe, wm)), + readl(vfe->base + VFE_BUS_IMAGE_CFG1(vfe, wm)), + readl(vfe->base + VFE_BUS_IMAGE_CFG2(vfe, wm)), + readl(vfe->base + VFE_BUS_PACKER_CFG(vfe, wm))); + dev_info(vfe->camss->dev, + "VFE%u IMX681 IRQ: TOP=%#010x/%#010x BUS=%#010x/%#010x VIOL=%#010x OVERFLOW=%#010x IMAGE_VIOL=%#010x\n", + vfe->id, + readl(vfe->base + VFE_TOP_IRQn_STATUS(vfe, 0)), + readl(vfe->base + VFE_TOP_IRQn_STATUS(vfe, 1)), + readl(vfe->base + VFE_BUS_IRQn_STATUS(vfe, 0)), + readl(vfe->base + VFE_BUS_IRQn_STATUS(vfe, 1)), + readl(vfe->base + VFE_BUS_WR_VIOLATION_STATUS(vfe)), + readl(vfe->base + VFE_BUS_WR_OVERFLOW_STATUS(vfe)), + readl(vfe->base + + VFE_BUS_WR_IMAGE_VIOLATION_STATUS(vfe))); + } + writel(0, vfe->base + VFE_BUS_WRITE_CLIENT_CFG(vfe, wm)); } diff --git a/drivers/media/platform/qcom/camss/camss-video.c b/drivers/media/platform/qcom/camss/camss-video.c index 0852eb6f13154c..7ff03ebb5450db 100644 --- a/drivers/media/platform/qcom/camss/camss-video.c +++ b/drivers/media/platform/qcom/camss/camss-video.c @@ -249,11 +249,43 @@ static int video_prepare_streaming(struct vb2_queue *q) return ret; } +static void video_stop_subdevices(struct camss_video *video, + struct media_entity *last_started) +{ + struct video_device *vdev = &video->vdev; + struct media_entity *entity = &vdev->entity; + struct media_pad *pad; + struct v4l2_subdev *subdev; + int ret; + + while (1) { + pad = &entity->pads[0]; + if (!(pad->flags & MEDIA_PAD_FL_SINK)) + break; + + pad = media_pad_remote_pad_first(pad); + if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) + break; + + entity = pad->entity; + subdev = media_entity_to_v4l2_subdev(entity); + + ret = v4l2_subdev_call(subdev, video, s_stream, 0); + if (ret < 0 && ret != -ENOIOCTLCMD) + dev_err(video->camss->dev, + "Video pipeline stop failed: %d\n", ret); + + if (last_started && entity == last_started) + break; + } +} + static int video_start_streaming(struct vb2_queue *q, unsigned int count) { struct camss_video *video = vb2_get_drv_priv(q); struct video_device *vdev = &video->vdev; struct media_entity *entity; + struct media_entity *last_started = NULL; struct media_pad *pad; struct v4l2_subdev *subdev; int ret; @@ -284,11 +316,15 @@ static int video_start_streaming(struct vb2_queue *q, unsigned int count) ret = v4l2_subdev_call(subdev, video, s_stream, 1); if (ret < 0 && ret != -ENOIOCTLCMD) goto error; + if (ret >= 0) + last_started = entity; } return 0; error: + if (last_started) + video_stop_subdevices(video, last_started); video_device_pipeline_stop(vdev); flush_buffers: @@ -301,31 +337,8 @@ static void video_stop_streaming(struct vb2_queue *q) { struct camss_video *video = vb2_get_drv_priv(q); struct video_device *vdev = &video->vdev; - struct media_entity *entity; - struct media_pad *pad; - struct v4l2_subdev *subdev; - int ret; - - entity = &vdev->entity; - while (1) { - pad = &entity->pads[0]; - if (!(pad->flags & MEDIA_PAD_FL_SINK)) - break; - pad = media_pad_remote_pad_first(pad); - if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) - break; - - entity = pad->entity; - subdev = media_entity_to_v4l2_subdev(entity); - - ret = v4l2_subdev_call(subdev, video, s_stream, 0); - - if (ret) { - dev_err(video->camss->dev, "Video pipeline stop failed: %d\n", ret); - return; - } - } + video_stop_subdevices(video, NULL); video_device_pipeline_stop(vdev); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 2123f6388e3d7e..6386eb4080d840 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4190,15 +4190,6 @@ static const struct resources_icc icc_res_sa8775p[] = { static const struct camss_subdev_resources csiphy_res_x1e80100[] = { /* CSIPHY0 */ { - .regulators = { - { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, - { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } - }, - .clock = { "csiphy0", "csiphy0_timer" }, - .clock_rate = { { 300000000, 400000000, 480000000 }, - { 266666667, 400000000 } }, - .reg = { "csiphy0" }, - .interrupt = { "csiphy0" }, .csiphy = { .id = 0, .hw_ops = &csiphy_ops_3ph_1_0, @@ -4207,15 +4198,6 @@ static const struct camss_subdev_resources csiphy_res_x1e80100[] = { }, /* CSIPHY1 */ { - .regulators = { - { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, - { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } - }, - .clock = { "csiphy1", "csiphy1_timer" }, - .clock_rate = { { 300000000, 400000000, 480000000 }, - { 266666667, 400000000 } }, - .reg = { "csiphy1" }, - .interrupt = { "csiphy1" }, .csiphy = { .id = 1, .hw_ops = &csiphy_ops_3ph_1_0, @@ -4224,15 +4206,6 @@ static const struct camss_subdev_resources csiphy_res_x1e80100[] = { }, /* CSIPHY2 */ { - .regulators = { - { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, - { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } - }, - .clock = { "csiphy2", "csiphy2_timer" }, - .clock_rate = { { 300000000, 400000000, 480000000 }, - { 266666667, 400000000 } }, - .reg = { "csiphy2" }, - .interrupt = { "csiphy2" }, .csiphy = { .id = 2, .hw_ops = &csiphy_ops_3ph_1_0, @@ -4241,15 +4214,6 @@ static const struct camss_subdev_resources csiphy_res_x1e80100[] = { }, /* CSIPHY4 */ { - .regulators = { - { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, - { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } - }, - .clock = { "csiphy4", "csiphy4_timer" }, - .clock_rate = { { 300000000, 400000000, 480000000 }, - { 266666667, 400000000 } }, - .reg = { "csiphy4" }, - .interrupt = { "csiphy4" }, .csiphy = { .id = 4, .hw_ops = &csiphy_ops_3ph_1_0, @@ -4605,6 +4569,14 @@ struct media_pad *camss_find_sensor_pad(struct media_entity *entity) while (1) { pad = &entity->pads[0]; + + /* + * Work around unresolved bug in camss (or v4l2) which can + * result in pad being NULL here. + */ + if (WARN_ON(!pad)) + return NULL; + if (!(pad->flags & MEDIA_PAD_FL_SINK)) return NULL; @@ -4620,7 +4592,7 @@ struct media_pad *camss_find_sensor_pad(struct media_entity *entity) } /** - * camss_get_link_freq - Get link frequency from sensor + * camss_get_link_freq - Get link frequency from the upstream transmitter * @entity: Media entity in the current pipeline * @bpp: Number of bits per pixel for the current format * @lanes: Number of lanes in the link to the sensor @@ -4630,13 +4602,38 @@ struct media_pad *camss_find_sensor_pad(struct media_entity *entity) s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, unsigned int lanes) { - struct media_pad *sensor_pad; + struct media_pad *sink_pad; + struct media_pad *source_pad; + s64 link_freq; - sensor_pad = camss_find_sensor_pad(entity); - if (!sensor_pad) - return -ENODEV; + /* + * A sensor can expose multiple subdevices between its pixel array and + * the receiver. The link-frequency control belongs to the subdevice + * driving the physical link (for example a CCS scaler), not necessarily + * to the entity classified as MEDIA_ENT_F_CAM_SENSOR. Walk upstream and + * use the first transmitter source pad that advertises the frequency. + */ + while (1) { + if (WARN_ON(!entity->pads || !entity->num_pads)) + return -ENODEV; + + sink_pad = &entity->pads[0]; + if (!(sink_pad->flags & MEDIA_PAD_FL_SINK)) + return -ENODEV; + + source_pad = media_pad_remote_pad_first(sink_pad); + if (!source_pad || + !is_media_entity_v4l2_subdev(source_pad->entity)) + return -ENODEV; + + link_freq = v4l2_get_link_freq(source_pad, bpp, 2 * lanes); + if (link_freq != -ENOENT) + return link_freq; - return v4l2_get_link_freq(sensor_pad, bpp, 2 * lanes); + entity = source_pad->entity; + if (entity->function == MEDIA_ENT_F_CAM_SENSOR) + return -ENODEV; + } } /* @@ -4746,7 +4743,10 @@ static int camss_parse_endpoint_node(struct device *dev, { struct csiphy_lanes_cfg *lncfg = &csd->interface.csi2.lane_cfg; struct v4l2_mbus_config_mipi_csi2 *mipi_csi2; + struct v4l2_fwnode_endpoint remote_vep = { { 0 } }; struct v4l2_fwnode_endpoint vep = { { 0 } }; + struct fwnode_handle *remote_ep; + enum v4l2_mbus_type bus_type; unsigned int i; int ret; @@ -4754,20 +4754,33 @@ static int camss_parse_endpoint_node(struct device *dev, if (ret) return ret; - /* - * Most SoCs support both D-PHY and C-PHY standards, but currently only - * D-PHY is supported in the driver. - */ - if (vep.bus_type != V4L2_MBUS_CSI2_DPHY) { - dev_err(dev, "Unsupported bus type %d\n", vep.bus_type); + remote_ep = fwnode_graph_get_remote_endpoint(ep); + if (!remote_ep) + return -ENOTCONN; + + ret = v4l2_fwnode_endpoint_parse(remote_ep, &remote_vep); + fwnode_handle_put(remote_ep); + if (ret) + return ret; + + /* The transmitter endpoint is authoritative for the CSI-2 PHY type. */ + bus_type = remote_vep.bus_type == V4L2_MBUS_UNKNOWN ? + vep.bus_type : remote_vep.bus_type; + if (bus_type != V4L2_MBUS_CSI2_DPHY && + bus_type != V4L2_MBUS_CSI2_CPHY) { + dev_err(dev, "Unsupported bus type %d\n", bus_type); return -EINVAL; } csd->interface.csiphy_id = vep.base.port; + csd->interface.csi2.bus_type = bus_type; mipi_csi2 = &vep.bus.mipi_csi2; - lncfg->clk.pos = mipi_csi2->clock_lane; - lncfg->clk.pol = mipi_csi2->lane_polarities[0]; + if (bus_type == V4L2_MBUS_CSI2_DPHY) { + lncfg->clk.pos = mipi_csi2->clock_lane; + lncfg->clk.pol = mipi_csi2->lane_polarities[0]; + } + lncfg->num_data = mipi_csi2->num_data_lanes; lncfg->data = devm_kcalloc(dev, @@ -4829,18 +4842,40 @@ static int camss_init_subdevices(struct camss *camss) { struct platform_device *pdev = to_platform_device(camss->dev); const struct camss_resources *res = camss->res; + struct device_node *phy_np; unsigned int i; int ret; for (i = 0; i < camss->res->csiphy_num; i++) { - ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i], - &res->csiphy_res[i], - res->csiphy_res[i].csiphy.id); - if (ret < 0) { - dev_err(camss->dev, - "Failed to init csiphy%d sub-device: %d\n", - i, ret); - return ret; + phy_np = of_parse_phandle(pdev->dev.of_node, "phys", i); + if (phy_np && of_device_is_available(phy_np)) { + ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i], + &res->csiphy_res[i], + res->csiphy_res[i].csiphy.id); + if (ret < 0) { + dev_err(camss->dev, + "Failed to init csiphy%d sub-device: %d\n", + i, ret); + return ret; + } + } + } + + if (!phy_np) { + if (!res->legacy_phy) + return -ENODEV; + + for (i = 0; i < camss->res->csiphy_num; i++) { + ret = msm_csiphy_subdev_init_legacy(camss, &camss->csiphy[i], + &res->csiphy_res[i], + res->csiphy_res[i].csiphy.id); + if (ret < 0) { + dev_err(camss->dev, + "Failed to init csiphy%d sub-device: %d\n", + i, ret); + return ret; + } + camss->csiphy[i].phy = ERR_PTR(-ENODEV); } } @@ -4930,6 +4965,9 @@ static int camss_link_entities(struct camss *camss) for (i = 0; i < camss->res->csiphy_num; i++) { for (j = 0; j < camss->res->csid_num; j++) { + if (!camss->csiphy[i].phy) + continue; + ret = media_create_pad_link(&camss->csiphy[i].subdev.entity, MSM_CSIPHY_PAD_SRC, &camss->csid[j].subdev.entity, @@ -5056,6 +5094,9 @@ static int camss_register_entities(struct camss *camss) int ret; for (i = 0; i < camss->res->csiphy_num; i++) { + if (!camss->csiphy[i].phy) + continue; + ret = msm_csiphy_register_entity(&camss->csiphy[i], &camss->v4l2_dev); if (ret < 0) { @@ -5131,8 +5172,10 @@ static int camss_register_entities(struct camss *camss) i = camss->res->csiphy_num; err_reg_csiphy: - for (i--; i >= 0; i--) - msm_csiphy_unregister_entity(&camss->csiphy[i]); + for (i--; i >= 0; i--) { + if (camss->csiphy[i].phy) + msm_csiphy_unregister_entity(&camss->csiphy[i]); + } return ret; } @@ -5147,8 +5190,10 @@ static void camss_unregister_entities(struct camss *camss) { unsigned int i; - for (i = 0; i < camss->res->csiphy_num; i++) - msm_csiphy_unregister_entity(&camss->csiphy[i]); + for (i = 0; i < camss->res->csiphy_num; i++) { + if (camss->csiphy[i].phy) + msm_csiphy_unregister_entity(&camss->csiphy[i]); + } if (camss->tpg) { for (i = 0; i < camss->res->tpg_num; i++) @@ -5509,6 +5554,7 @@ static void camss_remove(struct platform_device *pdev) static const struct camss_resources msm8916_resources = { .version = CAMSS_8x16, + .legacy_phy = true, .csiphy_res = csiphy_res_8x16, .csid_res = csid_res_8x16, .ispif_res = &ispif_res_8x16, @@ -5531,6 +5577,7 @@ static const struct camss_resources msm8939_resources = { static const struct camss_resources msm8953_resources = { .version = CAMSS_8x53, + .legacy_phy = true, .icc_res = icc_res_8x53, .icc_path_num = ARRAY_SIZE(icc_res_8x53), .csiphy_res = csiphy_res_8x96, @@ -5544,6 +5591,7 @@ static const struct camss_resources msm8953_resources = { static const struct camss_resources msm8996_resources = { .version = CAMSS_8x96, + .legacy_phy = true, .csiphy_res = csiphy_res_8x96, .csid_res = csid_res_8x96, .ispif_res = &ispif_res_8x96, @@ -5599,6 +5647,7 @@ static const struct camss_resources sa8775p_resources = { static const struct camss_resources sdm660_resources = { .version = CAMSS_660, + .legacy_phy = true, .csiphy_res = csiphy_res_660, .csid_res = csid_res_660, .ispif_res = &ispif_res_660, @@ -5610,6 +5659,7 @@ static const struct camss_resources sdm660_resources = { static const struct camss_resources sdm670_resources = { .version = CAMSS_845, + .legacy_phy = true, .csiphy_res = csiphy_res_670, .csid_res = csid_res_670, .vfe_res = vfe_res_670, @@ -5621,6 +5671,7 @@ static const struct camss_resources sdm670_resources = { static const struct camss_resources sdm845_resources = { .version = CAMSS_845, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_845, .csid_res = csid_res_845, .vfe_res = vfe_res_845, @@ -5658,6 +5709,7 @@ static const struct camss_resources sm6350_resources = { static const struct camss_resources sm8250_resources = { .version = CAMSS_8250, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_8250, .csid_res = csid_res_8250, .vfe_res = vfe_res_8250, @@ -5671,6 +5723,7 @@ static const struct camss_resources sm8250_resources = { static const struct camss_resources sc8280xp_resources = { .version = CAMSS_8280XP, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_sc8280xp, .csid_res = csid_res_sc8280xp, .ispif_res = NULL, @@ -5685,6 +5738,7 @@ static const struct camss_resources sc8280xp_resources = { static const struct camss_resources sc7280_resources = { .version = CAMSS_7280, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_7280, .csid_res = csid_res_7280, .vfe_res = vfe_res_7280, @@ -5698,6 +5752,7 @@ static const struct camss_resources sc7280_resources = { static const struct camss_resources sm8550_resources = { .version = CAMSS_8550, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_8550, .csid_res = csid_res_8550, .vfe_res = vfe_res_8550, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 93d691c8ac63b2..698694d3064eac 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -107,6 +107,7 @@ enum icc_count { struct camss_resources { enum camss_version version; const char *pd_name; + const bool legacy_phy; const struct camss_subdev_resources *csiphy_res; const struct camss_subdev_resources *tpg_res; const struct camss_subdev_resources *csid_res; diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 24da60448cf248..b878da43f91d62 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -123,6 +123,12 @@ struct iris_core { /* encoder and decoder have overlapping caps, so two different arrays are required */ struct platform_inst_fw_cap inst_fw_caps_dec[INST_FW_CAP_MAX]; struct platform_inst_fw_cap inst_fw_caps_enc[INST_FW_CAP_MAX]; + bool use_tz; + struct video_firmware { + struct platform_device *pdev; + struct iommu_domain *iommu_domain; + size_t mapped_mem_size; + } fw; }; int iris_core_init(struct iris_core *core); diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index 1a476146d75808..79f88f24f84293 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -5,16 +5,57 @@ #include #include +#include #include +#include #include #include #include "iris_core.h" #include "iris_firmware.h" -#define IRIS_PAS_ID 9 +#define IRIS_PAS_ID 9 -#define MAX_FIRMWARE_NAME_SIZE 128 +#define MAX_FIRMWARE_NAME_SIZE 128 + +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 + +#define WRAPPER_TZ_XTSS_SW_RESET (WRAPPER_TZ_BASE_OFFS + 0x1000) +#define WRAPPER_XTSS_SW_RESET_BIT BIT(0) + +#define WRAPPER_CPA_START_ADDR (WRAPPER_TZ_BASE_OFFS + 0x1020) +#define WRAPPER_CPA_END_ADDR (WRAPPER_TZ_BASE_OFFS + 0x1024) +#define WRAPPER_FW_START_ADDR (WRAPPER_TZ_BASE_OFFS + 0x1028) +#define WRAPPER_FW_END_ADDR (WRAPPER_TZ_BASE_OFFS + 0x102C) +#define WRAPPER_NONPIX_START_ADDR (WRAPPER_TZ_BASE_OFFS + 0x1030) +#define WRAPPER_NONPIX_END_ADDR (WRAPPER_TZ_BASE_OFFS + 0x1034) + +#define IRIS_FW_START_ADDR 0x0 + +static void iris_reset_cpu_no_tz(struct iris_core *core) +{ + u32 fw_size = core->fw.mapped_mem_size; + + writel(0, core->reg_base + WRAPPER_FW_START_ADDR); + writel(fw_size, core->reg_base + WRAPPER_FW_END_ADDR); + writel(0, core->reg_base + WRAPPER_CPA_START_ADDR); + writel(fw_size, core->reg_base + WRAPPER_CPA_END_ADDR); + writel(fw_size, core->reg_base + WRAPPER_NONPIX_START_ADDR); + writel(fw_size, core->reg_base + WRAPPER_NONPIX_END_ADDR); + + /* Bring XTSS out of reset */ + writel(0, core->reg_base + WRAPPER_TZ_XTSS_SW_RESET); +} + +static int iris_set_hw_state_no_tz(struct iris_core *core, bool resume) +{ + if (resume) + iris_reset_cpu_no_tz(core); + else + writel(WRAPPER_XTSS_SW_RESET_BIT, core->reg_base + WRAPPER_TZ_XTSS_SW_RESET); + + return 0; +} static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) { @@ -53,10 +94,29 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) goto err_release_fw; } - ret = qcom_mdt_load(dev, firmware, fw_name, - IRIS_PAS_ID, mem_virt, mem_phys, res_size, NULL); + if (core->use_tz) + ret = qcom_mdt_load(dev, firmware, fw_name, + IRIS_PAS_ID, mem_virt, mem_phys, res_size, NULL); + else + ret = qcom_mdt_load_no_init(dev, firmware, fw_name, + mem_virt, mem_phys, res_size, NULL); + /* Unmap memory on our side before we give firmware access to it */ memunmap(mem_virt); + if (ret) + goto err_release_fw; + + if (core->fw.iommu_domain) { + ret = iommu_map(core->fw.iommu_domain, IRIS_FW_START_ADDR, mem_phys, res_size, + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); + if (ret) { + dev_err(core->dev, "failed to map firmware in IOMMU: %d\n", ret); + goto err_release_fw; + } + + core->fw.mapped_mem_size = res_size; + } + err_release_fw: release_firmware(firmware); @@ -80,23 +140,27 @@ int iris_fw_load(struct iris_core *core) return -ENOMEM; } - ret = qcom_scm_pas_auth_and_reset(IRIS_PAS_ID); - if (ret) { - dev_err(core->dev, "auth and reset failed: %d\n", ret); - return ret; - } - - for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) { - cp_config = &core->iris_platform_data->tz_cp_config_data[i]; - ret = qcom_scm_mem_protect_video_var(cp_config->cp_start, - cp_config->cp_size, - cp_config->cp_nonpixel_start, - cp_config->cp_nonpixel_size); - if (ret) { - dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); - qcom_scm_pas_shutdown(IRIS_PAS_ID); + if (core->use_tz) { + ret = qcom_scm_pas_auth_and_reset(IRIS_PAS_ID); + if (ret) { + dev_err(core->dev, "auth and reset failed: %d\n", ret); return ret; } + + for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) { + cp_config = &core->iris_platform_data->tz_cp_config_data[i]; + ret = qcom_scm_mem_protect_video_var(cp_config->cp_start, + cp_config->cp_size, + cp_config->cp_nonpixel_start, + cp_config->cp_nonpixel_size); + if (ret) { + dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); + qcom_scm_pas_shutdown(IRIS_PAS_ID); + return ret; + } + } + } else { + iris_reset_cpu_no_tz(core); } return ret; @@ -104,10 +168,98 @@ int iris_fw_load(struct iris_core *core) int iris_fw_unload(struct iris_core *core) { - return qcom_scm_pas_shutdown(IRIS_PAS_ID); + int ret; + + if (core->use_tz) + ret = qcom_scm_pas_shutdown(IRIS_PAS_ID); + else + ret = iris_set_hw_state_no_tz(core, false); + + if (core->fw.mapped_mem_size) { + size_t unmapped = iommu_unmap(core->fw.iommu_domain, IRIS_FW_START_ADDR, + core->fw.mapped_mem_size); + + if (unmapped != core->fw.mapped_mem_size) + dev_err(core->dev, "failed to unmap firmware in IOMMU\n"); + + core->fw.mapped_mem_size = 0; + } + + return ret; } int iris_set_hw_state(struct iris_core *core, bool resume) { - return qcom_scm_set_remote_state(resume, 0); + if (core->use_tz) + return qcom_scm_set_remote_state(resume, 0); + else + return iris_set_hw_state_no_tz(core, resume); +} + +int iris_fw_init(struct iris_core *core) +{ + struct iommu_domain *iommu_domain; + struct platform_device_info info; + struct platform_device *pdev; + struct device_node *np; + int ret; + + np = of_get_child_by_name(core->dev->of_node, "video-firmware"); + if (!np) { + core->use_tz = true; + return 0; + } + + memset(&info, 0, sizeof(info)); + info.parent = core->dev; + info.fwnode = &np->fwnode; + info.name = np->name; + info.dma_mask = DMA_BIT_MASK(32); + + pdev = platform_device_register_full(&info); + if (IS_ERR(pdev)) { + of_node_put(np); + return PTR_ERR(pdev); + } + + ret = of_dma_configure(&pdev->dev, np, true); + of_node_put(np); + if (ret) { + dev_err(&pdev->dev, "failed to configure dma: %d\n", ret); + goto err_unregister; + } + + iommu_domain = iommu_paging_domain_alloc(&pdev->dev); + if (IS_ERR(iommu_domain)) { + dev_err(&pdev->dev, "failed to allocate iommu domain: %pe\n", iommu_domain); + ret = PTR_ERR(iommu_domain); + goto err_unregister; + } + + ret = iommu_attach_device(iommu_domain, &pdev->dev); + if (ret) { + dev_err(&pdev->dev, "could not attach device to IOMMU: %d\n", ret); + goto err_iommu_free; + } + + core->fw.pdev = pdev; + core->fw.iommu_domain = iommu_domain; + + return 0; + +err_iommu_free: + iommu_domain_free(iommu_domain); +err_unregister: + platform_device_unregister(pdev); + return ret; +} + +void iris_fw_deinit(struct iris_core *core) +{ + if (!core->fw.iommu_domain) + return; + + iommu_detach_device(core->fw.iommu_domain, &core->fw.pdev->dev); + iommu_domain_free(core->fw.iommu_domain); + platform_device_unregister(core->fw.pdev); } diff --git a/drivers/media/platform/qcom/iris/iris_firmware.h b/drivers/media/platform/qcom/iris/iris_firmware.h index e833ecd3488716..1a077a587c8059 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.h +++ b/drivers/media/platform/qcom/iris/iris_firmware.h @@ -12,4 +12,7 @@ int iris_fw_load(struct iris_core *core); int iris_fw_unload(struct iris_core *core); int iris_set_hw_state(struct iris_core *core, bool resume); +int iris_fw_init(struct iris_core *core); +void iris_fw_deinit(struct iris_core *core); + #endif diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index c2dcb50a27824d..38556d2dd53c46 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -14,6 +14,7 @@ #include "iris_core.h" #include "iris_ctrls.h" +#include "iris_firmware.h" #include "iris_vidc.h" static int iris_init_icc(struct iris_core *core) @@ -207,6 +208,8 @@ static void iris_remove(struct platform_device *pdev) v4l2_device_unregister(&core->v4l2_dev); + iris_fw_deinit(core); + mutex_destroy(&core->lock); } @@ -271,6 +274,10 @@ static int iris_probe(struct platform_device *pdev) if (ret) return ret; + ret = iris_fw_init(core); + if (ret) + return ret; + iris_session_init_caps(core); ret = v4l2_device_register(dev, &core->v4l2_dev); diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c index 243e342b0ae753..cdcd5039270914 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -401,6 +401,15 @@ static int venus_probe(struct platform_device *pdev) if (IS_ERR(core->cpucfg_path)) return PTR_ERR(core->cpucfg_path); + core->llcc_path = devm_of_icc_get(dev, "video-llcc"); + if (IS_ERR(core->llcc_path)) { + /* LLCC path is optional */ + if (PTR_ERR(core->llcc_path) == -ENODATA) + core->llcc_path = NULL; + else + return PTR_ERR(core->llcc_path); + } + core->irq = platform_get_irq(pdev, 0); if (core->irq < 0) return core->irq; @@ -597,12 +606,18 @@ static __maybe_unused int venus_runtime_suspend(struct device *dev) if (ret) goto err_cpucfg_path; + ret = icc_set_bw(core->llcc_path, 0, 0); + if (ret) + goto err_llcc_path; + ret = icc_set_bw(core->video_path, 0, 0); if (ret) goto err_video_path; return ret; +err_llcc_path: + icc_set_bw(core->video_path, kbps_to_icc(20000), 0); err_video_path: icc_set_bw(core->cpucfg_path, kbps_to_icc(1000), 0); err_cpucfg_path: @@ -642,6 +657,10 @@ static __maybe_unused int venus_runtime_resume(struct device *dev) if (ret) return ret; + ret = icc_set_bw(core->llcc_path, kbps_to_icc(20000), 0); + if (ret) + return ret; + ret = icc_set_bw(core->cpucfg_path, kbps_to_icc(1000), 0); if (ret) return ret; @@ -1054,6 +1073,46 @@ static const struct venus_resources sm8250_res = { .enc_nodename = "video-encoder", }; +static const struct reg_val sm8350_reg_preset[] = { + { 0xb0088, 0, 0x11 }, +}; + +static const struct venus_resources sm8350_res = { + .freq_tbl = sm8250_freq_table, + .freq_tbl_size = ARRAY_SIZE(sm8250_freq_table), + .reg_tbl = sm8350_reg_preset, + .reg_tbl_size = ARRAY_SIZE(sm8350_reg_preset), + .bw_tbl_enc = sm8250_bw_table_enc, + .bw_tbl_enc_size = ARRAY_SIZE(sm8250_bw_table_enc), + .bw_tbl_dec = sm8250_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), + .clks = { "core", "iface" }, + .clks_num = 2, + .resets = { "core" }, + .resets_num = 1, + .vcodec0_clks = { "vcodec0_core" }, + .vcodec_clks_num = 1, + .vcodec_pmdomains = (const char *[]) { "venus", "vcodec0" }, + .vcodec_pmdomains_num = 2, + .opp_pmdomain = (const char *[]) { "mx", NULL }, + .vcodec_num = 1, + .max_load = 7833600, /* 7680x4320@60fps */ + .hfi_version = HFI_VERSION_6XX, + .vpu_version = VPU_VERSION_IRIS2, + .num_vpp_pipes = 4, + .vmem_id = VIDC_RESOURCE_NONE, + .vmem_size = 0, + .vmem_addr = 0, + .dma_mask = GENMASK(31, 29) - 1, + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x1000000, + .cp_nonpixel_size = 0x24800000, + .fwname = "qcom/vpu-2.0/venus.mbn", + .dec_nodename = "video-decoder", + .enc_nodename = "video-encoder", +}; + static const struct freq_tbl sc7280_freq_table[] = { { 0, 460000000 }, { 0, 424000000 }, @@ -1170,19 +1229,70 @@ static const struct venus_resources qcm2290_res = { .min_fw = &min_fw, }; +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) + +static const struct freq_tbl sc8280xp_freq_table[] = { + { 0, 239999999 }, + { 0, 338000000 }, + { 0, 366000000 }, + { 0, 444000000 }, + { 0, 533000000 }, + { 0, 560000000 }, +}; + +static const struct venus_resources sc8280xp_res = { + .freq_tbl = sc8280xp_freq_table, + .freq_tbl_size = ARRAY_SIZE(sc8280xp_freq_table), + .reg_tbl = sm8350_reg_preset, + .reg_tbl_size = ARRAY_SIZE(sm8350_reg_preset), + .bw_tbl_enc = sm8250_bw_table_enc, + .bw_tbl_enc_size = ARRAY_SIZE(sm8250_bw_table_enc), + .bw_tbl_dec = sm8250_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), + .clks = { "core", "iface" }, + .clks_num = 2, + .resets = { "core" }, + .resets_num = 1, + .vcodec0_clks = { "vcodec0_core" }, + .vcodec_clks_num = 1, + .vcodec_pmdomains = (const char *[]) { "venus", "vcodec0" }, + .vcodec_pmdomains_num = 2, + .opp_pmdomain = (const char *[]) { "mx", NULL }, + .vcodec_num = 1, + .max_load = 7833600, /* 7680x4320@60fps */ + .hfi_version = HFI_VERSION_6XX, + .vpu_version = VPU_VERSION_IRIS2, + .num_vpp_pipes = 4, + .vmem_id = VIDC_RESOURCE_NONE, + .vmem_size = 0, + .vmem_addr = 0, + .dma_mask = GENMASK(31, 29) - 1, + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x1000000, + .cp_nonpixel_size = 0x24800000, + .fwname = "qcom/vpu-2.0/venus.mbn", + .dec_nodename = "video-decoder", + .enc_nodename = "video-encoder", +}; + +#endif /* !CONFIG_VIDEO_QCOM_IRIS */ + static const struct of_device_id venus_dt_match[] = { - { .compatible = "qcom,msm8916-venus", .data = &msm8916_res, }, - { .compatible = "qcom,msm8939-venus", .data = &msm8939_res, }, - { .compatible = "qcom,msm8996-venus", .data = &msm8996_res, }, - { .compatible = "qcom,msm8998-venus", .data = &msm8998_res, }, - { .compatible = "qcom,qcm2290-venus", .data = &qcm2290_res, }, - { .compatible = "qcom,sc7180-venus", .data = &sc7180_res, }, - { .compatible = "qcom,sdm660-venus", .data = &sdm660_res, }, - { .compatible = "qcom,sdm845-venus", .data = &sdm845_res, }, - { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2, }, + { .compatible = "qcom,msm8916-venus", .data = &msm8916_res }, + { .compatible = "qcom,msm8939-venus", .data = &msm8939_res }, + { .compatible = "qcom,msm8996-venus", .data = &msm8996_res }, + { .compatible = "qcom,msm8998-venus", .data = &msm8998_res }, + { .compatible = "qcom,qcm2290-venus", .data = &qcm2290_res }, + { .compatible = "qcom,sc7180-venus", .data = &sc7180_res }, + { .compatible = "qcom,sdm660-venus", .data = &sdm660_res }, + { .compatible = "qcom,sdm845-venus", .data = &sdm845_res }, + { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2 }, #if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) - { .compatible = "qcom,sc7280-venus", .data = &sc7280_res, }, - { .compatible = "qcom,sm8250-venus", .data = &sm8250_res, }, + { .compatible = "qcom,sc7280-venus", .data = &sc7280_res }, + { .compatible = "qcom,sm8250-venus", .data = &sm8250_res }, + { .compatible = "qcom,sm8350-venus", .data = &sm8350_res }, + { .compatible = "qcom,sc8280xp-venus", .data = &sc8280xp_res }, #endif { } }; diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h index 46705a6667762e..da4a18eb0474e0 100644 --- a/drivers/media/platform/qcom/venus/core.h +++ b/drivers/media/platform/qcom/venus/core.h @@ -40,6 +40,7 @@ struct freq_tbl { struct reg_val { u32 reg; u32 value; + u32 mask; }; struct bw_tbl { @@ -74,6 +75,7 @@ struct venus_resources { unsigned int bw_tbl_enc_size; const struct bw_tbl *bw_tbl_dec; unsigned int bw_tbl_dec_size; + bool has_llcc_path; const struct reg_val *reg_tbl; unsigned int reg_tbl_size; const struct hfi_ubwc_config *ubwc_conf; @@ -151,6 +153,7 @@ struct venus_format { * @vcodec1_clks: an array of vcodec1 struct clk pointers * @video_path: an interconnect handle to video to/from memory path * @cpucfg_path: an interconnect handle to cpu configuration path + * @llcc_path: an interconnect handle to video to/from llcc path * @pmdomains: a pointer to a list of pmdomains * @opp_pmdomain: an OPP power-domain * @resets: an array of reset signals @@ -206,6 +209,7 @@ struct venus_core { struct clk *vcodec1_clks[VIDC_VCODEC_CLKS_NUM_MAX]; struct icc_path *video_path; struct icc_path *cpucfg_path; + struct icc_path *llcc_path; struct dev_pm_domain_list *pmdomains; struct dev_pm_domain_list *opp_pmdomain; struct reset_control *resets[VIDC_RESETS_NUM_MAX]; diff --git a/drivers/media/platform/qcom/venus/hfi_venus.c b/drivers/media/platform/qcom/venus/hfi_venus.c index bd82066bb6e77f..9f76a4fe5d6f6a 100644 --- a/drivers/media/platform/qcom/venus/hfi_venus.c +++ b/drivers/media/platform/qcom/venus/hfi_venus.c @@ -369,10 +369,19 @@ static void venus_set_registers(struct venus_hfi_device *hdev) const struct venus_resources *res = hdev->core->res; const struct reg_val *tbl = res->reg_tbl; unsigned int count = res->reg_tbl_size; - unsigned int i; + unsigned int i, val; + + for (i = 0; i < count; i++) { + val = tbl[i].value; - for (i = 0; i < count; i++) - writel(tbl[i].value, hdev->core->base + tbl[i].reg); + /* In some cases, we only want to update certain bits */ + if (tbl[i].mask) { + val = readl(hdev->core->base + tbl[i].reg); + val = (val & ~tbl[i].mask) | (tbl[i].value & tbl[i].mask); + } + + writel(val, hdev->core->base + tbl[i].reg); + } } static void venus_soft_int(struct venus_hfi_device *hdev) diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c b/drivers/media/platform/qcom/venus/pm_helpers.c index be1cbd5cfe8426..068005303bc6e1 100644 --- a/drivers/media/platform/qcom/venus/pm_helpers.c +++ b/drivers/media/platform/qcom/venus/pm_helpers.c @@ -254,6 +254,9 @@ static int load_scale_bw(struct venus_core *core) dev_dbg(core->dev, VDBGL "total: avg_bw: %u, peak_bw: %u\n", total_avg, total_peak); + if (core->res->has_llcc_path) + icc_set_bw(core->llcc_path, total_avg, total_peak); + return icc_set_bw(core->video_path, total_avg, total_peak); } diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 763ce6a34782bd..49511ea6d9582d 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2395,6 +2395,18 @@ config MFD_QCOM_PM8008 under it in the device tree. Additional drivers must be enabled in order to use the functionality of the device. +config MFD_AAEON + tristate "AAEON WMI MFD devices" + depends on ASUS_WMI + depends on UBUNTU_ODM_DRIVERS + help + Say yes here to support mltiple IO devices on Single Board Computers + produced by AAEON. + + This driver leverages the ASUS WMI interface to access device + resources. + + menu "Multimedia Capabilities Port drivers" depends on ARCH_SA1100 diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index dd4bb7e77c336c..2d4fddf657299c 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -294,6 +294,7 @@ obj-$(CONFIG_MFD_LS2K_BMC_CORE) += ls2k-bmc-core.o obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o +obj-$(CONFIG_MFD_AAEON) += mfd-aaeon.o obj-$(CONFIG_MFD_QNAP_MCU) += qnap-mcu.o diff --git a/drivers/mfd/mfd-aaeon.c b/drivers/mfd/mfd-aaeon.c new file mode 100644 index 00000000000000..de702c45a3b6dc --- /dev/null +++ b/drivers/mfd/mfd-aaeon.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * UP Board main platform driver and FPGA configuration support + * + * Copyright (c) 2021, AAEON Ltd. + * + * Author: Kunyang_Fan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AAEON_WMI_MGMT_GUID "97845ED0-4E6D-11DE-8A39-0800200C9A66" + +#define WMI_REPORT_CAPABILITY_METHOD 0x00000000 +#define MAX_BFPI_VERSION 255 +#define GET_REVISION_ID 0x00 + +struct aaeon_wmi_priv { + const struct mfd_cell *cells; + size_t ncells; +}; + +static const struct mfd_cell aaeon_mfd_cells[] = { + { .name = "gpio-aaeon" }, + { .name = "hwmon-aaeon"}, + { .name = "leds-aaeon"}, + { .name = "wdt-aaeon"}, +}; + +static const struct aaeon_wmi_priv aaeon_wmi_priv_data = { + .cells = aaeon_mfd_cells, + .ncells = ARRAY_SIZE(aaeon_mfd_cells), +}; + +static int aaeon_wmi_check_device(void) +{ + int err; + int retval; + + err = asus_wmi_evaluate_method(WMI_REPORT_CAPABILITY_METHOD, GET_REVISION_ID, 0, + &retval); + if (err) + return -ENODEV; + if (retval < 3 || retval > MAX_BFPI_VERSION) + return -ENODEV; + + return 0; +} + +static int aaeon_wmi_probe(struct wmi_device *wdev, const void *context) +{ + struct aaeon_wmi_priv *priv; + + if (!wmi_has_guid(AAEON_WMI_MGMT_GUID)) { + dev_info(&wdev->dev, "AAEON Management GUID not found\n"); + return -ENODEV; + } + + if (aaeon_wmi_check_device()) + return -ENODEV; + + priv = (struct aaeon_wmi_priv *)context; + dev_set_drvdata(&wdev->dev, priv); + + return devm_mfd_add_devices(&wdev->dev, 0, priv->cells, + priv->ncells, NULL, 0, NULL); +} + +static const struct wmi_device_id aaeon_wmi_id_table[] = { + { AAEON_WMI_MGMT_GUID, (void *)&aaeon_wmi_priv_data }, + {} +}; + +static struct wmi_driver aaeon_wmi_driver = { + .driver = { + .name = "mfd-aaeon", + }, + .id_table = aaeon_wmi_id_table, + .probe = aaeon_wmi_probe, +}; + +module_wmi_driver(aaeon_wmi_driver); + +MODULE_DEVICE_TABLE(wmi, aaeon_wmi_id_table); +MODULE_AUTHOR("Kunyang Fan "); +MODULE_DESCRIPTION("AAEON Board WMI driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("ASUS_WMI"); diff --git a/drivers/net/ethernet/amazon/ena/ena_com.h b/drivers/net/ethernet/amazon/ena/ena_com.h index 64df2c48c9a6aa..60c816709d7d37 100644 --- a/drivers/net/ethernet/amazon/ena/ena_com.h +++ b/drivers/net/ethernet/amazon/ena/ena_com.h @@ -48,7 +48,7 @@ /*****************************************************************************/ /* ENA adaptive interrupt moderation settings */ -#define ENA_INTR_INITIAL_TX_INTERVAL_USECS 64 +#define ENA_INTR_INITIAL_TX_INTERVAL_USECS 0 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 20 #define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1 diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c index 39043d8ca1bf48..2a7e967f32fdab 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -7201,6 +7201,9 @@ static int igc_probe(struct pci_dev *pdev, memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); + if (pci_is_thunderbolt_attached(pdev)) + msleep(1000); + /* Initialize skew-specific constants */ err = ei->get_invariants(hw); if (err) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index ec4fc21fa21fb0..655cf4d84a07dc 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -5589,6 +5590,36 @@ static void rtl_init_mac_address(struct rtl8169_private *tp) rtl_rar_set(tp, mac_addr); } +static bool rtl_aspm_new_dell_platforms(void) +{ + const char *family = dmi_get_system_info(DMI_PRODUCT_FAMILY); + static const char * const dell_product_families[] = { + "Alienware", + "Dell Laptops", + "Dell Pro Laptops", + "Dell Pro Max Laptops", + "Dell Desktops", + "Dell Pro Desktops", + "Dell Pro Max Desktops", + "Dell Pro Rugged Laptops", + "Dell Pro Precision", + "Dell Pro Essential", + "Dell Pro Education", + "XPS" + }; + int i; + + if (!family) + return false; + + for (i = 0; i < ARRAY_SIZE(dell_product_families); i++) { + if (str_has_prefix(family, dell_product_families[i])) + return true; + } + + return false; +} + /* register is set if system vendor successfully tested ASPM 1.2 */ static bool rtl_aspm_is_safe(struct rtl8169_private *tp) { @@ -5596,6 +5627,9 @@ static bool rtl_aspm_is_safe(struct rtl8169_private *tp) r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) return true; + if (rtl_aspm_new_dell_platforms()) + return true; + return false; } diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index f71cffa8840628..053f53ee42d63c 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -356,6 +357,16 @@ struct marvell_priv { u8 vct_phase; }; +static const struct dmi_system_id skip_config_led_tbl[] = { + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "Dell EMC"), + DMI_MATCH(DMI_BOARD_NAME, "0d370eed-89ca-4dc0-a365-e9904c4c62bb"), + }, + }, + {} +}; + static int marvell_read_page(struct phy_device *phydev) { return __phy_read(phydev, MII_MARVELL_PHY_PAGE); @@ -845,6 +856,9 @@ static void marvell_config_led(struct phy_device *phydev) u16 def_config; int err; + if (dmi_check_system(skip_config_led_tbl)) + return; + switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) { /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */ case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R): diff --git a/drivers/net/vxlan/vxlan_core.c b/drivers/net/vxlan/vxlan_core.c index 824144bb7774ff..843210bdbaa3d8 100644 --- a/drivers/net/vxlan/vxlan_core.c +++ b/drivers/net/vxlan/vxlan_core.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -76,6 +77,170 @@ static inline bool vxlan_collect_metadata(struct vxlan_sock *vs) ip_tunnel_collect_metadata(); } +static struct ip_fan_map *vxlan_fan_find_map(struct vxlan_dev *vxlan, __be32 daddr) +{ + struct ip_fan_map *fan_map; + + rcu_read_lock(); + list_for_each_entry_rcu(fan_map, &vxlan->fan.fan_maps, list) { + if (fan_map->overlay == + (daddr & inet_make_mask(fan_map->overlay_prefix))) { + rcu_read_unlock(); + return fan_map; + } + } + rcu_read_unlock(); + + return NULL; +} + +static void vxlan_fan_flush_map(struct vxlan_dev *vxlan) +{ + struct ip_fan_map *fan_map; + + list_for_each_entry_rcu(fan_map, &vxlan->fan.fan_maps, list) { + list_del_rcu(&fan_map->list); + kfree_rcu(fan_map, rcu); + } +} + +static int vxlan_fan_del_map(struct vxlan_dev *vxlan, __be32 overlay) +{ + struct ip_fan_map *fan_map; + + fan_map = vxlan_fan_find_map(vxlan, overlay); + if (!fan_map) + return -ENOENT; + + list_del_rcu(&fan_map->list); + kfree_rcu(fan_map, rcu); + + return 0; +} + +static int vxlan_fan_add_map(struct vxlan_dev *vxlan, struct ifla_fan_map *map) +{ + __be32 overlay_mask, underlay_mask; + struct ip_fan_map *fan_map; + + overlay_mask = inet_make_mask(map->overlay_prefix); + underlay_mask = inet_make_mask(map->underlay_prefix); + + netdev_dbg(vxlan->dev, "vfam: map: o %x/%d u %x/%d om %x um %x\n", + map->overlay, map->overlay_prefix, + map->underlay, map->underlay_prefix, + overlay_mask, underlay_mask); + + if ((map->overlay & ~overlay_mask) || (map->underlay & ~underlay_mask)) + return -EINVAL; + + if (!(map->overlay & overlay_mask) && (map->underlay & underlay_mask)) + return -EINVAL; + + /* Special case: overlay 0 and underlay 0: flush all mappings */ + if (!map->overlay && !map->underlay) { + vxlan_fan_flush_map(vxlan); + return 0; + } + + /* Special case: overlay set and underlay 0: clear map for overlay */ + if (!map->underlay) + return vxlan_fan_del_map(vxlan, map->overlay); + + if (vxlan_fan_find_map(vxlan, map->overlay)) + return -EEXIST; + + fan_map = kmalloc(sizeof(*fan_map), GFP_KERNEL); + if (!fan_map) + return -ENOMEM; + + fan_map->underlay = map->underlay; + fan_map->overlay = map->overlay; + fan_map->underlay_prefix = map->underlay_prefix; + fan_map->overlay_mask = ntohl(overlay_mask); + fan_map->overlay_prefix = map->overlay_prefix; + + list_add_tail_rcu(&fan_map->list, &vxlan->fan.fan_maps); + + return 0; +} + +static int vxlan_parse_fan_map(struct nlattr *data[], struct vxlan_dev *vxlan) +{ + struct ifla_fan_map *map; + struct nlattr *attr; + int rem, rv; + + nla_for_each_nested(attr, data[IFLA_VXLAN_FAN_MAP], rem) { + map = nla_data(attr); + rv = vxlan_fan_add_map(vxlan, map); + if (rv) + return rv; + } + + return 0; +} + +static int vxlan_fan_build_rdst(struct vxlan_dev *vxlan, struct sk_buff *skb, + struct vxlan_rdst *fan_rdst) +{ + struct ip_fan_map *f_map; + union vxlan_addr *va; + u32 daddr, underlay; + struct arphdr *arp; + void *arp_ptr; + struct ethhdr *eth; + struct iphdr *iph; + + eth = eth_hdr(skb); + switch (eth->h_proto) { + case htons(ETH_P_IP): + iph = ip_hdr(skb); + if (!iph) + return -EINVAL; + daddr = iph->daddr; + break; + case htons(ETH_P_ARP): + arp = arp_hdr(skb); + if (!arp) + return -EINVAL; + arp_ptr = arp + 1; + netdev_dbg(vxlan->dev, + "vfbr: arp sha %pM sip %pI4 tha %pM tip %pI4\n", + arp_ptr, arp_ptr + skb->dev->addr_len, + arp_ptr + skb->dev->addr_len + 4, + arp_ptr + (skb->dev->addr_len * 2) + 4); + arp_ptr += (skb->dev->addr_len * 2) + 4; + memcpy(&daddr, arp_ptr, 4); + break; + default: + netdev_dbg(vxlan->dev, "vfbr: unknown eth p %x\n", eth->h_proto); + return -EINVAL; + } + + f_map = vxlan_fan_find_map(vxlan, daddr); + if (!f_map) + return -EINVAL; + + daddr = ntohl(daddr); + underlay = ntohl(f_map->underlay); + if (!underlay) + return -EINVAL; + + memset(fan_rdst, 0, sizeof(*fan_rdst)); + va = &fan_rdst->remote_ip; + va->sa.sa_family = AF_INET; + fan_rdst->remote_vni = vxlan->default_dst.remote_vni; + va->sin.sin_addr.s_addr = htonl(underlay | + ((daddr & ~f_map->overlay_mask) >> + (32 - f_map->overlay_prefix - + (32 - f_map->underlay_prefix)))); + netdev_dbg(vxlan->dev, "vfbr: daddr %x ul %x dst %x\n", + daddr, underlay, va->sin.sin_addr.s_addr); + + return 0; +} + /* Find VXLAN socket based on network namespace, address family, UDP port, * enabled unshareable flags and socket device binding (see l3mdev with * non-default VRF). @@ -2496,6 +2661,13 @@ void vxlan_xmit_one(struct sk_buff *skb, struct net_device *dev, if (flags & VXLAN_F_MC_ROUTE) ipcb_flags |= IPSKB_MCROUTE; + if (fan_has_map(&vxlan->fan) && rt->rt_flags & RTCF_LOCAL) { + netdev_dbg(dev, "discard fan to localhost %pI4\n", + &rdst->remote_ip.sin.sin_addr.s_addr); + ip_rt_put(rt); + goto tx_free; + } + if (!info) { /* Bypass encapsulation if the destination is local */ err = encap_bypass_if_local(skb, dev, vxlan, AF_INET, @@ -2650,6 +2822,7 @@ void vxlan_xmit_one(struct sk_buff *skb, struct net_device *dev, dst_release(ndst); DEV_STATS_INC(dev, tx_errors); vxlan_vnifilter_count(vxlan, vni, NULL, VXLAN_VNI_STATS_TX_ERRORS, 0); +tx_free: kfree_skb_reason(skb, reason); } @@ -2793,6 +2966,20 @@ static netdev_tx_t vxlan_xmit(struct sk_buff *skb, struct net_device *dev) rcu_read_unlock(); } + if (fan_has_map(&vxlan->fan)) { + struct vxlan_rdst fan_rdst; + + netdev_dbg(vxlan->dev, "vxlan_xmit p %x d %pM\n", + eth->h_proto, eth->h_dest); + if (vxlan_fan_build_rdst(vxlan, skb, &fan_rdst)) { + dev->stats.tx_dropped++; + kfree_skb(skb); + return NETDEV_TX_OK; + } + vxlan_xmit_one(skb, dev, vni, &fan_rdst, 0); + return NETDEV_TX_OK; + } + eth = eth_hdr(skb); rcu_read_lock(); f = vxlan_find_mac_tx(vxlan, eth->h_dest, vni); @@ -3394,6 +3581,8 @@ static void vxlan_setup(struct net_device *dev) vxlan->dev = dev; INIT_HLIST_HEAD(&vxlan->fdb_list); + + INIT_LIST_HEAD(&vxlan->fan.fan_maps); } static void vxlan_ether_setup(struct net_device *dev) @@ -3413,6 +3602,22 @@ static void vxlan_raw_setup(struct net_device *dev) dev->netdev_ops = &vxlan_netdev_raw_ops; } +/* Validate Ubuntu FAN payload. + * + * This is required to bypass the strict length validation enforced for the + * attribute types >= IFLA_VXLAN_LOCALBYPASS in vxlan_policy. + * + * In this way we can continue to use the same allocated ID for + * IFLA_VXLAN_FAN_MAP, without breaking the existing user-space and also + * future kernel ABIs that may add new attribute types to vxlan_policy. + */ +static int fan_map_validate_entry(const struct nlattr *attr, + struct netlink_ext_ack *extack) +{ + /* Accept any payload for Ubuntu FAN */ + return 0; +} + static const struct nla_policy vxlan_policy[IFLA_VXLAN_MAX + 1] = { [IFLA_VXLAN_UNSPEC] = { .strict_start_type = IFLA_VXLAN_LOCALBYPASS }, [IFLA_VXLAN_ID] = { .type = NLA_U32 }, @@ -3449,6 +3654,9 @@ static const struct nla_policy vxlan_policy[IFLA_VXLAN_MAX + 1] = { [IFLA_VXLAN_LABEL_POLICY] = NLA_POLICY_MAX(NLA_U32, VXLAN_LABEL_MAX), [IFLA_VXLAN_RESERVED_BITS] = NLA_POLICY_EXACT_LEN(sizeof(struct vxlanhdr)), [IFLA_VXLAN_MC_ROUTE] = NLA_POLICY_MAX(NLA_U8, 1), + [IFLA_VXLAN_FAN_MAP] = NLA_POLICY_VALIDATE_FN(NLA_BINARY, + fan_map_validate_entry, + sizeof(struct ifla_fan_map) * 256), }; static int vxlan_validate(struct nlattr *tb[], struct nlattr *data[], @@ -4110,6 +4318,12 @@ static int vxlan_nl2conf(struct nlattr *tb[], struct nlattr *data[], conf->remote_ip.sa.sa_family = AF_INET6; } + if (data[IFLA_VXLAN_FAN_MAP]) { + err = vxlan_parse_fan_map(data, vxlan); + if (err) + return err; + } + if (data[IFLA_VXLAN_LOCAL]) { if (changelink && (conf->saddr.sa.sa_family != AF_INET)) { NL_SET_ERR_MSG_ATTR(extack, tb[IFLA_VXLAN_LOCAL], "New local address family does not match old"); @@ -4563,6 +4777,7 @@ static size_t vxlan_get_size(const struct net_device *dev) nla_total_size(sizeof(__u8)) + /* IFLA_VXLAN_VNIFILTER */ /* IFLA_VXLAN_RESERVED_BITS */ nla_total_size(sizeof(struct vxlanhdr)) + + nla_total_size(sizeof(struct ip_fan_map) * 256) + 0; } @@ -4609,6 +4824,26 @@ static int vxlan_fill_info(struct sk_buff *skb, const struct net_device *dev) } } + if (fan_has_map(&vxlan->fan)) { + struct nlattr *fan_nest; + struct ip_fan_map *fan_map; + + fan_nest = nla_nest_start(skb, IFLA_VXLAN_FAN_MAP); + if (!fan_nest) + goto nla_put_failure; + list_for_each_entry_rcu(fan_map, &vxlan->fan.fan_maps, list) { + struct ifla_fan_map map; + + map.underlay = fan_map->underlay; + map.underlay_prefix = fan_map->underlay_prefix; + map.overlay = fan_map->overlay; + map.overlay_prefix = fan_map->overlay_prefix; + if (nla_put(skb, IFLA_FAN_MAPPING, sizeof(map), &map)) + goto nla_put_failure; + } + nla_nest_end(skb, fan_nest); + } + if (nla_put_u8(skb, IFLA_VXLAN_TTL, vxlan->cfg.ttl) || nla_put_u8(skb, IFLA_VXLAN_TTL_INHERIT, !!(vxlan->cfg.flags & VXLAN_F_TTL_INHERIT)) || @@ -4943,6 +5178,29 @@ static __net_init int vxlan_init_net(struct net *net) NULL); } +#ifdef CONFIG_SYSCTL +static struct ctl_table_header *vxlan_fan_header; +static unsigned int vxlan_fan_version = 4; +static unsigned int ifla_vxlan_fan_map = IFLA_VXLAN_FAN_MAP; + +static struct ctl_table vxlan_fan_sysctls[] = { + { + .procname = "vxlan", + .data = &vxlan_fan_version, + .maxlen = sizeof(vxlan_fan_version), + .mode = 0444, + .proc_handler = proc_dointvec, + }, + { + .procname = "IFLA_VXLAN_FAN_MAP", + .data = &ifla_vxlan_fan_map, + .maxlen = sizeof(ifla_vxlan_fan_map), + .mode = 0444, + .proc_handler = proc_dointvec, + }, +}; +#endif /* CONFIG_SYSCTL */ + static void __net_exit vxlan_destroy_tunnels(struct vxlan_net *vn, struct list_head *dev_to_kill) { @@ -5004,7 +5262,22 @@ static int __init vxlan_init_module(void) if (rc) goto out5; +#ifdef CONFIG_SYSCTL + vxlan_fan_header = register_net_sysctl(&init_net, "net/fan", + vxlan_fan_sysctls); + if (!vxlan_fan_header) { + rc = -ENOMEM; + goto sysctl_failed; + } +#endif /* CONFIG_SYSCTL */ + return 0; + +#ifdef CONFIG_SYSCTL +sysctl_failed: + rtnl_link_unregister(&vxlan_link_ops); +#endif /* CONFIG_SYSCTL */ + out5: rtnl_link_unregister(&vxlan_link_ops); out4: @@ -5020,6 +5293,9 @@ late_initcall(vxlan_init_module); static void __exit vxlan_cleanup_module(void) { +#ifdef CONFIG_SYSCTL + unregister_net_sysctl_table(vxlan_fan_header); +#endif /* CONFIG_SYSCTL */ vxlan_vnifilter_uninit(); rtnl_link_unregister(&vxlan_link_ops); unregister_switchdev_notifier(&vxlan_switchdev_notifier_block); diff --git a/drivers/net/wireless/ath/ath10k/Kconfig b/drivers/net/wireless/ath/ath10k/Kconfig index efb9f022d8c662..eac3ec5a4e78f5 100644 --- a/drivers/net/wireless/ath/ath10k/Kconfig +++ b/drivers/net/wireless/ath/ath10k/Kconfig @@ -17,7 +17,7 @@ config ATH10K_CE config ATH10K_PCI tristate "Atheros ath10k PCI support" - depends on ATH10K && PCI + depends on ATH10K && PCI && PCIEASPM help This module adds support for PCIE bus diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c index 335bc7c488e419..c110e901c529b8 100644 --- a/drivers/net/wireless/ath/ath10k/pci.c +++ b/drivers/net/wireless/ath/ath10k/pci.c @@ -1965,9 +1965,7 @@ static int ath10k_pci_hif_start(struct ath10k *ar) ath10k_pci_irq_enable(ar); ath10k_pci_rx_post(ar); - pcie_capability_clear_and_set_word(ar_pci->pdev, PCI_EXP_LNKCTL, - PCI_EXP_LNKCTL_ASPMC, - ar_pci->link_ctl & PCI_EXP_LNKCTL_ASPMC); + pci_enable_link_state(ar_pci->pdev, ar_pci->aspm_states); return 0; } @@ -2822,10 +2820,9 @@ static int ath10k_pci_hif_power_up(struct ath10k *ar, ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); - pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, - &ar_pci->link_ctl); - pcie_capability_clear_word(ar_pci->pdev, PCI_EXP_LNKCTL, - PCI_EXP_LNKCTL_ASPMC); + ar_pci->aspm_states = pcie_aspm_enabled(ar_pci->pdev); + + pci_disable_link_state(ar_pci->pdev, PCIE_LINK_STATE_ALL); /* * Bring the target up cleanly. diff --git a/drivers/net/wireless/ath/ath10k/pci.h b/drivers/net/wireless/ath/ath10k/pci.h index d114778edb4173..122e365b7cdd84 100644 --- a/drivers/net/wireless/ath/ath10k/pci.h +++ b/drivers/net/wireless/ath/ath10k/pci.h @@ -128,10 +128,9 @@ struct ath10k_pci { struct timer_list rx_post_retry; /* Due to HW quirks it is recommended to disable ASPM during device - * bootup. To do that the original PCI-E Link Control is stored before - * device bootup is executed and re-programmed later. + * bootup. To do that the ASPM states are saved and re-programmed later. */ - u16 link_ctl; + u32 aspm_states; /* Protects ps_awake and ps_wake_refcount */ spinlock_t ps_lock; diff --git a/drivers/net/wireless/ath/ath11k/Kconfig b/drivers/net/wireless/ath/ath11k/Kconfig index 122726f84492a3..c8b41852117396 100644 --- a/drivers/net/wireless/ath/ath11k/Kconfig +++ b/drivers/net/wireless/ath/ath11k/Kconfig @@ -19,7 +19,7 @@ config ATH11K_AHB config ATH11K_PCI tristate "Atheros ath11k PCI support" - depends on ATH11K && PCI + depends on ATH11K && PCI && PCIEASPM select MHI_BUS select QRTR select QRTR_MHI diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c index 8dacc878c00687..eeb5820b55b341 100644 --- a/drivers/net/wireless/ath/ath11k/core.c +++ b/drivers/net/wireless/ath/ath11k/core.c @@ -1854,6 +1854,8 @@ int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) if (!ret) goto exit; + ath11k_err(ab, "no success fetching board data for %s\n", boardname); + fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); if (!fallback_boardname) { ret = -ENOMEM; @@ -1874,6 +1876,8 @@ int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) if (!ret) goto exit; + ath11k_err(ab, "no success fetching board data for %s\n", fallback_boardname); + chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); if (!chip_id_boardname) { ret = -ENOMEM; diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c index a163168f361764..cffff31a59d7d2 100644 --- a/drivers/net/wireless/ath/ath11k/pci.c +++ b/drivers/net/wireless/ath/ath11k/pci.c @@ -33,9 +33,12 @@ #define TCSR_SOC_HW_SUB_VER 0x1910010 +#define PCI_VENDOR_ID_HP_BOGUS 0xffff + static const struct pci_device_id ath11k_pci_id_table[] = { { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) }, + { PCI_VDEVICE(HP_BOGUS, WCN6855_DEVICE_ID) }, { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) }, {} }; @@ -608,19 +611,9 @@ static void ath11k_pci_free_region(struct ath11k_pci *ab_pci) static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci) { - struct ath11k_base *ab = ab_pci->ab; - - pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, - &ab_pci->link_ctl); - - ath11k_dbg(ab, ATH11K_DBG_PCI, "link_ctl 0x%04x L0s %d L1 %d\n", - ab_pci->link_ctl, - u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), - u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); + ab_pci->aspm_states = pcie_aspm_enabled(ab_pci->pdev); - /* disable L0s and L1 */ - pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, - PCI_EXP_LNKCTL_ASPMC); + pci_disable_link_state(ab_pci->pdev, PCIE_LINK_STATE_ALL); set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags); } @@ -628,10 +621,7 @@ static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci) static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci) { if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags)) - pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, - PCI_EXP_LNKCTL_ASPMC, - ab_pci->link_ctl & - PCI_EXP_LNKCTL_ASPMC); + pci_enable_link_state(ab_pci->pdev, ab_pci->aspm_states); } #ifdef CONFIG_DEV_COREDUMP diff --git a/drivers/net/wireless/ath/ath11k/pci.h b/drivers/net/wireless/ath/ath11k/pci.h index 1e3005a4b64c68..474c1874141871 100644 --- a/drivers/net/wireless/ath/ath11k/pci.h +++ b/drivers/net/wireless/ath/ath11k/pci.h @@ -72,7 +72,8 @@ struct ath11k_pci { /* enum ath11k_pci_flags */ unsigned long flags; - u16 link_ctl; + /* Cached PCIe ASPM states */ + u32 aspm_states; u64 dma_mask; }; diff --git a/drivers/net/wireless/ath/ath12k/Kconfig b/drivers/net/wireless/ath/ath12k/Kconfig index 4a2b240f967aff..ce7df6d881c2f7 100644 --- a/drivers/net/wireless/ath/ath12k/Kconfig +++ b/drivers/net/wireless/ath/ath12k/Kconfig @@ -1,7 +1,8 @@ # SPDX-License-Identifier: BSD-3-Clause-Clear config ATH12K tristate "Qualcomm Wi-Fi 7 support (ath12k)" - depends on MAC80211 && HAS_DMA && PCI + depends on MAC80211 && HAS_DMA && PCI && PCIEASPM + select CRYPTO_MICHAEL_MIC select QCOM_QMI_HELPERS select MHI_BUS select QRTR diff --git a/drivers/net/wireless/ath/ath12k/core.c b/drivers/net/wireless/ath/ath12k/core.c index e87165e4f4b339..15d44d1e89664e 100644 --- a/drivers/net/wireless/ath/ath12k/core.c +++ b/drivers/net/wireless/ath/ath12k/core.c @@ -80,6 +80,9 @@ static int ath12k_core_rfkill_config(struct ath12k_base *ab) if (ath12k_acpi_get_disable_rfkill(ab)) return 0; + if (of_property_read_bool(ab->dev->of_node, "disable-rfkill")) + return 0; + for (i = 0; i < ab->num_radios; i++) { ar = ab->pdevs[i].ar; diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c index a0928890671ac6..dc82a9d1596fe9 100644 --- a/drivers/net/wireless/ath/ath12k/mac.c +++ b/drivers/net/wireless/ath/ath12k/mac.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "mac.h" #include "core.h" @@ -14793,7 +14794,7 @@ static int ath12k_mac_hw_register(struct ath12k_hw *ah) int ret, i, j; u32 ht_cap = U32_MAX, antennas_rx = 0, antennas_tx = 0; bool is_6ghz = false, is_raw_mode = false, is_monitor_disable = false; - u8 *mac_addr = NULL; + const u8 *mac_addr = NULL; u8 mbssid_max_interfaces = 0; wiphy->max_ap_assoc_sta = 0; @@ -14848,6 +14849,12 @@ static int ath12k_mac_hw_register(struct ath12k_hw *ah) wiphy->available_antennas_rx = antennas_rx; wiphy->available_antennas_tx = antennas_tx; + const u8 *addr; + addr = of_get_property(ah->dev->of_node, "local-mac-address", &ret); + if (addr && ret == ETH_ALEN) { + mac_addr = addr; + } + SET_IEEE80211_PERM_ADDR(hw, mac_addr); SET_IEEE80211_DEV(hw, ab->dev); diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c index fee4129ea4055b..041764dd1a77e5 100644 --- a/drivers/net/wireless/ath/ath12k/pci.c +++ b/drivers/net/wireless/ath/ath12k/pci.c @@ -888,19 +888,9 @@ static void ath12k_pci_free_region(struct ath12k_pci *ab_pci) static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci) { - struct ath12k_base *ab = ab_pci->ab; - - pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, - &ab_pci->link_ctl); - - ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", - ab_pci->link_ctl, - u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), - u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); + ab_pci->aspm_states = pcie_aspm_enabled(ab_pci->pdev); - /* disable L0s and L1 */ - pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, - PCI_EXP_LNKCTL_ASPMC); + pci_disable_link_state(ab_pci->pdev, PCIE_LINK_STATE_ALL); set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags); } @@ -929,10 +919,7 @@ static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci) { if (ab_pci->ab->hw_params->supports_aspm && test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) - pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, - PCI_EXP_LNKCTL_ASPMC, - ab_pci->link_ctl & - PCI_EXP_LNKCTL_ASPMC); + pci_enable_link_state(ab_pci->pdev, ab_pci->aspm_states); } static void ath12k_pci_cancel_workqueue(struct ath12k_base *ab) diff --git a/drivers/net/wireless/ath/ath12k/pci.h b/drivers/net/wireless/ath/ath12k/pci.h index 0e0e2020c6ae58..409ef063cd69af 100644 --- a/drivers/net/wireless/ath/ath12k/pci.h +++ b/drivers/net/wireless/ath/ath12k/pci.h @@ -128,7 +128,9 @@ struct ath12k_pci { /* enum ath12k_pci_flags */ unsigned long flags; - u16 link_ctl; + + /* Cached PCIe ASPM states */ + u32 aspm_states; unsigned long irq_flags; const struct ath12k_pci_ops *pci_ops; u32 qmi_instance; diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c index 7a7b10152e5ae1..6b41632cfb3255 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c @@ -208,6 +208,7 @@ VISIBLE_IF_IWLWIFI_KUNIT const struct pci_device_id iwl_hw_card_ids[] = { {IWL_PCI_DEVICE(0x088E, 0x446A, iwl6030_mac_cfg)}, {IWL_PCI_DEVICE(0x088E, 0x4860, iwl6030_mac_cfg)}, {IWL_PCI_DEVICE(0x088F, 0x5260, iwl6030_mac_cfg)}, + {IWL_PCI_DEVICE(0x088F, 0x526A, iwl6030_mac_cfg)}, /* 105 Series */ {IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_mac_cfg)}, diff --git a/drivers/net/wireless/marvell/mwifiex/fw.h b/drivers/net/wireless/marvell/mwifiex/fw.h index 93561116959ac3..bcda30b973ea85 100644 --- a/drivers/net/wireless/marvell/mwifiex/fw.h +++ b/drivers/net/wireless/marvell/mwifiex/fw.h @@ -206,6 +206,7 @@ enum MWIFIEX_802_11_PRIVACY_FILTER { #define TLV_TYPE_CHANNEL_STATS (PROPRIETARY_TLV_BASE_ID + 198) #define TLV_BTCOEX_WL_AGGR_WINSIZE (PROPRIETARY_TLV_BASE_ID + 202) #define TLV_BTCOEX_WL_SCANTIME (PROPRIETARY_TLV_BASE_ID + 203) +#define TLV_TYPE_LED_CONTROL (PROPRIETARY_TLV_BASE_ID + 205) #define TLV_TYPE_BSS_MODE (PROPRIETARY_TLV_BASE_ID + 206) #define TLV_TYPE_RANDOM_MAC (PROPRIETARY_TLV_BASE_ID + 236) #define TLV_TYPE_CHAN_ATTR_CFG (PROPRIETARY_TLV_BASE_ID + 237) @@ -356,6 +357,7 @@ enum MWIFIEX_802_11_PRIVACY_FILTER { #define HostCmd_CMD_802_11_AD_HOC_JOIN 0x002c #define HostCmd_CMD_802_11_AD_HOC_STOP 0x0040 #define HostCmd_CMD_802_11_MAC_ADDRESS 0x004D +#define HostCmd_CMD_802_11_LED_CONTROL 0X004E #define HostCmd_CMD_802_11D_DOMAIN_INFO 0x005b #define HostCmd_CMD_802_11_KEY_MATERIAL 0x005e #define HostCmd_CMD_802_11_BG_SCAN_CONFIG 0x006b @@ -1236,6 +1238,16 @@ struct ieee_types_oper_mode_ntf { u8 oper_mode; } __packed; +struct mwifiex_led_param { + __le16 mode; + __le16 on; +} __packed; + +struct mwifiex_ie_types_led_param { + struct mwifiex_ie_types_header header; + struct mwifiex_led_param led_cfg; +} __packed; + struct host_cmd_ds_802_11_ad_hoc_start { u8 ssid[IEEE80211_MAX_SSID_LEN]; u8 bss_mode; @@ -1359,6 +1371,11 @@ struct host_cmd_ds_802_11_hs_cfg_enh { } params; } __packed; +struct host_cmd_ds_802_11_led_control { + __le16 action; + __le16 num_led; +} __packed; + enum SNMP_MIB_INDEX { OP_RATE_SET_I = 1, DTIM_PERIOD_I = 3, @@ -2438,6 +2455,7 @@ struct host_cmd_ds_command { struct host_cmd_sdio_sp_rx_aggr_cfg sdio_rx_aggr_cfg; struct host_cmd_ds_multi_chan_policy mc_policy; struct host_cmd_ds_robust_coex coex; + struct host_cmd_ds_802_11_led_control led_cfg; struct host_cmd_ds_wakeup_reason hs_wakeup_reason; struct host_cmd_ds_gtk_rekey_params rekey; struct host_cmd_ds_chan_region_cfg reg_cfg; diff --git a/drivers/net/wireless/marvell/mwifiex/main.c b/drivers/net/wireless/marvell/mwifiex/main.c index a8eab6b1e63b0f..0d13cd60638751 100644 --- a/drivers/net/wireless/marvell/mwifiex/main.c +++ b/drivers/net/wireless/marvell/mwifiex/main.c @@ -731,8 +731,10 @@ static int mwifiex_init_hw_fw(struct mwifiex_adapter *adapter, static int mwifiex_open(struct net_device *dev) { - netif_carrier_off(dev); + struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev); + netif_carrier_off(dev); + mwifiex_set_led(priv->adapter, MWIFIEX_LED_ON); return 0; } @@ -763,6 +765,7 @@ mwifiex_close(struct net_device *dev) cfg80211_sched_scan_stopped(priv->wdev.wiphy, 0); } + mwifiex_set_led(priv->adapter, MWIFIEX_LED_OFF); return 0; } diff --git a/drivers/net/wireless/marvell/mwifiex/main.h b/drivers/net/wireless/marvell/mwifiex/main.h index 27559e2ddc3175..8a4d27c820c27f 100644 --- a/drivers/net/wireless/marvell/mwifiex/main.h +++ b/drivers/net/wireless/marvell/mwifiex/main.h @@ -119,6 +119,10 @@ enum { #define PKT_TYPE_MGMT 0xE5 +#define MWIFIEX_LED_ON 1 +#define MWIFIEX_LED_OFF 0 +#define MWIFIEX_LED_MAX 3 + /* * Do not check for data_received for USB, as data_received * is handled in mwifiex_usb_recv for USB @@ -681,6 +685,7 @@ struct mwifiex_private { struct sk_buff_head bypass_txq; struct mwifiex_user_scan_chan hidden_chan[MWIFIEX_USER_SCAN_CHAN_MAX]; bool ht_param_present; + bool is_edge_gateway; }; @@ -1479,6 +1484,7 @@ int mwifiex_wait_queue_complete(struct mwifiex_adapter *adapter, struct cmd_ctrl_node *cmd_queued); int mwifiex_bss_start(struct mwifiex_private *priv, struct cfg80211_bss *bss, struct cfg80211_ssid *req_ssid); +int mwifiex_set_led(struct mwifiex_adapter *adapter, int on); int mwifiex_cancel_hs(struct mwifiex_private *priv, int cmd_type); int mwifiex_enable_hs(struct mwifiex_adapter *adapter); int mwifiex_disable_auto_ds(struct mwifiex_private *priv); diff --git a/drivers/net/wireless/marvell/mwifiex/pcie.c b/drivers/net/wireless/marvell/mwifiex/pcie.c index a760de191fce73..9cc2c0c13e8c7e 100644 --- a/drivers/net/wireless/marvell/mwifiex/pcie.c +++ b/drivers/net/wireless/marvell/mwifiex/pcie.c @@ -377,6 +377,8 @@ static int mwifiex_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct pcie_service_card *card; + struct mwifiex_private *priv; + struct pci_dev *pdev_host; int ret; pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n", @@ -418,6 +420,14 @@ static int mwifiex_pcie_probe(struct pci_dev *pdev, return -1; } + priv = mwifiex_get_priv(card->adapter, MWIFIEX_BSS_ROLE_STA); + pdev_host = pci_get_subsys(PCI_ANY_ID, PCI_ANY_ID, 0x1028, 0x0720, NULL); + if (!pdev_host) + pdev_host = pci_get_subsys(PCI_ANY_ID, PCI_ANY_ID, 0x1028, 0x0733, NULL); + if (pdev_host) { + priv->is_edge_gateway = true; + pci_dev_put(pdev_host); + } return 0; } diff --git a/drivers/net/wireless/marvell/mwifiex/sta_cmd.c b/drivers/net/wireless/marvell/mwifiex/sta_cmd.c index 071f7cb305e1b7..9b4cbad1b5669b 100644 --- a/drivers/net/wireless/marvell/mwifiex/sta_cmd.c +++ b/drivers/net/wireless/marvell/mwifiex/sta_cmd.c @@ -401,6 +401,31 @@ mwifiex_cmd_802_11_hs_cfg(struct mwifiex_private *priv, return 0; } +static int mwifiex_cmd_802_11_led_cfg(struct mwifiex_private *priv, + struct host_cmd_ds_command *cmd, + u16 cmd_action, + struct mwifiex_led_param *ledcfg_param) +{ + struct host_cmd_ds_802_11_led_control *led_cfg = &cmd->params.led_cfg; + struct mwifiex_ie_types_led_param *led_tlv; + u8 *pos; + + cmd->command = cpu_to_le16(HostCmd_CMD_802_11_LED_CONTROL); + cmd->size = cpu_to_le16(S_DS_GEN); + le16_add_cpu(&cmd->size, sizeof(struct host_cmd_ds_802_11_led_control)); + + led_cfg->action = cpu_to_le16(cmd_action); + led_cfg->num_led = cpu_to_le16(MWIFIEX_LED_MAX); + + pos = (u8 *)led_cfg + sizeof(struct host_cmd_ds_802_11_led_control); + led_tlv = (void *)pos; + led_tlv->header.type = cpu_to_le16(TLV_TYPE_LED_CONTROL); + led_tlv->header.len = cpu_to_le16(sizeof(struct mwifiex_led_param)); + memcpy(&led_tlv->led_cfg, ledcfg_param, sizeof(struct mwifiex_led_param)); + le16_add_cpu(&cmd->size, sizeof(struct mwifiex_ie_types_led_param)); + return 0; +} + /* * This function prepares command to set/get MAC address. * @@ -2088,6 +2113,10 @@ int mwifiex_sta_prepare_cmd(struct mwifiex_private *priv, uint16_t cmd_no, ret = mwifiex_cmd_802_11_hs_cfg(priv, cmd_ptr, cmd_action, (struct mwifiex_hs_config_param *) data_buf); break; + case HostCmd_CMD_802_11_LED_CONTROL: + ret = mwifiex_cmd_802_11_led_cfg(priv, cmd_ptr, cmd_action, + data_buf); + break; case HostCmd_CMD_802_11_SCAN: ret = mwifiex_cmd_802_11_scan(cmd_ptr, data_buf); break; diff --git a/drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c b/drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c index 85512f526c5f2a..16d0fcb94469cc 100644 --- a/drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c +++ b/drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c @@ -1424,6 +1424,8 @@ int mwifiex_process_sta_cmdresp(struct mwifiex_private *priv, u16 cmdresp_no, case HostCmd_CMD_ROBUST_COEX: ret = mwifiex_ret_robust_coex(priv, resp, data_buf); break; + case HostCmd_CMD_802_11_LED_CONTROL: + break; case HostCmd_CMD_GTK_REKEY_OFFLOAD_CFG: break; case HostCmd_CMD_CHAN_REGION_CFG: diff --git a/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c b/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c index 9460d5352b234e..2d56ead01b4c32 100644 --- a/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c +++ b/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c @@ -612,6 +612,24 @@ int mwifiex_enable_hs(struct mwifiex_adapter *adapter) } EXPORT_SYMBOL_GPL(mwifiex_enable_hs); +int mwifiex_set_led(struct mwifiex_adapter *adapter, int on) +{ + struct mwifiex_private *priv; + struct mwifiex_led_param ledcfg; + + priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA); + if (!priv->is_edge_gateway) + return -ENODEV; + + memset(&ledcfg, 0, sizeof(struct mwifiex_led_param)); + ledcfg.on = cpu_to_le16(on); + + return mwifiex_send_cmd(priv, + HostCmd_CMD_802_11_LED_CONTROL, + HostCmd_ACT_GEN_SET, 0, + &ledcfg, true); +} + /* * IOCTL request handler to get BSS information. * diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index 453c1f0b2dd094..90ef027d7012ce 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -1319,7 +1319,7 @@ EXPORT_SYMBOL_NS_GPL(nvme_passthru_end, "NVME_TARGET_PASSTHRU"); * The host should send Keep Alive commands at half of the Keep Alive Timeout * accounting for transport roundtrip times [..]. */ -static unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl) +unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl) { unsigned long delay = ctrl->kato * HZ / 2; @@ -1333,6 +1333,7 @@ static unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl) delay /= 2; return delay; } +EXPORT_SYMBOL_GPL(nvme_keep_alive_work_period); static void nvme_queue_keep_alive_work(struct nvme_ctrl *ctrl) { diff --git a/drivers/nvme/host/fabrics.c b/drivers/nvme/host/fabrics.c index ac3d4f400601f5..91b9cb5f45f9f4 100644 --- a/drivers/nvme/host/fabrics.c +++ b/drivers/nvme/host/fabrics.c @@ -709,6 +709,7 @@ static const match_table_t opt_tokens = { { NVMF_OPT_TLS, "tls" }, { NVMF_OPT_CONCAT, "concat" }, #endif + { NVMF_OPT_RECOVERY_DELAY, "recovery_delay=%d" }, { NVMF_OPT_ERR, NULL } }; @@ -1064,6 +1065,18 @@ static int nvmf_parse_options(struct nvmf_ctrl_options *opts, } opts->concat = true; break; + case NVMF_OPT_RECOVERY_DELAY: + if (match_int(args, &token)) { + ret = -EINVAL; + goto out; + } + if (token <= 0) { + pr_err("Invalid recovery_delay %d\n", token); + ret = -EINVAL; + goto out; + } + opts->recovery_delay = token; + break; default: pr_warn("unknown parameter or missing value '%s' in ctrl creation request\n", p); diff --git a/drivers/nvme/host/fabrics.h b/drivers/nvme/host/fabrics.h index caf5503d083329..7edb14e9f0db60 100644 --- a/drivers/nvme/host/fabrics.h +++ b/drivers/nvme/host/fabrics.h @@ -67,6 +67,7 @@ enum { NVMF_OPT_KEYRING = 1 << 26, NVMF_OPT_TLS_KEY = 1 << 27, NVMF_OPT_CONCAT = 1 << 28, + NVMF_OPT_RECOVERY_DELAY = 1 << 29, }; /** @@ -93,6 +94,7 @@ enum { * @queue_size: Number of IO queue elements. * @nr_io_queues: Number of controller IO queues that will be established. * @reconnect_delay: Time between two consecutive reconnect attempts. + * @recovery_delay: Time before error recovery starts after error detection. * @discovery_nqn: indicates if the subsysnqn is the well-known discovery NQN. * @kato: Keep-alive timeout. * @host: Virtual NVMe host, contains the NQN and Host ID. @@ -123,6 +125,7 @@ struct nvmf_ctrl_options { size_t queue_size; unsigned int nr_io_queues; unsigned int reconnect_delay; + unsigned int recovery_delay; bool discovery_nqn; bool duplicate_connect; unsigned int kato; diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h index 824651cc898dbe..784bdf63456e7d 100644 --- a/drivers/nvme/host/nvme.h +++ b/drivers/nvme/host/nvme.h @@ -915,6 +915,7 @@ void nvme_unfreeze(struct nvme_ctrl *ctrl); void nvme_wait_freeze(struct nvme_ctrl *ctrl); int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl); void nvme_start_freeze(struct nvme_ctrl *ctrl); +unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl); static inline enum req_op nvme_req_op(struct nvme_command *cmd) { diff --git a/drivers/nvme/host/tcp.c b/drivers/nvme/host/tcp.c index ba5c7b3e2a7c6b..a416269feadf2f 100644 --- a/drivers/nvme/host/tcp.c +++ b/drivers/nvme/host/tcp.c @@ -161,7 +161,7 @@ struct nvme_tcp_ctrl { struct sockaddr_storage src_addr; struct nvme_ctrl ctrl; - struct work_struct err_work; + struct delayed_work err_work; struct delayed_work connect_work; struct nvme_tcp_request async_req; u32 io_queues[HCTX_MAX_TYPES]; @@ -603,13 +603,25 @@ static void nvme_tcp_init_recv_ctx(struct nvme_tcp_queue *queue) queue->ddgst_remaining = 0; } +/* + * Error recovery needs to be started after KATO expired, + * always delay until the next KATO interval before + * starting error recovery. + */ static void nvme_tcp_error_recovery(struct nvme_ctrl *ctrl) { + unsigned long delay; + if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) return; - dev_warn(ctrl->device, "starting error recovery\n"); - queue_work(nvme_reset_wq, &to_tcp_ctrl(ctrl)->err_work); + delay = ctrl->opts->recovery_delay * HZ; + if (!delay) + delay = nvme_keep_alive_work_period(ctrl); + + dev_warn(ctrl->device, "starting error recovery in %lu seconds\n", + delay / HZ); + queue_delayed_work(nvme_reset_wq, &to_tcp_ctrl(ctrl)->err_work, delay); } static int nvme_tcp_process_nvme_cqe(struct nvme_tcp_queue *queue, @@ -2496,7 +2508,7 @@ static void nvme_tcp_reconnect_ctrl_work(struct work_struct *work) static void nvme_tcp_error_recovery_work(struct work_struct *work) { - struct nvme_tcp_ctrl *tcp_ctrl = container_of(work, + struct nvme_tcp_ctrl *tcp_ctrl = container_of(to_delayed_work(work), struct nvme_tcp_ctrl, err_work); struct nvme_ctrl *ctrl = &tcp_ctrl->ctrl; @@ -2569,7 +2581,7 @@ static void nvme_reset_ctrl_work(struct work_struct *work) static void nvme_tcp_stop_ctrl(struct nvme_ctrl *ctrl) { - flush_work(&to_tcp_ctrl(ctrl)->err_work); + flush_delayed_work(&to_tcp_ctrl(ctrl)->err_work); cancel_delayed_work_sync(&to_tcp_ctrl(ctrl)->connect_work); } @@ -2673,6 +2685,14 @@ static enum blk_eh_timer_return nvme_tcp_timeout(struct request *rq) rq->tag, nvme_cid(rq), pdu->hdr.type, cmd->common.opcode, nvme_fabrics_opcode_str(qid, cmd), qid); + /* + * If the error recovery is started all commands will be + * aborted anyway, and nothing is to be done here. + */ + if (nvme_ctrl_state(ctrl) == NVME_CTRL_RESETTING && + delayed_work_pending(&to_tcp_ctrl(ctrl)->err_work)) + return BLK_EH_RESET_TIMER; + if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE) { /* * If we are resetting, connecting or deleting we should @@ -2928,7 +2948,8 @@ static struct nvme_tcp_ctrl *nvme_tcp_alloc_ctrl(struct device *dev, INIT_DELAYED_WORK(&ctrl->connect_work, nvme_tcp_reconnect_ctrl_work); - INIT_WORK(&ctrl->err_work, nvme_tcp_error_recovery_work); + INIT_DELAYED_WORK(&ctrl->err_work, + nvme_tcp_error_recovery_work); INIT_WORK(&ctrl->ctrl.reset_work, nvme_reset_ctrl_work); if (!(opts->mask & NVMF_OPT_TRSVCID)) { diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index d8eb52857f69c0..45f4caeb0814d9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1085,11 +1085,6 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) static int qcom_pcie_enable_aspm(struct pci_dev *pdev, void *userdata) { - /* - * Downstream devices need to be in D0 state before enabling PCI PM - * substates. - */ - pci_set_power_state_locked(pdev, PCI_D0); pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); return 0; diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index d4ae250d4bc6d7..2574f48d94f6f2 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -739,6 +739,8 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) if (!(features & VMD_FEAT_BIOS_PM_QUIRK)) return 0; + pdev->aspm_os_control = 1; + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR); if (!pos) goto out_state_change; @@ -762,11 +764,6 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) pci_info(pdev, "VMD: Default LTR value set by driver\n"); out_state_change: - /* - * Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per - * PCIe r6.0, sec 5.5.4. - */ - pci_set_power_state_locked(pdev, PCI_D0); pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); return 0; } @@ -901,10 +898,15 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) sd->node = pcibus_to_node(vmd->dev->bus); + pci_lock_rescan_remove(); + vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start, &vmd_ops, sd, &resources); if (!vmd->bus) { pci_bus_release_emul_domain_nr(sd->domain); + + pci_unlock_rescan_remove(); + pci_free_resource_list(&resources); vmd_remove_irq_domain(vmd); return -ENODEV; @@ -962,6 +964,8 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) pci_bus_add_devices(vmd->bus); vmd_acpi_end(); + + pci_unlock_rescan_remove(); return 0; } diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 172783e7f519ab..fa2bb9caa615eb 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -1449,16 +1449,23 @@ static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool locked return -EINVAL; /* * A driver requested that ASPM be disabled on this device, but - * if we don't have permission to manage ASPM (e.g., on ACPI + * if we might not have permission to manage ASPM (e.g., on ACPI * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and - * the _OSC method), we can't honor that request. Windows has - * a similar mechanism using "PciASPMOptOut", which is also - * ignored in this situation. + * the _OSC method), previously we chose to not honor disable + * request in that case. Windows has a similar mechanism using + * "PciASPMOptOut", which is also ignored in this situation. + * + * Not honoring the requests to disable ASPM, however, led to + * drivers forcing ASPM off on their own. As such changes of ASPM + * state are not tracked by this service driver, the state kept here + * became out of sync. + * + * Therefore, honor ASPM disable requests even when OS does not have + * ASPM control. Plain disable for ASPM is assumed to be slightly + * safer than fully managing it. */ - if (aspm_disabled) { - pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n"); - return -EPERM; - } + if (aspm_disabled) + pci_warn(pdev, "OS doesn't have ASPM control, disabling ASPM anyway\n"); if (!locked) down_read(&pci_bus_sem); @@ -1476,6 +1483,17 @@ static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool locked return 0; } +/** + * pci_disable_link_state_locked - Disable device's link state + * @pdev: PCI device + * @state: ASPM link state to disable + * + * Disable device's link state so the link will never enter specific states. + * + * Context: Caller holds pci_bus_sem read lock. + * + * Return: 0 on success, a negative errno otherwise. + */ int pci_disable_link_state_locked(struct pci_dev *pdev, int state) { lockdep_assert_held_read(&pci_bus_sem); @@ -1485,13 +1503,13 @@ int pci_disable_link_state_locked(struct pci_dev *pdev, int state) EXPORT_SYMBOL(pci_disable_link_state_locked); /** - * pci_disable_link_state - Disable device's link state, so the link will - * never enter specific states. Note that if the BIOS didn't grant ASPM - * control to the OS, this does nothing because we can't touch the LNKCTL - * register. Returns 0 or a negative errno. - * + * pci_disable_link_state - Disable device's link state * @pdev: PCI device * @state: ASPM link state to disable + * + * Disable device's link state so the link will never enter specific states. + * + * Return: 0 or a negative errno */ int pci_disable_link_state(struct pci_dev *pdev, int state) { @@ -1512,14 +1530,19 @@ static int __pci_enable_link_state(struct pci_dev *pdev, int state, bool locked) * the _OSC method), we can't honor that request. */ if (aspm_disabled) { - pci_warn(pdev, "can't override BIOS ASPM; OS doesn't have ASPM control\n"); - return -EPERM; + if (aspm_support_enabled && pdev->aspm_os_control) + pci_info(pdev, "BIOS can't program ASPM, let OS control it\n"); + else { + pci_warn(pdev, "can't override BIOS ASPM; OS doesn't have ASPM control\n"); + return -EPERM; + } } if (!locked) down_read(&pci_bus_sem); mutex_lock(&aspm_lock); link->aspm_default = pci_calc_aspm_enable_mask(state); + link->aspm_disable &= ~state; pcie_config_aspm_link(link, policy_to_aspm_state(link)); link->clkpm_default = (state & PCIE_LINK_STATE_CLKPM) ? 1 : 0; @@ -1532,43 +1555,59 @@ static int __pci_enable_link_state(struct pci_dev *pdev, int state, bool locked) } /** - * pci_enable_link_state - Clear and set the default device link state so that - * the link may be allowed to enter the specified states. Note that if the - * BIOS didn't grant ASPM control to the OS, this does nothing because we can't - * touch the LNKCTL register. Also note that this does not enable states - * disabled by pci_disable_link_state(). Return 0 or a negative errno. - * - * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per - * PCIe r6.0, sec 5.5.4. - * + * pci_enable_link_state - Enable device's link state * @pdev: PCI device * @state: Mask of ASPM link states to enable + * + * Enable device's link state, so the link will enter the specified states. + * Note that if the BIOS didn't grant ASPM control to the OS, this does + * nothing because we can't touch the LNKCTL register. + * + * Note: The device will be transitioned to D0 state if the PCI-PM L1 Substates + * are getting enabled. + * + * Return: 0 on success, a negative errno otherwise. */ int pci_enable_link_state(struct pci_dev *pdev, int state) { + /* + * Ensure the device is in D0 before enabling PCI-PM L1 PM Substates, per + * PCIe r6.0, sec 5.5.4. + */ + if (FIELD_GET(PCIE_LINK_STATE_L1_SS_PCIPM, state)) + pci_set_power_state(pdev, PCI_D0); + return __pci_enable_link_state(pdev, state, false); } EXPORT_SYMBOL(pci_enable_link_state); /** - * pci_enable_link_state_locked - Clear and set the default device link state - * so that the link may be allowed to enter the specified states. Note that if - * the BIOS didn't grant ASPM control to the OS, this does nothing because we - * can't touch the LNKCTL register. Also note that this does not enable states - * disabled by pci_disable_link_state(). Return 0 or a negative errno. - * - * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per - * PCIe r6.0, sec 5.5.4. - * + * pci_enable_link_state_locked - Enable device's link state * @pdev: PCI device * @state: Mask of ASPM link states to enable * + * Enable device's link state, so the link will enter the specified states. + * Note that if the BIOS didn't grant ASPM control to the OS, this does + * nothing because we can't touch the LNKCTL register. + * + * Note: The device will be transitioned to D0 state if the PCI-PM L1 Substates + * are getting enabled. + * * Context: Caller holds pci_bus_sem read lock. + * + * Return: 0 on success, a negative errno otherwise. */ int pci_enable_link_state_locked(struct pci_dev *pdev, int state) { lockdep_assert_held_read(&pci_bus_sem); + /* + * Ensure the device is in D0 before enabling PCI-PM L1 PM Substates, per + * PCIe r6.0, sec 5.5.4. + */ + if (FIELD_GET(PCIE_LINK_STATE_L1_SS_PCIPM, state)) + pci_set_power_state(pdev, PCI_D0); + return __pci_enable_link_state(pdev, state, true); } EXPORT_SYMBOL(pci_enable_link_state_locked); @@ -1628,15 +1667,17 @@ module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, NULL, 0644); /** - * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device. + * pcie_aspm_enabled - Get the enabled PCIe ASPM states for a device. * @pdev: Target device. * * Relies on the upstream bridge's link_state being valid. The link_state * is deallocated only when the last child of the bridge (i.e., @pdev or a * sibling) is removed, and the caller should be holding a reference to * @pdev, so this should be safe. + * + * Return: Enabled PCIe ASPM states. 0 if ASPM is disabled. */ -bool pcie_aspm_enabled(struct pci_dev *pdev) +u32 pcie_aspm_enabled(struct pci_dev *pdev) { struct pcie_link_state *link = pcie_aspm_get_link(pdev); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index b09f27f7846fcd..e7b3fda85327ba 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -304,6 +304,21 @@ static void quirk_mmio_always_on(struct pci_dev *dev) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); +/* The BAR0 ~ BAR4 of Marvell 9125 device can't be accessed +* by IO resource file, and need to skip the files +*/ +static void quirk_marvell_mask_bar(struct pci_dev *dev) +{ + int i; + + for (i = 0; i < 5; i++) + if (dev->resource[i].start) + dev->resource[i].start = + dev->resource[i].end = 0; +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, + quirk_marvell_mask_bar); + /* * The Mellanox Tavor device gives false positive parity errors. Disable * parity error reporting. diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c index af4fa17ac6cbcb..7c35dbbae2ce86 100644 --- a/drivers/phy/phy-snps-eusb2.c +++ b/drivers/phy/phy-snps-eusb2.c @@ -11,6 +11,7 @@ #include #include #include +#include #define EXYNOS_USB_PHY_HS_PHY_CTRL_RST (0x0) #define USB_PHY_RST_MASK GENMASK(1, 0) @@ -467,6 +468,12 @@ static int snps_eusb2_hsphy_init(struct phy *p) goto disable_vreg; } + ret = of_clk_set_defaults(dev_of_node(p->dev.parent), false); + if (ret) { + dev_err(&p->dev, "failed to set clk defaults: %d\n", ret); + goto exit_repeater; + } + ret = clk_bulk_prepare_enable(phy->data->num_clks, phy->clks); if (ret) { dev_err(&p->dev, "failed to enable ref clock: %d\n", ret); @@ -625,6 +632,7 @@ static struct platform_driver snps_eusb2_hsphy_driver = { .name = "snps-eusb2-hsphy", .of_match_table = snps_eusb2_hsphy_of_match_table, }, + .driver_managed_clk_defaults = true, }; module_platform_driver(snps_eusb2_hsphy_driver); diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 60a0ead127fa9f..24263f8f30a927 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -28,6 +28,17 @@ config PHY_QCOM_EDP Enable this driver to support the Qualcomm eDP PHY found in various Qualcomm chipsets. +config PHY_QCOM_MIPI_CSI2 + tristate "Qualcomm MIPI CSI2 PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on OF + depends on COMMON_CLK + select GENERIC_PHY + select GENERIC_PHY_MIPI_DPHY + help + Enable this to support the MIPI CSI2 PHY driver found in various + Qualcomm chipsets. + config PHY_QCOM_IPQ4019_USB tristate "Qualcomm IPQ4019 USB PHY driver" depends on OF && (ARCH_QCOM || COMPILE_TEST) diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index b71a6a0bed3f14..b21a4f9086f6cb 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -6,6 +6,12 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o obj-$(CONFIG_PHY_QCOM_M31_EUSB) += phy-qcom-m31-eusb2.o + +phy-qcom-mipi-csi2-objs += phy-qcom-mipi-csi2-core.o \ + phy-qcom-mipi-csi2-3ph-dphy.o + +obj-$(CONFIG_PHY_QCOM_MIPI_CSI2) += phy-qcom-mipi-csi2.o + obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index a3c893f72908f4..a391c29463ef6e 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -1453,18 +1453,6 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) if (ret) return ret; - ret = regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */ - if (ret) { - dev_err(dev, "failed to set load at %s\n", edp->supplies[0].supply); - return ret; - } - - ret = regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */ - if (ret) { - dev_err(dev, "failed to set load at %s\n", edp->supplies[1].supply); - return ret; - } - ret = qcom_edp_clks_register(edp, pdev->dev.of_node); if (ret) return ret; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c new file mode 100644 index 00000000000000..1f9736bfc76a14 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-phy_qcom_mipi_csi2-3ph-1-0.c + * + * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0 + * + * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2016-2025 Linaro Ltd. + */ +#define DEBUG +#include +#include +#include + +#include "phy-qcom-mipi-csi2.h" + +#define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) +#define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) +#define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) +#define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3) +#define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) +#define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) +#define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4 +#define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660 0xa5 +#define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n)) +#define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02 +#define CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT 0x50 +#define CSIPHY_3PH_LNn_TEST_IMP(n) (0x01c + 0x100 * (n)) +#define CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP 0xa +#define CSIPHY_3PH_LNn_MISC1(n) (0x028 + 0x100 * (n)) +#define CSIPHY_3PH_LNn_MISC1_IS_CLKLANE BIT(2) +#define CSIPHY_3PH_LNn_CFG6(n) (0x02c + 0x100 * (n)) +#define CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT BIT(0) +#define CSIPHY_3PH_LNn_CFG7(n) (0x030 + 0x100 * (n)) +#define CSIPHY_3PH_LNn_CFG7_SWI_T_INIT 0x2 +#define CSIPHY_3PH_LNn_CFG8(n) (0x034 + 0x100 * (n)) +#define CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP BIT(0) +#define CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE BIT(1) +#define CSIPHY_3PH_LNn_CFG9(n) (0x038 + 0x100 * (n)) +#define CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP 0x1 +#define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n) (0x03c + 0x100 * (n)) +#define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8 + +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(offset, n) ((offset) + 0x4 * (n)) +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7) +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n)) + +#define CSIPHY_DEFAULT_PARAMS 0 +#define CSIPHY_LANE_ENABLE 1 +#define CSIPHY_SETTLE_CNT_LOWER_BYTE 2 +#define CSIPHY_SETTLE_CNT_HIGHER_BYTE 3 +#define CSIPHY_DNP_PARAMS 4 +#define CSIPHY_2PH_REGS 5 +#define CSIPHY_3PH_REGS 6 +#define CSIPHY_SKEW_CAL 7 + +#include "phy-qcom-mipi-csi2-cphy-x1e80100.h" + +#define X1E80100_CPHY_SYMBOL_RATE 2406000000UL + +static bool is_x1e80100_cphy(struct mipi_csi2phy_device *csi2phy, + const struct mipi_csi2phy_stream_cfg *cfg); +static void x1e80100_cphy_write(struct mipi_csi2phy_device *csi2phy, + const struct x1e80100_cphy_reg *table, + unsigned int num_entries); +static void x1e80100_cphy_clear_irq(struct mipi_csi2phy_device *csi2phy); + +/* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */ +static const struct +mipi_csi2phy_lane_regs lane_regs_x1e80100[] = { + /* Power up lanes 2ph mode */ + {0x1014, 0xD5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x101C, 0x7A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x1018, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x0C5C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0C60, 0xBD, 0x00, CSIPHY_SKEW_CAL}, + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL}, +}; + +static inline const struct mipi_csi2phy_device_regs * +csi2phy_dev_to_regs(const struct mipi_csi2phy_device *csi2phy) +{ + return &csi2phy->soc_cfg->reg_info; +} + +static void phy_qcom_mipi_csi2_hw_version_read(struct mipi_csi2phy_device *csi2phy) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + u32 hw_version; + + writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); + + hw_version = readl_relaxed(csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 12)); + hw_version |= readl_relaxed(csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 13)) << 8; + hw_version |= readl_relaxed(csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 14)) << 16; + hw_version |= readl_relaxed(csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 15)) << 24; + + csi2phy->hw_version = hw_version; + + dev_dbg(csi2phy->dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version); +} + +/* + * phy_qcom_mipi_csi2_reset - Perform software reset on CSIPHY module + * @phy_qcom_mipi_csi2: CSIPHY device + */ +static void phy_qcom_mipi_csi2_reset(struct mipi_csi2phy_device *csi2phy) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + + writel_relaxed(0x1, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 0)); + usleep_range(5000, 8000); + writel_relaxed(0x0, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 0)); +} + +static irqreturn_t phy_qcom_mipi_csi2_isr(int irq, void *dev) +{ + struct mipi_csi2phy_device *csi2phy = dev; + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + int i; + + if (is_x1e80100_cphy(csi2phy, &csi2phy->stream_cfg)) { + x1e80100_cphy_clear_irq(csi2phy); + return IRQ_HANDLED; + } + + for (i = 0; i < 11; i++) { + int c = i + 22; + u8 val = readl_relaxed(csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, i)); + + writel_relaxed(val, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, c)); + } + + writel_relaxed(0x1, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 10)); + writel_relaxed(0x0, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 10)); + + for (i = 22; i < 33; i++) { + writel_relaxed(0x0, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i)); + } + + return IRQ_HANDLED; +} + +/* + * phy_qcom_mipi_csi2_settle_cnt_calc - Calculate settle count value + * + * Helper function to calculate settle count value. This is + * based on the CSI2 T_hs_settle parameter which in turn + * is calculated based on the CSI2 transmitter link frequency. + * + * Return settle count value or 0 if the CSI2 link frequency + * is not available + */ +static u8 phy_qcom_mipi_csi2_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate) +{ + u32 ui; /* ps */ + u32 timer_period; /* ps */ + u32 t_hs_prepare_max; /* ps */ + u32 t_hs_settle; /* ps */ + u8 settle_cnt; + + if (link_freq <= 0) + return 0; + + ui = div_u64(1000000000000LL, link_freq); + ui /= 2; + t_hs_prepare_max = 85000 + 6 * ui; + t_hs_settle = t_hs_prepare_max; + + timer_period = div_u64(1000000000000LL, timer_clk_rate); + settle_cnt = t_hs_settle / timer_period - 6; + + return settle_cnt; +} + +static void phy_qcom_mipi_csi2_gen1_config_lanes(struct mipi_csi2phy_device *csi2phy, + struct mipi_csi2phy_stream_cfg *cfg, + u8 settle_cnt) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + struct mipi_csi2phy_lanes_cfg *lane_cfg = &cfg->lane_cfg; + int i, l = 0; + u8 val; + + for (i = 0; i <= cfg->num_data_lanes; i++) { + if (i == cfg->num_data_lanes) + l = 7; + else + l = lane_cfg->data[i].pos * 2; + + val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG; + val |= 0x17; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_CFG1(l)); + + val = CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_CFG2(l)); + + val = settle_cnt; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_CFG3(l)); + + val = CSIPHY_3PH_LNn_CFG5_T_HS_DTERM | + CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_CFG5(l)); + + val = CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_CFG6(l)); + + val = CSIPHY_3PH_LNn_CFG7_SWI_T_INIT; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_CFG7(l)); + + val = CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP | + CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_CFG8(l)); + + val = CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_CFG9(l)); + + val = CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_TEST_IMP(l)); + + val = CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL; + writel_relaxed(val, csi2phy->base + + CSIPHY_3PH_LNn_CSI_LANE_CTRL15(l)); + } + + val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_CFG1(l)); + + if (regs->generation == GEN1_660) + val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660; + else + val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_CFG4(l)); + + val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE; + writel_relaxed(val, csi2phy->base + CSIPHY_3PH_LNn_MISC1(l)); +} + +static bool is_x1e80100_cphy(struct mipi_csi2phy_device *csi2phy, + const struct mipi_csi2phy_stream_cfg *cfg) +{ + return csi2phy->soc_cfg == &mipi_csi2_dphy_4nm_x1e && + cfg->mode == PHY_MODE_MIPI_CPHY && + cfg->cphy_trio == 0 && + cfg->num_data_lanes == 1 && + cfg->link_freq == + (s64)csi2phy->soc_cfg->cphy_symbol_rate; +} + +static void x1e80100_cphy_write(struct mipi_csi2phy_device *csi2phy, + const struct x1e80100_cphy_reg *table, + unsigned int num_entries) +{ + unsigned int i; + + might_sleep(); + + for (i = 0; i < num_entries; i++) { + u32 delay_us; + + /* writel() preserves the ordering seen at the runtime MMIO writer. */ + writel(table[i].reg_data, csi2phy->base + table[i].reg_addr); + + if (!table[i].delay_ns) + continue; + + /* The observed writer floors nanoseconds and enforces a 1 us minimum. */ + delay_us = max_t(u32, table[i].delay_ns / NSEC_PER_USEC, 1); + if (delay_us <= 50) + udelay(delay_us); + else + usleep_range(delay_us, + delay_us + max(delay_us / 100, 10U)); + } +} + +static void x1e80100_cphy_clear_irq(struct mipi_csi2phy_device *csi2phy) +{ + unsigned int i; + + /* The IRQ-clear table contains only zero or 100 ns observed delays. */ + for (i = 0; i < ARRAY_SIZE(x1e80100_cphy_irq_clear); i++) { + u32 delay_us; + + writel(x1e80100_cphy_irq_clear[i].reg_data, + csi2phy->base + x1e80100_cphy_irq_clear[i].reg_addr); + + if (!x1e80100_cphy_irq_clear[i].delay_ns) + continue; + + delay_us = max_t(u32, + x1e80100_cphy_irq_clear[i].delay_ns / + NSEC_PER_USEC, 1); + udelay(delay_us); + } +} + +static void +phy_qcom_mipi_csi2_gen2_config_lanes(struct mipi_csi2phy_device *csi2phy, + u8 settle_cnt) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + const struct mipi_csi2phy_lane_regs *r = regs->init_seq; + int i, array_size = regs->lane_array_size; + u32 val; + + for (i = 0; i < array_size; i++, r++) { + switch (r->mipi_csi2phy_param_type) { + case CSIPHY_SETTLE_CNT_LOWER_BYTE: + val = settle_cnt & 0xff; + break; + case CSIPHY_SKEW_CAL: + /* TODO: support application of skew from dt flag */ + continue; + case CSIPHY_DNP_PARAMS: + continue; + default: + val = r->reg_data; + break; + } + writel_relaxed(val, csi2phy->base + r->reg_addr); + if (r->delay_us) + udelay(r->delay_us); + } +} + +static bool phy_qcom_mipi_csi2_is_gen2(struct mipi_csi2phy_device *csi2phy) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + + return regs->generation == GEN2; +} + +static int +phy_qcom_mipi_csi2_cphy_lanes_enable(struct mipi_csi2phy_device *csi2phy, + struct mipi_csi2phy_stream_cfg *cfg) +{ + if (!is_x1e80100_cphy(csi2phy, cfg)) + return -EOPNOTSUPP; + + BUILD_BUG_ON(ARRAY_SIZE(x1e80100_cphy_reset) != 2); + BUILD_BUG_ON(ARRAY_SIZE(x1e80100_cphy_toggle) != 6); + BUILD_BUG_ON(ARRAY_SIZE(x1e80100_cphy_common) != 9); + BUILD_BUG_ON(ARRAY_SIZE(x1e80100_cphy_config) != 121); + BUILD_BUG_ON(ARRAY_SIZE(x1e80100_cphy_irq_clear) != 24); + BUILD_BUG_ON(ARRAY_SIZE(x1e80100_cphy_shutdown) != 3); + + dev_dbg(csi2phy->dev, + "enable X1E80100 C-PHY sequence at %lu symbols/s\n", + csi2phy->soc_cfg->cphy_symbol_rate); + x1e80100_cphy_write(csi2phy, x1e80100_cphy_reset, + ARRAY_SIZE(x1e80100_cphy_reset)); + x1e80100_cphy_write(csi2phy, x1e80100_cphy_toggle, + ARRAY_SIZE(x1e80100_cphy_toggle)); + x1e80100_cphy_write(csi2phy, x1e80100_cphy_common, + ARRAY_SIZE(x1e80100_cphy_common)); + x1e80100_cphy_write(csi2phy, x1e80100_cphy_config, + ARRAY_SIZE(x1e80100_cphy_config)); + + return 0; +} + +static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *csi2phy, + struct mipi_csi2phy_stream_cfg *cfg) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + struct mipi_csi2phy_lanes_cfg *lane_cfg = &cfg->lane_cfg; + u8 settle_cnt; + u8 val; + int i; + + if (cfg->mode == PHY_MODE_MIPI_CPHY) { + if (!phy_qcom_mipi_csi2_is_gen2(csi2phy)) + return -EOPNOTSUPP; + + return phy_qcom_mipi_csi2_cphy_lanes_enable(csi2phy, cfg); + } + + settle_cnt = phy_qcom_mipi_csi2_settle_cnt_calc(cfg->link_freq, csi2phy->timer_clk_rate); + + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + for (i = 0; i < cfg->num_data_lanes; i++) + val |= BIT(lane_cfg->data[i].pos * 2); + + writel_relaxed(val, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5)); + + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; + writel_relaxed(val, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); + + val = 0x02; + writel_relaxed(val, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 7)); + + val = 0x00; + writel_relaxed(val, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 0)); + + if (phy_qcom_mipi_csi2_is_gen2(csi2phy)) + phy_qcom_mipi_csi2_gen2_config_lanes(csi2phy, settle_cnt); + else + phy_qcom_mipi_csi2_gen1_config_lanes(csi2phy, cfg, settle_cnt); + + /* IRQ_MASK registers - disable all interrupts */ + for (i = 11; i < 22; i++) { + writel_relaxed(0, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i)); + } + + return 0; +} + +static void +phy_qcom_mipi_csi2_lanes_disable(struct mipi_csi2phy_device *csi2phy, + struct mipi_csi2phy_stream_cfg *cfg) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + + if (is_x1e80100_cphy(csi2phy, cfg)) { + x1e80100_cphy_write(csi2phy, x1e80100_cphy_shutdown, + ARRAY_SIZE(x1e80100_cphy_shutdown)); + return; + } + + writel_relaxed(0, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5)); + + writel_relaxed(0, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); +} + +static int phy_qcom_mipi_csi2_init(struct mipi_csi2phy_device *csi2phy) +{ + return 0; +} + +const struct mipi_csi2phy_hw_ops phy_qcom_mipi_csi2_ops_3ph_1_0 = { + .hw_version_read = phy_qcom_mipi_csi2_hw_version_read, + .reset = phy_qcom_mipi_csi2_reset, + .lanes_enable = phy_qcom_mipi_csi2_lanes_enable, + .lanes_disable = phy_qcom_mipi_csi2_lanes_disable, + .isr = phy_qcom_mipi_csi2_isr, + .init = phy_qcom_mipi_csi2_init, +}; + +const struct mipi_csi2phy_clk_freq zero = { 0 }; + +const struct mipi_csi2phy_clk_freq dphy_4nm_x1e_csiphy = { + .freq = { + 300000000, 400000000, 480000000 + }, + .num_freq = 3, +}; + +const struct mipi_csi2phy_clk_freq dphy_4nm_x1e_csiphy_timer = { + .freq = { + 266666667, 400000000 + }, + .num_freq = 2, +}; + +const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { + .ops = &phy_qcom_mipi_csi2_ops_3ph_1_0, + .reg_info = { + .init_seq = lane_regs_x1e80100, + .lane_array_size = ARRAY_SIZE(lane_regs_x1e80100), + .offset = 0x1000, + .generation = GEN2, + }, + .cphy_symbol_rate = X1E80100_CPHY_SYMBOL_RATE, + .cphy_trio_mask = BIT(0), + .supply_names = (const char *[]){ + "vdda-0p8", + "vdda-1p2" + }, + .num_supplies = 2, + .clk_names = (const char *[]) { + "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer" + }, + .num_clk = 4, + .clk_freq = { + zero, + zero, + dphy_4nm_x1e_csiphy, + dphy_4nm_x1e_csiphy_timer, + }, +}; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c new file mode 100644 index 00000000000000..9603eacd183545 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025, Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "phy-qcom-mipi-csi2.h" + +#define CAMSS_CLOCK_MARGIN_NUMERATOR 105 +#define CAMSS_CLOCK_MARGIN_DENOMINATOR 100 + +static inline void phy_qcom_mipi_csi2_add_clock_margin(u64 *rate) +{ + *rate *= CAMSS_CLOCK_MARGIN_NUMERATOR; + *rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR); +} + +static int +phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy, + s64 link_freq) +{ + const struct mipi_csi2phy_soc_cfg *soc_cfg = csi2phy->soc_cfg; + struct device *dev = csi2phy->dev; + int i, j; + int ret; + + for (i = 0; i < soc_cfg->num_clk; i++) { + const struct mipi_csi2phy_clk_freq *clk_freq = &soc_cfg->clk_freq[i]; + const char *clk_name = soc_cfg->clk_names[i]; + struct clk *clk = csi2phy->clks[i].clk; + u64 min_rate = link_freq / 4; + long round_rate; + + /* Use the conservative maximum clock vote for C-PHY. */ + if (csi2phy->stream_cfg.mode == PHY_MODE_MIPI_CPHY) + min_rate = 0; + + phy_qcom_mipi_csi2_add_clock_margin(&min_rate); + + /* This clock should be enabled only not set */ + if (!clk_freq->num_freq) + continue; + + for (j = 0; j < clk_freq->num_freq; j++) + if (min_rate < clk_freq->freq[j]) + break; + + if (j == clk_freq->num_freq) { + dev_err(dev, + "Pixel clock %llu is too high for %s\n", + min_rate, clk_name); + return -EINVAL; + } + + /* if sensor pixel clock is not available + * set highest possible CSIPHY clock rate + */ + if (min_rate == 0) + j = clk_freq->num_freq - 1; + + round_rate = clk_round_rate(clk, clk_freq->freq[j]); + if (round_rate < 0) { + dev_err(dev, "clk round rate failed: %ld\n", + round_rate); + return -EINVAL; + } + + csi2phy->timer_clk_rate = round_rate; + + dev_dbg(dev, "set clk %s %lu Hz\n", + clk_name, round_rate); + + ret = clk_set_rate(clk, csi2phy->timer_clk_rate); + if (ret < 0) { + dev_err(dev, "clk set rate failed: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int phy_qcom_mipi_csi2_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct mipi_csi2phy_device *csi2phy = phy_get_drvdata(phy); + + switch (mode) { + case PHY_MODE_MIPI_DPHY: + return submode ? -EINVAL : 0; + case PHY_MODE_MIPI_CPHY: + if (submode < 0 || submode >= BITS_PER_LONG) + return -EINVAL; + if (!csi2phy->soc_cfg->cphy_symbol_rate || + !(csi2phy->soc_cfg->cphy_trio_mask & BIT(submode))) + return -EOPNOTSUPP; + + csi2phy->stream_cfg.cphy_trio = submode; + return 0; + default: + return -EINVAL; + } +} + +static int phy_qcom_mipi_csi2_configure(struct phy *phy, + union phy_configure_opts *opts) +{ + struct mipi_csi2phy_device *csi2phy = phy_get_drvdata(phy); + struct phy_configure_opts_mipi_dphy *dphy_cfg_opts = &opts->mipi_dphy; + struct mipi_csi2phy_stream_cfg *stream_cfg = &csi2phy->stream_cfg; + enum phy_mode mode = phy_get_mode(phy); + int ret; + int i; + + if (mode == PHY_MODE_MIPI_CPHY) { + /* + * Until generic C-PHY options exist, the consumer carries the + * symbol rate in hs_clk_rate and the number of trios in lanes. + */ + if (dphy_cfg_opts->lanes != 1 || !dphy_cfg_opts->hs_clk_rate) + return -EINVAL; + if (dphy_cfg_opts->hs_clk_rate != + csi2phy->soc_cfg->cphy_symbol_rate) + return -EOPNOTSUPP; + + stream_cfg->mode = mode; + stream_cfg->combo_mode = 1; + stream_cfg->link_freq = dphy_cfg_opts->hs_clk_rate; + stream_cfg->num_data_lanes = dphy_cfg_opts->lanes; + + return 0; + } + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + ret = phy_mipi_dphy_config_validate(dphy_cfg_opts); + if (ret) + return ret; + + if (dphy_cfg_opts->lanes < 1 || dphy_cfg_opts->lanes > CSI2_MAX_DATA_LANES) + return -EINVAL; + + stream_cfg->mode = mode; + stream_cfg->combo_mode = 0; + stream_cfg->link_freq = dphy_cfg_opts->hs_clk_rate; + stream_cfg->num_data_lanes = dphy_cfg_opts->lanes; + + /* + * phy_configure_opts_mipi_dphy.lanes starts from zero to + * the maximum number of enabled lanes. + * + * TODO: add support for bitmask of enabled lanes and polarities + * of those lanes to the phy_configure_opts_mipi_dphy struct. + * For now take the polarities as zero and the position as fixed + * this is fine as no current upstream implementation maps otherwise. + */ + for (i = 0; i < stream_cfg->num_data_lanes; i++) { + stream_cfg->lane_cfg.data[i].pol = 0; + stream_cfg->lane_cfg.data[i].pos = i; + } + + stream_cfg->lane_cfg.clk.pol = 0; + stream_cfg->lane_cfg.clk.pos = 7; + + return 0; +} + +static int phy_qcom_mipi_csi2_power_on(struct phy *phy) +{ + struct mipi_csi2phy_device *csi2phy = phy_get_drvdata(phy); + const struct mipi_csi2phy_hw_ops *ops = csi2phy->soc_cfg->ops; + struct device *dev = &phy->dev; + int ret; + + ret = regulator_bulk_enable(csi2phy->soc_cfg->num_supplies, + csi2phy->supplies); + if (ret) + return ret; + + ret = phy_qcom_mipi_csi2_set_clock_rates(csi2phy, csi2phy->stream_cfg.link_freq); + if (ret) + goto disable_regulators; + + ret = clk_bulk_prepare_enable(csi2phy->soc_cfg->num_clk, + csi2phy->clks); + if (ret) { + dev_err(dev, "failed to enable clocks, %d\n", ret); + goto disable_regulators; + } + + enable_irq(csi2phy->irq); + ops->reset(csi2phy); + ops->hw_version_read(csi2phy); + + ret = ops->lanes_enable(csi2phy, &csi2phy->stream_cfg); + if (!ret) + return 0; + + disable_irq(csi2phy->irq); + clk_bulk_disable_unprepare(csi2phy->soc_cfg->num_clk, + csi2phy->clks); + +disable_regulators: + regulator_bulk_disable(csi2phy->soc_cfg->num_supplies, + csi2phy->supplies); + + return ret; +} + +static int phy_qcom_mipi_csi2_power_off(struct phy *phy) +{ + struct mipi_csi2phy_device *csi2phy = phy_get_drvdata(phy); + const struct mipi_csi2phy_hw_ops *ops = csi2phy->soc_cfg->ops; + + /* Shut the receiver down while its register interface is still clocked. */ + ops->lanes_disable(csi2phy, &csi2phy->stream_cfg); + disable_irq(csi2phy->irq); + + clk_bulk_disable_unprepare(csi2phy->soc_cfg->num_clk, + csi2phy->clks); + regulator_bulk_disable(csi2phy->soc_cfg->num_supplies, + csi2phy->supplies); + + return 0; +} + +static const struct phy_ops phy_qcom_mipi_csi2_ops = { + .configure = phy_qcom_mipi_csi2_configure, + .power_on = phy_qcom_mipi_csi2_power_on, + .power_off = phy_qcom_mipi_csi2_power_off, + .set_mode = phy_qcom_mipi_csi2_set_mode, + .owner = THIS_MODULE, +}; + +static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) +{ + unsigned int i, num_clk, num_supplies; + struct mipi_csi2phy_device *csi2phy; + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct phy *generic_phy; + int ret; + + csi2phy = devm_kzalloc(dev, sizeof(*csi2phy), GFP_KERNEL); + if (!csi2phy) + return -ENOMEM; + + csi2phy->dev = dev; + csi2phy->soc_cfg = device_get_match_data(&pdev->dev); + + if (!csi2phy->soc_cfg) + return -EINVAL; + + num_clk = csi2phy->soc_cfg->num_clk; + csi2phy->clks = devm_kzalloc(dev, sizeof(*csi2phy->clks) * num_clk, GFP_KERNEL); + if (!csi2phy->clks) + return -ENOMEM; + + for (i = 0; i < num_clk; i++) + csi2phy->clks[i].id = csi2phy->soc_cfg->clk_names[i]; + + ret = devm_clk_bulk_get(dev, num_clk, csi2phy->clks); + if (ret) { + dev_err(dev, "Failed to get clocks %d\n", ret); + return ret; + } + + num_supplies = csi2phy->soc_cfg->num_supplies; + csi2phy->supplies = devm_kzalloc(dev, sizeof(*csi2phy->supplies) * num_supplies, + GFP_KERNEL); + if (!csi2phy->supplies) + return -ENOMEM; + + for (i = 0; i < num_supplies; i++) + csi2phy->supplies[i].supply = csi2phy->soc_cfg->supply_names[i]; + + ret = devm_regulator_bulk_get(dev, num_supplies, csi2phy->supplies); + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); + + csi2phy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(csi2phy->base)) + return PTR_ERR(csi2phy->base); + + csi2phy->irq = platform_get_irq(pdev, 0); + if (csi2phy->irq < 0) + return csi2phy->irq; + + ret = devm_request_irq(dev, csi2phy->irq, csi2phy->soc_cfg->ops->isr, + IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, + dev_name(dev), csi2phy); + if (ret) + return dev_err_probe(dev, ret, "failed to request IRQ\n"); + + generic_phy = devm_phy_create(dev, NULL, &phy_qcom_mipi_csi2_ops); + if (IS_ERR(generic_phy)) { + ret = PTR_ERR(generic_phy); + dev_err(dev, "failed to create phy, %d\n", ret); + return ret; + } + csi2phy->phy = generic_phy; + + phy_set_drvdata(generic_phy, csi2phy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_dbg(dev, "Registered MIPI CSI2 PHY device\n"); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = { + { .compatible = "qcom,x1e80100-mipi-csi2-combo-phy", .data = &mipi_csi2_dphy_4nm_x1e }, + { } +}; +MODULE_DEVICE_TABLE(of, phy_qcom_mipi_csi2_of_match_table); + +static struct platform_driver phy_qcom_mipi_csi2_driver = { + .probe = phy_qcom_mipi_csi2_probe, + .driver = { + .name = "qcom-mipi-csi2-phy", + .of_match_table = phy_qcom_mipi_csi2_of_match_table, + }, +}; + +module_platform_driver(phy_qcom_mipi_csi2_driver); + +MODULE_DESCRIPTION("Qualcomm MIPI CSI2 PHY driver"); +MODULE_DESCRIPTION("Bryan O'Donoghue "); +MODULE_LICENSE("GPL"); diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-cphy-x1e80100.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-cphy-x1e80100.h new file mode 100644 index 00000000000000..370f0abcf5170d --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-cphy-x1e80100.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Qualcomm X1E80100 C-PHY register observations. + * + * These address/value/delay triples were independently transcribed from + * runtime WinDbg MMIO observations on the maintainer's own Surface Pro 11 + * while its front camera was streaming. They are hardware observations, not + * copied vendor source, decompiled output, or an extracted binary payload. + * Delays retain the observed nanosecond argument passed to the common writer. + */ +struct x1e80100_cphy_reg { + u32 reg_addr; + u32 reg_data; + u32 delay_ns; +}; + +static const struct x1e80100_cphy_reg x1e80100_cphy_reset[] = { + { 0x1000, 0x01, 0x00000014 }, + { 0x1000, 0x00, 0x00000000 }, +}; + +static const struct x1e80100_cphy_reg x1e80100_cphy_toggle[] = { + { 0x025c, 0x10, 0x00000064 }, + { 0x025c, 0x00, 0x00000000 }, + { 0x065c, 0x10, 0x00000064 }, + { 0x065c, 0x00, 0x00000000 }, + { 0x0a5c, 0x10, 0x00000064 }, + { 0x0a5c, 0x00, 0x00000000 }, +}; + +static const struct x1e80100_cphy_reg x1e80100_cphy_common[] = { + { 0x1084, 0x00, 0x00000000 }, + { 0x108c, 0x00, 0x000003e8 }, + { 0x02f0, 0x00, 0x00000000 }, + { 0x06f0, 0x00, 0x00000000 }, + { 0x0af0, 0x00, 0x00000000 }, + { 0x1014, 0x02, 0x00000000 }, + { 0x101c, 0x7a, 0x00000000 }, + { 0x1018, 0x01, 0x00000000 }, + { 0x101c, 0x7a, 0x00000000 }, +}; + +static const struct x1e80100_cphy_reg x1e80100_cphy_config[] = { + { 0x0268, 0xf1, 0x00 }, + { 0x0294, 0x01, 0x00 }, + { 0x0278, 0x20, 0x00 }, + { 0x0288, 0x20, 0x00 }, + { 0x026c, 0x3d, 0x00 }, + { 0x028c, 0x30, 0x00 }, + { 0x0270, 0x00, 0x00 }, + { 0x0274, 0x03, 0x00 }, + { 0x0668, 0xf1, 0x00 }, + { 0x0694, 0x01, 0x00 }, + { 0x0678, 0x20, 0x00 }, + { 0x0688, 0x20, 0x00 }, + { 0x066c, 0x3d, 0x00 }, + { 0x068c, 0x30, 0x00 }, + { 0x0670, 0x00, 0x00 }, + { 0x0674, 0x03, 0x00 }, + { 0x0a68, 0xf1, 0x00 }, + { 0x0a94, 0x01, 0x00 }, + { 0x0a78, 0x20, 0x00 }, + { 0x0a88, 0x20, 0x00 }, + { 0x0a6c, 0x3d, 0x00 }, + { 0x0a8c, 0x30, 0x00 }, + { 0x0a70, 0x00, 0x00 }, + { 0x0a74, 0x03, 0x00989680 }, + { 0x0294, 0x09, 0x00000000 }, + { 0x02f4, 0x00, 0x00000000 }, + { 0x02f8, 0x00, 0x00000000 }, + { 0x02fc, 0x00, 0x00000000 }, + { 0x02f0, 0xef, 0x000f4240 }, + { 0x0694, 0x09, 0x00000000 }, + { 0x06f4, 0x00, 0x00000000 }, + { 0x06f8, 0x00, 0x00000000 }, + { 0x06fc, 0x00, 0x00000000 }, + { 0x06f0, 0xef, 0x00000000 }, + { 0x0a94, 0x09, 0x00000000 }, + { 0x0af4, 0x00, 0x00000000 }, + { 0x0af8, 0x00, 0x00000000 }, + { 0x0afc, 0x00, 0x00000000 }, + { 0x0af0, 0xef, 0x00989680 }, + { 0x020c, 0x22, 0x00 }, + { 0x0208, 0x00, 0x00 }, + { 0x0210, 0x00, 0x00 }, + { 0x0214, 0x00, 0x00 }, + { 0x0204, 0x00, 0x00 }, + { 0x02e4, 0x00, 0x00 }, + { 0x02e8, 0x7f, 0x00 }, + { 0x02ec, 0x7f, 0x00 }, + { 0x0218, 0x3e, 0x00 }, + { 0x021c, 0x41, 0x00 }, + { 0x0220, 0x41, 0x00 }, + { 0x0224, 0x7f, 0x00 }, + { 0x0228, 0x00, 0x00 }, + { 0x022c, 0x00, 0x00 }, + { 0x0264, 0x01, 0x00 }, + { 0x0244, 0xb2, 0x00 }, + { 0x0310, 0x35, 0x00 }, + { 0x02bc, 0xd0, 0x00 }, + { 0x0254, 0x00, 0x00 }, + { 0x0240, 0x00, 0x00 }, + { 0x0260, 0xa8, 0x00 }, + { 0x0284, 0x00, 0x00 }, + { 0x0290, 0x02, 0x00 }, + { 0x060c, 0x22, 0x00 }, + { 0x0608, 0x00, 0x00 }, + { 0x0610, 0x00, 0x00 }, + { 0x0614, 0x00, 0x00 }, + { 0x0604, 0x00, 0x00 }, + { 0x06e4, 0x00, 0x00 }, + { 0x06e8, 0x7f, 0x00 }, + { 0x06ec, 0x7f, 0x00 }, + { 0x0618, 0x3e, 0x00 }, + { 0x061c, 0x41, 0x00 }, + { 0x0620, 0x41, 0x00 }, + { 0x0624, 0x7f, 0x00 }, + { 0x0628, 0x00, 0x00 }, + { 0x062c, 0x00, 0x00 }, + { 0x0664, 0x01, 0x00 }, + { 0x0644, 0xb2, 0x00 }, + { 0x0710, 0x35, 0x00 }, + { 0x06bc, 0xd0, 0x00 }, + { 0x0654, 0x00, 0x00 }, + { 0x0640, 0x00, 0x00 }, + { 0x0660, 0xa8, 0x00 }, + { 0x0684, 0x00, 0x00 }, + { 0x0690, 0x02, 0x00 }, + { 0x0a0c, 0x22, 0x00 }, + { 0x0a08, 0x00, 0x00 }, + { 0x0a10, 0x00, 0x00 }, + { 0x0a14, 0x00, 0x00 }, + { 0x0a00, 0x00, 0x00 }, + { 0x0a04, 0x00, 0x00 }, + { 0x0ae4, 0x00, 0x00 }, + { 0x0ae8, 0x7f, 0x00 }, + { 0x0aec, 0x7f, 0x00 }, + { 0x0a18, 0x3e, 0x00 }, + { 0x0a1c, 0x41, 0x00 }, + { 0x0a20, 0x41, 0x00 }, + { 0x0a24, 0x7f, 0x00 }, + { 0x0a28, 0x00, 0x00 }, + { 0x0a2c, 0x00, 0x00 }, + { 0x0a64, 0x01, 0x00 }, + { 0x0a44, 0xb2, 0x00 }, + { 0x0b10, 0x35, 0x00 }, + { 0x0abc, 0xd0, 0x00 }, + { 0x0a54, 0x00, 0x00 }, + { 0x0a40, 0x00, 0x00 }, + { 0x0a60, 0xa8, 0x00 }, + { 0x0a84, 0x00, 0x00 }, + { 0x0a90, 0x02, 0x00 }, + { 0x102c, 0xff, 0x00 }, + { 0x1030, 0xfe, 0x00 }, + { 0x1034, 0xe2, 0x00 }, + { 0x1038, 0xdf, 0x00 }, + { 0x103c, 0x5f, 0x00 }, + { 0x1040, 0xfc, 0x00 }, + { 0x1044, 0xfb, 0x00 }, + { 0x1048, 0x8b, 0x00 }, + { 0x104c, 0x7f, 0x00 }, + { 0x1050, 0xbf, 0x00 }, + { 0x1054, 0xff, 0x00 }, + { 0x1000, 0x0e, 0x00 }, +}; + +static const struct x1e80100_cphy_reg x1e80100_cphy_irq_clear[] = { + { 0x1058, 0xff, 0x00000000 }, + { 0x105c, 0xff, 0x00000000 }, + { 0x1060, 0xff, 0x00000000 }, + { 0x1064, 0xff, 0x00000000 }, + { 0x1068, 0xff, 0x00000000 }, + { 0x106c, 0xff, 0x00000000 }, + { 0x1070, 0xff, 0x00000000 }, + { 0x1074, 0xff, 0x00000000 }, + { 0x1078, 0xff, 0x00000000 }, + { 0x107c, 0xff, 0x00000000 }, + { 0x1080, 0xff, 0x00000064 }, + { 0x1028, 0x01, 0x00000064 }, + { 0x1058, 0x00, 0x00000000 }, + { 0x105c, 0x00, 0x00000000 }, + { 0x1060, 0x00, 0x00000000 }, + { 0x1064, 0x00, 0x00000000 }, + { 0x1068, 0x00, 0x00000000 }, + { 0x106c, 0x00, 0x00000000 }, + { 0x1070, 0x00, 0x00000000 }, + { 0x1074, 0x00, 0x00000000 }, + { 0x1078, 0x00, 0x00000000 }, + { 0x107c, 0x00, 0x00000000 }, + { 0x1080, 0x00, 0x00000064 }, + { 0x1028, 0x00, 0x00000064 }, +}; + +static const struct x1e80100_cphy_reg x1e80100_cphy_shutdown[] = { + { 0x1014, 0x00, 0x00000000 }, + { 0x101c, 0x00, 0x00000000 }, + { 0x1018, 0x00, 0x00000000 }, +}; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h new file mode 100644 index 00000000000000..3ab856bba880b8 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * + * Qualcomm MIPI CSI2 CPHY/DPHY driver + * + * Copyright (C) 2025 Linaro Ltd. + */ +#ifndef __PHY_QCOM_MIPI_CSI2_H__ +#define __PHY_QCOM_MIPI_CSI2_H__ + +#include + +#define CSI2_MAX_DATA_LANES 4 + +struct mipi_csi2phy_lane { + u8 pos; + u8 pol; +}; + +struct mipi_csi2phy_lanes_cfg { + struct mipi_csi2phy_lane data[CSI2_MAX_DATA_LANES]; + struct mipi_csi2phy_lane clk; +}; + +struct mipi_csi2phy_stream_cfg { + enum phy_mode mode; + u8 combo_mode; + u8 cphy_trio; + s64 link_freq; + u8 num_data_lanes; + struct mipi_csi2phy_lanes_cfg lane_cfg; +}; + +struct mipi_csi2phy_device; + +struct mipi_csi2phy_hw_ops { + void (*hw_version_read)(struct mipi_csi2phy_device *csi2phy_dev); + void (*reset)(struct mipi_csi2phy_device *csi2phy_dev); + int (*lanes_enable)(struct mipi_csi2phy_device *csi2phy_dev, + struct mipi_csi2phy_stream_cfg *cfg); + void (*lanes_disable)(struct mipi_csi2phy_device *csi2phy_dev, + struct mipi_csi2phy_stream_cfg *cfg); + irqreturn_t (*isr)(int irq, void *dev); + int (*init)(struct mipi_csi2phy_device *csi2phy_dev); +}; + +struct mipi_csi2phy_lane_regs { + const s32 reg_addr; + const s32 reg_data; + const u32 delay_us; + const u32 mipi_csi2phy_param_type; +}; + +struct mipi_csi2phy_device_regs { + const struct mipi_csi2phy_lane_regs *init_seq; + const int lane_array_size; + const u32 offset; + enum { + GEN1 = 0, + GEN1_660, + GEN1_670, + GEN2, + } generation; +}; + +#define MAX_CSI2PHY_CLKS 8 +struct mipi_csi2phy_clk_freq { + u32 num_freq; + u32 freq[MAX_CSI2PHY_CLKS]; +}; + +struct mipi_csi2phy_soc_cfg { + const struct mipi_csi2phy_hw_ops *ops; + const struct mipi_csi2phy_device_regs reg_info; + const unsigned long cphy_symbol_rate; + const unsigned long cphy_trio_mask; + + const char ** const supply_names; + const unsigned int num_supplies; + + const char ** const clk_names; + const unsigned int num_clk; + + const struct mipi_csi2phy_clk_freq clk_freq[]; +}; + +struct mipi_csi2phy_device { + struct device *dev; + + struct phy *phy; + void __iomem *base; + int irq; + + struct clk_bulk_data *clks; + struct regulator_bulk_data *supplies; + u32 timer_clk_rate; + + const struct mipi_csi2phy_soc_cfg *soc_cfg; + struct mipi_csi2phy_stream_cfg stream_cfg; + + u32 hw_version; +}; + +extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e; + +#endif /* __PHY_QCOM_MIPI_CSI2_H__ */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index cdcfad2e86b1d3..2ebaa16a1f7ef5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -22,6 +22,7 @@ #include #include #include +#include "../../usb/typec/mux.h" #include @@ -4429,6 +4430,9 @@ static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, struct qmp_combo *qmp = typec_switch_get_drvdata(sw); const struct qmp_phy_cfg *cfg = qmp->cfg; + /* print out call parameter */ + printk(KERN_INFO "%s: qmp_combo_switch_set() enter new_orientation=%d, altmode=%d, orientation=%d\n", dev_name(&sw->dev),orientation,qmp->dp_powered_on,qmp->orientation); + if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) return 0; @@ -4448,6 +4452,9 @@ static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, } mutex_unlock(&qmp->phy_mutex); + /* print out result */ + printk(KERN_INFO "%s: qmp_combo_switch_set() exit new_orientation=%d, altmode=%d, orientation=%d\n", dev_name(&sw->dev),orientation,qmp->dp_powered_on,qmp->orientation); + return 0; } @@ -4458,6 +4465,9 @@ static int qmp_combo_typec_mux_set(struct typec_mux_dev *mux, struct typec_mux_s enum qmpphy_mode new_mode; unsigned int svid; + /* print out call parameter */ + printk(KERN_INFO "%s: qmp_combo_mux_set() enter mode=%d, altmode=%d\n", dev_name(&mux->dev),(int)state->mode,qmp->dp_powered_on); + guard(mutex)(&qmp->phy_mutex); if (state->alt) @@ -4531,6 +4541,9 @@ static int qmp_combo_typec_mux_set(struct typec_mux_dev *mux, struct typec_mux_s } } + /* print out result */ + printk(KERN_INFO "%s: qmp_combo_mux_set() exit mode=%d, new_mode=%d, altmode=%d\n", dev_name(&mux->dev),(int)state->mode,(int)new_mode,qmp->dp_powered_on); + return 0; } @@ -4765,6 +4778,12 @@ static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phand return ERR_PTR(-EINVAL); } +static const char * const qmpphy_mode_str[] = { + [QMPPHY_MODE_USB3DP] = "usb3+dp", + [QMPPHY_MODE_DP_ONLY] = "dp", + [QMPPHY_MODE_USB3_ONLY] = "usb3", +}; + static void qmp_combo_find_lanes_orientation(const struct qmp_combo_lane_mapping *mapping, unsigned int mapping_count, u32 *lanes, unsigned int lanes_count, @@ -4849,7 +4868,8 @@ static int qmp_combo_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *dp_np, *usb_np; struct phy_provider *phy_provider; - int ret; + int ret, i; + bool explicit_mode = false; qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); if (!qmp) @@ -4896,11 +4916,26 @@ static int qmp_combo_probe(struct platform_device *pdev) qmp->qmpphy_mode = QMPPHY_MODE_USB3DP; + /* Replace with DT provided mode */ + if (of_find_property(dev->of_node, "qcom,combo-initial-mode", NULL)) { + for (i = 0; i < ARRAY_SIZE(qmpphy_mode_str); ++i) { + ret = of_property_match_string(dev->of_node, "qcom,combo-initial-mode", + qmpphy_mode_str[i]); + if (!ret) { + qmp->qmpphy_mode = i; + explicit_mode = true; + break; + } + } + } + if (of_property_present(dev->of_node, "mode-switch") || of_property_present(dev->of_node, "orientation-switch")) { ret = qmp_combo_typec_register(qmp); if (ret) goto err_node_put; + } else if (explicit_mode) { + dev_dbg(dev, "Static explicit mode %s enabled\n", qmpphy_mode_str[qmp->qmpphy_mode]); } else { enum typec_orientation dp_orientation = TYPEC_ORIENTATION_NONE; enum typec_orientation usb3_orientation = TYPEC_ORIENTATION_NONE; @@ -4934,15 +4969,15 @@ static int qmp_combo_probe(struct platform_device *pdev) if (ret) goto err_node_put; + /* + * Enable runtime PM support, but forbid it by default. + * Users can allow it again via the power/control attribute in sysfs. + */ pm_runtime_set_active(dev); + pm_runtime_forbid(dev); ret = devm_pm_runtime_enable(dev); if (ret) goto err_node_put; - /* - * Prevent runtime pm from being ON by default. Users can enable - * it using power/control in sysfs. - */ - pm_runtime_forbid(dev); ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); if (ret) diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig index e32e01b2a9bdd9..7a364e40faead2 100644 --- a/drivers/platform/arm64/Kconfig +++ b/drivers/platform/arm64/Kconfig @@ -33,6 +33,18 @@ config EC_ACER_ASPIRE1 laptop where this information is not properly exposed via the standard ACPI devices. +config EC_DELL_XPS + tristate "Dell XPS 9345 Embedded Controller driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on I2C + depends on IIO + help + Driver for the Embedded Controller in the Qualcomm Snapdragon-based + Dell XPS 13 9345, which handles thermal management and fan speed + control. + + Say M or Y here to include this support. + config EC_HUAWEI_GAOKUN tristate "Huawei Matebook E Go Embedded Controller driver" depends on ARCH_QCOM || COMPILE_TEST @@ -103,4 +115,16 @@ config EC_QCOM_HAMOA This driver currently supports Hamoa/Purwa/Glymur reference devices. +config EC_LENOVO_YOGA_SLIM7X + tristate "Lenovo Yoga Slim 7x Embedded Controller driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on I2C + help + Select this option to enable driver for the EC found in the Lenovo + Yoga Slim 7x. + + This driver currently supports reporting input event for microphone + mute button, and reporting device suspend to the EC so it can take + appropriate actions. + endif # ARM64_PLATFORM_DEVICES diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile index 7681be4a46e94e..affb7c14de3715 100644 --- a/drivers/platform/arm64/Makefile +++ b/drivers/platform/arm64/Makefile @@ -6,7 +6,9 @@ # obj-$(CONFIG_EC_ACER_ASPIRE1) += acer-aspire1-ec.o +obj-$(CONFIG_EC_DELL_XPS) += dell-xps-ec.o obj-$(CONFIG_EC_HUAWEI_GAOKUN) += huawei-gaokun-ec.o obj-$(CONFIG_EC_LENOVO_YOGA_C630) += lenovo-yoga-c630.o obj-$(CONFIG_EC_LENOVO_THINKPAD_T14S) += lenovo-thinkpad-t14s.o obj-$(CONFIG_EC_QCOM_HAMOA) += qcom-hamoa-ec.o +obj-$(CONFIG_EC_LENOVO_YOGA_SLIM7X) += lenovo-yoga-slim7x.o diff --git a/drivers/platform/arm64/dell-xps-ec.c b/drivers/platform/arm64/dell-xps-ec.c new file mode 100644 index 00000000000000..5ea8f30931d8b6 --- /dev/null +++ b/drivers/platform/arm64/dell-xps-ec.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026, Aleksandrs Vinarskis + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DELL_XPS_EC_SUSPEND_CMD 0xb9 +#define DELL_XPS_EC_SUSPEND_MSG_LEN 64 + +#define DELL_XPS_EC_TEMP_CMD0 0xfb +#define DELL_XPS_EC_TEMP_CMD1 0x20 +#define DELL_XPS_EC_TEMP_CMD3 0x02 +#define DELL_XPS_EC_TEMP_MSG_LEN 6 +#define DELL_XPS_EC_TEMP_INTERVAL_MS 100 + +/* + * Format: + * - header/unknown (2 bytes) + * - per-thermistor entries (3 bytes): thermistor_id, param1, param2 + */ +static const u8 dell_xps_ec_thermistor_profile[] = { + 0xff, 0x54, + 0x01, 0x00, 0x2b, /* sys_therm0 */ + 0x02, 0x44, 0x2a, /* sys_therm1 */ + 0x03, 0x44, 0x2b, /* sys_therm2 */ + 0x04, 0x44, 0x28, /* sys_therm3 */ + 0x05, 0x55, 0x2a, /* sys_therm4 */ + 0x06, 0x44, 0x26, /* sys_therm5 */ + 0x07, 0x44, 0x2b, /* sys_therm6 */ +}; + +/* + * Mapping from IIO channel name to EC command byte + */ +static const struct { + const char *name; + u8 cmd; +} dell_xps_ec_therms[] = { + /* TODO: 0x01 is sent only occasionally, likely TZ98 or TZ4 */ + { "sys_therm0", 0x02 }, + { "sys_therm1", 0x03 }, + { "sys_therm2", 0x04 }, + { "sys_therm3", 0x05 }, + { "sys_therm4", 0x06 }, + { "sys_therm5", 0x07 }, + { "sys_therm6", 0x08 }, +}; + +struct dell_xps_ec { + struct device *dev; + struct i2c_client *client; + struct iio_channel *therm_channels[ARRAY_SIZE(dell_xps_ec_therms)]; + struct delayed_work temp_work; +}; + +static int dell_xps_ec_suspend_cmd(struct dell_xps_ec *ec, bool suspend) +{ + u8 buf[DELL_XPS_EC_SUSPEND_MSG_LEN] = {}; + int ret; + + buf[0] = DELL_XPS_EC_SUSPEND_CMD; + buf[1] = suspend ? 0x01 : 0x00; + /* bytes 2..63 remain zero */ + + ret = i2c_master_send(ec->client, buf, sizeof(buf)); + if (ret < 0) + return ret; + + return 0; +} + +static int dell_xps_ec_send_temp(struct dell_xps_ec *ec, u8 cmd_byte, + int milli_celsius) +{ + u8 buf[DELL_XPS_EC_TEMP_MSG_LEN]; + u16 deci_celsius; + int ret; + + /* Convert milli-Celsius to deci-Celsius (Celsius * 10) */ + deci_celsius = milli_celsius / 100; + + buf[0] = DELL_XPS_EC_TEMP_CMD0; + buf[1] = DELL_XPS_EC_TEMP_CMD1; + buf[2] = cmd_byte; + buf[3] = DELL_XPS_EC_TEMP_CMD3; + buf[4] = deci_celsius & 0xff; /* LSB */ + buf[5] = (deci_celsius >> 8) & 0xff; /* MSB */ + + ret = i2c_master_send(ec->client, buf, sizeof(buf)); + if (ret < 0) + return ret; + + return 0; +} + +static void dell_xps_ec_temp_work_fn(struct work_struct *work) +{ + struct dell_xps_ec *ec = container_of(work, struct dell_xps_ec, + temp_work.work); + int val, ret, i; + + for (i = 0; i < ARRAY_SIZE(dell_xps_ec_therms); i++) { + if (!ec->therm_channels[i]) + continue; + + ret = iio_read_channel_processed(ec->therm_channels[i], &val); + if (ret < 0) { + dev_err_ratelimited(ec->dev, + "Failed to read thermistor %s: %d\n", + dell_xps_ec_therms[i].name, ret); + continue; + } + + ret = dell_xps_ec_send_temp(ec, dell_xps_ec_therms[i].cmd, val); + if (ret < 0) { + dev_err_ratelimited(ec->dev, + "Failed to send temp for %s: %d\n", + dell_xps_ec_therms[i].name, ret); + } + } + + schedule_delayed_work(&ec->temp_work, + msecs_to_jiffies(DELL_XPS_EC_TEMP_INTERVAL_MS)); +} + +static irqreturn_t dell_xps_ec_irq_handler(int irq, void *data) +{ + struct dell_xps_ec *ec = data; + + /* + * TODO: IRQ is fired on lid-close. Follow Windows example to read out + * the thermistor thresholds and potentially fan speeds. + */ + dev_info_ratelimited(ec->dev, "IRQ triggered! (irq=%d)\n", irq); + + return IRQ_HANDLED; +} + +static int dell_xps_ec_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct dell_xps_ec *ec; + int ret, i; + + ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL); + if (!ec) + return -ENOMEM; + + ec->dev = dev; + ec->client = client; + i2c_set_clientdata(client, ec); + + /* Set default thermistor profile */ + ret = i2c_master_send(client, dell_xps_ec_thermistor_profile, + sizeof(dell_xps_ec_thermistor_profile)); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to set thermistor profile\n"); + + /* Get IIO channels for thermistors */ + for (i = 0; i < ARRAY_SIZE(dell_xps_ec_therms); i++) { + ec->therm_channels[i] = devm_iio_channel_get(dev, + dell_xps_ec_therms[i].name); + if (IS_ERR(ec->therm_channels[i])) { + ret = PTR_ERR(ec->therm_channels[i]); + ec->therm_channels[i] = NULL; + if (ret == -EPROBE_DEFER) + return ret; + dev_warn(dev, "Thermistor %s not available: %d\n", + dell_xps_ec_therms[i].name, ret); + } + } + + /* Start periodic temperature reporting */ + ret = devm_delayed_work_autocancel(dev, &ec->temp_work, + dell_xps_ec_temp_work_fn); + if (ret) + return ret; + schedule_delayed_work(&ec->temp_work, + msecs_to_jiffies(DELL_XPS_EC_TEMP_INTERVAL_MS)); + dev_info(dev, "Started periodic temperature reporting to EC every %d ms\n", + DELL_XPS_EC_TEMP_INTERVAL_MS); + + /* Request IRQ for EC events */ + ret = devm_request_threaded_irq(dev, client->irq, NULL, + dell_xps_ec_irq_handler, + IRQF_ONESHOT, dev_name(dev), ec); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to request IRQ\n"); + + return 0; +} + +/* + * Notify EC of suspend + * + * This will: + * - Ramp down the fans + * - Cut power to display/trackpad/keyboard/touch row + * - Periodically (?) power them back, such that wake-up source still works + */ +static int dell_xps_ec_suspend(struct device *dev) +{ + struct dell_xps_ec *ec = dev_get_drvdata(dev); + + cancel_delayed_work_sync(&ec->temp_work); + + return dell_xps_ec_suspend_cmd(ec, true); +} + +/* + * Notify EC of resume + * + * This will undo the suspend actions + * Without the resume signal, device would wake up but be forced back into + * suspend by EC within seconds + */ +static int dell_xps_ec_resume(struct device *dev) +{ + struct dell_xps_ec *ec = dev_get_drvdata(dev); + int ret; + + ret = dell_xps_ec_suspend_cmd(ec, false); + if (ret) + return ret; + + schedule_delayed_work(&ec->temp_work, + msecs_to_jiffies(DELL_XPS_EC_TEMP_INTERVAL_MS)); + return 0; +} + +static const struct of_device_id dell_xps_ec_of_match[] = { + { .compatible = "dell,xps13-9345-ec" }, + {} +}; +MODULE_DEVICE_TABLE(of, dell_xps_ec_of_match); + +static const struct i2c_device_id dell_xps_ec_i2c_id[] = { + { "dell-xps-ec" }, + {} +}; +MODULE_DEVICE_TABLE(i2c, dell_xps_ec_i2c_id); + +static const struct dev_pm_ops dell_xps_ec_pm_ops = { + SYSTEM_SLEEP_PM_OPS(dell_xps_ec_suspend, dell_xps_ec_resume) +}; + +static struct i2c_driver dell_xps_ec_driver = { + .driver = { + .name = "dell-xps-ec", + .of_match_table = dell_xps_ec_of_match, + .pm = &dell_xps_ec_pm_ops, + }, + .probe = dell_xps_ec_probe, + .id_table = dell_xps_ec_i2c_id, +}; +module_i2c_driver(dell_xps_ec_driver); + +MODULE_AUTHOR("Aleksandrs Vinarskis "); +MODULE_DESCRIPTION("Dell XPS 13 9345 Embedded Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/platform/arm64/lenovo-thinkpad-t14s.c b/drivers/platform/arm64/lenovo-thinkpad-t14s.c index e7acb66b77f22e..36bedf8f762f47 100644 --- a/drivers/platform/arm64/lenovo-thinkpad-t14s.c +++ b/drivers/platform/arm64/lenovo-thinkpad-t14s.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -67,6 +68,16 @@ #define T14S_EC_EVT_KEY_FN_F11 0x7a #define T14S_EC_EVT_KEY_FN_G 0x7e +#define T14S_EC_SYS_THERM0 0x78 /* SoC (CPU+GPU) */ +#define T14S_EC_SYS_THERM1 0x79 /* Keyboard */ +#define T14S_EC_SYS_THERM2 0x7a /* Back cover */ +#define T14S_EC_SYS_THERM3 0x7b /* Charger / PMIC */ +#define T14S_EC_SYS_THERM6 0x7c /* QTM West */ +#define T14S_EC_SYS_THERM7 0x7d /* SSD */ + +#define T14S_EC_FAN_RPM_LSB 0x84 +#define T14S_EC_FAN_RPM_MSB 0x85 + /* Hardware LED blink rate is 1 Hz (500ms off, 500ms on) */ #define T14S_EC_BLINK_RATE_ON_OFF_MS 500 @@ -93,9 +104,22 @@ struct t14s_ec_led_classdev { struct t14s_ec *ec; }; +struct t14s_ec_hwmon_sys_thermx { + const char *label; + int reg; + u8 event; +}; + +struct t14s_ec_hwmon { + struct device *dev; + struct t14s_ec_hwmon_sys_thermx *sys_thermx; + size_t num_sys_thermx; +}; + struct t14s_ec { struct regmap *regmap; struct device *dev; + struct t14s_ec_hwmon ec_hwmon; struct t14s_ec_led_classdev led_pwr_btn; struct t14s_ec_led_classdev led_chrg_orange; struct t14s_ec_led_classdev led_chrg_white; @@ -472,6 +496,20 @@ static int t14s_input_probe(struct t14s_ec *ec) return input_register_device(ec->inputdev); } +static void t14s_ec_hwmon_notify_event(struct t14s_ec *ec, u8 event) +{ + for (int i = 0; i < ec->ec_hwmon.num_sys_thermx; i++) { + if (ec->ec_hwmon.sys_thermx[i].event != event) + continue; + + hwmon_notify_event(ec->ec_hwmon.dev, hwmon_temp, + hwmon_temp_alarm, i); + + dev_dbg(ec->dev, "Thermal Zone (%s) Status Change Event\n", + ec->ec_hwmon.sys_thermx[i].label); + } +} + static irqreturn_t t14s_ec_irq_handler(int irq, void *data) { struct t14s_ec *ec = data; @@ -521,13 +559,9 @@ static irqreturn_t t14s_ec_irq_handler(int irq, void *data) dev_dbg(ec->dev, "LID closed\n"); break; case T14S_EC_EVT_THERMAL_TZ40: - dev_dbg(ec->dev, "Thermal Zone 40 Status Change Event (CPU/GPU)\n"); - break; case T14S_EC_EVT_THERMAL_TZ42: - dev_dbg(ec->dev, "Thermal Zone 42 Status Change Event (Battery)\n"); - break; case T14S_EC_EVT_THERMAL_TZ39: - dev_dbg(ec->dev, "Thermal Zone 39 Status Change Event (CPU/GPU)\n"); + t14s_ec_hwmon_notify_event(ec, val); break; case T14S_EC_EVT_KEY_FN_G: dev_dbg(ec->dev, "FN + G - toggle double-tapping\n"); @@ -555,6 +589,151 @@ static irqreturn_t t14s_ec_irq_handler(int irq, void *data) return IRQ_HANDLED; } +static umode_t t14s_ec_hwmon_is_visible(const void *drvdata, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_temp: + return 0444; + case hwmon_fan: + return 0444; + default: + return 0; + } +} + +static int t14s_ec_hwmon_read_string(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + struct t14s_ec *ec = dev_get_drvdata(dev); + switch (type) { + case hwmon_temp: + if (attr == hwmon_temp_label) { + *str = ec->ec_hwmon.sys_thermx[channel].label; + return 0; + } + break; + default: + return -EOPNOTSUPP; + } + + return -EOPNOTSUPP; +} + +static int t14s_ec_hwmon_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct t14s_ec *ec = dev_get_drvdata(dev); + unsigned int value; + int ret; + + switch (type) { + case hwmon_temp: + if (attr == hwmon_temp_input) { + ret = t14s_ec_read(ec, ec->ec_hwmon.sys_thermx[channel].reg, &value); + if (ret) + return ret; + *val = value * 1000; + + return 0; + } + break; + + case hwmon_fan: + if (attr == hwmon_fan_input) { + int lsb, msb; + ret = t14s_ec_read(ec, T14S_EC_FAN_RPM_LSB, &lsb); + if (ret) + return ret; + + ret = t14s_ec_read(ec, T14S_EC_FAN_RPM_MSB, &msb); + if (ret) + return ret; + + *val = 0; + *val = lsb + (msb << 8); + + return 0; + } + break; + default: + break; + } + + return -EOPNOTSUPP; +} + +static const struct hwmon_ops t14s_ec_hwmon_ops = { + .is_visible = t14s_ec_hwmon_is_visible, + .read = t14s_ec_hwmon_read, + .read_string = t14s_ec_hwmon_read_string, +}; + +static const struct hwmon_channel_info *t14s_ec_hwmon_info[] = { + HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL), + HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT), + NULL +}; + +static const struct hwmon_chip_info t14s_ec_chip_info = { + .ops = &t14s_ec_hwmon_ops, + .info = t14s_ec_hwmon_info, +}; + +static int t14s_ec_hwmon_probe(struct t14s_ec *ec) +{ + struct t14s_ec_hwmon_sys_thermx sys_thermx[] = { + { + .label = "soc", + .reg = T14S_EC_SYS_THERM0, + .event = T14S_EC_EVT_THERMAL_TZ39 + }, + { + .label = "keyboard", + .reg = T14S_EC_SYS_THERM1, + .event = T14S_EC_EVT_THERMAL_TZ40 + }, + { + .label = "base", + .reg = T14S_EC_SYS_THERM2, + }, + { + .label = "pmbm", + .reg = T14S_EC_SYS_THERM3, + .event = T14S_EC_EVT_THERMAL_TZ42 + }, + { + .label = "qtm", + .reg = T14S_EC_SYS_THERM6 + }, + { + .label = "ssd", + .reg = T14S_EC_SYS_THERM7 + }, + }; + + ec->ec_hwmon.sys_thermx = devm_kmemdup_array(ec->dev, sys_thermx, + ARRAY_SIZE(sys_thermx), + sizeof(sys_thermx[0]), GFP_KERNEL); + if (!ec->ec_hwmon.sys_thermx) + return -ENOMEM; + + ec->ec_hwmon.num_sys_thermx = ARRAY_SIZE(sys_thermx); + + ec->ec_hwmon.dev = devm_hwmon_device_register_with_info(ec->dev, "t14s_ec", ec, + &t14s_ec_chip_info, NULL); + + return PTR_ERR_OR_ZERO(ec->ec_hwmon.dev); +} + static int t14s_ec_probe(struct i2c_client *client) { struct device *dev = &client->dev; @@ -590,6 +769,10 @@ static int t14s_ec_probe(struct i2c_client *client) if (ret < 0) return ret; + ret = t14s_ec_hwmon_probe(ec); + if (ret < 0) + return ret; + ret = devm_request_threaded_irq(dev, client->irq, NULL, t14s_ec_irq_handler, IRQF_ONESHOT, dev_name(dev), ec); diff --git a/drivers/platform/arm64/lenovo-yoga-slim7x.c b/drivers/platform/arm64/lenovo-yoga-slim7x.c new file mode 100644 index 00000000000000..8f6d523395bcba --- /dev/null +++ b/drivers/platform/arm64/lenovo-yoga-slim7x.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Maya Matuszczyk + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include + +// These are the registers that i know about available from SMBUS +#define EC_IRQ_REASON_REG 0x05 +#define EC_SUSPEND_RESUME_REG 0x23 +#define EC_IRQ_ENABLE_REG 0x35 +#define EC_BACKLIGHT_STATUS_REG 0x83 +#define EC_MIC_MUTE_LED_REG 0x84 +#define EC_AC_STATUS_REG 0x90 + +// Valid values for EC_SUSPEND_RESUME_REG +#define EC_NOTIFY_SUSPEND_ENTER 0x01 +#define EC_NOTIFY_SUSPEND_EXIT 0x00 +#define EC_NOTIFY_SCREEN_OFF 0x03 +#define EC_NOTIFY_SCREEN_ON 0x04 + +// These are the values in EC_IRQ_REASON_REG that i could find in DSDT +#define EC_IRQ_MICMUTE_BUTTON 0x04 +#define EC_IRQ_FAN1_STATUS_CHANGE 0x30 +#define EC_IRQ_FAN2_STATUS_CHANGE 0x31 +#define EC_IRQ_FAN1_SPEED_CHANGE 0x32 +#define EC_IRQ_FAN2_SPEED_CHANGE 0x33 +#define EC_IRQ_COMPLETED_LUT_UPDATE 0x34 +#define EC_IRQ_COMPLETED_FAN_PROFILE_SWITCH 0x35 +#define EC_IRQ_THERMISTOR_1_TEMP_THRESHOLD_CROSS 0x36 +#define EC_IRQ_THERMISTOR_2_TEMP_THRESHOLD_CROSS 0x37 +#define EC_IRQ_THERMISTOR_3_TEMP_THRESHOLD_CROSS 0x38 +#define EC_IRQ_THERMISTOR_4_TEMP_THRESHOLD_CROSS 0x39 +#define EC_IRQ_THERMISTOR_5_TEMP_THRESHOLD_CROSS 0x3a +#define EC_IRQ_THERMISTOR_6_TEMP_THRESHOLD_CROSS 0x3b +#define EC_IRQ_THERMISTOR_7_TEMP_THRESHOLD_CROSS 0x3c +#define EC_IRQ_RECOVERED_FROM_RESET 0x3d +#define EC_IRQ_LENOVO_SUPPORT_KEY 0x90 +#define EC_IRQ_FN_Q 0x91 +#define EC_IRQ_FN_M 0x92 +#define EC_IRQ_FN_SPACE 0x93 +#define EC_IRQ_FN_R 0x94 +#define EC_IRQ_FNLOCK_ON 0x95 +#define EC_IRQ_FNLOCK_OFF 0x96 +#define EC_IRQ_FN_N 0x97 +#define EC_IRQ_AI 0x9a +#define EC_IRQ_NPU 0x9b + +struct yoga_slim7x_ec { + struct i2c_client *client; + struct input_dev *idev; + struct mutex lock; +}; + +static irqreturn_t yoga_slim7x_ec_irq(int irq, void *data) +{ + struct yoga_slim7x_ec *ec = data; + struct device *dev = &ec->client->dev; + int val; + + guard(mutex)(&ec->lock); + + val = i2c_smbus_read_byte_data(ec->client, EC_IRQ_REASON_REG); + if (val < 0) { + dev_err(dev, "Failed to get EC IRQ reason: %d\n", val); + return IRQ_HANDLED; + } + + switch (val) { + case EC_IRQ_MICMUTE_BUTTON: + input_report_key(ec->idev, KEY_MICMUTE, 1); + input_sync(ec->idev); + input_report_key(ec->idev, KEY_MICMUTE, 0); + input_sync(ec->idev); + break; + default: + dev_info(dev, "Unhandled EC IRQ reason: %d\n", val); + } + + return IRQ_HANDLED; +} + +static int yoga_slim7x_ec_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct yoga_slim7x_ec *ec; + int ret; + + ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL); + if (!ec) + return -ENOMEM; + + mutex_init(&ec->lock); + ec->client = client; + + ec->idev = devm_input_allocate_device(dev); + if (!ec->idev) + return -ENOMEM; + ec->idev->name = "yoga-slim7x-ec"; + ec->idev->phys = "yoga-slim7x-ec/input0"; + input_set_capability(ec->idev, EV_KEY, KEY_MICMUTE); + + ret = input_register_device(ec->idev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to register input device\n"); + + ret = devm_request_threaded_irq(dev, client->irq, + NULL, yoga_slim7x_ec_irq, + IRQF_ONESHOT, "yoga_slim7x_ec", ec); + if (ret < 0) + return dev_err_probe(dev, ret, "Unable to request irq\n"); + + ret = i2c_smbus_write_byte_data(client, EC_IRQ_ENABLE_REG, 0x01); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to enable interrupts\n"); + + return 0; +} + +static void yoga_slim7x_ec_remove(struct i2c_client *client) +{ + struct device *dev = &client->dev; + int ret; + + ret = i2c_smbus_write_byte_data(client, EC_IRQ_ENABLE_REG, 0x00); + if (ret < 0) + dev_err(dev, "Failed to disable interrupts: %d\n", ret); +} + +static int yoga_slim7x_ec_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + int ret; + + ret = i2c_smbus_write_byte_data(client, EC_SUSPEND_RESUME_REG, EC_NOTIFY_SCREEN_OFF); + if (ret) + return ret; + + ret = i2c_smbus_write_byte_data(client, EC_SUSPEND_RESUME_REG, EC_NOTIFY_SUSPEND_ENTER); + if (ret) + return ret; + + return 0; +} + +static int yoga_slim7x_ec_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + int ret; + + ret = i2c_smbus_write_byte_data(client, EC_SUSPEND_RESUME_REG, EC_NOTIFY_SUSPEND_EXIT); + if (ret) + return ret; + + ret = i2c_smbus_write_byte_data(client, EC_SUSPEND_RESUME_REG, EC_NOTIFY_SCREEN_ON); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id yoga_slim7x_ec_of_match[] = { + { .compatible = "lenovo,yoga-slim7x-ec" }, + {} +}; +MODULE_DEVICE_TABLE(of, yoga_slim7x_ec_of_match); + +static const struct i2c_device_id yoga_slim7x_ec_i2c_id_table[] = { + { "yoga-slim7x-ec", }, + {} +}; +MODULE_DEVICE_TABLE(i2c, yoga_slim7x_ec_i2c_id_table); + +static DEFINE_SIMPLE_DEV_PM_OPS(yoga_slim7x_ec_pm_ops, + yoga_slim7x_ec_suspend, + yoga_slim7x_ec_resume); + +static struct i2c_driver yoga_slim7x_ec_i2c_driver = { + .driver = { + .name = "yoga-slim7x-ec", + .of_match_table = yoga_slim7x_ec_of_match, + .pm = &yoga_slim7x_ec_pm_ops + }, + .probe = yoga_slim7x_ec_probe, + .remove = yoga_slim7x_ec_remove, + .id_table = yoga_slim7x_ec_i2c_id_table, +}; +module_i2c_driver(yoga_slim7x_ec_i2c_driver); + +MODULE_DESCRIPTION("Lenovo Yoga Slim 7x Embedded Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/platform/surface/aggregator/controller.c b/drivers/platform/surface/aggregator/controller.c index 6a8430cb9cbfe1..507fb922281826 100644 --- a/drivers/platform/surface/aggregator/controller.c +++ b/drivers/platform/surface/aggregator/controller.c @@ -1155,7 +1155,7 @@ static int ssam_controller_caps_load_from_of(struct device *dev, struct ssam_con * Every device starting with Surface Pro X through Laptop 7 uses these * identical values, which makes them good defaults. */ - caps->d3_closes_handle = true; + caps->d3_closes_handle = false; caps->screen_on_sleep_idle_timeout = 5000; caps->screen_off_sleep_idle_timeout = 30; caps->ssh_buffer_size = 48; diff --git a/drivers/platform/surface/surface_aggregator_registry.c b/drivers/platform/surface/surface_aggregator_registry.c index d37a7e4c6b02a6..aef0b5d1c42ca1 100644 --- a/drivers/platform/surface/surface_aggregator_registry.c +++ b/drivers/platform/surface/surface_aggregator_registry.c @@ -89,6 +89,19 @@ static const struct software_node ssam_node_tmp_perf_profile_with_fan = { .properties = ssam_node_tmp_perf_profile_has_fan, }; +/* Platform profile device for SP11, with a fan and low-power default. */ +static const struct property_entry ssam_node_tmp_perf_profile_sp11_props[] = { + PROPERTY_ENTRY_BOOL("has_fan"), + PROPERTY_ENTRY_BOOL("default-low-power"), + { } +}; + +static const struct software_node ssam_node_tmp_perf_profile_sp11 = { + .name = "ssam:01:03:01:00:01", + .parent = &ssam_node_root, + .properties = ssam_node_tmp_perf_profile_sp11_props, +}; + /* Thermal sensors. */ static const struct software_node ssam_node_tmp_sensors = { .name = "ssam:01:03:01:00:02", @@ -410,6 +423,8 @@ static const struct software_node *ssam_node_group_sp11[] = { &ssam_node_hub_kip, &ssam_node_bat_ac, &ssam_node_bat_main, + &ssam_node_tmp_perf_profile_sp11, + &ssam_node_fan_speed, &ssam_node_tmp_sensors, &ssam_node_hid_kip_keyboard, &ssam_node_hid_kip_penstash, diff --git a/drivers/platform/surface/surface_platform_profile.c b/drivers/platform/surface/surface_platform_profile.c index 0e479e35e66e16..5dce1877f14b6c 100644 --- a/drivers/platform/surface/surface_platform_profile.c +++ b/drivers/platform/surface/surface_platform_profile.c @@ -6,14 +6,21 @@ * Copyright (C) 2021-2022 Maximilian Luz */ -#include +#include +#include #include #include +#include #include +#include +#include #include +#include #include +#define SSAM_PROFILE_POWER_SAVER_MAX_FREQ_KHZ 2515000 + // Enum for the platform performance profile sent to the TMP module. enum ssam_tmp_profile { SSAM_TMP_PROFILE_NORMAL = 1, @@ -41,6 +48,18 @@ struct ssam_tmp_profile_info { struct ssam_platform_profile_device { struct ssam_device *sdev; struct device *ppdev; + struct cpufreq_policy **cpufreq_policies; + struct freq_qos_request *freq_qos_reqs; + unsigned int *freq_cap_khz; + struct mutex freq_qos_lock; + int num_policies; + bool freq_capped; +#if IS_ENABLED(CONFIG_CPU_FREQ) + struct notifier_block cpufreq_nb; +#endif +#if IS_ENABLED(CONFIG_POWER_SUPPLY) + struct notifier_block power_supply_nb; +#endif bool has_fan; }; @@ -88,6 +107,109 @@ static int ssam_fan_profile_set(struct ssam_device *sdev, enum ssam_fan_profile return ssam_retry(__ssam_fan_profile_set, sdev->ctrl, &profile); } +static unsigned int ssam_find_cap_freq(struct cpufreq_policy *policy, + unsigned int ceiling_khz) +{ + struct cpufreq_frequency_table *entry; + unsigned int cap_freq = 0; + + if (!policy->freq_table) + return ceiling_khz; + + cpufreq_for_each_valid_entry(entry, policy->freq_table) { + if (entry->frequency <= ceiling_khz && + entry->frequency > cap_freq) + cap_freq = entry->frequency; + } + + return cap_freq ?: ceiling_khz; +} + +static unsigned int +ssam_platform_profile_cap_freq(struct cpufreq_policy *policy) +{ + unsigned int max_freq; + + down_read(&policy->rwsem); + max_freq = ssam_find_cap_freq(policy, + SSAM_PROFILE_POWER_SAVER_MAX_FREQ_KHZ); + up_read(&policy->rwsem); + + return max_freq; +} + +static int +ssam_platform_profile_apply_freq_cap(struct ssam_platform_profile_device *tpd, + enum platform_profile_option profile) +{ + struct cpufreq_policy *policy; + bool capped; + int i, status; + + switch (profile) { + case PLATFORM_PROFILE_LOW_POWER: + capped = true; + break; + case PLATFORM_PROFILE_BALANCED: + case PLATFORM_PROFILE_BALANCED_PERFORMANCE: + case PLATFORM_PROFILE_PERFORMANCE: + capped = false; + break; + default: + return -EOPNOTSUPP; + } + + mutex_lock(&tpd->freq_qos_lock); + + if (tpd->freq_capped == capped) { + mutex_unlock(&tpd->freq_qos_lock); + return 0; + } + + for (i = 0; i < num_possible_cpus(); i++) { + unsigned int max_freq; + + policy = tpd->cpufreq_policies[i]; + if (!policy) + continue; + + max_freq = capped ? tpd->freq_cap_khz[i] : + FREQ_QOS_MAX_DEFAULT_VALUE; + status = freq_qos_update_request(&tpd->freq_qos_reqs[i], + max_freq); + if (status < 0) + goto rollback; + } + + tpd->freq_capped = capped; + mutex_unlock(&tpd->freq_qos_lock); + return 0; + +rollback: + dev_err(&tpd->sdev->dev, + "failed to update CPU frequency cap for policy %u: %d\n", + policy->cpu, status); + + while (--i >= 0) { + unsigned int max_freq; + + policy = tpd->cpufreq_policies[i]; + if (!policy) + continue; + + max_freq = tpd->freq_capped ? tpd->freq_cap_khz[i] : + FREQ_QOS_MAX_DEFAULT_VALUE; + if (freq_qos_update_request(&tpd->freq_qos_reqs[i], + max_freq) < 0) + dev_warn(&tpd->sdev->dev, + "failed to roll back CPU frequency cap for policy %u\n", + policy->cpu); + } + + mutex_unlock(&tpd->freq_qos_lock); + return status; +} + static int convert_ssam_tmp_to_profile(struct ssam_device *sdev, enum ssam_tmp_profile p) { switch (p) { @@ -109,7 +231,6 @@ static int convert_ssam_tmp_to_profile(struct ssam_device *sdev, enum ssam_tmp_p } } - static int convert_profile_to_ssam_tmp(struct ssam_device *sdev, enum platform_profile_option p) { switch (p) { @@ -175,14 +296,12 @@ static int ssam_platform_profile_get(struct device *dev, return 0; } -static int ssam_platform_profile_set(struct device *dev, - enum platform_profile_option profile) +static int +ssam_platform_profile_set_internal(struct ssam_platform_profile_device *tpd, + enum platform_profile_option profile) { - struct ssam_platform_profile_device *tpd; int tp; - tpd = dev_get_drvdata(dev); - tp = convert_profile_to_ssam_tmp(tpd->sdev, profile); if (tp < 0) return tp; @@ -196,9 +315,17 @@ static int ssam_platform_profile_set(struct device *dev, if (tp < 0) return tp; tp = ssam_fan_profile_set(tpd->sdev, tp); + if (tp < 0) + return tp; } - return tp; + return ssam_platform_profile_apply_freq_cap(tpd, profile); +} + +static int ssam_platform_profile_set(struct device *dev, + enum platform_profile_option profile) +{ + return ssam_platform_profile_set_internal(dev_get_drvdata(dev), profile); } static int ssam_platform_profile_probe(void *drvdata, unsigned long *choices) @@ -217,23 +344,316 @@ static const struct platform_profile_ops ssam_platform_profile_ops = { .profile_set = ssam_platform_profile_set, }; +static void +ssam_platform_profile_remove_freq_qos(struct ssam_platform_profile_device *tpd) +{ + int i; + + mutex_lock(&tpd->freq_qos_lock); + for (i = 0; i < num_possible_cpus(); i++) { + if (!tpd->cpufreq_policies[i]) + continue; + + if (freq_qos_request_active(&tpd->freq_qos_reqs[i])) + freq_qos_remove_request(&tpd->freq_qos_reqs[i]); + cpufreq_cpu_put(tpd->cpufreq_policies[i]); + tpd->cpufreq_policies[i] = NULL; + tpd->freq_cap_khz[i] = 0; + } + + tpd->num_policies = 0; + tpd->freq_capped = false; + mutex_unlock(&tpd->freq_qos_lock); +} + +static int +ssam_platform_profile_add_policy(struct ssam_platform_profile_device *tpd, + struct cpufreq_policy *policy, + unsigned int cap_freq) +{ + unsigned int max_freq; + int free_slot = -1; + int i, status; + + mutex_lock(&tpd->freq_qos_lock); + + for (i = 0; i < num_possible_cpus(); i++) { + if (tpd->cpufreq_policies[i] == policy) { + mutex_unlock(&tpd->freq_qos_lock); + cpufreq_cpu_put(policy); + return 0; + } + + if (!tpd->cpufreq_policies[i] && free_slot < 0) + free_slot = i; + } + + if (free_slot < 0) { + status = -ENOSPC; + goto err_unlock; + } + + max_freq = tpd->freq_capped ? cap_freq : FREQ_QOS_MAX_DEFAULT_VALUE; + status = freq_qos_add_request(&policy->constraints, + &tpd->freq_qos_reqs[free_slot], + FREQ_QOS_MAX, max_freq); + if (status < 0) + goto err_unlock; + + tpd->cpufreq_policies[free_slot] = policy; + tpd->freq_cap_khz[free_slot] = cap_freq; + tpd->num_policies++; + mutex_unlock(&tpd->freq_qos_lock); + + return 0; + +err_unlock: + mutex_unlock(&tpd->freq_qos_lock); + cpufreq_cpu_put(policy); + return status; +} + +#if IS_ENABLED(CONFIG_CPU_FREQ) +static void +ssam_platform_profile_remove_policy(struct ssam_platform_profile_device *tpd, + struct cpufreq_policy *policy) +{ + int i; + + mutex_lock(&tpd->freq_qos_lock); + for (i = 0; i < num_possible_cpus(); i++) { + if (tpd->cpufreq_policies[i] != policy) + continue; + + if (freq_qos_request_active(&tpd->freq_qos_reqs[i])) + freq_qos_remove_request(&tpd->freq_qos_reqs[i]); + cpufreq_cpu_put(tpd->cpufreq_policies[i]); + tpd->cpufreq_policies[i] = NULL; + tpd->freq_cap_khz[i] = 0; + tpd->num_policies--; + break; + } + mutex_unlock(&tpd->freq_qos_lock); +} + +static int +ssam_platform_profile_cpufreq_event(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct ssam_platform_profile_device *tpd = + container_of(nb, struct ssam_platform_profile_device, cpufreq_nb); + struct cpufreq_policy *policy = data; + unsigned int cap_freq; + unsigned int cpu; + int status; + + switch (event) { + case CPUFREQ_CREATE_POLICY: + /* The cpufreq core holds policy->rwsem for write here. */ + cap_freq = ssam_find_cap_freq(policy, + SSAM_PROFILE_POWER_SAVER_MAX_FREQ_KHZ); + cpu = policy->cpu; + policy = cpufreq_cpu_get(cpu); + if (!policy) + return NOTIFY_DONE; + + status = ssam_platform_profile_add_policy(tpd, policy, cap_freq); + if (status < 0) + dev_err(&tpd->sdev->dev, + "failed to add CPU frequency QoS request for policy %u: %d\n", + cpu, status); + break; + + case CPUFREQ_REMOVE_POLICY: + ssam_platform_profile_remove_policy(tpd, policy); + break; + } + + return NOTIFY_OK; +} + +static int +ssam_platform_profile_register_cpufreq_notifier(struct ssam_platform_profile_device *tpd) +{ + tpd->cpufreq_nb.notifier_call = ssam_platform_profile_cpufreq_event; + + return cpufreq_register_notifier(&tpd->cpufreq_nb, + CPUFREQ_POLICY_NOTIFIER); +} + +static void +ssam_platform_profile_unregister_cpufreq_notifier(struct ssam_platform_profile_device *tpd) +{ + cpufreq_unregister_notifier(&tpd->cpufreq_nb, CPUFREQ_POLICY_NOTIFIER); +} +#else +static int +ssam_platform_profile_register_cpufreq_notifier(struct ssam_platform_profile_device *tpd) +{ + return 0; +} + +static void +ssam_platform_profile_unregister_cpufreq_notifier(struct ssam_platform_profile_device *tpd) +{ +} +#endif + +static int +ssam_platform_profile_add_freq_qos(struct ssam_platform_profile_device *tpd) +{ + struct device *dev = &tpd->sdev->dev; + struct cpufreq_policy *policy; + unsigned int policy_cpu = 0; + int cpu, status; + + tpd->cpufreq_policies = devm_kcalloc(dev, num_possible_cpus(), + sizeof(*tpd->cpufreq_policies), + GFP_KERNEL); + if (!tpd->cpufreq_policies) + return -ENOMEM; + + tpd->freq_qos_reqs = devm_kcalloc(dev, num_possible_cpus(), + sizeof(*tpd->freq_qos_reqs), + GFP_KERNEL); + if (!tpd->freq_qos_reqs) + return -ENOMEM; + + tpd->freq_cap_khz = devm_kcalloc(dev, num_possible_cpus(), + sizeof(*tpd->freq_cap_khz), + GFP_KERNEL); + if (!tpd->freq_cap_khz) + return -ENOMEM; + + status = ssam_platform_profile_register_cpufreq_notifier(tpd); + if (status) + return status; + + cpus_read_lock(); + for_each_online_cpu(cpu) { + policy = cpufreq_cpu_get(cpu); + if (!policy) + continue; + + policy_cpu = policy->cpu; + status = ssam_platform_profile_add_policy(tpd, policy, + ssam_platform_profile_cap_freq(policy)); + if (status < 0) + break; + } + cpus_read_unlock(); + + if (status >= 0) + return 0; + + dev_err(dev, + "failed to add CPU frequency QoS request for policy %u: %d\n", + policy_cpu, status); + ssam_platform_profile_unregister_cpufreq_notifier(tpd); + ssam_platform_profile_remove_freq_qos(tpd); + return status; +} + +#if IS_ENABLED(CONFIG_POWER_SUPPLY) +static int +ssam_platform_profile_power_supply_event(struct notifier_block *nb, + unsigned long event, void *data) +{ + if (event != PSY_EVENT_PROP_CHANGED) + return NOTIFY_DONE; + + /* + * Keep the selected profile and frequency cap identical on AC and DC. + * AC/DC energy-performance preference differentiation is deferred until + * the SCMI cpufreq interface provides EPP support. + */ + return NOTIFY_OK; +} + +static int +ssam_platform_profile_register_power_notifier(struct ssam_platform_profile_device *tpd) +{ + tpd->power_supply_nb.notifier_call = + ssam_platform_profile_power_supply_event; + + return power_supply_reg_notifier(&tpd->power_supply_nb); +} + +static void +ssam_platform_profile_unregister_power_notifier(struct ssam_platform_profile_device *tpd) +{ + power_supply_unreg_notifier(&tpd->power_supply_nb); +} +#else +static int +ssam_platform_profile_register_power_notifier(struct ssam_platform_profile_device *tpd) +{ + return 0; +} + +static void +ssam_platform_profile_unregister_power_notifier(struct ssam_platform_profile_device *tpd) +{ +} +#endif + static int surface_platform_profile_probe(struct ssam_device *sdev) { struct ssam_platform_profile_device *tpd; + int status; tpd = devm_kzalloc(&sdev->dev, sizeof(*tpd), GFP_KERNEL); if (!tpd) return -ENOMEM; tpd->sdev = sdev; + mutex_init(&tpd->freq_qos_lock); ssam_device_set_drvdata(sdev, tpd); tpd->has_fan = device_property_read_bool(&sdev->dev, "has_fan"); - tpd->ppdev = devm_platform_profile_register(&sdev->dev, "Surface Platform Profile", - tpd, &ssam_platform_profile_ops); + status = ssam_platform_profile_add_freq_qos(tpd); + if (status) + return status; + + status = ssam_platform_profile_register_power_notifier(tpd); + if (status) + goto err_unregister_cpufreq_notifier; + + if (device_property_read_bool(&sdev->dev, "default-low-power")) { + status = ssam_platform_profile_set_internal(tpd, + PLATFORM_PROFILE_LOW_POWER); + if (status) + goto err_unregister_power_notifier; + } + + tpd->ppdev = devm_platform_profile_register(&sdev->dev, + "Surface Platform Profile", + tpd, + &ssam_platform_profile_ops); + if (IS_ERR(tpd->ppdev)) { + status = PTR_ERR(tpd->ppdev); + goto err_unregister_power_notifier; + } + + return 0; + +err_unregister_power_notifier: + ssam_platform_profile_unregister_power_notifier(tpd); +err_unregister_cpufreq_notifier: + ssam_platform_profile_unregister_cpufreq_notifier(tpd); + ssam_platform_profile_remove_freq_qos(tpd); + return status; +} + +static void surface_platform_profile_remove(struct ssam_device *sdev) +{ + struct ssam_platform_profile_device *tpd = + ssam_device_get_drvdata(sdev); - return PTR_ERR_OR_ZERO(tpd->ppdev); + ssam_platform_profile_unregister_power_notifier(tpd); + ssam_platform_profile_unregister_cpufreq_notifier(tpd); + ssam_platform_profile_remove_freq_qos(tpd); } static const struct ssam_device_id ssam_platform_profile_match[] = { @@ -244,6 +664,7 @@ MODULE_DEVICE_TABLE(ssam, ssam_platform_profile_match); static struct ssam_device_driver surface_platform_profile = { .probe = surface_platform_profile_probe, + .remove = surface_platform_profile_remove, .match_table = ssam_platform_profile_match, .driver = { .name = "surface_platform_profile", diff --git a/drivers/platform/x86/intel_ips.c b/drivers/platform/x86/intel_ips.c index b1b2d9caba7b38..72700da950b117 100644 --- a/drivers/platform/x86/intel_ips.c +++ b/drivers/platform/x86/intel_ips.c @@ -1416,6 +1416,14 @@ static const struct dmi_system_id ips_blacklist[] = { DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook"), }, }, + { + .callback = ips_blacklist_callback, + .ident = "G60JX", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "G60JX"), + }, + }, { } /* terminating entry */ }; diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qcom_battmgr.c index 490137a23d00e9..d282d969bfe924 100644 --- a/drivers/power/supply/qcom_battmgr.c +++ b/drivers/power/supply/qcom_battmgr.c @@ -349,6 +349,10 @@ static int qcom_battmgr_request(struct qcom_battmgr *battmgr, void *data, size_t battmgr->error = 0; + if (!battmgr->client) { + printk(KERN_ERR "battmgr->client is NULL"); + return -EINVAL; + } ret = pmic_glink_send(battmgr->client, data, len); if (ret < 0) return ret; diff --git a/drivers/power/supply/surface_battery.c b/drivers/power/supply/surface_battery.c index c759add4df49da..8adf02ddd98fec 100644 --- a/drivers/power/supply/surface_battery.c +++ b/drivers/power/supply/surface_battery.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -819,6 +820,10 @@ static int surface_battery_probe(struct ssam_device *sdev) const struct spwr_psy_properties *p; struct spwr_battery_device *bat; + /* Qualcomm battmgr is the authoritative battery provider on Denali. */ + if (of_machine_is_compatible("microsoft,denali")) + return -ENODEV; + p = ssam_device_get_match_data(sdev); if (!p) return -ENODEV; diff --git a/drivers/powercap/Kconfig b/drivers/powercap/Kconfig index 03c4c796d99313..e3a47c65349995 100644 --- a/drivers/powercap/Kconfig +++ b/drivers/powercap/Kconfig @@ -93,4 +93,17 @@ config DTPM_DEVFREQ help This enables support for device power limitation based on energy model. + +config QCOM_SPEL + tristate "Qualcomm SPEL Powercap driver" + depends on ARM64 || COMPILE_TEST + help + This enables support for the Qualcomm SoC Power and Electrical + Limits (SPEL) hardware, which allows power limits to be + enforced and monitored on Qualcomm SoCs. + + SPEL provides energy monitoring and power capping for multiple + domains including system, SoC, CPU clusters, GPU, and various + other subsystems. + endif diff --git a/drivers/powercap/Makefile b/drivers/powercap/Makefile index 5ab0dce565b9ac..8235fb9d3df600 100644 --- a/drivers/powercap/Makefile +++ b/drivers/powercap/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_INTEL_RAPL) += intel_rapl_msr.o obj-$(CONFIG_INTEL_RAPL_TPMI) += intel_rapl_tpmi.o obj-$(CONFIG_IDLE_INJECT) += idle_inject.o obj-$(CONFIG_ARM_SCMI_POWERCAP) += arm_scmi_powercap.o +obj-$(CONFIG_QCOM_SPEL) += qcom_spel.o diff --git a/drivers/powercap/qcom_spel.c b/drivers/powercap/qcom_spel.c new file mode 100644 index 00000000000000..4dd91cf36cccaf --- /dev/null +++ b/drivers/powercap/qcom_spel.c @@ -0,0 +1,776 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Qualcomm SPEL (SoC Power and Electrical Limits) Driver + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SPEL register bitmasks */ +#define ENERGY_STATUS_MASK GENMASK(31, 0) + +#define POWER_LIMIT_MASK GENMASK(14, 0) +#define POWER_LIMIT_ENABLE BIT(31) + +#define TIME_WINDOW_MASK_L GENMASK(14, 0) +#define TIME_WINDOW_MASK_H GENMASK(22, 16) +#define TIME_WINDOW_MAX ((FIELD_MAX(TIME_WINDOW_MASK_H) << 15) | \ + FIELD_MAX(TIME_WINDOW_MASK_L)) + +#define ENERGY_UNIT_MASK GENMASK(19, 16) +#define TIME_UNIT_MASK GENMASK(11, 8) +#define POWER_UNIT_MASK GENMASK(2, 0) + +#define LIMITS_CAPABILITY_OFFSET 0x20 +#define ENERGY_RPT_UNIT_OFFSET 0x04 + +#define ENERGY_UNIT_SCALE 1000 + +#define SPEL_DOMAIN_NAME_LENGTH 16 + +/* Domain types */ +enum spel_domain_type { + SPEL_DOMAIN_SYS, + SPEL_DOMAIN_SOC, + SPEL_DOMAIN_CL0, + SPEL_DOMAIN_CL1, + SPEL_DOMAIN_CL2, + SPEL_DOMAIN_IGPU, + SPEL_DOMAIN_DGPU, + SPEL_DOMAIN_NSP, + SPEL_DOMAIN_MMCX, + SPEL_DOMAIN_INFRA, + SPEL_DOMAIN_DRAM, + SPEL_DOMAIN_MDM, + SPEL_DOMAIN_WLAN, + SPEL_DOMAIN_USB1, + SPEL_DOMAIN_USB2, + SPEL_DOMAIN_USB3, + SPEL_DOMAIN_MAX, +}; + +/* Power limit IDs */ +enum spel_power_limit_id { + POWER_LIMIT1, + POWER_LIMIT2, + POWER_LIMIT3, + POWER_LIMIT4, + POWER_LIMITS_MAX, +}; + +/* Unit types for conversion */ +enum unit_type { + POWER_UNIT, + ENERGY_UNIT, + TIME_UNIT, +}; + +/* Power limit operation types */ +enum pl_ops_type { + PL_LIMIT, + PL_TIME_WINDOW, +}; + +static const char * const pl_names[] = { + [POWER_LIMIT1] = "pl1", + [POWER_LIMIT2] = "pl2", + [POWER_LIMIT3] = "pl3", + [POWER_LIMIT4] = "pl4", +}; + +/** + * struct spel_domain_info - Domain configuration + * @name: Domain name + * @offset: Register offset in node base + */ +struct spel_domain_info { + const char *name; + u32 offset; +}; + +/* Domain configuration */ +static const struct spel_domain_info domain_info[SPEL_DOMAIN_MAX] = { + [SPEL_DOMAIN_SYS] = { "sys", 0x40 }, + [SPEL_DOMAIN_SOC] = { "soc", 0x00 }, + [SPEL_DOMAIN_CL0] = { "cl0", 0x5c }, + [SPEL_DOMAIN_CL1] = { "cl1", 0x60 }, + [SPEL_DOMAIN_CL2] = { "cl2", 0x64 }, + [SPEL_DOMAIN_IGPU] = { "igpu", 0x08 }, + [SPEL_DOMAIN_DGPU] = { "dgpu", 0x44 }, + [SPEL_DOMAIN_NSP] = { "nsp", 0x0c }, + [SPEL_DOMAIN_MMCX] = { "mmcx", 0x10 }, + [SPEL_DOMAIN_INFRA] = { "infra", 0x18 }, + [SPEL_DOMAIN_DRAM] = { "dram", 0x1c }, + [SPEL_DOMAIN_MDM] = { "mdm", 0x48 }, + [SPEL_DOMAIN_WLAN] = { "wlan", 0x4c }, + [SPEL_DOMAIN_USB1] = { "usb1", 0x50 }, + [SPEL_DOMAIN_USB2] = { "usb2", 0x54 }, + [SPEL_DOMAIN_USB3] = { "usb3", 0x58 }, +}; + +/** + * struct spel_constraint_info - Power limit constraint information + * @limit_offset: Register offset for power limit value + * @time_window_offset: Register offset for time window + * @supported_mask: Bit mask in capability register + * @domain_id: Domain this constraint applies to + * @pl_id: Power limit ID (PL1, PL2, etc.) + */ +struct spel_constraint_info { + u32 limit_offset; + u32 time_window_offset; + u32 supported_mask; + enum spel_domain_type domain_id; + int pl_id; +}; + +/* Constraint configuration */ +static const struct spel_constraint_info constraints[] = { + /* SYS domain constraints */ + { 0x10, 0x70, BIT(0), SPEL_DOMAIN_SYS, POWER_LIMIT1 }, + { 0x14, 0x74, BIT(1), SPEL_DOMAIN_SYS, POWER_LIMIT2 }, + { 0x18, 0x78, BIT(2), SPEL_DOMAIN_SYS, POWER_LIMIT3 }, + { 0x1c, 0x7c, BIT(3), SPEL_DOMAIN_SYS, POWER_LIMIT4 }, + /* SoC domain constraints */ + { 0x00, 0x60, BIT(4), SPEL_DOMAIN_SOC, POWER_LIMIT1 }, + { 0x04, 0x64, BIT(5), SPEL_DOMAIN_SOC, POWER_LIMIT2 }, + { 0x08, 0x68, BIT(6), SPEL_DOMAIN_SOC, POWER_LIMIT3 }, + { 0x0c, 0x6c, BIT(7), SPEL_DOMAIN_SOC, POWER_LIMIT4 }, +}; + +/** + * struct spel_domain - SPEL power domain + * @power_zone: Powercap zone + * @lock: Mutex protecting register access + * @sp: Parent sys domain + * @status_reg: Energy counter register + * @name: Domain name + * @id: Domain type ID + */ +struct spel_domain { + struct powercap_zone power_zone; + struct mutex lock; /* Protects register read/write operations */ + void *sp; + void __iomem *status_reg; + char name[SPEL_DOMAIN_NAME_LENGTH]; + enum spel_domain_type id; +}; + +/** + * struct spel_system - SPEL system + * @domains: Array of domains + * @power_zone: Parent powercap zone + * @node_base: Base address for node registers + * @constraint_base: Base address for constraint registers + * @config_base: Base address for config registers + * @control_type: Powercap control type + * @dev: Device pointer for logging + * @limits: Supported power limits per domain + * @power_unit: Power unit in microWatts (common for all domains) + * @energy_unit: Energy unit in nanoJoules (common for all domains) + * @time_unit: Time unit in microseconds (common for all domains) + */ +struct spel_system { + struct spel_domain *domains; + struct powercap_zone *power_zone; + void __iomem *node_base; + void __iomem *constraint_base; + void __iomem *config_base; + struct powercap_control_type *control_type; + struct device *dev; + int limits[SPEL_DOMAIN_MAX]; + unsigned int power_unit; + unsigned int energy_unit; + unsigned int time_unit; +}; + +#define power_zone_to_spel_domain(_zone) \ + container_of(_zone, struct spel_domain, power_zone) + +static bool is_pl_valid(struct spel_domain *sd, int pl) +{ + struct spel_system *sp = sd->sp; + + return !!(sp->limits[sd->id] & BIT(pl)); +} + +static int get_pl_ops_offset(struct spel_domain *sd, int pl, enum pl_ops_type pl_op) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(constraints); i++) { + const struct spel_constraint_info *ci = &constraints[i]; + + if (ci->domain_id == sd->id && ci->pl_id == pl) { + switch (pl_op) { + case PL_LIMIT: + return ci->limit_offset; + case PL_TIME_WINDOW: + return ci->time_window_offset; + default: + return -EOPNOTSUPP; + } + } + } + + return -EOPNOTSUPP; +} + +static u64 spel_unit_xlate(struct spel_domain *sd, enum unit_type type, + u64 value, int to_raw) +{ + struct spel_system *sp = sd->sp; + u64 units, scale; + + switch (type) { + case POWER_UNIT: + units = sp->power_unit; + scale = 1; + break; + case ENERGY_UNIT: + units = sp->energy_unit; + scale = ENERGY_UNIT_SCALE; + break; + case TIME_UNIT: + units = sp->time_unit; + scale = 1; + break; + default: + return value; + } + + if (to_raw) + return DIV_ROUND_CLOSEST_ULL(value * scale, units); + + value *= units; + return div64_u64(value, scale); +} + +static int spel_read_pl_data(struct spel_domain *sd, int pl, + enum pl_ops_type pl_op, bool xlate, u64 *data) +{ + struct spel_system *sp = sd->sp; + void __iomem *reg_addr; + u64 value; + int offset; + + if (!is_pl_valid(sd, pl)) + return -EINVAL; + + offset = get_pl_ops_offset(sd, pl, pl_op); + if (offset < 0) + return offset; + + guard(mutex)(&sd->lock); + + reg_addr = sp->constraint_base + offset; + value = readl(reg_addr); + + switch (pl_op) { + case PL_LIMIT: + value = FIELD_GET(POWER_LIMIT_MASK, value); + if (xlate) + *data = spel_unit_xlate(sd, POWER_UNIT, value, 0); + else + *data = value; + break; + case PL_TIME_WINDOW: + /* Decode time window: bits [22:16] are upper 7 bits, [14:0] are lower 15 bits */ + value = (FIELD_GET(TIME_WINDOW_MASK_H, value) << 15) | + FIELD_GET(TIME_WINDOW_MASK_L, value); + if (xlate) + *data = spel_unit_xlate(sd, TIME_UNIT, value, 0); + else + *data = value; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int spel_write_pl_data(struct spel_domain *sd, int pl, + enum pl_ops_type pl_op, unsigned long long value) +{ + struct spel_system *sp = sd->sp; + void __iomem *reg_addr; + u64 reg_val, new_val; + int offset; + + if (!is_pl_valid(sd, pl)) + return -EINVAL; + + offset = get_pl_ops_offset(sd, pl, pl_op); + if (offset < 0) + return offset; + + guard(mutex)(&sd->lock); + + reg_addr = sp->constraint_base + offset; + reg_val = readl(reg_addr); + + switch (pl_op) { + case PL_LIMIT: + new_val = spel_unit_xlate(sd, POWER_UNIT, value, 1); + if (new_val > FIELD_MAX(POWER_LIMIT_MASK)) + return -EINVAL; + reg_val = (reg_val & ~POWER_LIMIT_MASK) | FIELD_PREP(POWER_LIMIT_MASK, new_val); + + /* + * Enable/Disable PL based on the value: + * - If value is 0, disable the PL (clear enable bit) + * - If value is non-zero, enable the PL (set enable bit) + */ + if (new_val == 0) + reg_val &= ~POWER_LIMIT_ENABLE; + else + reg_val |= POWER_LIMIT_ENABLE; + + writel(reg_val, reg_addr); + return 0; + + case PL_TIME_WINDOW: + /* + * Encode time window: upper 7 bits to [22:16], lower 15 bits to [14:0] + */ + new_val = spel_unit_xlate(sd, TIME_UNIT, value, 1); + if (new_val > TIME_WINDOW_MAX) + return -EINVAL; + /* Read-modify-write to preserve other bits */ + reg_val = (reg_val & ~(TIME_WINDOW_MASK_H | TIME_WINDOW_MASK_L)) | + FIELD_PREP(TIME_WINDOW_MASK_H, new_val >> 15) | + FIELD_PREP(TIME_WINDOW_MASK_L, new_val); + writel(reg_val, reg_addr); + + /* + * Time window register update doesn't trigger firmware interrupt. + * Write to the PL register with current value to trigger the interrupt. + */ + offset = get_pl_ops_offset(sd, pl, PL_LIMIT); + if (offset >= 0) { + reg_addr = sp->constraint_base + offset; + reg_val = readl(reg_addr); + writel(reg_val, reg_addr); + } + return 0; + + default: + return -EINVAL; + } +} + +static int spel_get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + u64 value; + + value = readl(sd->status_reg); + + *energy_raw = spel_unit_xlate(sd, ENERGY_UNIT, value, 0); + + return 0; +} + +static int spel_get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy) +{ + struct spel_domain *sd = power_zone_to_spel_domain(pcd_dev); + + *energy = spel_unit_xlate(sd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); + + return 0; +} + +static int spel_release_zone(struct powercap_zone *power_zone) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + struct spel_system *sp = sd->sp; + + /* Free the domains array when the last zone (SYS domain) is released */ + if (sd->id == SPEL_DOMAIN_SYS) + kfree(sp->domains); + + return 0; +} + +static int spel_find_nr_power_limit(struct spel_domain *sd) +{ + int i, nr_pl = 0; + + for (i = 0; i < ARRAY_SIZE(pl_names); i++) { + if (is_pl_valid(sd, i)) + nr_pl++; + } + + return nr_pl; +} + +static const struct powercap_zone_ops zone_ops = { + .get_energy_uj = spel_get_energy_counter, + .get_max_energy_range_uj = spel_get_max_energy_counter, + .release = spel_release_zone, +}; + +static int spel_constraint_to_pl(struct spel_domain *sd, int cid) +{ + int i, id; + + for (i = 0, id = 0; i < ARRAY_SIZE(pl_names); i++) { + if (is_pl_valid(sd, i) && id++ == cid) + return i; + } + + return -EINVAL; +} + +static int spel_set_power_limit(struct powercap_zone *power_zone, int cid, + u64 power_limit) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + int id; + + id = spel_constraint_to_pl(sd, cid); + if (id < 0) + return id; + + return spel_write_pl_data(sd, id, PL_LIMIT, power_limit); +} + +static int spel_get_power_limit(struct powercap_zone *power_zone, int cid, + u64 *data) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + u64 val; + int ret, id; + + id = spel_constraint_to_pl(sd, cid); + if (id < 0) + return id; + + ret = spel_read_pl_data(sd, id, PL_LIMIT, true, &val); + if (!ret) + *data = val; + + return ret; +} + +static int spel_set_time_window(struct powercap_zone *power_zone, int cid, + u64 window) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + int id; + + id = spel_constraint_to_pl(sd, cid); + if (id < 0) + return id; + + return spel_write_pl_data(sd, id, PL_TIME_WINDOW, window); +} + +static int spel_get_time_window(struct powercap_zone *power_zone, int cid, + u64 *data) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + u64 val; + int ret, id; + + id = spel_constraint_to_pl(sd, cid); + if (id < 0) + return id; + + ret = spel_read_pl_data(sd, id, PL_TIME_WINDOW, true, &val); + if (!ret) + *data = val; + + return ret; +} + +static const char *spel_get_constraint_name(struct powercap_zone *power_zone, + int cid) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + int id; + + id = spel_constraint_to_pl(sd, cid); + if (id >= 0 && id < ARRAY_SIZE(pl_names)) + return pl_names[id]; + + return NULL; +} + +static const struct powercap_zone_constraint_ops constraint_ops = { + .set_power_limit_uw = spel_set_power_limit, + .get_power_limit_uw = spel_get_power_limit, + .set_time_window_us = spel_set_time_window, + .get_time_window_us = spel_get_time_window, + .get_name = spel_get_constraint_name, +}; + +static void spel_init_domains(struct spel_system *sp) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(domain_info); i++) { + struct spel_domain *sd = &sp->domains[i]; + + sd->sp = sp; + snprintf(sd->name, SPEL_DOMAIN_NAME_LENGTH, "%s", + domain_info[i].name); + sd->id = i; + sd->status_reg = sp->node_base + domain_info[i].offset; + + /* PL1 is always supported (required for powercap registration) */ + sp->limits[i] = BIT(POWER_LIMIT1); + } +} + +static void spel_update_unit(struct spel_system *sp) +{ + u32 value, shift; + + /* Read power_unit and time_unit from offset 0x0 */ + value = readl(sp->config_base); + + /* + * Unit calculation: 1 / (2^shift) + * Masks limit: TIME_UNIT (4 bits, max 15), POWER_UNIT (3 bits, max 7). + */ + shift = FIELD_GET(POWER_UNIT_MASK, value); + sp->power_unit = 1000000 / (1 << shift); + + shift = FIELD_GET(TIME_UNIT_MASK, value); + /* + * Time window in register is in milliseconds. + */ + sp->time_unit = 1000 * (1 << shift); + + /* Read energy_unit from ENERGY_RPT_UNIT_OFFSET */ + value = readl(sp->config_base + ENERGY_RPT_UNIT_OFFSET); + + /* + * Unit calculation: 1 / (2^shift) + * Masks limit: ENERGY_UNIT (4 bits, max 15). + */ + shift = FIELD_GET(ENERGY_UNIT_MASK, value); + sp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << shift); + + dev_dbg(sp->dev, "Units: energy=%dnJ, time=%dus, power=%duW\n", + sp->energy_unit, sp->time_unit, sp->power_unit); +} + +static void spel_detect_powerlimit(struct spel_domain *sd) +{ + struct spel_system *sp = sd->sp; + u32 capabilities; + int i, j; + + capabilities = readl(sp->config_base + LIMITS_CAPABILITY_OFFSET); + + /* + * Detect power limits from hardware capabilities. + * Start from index 1 (POWER_LIMIT2) since PL1 is always enabled in spel_init_domains(). + */ + for (i = 1; i < ARRAY_SIZE(pl_names); i++) { + for (j = 0; j < ARRAY_SIZE(constraints); j++) { + const struct spel_constraint_info *ci = &constraints[j]; + + if (ci->domain_id == sd->id && ci->pl_id == i) { + if (capabilities & ci->supported_mask) + sp->limits[sd->id] |= BIT(i); + break; + } + } + } +} + +static int spel_init_system(struct spel_system *sp, struct device *dev) +{ + int i, ret; + + /* Read unit configuration (common for all domains) */ + spel_update_unit(sp); + + sp->domains = kcalloc(ARRAY_SIZE(domain_info), + sizeof(struct spel_domain), GFP_KERNEL); + if (!sp->domains) + return -ENOMEM; + + spel_init_domains(sp); + + for (i = 0; i < ARRAY_SIZE(domain_info); i++) { + struct spel_domain *sd = &sp->domains[i]; + + ret = devm_mutex_init(dev, &sd->lock); + if (ret) { + dev_err(dev, "Failed to initialize mutex for domain %s\n", sd->name); + kfree(sp->domains); + return ret; + } + + spel_detect_powerlimit(sd); + } + + return 0; +} + +static int spel_register_powercap(struct spel_system *sp) +{ + struct spel_domain *sd; + struct powercap_zone *power_zone; + int nr_pl, ret, i; + + /* Register SYS domain as parent zone */ + sd = &sp->domains[SPEL_DOMAIN_SYS]; + nr_pl = spel_find_nr_power_limit(sd); + + power_zone = powercap_register_zone(&sd->power_zone, + sp->control_type, sd->name, + NULL, &zone_ops, nr_pl, + &constraint_ops); + if (IS_ERR(power_zone)) { + dev_err(sp->dev, "Failed to register power zone %s\n", + sd->name); + return PTR_ERR(power_zone); + } + sp->power_zone = power_zone; + + /* Register other domains as children */ + for (i = 0; i < ARRAY_SIZE(domain_info); i++) { + struct powercap_zone *parent; + + if (i == SPEL_DOMAIN_SYS) + continue; + + sd = &sp->domains[i]; + + /* SOC is child of SYS, others are children of SOC */ + if (i == SPEL_DOMAIN_SOC) + parent = sp->power_zone; + else + parent = &sp->domains[SPEL_DOMAIN_SOC].power_zone; + + nr_pl = spel_find_nr_power_limit(sd); + power_zone = powercap_register_zone(&sd->power_zone, + sp->control_type, + sd->name, parent, + &zone_ops, nr_pl, + &constraint_ops); + + if (IS_ERR(power_zone)) { + dev_err(sp->dev, "Failed to register power_zone %s\n", + sd->name); + ret = PTR_ERR(power_zone); + goto err_cleanup; + } + } + + return 0; + +err_cleanup: + /* Unregister in reverse order: children first, then SOC, then SYS */ + for (i = i - 1; i >= 0; i--) + powercap_unregister_zone(sp->control_type, &sp->domains[i].power_zone); + + return ret; +} + +static int spel_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spel_system *sp; + int ret; + + sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); + if (!sp) + return -ENOMEM; + + sp->dev = dev; + + /* Map config registers (units, capabilities) */ + sp->config_base = devm_platform_ioremap_resource_byname(pdev, "config"); + if (IS_ERR(sp->config_base)) + return PTR_ERR(sp->config_base); + + /* Map constraint registers (power limits) */ + sp->constraint_base = devm_platform_ioremap_resource_byname(pdev, "constraints"); + if (IS_ERR(sp->constraint_base)) + return PTR_ERR(sp->constraint_base); + + /* Map spel domain registers (energy counters) */ + sp->node_base = devm_platform_ioremap_resource_byname(pdev, "nodes"); + if (IS_ERR(sp->node_base)) + return PTR_ERR(sp->node_base); + + sp->control_type = powercap_register_control_type(NULL, "qcom-spel", + NULL); + if (IS_ERR(sp->control_type)) { + dev_err(dev, "Failed to register control type\n"); + return PTR_ERR(sp->control_type); + } + + /* Initialize system and domains */ + ret = spel_init_system(sp, dev); + if (ret) { + dev_err(dev, "Failed to initialize system\n"); + goto err_unregister_control; + } + + ret = spel_register_powercap(sp); + if (ret) { + dev_err(dev, "Failed to register powercap zones\n"); + if (!sp->power_zone) + kfree(sp->domains); + goto err_unregister_control; + } + + platform_set_drvdata(pdev, sp); + + return 0; + +err_unregister_control: + powercap_unregister_control_type(sp->control_type); + return ret; +} + +static void spel_remove(struct platform_device *pdev) +{ + struct spel_system *sp = platform_get_drvdata(pdev); + int i; + + /* Unregister in reverse order: children first, then SOC, then SYS */ + for (i = ARRAY_SIZE(domain_info) - 1; i >= 0; i--) + powercap_unregister_zone(sp->control_type, &sp->domains[i].power_zone); + + powercap_unregister_control_type(sp->control_type); +} + +static const struct of_device_id spel_of_match[] = { + { .compatible = "qcom,glymur-spel" }, + { } +}; +MODULE_DEVICE_TABLE(of, spel_of_match); + +static struct platform_driver spel_driver = { + .probe = spel_probe, + .remove = spel_remove, + .driver = { + .name = "qcom_spel", + .of_match_table = spel_of_match, + }, +}; + +module_platform_driver(spel_driver); + +MODULE_DESCRIPTION("Qualcomm SPEL Powercap Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index a54a549196fe3d..64035e5e40430a 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -30,6 +30,16 @@ config REGULATOR_DEBUG help Say yes here to enable debugging support. +config REGULATOR_DUMMY_CONSUMER + tristate "Dummy regulator consumer support" + depends on REGULATOR + help + This driver provides a dummy consumer for a device behind an + USB phy (for example) that needs power supplies, but has no + own device node since it's enumerated by USB. + + If unsure, say no. + config REGULATOR_FIXED_VOLTAGE tristate "Fixed voltage regulator support" help diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 134eee274dbfb9..4d0e60dc7dea70 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_REGULATOR) += core.o dummy.o fixed-helper.o helpers.o devres.o irq_helpers.o +obj-$(CONFIG_REGULATOR_DUMMY_CONSUMER) += dummy-consumer.o obj-$(CONFIG_REGULATOR_NETLINK_EVENTS) += event.o obj-$(CONFIG_OF) += of_regulator.o obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o diff --git a/drivers/regulator/dummy-consumer.c b/drivers/regulator/dummy-consumer.c new file mode 100644 index 00000000000000..813c7abce660f0 --- /dev/null +++ b/drivers/regulator/dummy-consumer.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025, Aleksandrs Vinarskis + */ + +#include +#include +#include +#include +#include + +struct dummy_consumer_data { + struct regulator *regulator; +}; + +static int dummy_consumer_probe(struct platform_device *pdev) +{ + struct dummy_consumer_data *data; + int ret; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->regulator = devm_regulator_get(&pdev->dev, "vdd"); + if (IS_ERR(data->regulator)) { + dev_err(&pdev->dev, "Failed to get regulator\n"); + return PTR_ERR(data->regulator); + } + + ret = regulator_enable(data->regulator); + if (ret) { + dev_err(&pdev->dev, "Failed to enable regulator: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, data); + + dev_dbg(&pdev->dev, "Dummy regulator consumer initialized\n"); + return 0; +} + +static void dummy_consumer_remove(struct platform_device *pdev) +{ + struct dummy_consumer_data *data = platform_get_drvdata(pdev); + + regulator_disable(data->regulator); +} + +static int dummy_consumer_resume(struct device *dev) +{ + struct dummy_consumer_data *data = dev_get_drvdata(dev); + + return regulator_enable(data->regulator); +} + +static int dummy_consumer_suspend(struct device *dev) +{ + struct dummy_consumer_data *data = dev_get_drvdata(dev); + + return regulator_disable(data->regulator); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(dummy_consumer_pm, dummy_consumer_suspend, dummy_consumer_resume); + +static const struct of_device_id dummy_consumer_of_match[] = { + { .compatible = "regulator-dummy-consumer", }, + { } +}; +MODULE_DEVICE_TABLE(of, dummy_consumer_of_match); + +static struct platform_driver dummy_consumer_driver = { + .driver = { + .name = "regulator-dummy-consumer", + .of_match_table = dummy_consumer_of_match, + .pm = pm_sleep_ptr(&dummy_consumer_pm), + }, + .probe = dummy_consumer_probe, + .remove = dummy_consumer_remove, +}; +module_platform_driver(dummy_consumer_driver); + +MODULE_AUTHOR("Aleksandrs Vinarskis "); +MODULE_DESCRIPTION("Dummy regulator consumer driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c index 7662ebd9d2f49b..34cd03ce228e83 100644 --- a/drivers/remoteproc/imx_rproc.c +++ b/drivers/remoteproc/imx_rproc.c @@ -1344,8 +1344,12 @@ static int imx_rproc_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to enable clock\n"); } - if (rproc->state != RPROC_DETACHED) - rproc->auto_boot = of_property_read_bool(np, "fsl,auto-boot"); + if (rproc->state != RPROC_DETACHED) { + if (of_property_read_bool(np, "fsl,auto-boot")) + rproc->auto_boot = RPROC_AUTO_BOOT_ATTACH_OR_START; + else + rproc->auto_boot = RPROC_AUTO_BOOT_DISABLED; + } if (dcfg->flags & IMX_RPROC_NEED_SYSTEM_OFF) { /* diff --git a/drivers/remoteproc/ingenic_rproc.c b/drivers/remoteproc/ingenic_rproc.c index 1b78d8ddeacfd5..351b9529713790 100644 --- a/drivers/remoteproc/ingenic_rproc.c +++ b/drivers/remoteproc/ingenic_rproc.c @@ -177,7 +177,10 @@ static int ingenic_rproc_probe(struct platform_device *pdev) if (!rproc) return -ENOMEM; - rproc->auto_boot = auto_boot; + if (auto_boot) + rproc->auto_boot = RPROC_AUTO_BOOT_ATTACH_OR_START; + else + rproc->auto_boot = RPROC_AUTO_BOOT_DISABLED; vpu = rproc->priv; vpu->dev = &pdev->dev; diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index a4636c7bc6b7be..0928a75916f352 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -1029,7 +1029,7 @@ static int pru_rproc_probe(struct platform_device *pdev) * remote-processor as part of its state machine either through the * remoteproc sysfs interface or through the equivalent kernel API. */ - rproc->auto_boot = false; + rproc->auto_boot = RPROC_AUTO_BOOT_DISABLED; pru = rproc->priv; pru->dev = dev; diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c index 58d5b85e58cdad..ed1b578a831dd1 100644 --- a/drivers/remoteproc/qcom_q6v5.c +++ b/drivers/remoteproc/qcom_q6v5.c @@ -36,6 +36,25 @@ static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable) return ret; } +static int q6v5_init(struct qcom_q6v5 *q6v5, bool handover_issued) +{ + int ret; + + /* Always send correct load state in case it was not done before */ + ret = q6v5_load_state_toggle(q6v5, true); + if (ret) + return ret; + + reinit_completion(&q6v5->start_done); + reinit_completion(&q6v5->stop_done); + + q6v5->running = true; + q6v5->handover_issued = handover_issued; + + enable_irq(q6v5->handover_irq); + return 0; +} + /** * qcom_q6v5_prepare() - reinitialize the qcom_q6v5 context before start * @q6v5: reference to qcom_q6v5 context to be reinitialized @@ -52,23 +71,34 @@ int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5) return ret; } - ret = q6v5_load_state_toggle(q6v5, true); + ret = q6v5_init(q6v5, false); if (ret) { icc_set_bw(q6v5->path, 0, 0); return ret; } - reinit_completion(&q6v5->start_done); - reinit_completion(&q6v5->stop_done); + return 0; +} +EXPORT_SYMBOL_GPL(qcom_q6v5_prepare); - q6v5->running = true; - q6v5->handover_issued = false; +/** + * qcom_q6v5_attach() - attach to already running qcom_q6v5 remoteproc + * @q6v5: reference to qcom_q6v5 context to be attached + * + * Return: 0 on success, negative errno on failure + */ +int qcom_q6v5_attach(struct qcom_q6v5 *q6v5) +{ + int ret; - enable_irq(q6v5->handover_irq); + ret = q6v5_init(q6v5, true); + if (ret) + return ret; + complete(&q6v5->start_done); return 0; } -EXPORT_SYMBOL_GPL(qcom_q6v5_prepare); +EXPORT_SYMBOL_GPL(qcom_q6v5_attach); /** * qcom_q6v5_unprepare() - unprepare the qcom_q6v5 context after stop @@ -201,8 +231,8 @@ int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon) q6v5->running = false; - /* Don't perform SMP2P dance if remote isn't running */ - if (q6v5->rproc->state != RPROC_RUNNING || qcom_sysmon_shutdown_acked(sysmon)) + /* Don't perform SMP2P dance if remote crashed or already stopped */ + if (q6v5->rproc->state == RPROC_CRASHED || qcom_sysmon_shutdown_acked(sysmon)) return 0; qcom_smem_state_update_bits(q6v5->state, @@ -234,6 +264,35 @@ unsigned long qcom_q6v5_panic(struct qcom_q6v5 *q6v5) } EXPORT_SYMBOL_GPL(qcom_q6v5_panic); +/** + * qcom_q6v5_read_smp2p_state() - check the initial state during boot using SMP2P + * @q6v5: reference to qcom_q6v5 context + * + * Read the current state of the SMP2P interrupts and attempt to determine if + * the remoteproc is already running. If yes, the remoteproc state is set to + * RPROC_DETACHED. Drivers can use this to add support for attaching to + * remoteprocs during boot. + * + * There is a small chance for false-positives, so drivers should combine this + * with device-specific status information if possible. + */ +void qcom_q6v5_read_smp2p_state(struct qcom_q6v5 *q6v5) +{ + bool handover = false; + bool ready = false; + bool fatal = false; + bool stop = false; + + irq_get_irqchip_state(q6v5->handover_irq, IRQCHIP_STATE_LINE_LEVEL, &handover); + irq_get_irqchip_state(q6v5->ready_irq, IRQCHIP_STATE_LINE_LEVEL, &ready); + irq_get_irqchip_state(q6v5->fatal_irq, IRQCHIP_STATE_LINE_LEVEL, &fatal); + irq_get_irqchip_state(q6v5->stop_irq, IRQCHIP_STATE_LINE_LEVEL, &stop); + + if (ready && handover && !stop && !fatal) + q6v5->rproc->state = RPROC_DETACHED; +} +EXPORT_SYMBOL_GPL(qcom_q6v5_read_smp2p_state); + /** * qcom_q6v5_init() - initializer of the q6v5 common struct * @q6v5: handle to be initialized diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h index 5a859c41896e99..f034bb6286055a 100644 --- a/drivers/remoteproc/qcom_q6v5.h +++ b/drivers/remoteproc/qcom_q6v5.h @@ -47,7 +47,10 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev, void (*handover)(struct qcom_q6v5 *q6v5)); void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5); +void qcom_q6v5_read_smp2p_state(struct qcom_q6v5 *q6v5); + int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5); +int qcom_q6v5_attach(struct qcom_q6v5 *q6v5); int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5); int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon); int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout); diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index b5c8d6d38c9cbc..7184f73be69105 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -673,7 +673,10 @@ static int adsp_probe(struct platform_device *pdev) return -ENOMEM; } - rproc->auto_boot = desc->auto_boot; + if (desc->auto_boot) + rproc->auto_boot = RPROC_AUTO_BOOT_ATTACH_OR_START; + else + rproc->auto_boot = RPROC_AUTO_BOOT_DISABLED; rproc->has_iommu = desc->has_iommu; rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index ae78f5c7c1b69e..606896500ec310 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -2095,7 +2095,7 @@ static int q6v5_probe(struct platform_device *pdev) return -ENOMEM; } - rproc->auto_boot = false; + rproc->auto_boot = RPROC_AUTO_BOOT_DISABLED; rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); qproc = rproc->priv; diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 808e9609988d31..89b134b331fba4 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -224,10 +224,13 @@ static int qcom_pas_load(struct rproc *rproc, const struct firmware *fw) /* Store firmware handle to be used in qcom_pas_start() */ pas->firmware = fw; - if (pas->lite_pas_id) - qcom_scm_pas_shutdown(pas->lite_pas_id); - if (pas->lite_dtb_pas_id) - qcom_scm_pas_shutdown(pas->lite_dtb_pas_id); + /* + * We don't support loading the "lite" firmware, so we don't need to + * keep trying to shut it down. If it was running, it should have + * already been stopped by adsp_stop(). + */ + pas->lite_pas_id = 0; + pas->lite_dtb_pas_id = 0; if (pas->dtb_pas_id) { ret = request_firmware(&pas->dtb_firmware, pas->dtb_firmware_name, pas->dev); @@ -393,6 +396,28 @@ static void qcom_pas_handover(struct qcom_q6v5 *q6v5) qcom_pas_pds_disable(pas, pas->proxy_pds, pas->proxy_pd_count); } +static int qcom_pas_shutdown(int pas_id, int lite_pas_id) +{ + int ret, lite_ret = -ENODEV; + + /* + * We don't know if the boot firmware started the "full" or "lite" + * firmware, so we don't know if we need to shutdown the lite_pas_id or + * the normal pas_id. Unfortunately, the return codes of the SCM calls + * are also not helpful to figure that out. Since shutting down a + * stopped remoteproc is a no-op, we just shutdown both and if one of + * the calls succeeds, we assume it's okay. + */ + if (lite_pas_id) + lite_ret = qcom_scm_pas_shutdown(lite_pas_id); + + ret = qcom_scm_pas_shutdown(pas_id); + if (ret && lite_ret) + return ret; + + return 0; +} + static int qcom_pas_stop(struct rproc *rproc) { struct qcom_pas *pas = rproc->priv; @@ -403,7 +428,7 @@ static int qcom_pas_stop(struct rproc *rproc) if (ret == -ETIMEDOUT) dev_err(pas->dev, "timed out on wait\n"); - ret = qcom_scm_pas_shutdown(pas->pas_id); + ret = qcom_pas_shutdown(pas->pas_id, pas->lite_pas_id); if (ret && pas->decrypt_shutdown) ret = qcom_pas_shutdown_poll_decrypt(pas); @@ -411,7 +436,7 @@ static int qcom_pas_stop(struct rproc *rproc) dev_err(pas->dev, "failed to shutdown: %d\n", ret); if (pas->dtb_pas_id) { - ret = qcom_scm_pas_shutdown(pas->dtb_pas_id); + ret = qcom_pas_shutdown(pas->dtb_pas_id, pas->lite_dtb_pas_id); if (ret) dev_err(pas->dev, "failed to shutdown dtb: %d\n", ret); @@ -420,9 +445,11 @@ static int qcom_pas_stop(struct rproc *rproc) qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size); - handover = qcom_q6v5_unprepare(&pas->q6v5); - if (handover) - qcom_pas_handover(&pas->q6v5); + if (rproc->state != RPROC_DETACHED) { + handover = qcom_q6v5_unprepare(&pas->q6v5); + if (handover) + qcom_pas_handover(&pas->q6v5); + } if (pas->smem_host_id) ret = qcom_smem_bust_hwspin_lock_by_host(pas->smem_host_id); @@ -430,6 +457,13 @@ static int qcom_pas_stop(struct rproc *rproc) return ret; } +static int qcom_pas_attach(struct rproc *rproc) +{ + struct qcom_pas *pas = rproc->priv; + + return qcom_q6v5_attach(&pas->q6v5); +} + static void *qcom_pas_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem) { struct qcom_pas *pas = rproc->priv; @@ -511,6 +545,7 @@ static const struct rproc_ops qcom_pas_ops = { .unprepare = qcom_pas_unprepare, .start = qcom_pas_start, .stop = qcom_pas_stop, + .attach = qcom_pas_attach, .da_to_va = qcom_pas_da_to_va, .parse_fw = qcom_pas_parse_firmware, .load = qcom_pas_load, @@ -521,6 +556,7 @@ static const struct rproc_ops qcom_pas_minidump_ops = { .unprepare = qcom_pas_unprepare, .start = qcom_pas_start, .stop = qcom_pas_stop, + .attach = qcom_pas_attach, .da_to_va = qcom_pas_da_to_va, .parse_fw = qcom_pas_parse_firmware, .load = qcom_pas_load, @@ -528,6 +564,13 @@ static const struct rproc_ops qcom_pas_minidump_ops = { .coredump = qcom_pas_minidump, }; +static const struct rproc_ops qcom_pas_ops_no_reset = { + .attach = qcom_pas_attach, + .da_to_va = qcom_pas_da_to_va, + .stop = qcom_pas_stop, + .panic = qcom_pas_panic, +}; + static int qcom_pas_init_clock(struct qcom_pas *pas) { pas->xo = devm_clk_get(pas->dev, "xo"); @@ -763,6 +806,9 @@ static int qcom_pas_probe(struct platform_device *pdev) if (desc->minidump_id) ops = &qcom_pas_minidump_ops; + if (device_property_read_bool(&pdev->dev, "qcom,broken-reset")) + ops = &qcom_pas_ops_no_reset; + rproc = devm_rproc_alloc(&pdev->dev, desc->sysmon_name, ops, fw_name, sizeof(*pas)); if (!rproc) { @@ -771,7 +817,14 @@ static int qcom_pas_probe(struct platform_device *pdev) } rproc->has_iommu = of_property_present(pdev->dev.of_node, "iommus"); - rproc->auto_boot = desc->auto_boot; + if (desc->auto_boot) { + if (ops->start) + rproc->auto_boot = RPROC_AUTO_BOOT_RESTART_IF_FW_AVAILABLE; + else + rproc->auto_boot = RPROC_AUTO_BOOT_ATTACH_OR_START; + } else { + rproc->auto_boot = RPROC_AUTO_BOOT_DISABLED; + } rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); pas = rproc->priv; @@ -824,6 +877,21 @@ static int qcom_pas_probe(struct platform_device *pdev) if (ret) goto detach_proxy_pds; + /* + * Unfortunately, the PAS interface does not provide a reliable way to + * check if a certain pas_id is currently running. Reading the smp2p + * state is the best we can do to check if the remoteproc is already + * running during boot. + */ + qcom_q6v5_read_smp2p_state(&pas->q6v5); + + if (rproc->state == RPROC_OFFLINE && !ops->start) { + dev_err(&pdev->dev, "reset broken and remoteproc not running during boot, exiting\n"); + /* Release all resources, but return 0 so we don't block sync_state() */ + ret = 0; + goto deinit_q6v5; + } + qcom_add_glink_subdev(rproc, &pas->glink_subdev, desc->ssr_name); qcom_add_smd_subdev(rproc, &pas->smd_subdev); qcom_add_pdm_subdev(rproc, &pas->pdm_subdev); @@ -865,6 +933,7 @@ static int qcom_pas_probe(struct platform_device *pdev) qcom_remove_pdm_subdev(rproc, &pas->pdm_subdev); qcom_remove_smd_subdev(rproc, &pas->smd_subdev); qcom_remove_glink_subdev(rproc, &pas->glink_subdev); +deinit_q6v5: qcom_q6v5_deinit(&pas->q6v5); detach_proxy_pds: qcom_pas_pds_detach(pas, pas->proxy_pds, pas->proxy_pd_count); @@ -872,6 +941,7 @@ static int qcom_pas_probe(struct platform_device *pdev) qcom_pas_unassign_memory_region(pas); free_rproc: device_init_wakeup(pas->dev, false); + pas->rproc = NULL; return ret; } @@ -880,6 +950,9 @@ static void qcom_pas_remove(struct platform_device *pdev) { struct qcom_pas *pas = platform_get_drvdata(pdev); + if (!pas->rproc) + return; + rproc_del(pas->rproc); qcom_q6v5_deinit(&pas->q6v5); diff --git a/drivers/remoteproc/rcar_rproc.c b/drivers/remoteproc/rcar_rproc.c index 3c25625f966dcb..99a26a05165883 100644 --- a/drivers/remoteproc/rcar_rproc.c +++ b/drivers/remoteproc/rcar_rproc.c @@ -172,7 +172,7 @@ static int rcar_rproc_probe(struct platform_device *pdev) dev_set_drvdata(dev, rproc); /* Manually start the rproc */ - rproc->auto_boot = false; + rproc->auto_boot = RPROC_AUTO_BOOT_DISABLED; ret = devm_rproc_add(dev, rproc); if (ret) { diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c index f003be006b1bf8..c44985b2fba7b7 100644 --- a/drivers/remoteproc/remoteproc_core.c +++ b/drivers/remoteproc/remoteproc_core.c @@ -1678,7 +1678,8 @@ static int rproc_trigger_auto_boot(struct rproc *rproc) * for a firmware image to be loaded, we can simply initiate the process * of attaching to it immediately. */ - if (rproc->state == RPROC_DETACHED) + if (rproc->state == RPROC_DETACHED && + rproc->auto_boot != RPROC_AUTO_BOOT_RESTART_IF_FW_AVAILABLE) return rproc_boot(rproc); /* @@ -1703,8 +1704,9 @@ static int rproc_stop(struct rproc *rproc, bool crashed) if (!rproc->ops->stop) return -EINVAL; - /* Stop any subdevices for the remote processor */ - rproc_stop_subdevices(rproc, crashed); + /* Stop any subdevices for the remote processor if it was attached */ + if (rproc->state != RPROC_DETACHED) + rproc_stop_subdevices(rproc, crashed); /* the installed resource table is no longer accessible */ ret = rproc_reset_rsc_table_on_stop(rproc); @@ -1721,7 +1723,8 @@ static int rproc_stop(struct rproc *rproc, bool crashed) return ret; } - rproc_unprepare_subdevices(rproc); + if (rproc->state != RPROC_DETACHED) + rproc_unprepare_subdevices(rproc); rproc->state = RPROC_OFFLINE; @@ -1898,9 +1901,9 @@ static void rproc_crash_handler_work(struct work_struct *work) */ int rproc_boot(struct rproc *rproc) { - const struct firmware *firmware_p; + const struct firmware *firmware_p = NULL; struct device *dev; - int ret; + int ret, fw_ret = 1; if (!rproc) { pr_err("invalid rproc handle\n"); @@ -1927,6 +1930,19 @@ int rproc_boot(struct rproc *rproc) goto unlock_mutex; } + /* Check early if we have firmware avilable if needed */ + if (rproc->auto_boot == RPROC_AUTO_BOOT_RESTART_IF_FW_AVAILABLE && + rproc->state == RPROC_DETACHED) { + fw_ret = request_firmware(&firmware_p, rproc->firmware, dev); + if (fw_ret == 0) { + dev_info(dev, "restarting %s with new firmware\n", rproc->name); + + ret = rproc_stop(rproc, false); + if (ret) + goto downref_rproc; + } + } + if (rproc->state == RPROC_DETACHED) { dev_info(dev, "attaching to %s\n", rproc->name); @@ -1934,19 +1950,20 @@ int rproc_boot(struct rproc *rproc) } else { dev_info(dev, "powering up %s\n", rproc->name); - /* load firmware */ - ret = request_firmware(&firmware_p, rproc->firmware, dev); - if (ret < 0) { - dev_err(dev, "request_firmware failed: %d\n", ret); + /* load firmware (if not already happened above) */ + if (fw_ret == 1) + fw_ret = request_firmware(&firmware_p, rproc->firmware, dev); + if (fw_ret < 0) { + dev_err(dev, "request_firmware failed: %d\n", fw_ret); + ret = fw_ret; goto downref_rproc; } ret = rproc_fw_boot(rproc, firmware_p); - - release_firmware(firmware_p); } downref_rproc: + release_firmware(firmware_p); if (ret) atomic_dec(&rproc->power); unlock_mutex: @@ -2254,6 +2271,10 @@ static int rproc_validate(struct rproc *rproc) return -EINVAL; } + if (rproc->auto_boot == RPROC_AUTO_BOOT_RESTART_IF_FW_AVAILABLE && + (!rproc->ops->stop || !rproc->ops->start || !rproc->ops->attach)) + return -EINVAL; + return 0; } @@ -2465,7 +2486,7 @@ struct rproc *rproc_alloc(struct device *dev, const char *name, return NULL; rproc->priv = &rproc[1]; - rproc->auto_boot = true; + rproc->auto_boot = RPROC_AUTO_BOOT_ATTACH_OR_START; rproc->elf_class = ELFCLASSNONE; rproc->elf_machine = EM_NONE; diff --git a/drivers/remoteproc/stm32_rproc.c b/drivers/remoteproc/stm32_rproc.c index 632614013dc652..891fc17f8a63eb 100644 --- a/drivers/remoteproc/stm32_rproc.c +++ b/drivers/remoteproc/stm32_rproc.c @@ -696,7 +696,8 @@ static int stm32_rproc_get_syscon(struct device_node *np, const char *prop, } static int stm32_rproc_parse_dt(struct platform_device *pdev, - struct stm32_rproc *ddata, bool *auto_boot) + struct stm32_rproc *ddata, + enum rproc_auto_boot *auto_boot) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; @@ -777,7 +778,10 @@ static int stm32_rproc_parse_dt(struct platform_device *pdev, if (err) dev_info(dev, "failed to get pdds\n"); - *auto_boot = of_property_read_bool(np, "st,auto-boot"); + if (of_property_read_bool(np, "st,auto-boot")) + *auto_boot = RPROC_AUTO_BOOT_ATTACH_OR_START; + else + *auto_boot = RPROC_AUTO_BOOT_DISABLED; /* * See if we can check the M4 status, i.e if it was started diff --git a/drivers/remoteproc/wkup_m3_rproc.c b/drivers/remoteproc/wkup_m3_rproc.c index 2d5bfbefcacc5b..8815648295c892 100644 --- a/drivers/remoteproc/wkup_m3_rproc.c +++ b/drivers/remoteproc/wkup_m3_rproc.c @@ -170,7 +170,7 @@ static int wkup_m3_rproc_probe(struct platform_device *pdev) if (!rproc) return -ENOMEM; - rproc->auto_boot = false; + rproc->auto_boot = RPROC_AUTO_BOOT_DISABLED; rproc->sysfs_read_only = true; wkupm3 = rproc->priv; diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c index 3349d187775100..95b889a52ec6ef 100644 --- a/drivers/remoteproc/xlnx_r5_remoteproc.c +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c @@ -941,12 +941,7 @@ static struct zynqmp_r5_core *zynqmp_r5_alloc_rproc_core(struct device *cdev) r5_rproc->recovery_disabled = true; r5_rproc->has_iommu = false; - r5_rproc->auto_boot = false; - - /* attempt to boot automatically if the firmware-name is provided */ - if (fw_name) - r5_rproc->auto_boot = true; - + r5_rproc->auto_boot = RPROC_AUTO_BOOT_DISABLED; r5_core = r5_rproc->priv; r5_core->dev = cdev; r5_core->np = dev_of_node(cdev); diff --git a/drivers/rpmsg/rpmsg_core.c b/drivers/rpmsg/rpmsg_core.c index c56f69c22e420c..749f7d82de2c04 100644 --- a/drivers/rpmsg/rpmsg_core.c +++ b/drivers/rpmsg/rpmsg_core.c @@ -95,6 +95,14 @@ EXPORT_SYMBOL(rpmsg_release_channel); * equals to the src address of their rpmsg channel), the driver's handler * is invoked to process it. * + * Note that the endpoint for simple rpmsg drivers is created before calling + * probe() and closed after calling remove(), so special care must be taken + * to handle calls to the rx callback before/in parallel of probe() and + * after/in parallel of remove(). If more control over the endpoint creation + * is required to avoid race conditions, drivers can omit the callback and + * explicitly call rpmsg_dev_open_ept() in probe() and rpmsg_destroy_ept() in + * remove(), together with locks as needed. + * * That said, more complicated drivers might need to allocate * additional rpmsg addresses, and bind them to different rx callbacks. * To accomplish that, those drivers need to call this function. @@ -425,6 +433,32 @@ static int rpmsg_uevent(const struct device *dev, struct kobj_uevent_env *env) rpdev->id.name); } +struct rpmsg_endpoint *rpmsg_dev_open_ept(struct rpmsg_device *rpdev, + rpmsg_rx_cb_t cb, void *priv) +{ + struct rpmsg_driver *rpdrv = to_rpmsg_driver(rpdev->dev.driver); + struct rpmsg_channel_info chinfo = { + .src = rpdev->src, + .dst = RPMSG_ADDR_ANY, + }; + struct rpmsg_endpoint *ept; + + strscpy(chinfo.name, rpdev->id.name, sizeof(chinfo.name)); + + ept = rpmsg_create_ept(rpdev, cb, priv, chinfo); + if (!ept) { + dev_err(&rpdev->dev, "failed to create endpoint\n"); + return NULL; + } + + rpdev->ept = ept; + rpdev->src = ept->addr; + + ept->flow_cb = rpdrv->flowcontrol; + return ept; +} +EXPORT_SYMBOL(rpmsg_dev_open_ept); + /* * when an rpmsg driver is probed with a channel, we seamlessly create * it an endpoint, binding its rx callback to a unique local rpmsg @@ -437,7 +471,6 @@ static int rpmsg_dev_probe(struct device *dev) { struct rpmsg_device *rpdev = to_rpmsg_device(dev); struct rpmsg_driver *rpdrv = to_rpmsg_driver(rpdev->dev.driver); - struct rpmsg_channel_info chinfo = {}; struct rpmsg_endpoint *ept = NULL; int err; @@ -447,21 +480,11 @@ static int rpmsg_dev_probe(struct device *dev) goto out; if (rpdrv->callback) { - strscpy(chinfo.name, rpdev->id.name, sizeof(chinfo.name)); - chinfo.src = rpdev->src; - chinfo.dst = RPMSG_ADDR_ANY; - - ept = rpmsg_create_ept(rpdev, rpdrv->callback, NULL, chinfo); + ept = rpmsg_dev_open_ept(rpdev, rpdrv->callback, NULL); if (!ept) { - dev_err(dev, "failed to create endpoint\n"); err = -ENOMEM; goto out; } - - rpdev->ept = ept; - rpdev->src = ept->addr; - - ept->flow_cb = rpdrv->flowcontrol; } err = rpdrv->probe(rpdev); @@ -470,7 +493,7 @@ static int rpmsg_dev_probe(struct device *dev) goto destroy_ept; } - if (ept && rpdev->ops->announce_create) { + if (rpdev->ept && rpdev->ops->announce_create) { err = rpdev->ops->announce_create(rpdev); if (err) { dev_err(dev, "failed to announce creation\n"); @@ -495,13 +518,13 @@ static void rpmsg_dev_remove(struct device *dev) struct rpmsg_device *rpdev = to_rpmsg_device(dev); struct rpmsg_driver *rpdrv = to_rpmsg_driver(rpdev->dev.driver); - if (rpdev->ops->announce_destroy) + if (rpdev->ept && rpdev->ops->announce_destroy) rpdev->ops->announce_destroy(rpdev); if (rpdrv->remove) rpdrv->remove(rpdev); - if (rpdev->ept) + if (rpdrv->callback && rpdev->ept) rpmsg_destroy_ept(rpdev->ept); } diff --git a/drivers/scsi/libsas/sas_scsi_host.c b/drivers/scsi/libsas/sas_scsi_host.c index 97ac3db5dccb3f..f187b4fb51baa3 100644 --- a/drivers/scsi/libsas/sas_scsi_host.c +++ b/drivers/scsi/libsas/sas_scsi_host.c @@ -433,6 +433,9 @@ int sas_eh_abort_handler(struct scsi_cmnd *cmd) struct sas_internal *i = to_sas_internal(host->transportt); unsigned long flags; + if (current != host->ehandler) + return FAILED; + if (!i->dft->lldd_abort_task) return FAILED; diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index 3042261578aad8..dd31ae609f74fa 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -355,8 +355,18 @@ static int pmic_glink_probe(struct platform_device *pdev) __pmic_glink = pg; mutex_unlock(&__pmic_glink_lock); + ret = register_rpmsg_driver(&pmic_glink_rpmsg_driver); + if (ret) { + ret = dev_err_probe(&pdev->dev, ret, "failed to register rpmsg driver\n"); + goto out_release_pmic_glink; + } + return 0; +out_release_pmic_glink: + mutex_lock(&__pmic_glink_lock); + __pmic_glink = NULL; + mutex_unlock(&__pmic_glink_lock); out_release_aux_devices: if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) pmic_glink_del_aux_device(pg, &pg->ps_aux); @@ -385,6 +395,8 @@ static void pmic_glink_remove(struct platform_device *pdev) if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) pmic_glink_del_aux_device(pg, &pg->ucsi_aux); + unregister_rpmsg_driver(&pmic_glink_rpmsg_driver); + guard(mutex)(&__pmic_glink_lock); __pmic_glink = NULL; } @@ -419,31 +431,7 @@ static struct platform_driver pmic_glink_driver = { .of_match_table = pmic_glink_of_match, }, }; - -static int pmic_glink_init(void) -{ - int ret; - - ret = platform_driver_register(&pmic_glink_driver); - if (ret < 0) - return ret; - - ret = register_rpmsg_driver(&pmic_glink_rpmsg_driver); - if (ret < 0) { - platform_driver_unregister(&pmic_glink_driver); - return ret; - } - - return 0; -} -module_init(pmic_glink_init); - -static void pmic_glink_exit(void) -{ - unregister_rpmsg_driver(&pmic_glink_rpmsg_driver); - platform_driver_unregister(&pmic_glink_driver); -} -module_exit(pmic_glink_exit); +module_platform_driver(pmic_glink_driver); MODULE_DESCRIPTION("Qualcomm PMIC GLINK driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/soc/qcom/pmic_glink_altmode.c b/drivers/soc/qcom/pmic_glink_altmode.c index 619bad2c27eeb3..939a444ebe6e9e 100644 --- a/drivers/soc/qcom/pmic_glink_altmode.c +++ b/drivers/soc/qcom/pmic_glink_altmode.c @@ -450,7 +450,7 @@ static void pmic_glink_altmode_sc8180xp_notify(struct pmic_glink_altmode *altmod alt_port->mode = mode; alt_port->hpd_state = hpd_state; alt_port->hpd_irq = hpd_irq; - schedule_work(&alt_port->work); + queue_work(system_freezable_wq, &alt_port->work); } #define SC8280XP_DPAM_MASK 0x3f @@ -501,7 +501,7 @@ static void pmic_glink_altmode_sc8280xp_notify(struct pmic_glink_altmode *altmod alt_port->tbt_data = *tbt; } - schedule_work(&alt_port->work); + queue_work(system_freezable_wq, &alt_port->work); } static void pmic_glink_altmode_callback(const void *data, size_t len, void *priv) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index af0ceeaf6e0730..8645c7a69ab319 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -78,7 +78,7 @@ struct smp2p_smem_item { u32 flags; struct { - u8 name[SMP2P_MAX_ENTRY_NAME]; + char name[SMP2P_MAX_ENTRY_NAME]; u32 value; } entries[SMP2P_MAX_ENTRY]; } __packed; @@ -215,8 +215,6 @@ static void qcom_smp2p_do_ssr_ack(struct qcom_smp2p *smp2p) if (smp2p->ssr_ack) val |= BIT(SMP2P_FLAGS_RESTART_ACK_BIT); out->flags = val; - - qcom_smp2p_kick(smp2p); } static void qcom_smp2p_negotiate(struct qcom_smp2p *smp2p) @@ -227,8 +225,10 @@ static void qcom_smp2p_negotiate(struct qcom_smp2p *smp2p) if (in->version == out->version) { out->features &= in->features; - if (out->features & SMP2P_FEATURE_SSR_ACK) + if (out->features & SMP2P_FEATURE_SSR_ACK) { smp2p->ssr_ack_enabled = true; + smp2p->ssr_ack = !!(out->flags & BIT(SMP2P_FLAGS_RESTART_ACK_BIT)); + } smp2p->negotiation_done = true; trace_smp2p_negotiate(smp2p->dev, out->features); @@ -291,7 +291,6 @@ static void qcom_smp2p_notify_in(struct qcom_smp2p *smp2p) struct smp2p_entry *entry; int irq_pin; u32 status; - char buf[SMP2P_MAX_ENTRY_NAME]; u32 val; int i; @@ -300,8 +299,7 @@ static void qcom_smp2p_notify_in(struct qcom_smp2p *smp2p) /* Match newly created entries */ for (i = smp2p->valid_entries; i < in->valid_entries; i++) { list_for_each_entry(entry, &smp2p->inbound, node) { - memcpy(buf, in->entries[i].name, sizeof(buf)); - if (!strcmp(buf, entry->name)) { + if (!strncmp(in->entries[i].name, entry->name, SMP2P_MAX_ENTRY_NAME)) { entry->value = &in->entries[i].value; break; } @@ -339,6 +337,24 @@ static void qcom_smp2p_notify_in(struct qcom_smp2p *smp2p) } } +static bool qcom_smp2p_scan(struct qcom_smp2p *smp2p) +{ + bool ack_restart = false; + + if (!smp2p->negotiation_done) + qcom_smp2p_negotiate(smp2p); + + if (smp2p->negotiation_done) { + ack_restart = qcom_smp2p_check_ssr(smp2p); + qcom_smp2p_notify_in(smp2p); + + if (ack_restart) + qcom_smp2p_do_ssr_ack(smp2p); + } + + return ack_restart; +} + /** * qcom_smp2p_intr() - interrupt handler for incoming notifications * @irq: unused @@ -355,7 +371,6 @@ static irqreturn_t qcom_smp2p_intr(int irq, void *data) struct qcom_smp2p *smp2p = data; unsigned int smem_id = smp2p->smem_items[SMP2P_INBOUND]; unsigned int pid = smp2p->remote_pid; - bool ack_restart; size_t size; in = smp2p->in; @@ -372,16 +387,8 @@ static irqreturn_t qcom_smp2p_intr(int irq, void *data) smp2p->in = in; } - if (!smp2p->negotiation_done) - qcom_smp2p_negotiate(smp2p); - - if (smp2p->negotiation_done) { - ack_restart = qcom_smp2p_check_ssr(smp2p); - qcom_smp2p_notify_in(smp2p); - - if (ack_restart) - qcom_smp2p_do_ssr_ack(smp2p); - } + if (qcom_smp2p_scan(smp2p)) + qcom_smp2p_kick(smp2p); out: return IRQ_HANDLED; @@ -431,20 +438,22 @@ static void smp2p_irq_print_chip(struct irq_data *irqd, struct seq_file *p) seq_printf(p, "%8s", dev_name(entry->smp2p->dev)); } -static int smp2p_irq_get_irqchip_state(struct irq_data *irqd, enum irqchip_irq_state which, - bool *state) +static int smp2p_get_irqchip_state(struct irq_data *irqd, + enum irqchip_irq_state which, bool *state) { struct smp2p_entry *entry = irq_data_get_irq_chip_data(irqd); + irq_hw_number_t irq = irqd_to_hwirq(irqd); u32 val; if (which != IRQCHIP_STATE_LINE_LEVEL) return -EINVAL; - if (!entry->value) - return -ENODEV; - - val = readl(entry->value); - *state = !!(val & BIT(irqd_to_hwirq(irqd))); + if (entry->value) { + val = readl(entry->value); + *state = !!(val & BIT(irq)); + } else { + *state = 0; + } return 0; } @@ -455,7 +464,7 @@ static struct irq_chip smp2p_irq_chip = { .irq_unmask = smp2p_unmask_irq, .irq_set_type = smp2p_set_irq_type, .irq_print_chip = smp2p_irq_print_chip, - .irq_get_irqchip_state = smp2p_irq_get_irqchip_state, + .irq_get_irqchip_state = smp2p_get_irqchip_state, }; static int smp2p_irq_map(struct irq_domain *d, @@ -521,16 +530,24 @@ static int qcom_smp2p_outbound_entry(struct qcom_smp2p *smp2p, struct device_node *node) { struct smp2p_smem_item *out = smp2p->out; - char buf[SMP2P_MAX_ENTRY_NAME] = {}; + int i; - /* Allocate an entry from the smem item */ - strscpy(buf, entry->name, SMP2P_MAX_ENTRY_NAME); - memcpy(out->entries[out->valid_entries].name, buf, SMP2P_MAX_ENTRY_NAME); + /* Check if we have an entry already (e.g. allocated by boot firmware) */ + for (i = 0; i < out->valid_entries; i++) + if (!strncmp(out->entries[i].name, entry->name, SMP2P_MAX_ENTRY_NAME)) + break; - /* Make the logical entry reference the physical value */ - entry->value = &out->entries[out->valid_entries].value; + if (i == out->valid_entries) { + /* Allocate an entry from the smem item */ + if (i == out->total_entries) + return -ENOMEM; - out->valid_entries++; + strscpy(out->entries[i].name, entry->name, SMP2P_MAX_ENTRY_NAME); + out->valid_entries++; + } + + /* Make the logical entry reference the physical value */ + entry->value = &out->entries[i].value; entry->state = qcom_smem_state_register(node, &smp2p_state_ops, entry); if (IS_ERR(entry->state)) { @@ -560,6 +577,29 @@ static int qcom_smp2p_alloc_outbound_item(struct qcom_smp2p *smp2p) return PTR_ERR(out); } + smp2p->out = out; + + if (ret == -EEXIST && smp2p->in) { + if (out->magic == SMP2P_MAGIC && + out->version == 1 && + out->local_pid == smp2p->local_pid && + out->remote_pid == smp2p->remote_pid && + out->total_entries >= SMP2P_MAX_ENTRY && + out->valid_entries <= out->total_entries) { + /* + * Reuse existing smem item, but adjust features to + * what we support. This will be updated later when we + * negotiate with the features of the remote side. + */ + out->features = SMP2P_ALL_FEATURES; + return 0; + } else { + dev_warn(smp2p->dev, "Unexpected local smp2p item allocated by firmware, resetting. " + "(magic: %#x, version: %d, local_pid: %d, remote_pid: %d, total_entries: %d, valid_entries: %d)\n", + out->magic, out->version, out->local_pid, out->remote_pid, out->total_entries, out->valid_entries); + } + } + memset(out, 0, sizeof(*out)); out->magic = SMP2P_MAGIC; out->local_pid = smp2p->local_pid; @@ -586,8 +626,6 @@ static int qcom_smp2p_alloc_outbound_item(struct qcom_smp2p *smp2p) qcom_smp2p_kick(smp2p); - smp2p->out = out; - return 0; } @@ -627,6 +665,7 @@ static int smp2p_parse_ipc(struct qcom_smp2p *smp2p) static int qcom_smp2p_probe(struct platform_device *pdev) { + struct smp2p_smem_item *in; struct smp2p_entry *entry; struct qcom_smp2p *smp2p; const char *key; @@ -677,6 +716,10 @@ static int qcom_smp2p_probe(struct platform_device *pdev) return ret; } + in = qcom_smem_get(smp2p->remote_pid, smp2p->smem_items[SMP2P_INBOUND], NULL); + if (!IS_ERR(in)) + smp2p->in = in; + ret = qcom_smp2p_alloc_outbound_item(smp2p); if (ret < 0) goto release_mbox; @@ -713,8 +756,9 @@ static int qcom_smp2p_probe(struct platform_device *pdev) /* Check inbound entries in the case of early boot processor */ qcom_smp2p_start_in(smp2p); - /* Kick the outgoing edge after allocating entries */ - qcom_smp2p_kick(smp2p); + if (smp2p->in) + /* Ignore return status since we kick unconditionally below */ + qcom_smp2p_scan(smp2p); ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qcom_smp2p_intr, @@ -725,6 +769,9 @@ static int qcom_smp2p_probe(struct platform_device *pdev) goto unwind_interfaces; } + /* Kick the outgoing edge after allocating entries */ + qcom_smp2p_kick(smp2p); + /* * Treat smp2p interrupt as wakeup source, but keep it disabled * by default. User space can decide enabling it depending on its diff --git a/drivers/soundwire/bus.h b/drivers/soundwire/bus.h index 8115c64dd48e2f..bc3f862878a4b2 100644 --- a/drivers/soundwire/bus.h +++ b/drivers/soundwire/bus.h @@ -117,6 +117,8 @@ int sdw_find_col_index(int col); * @ch_mask: Channel mask * @transport_params: Transport parameters * @port_params: Port parameters + * @transport_params_override_mask: Bitmask of per-slave transport overrides + * @transport_params_override: Per-slave transport override values * @port_node: List node for Master or Slave port_list * @lane: Which lane is used * @@ -128,6 +130,8 @@ struct sdw_port_runtime { int ch_mask; struct sdw_transport_params transport_params; struct sdw_port_params port_params; + unsigned int transport_params_override_mask; + struct sdw_transport_params transport_params_override; struct list_head port_node; unsigned int lane; }; diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 3d8f5a81eff195..a777c134ff8f8e 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -122,6 +122,29 @@ #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08 + +/* + * SP11/Denali diagnostic parity gate. Native Windows programs active WSA + * feedback master ports 10/11/13 with Offset2 == 0 immediately before graph + * start. Golden Linux preserves the inactive 0xff Offset2 when enabling the + * channel mask. Keep this opt-in and touch only those three ports. + */ +static bool sp11_feedback_active_offset2_zero; +module_param_named(sp11_feedback_active_offset2_zero, + sp11_feedback_active_offset2_zero, bool, 0644); +MODULE_PARM_DESC(sp11_feedback_active_offset2_zero, + "Clear WSA feedback ports 10/11/13 Offset2 only while enabling channels"); + +/* SP11 diagnostic: Windows WSA controller/CPS packetization state. */ +static bool sp11_cps_pcm_route_105c; +module_param_named(sp11_cps_pcm_route_105c, sp11_cps_pcm_route_105c, bool, 0644); +MODULE_PARM_DESC(sp11_cps_pcm_route_105c, + "Program Windows WSA route 0x105c and CPS DP13 PCM control 0x1d54"); + +static bool qcom_swrm_is_sp11_feedback_port(unsigned int port_num) +{ + return port_num == 10 || port_num == 11 || port_num == 13; +} #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d @@ -1040,6 +1063,37 @@ static int qcom_swrm_transport_params(struct sdw_bus *bus, pcfg = &ctrl->pconfig[params->port_num]; + /* + * Native Windows speaker start also programs controller route 0x105c + * and CPS DIN DP13 PCM control 0x1d54. This was insufficient by + * itself, but is re-tested here only after PROTCLK + Offset2 parity. + */ + if (sp11_cps_pcm_route_105c && + of_machine_is_compatible("microsoft,denali") && + bus->controller_id == MASTER_ID_WSA && params->port_num == 13) { + u32 route_old = 0; + u32 pcm_old = 0; + u32 pcm_reg = 0x1054 + params->port_num * 0x100; + + ret = ctrl->reg_read(ctrl, 0x105c, &route_old); + if (ret) + goto err; + if (route_old != 0x0005000f) { + ret = ctrl->reg_write(ctrl, 0x105c, 0x0005000f); + if (ret) + goto err; + } + ret = ctrl->reg_read(ctrl, pcm_reg, &pcm_old); + if (ret) + goto err; + ret = ctrl->reg_write(ctrl, pcm_reg, 0x3); + dev_info(ctrl->dev, + "SP11 CPS wake parity: bank=%u route_old=%#x route_new=0x5000f pcm_reg=%#x pcm_old=%#x pcm_new=0x3 ret=%d\n", + bank, route_old, pcm_reg, pcm_old, ret); + if (ret) + goto err; + } + value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; value |= pcfg->si & 0xff; @@ -1116,10 +1170,23 @@ static int qcom_swrm_port_enable(struct sdw_bus *bus, ctrl->reg_read(ctrl, reg, &val); - if (enable_ch->enable) + if (enable_ch->enable) { + u32 old = val; + + if (sp11_feedback_active_offset2_zero && + qcom_swrm_is_sp11_feedback_port(enable_ch->port_num)) + val &= ~(0xff << SWRM_DP_PORT_CTRL_OFFSET2_SHFT); + val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); - else + + if (sp11_feedback_active_offset2_zero && + qcom_swrm_is_sp11_feedback_port(enable_ch->port_num)) + dev_info(ctrl->dev, + "SP11 feedback active Offset2 parity: port=%u bank=%u old=%#010x new=%#010x ch=%#x\n", + enable_ch->port_num, bank, old, val, enable_ch->ch_mask); + } else { val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); + } return ctrl->reg_write(ctrl, reg, val); } @@ -1220,7 +1287,7 @@ static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, struct sdw_stream_runtime *stream, struct snd_pcm_hw_params *params, - int direction) + int dai_id) { struct sdw_stream_config sconfig; struct sdw_master_runtime *m_rt; @@ -1228,14 +1295,20 @@ static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, struct sdw_port_runtime *p_rt; struct sdw_slave *slave; unsigned long *port_mask; - int maxport, pn, nports = 0; + int maxport, pn, nports = 0, i; unsigned int m_port; struct sdw_port_config *pconfig __free(kfree) = kzalloc_objs(*pconfig, ctrl->nports); if (!pconfig) return -ENOMEM; - if (direction == SNDRV_PCM_STREAM_CAPTURE) + /* + * Direction is a property of the controller data port. A speaker VI + * sidechain is intentionally exposed as a companion playback BE so + * DPCM starts it with render, while the physical DIN port still carries + * data from the SoundWire slaves into the master. + */ + if (dai_id >= ctrl->num_dout_ports) sconfig.direction = SDW_DATA_DIR_TX; else sconfig.direction = SDW_DATA_DIR_RX; @@ -1275,6 +1348,21 @@ static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, dev_err(ctrl->dev, "All ports busy\n"); return -EBUSY; } + + /* Multiple slaves may intentionally share one physical + * master port. Keep one master runtime and merge the + * channels instead of programming the same port twice. + */ + for (i = 0; i < nports; i++) { + if (pconfig[i].num != pn) + continue; + + pconfig[i].ch_mask |= p_rt->ch_mask; + break; + } + if (i < nports) + continue; + set_bit(pn, port_mask); pconfig[nports].num = pn; pconfig[nports].ch_mask = p_rt->ch_mask; @@ -1298,7 +1386,7 @@ static int qcom_swrm_hw_params(struct snd_pcm_substream *substream, int ret; ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, - substream->stream); + dai->id); if (ret) qcom_swrm_stream_free_ports(ctrl, sruntime); @@ -1394,15 +1482,36 @@ static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) if (!dais[i].name) return -ENOMEM; - if (i < ctrl->num_dout_ports) + if (i < ctrl->num_dout_ports) { stream = &dais[i].playback; - else + } else { stream = &dais[i].capture; + dais[i].playback = (struct snd_soc_pcm_stream) { + .channels_min = 1, + .channels_max = 1, + .rates = SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_24000 | + SNDRV_PCM_RATE_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }; + dais[i].playback.stream_name = devm_kasprintf( + dev, GFP_KERNEL, "SoundWire VI Protection%d", + i - ctrl->num_dout_ports); + if (!dais[i].playback.stream_name) + return -ENOMEM; + } stream->channels_min = 1; stream->channels_max = 1; - stream->rates = SNDRV_PCM_RATE_48000; - stream->formats = SNDRV_PCM_FMTBIT_S16_LE; + stream->rates = i < ctrl->num_dout_ports ? + SNDRV_PCM_RATE_48000 : + SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_24000 | + SNDRV_PCM_RATE_48000; + stream->formats = i < ctrl->num_dout_ports ? + SNDRV_PCM_FMTBIT_S16_LE : + SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE; dais[i].ops = &qcom_swrm_pdm_dai_ops; dais[i].id = i; diff --git a/drivers/soundwire/stream.c b/drivers/soundwire/stream.c index 5d20e95a1e23eb..b00d3354f40c40 100644 --- a/drivers/soundwire/stream.c +++ b/drivers/soundwire/stream.c @@ -62,6 +62,65 @@ int sdw_find_row_index(int row) } EXPORT_SYMBOL(sdw_find_row_index); +static int sdw_program_simple_ext(struct sdw_bus *bus, struct sdw_slave *slave, + struct sdw_transport_params *t_params, + u32 registers) +{ + u32 blockctrl3, samplectrl2, hctrl, offsetctrl2; + u16 wbuf; + int ret; + + if (bus->params.next_bank) { + blockctrl3 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num); + samplectrl2 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num); + hctrl = SDW_DPN_HCTRL_B1(t_params->port_num); + offsetctrl2 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num); + } else { + blockctrl3 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num); + samplectrl2 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num); + hctrl = SDW_DPN_HCTRL_B0(t_params->port_num); + offsetctrl2 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num); + } + + if (registers & SDW_DPN_SIMPLE_TRANSPORT_BLOCKCTRL3) { + ret = sdw_write_no_pm(slave, blockctrl3, t_params->blk_pkg_mode); + if (ret < 0) + return ret; + } + + if (registers & SDW_DPN_SIMPLE_TRANSPORT_SAMPLECTRL2) { + wbuf = FIELD_GET(SDW_DPN_SAMPLECTRL_HIGH, + t_params->sample_interval - 1); + ret = sdw_write_no_pm(slave, samplectrl2, wbuf); + if (ret < 0) + return ret; + } + + if (registers & SDW_DPN_SIMPLE_TRANSPORT_HCTRL) { + wbuf = FIELD_PREP(SDW_DPN_HCTRL_HSTART, t_params->hstart); + wbuf |= FIELD_PREP(SDW_DPN_HCTRL_HSTOP, t_params->hstop); + ret = sdw_write_no_pm(slave, hctrl, wbuf); + if (ret < 0) + return ret; + } + + if (registers & SDW_DPN_SIMPLE_TRANSPORT_OFFSETCTRL2) { + ret = sdw_write_no_pm(slave, offsetctrl2, t_params->offset2); + if (ret < 0) + return ret; + } + + return 0; +} + +static void sdw_apply_slave_transport_overrides(struct sdw_port_runtime *p_rt) +{ + if (p_rt->transport_params_override_mask & + SDW_PORT_CONFIG_OVERRIDE_OFFSET1) + p_rt->transport_params.offset1 = + p_rt->transport_params_override.offset1; +} + static int _sdw_program_slave_port_params(struct sdw_bus *bus, struct sdw_slave *slave, struct sdw_transport_params *t_params, @@ -137,6 +196,7 @@ static int sdw_program_slave_port_params(struct sdw_bus *bus, struct sdw_slave_prop *slave_prop = &s_rt->slave->prop; u32 addr1, addr2, addr3, addr4, addr5, addr6; enum sdw_dpn_type port_type; + u32 simple_transport_registers = 0; bool read_only_wordlength; int ret; u8 wbuf; @@ -144,6 +204,12 @@ static int sdw_program_slave_port_params(struct sdw_bus *bus, if (s_rt->slave->is_mockup_device) return 0; + /* Bus compute_params() establishes the common master schedule. Apply + * explicitly requested slave-only deltas immediately before the slave is + * programmed so master transport state remains shared. + */ + sdw_apply_slave_transport_overrides(p_rt); + if (t_params->port_num) { struct sdw_dpn_prop *dpn_prop; @@ -154,6 +220,7 @@ static int sdw_program_slave_port_params(struct sdw_bus *bus, read_only_wordlength = dpn_prop->read_only_wordlength; port_type = dpn_prop->type; + simple_transport_registers = dpn_prop->simple_transport_registers; } else { read_only_wordlength = false; port_type = SDW_DPN_FULL; @@ -239,7 +306,14 @@ static int sdw_program_slave_port_params(struct sdw_bus *bus, } } - if (port_type != SDW_DPN_SIMPLE) { + if (port_type == SDW_DPN_SIMPLE && simple_transport_registers) { + ret = sdw_program_simple_ext(bus, s_rt->slave, t_params, + simple_transport_registers); + if (ret < 0) + dev_err(&s_rt->slave->dev, + "Extended SIMPLE transport reg write failed for port: %d\n", + t_params->port_num); + } else if (port_type != SDW_DPN_SIMPLE) { ret = _sdw_program_slave_port_params(bus, s_rt->slave, t_params, port_type); if (ret < 0) @@ -983,6 +1057,10 @@ static int sdw_port_config(struct sdw_port_runtime *p_rt, { p_rt->ch_mask = port_config[port_index].ch_mask; p_rt->num = port_config[port_index].num; + p_rt->transport_params_override_mask = + port_config[port_index].transport_params_override_mask; + p_rt->transport_params_override = + port_config[port_index].transport_params_override; /* * TODO: Check port capabilities for requested configuration diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index 26e723cfea61ef..2db9cc547e1ee8 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -1,10 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. -#define CREATE_TRACE_POINTS -#include - #include +#include #include #include #include @@ -18,6 +16,7 @@ #include #include #include +#include #include /* SPI SE specific registers and respective register fields */ @@ -51,6 +50,29 @@ #define SE_SPI_PRE_POST_CMD_DLY 0x274 +#define SE_GSI_EVENT_EN 0xe18 +#define SE_GSI_IRQ_EN 0xe1c +#define SE_DMA_TX_IRQ_EN 0xc4c +#define SE_DMA_TX_IRQ_MSK 0xc50 +#define SE_DMA_RX_IRQ_EN 0xd4c +#define SE_DMA_RX_IRQ_MSK 0xd50 + +#define SP11_QSPI_M_IRQ_INIT 0x33c00046 +#define SP11_QSPI_M_IRQ_LIVE 0xffc0007f +#define SP11_QSPI_S_IRQ_INIT 0x03001e06 +#define SP11_QSPI_S_IRQ_LIVE 0x03001e36 +#define SP11_QSPI_M_IRQ_CLEAR 0xffc07fff +#define SP11_QSPI_S_IRQ_CLEAR 0x0fc07f3f + +/* + * Laboratory-only controller checkpoint. The default path remains unchanged; + * Phase 84/85 opt in to the exact qcspi8380 cold PrepareHardware sequence. + */ +static bool sp11_windows_se_init; +module_param(sp11_windows_se_init, bool, 0444); +MODULE_PARM_DESC(sp11_windows_se_init, + "Use the captured Windows SP11 QSPI cold SE initialization"); + #define SE_SPI_DELAY_COUNTERS 0x278 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) @@ -59,6 +81,12 @@ #define SE_SPI_SLAVE_EN (0x2BC) #define SPI_SLAVE_EN BIT(0) +/* QSPI proto 9 host mode - Surface Pro 11 touch */ +#define GENI_SE_QSPI 9 +#define M_CMD_LANE_QUAD 2 +#define M_CMD_TX_LANES_SHFT 11 +#define M_CMD_RX_LANES_SHFT 13 + /* M_CMD OP codes for SPI */ #define SPI_TX_ONLY 1 #define SPI_RX_ONLY 2 @@ -102,11 +130,110 @@ struct spi_geni_master { int irq; bool cs_flag; bool abort_failed; + bool is_qspi; struct dma_chan *tx; struct dma_chan *rx; int cur_xfer_mode; }; +static bool spi_geni_is_sp11_qspi(struct spi_geni_master *mas) +{ + return mas->is_qspi && !strcmp(dev_name(mas->dev), "a88000.spi"); +} + +static int spi_geni_transfer_one(struct spi_controller *spi, + struct spi_device *slv, + struct spi_transfer *xfer); + +static void spi_geni_sp11_qspi_prepare_hw(struct spi_geni_master *mas) +{ + struct geni_se *se = &mas->se; + + if (!spi_geni_is_sp11_qspi(mas)) + return; + + writel(readl(se->base + SE_GENI_DMA_MODE_EN) | GENI_DMA_MODE_EN, + se->base + SE_GENI_DMA_MODE_EN); + writel(0, se->base + SE_GSI_IRQ_EN); + writel(0xf, se->base + SE_GSI_EVENT_EN); + writel(SP11_QSPI_M_IRQ_INIT, se->base + SE_GENI_M_IRQ_EN); + writel(SP11_QSPI_S_IRQ_INIT, se->base + SE_GENI_S_IRQ_EN); + writel(0xf, se->base + SE_DMA_TX_IRQ_MSK); + writel(0xd, se->base + SE_DMA_TX_IRQ_EN); + writel(0xfff, se->base + SE_DMA_RX_IRQ_MSK); + writel(0x1d, se->base + SE_DMA_RX_IRQ_EN); + writel(SP11_QSPI_M_IRQ_CLEAR, se->base + SE_GENI_M_IRQ_CLEAR); + writel(SP11_QSPI_S_IRQ_CLEAR, se->base + SE_GENI_S_IRQ_CLEAR); + writel(0xf, se->base + SE_DMA_TX_IRQ_CLR); + writel(0xfff, se->base + SE_DMA_RX_IRQ_CLR); + /* Complete the SE register sequence before starting GPI channels. */ + wmb(); + + dev_info_once(mas->dev, + "SP11: applied Linux-integrated QSPI SE preparation before GPI channel start\n"); +} + +static void spi_geni_sp11_qspi_prepare_windows_hw(struct spi_geni_master *mas) +{ + struct geni_se *se = &mas->se; + + if (!spi_geni_is_sp11_qspi(mas)) + return; + + /* qcspi8380 skips this block when the FIFO interface is disabled. */ + if (readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE) { + dev_info_once(mas->dev, + "SP11: Windows SE init guard skipped 13-write block\n"); + return; + } + + /* Exact FUN_14001b3c8 write order, confirmed by cold KDNET capture. */ + writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN); + writel(0, se->base + SE_GSI_IRQ_EN); + writel(0xf, se->base + SE_GSI_EVENT_EN); + writel(SP11_QSPI_M_IRQ_INIT, se->base + SE_GENI_M_IRQ_EN); + writel(SP11_QSPI_S_IRQ_INIT, se->base + SE_GENI_S_IRQ_EN); + writel(0xf, se->base + SE_DMA_TX_IRQ_MSK); + writel(0xd, se->base + SE_DMA_TX_IRQ_EN); + writel(0xfff, se->base + SE_DMA_RX_IRQ_MSK); + writel(0x1d, se->base + SE_DMA_RX_IRQ_EN); + writel(SP11_QSPI_M_IRQ_CLEAR, se->base + SE_GENI_M_IRQ_CLEAR); + writel(SP11_QSPI_S_IRQ_CLEAR, se->base + SE_GENI_S_IRQ_CLEAR); + writel(0xf, se->base + SE_DMA_TX_IRQ_CLR); + writel(0xfff, se->base + SE_DMA_RX_IRQ_CLR); + /* Publish the complete Windows SE sequence before channel allocation. */ + wmb(); + + dev_info_once(mas->dev, + "SP11: applied exact Windows QSPI cold SE init sequence\n"); +} + +static void spi_geni_sp11_qspi_arm_live(struct spi_geni_master *mas) +{ + struct geni_se *se = &mas->se; + + if (!spi_geni_is_sp11_qspi(mas)) + return; + + writel(SP11_QSPI_M_IRQ_LIVE, se->base + SE_GENI_M_IRQ_EN); + writel(SP11_QSPI_S_IRQ_LIVE, se->base + SE_GENI_S_IRQ_EN); + /* Make the live completion masks visible before submitting descriptors. */ + wmb(); +} + +static void spi_geni_sp11_qspi_restore_rest(struct spi_geni_master *mas) +{ + struct geni_se *se = &mas->se; + + if (!spi_geni_is_sp11_qspi(mas)) + return; + + writel(SP11_QSPI_M_IRQ_INIT, se->base + SE_GENI_M_IRQ_EN); + writel(SP11_QSPI_S_IRQ_INIT, se->base + SE_GENI_S_IRQ_EN); + /* Restore the resting masks before another transfer can be prepared. */ + wmb(); +} + static void spi_slv_setup(struct spi_geni_master *mas) { struct geni_se *se = &mas->se; @@ -228,6 +355,7 @@ static void handle_gpi_timeout(struct spi_controller *spi) { struct spi_geni_master *mas = spi_controller_get_devdata(spi); + spi_geni_sp11_qspi_restore_rest(mas); dmaengine_terminate_sync(mas->tx); dmaengine_terminate_sync(mas->rx); } @@ -335,9 +463,6 @@ static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, writel(clk_sel, se->base + SE_GENI_CLK_SEL); writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); - trace_geni_spi_clk_cfg(mas->dev, clk_hz, mas->cur_sclk_hz, idx, div, - mas->cur_bits_per_word); - /* Set BW quota for CPU as driver supports FIFO mode only. */ se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); ret = geni_icc_set_bw(se); @@ -372,9 +497,6 @@ static int setup_fifo_params(struct spi_device *spi_slv, if ((mode_changed & SPI_CS_HIGH) || (cs_changed && (spi_slv->mode & SPI_CS_HIGH))) writel((spi_slv->mode & SPI_CS_HIGH) ? BIT(chipselect) : 0, se->base + SE_SPI_DEMUX_OUTPUT_INV); - trace_geni_spi_setup_params(mas->dev, chipselect, spi_slv->mode, - mode_changed, cs_changed); - return 0; } @@ -382,6 +504,9 @@ static void spi_gsi_callback_result(void *cb, const struct dmaengine_result *result) { struct spi_controller *spi = cb; + struct spi_geni_master *mas = spi_controller_get_devdata(spi); + + spi_geni_sp11_qspi_restore_rest(mas); spi->cur_msg->status = -EIO; if (result->result != DMA_TRANS_NOERROR) { @@ -400,6 +525,343 @@ spi_gsi_callback_result(void *cb, const struct dmaengine_result *result) spi_finalize_current_transfer(spi); } +static void spi_gsi_fill_config(struct spi_geni_master *mas, + struct spi_device *spi_slv, + struct gpi_spi_config *peripheral, + u32 rx_len, u32 cmd) +{ + peripheral->cmd = cmd; + peripheral->rx_len = rx_len; + peripheral->loopback_en = !!(spi_slv->mode & SPI_LOOP); + peripheral->clock_pol_high = !!(spi_slv->mode & SPI_CPOL); + peripheral->data_pol_high = !!(spi_slv->mode & SPI_CPHA); + peripheral->cs = spi_get_chipselect(spi_slv, 0); + peripheral->pack_en = true; + peripheral->word_len = mas->cur_bits_per_word - MIN_WORD_LEN; + peripheral->qspi = mas->is_qspi; +} + +struct spi_geni_sp11_qspi_pair { + struct completion tx_done; + struct completion rx_done; + struct dmaengine_result tx_result; + struct dmaengine_result rx_result; +}; + +static void spi_geni_sp11_qspi_tx_done(void *data, + const struct dmaengine_result *result) +{ + struct spi_geni_sp11_qspi_pair *pair = data; + + pair->tx_result = *result; + complete(&pair->tx_done); +} + +static void spi_geni_sp11_qspi_rx_done(void *data, + const struct dmaengine_result *result) +{ + struct spi_geni_sp11_qspi_pair *pair = data; + + pair->rx_result = *result; + complete(&pair->rx_done); +} + +/* + * The SPI core maps messages with DMA_ATTR_SKIP_CPU_SYNC and its normal + * transfer_one_message() implementation performs these two synchronizations + * around transfer_one(). The SP11 paired-QSPI path replaces that whole + * implementation, so it must preserve the same DMA API contract itself. + * Use the core-recorded mapping devices rather than the GENI child or GPI + * control device; on SP11 the QUP wrapper is the payload DMA master. + */ +static void spi_geni_sp11_qspi_sync_pair_for_device(struct spi_controller *spi, + struct spi_transfer *tx_xfer, + struct spi_transfer *rx_xfer) +{ + if (tx_xfer->tx_sg_mapped) + dma_sync_sgtable_for_device(spi->cur_tx_dma_dev, &tx_xfer->tx_sg, + DMA_TO_DEVICE); + if (rx_xfer->rx_sg_mapped) + dma_sync_sgtable_for_device(spi->cur_rx_dma_dev, &rx_xfer->rx_sg, + DMA_FROM_DEVICE); +} + +static void spi_geni_sp11_qspi_sync_pair_for_cpu(struct spi_controller *spi, + struct spi_transfer *tx_xfer, + struct spi_transfer *rx_xfer) +{ + if (rx_xfer->rx_sg_mapped) + dma_sync_sgtable_for_cpu(spi->cur_rx_dma_dev, &rx_xfer->rx_sg, + DMA_FROM_DEVICE); + if (tx_xfer->tx_sg_mapped) + dma_sync_sgtable_for_cpu(spi->cur_tx_dma_dev, &tx_xfer->tx_sg, + DMA_TO_DEVICE); +} + +static int spi_geni_sp11_qspi_submit_read_pair(struct spi_controller *spi, + struct spi_message *msg, + struct spi_transfer *tx_xfer, + struct spi_transfer *rx_xfer) +{ + struct spi_geni_master *mas = spi_controller_get_devdata(spi); + unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; + struct dma_slave_config config = {}; + struct gpi_spi_config peripheral = {}; + struct spi_geni_sp11_qspi_pair pair = {}; + struct dma_async_tx_descriptor *tx_desc, *rx_desc; + dma_cookie_t tx_cookie, rx_cookie; + unsigned long deadline, timeout; + int ret; + + if (tx_xfer->bits_per_word != mas->cur_bits_per_word || + tx_xfer->speed_hz != mas->cur_speed_hz) { + mas->cur_bits_per_word = tx_xfer->bits_per_word; + mas->cur_speed_hz = tx_xfer->speed_hz; + } + + ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, + &peripheral.clk_src, &peripheral.clk_div); + if (ret) { + msg->status = ret; + return ret; + } + + config.peripheral_config = &peripheral; + config.peripheral_size = sizeof(peripheral); + peripheral.set_config = true; + spi_gsi_fill_config(mas, msg->spi, &peripheral, rx_xfer->len, + SPI_DUPLEX); + /* Windows arms the broader completion masks for every live transfer. */ + spi_geni_sp11_qspi_arm_live(mas); + if (spi_geni_is_sp11_qspi(mas)) { + struct geni_se *dse = &mas->se; + + dev_dbg(mas->dev, + "SP11 framing r7c:%08x txpack:%08x/%08x rxpack:%08x/%08x\n", + readl(dse->base + 0x7c), + readl(dse->base + 0x260), readl(dse->base + 0x264), + readl(dse->base + 0x284), readl(dse->base + 0x288)); + dev_dbg(mas->dev, + "SP11 framing cpha:%08x cpol:%08x trans:%08x word:%08x demux:%08x\n", + readl(dse->base + 0x224), readl(dse->base + 0x230), + readl(dse->base + 0x25c), readl(dse->base + 0x268), + readl(dse->base + 0x250)); + dev_dbg(mas->dev, + "SP11 framing mirq:%08x sirq:%08x qspi:%d wl:%u\n", + readl(dse->base + 0x614), readl(dse->base + 0x644), + peripheral.qspi, peripheral.word_len); + } + dev_info_once(mas->dev, + "SP11: paired DMA sync map tx:%s/%u rx:%s/%u\n", + dev_name(spi->cur_tx_dma_dev), tx_xfer->tx_sg_mapped, + dev_name(spi->cur_rx_dma_dev), rx_xfer->rx_sg_mapped); + spi_geni_sp11_qspi_sync_pair_for_device(spi, tx_xfer, rx_xfer); + + ret = dmaengine_slave_config(mas->rx, &config); + if (ret) { + dev_err(mas->dev, + "SP11 QSPI RX configuration failed: %d\n", ret); + goto terminate; + } + rx_desc = dmaengine_prep_slave_sg(mas->rx, rx_xfer->rx_sg.sgl, + rx_xfer->rx_sg.nents, + DMA_DEV_TO_MEM, flags); + if (!rx_desc) { + ret = -EIO; + dev_err(mas->dev, "SP11 QSPI RX descriptor preparation failed\n"); + goto terminate; + } + + ret = dmaengine_slave_config(mas->tx, &config); + if (ret) { + dev_err(mas->dev, + "SP11 QSPI TX configuration failed: %d\n", ret); + goto terminate; + } + tx_desc = dmaengine_prep_slave_sg(mas->tx, tx_xfer->tx_sg.sgl, + tx_xfer->tx_sg.nents, + DMA_MEM_TO_DEV, flags); + if (!tx_desc) { + ret = -EIO; + dev_err(mas->dev, "SP11 QSPI TX descriptor preparation failed\n"); + goto terminate; + } + + init_completion(&pair.tx_done); + init_completion(&pair.rx_done); + tx_desc->callback_result = spi_geni_sp11_qspi_tx_done; + tx_desc->callback_param = &pair; + rx_desc->callback_result = spi_geni_sp11_qspi_rx_done; + rx_desc->callback_param = &pair; + + rx_cookie = dmaengine_submit(rx_desc); + ret = dma_submit_error(rx_cookie); + if (ret) { + dev_err(mas->dev, + "SP11 QSPI RX submission failed: %d\n", ret); + goto terminate; + } + tx_cookie = dmaengine_submit(tx_desc); + ret = dma_submit_error(tx_cookie); + if (ret) { + dev_err(mas->dev, + "SP11 QSPI TX submission failed: %d\n", ret); + goto terminate; + } + dma_async_issue_pending(mas->rx); + dma_async_issue_pending(mas->tx); + + deadline = jiffies + msecs_to_jiffies(500); + timeout = wait_for_completion_timeout(&pair.rx_done, + msecs_to_jiffies(500)); + if (!timeout) { + dev_err(&msg->spi->dev, "SPI RX transfer timed out\n"); + goto timeout; + } + + timeout = time_before(jiffies, deadline) ? deadline - jiffies : 1; + if (!wait_for_completion_timeout(&pair.tx_done, timeout)) { + dev_err(&msg->spi->dev, + "SPI TX transfer timed out after RX completion\n"); + goto timeout; + } + + if (pair.tx_result.result != DMA_TRANS_NOERROR || + pair.rx_result.result != DMA_TRANS_NOERROR || + pair.tx_result.residue || pair.rx_result.residue) { + spi_geni_sp11_qspi_sync_pair_for_cpu(spi, tx_xfer, rx_xfer); + dev_err(&msg->spi->dev, + "SP11 QSPI pair failed tx(result:%d residue:%u) rx(result:%d residue:%u)\n", + pair.tx_result.result, pair.tx_result.residue, + pair.rx_result.result, pair.rx_result.residue); + msg->status = -EIO; + spi_geni_sp11_qspi_restore_rest(mas); + spi_geni_handle_err(spi, msg); + return -EIO; + } + spi_geni_sp11_qspi_sync_pair_for_cpu(spi, tx_xfer, rx_xfer); + + dev_dbg(mas->dev, "SP11 QSPI pair complete tx:%u rx:%u data:%*ph\n", + tx_xfer->len, rx_xfer->len, + min_t(unsigned int, rx_xfer->len, 16), rx_xfer->rx_buf); + + spi_geni_sp11_qspi_restore_rest(mas); + if (msg->status == -EINPROGRESS) + msg->status = 0; + if (!msg->status) + msg->actual_length += tx_xfer->len + rx_xfer->len; + + return msg->status; + +timeout: + msg->status = -ETIMEDOUT; + spi_geni_sp11_qspi_restore_rest(mas); + spi_geni_handle_err(spi, msg); + spi_geni_sp11_qspi_sync_pair_for_cpu(spi, tx_xfer, rx_xfer); + return -ETIMEDOUT; + +terminate: + msg->status = ret; + dmaengine_terminate_sync(mas->tx); + dmaengine_terminate_sync(mas->rx); + spi_geni_sp11_qspi_sync_pair_for_cpu(spi, tx_xfer, rx_xfer); + spi_geni_sp11_qspi_restore_rest(mas); + return ret; +} + +static bool spi_geni_sp11_qspi_is_read_pair(struct spi_geni_master *mas, + struct spi_message *msg, + struct spi_transfer **tx_xfer, + struct spi_transfer **rx_xfer) +{ + struct spi_transfer *first, *second; + + if (!spi_geni_is_sp11_qspi(mas) || mas->cur_xfer_mode != GENI_GPI_DMA) + return false; + if (list_count_nodes(&msg->transfers) != 2) + return false; + + first = list_first_entry(&msg->transfers, struct spi_transfer, transfer_list); + second = list_next_entry(first, transfer_list); + if (!first->tx_buf || first->rx_buf || !second->rx_buf) + return false; + if (!first->len || !second->len) + return false; + + *tx_xfer = first; + *rx_xfer = second; + return true; +} + +static int spi_geni_sp11_qspi_transfer_one_message(struct spi_controller *spi, + struct spi_message *msg) +{ + struct spi_geni_master *mas = spi_controller_get_devdata(spi); + struct spi_transfer *tx_xfer, *rx_xfer, *xfer; + int ret = 0; + + if (spi_geni_sp11_qspi_is_read_pair(mas, msg, &tx_xfer, &rx_xfer)) { + dev_info_once(mas->dev, + "SP11: QSPI combining HID read tx_len=%u rx_len=%u\n", + tx_xfer->len, rx_xfer->len); + ret = spi_geni_sp11_qspi_submit_read_pair(spi, msg, tx_xfer, rx_xfer); + spi_finalize_current_message(spi); + return ret; + } + + list_for_each_entry(xfer, &msg->transfers, transfer_list) { + if ((xfer->tx_buf || xfer->rx_buf) && xfer->len) { + reinit_completion(&spi->xfer_completion); + if (xfer->tx_sg_mapped) + dma_sync_sgtable_for_device(spi->cur_tx_dma_dev, + &xfer->tx_sg, + DMA_TO_DEVICE); + if (xfer->rx_sg_mapped) + dma_sync_sgtable_for_device(spi->cur_rx_dma_dev, + &xfer->rx_sg, + DMA_FROM_DEVICE); + ret = spi_geni_transfer_one(spi, msg->spi, xfer); + if (ret < 0) { + if (xfer->rx_sg_mapped) + dma_sync_sgtable_for_cpu(spi->cur_rx_dma_dev, + &xfer->rx_sg, + DMA_FROM_DEVICE); + if (xfer->tx_sg_mapped) + dma_sync_sgtable_for_cpu(spi->cur_tx_dma_dev, + &xfer->tx_sg, + DMA_TO_DEVICE); + break; + } + if (ret > 0) { + ret = wait_for_completion_timeout(&spi->xfer_completion, + msecs_to_jiffies(500)) ? + 0 : -ETIMEDOUT; + } + if (xfer->rx_sg_mapped) + dma_sync_sgtable_for_cpu(spi->cur_rx_dma_dev, + &xfer->rx_sg, + DMA_FROM_DEVICE); + if (xfer->tx_sg_mapped) + dma_sync_sgtable_for_cpu(spi->cur_tx_dma_dev, + &xfer->tx_sg, + DMA_TO_DEVICE); + if (ret) + break; + } + + if (msg->status != -EINPROGRESS) + break; + msg->actual_length += xfer->len; + } + + if (msg->status == -EINPROGRESS) + msg->status = ret; + if (msg->status) + spi_geni_handle_err(spi, msg); + spi_finalize_current_message(spi); + return ret; +} + static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas, struct spi_device *spi_slv, struct spi_controller *spi) { @@ -412,6 +874,7 @@ static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas config.peripheral_config = &peripheral; config.peripheral_size = sizeof(peripheral); peripheral.set_config = true; + peripheral.qspi = mas->is_qspi; if (xfer->bits_per_word != mas->cur_bits_per_word || xfer->speed_hz != mas->cur_speed_hz) { @@ -421,6 +884,13 @@ static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas if (xfer->tx_buf && xfer->rx_buf) { peripheral.cmd = SPI_DUPLEX; + if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { + peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); + } else { + int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; + + peripheral.rx_len = (xfer->len / bytes_per_word); + } } else if (xfer->tx_buf) { peripheral.cmd = SPI_TX; peripheral.rx_len = 0; @@ -435,12 +905,10 @@ static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas } } - peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); - peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); - peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); - peripheral.cs = spi_get_chipselect(spi_slv, 0); - peripheral.pack_en = true; - peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN; + spi_gsi_fill_config(mas, spi_slv, &peripheral, peripheral.rx_len, + peripheral.cmd); + if (sp11_windows_se_init) + spi_geni_sp11_qspi_arm_live(mas); ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, &peripheral.clk_src, &peripheral.clk_div); @@ -629,10 +1097,17 @@ static int spi_geni_init(struct spi_geni_master *mas) dev_err(mas->dev, "spi master firmware load failed ret: %d\n", ret); goto out_pm; } + } else if (proto == GENI_SE_QSPI && !strcmp(dev_name(mas->dev), "a88000.spi")) { + dev_info(mas->dev, "SP11: accepting protocol 9 as QSPI controller\n"); + mas->is_qspi = true; } else if (proto != GENI_SE_SPI) { dev_err(mas->dev, "Invalid proto %d\n", proto); goto out_pm; } + + if (mas->is_qspi) + spi->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD; + mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); /* Width of Tx and Rx FIFO is same */ @@ -642,7 +1117,9 @@ static int spi_geni_init(struct spi_geni_master *mas) * Hardware programming guide suggests to configure * RX FIFO RFR level to fifo_depth-2. */ - geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); + if (!sp11_windows_se_init || !spi_geni_is_sp11_qspi(mas)) + geni_se_init(se, mas->tx_fifo_depth - 3, + mas->tx_fifo_depth - 2); /* Transmit an entire FIFO worth of data per IRQ */ mas->tx_wm = 1; ver = geni_se_get_qup_hw_version(se); @@ -654,6 +1131,42 @@ static int spi_geni_init(struct spi_geni_master *mas) else mas->oversampling = 1; + if (mas->is_qspi && + device_property_read_bool(mas->dev, "qcom,enable-gsi-dma")) { + /* + * SP11: do NOT call geni_load_se_firmware() here. KDNET + * ground truth confirms the SE already reads proto=9 + * (QSPI) at this point, meaning TrustZone has already + * loaded the QSPI protocol firmware at boot. A prior + * attempt to force an explicit kernel-side firmware + * reload here regressed GPI channel allocation itself + * (EV ALLOCATE / DE ALLOC / CH START all began failing + * with -5 immediately after the "successful" reload, + * vs. previously reaching real TRE/event processing). + * Rely on the TZ-provided firmware as before. + */ + if (sp11_windows_se_init) + spi_geni_sp11_qspi_prepare_windows_hw(mas); + else + spi_geni_sp11_qspi_prepare_hw(mas); + ret = spi_geni_grab_gpi_chan(mas); + if (!ret) { + mas->cur_xfer_mode = GENI_GPI_DMA; + if (!sp11_windows_se_init) { + geni_se_select_mode(se, GENI_GPI_DMA); + spi_geni_sp11_qspi_arm_live(mas); + } + dev_info(mas->dev, "SP11: QSPI using GPI DMA descriptor mode\n"); + goto setup_cs; + } else if (ret == -EPROBE_DEFER) { + goto out_pm; + } + + dev_warn(mas->dev, + "SP11: QSPI GPI probe failed (%d); falling back to FIFO\n", + ret); + } + fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; switch (fifo_disable) { case 1: @@ -686,6 +1199,7 @@ static int spi_geni_init(struct spi_geni_master *mas) break; } +setup_cs: /* We never control CS manually */ if (!spi->target) { spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); @@ -839,12 +1353,16 @@ static int setup_se_xfer(struct spi_transfer *xfer, m_cmd |= SPI_TX_ONLY; mas->tx_rem_bytes = xfer->len; writel(len, se->base + SE_SPI_TX_TRANS_LEN); + } else if (mas->is_qspi) { + writel(0, se->base + SE_SPI_TX_TRANS_LEN); } if (xfer->rx_buf) { m_cmd |= SPI_RX_ONLY; writel(len, se->base + SE_SPI_RX_TRANS_LEN); mas->rx_rem_bytes = xfer->len; + } else if (mas->is_qspi) { + writel(0, se->base + SE_SPI_RX_TRANS_LEN); } /* @@ -874,6 +1392,19 @@ static int setup_se_xfer(struct spi_transfer *xfer, xfer->cs_change : !xfer->cs_change) m_params = FRAGMENTATION; + if (mas->is_qspi) { + if (xfer->tx_nbits == SPI_NBITS_QUAD) + m_params |= M_CMD_LANE_QUAD << M_CMD_TX_LANES_SHFT; + if (xfer->rx_nbits == SPI_NBITS_QUAD) + m_params |= M_CMD_LANE_QUAD << M_CMD_RX_LANES_SHFT; + dev_dbg(mas->dev, + "SP11 QSPI xfer mode=%d cmd=%#x params=%#x len=%u tx=%u rx=%u tx_len=%#x rx_len=%#x\n", + mas->cur_xfer_mode, m_cmd, m_params, xfer->len, + !!xfer->tx_buf, !!xfer->rx_buf, + readl(se->base + SE_SPI_TX_TRANS_LEN), + readl(se->base + SE_SPI_RX_TRANS_LEN)); + } + /* * Lock around right before we start the transfer since our * interrupt could come in at any time now. @@ -881,8 +1412,6 @@ static int setup_se_xfer(struct spi_transfer *xfer, spin_lock_irq(&mas->lock); geni_se_setup_m_cmd(se, m_cmd, m_params); - trace_geni_spi_transfer(mas->dev, len, m_cmd); - if (mas->cur_xfer_mode == GENI_SE_DMA) { if (m_cmd & SPI_RX_ONLY) geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl), @@ -937,8 +1466,6 @@ static irqreturn_t geni_spi_isr(int irq, void *data) if (!m_irq && !dma_tx_status && !dma_rx_status) return IRQ_NONE; - trace_geni_spi_irq(mas->dev, m_irq, dma_tx_status, dma_rx_status); - if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) @@ -1142,6 +1669,8 @@ static int spi_geni_probe(struct platform_device *pdev) */ if (mas->cur_xfer_mode == GENI_GPI_DMA) spi->flags = SPI_CONTROLLER_MUST_TX; + if (spi_geni_is_sp11_qspi(mas) && mas->cur_xfer_mode == GENI_GPI_DMA) + spi->transfer_one_message = spi_geni_sp11_qspi_transfer_one_message; ret = devm_request_irq(dev, mas->irq, geni_spi_isr, 0, dev_name(dev), spi); if (ret) @@ -1150,6 +1679,244 @@ static int spi_geni_probe(struct platform_device *pdev) return devm_spi_register_controller(dev, spi); } +/* + * Surface SP11 BIOS-reference asymmetric protocol-9 transaction. + * + * UEFI programs independent TX/RX lengths and starts SPI_TX_RX with command + * parameter bit 9. The normal SPI transfer API cannot represent that + * transaction, so the touchscreen client calls this controller-owned helper. + */ +#define BIOSREF_QSPI_FAST_PARAM BIT(9) +#define BIOSREF_MAX_TRANS_LEN GENMASK(23, 0) +#define BIOSREF_ERR_IRQS (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | \ + M_CMD_FAILURE_EN | M_RX_FIFO_RD_ERR_EN | \ + M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ + M_TX_FIFO_WR_ERR_EN) + +static void biosref_write_tx_fifo(struct spi_geni_master *mas, + const u8 *buf, size_t len, size_t *done) +{ + struct geni_se *se = &mas->se; + unsigned int bytes_per_word = geni_byte_per_fifo_word(mas); + unsigned int max_bytes; + + max_bytes = (mas->tx_fifo_depth - 1) * bytes_per_word; + max_bytes = min_t(size_t, max_bytes, len - *done); + + while (max_bytes) { + u32 word = 0; + unsigned int n = min_t(unsigned int, bytes_per_word, max_bytes); + + memcpy(&word, buf + *done, n); + iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &word, 1); + *done += n; + max_bytes -= n; + } + + if (*done == len) + writel(0, se->base + SE_GENI_TX_WATERMARK_REG); +} + +static void biosref_read_rx_fifo(struct spi_geni_master *mas, + u8 *buf, size_t len, size_t *done) +{ + struct geni_se *se = &mas->se; + unsigned int bytes_per_word = geni_byte_per_fifo_word(mas); + u32 status = readl(se->base + SE_GENI_RX_FIFO_STATUS); + size_t available = (status & RX_FIFO_WC_MSK) * bytes_per_word; + + if (status & RX_LAST) { + unsigned int valid; + + valid = (status & RX_LAST_BYTE_VALID_MSK) >> + RX_LAST_BYTE_VALID_SHFT; + if (valid && valid < bytes_per_word) + available -= bytes_per_word - valid; + } + + available = min_t(size_t, available, len - *done); + while (available) { + u32 word = 0; + unsigned int n = min_t(unsigned int, bytes_per_word, available); + + ioread32_rep(se->base + SE_GENI_RX_FIFOn, &word, 1); + memcpy(buf + *done, &word, n); + *done += n; + available -= n; + } +} + +static int biosref_prepare_engine(struct spi_geni_master *mas) +{ + struct geni_se *se = &mas->se; + unsigned int i; + + if (!mas->is_qspi || geni_se_read_proto(se) != GENI_SE_QSPI) + return -EOPNOTSUPP; + + for (i = 0; i < 10000; i++) { + if (!(readl(se->base + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE)) + break; + udelay(1); + } + if (i == 10000) + return -EBUSY; + + /* Discard words left by firmware or an interrupted transaction. */ + for (i = 0; i < 256; i++) { + u32 status = readl(se->base + SE_GENI_RX_FIFO_STATUS); + + if (!(status & RX_FIFO_WC_MSK)) + return 0; + readl(se->base + SE_GENI_RX_FIFOn); + } + + return -EIO; +} + +int qcom_geni_spi_biosref_xfer(struct spi_device *spi_slv, + const void *tx_buf, size_t tx_len, + void *rx_buf, size_t rx_len, + u32 speed_hz, unsigned int timeout_ms) +{ + struct spi_controller *ctlr; + struct spi_geni_master *mas; + struct geni_se *se; + enum geni_se_xfer_mode old_mode; + ktime_t deadline; + size_t tx_done = 0, rx_done = 0; + u32 irq_status; + int ret; + + if (!spi_slv || !tx_buf || !tx_len || !rx_buf || !rx_len) + return -EINVAL; + if (tx_len > BIOSREF_MAX_TRANS_LEN || rx_len > BIOSREF_MAX_TRANS_LEN) + return -EMSGSIZE; + + ctlr = spi_slv->controller; + if (!ctlr || !ctlr->dev.parent || !ctlr->dev.parent->driver || + strcmp(ctlr->dev.parent->driver->name, "geni_spi")) + return -EOPNOTSUPP; + + ret = spi_bus_lock(ctlr); + if (ret) + return ret; + + mas = spi_controller_get_devdata(ctlr); + se = &mas->se; + + ret = pm_runtime_resume_and_get(mas->dev); + if (ret < 0) + goto out_unlock; + + if (readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE) { + ret = -EOPNOTSUPP; + goto out_pm; + } + + /* Keep the normal ISR from consuming this command's FIFO/status. */ + disable_irq(mas->irq); + synchronize_irq(mas->irq); + + old_mode = mas->cur_xfer_mode; + mas->cur_xfer_mode = GENI_SE_FIFO; + geni_se_select_mode(se, GENI_SE_FIFO); + + ret = biosref_prepare_engine(mas); + if (ret) + goto out_restore_irq; + + ret = setup_fifo_params(spi_slv, ctlr); + if (ret) + goto out_restore_irq; + + spi_setup_word_len(mas, spi_slv->mode, 8); + mas->cur_bits_per_word = 8; + + ret = geni_spi_set_clock_and_bw(mas, speed_hz); + if (ret) + goto out_restore_irq; + + writel(0, se->base + SE_SPI_TRANS_CFG); + writel(0, se->base + SE_SPI_DELAY_COUNTERS); + writel(tx_len, se->base + SE_SPI_TX_TRANS_LEN); + writel(rx_len, se->base + SE_SPI_RX_TRANS_LEN); + writel(1, se->base + SE_GENI_TX_WATERMARK_REG); + writel(0, se->base + SE_GENI_RX_WATERMARK_REG); + + irq_status = readl(se->base + SE_GENI_M_IRQ_STATUS); + if (irq_status) + writel(irq_status, se->base + SE_GENI_M_IRQ_CLEAR); + + geni_se_setup_m_cmd(se, SPI_TX_RX, BIOSREF_QSPI_FAST_PARAM); + writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START); + + deadline = ktime_add_ms(ktime_get(), timeout_ms ?: 1000); + ret = -ETIMEDOUT; + + while (ktime_before(ktime_get(), deadline)) { + irq_status = readl(se->base + SE_GENI_M_IRQ_STATUS); + if (!irq_status) { + cpu_relax(); + udelay(2); + continue; + } + + if (irq_status & BIOSREF_ERR_IRQS) { + dev_err(mas->dev, "biosref transfer GENI error %#010x\n", + (u32)(irq_status & BIOSREF_ERR_IRQS)); + writel(irq_status, se->base + SE_GENI_M_IRQ_CLEAR); + ret = -EIO; + break; + } + + if ((irq_status & M_TX_FIFO_WATERMARK_EN) && tx_done < tx_len) + biosref_write_tx_fifo(mas, tx_buf, tx_len, &tx_done); + + if (irq_status & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) + biosref_read_rx_fifo(mas, rx_buf, rx_len, &rx_done); + + writel(irq_status, se->base + SE_GENI_M_IRQ_CLEAR); + + if (irq_status & M_CMD_DONE_EN) { + if (rx_done < rx_len) + biosref_read_rx_fifo(mas, rx_buf, rx_len, &rx_done); + ret = (tx_done == tx_len && rx_done == rx_len) ? 0 : -EPROTO; + break; + } + } + + writel(0, se->base + SE_GENI_TX_WATERMARK_REG); + writel(0, se->base + SE_GENI_RX_WATERMARK_REG); + + if (ret == -ETIMEDOUT) { + unsigned int i; + + geni_se_abort_m_cmd(se); + for (i = 0; i < 10000; i++) { + irq_status = readl(se->base + SE_GENI_M_IRQ_STATUS); + if (irq_status & M_CMD_ABORT_EN) { + writel(irq_status, se->base + SE_GENI_M_IRQ_CLEAR); + break; + } + udelay(1); + } + } + +out_restore_irq: + mas->cur_bits_per_word = 0; + mas->cur_xfer_mode = old_mode; + geni_se_select_mode(se, old_mode); + enable_irq(mas->irq); +out_pm: + pm_runtime_mark_last_busy(mas->dev); + pm_runtime_put_autosuspend(mas->dev); +out_unlock: + spi_bus_unlock(ctlr); + return ret; +} +EXPORT_SYMBOL_GPL(qcom_geni_spi_biosref_xfer); + static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) { struct spi_controller *spi = dev_get_drvdata(dev); diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig index a6bb01082ec697..1acb11e4ac8007 100644 --- a/drivers/thermal/qcom/Kconfig +++ b/drivers/thermal/qcom/Kconfig @@ -21,6 +21,15 @@ config QCOM_SPMI_ADC_TM5 Thermal client sets threshold temperature for both warm and cool and gets updated when a threshold is reached. +config QCOM_SPMI_ADC_TM5_GEN3 + tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5 Gen3" + depends on QCOM_SPMI_ADC5_GEN3 + help + This enables the auxiliary thermal driver for the ADC5 Gen3 thermal + monitoring device. It shows up as a thermal zone with multiple trip points. + Thermal client sets threshold temperature for both warm and cool and + gets updated when a threshold is reached. + config QCOM_SPMI_TEMP_ALARM tristate "Qualcomm SPMI PMIC Temperature Alarm" depends on OF && SPMI && IIO diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 0fa2512042e782..828d9e7bc79709 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -4,5 +4,6 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \ tsens-8960.o obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o +obj-$(CONFIG_QCOM_SPMI_ADC_TM5_GEN3) += qcom-spmi-adc-tm5-gen3.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o obj-$(CONFIG_QCOM_LMH) += lmh.o diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c new file mode 100644 index 00000000000000..fde9b073f48265 --- /dev/null +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +struct device; +struct adc_tm5_gen3_chip; + +/** + * struct adc_tm5_gen3_channel_props - ADC_TM channel structure + * @timer: time period of recurring TM measurement. + * @tm_chan_index: TM channel number used (ranging from 1-7). + * @sdam_index: SDAM on which this TM channel lies. + * @common_props: structure with common ADC channel properties. + * @high_thr_en: TM high threshold crossing detection enabled. + * @low_thr_en: TM low threshold crossing detection enabled. + * @chip: ADC TM device. + * @tzd: pointer to thermal device corresponding to TM channel. + * @last_temp: last temperature that caused threshold violation, + * or a thermal TM channel. + * @last_temp_set: indicates if last_temp is stored. + */ +struct adc_tm5_gen3_channel_props { + unsigned int timer; + unsigned int tm_chan_index; + unsigned int sdam_index; + struct adc5_channel_common_prop common_props; + bool high_thr_en; + bool low_thr_en; + struct adc_tm5_gen3_chip *chip; + struct thermal_zone_device *tzd; + int last_temp; + bool last_temp_set; +}; + +/** + * struct adc_tm5_gen3_chip - ADC Thermal Monitoring device structure + * @dev_data: Top-level ADC device data. + * @chan_props: Array of ADC_TM channel structures. + * @nchannels: number of TM channels allocated + * @dev: SPMI ADC5 Gen3 device. + * @tm_handler_work: handler for TM interrupt for threshold violation. + */ +struct adc_tm5_gen3_chip { + struct adc5_device_data *dev_data; + struct adc_tm5_gen3_channel_props *chan_props; + unsigned int nchannels; + struct device *dev; + struct work_struct tm_handler_work; +}; + +DEFINE_GUARD(adc5_gen3, struct adc_tm5_gen3_chip *, adc5_gen3_mutex_lock(_T->dev), + adc5_gen3_mutex_unlock(_T->dev)) + +static int get_sdam_from_irq(struct adc_tm5_gen3_chip *adc_tm5, int irq) +{ + for (int i = 0; i < adc_tm5->dev_data->num_sdams; i++) { + if (adc_tm5->dev_data->base[i].irq == irq) + return i; + } + return -ENOENT; +} + +static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id) +{ + struct adc_tm5_gen3_chip *adc_tm5 = dev_id; + int ret, sdam_num; + u8 tm_status[2]; + u8 status, val; + + sdam_num = get_sdam_from_irq(adc_tm5, irq); + if (sdam_num < 0) { + dev_err(adc_tm5->dev, "adc irq %d not associated with an sdam\n", + irq); + return IRQ_HANDLED; + } + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_STATUS1, + &status, sizeof(status)); + if (ret) { + dev_err(adc_tm5->dev, "adc read status1 failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (status & ADC5_GEN3_STATUS1_CONV_FAULT) { + dev_err_ratelimited(adc_tm5->dev, + "Unexpected conversion fault, status:%#x\n", + status); + val = ADC5_GEN3_CONV_ERR_CLR_REQ; + adc5_gen3_status_clear(adc_tm5->dev_data, sdam_num, + ADC5_GEN3_CONV_ERR_CLR, &val, 1); + return IRQ_HANDLED; + } + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_TM_HIGH_STS, + tm_status, sizeof(tm_status)); + if (ret) { + dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (tm_status[0] || tm_status[1]) + schedule_work(&adc_tm5->tm_handler_work); + + dev_dbg(adc_tm5->dev, "Interrupt status:%#x, high:%#x, low:%#x\n", + status, tm_status[0], tm_status[1]); + + return IRQ_HANDLED; +} + +static int adc5_gen3_tm_status_check(struct adc_tm5_gen3_chip *adc_tm5, + int sdam_index, u8 *tm_status, u8 *buf) +{ + int ret; + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_TM_HIGH_STS, + tm_status, 2); + if (ret) { + dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret); + return ret; + } + + ret = adc5_gen3_status_clear(adc_tm5->dev_data, sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR, + tm_status, 2); + if (ret) { + dev_err(adc_tm5->dev, "adc status clear conv_req failed with %d\n", + ret); + return ret; + } + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_CH_DATA0(0), + buf, 16); + if (ret) + dev_err(adc_tm5->dev, "adc read data failed with %d\n", ret); + + return ret; +} + +static void tm_handler_work(struct work_struct *work) +{ + struct adc_tm5_gen3_chip *adc_tm5 = container_of(work, struct adc_tm5_gen3_chip, + tm_handler_work); + int sdam_index = -1; + u8 tm_status[2] = { }; + u8 buf[16] = { }; + + for (int i = 0; i < adc_tm5->nchannels; i++) { + struct adc_tm5_gen3_channel_props *chan_prop = &adc_tm5->chan_props[i]; + int offset = chan_prop->tm_chan_index; + bool upper_set, lower_set; + int ret, temp; + u16 code; + + scoped_guard(adc5_gen3, adc_tm5) { + if (chan_prop->sdam_index != sdam_index) { + sdam_index = chan_prop->sdam_index; + ret = adc5_gen3_tm_status_check(adc_tm5, sdam_index, + tm_status, buf); + if (ret) + return; + } + + upper_set = ((tm_status[0] & BIT(offset)) && chan_prop->high_thr_en); + lower_set = ((tm_status[1] & BIT(offset)) && chan_prop->low_thr_en); + } + + if (!(upper_set || lower_set)) + continue; + + code = get_unaligned_le16(&buf[2 * offset]); + dev_dbg(adc_tm5->dev, "ADC_TM threshold code:%#x\n", code); + + ret = adc5_gen3_therm_code_to_temp(adc_tm5->dev, + &chan_prop->common_props, + code, &temp); + if (ret) { + dev_err(adc_tm5->dev, + "Invalid temperature reading, ret = %d, code=%#x\n", + ret, code); + continue; + } + + chan_prop->last_temp = temp; + chan_prop->last_temp_set = true; + thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED); + } +} + +static int adc_tm5_gen3_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct adc_tm5_gen3_channel_props *prop = thermal_zone_device_priv(tz); + struct adc_tm5_gen3_chip *adc_tm5; + + if (!prop || !prop->chip) + return -EINVAL; + + adc_tm5 = prop->chip; + + if (prop->last_temp_set) { + pr_debug("last_temp: %d\n", prop->last_temp); + prop->last_temp_set = false; + *temp = prop->last_temp; + return 0; + } + + return adc5_gen3_get_scaled_reading(adc_tm5->dev, &prop->common_props, + temp); +} + +static int adc_tm5_gen3_disable_channel(struct adc_tm5_gen3_channel_props *prop) +{ + struct adc_tm5_gen3_chip *adc_tm5 = prop->chip; + int ret; + u8 val; + + prop->high_thr_en = false; + prop->low_thr_en = false; + + ret = adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index); + if (ret) + return ret; + + val = BIT(prop->tm_chan_index); + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_TM_HIGH_STS_CLR, &val, sizeof(val)); + if (ret) + return ret; + + val = MEAS_INT_DISABLE; + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_TIMER_SEL, &val, sizeof(val)); + if (ret) + return ret; + + /* To indicate there is an actual conversion request */ + val = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_PERPH_CH, &val, sizeof(val)); + if (ret) + return ret; + + val = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_CONV_REQ, &val, sizeof(val)); +} + +#define ADC_TM5_GEN3_CONFIG_REGS 12 + +static int adc_tm5_gen3_configure(struct adc_tm5_gen3_channel_props *prop, + int low_temp, int high_temp) +{ + struct adc_tm5_gen3_chip *adc_tm5 = prop->chip; + u8 buf[ADC_TM5_GEN3_CONFIG_REGS]; + u8 conv_req; + u16 adc_code; + int ret; + + ret = adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index); + if (ret < 0) + return ret; + + ret = adc5_gen3_read(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret < 0) + return ret; + + /* Write SID */ + buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->common_props.sid); + + /* Select TM channel and indicate there is an actual conversion request */ + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + + buf[2] = prop->timer; + + /* Digital param selection */ + adc5_gen3_update_dig_param(&prop->common_props, &buf[3]); + + /* Update fast average sample value */ + buf[4] &= ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK; + buf[4] |= prop->common_props.avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN; + + /* Select ADC channel */ + buf[5] = prop->common_props.channel; + + /* Select HW settle delay for channel */ + buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, + prop->common_props.hw_settle_time_us); + + /* High temperature corresponds to low voltage threshold */ + prop->low_thr_en = (high_temp != INT_MAX); + if (prop->low_thr_en) { + adc_code = qcom_adc_tm5_gen2_temp_res_scale(high_temp); + put_unaligned_le16(adc_code, &buf[8]); + } + + /* Low temperature corresponds to high voltage threshold */ + prop->high_thr_en = (low_temp != -INT_MAX); + if (prop->high_thr_en) { + adc_code = qcom_adc_tm5_gen2_temp_res_scale(low_temp); + put_unaligned_le16(adc_code, &buf[10]); + } + + buf[7] = 0; + if (prop->high_thr_en) + buf[7] |= ADC5_GEN3_HIGH_THR_INT_EN; + if (prop->low_thr_en) + buf[7] |= ADC5_GEN3_LOW_THR_INT_EN; + + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_SID, + buf, sizeof(buf)); + if (ret < 0) + return ret; + + conv_req = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_CONV_REQ, &conv_req, sizeof(conv_req)); +} + +static int adc_tm5_gen3_set_trip_temp(struct thermal_zone_device *tz, + int low_temp, int high_temp) +{ + struct adc_tm5_gen3_channel_props *prop = thermal_zone_device_priv(tz); + struct adc_tm5_gen3_chip *adc_tm5; + + if (!prop || !prop->chip) + return -EINVAL; + + adc_tm5 = prop->chip; + + dev_dbg(adc_tm5->dev, "channel:%s, low_temp(mdegC):%d, high_temp(mdegC):%d\n", + prop->common_props.label, low_temp, high_temp); + + guard(adc5_gen3)(adc_tm5); + if (high_temp == INT_MAX && low_temp == -INT_MAX) + return adc_tm5_gen3_disable_channel(prop); + + return adc_tm5_gen3_configure(prop, low_temp, high_temp); +} + +static const struct thermal_zone_device_ops adc_tm_ops = { + .get_temp = adc_tm5_gen3_get_temp, + .set_trips = adc_tm5_gen3_set_trip_temp, +}; + +static int adc_tm5_register_tzd(struct adc_tm5_gen3_chip *adc_tm5) +{ + struct thermal_zone_device *tzd; + unsigned int channel; + int ret; + + for (int i = 0; i < adc_tm5->nchannels; i++) { + channel = ADC5_GEN3_V_CHAN(adc_tm5->chan_props[i].common_props); + tzd = devm_thermal_of_zone_register(adc_tm5->dev, channel, + &adc_tm5->chan_props[i], + &adc_tm_ops); + if (IS_ERR(tzd)) { + if (PTR_ERR(tzd) == -ENODEV) { + dev_info(adc_tm5->dev, + "thermal sensor on channel %d is not used\n", + channel); + continue; + } + return dev_err_probe(adc_tm5->dev, PTR_ERR(tzd), + "Error registering TZ zone:%ld for channel:%d\n", + PTR_ERR(tzd), channel); + } + adc_tm5->chan_props[i].tzd = tzd; + ret = devm_thermal_add_hwmon_sysfs(adc_tm5->dev, tzd); + if (ret) + return ret; + } + return 0; +} + +static void adc5_gen3_clear_work(void *data) +{ + struct adc_tm5_gen3_chip *adc_tm5 = data; + + cancel_work_sync(&adc_tm5->tm_handler_work); +} + +static void adc5_gen3_disable(void *data) +{ + struct adc_tm5_gen3_chip *adc_tm5 = data; + + guard(adc5_gen3)(adc_tm5); + /* Disable all available TM channels */ + for (int i = 0; i < adc_tm5->nchannels; i++) + adc_tm5_gen3_disable_channel(&adc_tm5->chan_props[i]); +} + +static void adctm_event_handler(struct auxiliary_device *adev) +{ + struct adc_tm5_gen3_chip *adc_tm5 = auxiliary_get_drvdata(adev); + + schedule_work(&adc_tm5->tm_handler_work); +} + +static int adc_tm5_probe(struct auxiliary_device *aux_dev, + const struct auxiliary_device_id *id) +{ + struct adc_tm5_gen3_chip *adc_tm5; + struct tm5_aux_dev_wrapper *aux_dev_wrapper; + struct device *dev = &aux_dev->dev; + int ret; + + adc_tm5 = devm_kzalloc(dev, sizeof(*adc_tm5), GFP_KERNEL); + if (!adc_tm5) + return -ENOMEM; + + aux_dev_wrapper = container_of(aux_dev, struct tm5_aux_dev_wrapper, + aux_dev); + + adc_tm5->dev = dev; + adc_tm5->dev_data = aux_dev_wrapper->dev_data; + adc_tm5->nchannels = aux_dev_wrapper->n_tm_channels; + adc_tm5->chan_props = devm_kcalloc(dev, aux_dev_wrapper->n_tm_channels, + sizeof(*adc_tm5->chan_props), GFP_KERNEL); + if (!adc_tm5->chan_props) + return -ENOMEM; + + for (int i = 0; i < adc_tm5->nchannels; i++) { + adc_tm5->chan_props[i].common_props = aux_dev_wrapper->tm_props[i]; + adc_tm5->chan_props[i].timer = MEAS_INT_1S; + adc_tm5->chan_props[i].sdam_index = (i + 1) / 8; + adc_tm5->chan_props[i].tm_chan_index = (i + 1) % 8; + adc_tm5->chan_props[i].chip = adc_tm5; + } + + INIT_WORK(&adc_tm5->tm_handler_work, tm_handler_work); + + /* + * Skipping first SDAM IRQ as it is requested in parent driver. + * If there is a TM violation on that IRQ, the parent driver calls + * the notifier (adctm_event_handler) exposed from this driver to handle it. + */ + for (int i = 1; i < adc_tm5->dev_data->num_sdams; i++) { + ret = devm_request_threaded_irq(dev, + adc_tm5->dev_data->base[i].irq, + NULL, adctm5_gen3_isr, IRQF_ONESHOT, + adc_tm5->dev_data->base[i].irq_name, + adc_tm5); + if (ret < 0) + return ret; + } + + /* + * This drvdata is only used in the function (adctm_event_handler) + * called by parent ADC driver in case of TM violation on the first SDAM. + */ + auxiliary_set_drvdata(aux_dev, adc_tm5); + + adc5_gen3_register_tm_event_notifier(dev, adctm_event_handler); + + /* + * This is to cancel any instances of tm_handler_work scheduled by + * TM interrupt, at the time of module removal. + */ + ret = devm_add_action(dev, adc5_gen3_clear_work, adc_tm5); + if (ret) + return ret; + + ret = adc_tm5_register_tzd(adc_tm5); + if (ret) + return ret; + + /* This is to disable all ADC_TM channels in case of probe failure. */ + + return devm_add_action(dev, adc5_gen3_disable, adc_tm5); +} + +static const struct auxiliary_device_id adctm5_auxiliary_id_table[] = { + { .name = "qcom_spmi_adc5_gen3.adc5_tm_gen3", }, + { } +}; + +MODULE_DEVICE_TABLE(auxiliary, adctm5_auxiliary_id_table); + +static struct auxiliary_driver adctm5gen3_auxiliary_driver = { + .id_table = adctm5_auxiliary_id_table, + .probe = adc_tm5_probe, +}; + +module_auxiliary_driver(adctm5gen3_auxiliary_driver); + +MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("QCOM_SPMI_ADC5_GEN3"); diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c index 7bc5329fa3ed39..34ff038fbd6d22 100644 --- a/drivers/usb/class/cdc-acm.c +++ b/drivers/usb/class/cdc-acm.c @@ -2048,6 +2048,20 @@ static const struct usb_device_id acm_ids[] = { /* CH343 supports CAP_BRK, but doesn't advertise it */ { USB_DEVICE(0x1a86, 0x55d3), .driver_info = MISSING_CAP_BRK, }, + /* Exclude Exar USB serial ports */ + { USB_DEVICE(0x04e2, 0x1400), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1401), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1402), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1403), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1410), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1411), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1412), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1414), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1420), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1421), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1422), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1424), .driver_info = IGNORE_DEVICE, }, + /* * Lenovo Yoga Book 9 14IAH10 (83KJ) — INGENIC 17EF:6161 touchscreen * composite device. The CDC ACM control interface (0) uses a standard diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index ceb49f2f800418..7513f1d721bf8b 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1873,6 +1873,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->dis_split_quirk = device_property_read_bool(dev, "snps,dis-split-quirk"); + dwc->reinit_phy_on_resume = device_property_read_bool(dev, + "snps,reinit-phy-on-resume"); dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; @@ -2582,6 +2584,29 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg); } + /* + * Some platforms gate USB2 PHY power during deep sleep even + * when device_may_wakeup is true, causing register state to be + * lost. Re-initialize the PHY to ensure clean signalling. + */ + if (dwc->reinit_phy_on_resume && !PMSG_IS_AUTO(msg)) { + for (i = 0; i < dwc->num_usb2_ports; i++) { + int ret; + + ret = phy_exit(dwc->usb2_generic_phy[i]); + if (ret) + dev_warn_ratelimited(dwc->dev, + "failed to exit usb2 phy %d: %d\n", + i, ret); + + ret = phy_init(dwc->usb2_generic_phy[i]); + if (ret) + dev_warn_ratelimited(dwc->dev, + "failed to init usb2 phy %d: %d\n", + i, ret); + } + } + for (i = 0; i < dwc->num_usb2_ports; i++) phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]); for (i = 0; i < dwc->num_usb3_ports; i++) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index e0dee9d2874010..dc8f702668f072 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1409,6 +1409,7 @@ struct dwc3 { unsigned dis_metastability_quirk:1; unsigned dis_split_quirk:1; + unsigned reinit_phy_on_resume:1; unsigned enable_usb2_transceiver_delay:1; unsigned async_callbacks:1; unsigned sys_wakeup:1; diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index f43f73ac36ff1a..1c91b41ae0ff93 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "core.h" #include "glue.h" @@ -661,6 +662,12 @@ static int dwc3_qcom_probe(struct platform_device *pdev) res = *r; res.end = res.start + SDM845_QSCRATCH_BASE_OFFSET; + ret = of_clk_set_defaults(dev->of_node, false); + if (ret) { + dev_err(dev, "failed to set clk defaults: %d\n", ret); + goto clk_disable; + } + qcom->qscratch_base = devm_ioremap(dev, res.end, SDM845_QSCRATCH_SIZE); if (!qcom->qscratch_base) { dev_err(dev, "failed to map qscratch region\n"); @@ -853,6 +860,7 @@ static struct platform_driver dwc3_qcom_driver = { .pm = pm_ptr(&dwc3_qcom_dev_pm_ops), .of_match_table = dwc3_qcom_of_match, }, + .driver_managed_clk_defaults = true, }; module_platform_driver(dwc3_qcom_driver); diff --git a/drivers/usb/misc/onboard_usb_dev.c b/drivers/usb/misc/onboard_usb_dev.c index 11508ed4df2516..c786a2af0ca054 100644 --- a/drivers/usb/misc/onboard_usb_dev.c +++ b/drivers/usb/misc/onboard_usb_dev.c @@ -575,6 +575,7 @@ static struct platform_driver onboard_dev_driver = { #define VENDOR_ID_TI 0x0451 #define VENDOR_ID_VIA 0x2109 #define VENDOR_ID_XMOS 0x20B1 +#define VENDOR_ID_BISON 0x5986 /* * Returns the onboard_dev platform device that is associated with the USB @@ -688,6 +689,7 @@ static const struct usb_device_id onboard_dev_id_table[] = { { USB_DEVICE(VENDOR_ID_VIA, 0x0817) }, /* VIA VL817 3.1 HUB */ { USB_DEVICE(VENDOR_ID_VIA, 0x2817) }, /* VIA VL817 2.0 HUB */ { USB_DEVICE(VENDOR_ID_XMOS, 0x0013) }, /* XMOS XVF3500 Voice Processor */ + { USB_DEVICE(VENDOR_ID_BISON, 0x1198) }, /* Bison Electronics Inc. Integrated Camera */ {} }; MODULE_DEVICE_TABLE(usb, onboard_dev_id_table); diff --git a/drivers/usb/misc/onboard_usb_dev.h b/drivers/usb/misc/onboard_usb_dev.h index 3523f8f8a1496d..b58a158e601ffc 100644 --- a/drivers/usb/misc/onboard_usb_dev.h +++ b/drivers/usb/misc/onboard_usb_dev.h @@ -66,13 +66,6 @@ static const struct onboard_dev_pdata ti_tusb8020b_data = { .is_hub = true, }; -static const struct onboard_dev_pdata bison_intcamera_data = { - .reset_us = 1000, - .num_supplies = 1, - .supply_names = { "vdd" }, - .is_hub = false, -}; - static const struct onboard_dev_pdata corechips_sl6341_data = { .reset_us = 10000, .num_supplies = 2, @@ -134,6 +127,13 @@ static const struct onboard_dev_pdata xmos_xvf3500_data = { .is_hub = false, }; +static const struct onboard_dev_pdata bison_intcamera_data = { + .reset_us = 1000, + .num_supplies = 1, + .supply_names = { "vdd" }, + .is_hub = false, +}; + static const struct of_device_id onboard_dev_match[] = { { .compatible = "usb-a-connector", .data = &usb_a_conn_data, }, { .compatible = "usb424,2412", .data = µchip_usb424_data, }, diff --git a/drivers/usb/typec/mux/gpio-sbu-mux.c b/drivers/usb/typec/mux/gpio-sbu-mux.c index 1834f1a2dd9dd0..fb078515cefb12 100644 --- a/drivers/usb/typec/mux/gpio-sbu-mux.c +++ b/drivers/usb/typec/mux/gpio-sbu-mux.c @@ -10,6 +10,7 @@ #include #include #include +#include "../mux.h" struct gpio_sbu_mux { struct gpio_desc *enable_gpio; @@ -30,6 +31,9 @@ static int gpio_sbu_switch_set(struct typec_switch_dev *sw, bool enabled; bool swapped; + /* print out call parameter */ + printk(KERN_INFO "%s: gpio_sbu_switch_set() enter orientation=%d, altmode=%d, swapped=%d\n", dev_name(&sw->dev),orientation,sbu_mux->enabled,sbu_mux->swapped); + mutex_lock(&sbu_mux->lock); enabled = sbu_mux->enabled; @@ -58,6 +62,9 @@ static int gpio_sbu_switch_set(struct typec_switch_dev *sw, mutex_unlock(&sbu_mux->lock); + /* print out result */ + printk(KERN_INFO "%s: gpio_sbu_switch_set() exit orientation=%d, altmode=%d, swapped=%d\n", dev_name(&sw->dev),orientation,enabled,swapped); + return 0; } @@ -69,6 +76,9 @@ static int gpio_sbu_mux_set(struct typec_mux_dev *mux, if (!sbu_mux->enable_gpio) return -EOPNOTSUPP; + /* print out call parameter */ + printk(KERN_INFO "%s: gpio_sbu_mux_set() enter mode=%d, altmode=%d\n", dev_name(&mux->dev),(int)state->mode,sbu_mux->enabled); + mutex_lock(&sbu_mux->lock); switch (state->mode) { @@ -89,6 +99,9 @@ static int gpio_sbu_mux_set(struct typec_mux_dev *mux, mutex_unlock(&sbu_mux->lock); + /* print out result */ + printk(KERN_INFO "%s: gpio_sbu_mux_set() exit mode=%d, altmode=%d\n", dev_name(&mux->dev),(int)state->mode,sbu_mux->enabled); + return 0; } @@ -138,6 +151,9 @@ static int gpio_sbu_mux_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sbu_mux); + /* anounce device is loaded */ + printk(KERN_INFO "%s: registered type-c switch/mux\n", dev_name(dev)); + return 0; } diff --git a/drivers/usb/typec/mux/ps883x.c b/drivers/usb/typec/mux/ps883x.c index 64e0a61b776a18..152b2b397f396f 100644 --- a/drivers/usb/typec/mux/ps883x.c +++ b/drivers/usb/typec/mux/ps883x.c @@ -62,6 +62,7 @@ struct ps883x_retimer { enum typec_orientation orientation; bool in_reset; + bool disable_usb4; }; static int ps883x_enable_vregs(struct ps883x_retimer *retimer) @@ -184,9 +185,30 @@ static int ps883x_configure(struct ps883x_retimer *retimer, int cfg0, return ret; } + usleep_range(20000, 30000); + return 0; } +static void ps883x_apply_dp_altmode(int *cfg0, int *cfg1, int dp_state) +{ + *cfg1 |= CONN_STATUS_1_DP_CONNECTED | CONN_STATUS_1_DP_HPD_LEVEL; + + switch (dp_state) { + case TYPEC_DP_STATE_D: + case TYPEC_DP_STATE_F: + *cfg0 |= CONN_STATUS_0_USB_3_1_CONNECTED; + fallthrough; + case TYPEC_DP_STATE_C: + case TYPEC_DP_STATE_E: + *cfg1 |= CONN_STATUS_1_DP_SINK_REQUESTED | + CONN_STATUS_1_DP_PIN_ASSIGNMENT_C_D; + break; + default: + break; + } +} + static int ps883x_set(struct ps883x_retimer *retimer, struct typec_retimer_state *state) { struct typec_thunderbolt_data *tb_data; @@ -202,20 +224,7 @@ static int ps883x_set(struct ps883x_retimer *retimer, struct typec_retimer_state if (state->alt) { switch (state->alt->svid) { case USB_TYPEC_DP_SID: - cfg1 |= CONN_STATUS_1_DP_CONNECTED | - CONN_STATUS_1_DP_HPD_LEVEL; - - switch (state->mode) { - case TYPEC_DP_STATE_D: - cfg0 |= CONN_STATUS_0_USB_3_1_CONNECTED; - fallthrough; - case TYPEC_DP_STATE_C: - cfg1 |= CONN_STATUS_1_DP_SINK_REQUESTED | - CONN_STATUS_1_DP_PIN_ASSIGNMENT_C_D; - break; - default: /* MODE_E */ - break; - } + ps883x_apply_dp_altmode(&cfg0, &cfg1, state->mode); break; case USB_TYPEC_TBT_SID: tb_data = state->data; @@ -249,6 +258,13 @@ static int ps883x_set(struct ps883x_retimer *retimer, struct typec_retimer_state cfg0 |= CONN_STATUS_0_USB_3_1_CONNECTED; break; case TYPEC_MODE_USB4: + if (retimer->disable_usb4) { + dev_info(&retimer->client->dev, + "USB4 disabled via DT property, rejecting USB4 mode\n"); + return -EOPNOTSUPP; + } + + /* Normal USB4 handling */ eudo_data = state->data; cfg2 |= CONN_STATUS_2_USB4_CONNECTED; @@ -369,7 +385,6 @@ static int ps883x_retimer_probe(struct i2c_client *client) struct typec_switch_desc sw_desc = { }; struct typec_retimer_desc rtmr_desc = { }; struct ps883x_retimer *retimer; - unsigned int val; int ret; retimer = devm_kzalloc(dev, sizeof(*retimer), GFP_KERNEL); @@ -378,6 +393,8 @@ static int ps883x_retimer_probe(struct i2c_client *client) retimer->client = client; + retimer->disable_usb4 = device_property_read_bool(dev, "parade,disable-usb4"); + mutex_init(&retimer->lock); retimer->regmap = devm_regmap_init_i2c(client, &ps883x_retimer_regmap); @@ -439,16 +456,6 @@ static int ps883x_retimer_probe(struct i2c_client *client) /* firmware initialization delay */ msleep(60); - - /* make sure device is accessible */ - ret = regmap_read(retimer->regmap, REG_USB_PORT_CONN_STATUS_0, - &val); - if (ret) { - dev_err(dev, "failed to read conn_status_0: %d\n", ret); - if (ret == -ENXIO) - ret = -EIO; - goto err_clk_disable; - } } /* Keep the retimer in reset until a Type-C notification comes */ diff --git a/drivers/usb/typec/ucsi/ucsi.c b/drivers/usb/typec/ucsi/ucsi.c index 49f1c53721bbda..12c95c2ed99e25 100644 --- a/drivers/usb/typec/ucsi/ucsi.c +++ b/drivers/usb/typec/ucsi/ucsi.c @@ -304,10 +304,13 @@ static void ucsi_poll_worker(struct work_struct *work) mutex_lock(&con->lock); - if (!con->partner) { - list_del(&uwork->node); + if (!con->partner || !con->wq) { + /* + * Workqueue is being destroyed. Don't free the work item here; + * ucsi_destroy_connector_wq() will handle cleanup to avoid + * use-after-free race. + */ mutex_unlock(&con->lock); - kfree(uwork); return; } @@ -323,13 +326,50 @@ static void ucsi_poll_worker(struct work_struct *work) mutex_unlock(&con->lock); } +/** + * ucsi_destroy_connector_wq - Safely destroy connector workqueue + * @con: UCSI connector + * + * Cancel all pending delayed work and destroy the workqueue to prevent + * timer races where delayed work tries to queue on destroyed workqueue. + */ +static void ucsi_destroy_connector_wq(struct ucsi_connector *con) +{ + struct workqueue_struct *wq; + struct ucsi_work *uwork, *tmp; + LIST_HEAD(list); + + if (!con->wq) + return; + + /* + * Prevent new work from being queued and signal existing work to stop. + * Move all work items to a temporary list while holding the lock, + * then cancel them without the lock to avoid deadlock with + * ucsi_poll_worker() which also acquires con->lock. + */ + mutex_lock(&con->lock); + wq = con->wq; + con->wq = NULL; /* Signal workers to stop before canceling */ + list_splice_init(&con->partner_tasks, &list); + mutex_unlock(&con->lock); + + list_for_each_entry_safe(uwork, tmp, &list, node) { + cancel_delayed_work_sync(&uwork->work); + list_del(&uwork->node); + kfree(uwork); + } + + destroy_workqueue(wq); +} + static int ucsi_partner_task(struct ucsi_connector *con, int (*cb)(struct ucsi_connector *), int retries, unsigned long delay) { struct ucsi_work *uwork; - if (!con->partner) + if (!con->partner || !con->wq) return 0; uwork = kzalloc_obj(*uwork); @@ -1574,7 +1614,7 @@ void ucsi_connector_change(struct ucsi *ucsi, u8 num) con = &ucsi->connector[num - 1]; if (!test_and_set_bit(EVENT_PENDING, &ucsi->flags)) - schedule_work(&con->work); + queue_work(system_freezable_wq, &con->work); } EXPORT_SYMBOL_GPL(ucsi_connector_change); @@ -2092,6 +2132,8 @@ static int ucsi_init(struct ucsi *ucsi) if (ret < 0) goto err_reset; + dev_info(ucsi->dev, "UCSI features: 0x%04x\n", ucsi->cap.features); + if (!ucsi->cap.num_connectors) { ret = -ENODEV; goto err_reset; diff --git a/fs/ceph/mdsmap.c b/fs/ceph/mdsmap.c index 450a4dc9662e53..ddb4ce17b2b27a 100644 --- a/fs/ceph/mdsmap.c +++ b/fs/ceph/mdsmap.c @@ -13,6 +13,7 @@ #include "mdsmap.h" #include "mds_client.h" #include "super.h" +#include "mdsmap.h" #define CEPH_MDS_IS_READY(i, ignore_laggy) \ (m->m_info[i].state > 0 && (ignore_laggy ? true : !m->m_info[i].laggy)) diff --git a/fs/file.c b/fs/file.c index 628ca07dc4b179..cd6ac9e9e43fdb 100644 --- a/fs/file.c +++ b/fs/file.c @@ -886,6 +886,7 @@ struct file *file_close_fd(unsigned int fd) return file; } +EXPORT_SYMBOL(file_close_fd); void do_close_on_exec(struct files_struct *files) { diff --git a/fs/namei.c b/fs/namei.c index 19ce43c9a6e662..447d9291cfab7c 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -1201,8 +1201,8 @@ static inline void put_link(struct nameidata *nd) path_put(&last->link); } -static int sysctl_protected_symlinks __read_mostly; -static int sysctl_protected_hardlinks __read_mostly; +static int sysctl_protected_symlinks __read_mostly = 1; +static int sysctl_protected_hardlinks __read_mostly = 1; static int sysctl_protected_fifos __read_mostly; static int sysctl_protected_regular __read_mostly; diff --git a/fs/overlayfs/params.c b/fs/overlayfs/params.c index c93fcaa45d4a36..9e851dcf82a5b0 100644 --- a/fs/overlayfs/params.c +++ b/fs/overlayfs/params.c @@ -55,6 +55,7 @@ enum ovl_opt { Opt_uuid, Opt_nfs_export, Opt_userxattr, + Opt_nouserxattr, Opt_xino, Opt_metacopy, Opt_verity, @@ -170,6 +171,7 @@ const struct fs_parameter_spec ovl_parameter_spec[] = { fsparam_enum("uuid", Opt_uuid, ovl_parameter_uuid), fsparam_enum("nfs_export", Opt_nfs_export, ovl_parameter_bool), fsparam_flag("userxattr", Opt_userxattr), + fsparam_flag("nouserxattr", Opt_nouserxattr), fsparam_enum("xino", Opt_xino, ovl_parameter_xino), fsparam_enum("metacopy", Opt_metacopy, ovl_parameter_bool), fsparam_enum("verity", Opt_verity, ovl_parameter_verity), @@ -716,6 +718,9 @@ static int ovl_parse_param(struct fs_context *fc, struct fs_parameter *param) put_cred(cred); break; } + case Opt_nouserxattr: + config->userxattr = false; + break; default: pr_err("unrecognized mount option \"%s\" or missing value\n", param->key); @@ -823,6 +828,8 @@ int ovl_init_fs_context(struct fs_context *fc) ofs->config.xino = ovl_xino_def(); ofs->config.metacopy = ovl_metacopy_def; ofs->config.fsync_mode = ovl_fsync_mode_def(); + if (fc->user_ns != &init_user_ns) + ofs->config.userxattr = true; fc->s_fs_info = ofs; fc->fs_private = ctx; @@ -1097,6 +1104,8 @@ int ovl_show_options(struct seq_file *m, struct dentry *dentry) seq_printf(m, ",fsync=%s", ovl_fsync_mode(&ofs->config)); if (ofs->config.userxattr) seq_puts(m, ",userxattr"); + else + seq_puts(m, ",nouserxattr"); if (ofs->config.verity_mode != ovl_verity_mode_def()) seq_printf(m, ",verity=%s", ovl_verity_mode(&ofs->config)); diff --git a/fs/proc/Makefile b/fs/proc/Makefile index 8bc615ff84e5d7..ea62a3590a8a09 100644 --- a/fs/proc/Makefile +++ b/fs/proc/Makefile @@ -35,4 +35,4 @@ proc-$(CONFIG_PROC_KCORE) += kcore.o proc-$(CONFIG_PROC_VMCORE) += vmcore.o proc-$(CONFIG_PRINTK) += kmsg.o proc-$(CONFIG_PROC_PAGE_MONITOR) += page.o -proc-$(CONFIG_BOOT_CONFIG) += bootconfig.o +proc-$(CONFIG_BOOT_CONFIG) += bootconfig.o version_signature.o diff --git a/fs/proc/version_signature.c b/fs/proc/version_signature.c new file mode 100644 index 00000000000000..1feb4dfa1ddd2f --- /dev/null +++ b/fs/proc/version_signature.c @@ -0,0 +1,32 @@ +#include +#include +#include +#include +#include +#include +#include + +static int version_signature_proc_show(struct seq_file *m, void *v) +{ + seq_printf(m, "%s\n", CONFIG_VERSION_SIGNATURE); + return 0; +} + +static int version_signature_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, version_signature_proc_show, NULL); +} + +static const struct proc_ops version_signature_proc_fops = { + .proc_open = version_signature_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = single_release, +}; + +static int __init proc_version_signature_init(void) +{ + proc_create("version_signature", 0, NULL, &version_signature_proc_fops); + return 0; +} +module_init(proc_version_signature_init); diff --git a/include/asm-generic/mshyperv.h b/include/asm-generic/mshyperv.h index bf601d67cecb9f..8dd63d85086dd0 100644 --- a/include/asm-generic/mshyperv.h +++ b/include/asm-generic/mshyperv.h @@ -165,6 +165,14 @@ static inline u64 hv_do_rep_hypercall(u16 code, u16 rep_count, u16 varhead_size, input, output); } +#ifndef PKG_ABI +/* + * Preserve the ability to 'make deb-pkg' since PKG_ABI is provided + * by the Ubuntu build rules. + */ +#define PKG_ABI 0 +#endif + /* Generate the guest OS identifier as described in the Hyper-V TLFS */ static inline u64 hv_generate_guest_id(u64 kernel_version) { @@ -172,6 +180,7 @@ static inline u64 hv_generate_guest_id(u64 kernel_version) guest_id = (((u64)HV_LINUX_VENDOR_ID) << 48); guest_id |= (kernel_version << 16); + guest_id |= PKG_ABI; return guest_id; } diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h index ebda2a37f52aa0..373ef65f992ddd 100644 --- a/include/dt-bindings/dma/qcom-gpi.h +++ b/include/dt-bindings/dma/qcom-gpi.h @@ -7,5 +7,6 @@ #define QCOM_GPI_SPI 1 #define QCOM_GPI_UART 2 #define QCOM_GPI_I2C 3 +#define QCOM_GPI_QSPI 4 #endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */ diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h index 0d29d8d4829ce4..776d2cad6047f1 100644 --- a/include/dt-bindings/firmware/qcom,scm.h +++ b/include/dt-bindings/firmware/qcom,scm.h @@ -37,4 +37,7 @@ #define QCOM_SCM_VMID_OEMVM 0x31 #define QCOM_SCM_VMID_CP_ADSP_SHARED 0x33 +/* Special value intended for qcom,shm-bridge-vmid */ +#define QCOM_SCM_VMID_SELF_OWNER 0xffffffff + #endif diff --git a/include/dt-bindings/iio/adc/qcom,pm8550-adc5-gen3.h b/include/dt-bindings/iio/adc/qcom,pm8550-adc5-gen3.h new file mode 100644 index 00000000000000..9940715683b400 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,pm8550-adc5-gen3.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H + +#include + +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ +#define PM8550_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8550_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PM8550_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) +#define PM8550_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8550_ADC5_GEN3_AMUX_THM1(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM) +#define PM8550_ADC5_GEN3_AMUX_THM2(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM) +#define PM8550_ADC5_GEN3_AMUX_THM3(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM) +#define PM8550_ADC5_GEN3_AMUX_THM4(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM) +#define PM8550_ADC5_GEN3_AMUX_THM5(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO) + +/* 100k pull-up */ +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) + +/* 1/3 Divider */ +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_DIV3) + +#define PM8550_ADC5_GEN3_VPH_PWR(sid) ((sid) << 8 | ADC5_GEN3_VPH_PWR) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */ diff --git a/include/dt-bindings/iio/adc/qcom,pmk8550-adc5-gen3.h b/include/dt-bindings/iio/adc/qcom,pmk8550-adc5-gen3.h new file mode 100644 index 00000000000000..88fed365cc9ebf --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,pmk8550-adc5-gen3.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H + +#include + +/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */ +#define PMK8550_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PMK8550_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PMK8550_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) +#define PMK8550_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO) + +/* 30k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU) + +/* 100k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) + +/* 400k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h new file mode 100644 index 00000000000000..73efd8fda4b2b3 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h @@ -0,0 +1,384 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_H + +/* Voltage ADC channels */ +#define VADC_USBIN 0x00 +#define VADC_DCIN 0x01 +#define VADC_VCHG_SNS 0x02 +#define VADC_SPARE1_03 0x03 +#define VADC_USB_ID_MV 0x04 +#define VADC_VCOIN 0x05 +#define VADC_VBAT_SNS 0x06 +#define VADC_VSYS 0x07 +#define VADC_DIE_TEMP 0x08 +#define VADC_REF_625MV 0x09 +#define VADC_REF_1250MV 0x0a +#define VADC_CHG_TEMP 0x0b +#define VADC_SPARE1 0x0c +#define VADC_SPARE2 0x0d +#define VADC_GND_REF 0x0e +#define VADC_VDD_VADC 0x0f + +#define VADC_P_MUX1_1_1 0x10 +#define VADC_P_MUX2_1_1 0x11 +#define VADC_P_MUX3_1_1 0x12 +#define VADC_P_MUX4_1_1 0x13 +#define VADC_P_MUX5_1_1 0x14 +#define VADC_P_MUX6_1_1 0x15 +#define VADC_P_MUX7_1_1 0x16 +#define VADC_P_MUX8_1_1 0x17 +#define VADC_P_MUX9_1_1 0x18 +#define VADC_P_MUX10_1_1 0x19 +#define VADC_P_MUX11_1_1 0x1a +#define VADC_P_MUX12_1_1 0x1b +#define VADC_P_MUX13_1_1 0x1c +#define VADC_P_MUX14_1_1 0x1d +#define VADC_P_MUX15_1_1 0x1e +#define VADC_P_MUX16_1_1 0x1f + +#define VADC_P_MUX1_1_3 0x20 +#define VADC_P_MUX2_1_3 0x21 +#define VADC_P_MUX3_1_3 0x22 +#define VADC_P_MUX4_1_3 0x23 +#define VADC_P_MUX5_1_3 0x24 +#define VADC_P_MUX6_1_3 0x25 +#define VADC_P_MUX7_1_3 0x26 +#define VADC_P_MUX8_1_3 0x27 +#define VADC_P_MUX9_1_3 0x28 +#define VADC_P_MUX10_1_3 0x29 +#define VADC_P_MUX11_1_3 0x2a +#define VADC_P_MUX12_1_3 0x2b +#define VADC_P_MUX13_1_3 0x2c +#define VADC_P_MUX14_1_3 0x2d +#define VADC_P_MUX15_1_3 0x2e +#define VADC_P_MUX16_1_3 0x2f + +#define VADC_LR_MUX1_BAT_THERM 0x30 +#define VADC_LR_MUX2_BAT_ID 0x31 +#define VADC_LR_MUX3_XO_THERM 0x32 +#define VADC_LR_MUX4_AMUX_THM1 0x33 +#define VADC_LR_MUX5_AMUX_THM2 0x34 +#define VADC_LR_MUX6_AMUX_THM3 0x35 +#define VADC_LR_MUX7_HW_ID 0x36 +#define VADC_LR_MUX8_AMUX_THM4 0x37 +#define VADC_LR_MUX9_AMUX_THM5 0x38 +#define VADC_LR_MUX10_USB_ID 0x39 +#define VADC_AMUX_PU1 0x3a +#define VADC_AMUX_PU2 0x3b +#define VADC_LR_MUX3_BUF_XO_THERM 0x3c + +#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 +#define VADC_LR_MUX2_PU1_BAT_ID 0x71 +#define VADC_LR_MUX3_PU1_XO_THERM 0x72 +#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 +#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 +#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 +#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 +#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 +#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 +#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 +#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c + +#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 +#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 +#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 +#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 +#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 +#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 +#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 +#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 +#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 +#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 +#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc + +#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 +#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 +#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 +#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 +#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 +#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 +#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 +#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 +#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 +#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 +#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc + +/* ADC channels for SPMI PMIC5 */ + +#define ADC5_REF_GND 0x00 +#define ADC5_1P25VREF 0x01 +#define ADC5_VREF_VADC 0x02 +#define ADC5_VREF_VADC5_DIV_3 0x82 +#define ADC5_VPH_PWR 0x83 +#define ADC5_VBAT_SNS 0x84 +#define ADC5_VCOIN 0x85 +#define ADC5_DIE_TEMP 0x06 +#define ADC5_USB_IN_I 0x07 +#define ADC5_USB_IN_V_16 0x08 +#define ADC5_CHG_TEMP 0x09 +#define ADC5_BAT_THERM 0x0a +#define ADC5_BAT_ID 0x0b +#define ADC5_XO_THERM 0x0c +#define ADC5_AMUX_THM1 0x0d +#define ADC5_AMUX_THM2 0x0e +#define ADC5_AMUX_THM3 0x0f +#define ADC5_AMUX_THM4 0x10 +#define ADC5_AMUX_THM5 0x11 +#define ADC5_GPIO1 0x12 +#define ADC5_GPIO2 0x13 +#define ADC5_GPIO3 0x14 +#define ADC5_GPIO4 0x15 +#define ADC5_GPIO5 0x16 +#define ADC5_GPIO6 0x17 +#define ADC5_GPIO7 0x18 +#define ADC5_SBUx 0x99 +#define ADC5_MID_CHG_DIV6 0x1e +#define ADC5_OFF 0xff + +/* 30k pull-up1 */ +#define ADC5_BAT_THERM_30K_PU 0x2a +#define ADC5_BAT_ID_30K_PU 0x2b +#define ADC5_XO_THERM_30K_PU 0x2c +#define ADC5_AMUX_THM1_30K_PU 0x2d +#define ADC5_AMUX_THM2_30K_PU 0x2e +#define ADC5_AMUX_THM3_30K_PU 0x2f +#define ADC5_AMUX_THM4_30K_PU 0x30 +#define ADC5_AMUX_THM5_30K_PU 0x31 +#define ADC5_GPIO1_30K_PU 0x32 +#define ADC5_GPIO2_30K_PU 0x33 +#define ADC5_GPIO3_30K_PU 0x34 +#define ADC5_GPIO4_30K_PU 0x35 +#define ADC5_GPIO5_30K_PU 0x36 +#define ADC5_GPIO6_30K_PU 0x37 +#define ADC5_GPIO7_30K_PU 0x38 +#define ADC5_SBUx_30K_PU 0x39 + +/* 100k pull-up2 */ +#define ADC5_BAT_THERM_100K_PU 0x4a +#define ADC5_BAT_ID_100K_PU 0x4b +#define ADC5_XO_THERM_100K_PU 0x4c +#define ADC5_AMUX_THM1_100K_PU 0x4d +#define ADC5_AMUX_THM2_100K_PU 0x4e +#define ADC5_AMUX_THM3_100K_PU 0x4f +#define ADC5_AMUX_THM4_100K_PU 0x50 +#define ADC5_AMUX_THM5_100K_PU 0x51 +#define ADC5_GPIO1_100K_PU 0x52 +#define ADC5_GPIO2_100K_PU 0x53 +#define ADC5_GPIO3_100K_PU 0x54 +#define ADC5_GPIO4_100K_PU 0x55 +#define ADC5_GPIO5_100K_PU 0x56 +#define ADC5_GPIO6_100K_PU 0x57 +#define ADC5_GPIO7_100K_PU 0x58 +#define ADC5_SBUx_100K_PU 0x59 + +/* 400k pull-up3 */ +#define ADC5_BAT_THERM_400K_PU 0x6a +#define ADC5_BAT_ID_400K_PU 0x6b +#define ADC5_XO_THERM_400K_PU 0x6c +#define ADC5_AMUX_THM1_400K_PU 0x6d +#define ADC5_AMUX_THM2_400K_PU 0x6e +#define ADC5_AMUX_THM3_400K_PU 0x6f +#define ADC5_AMUX_THM4_400K_PU 0x70 +#define ADC5_AMUX_THM5_400K_PU 0x71 +#define ADC5_GPIO1_400K_PU 0x72 +#define ADC5_GPIO2_400K_PU 0x73 +#define ADC5_GPIO3_400K_PU 0x74 +#define ADC5_GPIO4_400K_PU 0x75 +#define ADC5_GPIO5_400K_PU 0x76 +#define ADC5_GPIO6_400K_PU 0x77 +#define ADC5_GPIO7_400K_PU 0x78 +#define ADC5_SBUx_400K_PU 0x79 + +/* 1/3 Divider */ +#define ADC5_GPIO1_DIV3 0x92 +#define ADC5_GPIO2_DIV3 0x93 +#define ADC5_GPIO3_DIV3 0x94 +#define ADC5_GPIO4_DIV3 0x95 +#define ADC5_GPIO5_DIV3 0x96 +#define ADC5_GPIO6_DIV3 0x97 +#define ADC5_GPIO7_DIV3 0x98 +#define ADC5_SBUx_DIV3 0x99 + +/* Current and combined current/voltage channels */ +#define ADC5_INT_EXT_ISENSE 0xa1 +#define ADC5_PARALLEL_ISENSE 0xa5 +#define ADC5_CUR_REPLICA_VDS 0xa7 +#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 +#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab +#define ADC5_EXT_SENS_OFFSET 0xad + +#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 +#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 +#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 +#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 +#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 +#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 + +#define ADC5_MAX_CHANNEL 0xc0 + +/* ADC channels for ADC for PMIC7 */ + +#define ADC7_REF_GND 0x00 +#define ADC7_1P25VREF 0x01 +#define ADC7_VREF_VADC 0x02 +#define ADC7_DIE_TEMP 0x03 + +#define ADC7_AMUX_THM1 0x04 +#define ADC7_AMUX_THM2 0x05 +#define ADC7_AMUX_THM3 0x06 +#define ADC7_AMUX_THM4 0x07 +#define ADC7_AMUX_THM5 0x08 +#define ADC7_AMUX_THM6 0x09 +#define ADC7_GPIO1 0x0a +#define ADC7_GPIO2 0x0b +#define ADC7_GPIO3 0x0c +#define ADC7_GPIO4 0x0d + +#define ADC7_SMB_TEMP 0x06 +#define ADC7_CHG_TEMP 0x10 +#define ADC7_USB_IN_V_16 0x11 +#define ADC7_VDC_16 0x12 +#define ADC7_CC1_ID 0x13 +#define ADC7_VREF_BAT_THERM 0x15 +#define ADC7_IIN_FB 0x17 +#define ADC7_ICHG_SMB 0x18 +#define ADC7_IIN_SMB 0x19 + +/* 30k pull-up1 */ +#define ADC7_AMUX_THM1_30K_PU 0x24 +#define ADC7_AMUX_THM2_30K_PU 0x25 +#define ADC7_AMUX_THM3_30K_PU 0x26 +#define ADC7_AMUX_THM4_30K_PU 0x27 +#define ADC7_AMUX_THM5_30K_PU 0x28 +#define ADC7_AMUX_THM6_30K_PU 0x29 +#define ADC7_GPIO1_30K_PU 0x2a +#define ADC7_GPIO2_30K_PU 0x2b +#define ADC7_GPIO3_30K_PU 0x2c +#define ADC7_GPIO4_30K_PU 0x2d +#define ADC7_CC1_ID_30K_PU 0x33 + +/* 100k pull-up2 */ +#define ADC7_AMUX_THM1_100K_PU 0x44 +#define ADC7_AMUX_THM2_100K_PU 0x45 +#define ADC7_AMUX_THM3_100K_PU 0x46 +#define ADC7_AMUX_THM4_100K_PU 0x47 +#define ADC7_AMUX_THM5_100K_PU 0x48 +#define ADC7_AMUX_THM6_100K_PU 0x49 +#define ADC7_GPIO1_100K_PU 0x4a +#define ADC7_GPIO2_100K_PU 0x4b +#define ADC7_GPIO3_100K_PU 0x4c +#define ADC7_GPIO4_100K_PU 0x4d +#define ADC7_CC1_ID_100K_PU 0x53 + +/* 400k pull-up3 */ +#define ADC7_AMUX_THM1_400K_PU 0x64 +#define ADC7_AMUX_THM2_400K_PU 0x65 +#define ADC7_AMUX_THM3_400K_PU 0x66 +#define ADC7_AMUX_THM4_400K_PU 0x67 +#define ADC7_AMUX_THM5_400K_PU 0x68 +#define ADC7_AMUX_THM6_400K_PU 0x69 +#define ADC7_GPIO1_400K_PU 0x6a +#define ADC7_GPIO2_400K_PU 0x6b +#define ADC7_GPIO3_400K_PU 0x6c +#define ADC7_GPIO4_400K_PU 0x6d +#define ADC7_CC1_ID_400K_PU 0x73 + +/* 1/3 Divider */ +#define ADC7_GPIO1_DIV3 0x8a +#define ADC7_GPIO2_DIV3 0x8b +#define ADC7_GPIO3_DIV3 0x8c +#define ADC7_GPIO4_DIV3 0x8d + +#define ADC7_VPH_PWR 0x8e +#define ADC7_VBAT_SNS 0x8f + +#define ADC7_SBUx 0x94 +#define ADC7_VBAT_2S_MID 0x96 + +/* ADC channels for PMIC5 Gen3 */ + +#define ADC5_GEN3_REF_GND 0x00 +#define ADC5_GEN3_1P25VREF 0x01 +#define ADC5_GEN3_VREF_VADC 0x02 +#define ADC5_GEN3_DIE_TEMP 0x03 + +#define ADC5_GEN3_AMUX1_THM 0x04 +#define ADC5_GEN3_AMUX2_THM 0x05 +#define ADC5_GEN3_AMUX3_THM 0x06 +#define ADC5_GEN3_AMUX4_THM 0x07 +#define ADC5_GEN3_AMUX5_THM 0x08 +#define ADC5_GEN3_AMUX6_THM 0x09 +#define ADC5_GEN3_AMUX1_GPIO 0x0a +#define ADC5_GEN3_AMUX2_GPIO 0x0b +#define ADC5_GEN3_AMUX3_GPIO 0x0c +#define ADC5_GEN3_AMUX4_GPIO 0x0d + +#define ADC5_GEN3_CHG_TEMP 0x10 +#define ADC5_GEN3_USB_SNS_V_16 0x11 +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 +#define ADC5_GEN3_VREF_BAT_THERM 0x15 +#define ADC5_GEN3_IIN_FB 0x17 +#define ADC5_GEN3_TEMP_ALARM_LITE 0x18 +#define ADC5_GEN3_IIN_SMB 0x19 +#define ADC5_GEN3_ICHG_SMB 0x1b +#define ADC5_GEN3_ICHG_FB 0xa1 + +/* 30k pull-up1 */ +#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24 +#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25 +#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26 +#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27 +#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28 +#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29 +#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a +#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b +#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c +#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d + +/* 100k pull-up2 */ +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d + +/* 400k pull-up3 */ +#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64 +#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65 +#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66 +#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67 +#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68 +#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69 +#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a +#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b +#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c +#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d + +/* 1/3 Divider */ +#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a +#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b +#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c +#define ADC5_GEN3_AMUX4_GPIO_DIV3 0x8d + +#define ADC5_GEN3_VPH_PWR 0x8e +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f + +#define ADC5_GEN3_VBAT_SNS_CHGR 0x94 +#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96 +#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d + +#define ADC5_GEN3_OFFSET_EXT2 0xf8 + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ diff --git a/include/hyperv/hvgdk.h b/include/hyperv/hvgdk.h index f538144280ca55..4d00330e719c14 100644 --- a/include/hyperv/hvgdk.h +++ b/include/hyperv/hvgdk.h @@ -21,7 +21,7 @@ * 15:0 - Distro specific identification */ -#define HV_LINUX_VENDOR_ID 0x8100 +#define HV_LINUX_VENDOR_ID 0x80 /* Canonical */ /* HV_VMX_ENLIGHTENED_VMCS */ struct hv_enlightened_vmcs { diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index d83c9175828f79..4106b6b3721171 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -46,9 +46,8 @@ struct adreno_smmu_fault_info { * @get_fault_info: Called by the GPU fault handler to get information about * the fault * @set_stall: Configure whether stall on fault (CFCFG) is enabled. If - * stalling on fault is enabled, the GPU driver must call - * resume_translation() - * @resume_translation: Resume translation after a fault + * stalling on fault is enabled, the GPU driver should return + * -EAGAIN from the fault handler if retrying is required. * * @set_prr_bit: [optional] Configure the GPU's Partially Resident * Region (PRR) bit in the ACTLR register. @@ -71,7 +70,6 @@ struct adreno_smmu_priv { int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); void (*set_stall)(const void *cookie, bool enabled); - void (*resume_translation)(const void *cookie, bool terminate); void (*set_prr_bit)(const void *cookie, bool set); void (*set_prr_addr)(const void *cookie, phys_addr_t page_addr); }; diff --git a/include/linux/clk.h b/include/linux/clk.h index 998ba3f261dac7..31a0c9224c46c2 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -846,6 +846,20 @@ void devm_clk_put(struct device *dev, struct clk *clk); */ +/* + * clk_sync_state - sync_state callback to disable unused clocks + * @dev: the clock provider device whose unused clocks should be disabled + * + * It is called by the driver core once all consumers of @dev have probed, + * and disables any clocks belonging to @dev that are unused at that point. + * + * If a clock provider doesn't have a sync_state callback, then the framework + * will set up clk_sync_state() on your drivers behalf. If your driver needs + * a sync_state callback, then that callback also needs to call + * clk_sync_state(). + */ +void clk_sync_state(struct device *dev); + /** * clk_round_rate - adjust a rate to the exact rate a clock can provide * @clk: clock source diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-dma.h index 332be28427e472..efb4efd9c8b8d6 100644 --- a/include/linux/dma/qcom-gpi-dma.h +++ b/include/linux/dma/qcom-gpi-dma.h @@ -16,6 +16,7 @@ enum spi_transfer_cmd { SPI_TX = 1, SPI_RX, SPI_DUPLEX, + SPI_TX_RX = 7, /* QSPI full-duplex (TX opcode+addr, RX data) */ }; /** @@ -36,6 +37,7 @@ enum spi_transfer_cmd { */ struct gpi_spi_config { u8 set_config; + u8 qspi; u8 loopback_en; u8 clock_pol_high; u8 data_pol_high; @@ -47,6 +49,11 @@ struct gpi_spi_config { u32 clk_src; enum spi_transfer_cmd cmd; u32 rx_len; + /* QSPI extensions */ + bool qspi_mode; + u16 qspi_lane_flags; + u8 dummy_clk_cnt; + u16 tx_cmd_len; }; enum i2c_op { diff --git a/include/linux/efi.h b/include/linux/efi.h index ccbc35479684a0..4d1c3e69917954 100644 --- a/include/linux/efi.h +++ b/include/linux/efi.h @@ -45,6 +45,8 @@ struct screen_info; #define EFI_ABORTED (21 | (1UL << (BITS_PER_LONG-1))) #define EFI_SECURITY_VIOLATION (26 | (1UL << (BITS_PER_LONG-1))) +#define EFI_IS_ERROR(x) ((x) & (1UL << (BITS_PER_LONG-1))) + typedef unsigned long efi_status_t; typedef u8 efi_bool_t; typedef u16 efi_char16_t; /* UNICODE character */ @@ -847,6 +849,23 @@ extern int __init parse_efi_signature_list( #define EFI_MEM_ATTR 9 /* Did firmware publish an EFI_MEMORY_ATTRIBUTES table? */ #define EFI_MEM_NO_SOFT_RESERVE 10 /* Is the kernel configured to ignore soft reservations? */ #define EFI_PRESERVE_BS_REGIONS 11 /* Are EFI boot-services memory segments available? */ +#define EFI_SECURE_BOOT 12 /* Are we in Secure Boot mode? */ + +enum efi_secureboot_mode { + efi_secureboot_mode_unset, + efi_secureboot_mode_unknown, + efi_secureboot_mode_disabled, + efi_secureboot_mode_enabled, +}; + +#ifdef CONFIG_EFI_PARAMS_FROM_FDT +u32 __init efi_get__secure_boot(void); +#else +static inline u32 efi_get__secure_boot(void) +{ + return efi_secureboot_mode_unset; +}; +#endif #ifdef CONFIG_EFI /* @@ -858,6 +877,8 @@ static inline bool efi_enabled(int feature) } extern void efi_reboot(enum reboot_mode reboot_mode, const char *__unused); +extern void __init efi_set_secure_boot(enum efi_secureboot_mode mode); + bool __pure __efi_soft_reserve_enabled(void); static inline bool __pure efi_soft_reserve_enabled(void) @@ -879,6 +900,8 @@ static inline bool efi_enabled(int feature) static inline void efi_reboot(enum reboot_mode reboot_mode, const char *__unused) {} +static inline void efi_set_secure_boot(enum efi_secureboot_mode mode) {} + static inline bool efi_soft_reserve_enabled(void) { return false; @@ -893,6 +916,7 @@ static inline void efi_find_mirror(void) {} #endif extern int efi_status_to_err(efi_status_t status); +extern const char *efi_status_to_str(efi_status_t status); /* * Variable Attributes @@ -1110,13 +1134,6 @@ extern unsigned long efi_call_virt_save_flags(void); void efi_runtime_assert_lock_held(void); -enum efi_secureboot_mode { - efi_secureboot_mode_unset, - efi_secureboot_mode_unknown, - efi_secureboot_mode_disabled, - efi_secureboot_mode_enabled, -}; - static inline enum efi_secureboot_mode efi_get_secureboot_mode(efi_get_variable_t *get_var) { diff --git a/include/linux/hid.h b/include/linux/hid.h index b240baa95ab5bb..bc1684706a8f78 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -441,6 +441,7 @@ struct hid_item { #define HID_GROUP_STEAM 0x0103 #define HID_GROUP_LOGITECH_27MHZ_DEVICE 0x0104 #define HID_GROUP_VIVALDI 0x0105 +#define HID_GROUP_MSHW0485_IPTS 0x0106 /* * HID protocol status @@ -819,6 +820,8 @@ struct hid_descriptor { .bus = BUS_BLUETOOTH, .vendor = (ven), .product = (prod) #define HID_I2C_DEVICE(ven, prod) \ .bus = BUS_I2C, .vendor = (ven), .product = (prod) +#define HID_SPI_DEVICE(ven, prod) \ + .bus = BUS_SPI, .vendor = (ven), .product = (prod) #define HID_REPORT_ID(rep) \ .report_type = (rep) diff --git a/include/linux/ipc_namespace.h b/include/linux/ipc_namespace.h index 12faca29bbb9c3..5bf174df249e65 100644 --- a/include/linux/ipc_namespace.h +++ b/include/linux/ipc_namespace.h @@ -128,6 +128,9 @@ extern int mq_init_ns(struct ipc_namespace *ns); static inline int mq_init_ns(struct ipc_namespace *ns) { return 0; } #endif +extern struct ipc_namespace *get_ipc_ns_exported(struct ipc_namespace *ns); +extern struct ipc_namespace *show_init_ipc_ns(void); + #if defined(CONFIG_IPC_NS) static inline struct ipc_namespace *to_ipc_ns(struct ns_common *ns) { diff --git a/include/linux/lsm_hook_defs.h b/include/linux/lsm_hook_defs.h index 65c9609ec20770..2cc243ec73f62a 100644 --- a/include/linux/lsm_hook_defs.h +++ b/include/linux/lsm_hook_defs.h @@ -456,6 +456,7 @@ LSM_HOOK(int, 0, bpf_token_capable, const struct bpf_token *token, int cap) LSM_HOOK(int, 0, locked_down, enum lockdown_reason what) + #ifdef CONFIG_PERF_EVENTS LSM_HOOK(int, 0, perf_event_open, int type) LSM_HOOK(int, 0, perf_event_alloc, struct perf_event *event) diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h index b4f8cad53ddb03..d6870f74df4b2f 100644 --- a/include/linux/lsm_hooks.h +++ b/include/linux/lsm_hooks.h @@ -120,6 +120,7 @@ struct lsm_blob_sizes { unsigned int lbs_bpf_map; unsigned int lbs_bpf_prog; unsigned int lbs_bpf_token; + bool lbs_secmark; /* expressed desire for secmark use */ }; /* diff --git a/include/linux/pci.h b/include/linux/pci.h index 64b308b6e61c19..e02373320d81a5 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -510,6 +510,7 @@ struct pci_dev { unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ unsigned int non_mappable_bars:1; /* BARs can't be mapped by CPU or peers */ + unsigned int aspm_os_control:1; /* Display of ROM attribute enabled? */ pci_dev_flags_t dev_flags; atomic_t enable_cnt; /* pci_enable_device has been called */ @@ -1920,7 +1921,7 @@ int pci_enable_link_state(struct pci_dev *pdev, int state); int pci_enable_link_state_locked(struct pci_dev *pdev, int state); void pcie_no_aspm(void); bool pcie_aspm_support_enabled(void); -bool pcie_aspm_enabled(struct pci_dev *pdev); +u32 pcie_aspm_enabled(struct pci_dev *pdev); #else static inline int pci_disable_link_state(struct pci_dev *pdev, int state) { return 0; } @@ -1932,7 +1933,7 @@ static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state) { return 0; } static inline void pcie_no_aspm(void) { } static inline bool pcie_aspm_support_enabled(void) { return false; } -static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } +static inline u32 pcie_aspm_enabled(struct pci_dev *pdev) { return false; } #endif #ifdef CONFIG_HOTPLUG_PCI diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 48d851fbd8ea58..6cdc23fb7e0932 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1784,6 +1784,12 @@ extern void perf_sample_event_took(u64 sample_len_ns); #define PERF_SECURITY_CPU 1 #define PERF_SECURITY_KERNEL 2 #define PERF_SECURITY_TRACEPOINT 3 +#define PERF_SECURITY_MAX 4 + +static inline bool perf_paranoid_any(void) +{ + return sysctl_perf_event_paranoid >= PERF_SECURITY_MAX; +} static inline int perf_is_paranoid(void) { diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index ea47975e288aea..df52c47c5bbe8a 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -41,6 +41,7 @@ enum phy_mode { PHY_MODE_PCIE, PHY_MODE_ETHERNET, PHY_MODE_MIPI_DPHY, + PHY_MODE_MIPI_CPHY, PHY_MODE_SATA, PHY_MODE_LVDS, PHY_MODE_DP, diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 8c566f09d04efe..e012e5ea47ed7a 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -284,6 +284,12 @@ struct platform_driver { * to setup and manage their own I/O address space. */ bool driver_managed_dma; + /* + * Skip calling of_clk_set_defaults() before calling the probe function. + * Use this if the driver needs to perform some initialization before + * clock defaults (parent, rates) are applied. + */ + bool driver_managed_clk_defaults; }; #define to_platform_driver(drv) (container_of((drv), struct platform_driver, \ diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h index 7c1546d4800825..4000729cd17aec 100644 --- a/include/linux/remoteproc.h +++ b/include/linux/remoteproc.h @@ -236,6 +236,27 @@ enum rproc_features { RPROC_MAX_FEATURES, }; +/** + * enum rproc_auto_boot - auto boot strategy for remoteproc during initial boot + * + * @RPROC_AUTO_BOOT_DISABLED: The remoteproc will be left offline (or detached). + * @RPROC_AUTO_BOOT_ATTACH_OR_START: The remoteproc will be attached (if it is + * already running). Otherwise, it will be + * started with new loaded firmware. + * @RPROC_FEAT_REBOOT_IF_FW_AVAILABLE: The remoteproc will be restarted if + * requesting new firmware succeeds. If + * the firmware is missing and the + * remoteproc is already running, it will + * be attached instead. A remoteproc + * implementing this must handle stop() + * being called in detached state. + */ +enum rproc_auto_boot { + RPROC_AUTO_BOOT_DISABLED, + RPROC_AUTO_BOOT_ATTACH_OR_START, + RPROC_AUTO_BOOT_RESTART_IF_FW_AVAILABLE, +}; + /** * struct rproc - represents a physical remote processor device * @node: list node of this rproc object @@ -310,7 +331,7 @@ struct rproc { struct resource_table *cached_table; size_t table_sz; bool has_iommu; - bool auto_boot; + enum rproc_auto_boot auto_boot; bool sysfs_read_only; struct list_head dump_segments; int nb_vdev; diff --git a/include/linux/rpmsg.h b/include/linux/rpmsg.h index 0171c490339cfc..5eda676aba0fcf 100644 --- a/include/linux/rpmsg.h +++ b/include/linux/rpmsg.h @@ -177,6 +177,8 @@ void rpmsg_destroy_ept(struct rpmsg_endpoint *); struct rpmsg_endpoint *rpmsg_create_ept(struct rpmsg_device *, rpmsg_rx_cb_t cb, void *priv, struct rpmsg_channel_info chinfo); +struct rpmsg_endpoint *rpmsg_dev_open_ept(struct rpmsg_device *rpdev, + rpmsg_rx_cb_t cb, void *priv); int rpmsg_send(struct rpmsg_endpoint *ept, const void *data, int len); int rpmsg_sendto(struct rpmsg_endpoint *ept, const void *data, int len, u32 dst); @@ -245,6 +247,16 @@ static inline struct rpmsg_endpoint *rpmsg_create_ept(struct rpmsg_device *rpdev return NULL; } +static inline struct rpmsg_endpoint *rpmsg_dev_open_ept(struct rpmsg_device *rpdev, + rpmsg_rx_cb_t cb, + void *priv) +{ + /* This shouldn't be possible */ + WARN_ON(1); + + return NULL; +} + static inline int rpmsg_send(struct rpmsg_endpoint *ept, const void *data, int len) { /* This shouldn't be possible */ diff --git a/include/linux/security.h b/include/linux/security.h index 153e9043058f88..2ee3a8990968ad 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -2439,4 +2439,13 @@ static inline void security_initramfs_populated(void) } #endif /* CONFIG_SECURITY */ +#ifdef CONFIG_SECURITY_LOCKDOWN_LSM +extern int security_lock_kernel_down(const char *where, enum lockdown_reason level); +#else +static inline int security_lock_kernel_down(const char *where, enum lockdown_reason level) +{ + return 0; +} +#endif /* CONFIG_SECURITY_LOCKDOWN_LSM */ + #endif /* ! __LINUX_SECURITY_H */ diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h index 79dd44922fbcae..b3c74c876b83fa 100644 --- a/include/linux/soundwire/sdw.h +++ b/include/linux/soundwire/sdw.h @@ -305,7 +305,14 @@ struct sdw_dp0_prop { * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register * @simple_ch_prep_sm: If the port supports simplified channel prepare state * machine + * @simple_transport_registers: Optional banked transport registers implemented + * by a SIMPLE port in addition to the mandatory SIMPLE register set. */ +#define SDW_DPN_SIMPLE_TRANSPORT_BLOCKCTRL3 BIT(0) +#define SDW_DPN_SIMPLE_TRANSPORT_SAMPLECTRL2 BIT(1) +#define SDW_DPN_SIMPLE_TRANSPORT_HCTRL BIT(2) +#define SDW_DPN_SIMPLE_TRANSPORT_OFFSETCTRL2 BIT(3) + struct sdw_dpn_prop { u32 num; u32 max_word; @@ -330,6 +337,7 @@ struct sdw_dpn_prop { bool block_pack_mode; bool read_only_wordlength; bool simple_ch_prep_sm; + u32 simple_transport_registers; }; /** @@ -890,10 +898,18 @@ void sdw_show_ping_status(struct sdw_bus *bus, bool sync_delay); * * @num: Port number * @ch_mask: channels mask for port + * @transport_params_override_mask: Bitmask selecting slave transport fields + * which override values computed by the bus master. Master port parameters are + * never affected by these per-slave overrides. + * @transport_params_override: Values for the selected transport fields. */ +#define SDW_PORT_CONFIG_OVERRIDE_OFFSET1 BIT(0) + struct sdw_port_config { unsigned int num; unsigned int ch_mask; + unsigned int transport_params_override_mask; + struct sdw_transport_params transport_params_override; }; /** diff --git a/include/linux/spi/spi-geni-qcom-biosref.h b/include/linux/spi/spi-geni-qcom-biosref.h new file mode 100644 index 00000000000000..bb7cebe9246211 --- /dev/null +++ b/include/linux/spi/spi-geni-qcom-biosref.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_SPI_GENI_QCOM_BIOSREF_H +#define _LINUX_SPI_GENI_QCOM_BIOSREF_H + +#include + +struct spi_device; + +/* + * Execute the asymmetric FIFO/polled transaction recovered from Surface UEFI + * SPIDxe protocol 0x09. This is deliberately not representable as an ordinary + * struct spi_transfer because the command has independent TX and RX lengths. + */ +int qcom_geni_spi_biosref_xfer(struct spi_device *spi, + const void *tx_buf, size_t tx_len, + void *rx_buf, size_t rx_len, + u32 speed_hz, unsigned int timeout_ms); + +#endif diff --git a/include/linux/user_namespace.h b/include/linux/user_namespace.h index 9c3be157397e02..f25153e2a2a6e1 100644 --- a/include/linux/user_namespace.h +++ b/include/linux/user_namespace.h @@ -204,6 +204,8 @@ extern bool in_userns(const struct user_namespace *ancestor, const struct user_namespace *child); extern bool current_in_userns(const struct user_namespace *target_ns); struct ns_common *ns_get_owner(struct ns_common *ns); + +extern int unprivileged_userns_clone; #else static inline struct user_namespace *get_user_ns(struct user_namespace *ns) diff --git a/include/net/ip_tunnels.h b/include/net/ip_tunnels.h index d708b66e55cda5..ff98129ff5dd3c 100644 --- a/include/net/ip_tunnels.h +++ b/include/net/ip_tunnels.h @@ -138,6 +138,28 @@ struct ip_tunnel_prl_entry { }; struct metadata_dst; +/* A fan overlay /8 (250.0.0.0/8, for example) maps to exactly one /16 + * underlay (10.88.0.0/16, for example). Multiple local addresses within + * the /16 may be used, but a particular overlay may not span + * multiple underlay subnets. + * + * We store one underlay, indexed by the overlay's high order octet. + */ +#define FAN_OVERLAY_CNT 256 + +struct ip_fan_map { + __be32 underlay; + __be32 overlay; + u16 underlay_prefix; + u16 overlay_prefix; + u32 overlay_mask; + struct list_head list; + struct rcu_head rcu; +}; + +struct ip_tunnel_fan { + struct list_head fan_maps; +}; /* Kernel-side variant of ip_tunnel_parm */ struct ip_tunnel_parm_kern { @@ -189,6 +211,7 @@ struct ip_tunnel { #endif struct ip_tunnel_prl_entry __rcu *prl; /* potential router list */ unsigned int prl_count; /* # of entries in PRL */ + struct ip_tunnel_fan fan; unsigned int ip_tnl_net_id; struct gro_cells gro_cells; __u32 fwmark; @@ -196,6 +219,11 @@ struct ip_tunnel { bool ignore_df; }; +static inline int fan_has_map(const struct ip_tunnel_fan *fan) +{ + return !list_empty(&fan->fan_maps); +} + struct tnl_ptk_info { IP_TUNNEL_DECLARE_FLAGS(flags); __be16 proto; diff --git a/include/net/vxlan.h b/include/net/vxlan.h index dfba89695efcfa..d5beb9fb354e95 100644 --- a/include/net/vxlan.h +++ b/include/net/vxlan.h @@ -296,6 +296,8 @@ struct vxlan_dev { struct net *net; /* netns for packet i/o */ struct vxlan_rdst default_dst; /* default destination */ + struct ip_tunnel_fan fan; + struct timer_list age_timer; spinlock_t hash_lock; unsigned int addrcnt; diff --git a/include/uapi/asm-generic/fcntl.h b/include/uapi/asm-generic/fcntl.h index 883cfd7de2effa..128a52b119c445 100644 --- a/include/uapi/asm-generic/fcntl.h +++ b/include/uapi/asm-generic/fcntl.h @@ -126,13 +126,11 @@ #define F_GETSIG 11 /* for sockets. */ #endif -#if __BITS_PER_LONG == 32 || defined(__KERNEL__) #ifndef F_GETLK64 #define F_GETLK64 12 /* using 'struct flock64' */ #define F_SETLK64 13 #define F_SETLKW64 14 #endif -#endif /* __BITS_PER_LONG == 32 || defined(__KERNEL__) */ #ifndef F_SETOWN_EX #define F_SETOWN_EX 15 diff --git a/include/uapi/linux/apparmor.h b/include/uapi/linux/apparmor.h new file mode 100644 index 00000000000000..a8333e1e2d2014 --- /dev/null +++ b/include/uapi/linux/apparmor.h @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _UAPI_LINUX_APPARMOR_H +#define _UAPI_LINUX_APPARMOR_H + +#include + +#define APPARMOR_MODESET_AUDIT 1 +#define APPARMOR_MODESET_ALLOWED 2 +#define APPARMOR_MODESET_ENFORCE 4 +#define APPARMOR_MODESET_HINT 8 +#define APPARMOR_MODESET_STATUS 16 +#define APPARMOR_MODESET_ERROR 32 +#define APPARMOR_MODESET_KILL 64 +#define APPARMOR_MODESET_USER 128 + +#define APPARMOR_FLAG_NOCACHE 1 + +enum apparmor_notif_type { + APPARMOR_NOTIF_RESP_PERM, + APPARMOR_NOTIF_CANCEL, + APPARMOR_NOTIF_INTERUPT, + APPARMOR_NOTIF_ALIVE, + APPARMOR_NOTIF_OP, + APPARMOR_NOTIF_RESP_NAME, +}; + +#define APPARMOR_NOTIFY_V3 3 +#define APPARMOR_NOTIFY_V5 5 +#define APPARMOR_NOTIFY_VERSION 5 + +/* base notification struct embedded as head of notifications to userspace */ +struct apparmor_notif_common { + __u16 len; /* actual len data */ + __u16 version; /* interface version */ +} __attribute__((packed)); + +struct apparmor_notif_register_v5 { + struct apparmor_notif_common base; + __u64 listener_id; /* unique id for listener */ +} __attribute__((packed)); + +struct apparmor_notif_resend_v5 { + struct apparmor_notif_common base; + __u64 listener_id; /* unique id for listener */ + __u32 ready; /* notifications that are ready */ + __u32 pending; /* notifs that are pendying reply */ +} __attribute__((packed)); + +struct apparmor_notif_filter { + struct apparmor_notif_common base; + __u32 modeset; /* which notification mode */ + __u32 ns; /* offset into data */ + __u32 filter; /* offset into data */ + + __u8 data[]; +} __attribute__((packed)); + +// flags +#define URESPONSE_NO_CACHE 1 +#define URESPONSE_LOOKUP 2 +#define URESPONSE_PROFILE 4 +#define URESPONSE_TAILGLOB 8 +#define UNOTIF_RESENT 0x10 + +struct apparmor_notif { + struct apparmor_notif_common base; + __u16 ntype; /* notify type */ + __u8 signalled; + __u8 flags; + __u64 id; /* unique id, not gloablly unique*/ + __s32 error; /* error if unchanged */ +} __attribute__((packed)); + + +struct apparmor_notif_update { + struct apparmor_notif base; + __u16 ttl; /* max keep alives left */ +} __attribute__((packed)); + +/* userspace response to notification that expects a response */ +struct apparmor_notif_resp_perm { + struct apparmor_notif base; + __s32 error; /* error if unchanged */ + __u32 allow; + __u32 deny; +} __attribute__((packed)); + +struct apparmor_notif_resp_name { + union { + struct apparmor_notif base; + struct apparmor_notif_resp_perm perm; + }; + __u32 name; + __u8 data[]; +} __attribute__((packed)); + +struct apparmor_notif_op { + struct apparmor_notif base; + __u32 allow; + __u32 deny; + pid_t pid; /* pid of task causing notification */ + __u32 label; /* offset into data */ + __u16 class; + __u16 op; +} __attribute__((packed)); + +struct apparmor_tags_header_v5 { + __u32 mask; + __u32 count; + __u32 tagset; +}; + +// v3 doesn't have tags but this just adds padding to the data section +struct apparmor_notif_file { + struct apparmor_notif_op base; + uid_t subj_uid, obj_uid; + __u32 name; /* offset into data */ + __u8 data[]; +} __attribute__((packed)); + +struct apparmor_notif_file_v5 { + struct apparmor_notif_op base; + uid_t subj_uid, obj_uid; + __u32 name; /* offset into data */ + __u32 tags; + __u16 tags_count; + __u8 data[]; +} __attribute__((packed)); + +/* ioctl structs */ +union apparmor_notif_filters { + struct { + struct apparmor_notif_common base; + __u32 modeset; /* which notification mode */ + __u32 ns; /* offset into data */ + __u32 filter; /* offset into data */ + + __u8 data[]; + }; + /* common and defined before vX, replicates v3 */ + struct apparmor_notif_filter v3; + struct apparmor_notif_filter v5; +} __attribute__((packed)); + +union apparmor_notif_recv { + /* common and defined before vX, replicates v3 */ + struct { + struct apparmor_notif_op base; + uid_t subj_uid, obj_uid; + __u32 name; /* offset into data */ + __u8 data[]; + }; + struct { + struct apparmor_notif_file file; + } v3; + struct { + struct apparmor_notif_file_v5 file; + } v5; +} __attribute__((packed)); + +union apparmor_notif_resp { + /* common and defined before vX, replicates v3 */ + struct apparmor_notif base; + struct apparmor_notif_resp_perm perm; + struct apparmor_notif_resp_name name; + union { + struct apparmor_notif_resp_perm perm; + struct apparmor_notif_resp_name name; + } v3; + union { + struct apparmor_notif_resp_perm perm; + struct apparmor_notif_resp_name name; + } v5; +} __attribute__((packed)); + +union apparmor_notif_register { + struct { + struct apparmor_notif_register_v5 registration; + struct apparmor_notif_resend_v5 resend; + } v5; +} __attribute__((packed)); + +union apparmor_notif_all { + struct apparmor_notif_common common; + struct apparmor_notif base; + struct apparmor_notif_op op; + struct apparmor_notif_file filev3; + struct apparmor_notif_file_v5 file; + union apparmor_notif_filters filter; + union apparmor_notif_recv recv; + union apparmor_notif_resp respnse; + union apparmor_notif_register registration; +} __attribute__((packed)); + +#define APPARMOR_IOC_MAGIC 0xF8 + +/* Flags for apparmor notification fd ioctl. */ + +#define APPARMOR_NOTIF_SET_FILTER _IOW(APPARMOR_IOC_MAGIC, 0, \ + union apparmor_notif_filters *) +#define APPARMOR_NOTIF_GET_FILTER _IOR(APPARMOR_IOC_MAGIC, 1, \ + union apparmor_notif_filters *) +#define APPARMOR_NOTIF_IS_ID_VALID _IOR(APPARMOR_IOC_MAGIC, 3, \ + __u64) +/* RECV/SEND from userspace pov */ +#define APPARMOR_NOTIF_RECV _IOWR(APPARMOR_IOC_MAGIC, 4, \ + union apparmor_notif_recv *) +#define APPARMOR_NOTIF_SEND _IOWR(APPARMOR_IOC_MAGIC, 5, \ + union apparmor_notif_resp *) +#define APPARMOR_NOTIF_REGISTER _IOWR(APPARMOR_IOC_MAGIC, 6, \ + union apparmor_notif_register *) +#define APPARMOR_NOTIF_RESEND _IOWR(APPARMOR_IOC_MAGIC, 7, \ + union apparmor_notif_register *) + + +#endif /* _UAPI_LINUX_APPARMOR_H */ diff --git a/include/uapi/linux/g6ts_heat.h b/include/uapi/linux/g6ts_heat.h new file mode 100644 index 00000000000000..827f23e2ce8934 --- /dev/null +++ b/include/uapi/linux/g6ts_heat.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _UAPI_LINUX_G6TS_HEAT_H +#define _UAPI_LINUX_G6TS_HEAT_H + +#include +#include + +#define G6TS_HEAT_ABI_VERSION 1U +#define G6TS_HEAT_RECORD_MAGIC 0x31483647U /* "G6H1", little-endian */ +#define G6TS_HEAT_RECORD_HEADER_SIZE 32U +#define G6TS_HEAT_MAX_CONTENT_SIZE 4349U + +#define G6TS_HEAT_RECORD_F_RESET (1U << 0) +#define G6TS_HEAT_RECORD_F_SUSPEND (1U << 1) +#define G6TS_HEAT_RECORD_F_TRANSPORT_FAULT (1U << 2) + +/* + * One read returns one complete header followed by content_len exact report + * content bytes. The HID report ID is carried separately in report_id. + * All multibyte members are little-endian and this header has no padding. + */ +struct g6ts_heat_record_header { + __le32 magic; + __le16 abi_version; + __le16 header_len; + __le32 record_len; + __le32 generation; + __le64 timestamp_ns; + __le32 sequence; + __le16 content_len; + __u8 report_id; + __u8 flags; +} __attribute__((__packed__)); + +struct g6ts_heat_info { + __le16 abi_version; + __le16 struct_size; + __le16 record_header_size; + __le16 reserved0; + __le32 max_content_size; + __le32 queue_capacity; + __le64 supported_record_flags; + __le64 reserved[3]; +}; + +struct g6ts_heat_stats { + __le16 abi_version; + __le16 struct_size; + __le32 generation; + __le32 queued_records; + __le32 queue_capacity; + __le64 records_enqueued; + __le64 records_dropped; + __le64 queue_flushes; + __le64 oversize_drops; + __le64 report_0b; + __le64 report_0c; + __le64 report_0d; + __le64 report_1a; + __le64 reserved[4]; +}; + +#define G6TS_HEAT_IOC_MAGIC 'G' +#define G6TS_HEAT_IOC_GET_INFO \ + _IOR(G6TS_HEAT_IOC_MAGIC, 0x00, struct g6ts_heat_info) +#define G6TS_HEAT_IOC_GET_STATS \ + _IOR(G6TS_HEAT_IOC_MAGIC, 0x01, struct g6ts_heat_stats) + +#endif /* _UAPI_LINUX_G6TS_HEAT_H */ diff --git a/include/uapi/linux/if_link.h b/include/uapi/linux/if_link.h index 43cecca49f017a..2eb78f6c5d5b7f 100644 --- a/include/uapi/linux/if_link.h +++ b/include/uapi/linux/if_link.h @@ -1463,6 +1463,7 @@ enum { IFLA_VXLAN_LABEL_POLICY, /* IPv6 flow label policy; ifla_vxlan_label_policy */ IFLA_VXLAN_RESERVED_BITS, IFLA_VXLAN_MC_ROUTE, + IFLA_VXLAN_FAN_MAP, __IFLA_VXLAN_MAX }; #define IFLA_VXLAN_MAX (__IFLA_VXLAN_MAX - 1) diff --git a/include/uapi/linux/if_tunnel.h b/include/uapi/linux/if_tunnel.h index e1a246dd8c620b..74709064c94d50 100644 --- a/include/uapi/linux/if_tunnel.h +++ b/include/uapi/linux/if_tunnel.h @@ -77,6 +77,10 @@ enum { IFLA_IPTUN_ENCAP_DPORT, IFLA_IPTUN_COLLECT_METADATA, IFLA_IPTUN_FWMARK, + + __IFLA_IPTUN_VENDOR_BREAK, /* Ensure new entries do not hit the below. */ + IFLA_IPTUN_FAN_MAP = 33, + __IFLA_IPTUN_MAX, }; #define IFLA_IPTUN_MAX (__IFLA_IPTUN_MAX - 1) @@ -218,4 +222,19 @@ enum { __IP_TUNNEL_FLAG_NUM, }; +enum { + IFLA_FAN_UNSPEC, + IFLA_FAN_MAPPING, + __IFLA_FAN_MAX, +}; + +#define IFLA_FAN_MAX (__IFLA_FAN_MAX - 1) + +struct ifla_fan_map { + __be32 underlay; + __be32 overlay; + __u16 underlay_prefix; + __u16 overlay_prefix; +}; + #endif /* _UAPI_IF_TUNNEL_H_ */ diff --git a/include/uapi/linux/rfkill.h b/include/uapi/linux/rfkill.h index db6c8588c1d0c1..9b77cfc42efa3b 100644 --- a/include/uapi/linux/rfkill.h +++ b/include/uapi/linux/rfkill.h @@ -159,16 +159,8 @@ struct rfkill_event_ext { * old behaviour for all userspace, unless it explicitly opts in to the * rules outlined here by using the new &struct rfkill_event_ext. * - * Additionally, some other userspace (bluez, g-s-d) was reading with a - * large size but as streaming reads rather than message-based, or with - * too strict checks for the returned size. So eventually, we completely - * reverted this, and extended messages need to be opted in to by using - * an ioctl: - * - * ioctl(fd, RFKILL_IOCTL_MAX_SIZE, sizeof(struct rfkill_event_ext)); - * - * Userspace using &struct rfkill_event_ext and the ioctl must adhere to - * the following rules: + * Userspace using &struct rfkill_event_ext must adhere to the following + * rules * * 1. accept short writes, optionally using them to detect that it's * running on an older kernel; @@ -183,8 +175,6 @@ struct rfkill_event_ext { #define RFKILL_IOC_MAGIC 'R' #define RFKILL_IOC_NOINPUT 1 #define RFKILL_IOCTL_NOINPUT _IO(RFKILL_IOC_MAGIC, RFKILL_IOC_NOINPUT) -#define RFKILL_IOC_MAX_SIZE 2 -#define RFKILL_IOCTL_MAX_SIZE _IOW(RFKILL_IOC_MAGIC, RFKILL_IOC_MAX_SIZE, __u32) /* and that's all userspace gets */ diff --git a/include/uapi/linux/sysctl.h b/include/uapi/linux/sysctl.h index bda5160641746f..2b83ff6184f76f 100644 --- a/include/uapi/linux/sysctl.h +++ b/include/uapi/linux/sysctl.h @@ -152,7 +152,7 @@ enum KERN_NMI_WATCHDOG=75, /* int: enable/disable nmi watchdog */ KERN_PANIC_ON_NMI=76, /* int: whether we will panic on an unrecovered */ KERN_PANIC_ON_WARN=77, /* int: call panic() in WARN() functions */ - KERN_PANIC_PRINT=78, /* ulong: bitmask to print system info on panic */ + KERN_PANIC_PRINT=78, /* unsigned long: bitmask to print system info on panic */ }; diff --git a/include/uapi/linux/tty_flags.h b/include/uapi/linux/tty_flags.h index cf25056d4b27ef..03f0a7cfca2e56 100644 --- a/include/uapi/linux/tty_flags.h +++ b/include/uapi/linux/tty_flags.h @@ -32,6 +32,7 @@ #define ASYNCB_AUTOPROBE 15 /* [x] Port was autoprobed by PCI/PNP code */ #define ASYNCB_MAGIC_MULTIPLIER 16 /* Use special CLK or divisor */ #define ASYNCB_LAST_USER 16 +#define ASYNCB_INITIALIZED 31 /* Serial port was initialized */ /* * Internal flags used only by kernel (read-only) @@ -40,7 +41,6 @@ * TTY_PORT_ flags in the iflags field (and not userspace-visible) */ #ifndef __KERNEL__ -#define ASYNCB_INITIALIZED 31 /* Serial port was initialized */ #define ASYNCB_SUSPENDED 30 /* Serial port is suspended */ #define ASYNCB_NORMAL_ACTIVE 29 /* Normal device is active */ #define ASYNCB_BOOT_AUTOCONF 28 /* Autoconfigure port on bootup */ diff --git a/include/uapi/sound/snd_ar_tokens.h b/include/uapi/sound/snd_ar_tokens.h index 6b8102eaa121f1..235fcf841f6a70 100644 --- a/include/uapi/sound/snd_ar_tokens.h +++ b/include/uapi/sound/snd_ar_tokens.h @@ -96,6 +96,10 @@ enum ar_event_types { * APM_PROC_DOMAIN_ID_SDSP = 4, * APM_PROC_DOMAIN_ID_CDSP = 5 * + * %AR_TKN_U32_CONTAINER_PARENT_ID: Parent container instance ID. + * + * %AR_TKN_U32_CONTAINER_HEAP_ID: Container heap ID. + * * %AR_TKN_U32_MODULE_ID: Module ID * * %AR_TKN_U32_MODULE_INSTANCE_ID: Module Instance ID. @@ -112,6 +116,16 @@ enum ar_event_types { * * %AR_TKN_U32_MODULE_DST_IN_PORT_ID: Destination module input port ID * + * %AR_TKN_U32_MODULE_SPEAKER_PROTECTION_BYPASS: + * Leave speaker-protection modules + * in their default disabled state. + * 0 = automatic setup, + * 1 = bypass. + * + * %AR_TKN_U32_MODULE_INTEGRATED_BACKEND_ID: + * Backend DAI ID represented inside + * the same graph as the frontend. + * * %AR_TKN_U32_MODULE_HW_IF_IDX: Interface index types for I2S/LPAIF * * %AR_TKN_U32_MODULE_HW_IF_TYPE: Interface type @@ -186,6 +200,8 @@ enum ar_event_types { #define AR_TKN_U32_CONTAINER_STACK_SIZE 102 #define AR_TKN_U32_CONTAINER_GRAPH_POS 103 #define AR_TKN_U32_CONTAINER_PROC_DOMAIN 104 +#define AR_TKN_U32_CONTAINER_PARENT_ID 105 +#define AR_TKN_U32_CONTAINER_HEAP_ID 106 /* Module Tokens */ #define AR_TKN_U32_MODULE_ID 200 @@ -239,8 +255,28 @@ enum ar_event_types { #define AR_TKN_U32_MODULE_LOG_CODE 259 #define AR_TKN_U32_MODULE_LOG_TAP_POINT_ID 260 #define AR_TKN_U32_MODULE_LOG_MODE 261 +#define AR_TKN_U32_MODULE_SPEAKER_PROTECTION_BYPASS 262 +#define AR_TKN_U32_MODULE_INTEGRATED_BACKEND_ID 263 #define SND_SOC_AR_TPLG_MODULE_CFG_TYPE 0x01001006 +/* + * Private byte-array payload for APM_PARAM_ID_MODULE_CTRL_LINK_CFG. + * The data begins with num_ctrl_link_cfg and is copied into GRAPH_OPEN. + */ +#define SND_SOC_AR_TPLG_CTRL_LINK_CFG_TYPE 0x08001061 + +/* Ordered, validated SP11 calibration stages. */ +#define SND_SOC_AR_TPLG_GRAPH_CAL_CFG_TYPE 0x53503101 +#define SND_SOC_AR_TPLG_RENDER_EP_CFG_TYPE 0x53503102 +#define SND_SOC_AR_TPLG_SP_TAG_CFG_TYPE 0x53503103 +#define SND_SOC_AR_TPLG_SPVI_TAG_CFG_TYPE 0x53503104 +#define SND_SOC_AR_TPLG_VI_EP_CFG_TYPE 0x53503105 +#define SND_SOC_AR_TPLG_PROTECTION_DYNAMIC_CFG_TYPE 0x53503106 +#define SND_SOC_AR_TPLG_VOLUME_GAIN_CFG_TYPE 0x53503107 +#define SND_SOC_AR_TPLG_VOLUME_FILTER_CFG_TYPE 0x53503108 +#define SND_SOC_AR_TPLG_VOLUME_MUTE_CFG_TYPE 0x53503109 +#define SND_SOC_AR_TPLG_CHANNEL_MIXER_CFG_TYPE 0x5350310A + struct audioreach_module_priv_data { __le32 size; /* size in bytes of the array, including all elements */ __le32 type; /* SND_SOC_AR_TPLG_MODULE_CFG_TYPE */ diff --git a/init/Kconfig b/init/Kconfig index 10f2013b532169..b2b0e1d2973b9e 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -467,6 +467,15 @@ config DEFAULT_HOSTNAME but you may wish to use a different default here to make a minimal system more usable with less configuration. +config VERSION_SIGNATURE + string "Arbitrary version signature" + help + This string will be created in a file, /proc/version_signature. It + is useful in determining arbitrary data about your kernel. For instance, + if you have several kernels of the same version, but need to keep track + of a revision of the same kernel, but not affect it's ability to load + compatible modules, this is the easiest way to do that. + config SYSVIPC bool "System V IPC" help diff --git a/init/do_mounts.c b/init/do_mounts.c index 95e0b3a0f711bd..85cb13d7b541e5 100644 --- a/init/do_mounts.c +++ b/init/do_mounts.c @@ -456,6 +456,8 @@ static dev_t __init parse_root_device(char *root_device_name) */ void __init prepare_namespace(void) { + int err; + if (root_delay) { printk(KERN_INFO "Waiting %d sec before mounting root device...\n", root_delay); @@ -492,6 +494,14 @@ void __init prepare_namespace(void) return; } pr_info("VFS: Pivoted into new rootfs\n"); + +#ifdef CONFIG_BLOCK + /* recreate the /dev/root */ + err = create_dev("/dev/root", ROOT_DEV); + + if (err < 0) + pr_emerg("Failed to create /dev/root: %d\n", err); +#endif } static bool is_tmpfs; diff --git a/init/version-timestamp.c b/init/version-timestamp.c index 375726e05f690f..60c309e1db063d 100644 --- a/init/version-timestamp.c +++ b/init/version-timestamp.c @@ -23,4 +23,8 @@ struct uts_namespace init_uts_ns = { /* FIXED STRINGS! Don't touch! */ const char linux_banner[] = "Linux version " UTS_RELEASE " (" LINUX_COMPILE_BY "@" - LINUX_COMPILE_HOST ") (" LINUX_COMPILER ") " UTS_VERSION "\n"; + LINUX_COMPILE_HOST ") (" LINUX_COMPILER ") " UTS_VERSION +#ifdef CONFIG_VERSION_SIGNATURE + " (" CONFIG_VERSION_SIGNATURE ")" +#endif + "\n"; diff --git a/ipc/mqueue.c b/ipc/mqueue.c index 4798b375972bf4..716915771390c0 100644 --- a/ipc/mqueue.c +++ b/ipc/mqueue.c @@ -593,6 +593,15 @@ static int mqueue_create_attr(struct dentry *dentry, umode_t mode, void *arg) ipc_ns->mq_queues_count--; goto out_unlock; } + error = security_inode_init_security(inode, dir, + &dentry->d_name, NULL, + NULL); + if (error) { + iput(inode); + spin_lock(&mq_lock); + ipc_ns->mq_queues_count--; + goto out_unlock; + } put_ipc_ns(ipc_ns); dir->i_size += DIRENT_SIZE; diff --git a/ipc/namespace.c b/ipc/namespace.c index 1e71353bdb4a33..40414a58ae9a98 100644 --- a/ipc/namespace.c +++ b/ipc/namespace.c @@ -210,6 +210,23 @@ void put_ipc_ns(struct ipc_namespace *ns) schedule_work(&free_ipc_work); } } +EXPORT_SYMBOL(put_ipc_ns); + +struct ipc_namespace *get_ipc_ns_exported(struct ipc_namespace *ns) +{ + return get_ipc_ns(ns); +} +EXPORT_SYMBOL(get_ipc_ns_exported); + +struct ipc_namespace *show_init_ipc_ns(void) +{ +#if defined(CONFIG_IPC_NS) + return &init_ipc_ns; +#else + return NULL; +#endif +} +EXPORT_SYMBOL(show_init_ipc_ns); static struct ns_common *ipcns_get(struct task_struct *task) { diff --git a/kernel/events/core.c b/kernel/events/core.c index 1a73ba0747df85..a3a6c36182ba86 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -492,8 +492,13 @@ static __always_inline bool is_guest_mediated_pmu_loaded(void) * 0 - disallow raw tracepoint access for unpriv * 1 - disallow cpu events for unpriv * 2 - disallow kernel profiling for unpriv + * 4 - disallow all unpriv perf event use */ +#ifdef CONFIG_SECURITY_PERF_EVENTS_RESTRICT +int sysctl_perf_event_paranoid __read_mostly = PERF_SECURITY_MAX; +#else int sysctl_perf_event_paranoid __read_mostly = 2; +#endif /* Minimum for 512 kiB + 1 user control page. 'free' kiB per user. */ static int sysctl_perf_event_mlock __read_mostly = 512 + (PAGE_SIZE / 1024); @@ -13909,6 +13914,9 @@ SYSCALL_DEFINE5(perf_event_open, if (flags & ~PERF_FLAG_ALL) return -EINVAL; + if (perf_paranoid_any() && !perfmon_capable()) + return -EACCES; + err = perf_copy_attr(attr_uptr, &attr); if (err) return err; diff --git a/kernel/fork.c b/kernel/fork.c index f0e2e131a9a5af..f559f3a0fd8075 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -124,6 +124,11 @@ #define CREATE_TRACE_POINTS #include +#ifdef CONFIG_USER_NS +extern int unprivileged_userns_clone; +#else +#define unprivileged_userns_clone 0 +#endif #include @@ -2014,6 +2019,10 @@ __latent_entropy struct task_struct *copy_process( if ((clone_flags & (CLONE_NEWUSER|CLONE_FS)) == (CLONE_NEWUSER|CLONE_FS)) return ERR_PTR(-EINVAL); + if ((clone_flags & CLONE_NEWUSER) && !unprivileged_userns_clone) + if (!capable(CAP_SYS_ADMIN)) + return ERR_PTR(-EPERM); + /* * Thread groups must share signals as well, and detached threads * can only be started up within the thread group. @@ -3247,6 +3256,12 @@ int ksys_unshare(unsigned long unshare_flags) if (unshare_flags & CLONE_NEWNS) unshare_flags |= CLONE_FS; + if ((unshare_flags & CLONE_NEWUSER) && !unprivileged_userns_clone) { + err = -EPERM; + if (!capable(CAP_SYS_ADMIN)) + goto bad_unshare_out; + } + err = check_unshare_flags(unshare_flags); if (err) goto bad_unshare_out; diff --git a/kernel/ksysfs.c b/kernel/ksysfs.c index f45ade718054af..670a7a57d7b237 100644 --- a/kernel/ksysfs.c +++ b/kernel/ksysfs.c @@ -133,6 +133,15 @@ KERNEL_ATTR_RO(vmcoreinfo); #endif /* CONFIG_VMCORE_INFO */ +#if defined(CONFIG_PREEMPT_RT) +static ssize_t realtime_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", 1); +} +KERNEL_ATTR_RO(realtime); +#endif + /* whether file capabilities are enabled */ static ssize_t fscaps_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) @@ -206,6 +215,9 @@ static struct attribute * kernel_attrs[] = { #ifndef CONFIG_TINY_RCU &rcu_expedited_attr.attr, &rcu_normal_attr.attr, +#endif +#ifdef CONFIG_PREEMPT_RT + &realtime_attr.attr, #endif NULL }; diff --git a/kernel/kthread.c b/kernel/kthread.c index 63beb59b7a3d18..26b30de342b60a 100644 --- a/kernel/kthread.c +++ b/kernel/kthread.c @@ -505,6 +505,17 @@ struct task_struct *__kthread_create_on_node(int (*threadfn)(void *data), * new kernel thread. */ if (unlikely(wait_for_completion_killable(&done))) { + int i = 0; + + /* + * I got SIGKILL, but wait for 10 more seconds for completion + * unless chosen by the OOM killer. This delay is there as a + * workaround for boot failure caused by SIGKILL upon device + * driver initialization timeout. + */ + while (i++ < 10 && !test_tsk_thread_flag(current, TIF_MEMDIE)) + if (wait_for_completion_timeout(&done, HZ)) + goto ready; /* * If I was killed by a fatal signal before kthreadd (or new * kernel thread) calls complete(), leave the cleanup of this @@ -518,6 +529,7 @@ struct task_struct *__kthread_create_on_node(int (*threadfn)(void *data), */ wait_for_completion(&done); } +ready: task = create->result; free_create: kfree(create); diff --git a/kernel/module/signing.c b/kernel/module/signing.c index 590ba29c85aba3..02153d857531d3 100644 --- a/kernel/module/signing.c +++ b/kernel/module/signing.c @@ -61,10 +61,17 @@ int mod_verify_sig(const void *mod, struct load_info *info) modlen -= sig_len + sizeof(ms); info->len = modlen; - return verify_pkcs7_signature(mod, modlen, mod + modlen, sig_len, + ret = verify_pkcs7_signature(mod, modlen, mod + modlen, sig_len, VERIFY_USE_SECONDARY_KEYRING, VERIFYING_MODULE_SIGNATURE, NULL, NULL); + if (ret == -ENOKEY && IS_ENABLED(CONFIG_INTEGRITY_PLATFORM_KEYRING)) { + ret = verify_pkcs7_signature(mod, modlen, mod + modlen, sig_len, + VERIFY_USE_PLATFORM_KEYRING, + VERIFYING_MODULE_SIGNATURE, + NULL, NULL); + } + return ret; } int module_sig_check(struct load_info *info, int flags) diff --git a/kernel/sched/syscalls.c b/kernel/sched/syscalls.c index b215b0ead9a60b..a9fc5414292c77 100644 --- a/kernel/sched/syscalls.c +++ b/kernel/sched/syscalls.c @@ -119,6 +119,7 @@ int can_nice(const struct task_struct *p, const int nice) { return is_nice_reduction(p, nice) || capable(CAP_SYS_NICE); } +EXPORT_SYMBOL(can_nice); #ifdef __ARCH_WANT_SYS_NICE diff --git a/kernel/sched/wait.c b/kernel/sched/wait.c index 20f27e2cf7aec6..8b1338c283414e 100644 --- a/kernel/sched/wait.c +++ b/kernel/sched/wait.c @@ -231,6 +231,7 @@ void __wake_up_pollfree(struct wait_queue_head *wq_head) /* POLLFREE must have cleared the queue. */ WARN_ON_ONCE(waitqueue_active(wq_head)); } +EXPORT_SYMBOL_GPL(__wake_up_pollfree); /* * Note: we use "set_current_state()" _after_ the wait-queue add, diff --git a/kernel/sys.c b/kernel/sys.c index df69bd71de032c..be0685ecea7c3d 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -1307,6 +1307,21 @@ SYSCALL_DEFINE0(setsid) DECLARE_RWSEM(uts_sem); +#ifdef COMPAT_UTS_MACHINE +static char compat_uts_machine[__OLD_UTS_LEN+1] = COMPAT_UTS_MACHINE; + +static int __init parse_compat_uts_machine(char *arg) +{ + strscpy(compat_uts_machine, arg, __OLD_UTS_LEN); + compat_uts_machine[__OLD_UTS_LEN] = 0; + return 0; +} +early_param("compat_uts_machine", parse_compat_uts_machine); + +#undef COMPAT_UTS_MACHINE +#define COMPAT_UTS_MACHINE compat_uts_machine +#endif + #ifdef COMPAT_UTS_MACHINE #define override_architecture(name) \ (personality(current->personality) == PER_LINUX32 && \ diff --git a/kernel/sysctl.c b/kernel/sysctl.c index c9efb17cc255cf..4a73aa14c1dff8 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "../lib/kstrtox.h" @@ -1415,6 +1416,15 @@ static const struct ctl_table sysctl_subsys_table[] = { .proc_handler = proc_dointvec, }, #endif +#ifdef CONFIG_USER_NS + { + .procname = "unprivileged_userns_clone", + .data = &unprivileged_userns_clone, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, +#endif }; int __init sysctl_init_bases(void) diff --git a/kernel/task_work.c b/kernel/task_work.c index 0f7519f8e7c93f..08eb29abaea6b9 100644 --- a/kernel/task_work.c +++ b/kernel/task_work.c @@ -102,6 +102,7 @@ int task_work_add(struct task_struct *task, struct callback_head *work, return 0; } +EXPORT_SYMBOL(task_work_add); /** * task_work_cancel_match - cancel a pending work added by task_work_add() diff --git a/kernel/user_namespace.c b/kernel/user_namespace.c index 0bed462e9b2a24..bc32c237c22a5f 100644 --- a/kernel/user_namespace.c +++ b/kernel/user_namespace.c @@ -23,6 +23,12 @@ #include #include +/* + * sysctl determining whether unprivileged users may unshare a new + * userns. Allowed by default + */ +int unprivileged_userns_clone = 1; + static struct kmem_cache *user_ns_cachep __ro_after_init; static DEFINE_MUTEX(userns_state_mutex); diff --git a/mm/ksm.c b/mm/ksm.c index 7d5b76478f0b65..29eb266688471f 100644 --- a/mm/ksm.c +++ b/mm/ksm.c @@ -2817,9 +2817,14 @@ static int ksm_scan_thread(void *nothing) if (ksmd_should_run()) { sleep_ms = READ_ONCE(ksm_thread_sleep_millisecs); - wait_event_freezable_timeout(ksm_iter_wait, - sleep_ms != READ_ONCE(ksm_thread_sleep_millisecs), - msecs_to_jiffies(sleep_ms)); + if (sleep_ms >= 1000) + wait_event_freezable_timeout(ksm_iter_wait, + sleep_ms != READ_ONCE(ksm_thread_sleep_millisecs), + msecs_to_jiffies(round_jiffies_relative(sleep_ms))); + else + wait_event_freezable_timeout(ksm_iter_wait, + sleep_ms != READ_ONCE(ksm_thread_sleep_millisecs), + msecs_to_jiffies(sleep_ms)); } else { wait_event_freezable(ksm_thread_wait, ksmd_should_run() || kthread_should_stop()); diff --git a/mm/list_lru.c b/mm/list_lru.c index 36662d02ff9631..b7ea86ae6d669a 100644 --- a/mm/list_lru.c +++ b/mm/list_lru.c @@ -273,6 +273,7 @@ bool list_lru_del(struct list_lru *lru, struct list_head *item, int nid, list_lru_unlock(l); return ret; } +EXPORT_SYMBOL_GPL(list_lru_del); bool list_lru_del_obj(struct list_lru *lru, struct list_head *item) { diff --git a/mm/memory.c b/mm/memory.c index 6b8280cfc1dbea..1e8945674bd682 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -2247,6 +2247,7 @@ void zap_vma_range(struct vm_area_struct *vma, unsigned long address, zap_vma_range_batched(&tlb, vma, address, size, NULL); tlb_finish_mmu(&tlb); } +EXPORT_SYMBOL(zap_vma_range); /** * zap_special_vma_range - zap all page table entries in a special vma range diff --git a/mm/mmap_lock.c b/mm/mmap_lock.c index 898c2ef1e95803..4f5e3badb8ea7a 100644 --- a/mm/mmap_lock.c +++ b/mm/mmap_lock.c @@ -340,6 +340,7 @@ struct vm_area_struct *lock_vma_under_rcu(struct mm_struct *mm, count_vm_vma_lock_event(VMA_LOCK_ABORT); return NULL; } +EXPORT_SYMBOL_GPL(lock_vma_under_rcu); static struct vm_area_struct *lock_next_vma_under_mmap_lock(struct mm_struct *mm, struct vma_iterator *vmi, diff --git a/mm/vmalloc.c b/mm/vmalloc.c index f4fa227a8d7f04..b15459500d7be3 100644 --- a/mm/vmalloc.c +++ b/mm/vmalloc.c @@ -3292,6 +3292,7 @@ struct vm_struct *get_vm_area(unsigned long size, unsigned long flags) NUMA_NO_NODE, GFP_KERNEL, __builtin_return_address(0)); } +EXPORT_SYMBOL(get_vm_area); struct vm_struct *get_vm_area_caller(unsigned long size, unsigned long flags, const void *caller) diff --git a/net/ipv4/ip_tunnel.c b/net/ipv4/ip_tunnel.c index 9d114bd575f928..68697cb95a462b 100644 --- a/net/ipv4/ip_tunnel.c +++ b/net/ipv4/ip_tunnel.c @@ -1255,7 +1255,7 @@ int ip_tunnel_changelink(struct net_device *dev, struct nlattr *tb[], struct ip_tunnel_net *itn = net_generic(net, tunnel->ip_tnl_net_id); if (dev == itn->fb_tunnel_dev) - return -EINVAL; + return fan_has_map(&tunnel->fan) ? 0 : -EINVAL; t = ip_tunnel_find(itn, p, dev->type); diff --git a/net/ipv4/ipip.c b/net/ipv4/ipip.c index b643194f57d29f..1ee520ec35dec2 100644 --- a/net/ipv4/ipip.c +++ b/net/ipv4/ipip.c @@ -101,6 +101,8 @@ #include #include #include +#include +#include #include #include @@ -275,6 +277,147 @@ static int mplsip_rcv(struct sk_buff *skb) } #endif +static struct ip_fan_map *ipip_fan_find_map(struct ip_tunnel *t, __be32 daddr) +{ + struct ip_fan_map *fan_map; + + rcu_read_lock(); + list_for_each_entry_rcu(fan_map, &t->fan.fan_maps, list) { + if (fan_map->overlay == + (daddr & inet_make_mask(fan_map->overlay_prefix))) { + rcu_read_unlock(); + return fan_map; + } + } + rcu_read_unlock(); + + return NULL; +} + +/* Determine fan tunnel endpoint to send packet to, based on the inner IP + * address. + * + * Given a /8 overlay and /16 underlay, for an overlay (inner) address + * Y.A.B.C, the transformation is F.G.A.B, where "F" and "G" are the first + * two octets of the underlay network (the network portion of a /16), "A" + * and "B" are the low order two octets of the underlay network host (the + * host portion of a /16), and "Y" is a configured first octet of the + * overlay network. + * + * E.g., underlay host 10.88.3.4/16 with an overlay of 99.0.0.0/8 would + * host overlay subnet 99.3.4.0/24. An overlay network datagram from + * 99.3.4.5 to 99.6.7.8, would be directed to underlay host 10.88.6.7, + * which hosts overlay network subnet 99.6.7.0/24. This transformation is + * described in detail further below. + * + * Using netmasks for the overlay and underlay other than /8 and /16, as + * shown above, can yield larger (or smaller) overlay subnets, with the + * trade-off of allowing fewer (or more) underlay hosts to participate. + * + * The size of each overlay network subnet is defined by the total of the + * network mask of the overlay plus the size of host portion of the + * underlay network. In the above example, /8 + /16 = /24. + * + * E.g., consider underlay host 10.99.238.5/20 and overlay 99.0.0.0/8. In + * this case, the network portion of the underlay is 10.99.224.0/20, and + * the host portion is 0.0.14.5 (12 bits). To determine the overlay + * network subnet, the 12 bits of host portion are left shifted 12 bits + * (/20 - /8) and ORed with the overlay subnet prefix. This yields an + * overlay subnet of 99.224.80/20, composed of 8 bits overlay, followed by + * 12 bits underlay. This yields 12 bits in the overlay network portion, + * allowing for 4094 addresses in each overlay network subnet. The + * trade-off is that fewer hosts may participate in the underlay network, + * as its host address size has shrunk from 16 bits (65534 addresses) in + * the first example to 12 bits (4094 addresses) here. + * + * For fewer hosts per overlay subnet (permitting a larger number of + * underlay hosts to participate), the underlay netmask may be made + * smaller. + * + * E.g., underlay host 10.111.1.2/12 (network 10.96.0.0/12, host portion + * is 0.15.1.2, 20 bits) with an overlay of 33.0.0.0/8 would left shift + * the 20 bits of host by 4 (so that it's highest order bit is adjacent to + * the lowest order bit of the /8 overlay). This yields an overlay subnet + * of 33.240.16.32/28 (8 bits overlay, 20 bits from the host portion of + * the underlay). This provides more addresses for the underlay network + * (approximately 2^20), but each host's segment of the overlay provides + * only 4 bits of addresses (14 usable). + * + * It is also possible to adjust the overlay subnet. + * + * For an overlay of 240.0.0.0/5 and underlay of 10.88.0.0/20, consider + * underlay host 10.88.129.2; the 12 bits of host, 0.0.1.2, are left + * shifted 15 bits (/20 - /5), yielding an overlay network of + * 240.129.0.0/17. An underlay host of 10.88.244.215 would yield an + * overlay network of 242.107.128.0/17. + * + * For an overlay of 100.64.0.0/10 and underlay of 10.224.220.0/24, for + * underlay host 10.224.220.10, the underlay host portion (.10) is left + * shifted 14 bits, yielding an overlay network subnet of 100.66.128.0/18. + * This would permit 254 addresses on the underlay, with each overlay + * segment providing approximately 2^14 - 2 addresses (16382). + * + * For packets being encapsulated, the overlay network destination IP + * address is deconstructed into its overlay and underlay-derived + * portions. The underlay portion (determined by the overlay mask and + * overlay subnet mask) is right shifted according to the size of the + * underlay network mask. This value is then ORed with the network + * portion of the underlay network to produce the underlay network + * destination for the encapsulated datagram. + * + * For example, using the initial example of underlay 10.88.3.4/16 and + * overlay 99.0.0.0/8, with underlay host 10.88.3.4/16 providing overlay + * subnet 99.3.4.0/24 with specfic host 99.3.4.5. A datagram from + * 99.3.4.5 to 99.6.7.8 would first have the underlay host derived portion + * of the address extracted. This is a number of bits equal to underlay + * network host portion. In the destination address, the highest order of + * these bits is one bit lower than the lowest order bit from the overlay + * network mask. + * + * Using the sample value, 99.6.7.8, the overlay mask is /8, and the + * underlay mask is /16 (leaving 16 bits for the host portion). The bits + * to be shifted are the middle two octets, 0.6.7.0, as this is 99.6.7.8 + * ANDed with the mask 0x00ffff00 (which is 16 bits, the highest order of + * which is 1 bit lower than the lowest order overlay address bit). + * + * These octets, 0.6.7.0, are then right shifted 8 bits, yielding 0.0.6.7. + * This value is then ORed with the underlay network portion, + * 10.88.0.0/16, providing 10.88.6.7 as the final underlay destination for + * the encapuslated datagram. + * + * Another transform using the final example: overlay 100.64.0.0/10 and + * underlay 10.224.220.0/24. Consider overlay address 100.66.128.1 + * sending a datagram to 100.66.200.5. In this case, 8 bits (the host + * portion size of 10.224.220.0/24) beginning after the 100.64/10 overlay + * prefix are masked off, yielding 0.2.192.0. This is right shifted 14 + * (32 - 10 - (32 - 24), i.e., the number of bits between the overlay + * network portion and the underlay host portion) bits, yielding 0.0.0.11. + * This is ORed with the underlay network portion, 10.224.220.0/24, giving + * the underlay destination of 10.224.220.11 for overlay destination + * 100.66.200.5. + */ +static int ipip_build_fan_iphdr(struct ip_tunnel *tunnel, struct sk_buff *skb, struct iphdr *iph) +{ + struct ip_fan_map *f_map; + u32 daddr, underlay; + + f_map = ipip_fan_find_map(tunnel, ip_hdr(skb)->daddr); + if (!f_map) + return -ENOENT; + + daddr = ntohl(ip_hdr(skb)->daddr); + underlay = ntohl(f_map->underlay); + if (!underlay) + return -EINVAL; + + *iph = tunnel->parms.iph; + iph->daddr = htonl(underlay | + ((daddr & ~f_map->overlay_mask) >> + (32 - f_map->overlay_prefix - + (32 - f_map->underlay_prefix)))); + return 0; +} + /* * This function assumes it is being called from dev_queue_xmit() * and that skb is filled properly by that function. @@ -285,6 +428,7 @@ static netdev_tx_t ipip_tunnel_xmit(struct sk_buff *skb, struct ip_tunnel *tunnel = netdev_priv(dev); const struct iphdr *tiph = &tunnel->parms.iph; u8 ipproto; + struct iphdr fiph; if (!pskb_inet_may_pull(skb)) goto tx_error; @@ -308,6 +452,14 @@ static netdev_tx_t ipip_tunnel_xmit(struct sk_buff *skb, if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP4)) goto tx_error; + if (fan_has_map(&tunnel->fan)) { + if (ipip_build_fan_iphdr(tunnel, skb, &fiph)) + goto tx_error; + tiph = &fiph; + } else { + tiph = &tunnel->parms.iph; + } + skb_set_inner_ipproto(skb, ipproto); if (tunnel->collect_md) @@ -397,6 +549,8 @@ static const struct net_device_ops ipip_netdev_ops = { static void ipip_tunnel_setup(struct net_device *dev) { + struct ip_tunnel *t = netdev_priv(dev); + dev->netdev_ops = &ipip_netdev_ops; dev->header_ops = &ip_tunnel_header_ops; @@ -409,6 +563,7 @@ static void ipip_tunnel_setup(struct net_device *dev) dev->features |= IPIP_FEATURES; dev->hw_features |= IPIP_FEATURES; ip_tunnel_setup(dev, ipip_net_id); + INIT_LIST_HEAD(&t->fan.fan_maps); } static int ipip_tunnel_init(struct net_device *dev) @@ -461,6 +616,92 @@ static void ipip_netlink_parms(struct nlattr *data[], *fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]); } +static void ipip_fan_flush_map(struct ip_tunnel *t) +{ + struct ip_fan_map *fan_map; + + list_for_each_entry_rcu(fan_map, &t->fan.fan_maps, list) { + list_del_rcu(&fan_map->list); + kfree_rcu(fan_map, rcu); + } +} + +static int ipip_fan_del_map(struct ip_tunnel *t, __be32 overlay) +{ + struct ip_fan_map *fan_map; + + fan_map = ipip_fan_find_map(t, overlay); + if (!fan_map) + return -ENOENT; + + list_del_rcu(&fan_map->list); + kfree_rcu(fan_map, rcu); + + return 0; +} + +static int ipip_fan_add_map(struct ip_tunnel *t, struct ifla_fan_map *map) +{ + __be32 overlay_mask, underlay_mask; + struct ip_fan_map *fan_map; + + overlay_mask = inet_make_mask(map->overlay_prefix); + underlay_mask = inet_make_mask(map->underlay_prefix); + + if ((map->overlay & ~overlay_mask) || (map->underlay & ~underlay_mask)) + return -EINVAL; + + if (!(map->overlay & overlay_mask) && (map->underlay & underlay_mask)) + return -EINVAL; + + /* Special case: overlay 0 and underlay 0: flush all mappings */ + if (!map->overlay && !map->underlay) { + ipip_fan_flush_map(t); + return 0; + } + + /* Special case: overlay set and underlay 0: clear map for overlay */ + if (!map->underlay) + return ipip_fan_del_map(t, map->overlay); + + if (ipip_fan_find_map(t, map->overlay)) + return -EEXIST; + + fan_map = kmalloc(sizeof(*fan_map), GFP_KERNEL); + fan_map->underlay = map->underlay; + fan_map->overlay = map->overlay; + fan_map->underlay_prefix = map->underlay_prefix; + fan_map->overlay_mask = ntohl(overlay_mask); + fan_map->overlay_prefix = map->overlay_prefix; + + list_add_tail_rcu(&fan_map->list, &t->fan.fan_maps); + + return 0; +} + +static int ipip_netlink_fan(struct nlattr *data[], struct ip_tunnel *t, + struct ip_tunnel_parm_kern *parms) +{ + struct ifla_fan_map *map; + struct nlattr *attr; + int rem, rv; + + if (data == NULL || !data[IFLA_IPTUN_FAN_MAP]) + return 0; + + if (parms->iph.daddr) + return -EINVAL; + + nla_for_each_nested(attr, data[IFLA_IPTUN_FAN_MAP], rem) { + map = nla_data(attr); + rv = ipip_fan_add_map(t, map); + if (rv) + return rv; + } + + return 0; +} + static int ipip_newlink(struct net_device *dev, struct rtnl_newlink_params *params, struct netlink_ext_ack *extack) @@ -471,15 +712,19 @@ static int ipip_newlink(struct net_device *dev, struct ip_tunnel_encap ipencap; struct ip_tunnel_parm_kern p; __u32 fwmark = 0; + int err; if (ip_tunnel_netlink_encap_parms(data, &ipencap)) { - int err = ip_tunnel_encap_setup(t, &ipencap); + err = ip_tunnel_encap_setup(t, &ipencap); if (err < 0) return err; } ipip_netlink_parms(data, &p, &t->collect_md, &fwmark); + err = ipip_netlink_fan(data, t, &p); + if (err < 0) + return err; return ip_tunnel_newlink(params->link_net ? : dev_net(dev), dev, tb, &p, fwmark); } @@ -493,12 +738,13 @@ static int ipip_changelink(struct net_device *dev, struct nlattr *tb[], struct ip_tunnel_parm_kern p; bool collect_md; __u32 fwmark = t->fwmark; + int err; if (!rtnl_dev_link_net_capable(dev, t->net)) return -EPERM; if (ip_tunnel_netlink_encap_parms(data, &ipencap)) { - int err = ip_tunnel_encap_setup(t, &ipencap); + err = ip_tunnel_encap_setup(t, &ipencap); if (err < 0) return err; @@ -507,6 +753,9 @@ static int ipip_changelink(struct net_device *dev, struct nlattr *tb[], ipip_netlink_parms(data, &p, &collect_md, &fwmark); if (collect_md) return -EINVAL; + err = ipip_netlink_fan(data, t, &p); + if (err < 0) + return err; if (((dev->flags & IFF_POINTOPOINT) && !p.iph.daddr) || (!(dev->flags & IFF_POINTOPOINT) && p.iph.daddr)) @@ -544,6 +793,8 @@ static size_t ipip_get_size(const struct net_device *dev) nla_total_size(0) + /* IFLA_IPTUN_FWMARK */ nla_total_size(4) + + /* IFLA_IPTUN_FAN_MAP */ + nla_total_size(sizeof(struct ifla_fan_map)) * 256 + 0; } @@ -576,6 +827,26 @@ static int ipip_fill_info(struct sk_buff *skb, const struct net_device *dev) if (tunnel->collect_md) if (nla_put_flag(skb, IFLA_IPTUN_COLLECT_METADATA)) goto nla_put_failure; + if (fan_has_map(&tunnel->fan)) { + struct nlattr *fan_nest; + struct ip_fan_map *fan_map; + + fan_nest = nla_nest_start(skb, IFLA_IPTUN_FAN_MAP); + if (!fan_nest) + goto nla_put_failure; + list_for_each_entry_rcu(fan_map, &tunnel->fan.fan_maps, list) { + struct ifla_fan_map map; + + map.underlay = fan_map->underlay; + map.underlay_prefix = fan_map->underlay_prefix; + map.overlay = fan_map->overlay; + map.overlay_prefix = fan_map->overlay_prefix; + if (nla_put(skb, IFLA_FAN_MAPPING, sizeof(map), &map)) + goto nla_put_failure; + } + nla_nest_end(skb, fan_nest); + } + return 0; nla_put_failure: @@ -596,6 +867,9 @@ static const struct nla_policy ipip_policy[IFLA_IPTUN_MAX + 1] = { [IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 }, [IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG }, [IFLA_IPTUN_FWMARK] = { .type = NLA_U32 }, + + [__IFLA_IPTUN_VENDOR_BREAK ... IFLA_IPTUN_MAX] = { .type = NLA_BINARY }, + [IFLA_IPTUN_FAN_MAP] = { .type = NLA_NESTED }, }; static struct rtnl_link_ops ipip_link_ops __read_mostly = { @@ -645,6 +919,22 @@ static struct pernet_operations ipip_net_ops = { .size = sizeof(struct ip_tunnel_net), }; +#ifdef CONFIG_SYSCTL +static struct ctl_table_header *ipip_fan_header; +static unsigned int ipip_fan_version = 3; + +static struct ctl_table ipip_fan_sysctls[] = { + { + .procname = "version", + .data = &ipip_fan_version, + .maxlen = sizeof(ipip_fan_version), + .mode = 0444, + .proc_handler = proc_dointvec, + }, +}; + +#endif /* CONFIG_SYSCTL */ + static int __init ipip_init(void) { int err; @@ -670,9 +960,22 @@ static int __init ipip_init(void) if (err < 0) goto rtnl_link_failed; +#ifdef CONFIG_SYSCTL + ipip_fan_header = register_net_sysctl(&init_net, "net/fan", + ipip_fan_sysctls); + if (!ipip_fan_header) { + err = -ENOMEM; + goto sysctl_failed; + } +#endif /* CONFIG_SYSCTL */ + out: return err; +#ifdef CONFIG_SYSCTL +sysctl_failed: + rtnl_link_unregister(&ipip_link_ops); +#endif /* CONFIG_SYSCTL */ rtnl_link_failed: #if IS_ENABLED(CONFIG_MPLS) xfrm4_tunnel_deregister(&mplsip_handler, AF_MPLS); @@ -687,6 +990,9 @@ static int __init ipip_init(void) static void __exit ipip_fini(void) { +#ifdef CONFIG_SYSCTL + unregister_net_sysctl_table(ipip_fan_header); +#endif /* CONFIG_SYSCTL */ rtnl_link_unregister(&ipip_link_ops); if (xfrm4_tunnel_deregister(&ipip_handler, AF_INET)) pr_info("%s: can't deregister tunnel\n", __func__); diff --git a/net/ipv4/netfilter/arp_tables.c b/net/ipv4/netfilter/arp_tables.c index a87e07e80d0ded..ac63edb6db8389 100644 --- a/net/ipv4/netfilter/arp_tables.c +++ b/net/ipv4/netfilter/arp_tables.c @@ -308,6 +308,17 @@ static inline bool unconditional(const struct arpt_entry *e) memcmp(&e->arp, &uncond, sizeof(uncond)) == 0; } +static bool next_offset_ok(const struct xt_table_info *t, unsigned int newpos) +{ + if (newpos > t->size - sizeof(struct arpt_entry)) + return false; + + if (newpos % __alignof__(struct arpt_entry) != 0) + return false; + + return true; +} + /* Figures out from what hook each rule can be called: returns 0 if * there are loops. Puts hook bitmask in comefrom. */ @@ -366,6 +377,8 @@ static int mark_source_chains(const struct xt_table_info *newinfo, /* Move along one */ size = e->next_offset; + if (!next_offset_ok(newinfo, pos + size)) + return 0; e = entry0 + pos + size; if (pos + size >= newinfo->size) return 0; @@ -387,6 +400,10 @@ static int mark_source_chains(const struct xt_table_info *newinfo, if (newpos >= newinfo->size) return 0; } + + if (!next_offset_ok(newinfo, newpos)) + return 0; + e = entry0 + newpos; e->counters.pcnt = pos; pos = newpos; diff --git a/net/ipv4/netfilter/ip_tables.c b/net/ipv4/netfilter/ip_tables.c index 809441cedcedc7..308a33b3c9f8e6 100644 --- a/net/ipv4/netfilter/ip_tables.c +++ b/net/ipv4/netfilter/ip_tables.c @@ -361,6 +361,17 @@ ipt_do_table(void *priv, else return verdict; } +static bool next_offset_ok(const struct xt_table_info *t, unsigned int newpos) +{ + if (newpos > t->size - sizeof(struct ipt_entry)) + return false; + + if (newpos % __alignof__(struct ipt_entry) != 0) + return false; + + return true; +} + /* Figures out from what hook each rule can be called: returns 0 if there are loops. Puts hook bitmask in comefrom. */ static int @@ -416,6 +427,8 @@ mark_source_chains(const struct xt_table_info *newinfo, /* Move along one */ size = e->next_offset; + if (!next_offset_ok(newinfo, pos + size)) + return 0; e = entry0 + pos + size; if (pos + size >= newinfo->size) return 0; @@ -437,6 +450,10 @@ mark_source_chains(const struct xt_table_info *newinfo, if (newpos >= newinfo->size) return 0; } + + if (!next_offset_ok(newinfo, newpos)) + return 0; + e = entry0 + newpos; e->counters.pcnt = pos; pos = newpos; diff --git a/net/ipv6/netfilter/ip6_tables.c b/net/ipv6/netfilter/ip6_tables.c index f42fb96ef64b68..f6ee44e00b4222 100644 --- a/net/ipv6/netfilter/ip6_tables.c +++ b/net/ipv6/netfilter/ip6_tables.c @@ -379,6 +379,17 @@ ip6t_do_table(void *priv, struct sk_buff *skb, else return verdict; } +static bool next_offset_ok(const struct xt_table_info *t, unsigned int newpos) +{ + if (newpos > t->size - sizeof(struct ip6t_entry)) + return false; + + if (newpos % __alignof__(struct ip6t_entry) != 0) + return false; + + return true; +} + /* Figures out from what hook each rule can be called: returns 0 if there are loops. Puts hook bitmask in comefrom. */ static int @@ -434,6 +445,8 @@ mark_source_chains(const struct xt_table_info *newinfo, /* Move along one */ size = e->next_offset; + if (!next_offset_ok(newinfo, pos + size)) + return 0; e = entry0 + pos + size; if (pos + size >= newinfo->size) return 0; @@ -455,6 +468,10 @@ mark_source_chains(const struct xt_table_info *newinfo, if (newpos >= newinfo->size) return 0; } + + if (!next_offset_ok(newinfo, newpos)) + return 0; + e = entry0 + newpos; e->counters.pcnt = pos; pos = newpos; diff --git a/net/qrtr/smd.c b/net/qrtr/smd.c index c91bf030fbc7d9..bd70dcfe499ad5 100644 --- a/net/qrtr/smd.c +++ b/net/qrtr/smd.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -14,18 +15,18 @@ struct qrtr_smd_dev { struct qrtr_endpoint ep; struct rpmsg_endpoint *channel; struct device *dev; + + /* Protect against channel open/close while sending */ + struct mutex send_lock; }; /* from smd to qrtr */ static int qcom_smd_qrtr_callback(struct rpmsg_device *rpdev, void *data, int len, void *priv, u32 addr) { - struct qrtr_smd_dev *qdev = dev_get_drvdata(&rpdev->dev); + struct qrtr_smd_dev *qdev = priv; int rc; - if (!qdev) - return -EAGAIN; - rc = qrtr_endpoint_post(&qdev->ep, data, len); if (rc == -EINVAL) { dev_err(qdev->dev, "invalid ipcrouter packet\n"); @@ -46,7 +47,12 @@ static int qcom_smd_qrtr_send(struct qrtr_endpoint *ep, struct sk_buff *skb) if (rc) goto out; - rc = rpmsg_send(qdev->channel, skb->data, skb->len); + scoped_guard(mutex, &qdev->send_lock) { + if (qdev->channel) + rc = rpmsg_send(qdev->channel, skb->data, skb->len); + else + rc = -ENODEV; + } out: if (rc) @@ -65,14 +71,26 @@ static int qcom_smd_qrtr_probe(struct rpmsg_device *rpdev) if (!qdev) return -ENOMEM; - qdev->channel = rpdev->ept; qdev->dev = &rpdev->dev; qdev->ep.xmit = qcom_smd_qrtr_send; + rc = devm_mutex_init(&rpdev->dev, &qdev->send_lock); + if (rc) + return rc; + + /* Block sending until we have fully opened the channel */ + guard(mutex)(&qdev->send_lock); + rc = qrtr_endpoint_register(&qdev->ep, QRTR_EP_NID_AUTO); if (rc) return rc; + qdev->channel = rpmsg_dev_open_ept(rpdev, qcom_smd_qrtr_callback, qdev); + if (!qdev->channel) { + qrtr_endpoint_unregister(&qdev->ep); + return -EREMOTEIO; + } + dev_set_drvdata(&rpdev->dev, qdev); dev_dbg(&rpdev->dev, "Qualcomm SMD QRTR driver probed\n"); @@ -83,10 +101,16 @@ static int qcom_smd_qrtr_probe(struct rpmsg_device *rpdev) static void qcom_smd_qrtr_remove(struct rpmsg_device *rpdev) { struct qrtr_smd_dev *qdev = dev_get_drvdata(&rpdev->dev); + struct rpmsg_endpoint *ept; - qrtr_endpoint_unregister(&qdev->ep); + /* We are about to close the channel, so stop all sending now */ + scoped_guard(mutex, &qdev->send_lock) { + ept = qdev->channel; + qdev->channel = NULL; + } - dev_set_drvdata(&rpdev->dev, NULL); + rpmsg_destroy_ept(ept); + qrtr_endpoint_unregister(&qdev->ep); } static const struct rpmsg_device_id qcom_smd_qrtr_smd_match[] = { @@ -97,7 +121,6 @@ static const struct rpmsg_device_id qcom_smd_qrtr_smd_match[] = { static struct rpmsg_driver qcom_smd_qrtr_driver = { .probe = qcom_smd_qrtr_probe, .remove = qcom_smd_qrtr_remove, - .callback = qcom_smd_qrtr_callback, .id_table = qcom_smd_qrtr_smd_match, .drv = { .name = "qcom_smd_qrtr", diff --git a/net/rds/ib_send.c b/net/rds/ib_send.c index d6be95542119f6..e7b0e86cc990a6 100644 --- a/net/rds/ib_send.c +++ b/net/rds/ib_send.c @@ -505,7 +505,7 @@ int rds_ib_xmit(struct rds_connection *conn, struct rds_message *rm, int flow_controlled = 0; int nr_sig = 0; - BUG_ON(off % RDS_FRAG_SIZE); + BUG_ON(!conn->c_loopback && off % RDS_FRAG_SIZE); BUG_ON(hdr_off != 0 && hdr_off != sizeof(struct rds_header)); /* Do not send cong updates to IB loopback */ diff --git a/net/rfkill/core.c b/net/rfkill/core.c index 9e143c4bfe6a6b..9a0ebb48e71b4f 100644 --- a/net/rfkill/core.c +++ b/net/rfkill/core.c @@ -82,7 +82,6 @@ struct rfkill_data { wait_queue_head_t read_wait; u32 event_count; bool input_handler; - u8 max_size; }; @@ -1185,8 +1184,6 @@ static int rfkill_fop_open(struct inode *inode, struct file *file) if (!data) return -ENOMEM; - data->max_size = RFKILL_EVENT_SIZE_V1; - INIT_LIST_HEAD(&data->events); mutex_init(&data->mtx); init_waitqueue_head(&data->read_wait); @@ -1267,7 +1264,6 @@ static ssize_t rfkill_fop_read(struct file *file, char __user *buf, list); sz = min_t(unsigned long, sizeof(ev->ev), count); - sz = min_t(unsigned long, sz, data->max_size); ret = sz; if (copy_to_user(buf, &ev->ev, sz)) ret = -EFAULT; @@ -1283,7 +1279,6 @@ static ssize_t rfkill_fop_read(struct file *file, char __user *buf, static ssize_t rfkill_fop_write(struct file *file, const char __user *buf, size_t count, loff_t *pos) { - struct rfkill_data *data = file->private_data; struct rfkill *rfkill; struct rfkill_event_ext ev; int ret; @@ -1298,7 +1293,6 @@ static ssize_t rfkill_fop_write(struct file *file, const char __user *buf, * our API version even in a write() call, if it cares. */ count = min(count, sizeof(ev)); - count = min_t(size_t, count, data->max_size); if (copy_from_user(&ev, buf, count)) return -EFAULT; @@ -1358,47 +1352,31 @@ static int rfkill_fop_release(struct inode *inode, struct file *file) return 0; } +#ifdef CONFIG_RFKILL_INPUT static long rfkill_fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct rfkill_data *data = file->private_data; - int ret = -ENOTTY; - u32 size; if (_IOC_TYPE(cmd) != RFKILL_IOC_MAGIC) return -ENOTTY; + if (_IOC_NR(cmd) != RFKILL_IOC_NOINPUT) + return -ENOSYS; + mutex_lock(&data->mtx); - switch (_IOC_NR(cmd)) { -#ifdef CONFIG_RFKILL_INPUT - case RFKILL_IOC_NOINPUT: - if (!data->input_handler) { - if (atomic_inc_return(&rfkill_input_disabled) == 1) - printk(KERN_DEBUG "rfkill: input handler disabled\n"); - data->input_handler = true; - } - ret = 0; - break; -#endif - case RFKILL_IOC_MAX_SIZE: - if (get_user(size, (__u32 __user *)arg)) { - ret = -EFAULT; - break; - } - if (size < RFKILL_EVENT_SIZE_V1 || size > U8_MAX) { - ret = -EINVAL; - break; - } - data->max_size = size; - ret = 0; - break; - default: - break; + + if (!data->input_handler) { + if (atomic_inc_return(&rfkill_input_disabled) == 1) + printk(KERN_DEBUG "rfkill: input handler disabled\n"); + data->input_handler = true; } + mutex_unlock(&data->mtx); - return ret; + return 0; } +#endif static const struct file_operations rfkill_fops = { .owner = THIS_MODULE, @@ -1407,8 +1385,10 @@ static const struct file_operations rfkill_fops = { .write = rfkill_fop_write, .poll = rfkill_fop_poll, .release = rfkill_fop_release, +#ifdef CONFIG_RFKILL_INPUT .unlocked_ioctl = rfkill_fop_ioctl, .compat_ioctl = compat_ptr_ioctl, +#endif }; #define RFKILL_NAME "rfkill" diff --git a/rebuild.sh b/rebuild.sh new file mode 100755 index 00000000000000..48eeda0a85de1f --- /dev/null +++ b/rebuild.sh @@ -0,0 +1,25 @@ +#!/usr/bin/env bash + +set -ex + +if ! diff -u debian/changelog debian.qcom-x1e/changelog +then + fakeroot debian/rules clean +fi + +dh_clean + +rm -rf debian/build/build-qcom-x1e/_____________________________________dkms/ + +# export LLVM=1 + +# Detect if we're on ARM64/AArch64 +if uname -m | grep -q 'aarch64\|arm64'; then + echo "Native ARM64 compilation detected" + time dpkg-buildpackage -d -b -k'jens.glathe@oldschoolsolutions.biz' +else + echo "Cross-compiling to ARM64" + time dpkg-buildpackage -d -b -aarm64 -k'jens.glathe@oldschoolsolutions.biz' +fi + +#time debuild --no-lintian -k'jens.glathe@oldschoolsolutions.biz' diff --git a/rebuild_t14s.sh b/rebuild_t14s.sh new file mode 100755 index 00000000000000..70a347f03cf969 --- /dev/null +++ b/rebuild_t14s.sh @@ -0,0 +1,28 @@ +#!/usr/bin/env bash + +set -ex + +export MAKEFLAGS="-j8 -l 6.5" +export DEB_BUILD_OPTIONS="parallel=8" + +if ! diff -u debian/changelog debian.qcom-x1e/changelog +then + fakeroot debian/rules clean +fi + +dh_clean + +rm -rf debian/build/build-qcom-x1e/_____________________________________dkms/ + +#export LLVM=1 + +# Detect if we're on ARM64/AArch64 +if uname -m | grep -q 'aarch64\|arm64'; then + echo "Native ARM64 compilation detected" + time dpkg-buildpackage -d -b -k'jens.glathe@oldschoolsolutions.biz' +else + echo "Cross-compiling to ARM64" + time dpkg-buildpackage -d -b -aarm64 -k'jens.glathe@oldschoolsolutions.biz' +fi + +#time debuild --no-lintian -k'jens.glathe@oldschoolsolutions.biz' diff --git a/rust/Makefile b/rust/Makefile index 627ed79dc6f504..80aefe3603be12 100644 --- a/rust/Makefile +++ b/rust/Makefile @@ -59,9 +59,9 @@ libpin_init_internal_name := $(call procmacro-name,pin_init_internal) always-$(CONFIG_RUST) += $(libzerocopy_derive_name) $(libmacros_name) $(libpin_init_internal_name) # `$(rust_flags)` is passed in case the user added `--sysroot`. -rustc_sysroot := $(shell MAKEFLAGS= $(RUSTC) $(rust_flags) --print sysroot) +rustc_sysroot := $(shell MAKEFLAGS= $(RUSTC) $(rust_flags) --version | awk '{print "/usr/src/" $$1 "-" $$2}') rustc_host_target := $(shell $(RUSTC) --version --verbose | grep -F 'host: ' | cut -d' ' -f2) -RUST_LIB_SRC ?= $(rustc_sysroot)/lib/rustlib/src/rust/library +RUST_LIB_SRC ?= $(rustc_sysroot)/library ifneq ($(quiet),) rust_test_quiet=-q diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst index 9d920419a62cf4..3de271b5dd6507 100644 --- a/scripts/Makefile.dtbinst +++ b/scripts/Makefile.dtbinst @@ -40,4 +40,6 @@ endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL __dtbs_install: $(addprefix $(dst)/, $(dtbs)) @: +.NOTPARALLEL: __dtbs_install + .PHONY: $(PHONY) diff --git a/scripts/Makefile.modinst b/scripts/Makefile.modinst index 9ba45e5b32b183..19eccef32daa0d 100644 --- a/scripts/Makefile.modinst +++ b/scripts/Makefile.modinst @@ -105,8 +105,11 @@ else sig-key := $(CONFIG_MODULE_SIG_KEY) endif quiet_cmd_sign = SIGN $@ - cmd_sign = $(objtree)/scripts/sign-file $(CONFIG_MODULE_SIG_HASH) "$(sig-key)" $(objtree)/certs/signing_key.x509 $@ \ - $(if $(KBUILD_EXTMOD),|| true) + cmd_sign = if test -e $(srctree)/debian/scripts/sign-module && \ + $(srctree)/debian/scripts/sign-module $@ ; \ + then $(objtree)/scripts/sign-file $(CONFIG_MODULE_SIG_HASH) "$(sig-key)" $(objtree)/certs/signing_key.x509 $@ \ + $(if $(KBUILD_EXTMOD),|| true) ; \ + fi ifeq ($(sign-only),) diff --git a/scripts/insert-sys-cert.c b/scripts/insert-sys-cert.c index 8902836c234244..6c6120dad676aa 100644 --- a/scripts/insert-sys-cert.c +++ b/scripts/insert-sys-cert.c @@ -7,7 +7,8 @@ * This software may be used and distributed according to the terms * of the GNU General Public License, incorporated herein by reference. * - * Usage: insert-sys-cert [-s -b -c + * Usage: insert-sys-cert [-s ] -b -c + * [-s ] -z -c */ #define _GNU_SOURCE @@ -257,6 +258,169 @@ static char *read_file(char *file_name, int *size) return buf; } +static void get_payload_info(char *bzimage, int *offset, int *size) +{ + unsigned int system_offset; + unsigned char setup_sectors; + + setup_sectors = bzimage[0x1f1] + 1; + system_offset = setup_sectors * 512; + *offset = system_offset + *((int*)&bzimage[0x248]); + *size = *((int*)&bzimage[0x24c]); +} + +static void update_payload_info(char* bzimage, int new_size) +{ + int offset, size; + get_payload_info(bzimage, &offset, &size); + *((int*)&bzimage[0x24c]) = new_size; + if (new_size < size) + memset(bzimage + offset + new_size, 0, size - new_size); +} + +struct zipper { + unsigned char pattern[10]; + int length; + char *command; + char *compress; +}; + +struct zipper zippers[] = { + {{0x7F,'E','L','F'}, 4, "cat", "cat"}, + {{0x1F,0x8B}, 2, "gunzip", "gzip -n -f -9"}, + {{0xFD,'7','z','X','Z',0}, 6, "unxz", "xz"}, + {{'B','Z','h'},3, "bunzip2", "bzip2 -9"}, + {{0xFF,'L','Z','M','A',0}, 6, "unlzma", "lzma -9"}, + {{0xD3,'L','Z','O',0,'\r','\n',0x20,'\n'}, 9, "lzop -d", "lzop -9"} +}; + +static struct zipper* get_zipper(char *p) { + int i; + for (i = 0; i < sizeof(zippers)/sizeof(struct zipper); i++) { + if (memcmp(p, zippers[i].pattern, zippers[i].length) == 0) + return &zippers[i]; + } + return NULL; +} + +/* + * This only works for x86 bzImage + */ +static void extract_vmlinux(char *bzimage, int bzimage_size, + char **file, struct zipper **zipper) +{ + int r; + char src[15] = "vmlinux-XXXXXX"; + char dest[15] = "vmlinux-XXXXXX"; + char cmd[100]; + int src_fd, dest_fd; + int offset, size; + struct zipper *z; + + /* TODO: verify that bzImage is supported */ + + get_payload_info(bzimage, &offset, &size); + z = get_zipper(bzimage + offset); + if (z == NULL) { + err("Unable to determine the compression of vmlinux\n"); + return; + } + + src_fd = mkstemp(src); + if (src_fd == -1) { + perror("Could not create temp file"); + return; + } + + r = write(src_fd, bzimage + offset, size); + if (r != size) { + perror("Could not write vmlinux"); + return; + } + dest_fd = mkstemp(dest); + if (dest_fd == -1) { + perror("Could not create temp file"); + return; + } + + snprintf(cmd, sizeof(cmd), "%s <%s >%s", z->command, src, dest); + info("Executing: %s\n", cmd); + r = system(cmd); + if (r!=0) + warn("Possible errors when extracting\n"); + + r = remove(src); + if (r!=0) + perror(src); + + *file = strdup(dest); + *zipper = z; +} + +static void repack_image(char *bzimage, int bzimage_size, + char* vmlinux_file, struct zipper *z) +{ + char tmp[15] = "vmlinux-XXXXXX"; + char cmd[100]; + int fd; + struct stat st; + int new_size; + int r; + int offset, size; + + get_payload_info(bzimage, &offset, &size); + + fd = mkstemp(tmp); + if (fd == -1) { + perror("Could not create temp file"); + return; + } + snprintf(cmd, sizeof(cmd), "%s <%s >%s", + z->compress, vmlinux_file, tmp); + + info("Executing: %s\n", cmd); + r = system(cmd); + if (r!=0) + warn("Possible errors when compressing\n"); + + r = remove(vmlinux_file); + if (r!=0) + perror(vmlinux_file); + + if (fstat(fd, &st)) { + perror("Could not determine file size"); + close(fd); + + } + new_size = st.st_size; + if (new_size > size) { + err("Increase in compressed size is not supported.\n"); + err("Old size was %d, new size is %d\n", size, new_size); + exit(EXIT_FAILURE); + } + + r = read(fd, bzimage + offset, new_size); + if (r != new_size) + perror(tmp); + + r = remove(tmp); + if (r!=0) + perror(tmp); + + /* x86 specific patching of bzimage */ + update_payload_info(bzimage, new_size); + + /* TODO: update CRC */ + +} + +static void fill_random(unsigned char *p, int n) { + srand(0); + int i; + for (i = 0; i < n; i++) + p[i] = rand(); +} + static void print_sym(Elf_Ehdr *hdr, struct sym *s) { info("sym: %s\n", s->name); @@ -267,18 +431,23 @@ static void print_sym(Elf_Ehdr *hdr, struct sym *s) static void print_usage(char *e) { - printf("Usage %s [-s ] -b -c \n", e); + printf("Usage: %s [-s ] -b -c \n", e); + printf(" %s [-s ] -z -c \n", e); } int main(int argc, char **argv) { char *system_map_file = NULL; char *vmlinux_file = NULL; + char *bzimage_file = NULL; char *cert_file = NULL; int vmlinux_size; + int bzimage_size; int cert_size; Elf_Ehdr *hdr; char *cert; + char *bzimage = NULL; + struct zipper *z = NULL; FILE *system_map; unsigned long *lsize; int *used; @@ -286,7 +455,7 @@ int main(int argc, char **argv) Elf_Shdr *symtab = NULL; struct sym cert_sym, lsize_sym, used_sym; - while ((opt = getopt(argc, argv, "b:c:s:")) != -1) { + while ((opt = getopt(argc, argv, "b:z:c:s:")) != -1) { switch (opt) { case 's': system_map_file = optarg; @@ -294,6 +463,9 @@ int main(int argc, char **argv) case 'b': vmlinux_file = optarg; break; + case 'z': + bzimage_file = optarg; + break; case 'c': cert_file = optarg; break; @@ -302,7 +474,9 @@ int main(int argc, char **argv) } } - if (!vmlinux_file || !cert_file) { + if (!cert_file || + (!vmlinux_file && !bzimage_file) || + (vmlinux_file && bzimage_file)) { print_usage(argv[0]); exit(EXIT_FAILURE); } @@ -311,6 +485,16 @@ int main(int argc, char **argv) if (!cert) exit(EXIT_FAILURE); + if (bzimage_file) { + bzimage = map_file(bzimage_file, &bzimage_size); + if (!bzimage) + exit(EXIT_FAILURE); + + extract_vmlinux(bzimage, bzimage_size, &vmlinux_file, &z); + if (!vmlinux_file) + exit(EXIT_FAILURE); + } + hdr = map_file(vmlinux_file, &vmlinux_size); if (!hdr) exit(EXIT_FAILURE); @@ -386,7 +570,7 @@ int main(int argc, char **argv) } /* If the existing cert is the same, don't overwrite */ - if (cert_size == *used && + if (cert_size > 0 && cert_size == *used && strncmp(cert_sym.content, cert, cert_size) == 0) { warn("Certificate was already inserted.\n"); exit(EXIT_SUCCESS); @@ -396,9 +580,11 @@ int main(int argc, char **argv) warn("Replacing previously inserted certificate.\n"); memcpy(cert_sym.content, cert, cert_size); + if (cert_size < cert_sym.size) - memset(cert_sym.content + cert_size, - 0, cert_sym.size - cert_size); + /* This makes the reserved space incompressable */ + fill_random(cert_sym.content + cert_size, + cert_sym.size - cert_size); *lsize = *lsize + cert_size - *used; *used = cert_size; @@ -406,5 +592,15 @@ int main(int argc, char **argv) cert_sym.address); info("Used %d bytes out of %d bytes reserved.\n", *used, cert_sym.size); + + if (munmap(hdr, vmlinux_size) == -1) { + perror(vmlinux_file); + exit(EXIT_FAILURE); + } + + if (bzimage) { + repack_image(bzimage, bzimage_size, vmlinux_file, z); + } + exit(EXIT_SUCCESS); } diff --git a/scripts/kconfig/lkc.h b/scripts/kconfig/lkc.h index 7e6f6ca299cf1a..68ab0fd38c45a2 100644 --- a/scripts/kconfig/lkc.h +++ b/scripts/kconfig/lkc.h @@ -44,7 +44,9 @@ const char *conf_get_configname(void); /* confdata.c and expr.c */ static inline void xfwrite(const void *str, size_t len, size_t count, FILE *out) { - assert(len != 0); + //assert(len != 0); + if (len == 0) + return; if (fwrite(str, len, count, out) != count) fprintf(stderr, "Error in writing or end of file.\n"); diff --git a/scripts/rust_is_available.sh b/scripts/rust_is_available.sh index 551f1ebd0dcb7d..a063a929be6173 100755 --- a/scripts/rust_is_available.sh +++ b/scripts/rust_is_available.sh @@ -233,8 +233,8 @@ fi # Check that the source code for the `core` standard library exists. # # `$KRUSTFLAGS` is passed in case the user added `--sysroot`. -rustc_sysroot=$("$RUSTC" $KRUSTFLAGS --print sysroot) -rustc_src=${RUST_LIB_SRC:-"$rustc_sysroot/lib/rustlib/src/rust/library"} +rustc_sysroot=$("$RUSTC" $KRUSTFLAGS --version | awk '{print "/usr/src/" $1 "-" $2}') +rustc_src=${RUST_LIB_SRC:-"$rustc_sysroot/library"} rustc_src_core="$rustc_src/core/src/lib.rs" if [ ! -e "$rustc_src_core" ]; then echo >&2 "***" diff --git a/security/Kconfig b/security/Kconfig index f7bf6cdc6229eb..229c38cb74387e 100644 --- a/security/Kconfig +++ b/security/Kconfig @@ -70,6 +70,15 @@ config MSEAL_SYSTEM_MAPPINGS For complete descriptions of memory sealing, please see Documentation/userspace-api/mseal.rst +config SECURITY_PERF_EVENTS_RESTRICT + bool "Restrict unprivileged use of performance events" + depends on PERF_EVENTS + help + If you say Y here, the kernel.perf_event_paranoid sysctl + will be set to 3 by default, and no unprivileged use of the + perf_event_open syscall will be permitted unless it is + changed. + config SECURITY bool "Enable different security models" depends on SYSFS diff --git a/security/apparmor/Kconfig b/security/apparmor/Kconfig index 1e3bd44643dacc..87e46f293ac467 100644 --- a/security/apparmor/Kconfig +++ b/security/apparmor/Kconfig @@ -104,6 +104,18 @@ config SECURITY_APPARMOR_PARANOID_LOAD includes policy, and has some form of integrity check. Disabling the check will speed up policy loads. +config SECURITY_APPARMOR_RESTRICT_USERNS + bool "Restrict user namespace creation to confined domains" + depends on SECURITY_APPARMOR && USER_NS + default y + help + This options allows controlling whether apparmor restricts + the creation of new user namespaces to confined tasks by + default. If set unconfined tasks without CAP_SYS_ADMIN + will not be allowed to create new user namespaces. Confined + tasks ability to create new user namespaces will be controlled + by their profile. + config SECURITY_APPARMOR_KUNIT_TEST tristate "Build KUnit tests for policy_unpack.c" if !KUNIT_ALL_TESTS depends on KUNIT && SECURITY_APPARMOR diff --git a/security/apparmor/Makefile b/security/apparmor/Makefile index 12fb419714c01d..90d62db907c8c1 100644 --- a/security/apparmor/Makefile +++ b/security/apparmor/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_SECURITY_APPARMOR) += apparmor.o apparmor-y := apparmorfs.o audit.o capability.o task.o ipc.o lib.o match.o \ path.o domain.o policy.o policy_unpack.o procattr.o lsm.o \ resource.o secid.o file.o policy_ns.o label.o mount.o net.o \ - policy_compat.o af_unix.o + policy_compat.o af_unix.o af_inet.o notify.o apparmor-$(CONFIG_SECURITY_APPARMOR_HASH) += crypto.o obj-$(CONFIG_SECURITY_APPARMOR_KUNIT_TEST) += apparmor_policy_unpack_test.o diff --git a/security/apparmor/af_inet.c b/security/apparmor/af_inet.c new file mode 100644 index 00000000000000..31c975f8bcc623 --- /dev/null +++ b/security/apparmor/af_inet.c @@ -0,0 +1,828 @@ +/* + * AppArmor security module + * + * This file contains AppArmor inet fine grained mediation + * + * Copyright 2024 Canonical Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + */ + +#include + +#include "include/audit.h" +#include "include/af_inet.h" +#include "include/apparmor.h" +#include "include/file.h" +#include "include/label.h" +#include "include/path.h" +#include "include/policy.h" +#include "include/cred.h" + + + +static inline aa_state_t RULE_MEDIATES_SK(struct aa_ruleset *rules, + struct sock *sk) +{ + return RULE_MEDIATES_NET(rules); +} + + +enum addr_type { + ADDR_LOCAL = 0, + ADDR_LOCAL_PRIV = 1, + ADDR_REMOTE = 2, +}; + +struct match_addr { + const char *addrp; + enum addr_type addrtype; + int len; + __be16 port; +}; + +struct stored_match_addr { + union { + struct sockaddr addr; + struct sockaddr_in addr4; + struct sockaddr_in6 addr6; + }; + int addrlen; + struct match_addr maddr; +}; + +static void set_ad_create(struct apparmor_audit_data *ad, + int family, int type, int protocol) +{ + ad->common.u.net->family = family; + ad->net.type = type; + ad->net.protocol = protocol; +} + +static int set_ad_addr(struct apparmor_audit_data *ad, + u16 family, bool source, struct match_addr *maddr) +{ + ad->common.u.net->family = family; + + if (source) { + ad->common.u.net->sport = maddr->port; + if (maddr->addrp) { + if (family == AF_INET) + //ad.u.net->v4info.saddr = addr4->sin_addr.s_addr; + ad->common.u.net->v4info.saddr = *(__be32 *)maddr->addrp; + else + //ad.u.net->v4info.saddr = addr6->sin6_addr.s6_addr; + ad->common.u.net->v6info.saddr = *(struct in6_addr *)maddr->addrp; + } + } else { + ad->common.u.net->dport = maddr->port; + if (maddr->addrp) { + if (family == AF_INET) + //ad.u.net->v4info.saddr = addr4->sin_addr.s_addr; + ad->common.u.net->v4info.daddr = *(__be32 *)maddr->addrp; + else + //ad.u.net->v4info.saddr = addr6->sin6_addr.s6_addr; + ad->common.u.net->v6info.daddr = *(struct in6_addr *)maddr->addrp; + } + } + return 0; +} + +/* returns 0 on success +* raw_port - if set raw_port (protocol) when SOCK_RAW */ +static int map_addr(struct sockaddr *addr, int addrlen, u16 raw_port, + enum addr_type addrtype, struct match_addr *maddr, + struct apparmor_audit_data *ad) +{ + struct sockaddr_in *addr4 = NULL; + struct sockaddr_in6 *addr6 = NULL; + + AA_BUG(!maddr); + + maddr->addrtype = addrtype; + if (!addr || addrlen < offsetofend(struct sockaddr, sa_family)) { + maddr->addrp = NULL; + maddr->port = 0; + maddr->len = 0; + return 0; + } + + /* + * its possibly to have sk->sk_family == PF_INET6 and + * addr->sa_family == AF_INET. sk_family is used for socket + * mediation, sa_family for when we have address ... + */ + switch (addr->sa_family) { + case AF_INET: + addr4 = (struct sockaddr_in *)addr; + if (addrlen < sizeof(struct sockaddr_in)) + return -EINVAL; + maddr->port = addr4->sin_port; + maddr->addrp = (char *)&addr4->sin_addr.s_addr; + maddr->len = 4; + break; + case AF_INET6: + addr6 = (struct sockaddr_in6 *)addr; + if (addrlen < SIN6_LEN_RFC2133) + return -EINVAL; + maddr->port = addr6->sin6_port; + maddr->addrp = (char *)&addr6->sin6_addr.s6_addr; + maddr->len = 16; + break; + default: + return -EAFNOSUPPORT; + } + /* per ip spec, && sk->sk_type == SOCK_RAW*/ + if (raw_port && addrtype != ADDR_REMOTE) + maddr->port = htons(raw_port); + if (ad) + set_ad_addr(ad, addr->sa_family, addrtype != ADDR_REMOTE, maddr); + + return 0; +} + +/* -ENOTCONN if not connected */ +static int map_sock_addr(struct socket *sock, enum addr_type addrtype, + struct stored_match_addr *maddr, + struct apparmor_audit_data *ad) +{ + /* do we need early bailout for !family ... */ + maddr->addrlen = sock->ops->getname(sock, (struct sockaddr *) &maddr->addr, addrtype != ADDR_REMOTE ? 0 : 1); + if (maddr->addrlen == -ENOTCONN) { + maddr->addrlen = 0; + return map_addr(NULL, 0, 0, addrtype, &maddr->maddr, ad); + } else if (maddr->addrlen < 0) + return maddr->addrlen; + return map_addr(&maddr->addr, maddr->addrlen, 0, addrtype, + &maddr->maddr, ad); +} + +/* TODO: combine with connect map addr */ +/* TODO: raw_port */ +static int bind_map_addr(struct sock *sk, struct sockaddr *addr, int addrlen, + struct match_addr *maddr, + struct apparmor_audit_data *ad) +{ + struct sockaddr_in *addr4 = NULL; + struct sockaddr_in6 *addr6 = NULL; + u16 family; + + AA_BUG(!addr); + AA_BUG(!maddr); + + if (addrlen < offsetofend(struct sockaddr, sa_family)) + return -EINVAL; + + maddr->addrtype = ADDR_LOCAL; + /* + * its possibly to have sk->sk_family == PF_INET6 and + * addr->sa_family == AF_INET. sk_family is used for socket + * mediation, sa_family for when we have address ... + */ + family = addr->sa_family; + switch (addr->sa_family) { + case AF_UNSPEC: + if (sk->sk_family == PF_INET6) { + /* Length check from inet6_bind_sk() */ + if (addrlen < SIN6_LEN_RFC2133) + return -EINVAL; + /* Family check from __inet6_bind() */ + return -EAFNOSUPPORT; + } + /* see __inet_bind(), we only want to allow + * AF_UNSPEC if the address is INADDR_ANY + */ + if (addr4->sin_addr.s_addr != htonl(INADDR_ANY)) + return -EAFNOSUPPORT; + family = AF_INET; + fallthrough; + case AF_INET: + addr4 = (struct sockaddr_in *)addr; + if (addrlen < sizeof(struct sockaddr_in)) + return -EINVAL; + maddr->port = addr4->sin_port; + maddr->addrp = (char *)&addr4->sin_addr.s_addr; + maddr->len = 4; + break; + case AF_INET6: + addr6 = (struct sockaddr_in6 *)addr; + if (addrlen < SIN6_LEN_RFC2133) + return -EINVAL; + maddr->port = addr6->sin6_port; + maddr->addrp = (char *)&addr6->sin6_addr.s6_addr; + maddr->len = 16; + break; + default: + return -EAFNOSUPPORT; + } + + if (ad) + set_ad_addr(ad, family, true, maddr); + + return 0; +} + +/* only continue match if + * insufficient current perms at current state + * indicates there are more perms in later state + * Returns: perms struct if early match + */ +static struct aa_perms *early_match(struct aa_policydb *policy, + aa_state_t state, u32 request) +{ + struct aa_perms *p; + + p = aa_lookup_perms(policy, state); + if (((p->allow & request) != request) && (p->allow & AA_CONT_MATCH)) + return NULL; + return p; +} + +static int do_perms(struct aa_profile *profile, aa_state_t state, u32 request, + struct aa_perms *p, struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms perms; + + AA_BUG(!profile); + + if (state || !p) + p = aa_lookup_perms(rules->policy, state); + perms = *p; + aa_apply_modes_to_perms(profile, &perms); + return aa_check_perms(profile, &perms, request, ad, + audit_net_cb); +} + +static aa_state_t match_addr(struct aa_dfa *dfa, aa_state_t state, + struct match_addr *maddr) +{ + char l = (char) maddr->addrtype; + + state = aa_dfa_match_len(dfa, state, &l, 1); + state = aa_dfa_match_len(dfa, state, (char *)&maddr->port, 2); + if (maddr->len == 0 && !maddr->addrp) { + l = 0; + } else if (maddr->len == 4) { + l = 1; + } else if (maddr->len == 16) { + l = 2; + } else { + AA_BUG("address length unsupported"); + return 0; + } + state = aa_dfa_match_len(dfa, state, &l, 1); + if (maddr->addrp) + state = aa_dfa_match_len(dfa, state, maddr->addrp, maddr->len); + /* null transition between addr and label */ + state = aa_dfa_null_transition(dfa, state); + + return state; +} + + +static aa_state_t match_addr_info(struct aa_dfa *dfa, aa_state_t state, + struct match_addr *maddr, + const char **info) +{ + state = match_addr(dfa, state, maddr); + if (!state) { + *info = maddr->addrtype == ADDR_REMOTE ? + "failed remote addr match" : + "failed local addr match"; + } + + return state; +} + +static aa_state_t match_addr_label(struct aa_policydb *policy, aa_state_t state, + u32 request, struct match_addr *maddr, + struct aa_perms **p, const char **info) +{ + state = match_addr_info(policy->dfa, state, maddr, info); + *p = early_match(policy, state, request); + if (!*p) { + /* TODO: actual label match: */ + if (!state) { + *info = maddr->addrtype == ADDR_REMOTE ? + "failed remote label match" : + "failed local label match"; + } + + /* null transition after label match */ + state = aa_dfa_null_transition(policy->dfa, state); + } + + return state; +} + + +static aa_state_t match_to_sk(struct aa_policydb *policy, aa_state_t state, + u32 request, struct sock *sk, + struct match_addr *maddr, + struct aa_perms **p, const char **info) +{ + *p = NULL; + state = aa_match_to_prot(policy, state, request, sk->sk_family, + sk->sk_type, sk->sk_protocol, p, info); + if (*p || !state) + return state; + return match_addr_label(policy, state, request, maddr, p, info); +} + +enum cmd_type { + CMD_ADDR = 1, + CMD_LISTEN = 2, + CMD_OPT = 4, +}; + +static inline aa_state_t match_to_cmd(struct aa_policydb *policy, + aa_state_t state, u32 request, + struct sock *sk, enum cmd_type cmd, + struct match_addr *maddr, + struct aa_perms **p, const char **info) +{ + state = match_to_sk(policy, state, request, sk, maddr, p, info); + if (!*p && state) { + char c = (char) cmd; + state = aa_dfa_match_len(policy->dfa, state, &c, 1); + if (!state) + *info = "failed cmd selection match"; + } + + return state; +} + +/* +static int match_label(struct aa_profile *profile, struct aa_profile *peer, + aa_state_t state, u32 request, + struct apparmor_audit_data *ad) +{ + AA_BUG(!profile); + AA_BUG(!peer); + + ad->peer = &peer->label; + + if (state) { + state = aa_dfa_match(profile->policy.dfa, state, + peer->base.hname); + if (!state) + ad->info = "failed peer label match"; + } + return do_perms(profile, state, request, ad); +} +*/ + +/* ---------------------------------------------------------------------- */ + + + +static inline int profile_sk_perm(struct aa_profile *profile, u32 request, + struct sock *sk, struct match_addr *maddr, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + + state = RULE_MEDIATES_NET(rules); + if (state) { + state = match_to_sk(rules->policy, state, request, sk, + maddr, &p, &ad->info); + return do_perms(profile, state, request, p, ad); + } + + return aa_profile_af_sk_perm(profile, ad, request, sk); +} + +/* no kernel_t bailout */ +static int profile_create_perm(struct aa_profile *profile, int family, + int type, int protocol, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + + state = RULE_MEDIATES_NET(rules); + if (state) { + state = aa_match_to_prot(rules->policy, state, AA_MAY_CREATE, + family, type, protocol, &p, &ad->info); + return do_perms(profile, state, AA_MAY_CREATE, p, ad); + } + + return aa_profile_af_compat_perm(profile, ad, AA_MAY_CREATE, family, + type); +} + + +/* sendmsg/rcvmsg/connect */ +static int profile_remote_perm(struct aa_profile *profile, struct sock *sk, + u32 request, struct match_addr *raddr, + struct match_addr *laddr, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + AA_BUG(!raddr); + AA_BUG(!laddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SK(rules, sk); + if (!state) + return aa_profile_af_sk_perm(profile, ad, request, sk); + + /* TODO: deal with sa_family vs. sk_family */ + state = match_to_cmd(rules->policy, state, request, sk, CMD_ADDR, + raddr, &p, &ad->info); + if (state && !p) + /* check if perm is restricted to a pairing */ + state = match_addr_label(rules->policy, state, request, + laddr, &p, &ad->info); + return do_perms(profile, state, request, p, ad); +} + +static int profile_bind_perm(struct aa_profile *profile, struct sock *sk, + struct match_addr *maddr, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + unsigned short sport; + + AA_BUG(!profile); + AA_BUG(!sk); + AA_BUG(!maddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SK(rules, sk); + if (!state) + return aa_profile_af_sk_perm(profile, ad, AA_MAY_BIND, sk); + + /* + * its possibly to have sk->sk_family == PF_INET6 and + * addr->sa_family == AF_INET + */ + sport = ntohs(maddr->port); + if (sport) { + if (inet_port_requires_bind_service(sock_net(sk), sport)) { + /* cap NET_BIND_SERVICE will get raised */ + maddr->addrtype = ADDR_LOCAL_PRIV; + } + } + state = match_to_sk(rules->policy, state, AA_MAY_BIND, sk, + maddr, &p, &ad->info); + return do_perms(profile, state, AA_MAY_BIND, p, ad); +} + +static int profile_listen_perm(struct aa_profile *profile, struct sock *sk, + struct match_addr *maddr, int backlog, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + AA_BUG(!maddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SK(rules, sk); + if (state) { + __be16 b = htons(backlog); + + state = match_to_cmd(rules->policy, state, AA_MAY_LISTEN, sk, + CMD_LISTEN, maddr, &p, &ad->info); + if (state && !p) { + state = aa_dfa_match_len(rules->policy->dfa, state, + (char *) &b, 2); + if (!state) + ad->info = "failed listen backlog match"; + } + return do_perms(profile, state, AA_MAY_LISTEN, p, ad); + } + + return aa_profile_af_sk_perm(profile, ad, AA_MAY_LISTEN, sk); +} + +static inline int profile_accept_perm(struct aa_profile *profile, + struct sock *sk, struct match_addr *maddr, + struct sock *newsk, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + /* AA_BUG(!newsk); newsk can be null here, since not using atm ... */ + AA_BUG(!maddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SK(rules, sk); + if (state) { + state = match_to_sk(rules->policy, state, AA_MAY_ACCEPT, sk, + maddr, &p, &ad->info); + return do_perms(profile, state, AA_MAY_ACCEPT, p, ad); + } + + return aa_profile_af_sk_perm(profile, ad, AA_MAY_ACCEPT, sk); +} + +/* getopt/setopt */ +static int profile_opt_perm(struct aa_profile *profile, u32 request, + struct sock *sk, struct match_addr *maddr, + int level, int optname, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + AA_BUG(!maddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SK(rules, sk); + if (state) { + __be16 l = htons(level); + __be16 n = htons(optname); + + state = match_to_cmd(rules->policy, state, request, sk, + CMD_OPT, maddr, &p, &ad->info); + if (state && !p) { + state = aa_dfa_match_len(rules->policy->dfa, state, + (char *) &l, 2); + state = aa_dfa_match_len(rules->policy->dfa, state, + (char *) &n, 2); + if (!state) + ad->info = "failed sockopt match"; + } + return do_perms(profile, state, request, p, ad); + } + + return aa_profile_af_sk_perm(profile, ad, request, sk); +} + +/* ---------------------------------------------------------------------- */ + +// TODO: cleanup init to use recursion, so we can have N init fns, in 1 macro +// TODO: lift DEFINE_AUDIT out of macro into init fn??? + +/* no kernel_t bailout */ +#define label_sk_has_perm2(CRED, LABEL, SOCKSK, OP, REQUEST, PROFILE, AAD, XXXX, YYYY, CALLBACKFN) \ +({ \ + int __EERROR = 0; \ + if (label_mediates(LABEL, AA_CLASS_NET)) { \ + struct aa_profile *PROFILE; \ + DEFINE_AUDIT_SK(AAD, OP, CRED, SOCKSK); \ + (AAD).subj_cred = (CRED); \ + __EERROR = (XXXX); \ + if (__EERROR == 0) { \ + __EERROR = (YYYY); \ + if (__EERROR == 0) { \ + __EERROR = fn_for_each(label, PROFILE, \ + (CALLBACKFN)); \ + } \ + } \ + } \ + __EERROR; \ +}) + +/* no kernel_t bailout */ +#define label_sk_has_perm(CRED, LABEL, SOCKSK, OP, REQUEST, PROFILE, AAD, CALLBACKFN) \ + label_sk_has_perm2(CRED, LABEL, SOCKSK, OP, REQUEST, PROFILE, AAD, \ + 0, 0, CALLBACKFN) + +/* no kernel_t bailout */ +#define label_sk_has_perm1(CRED, LABEL, SOCKSK, OP, REQUEST, PROFILE, AAD, XXXX, CALLBACKFN) \ + label_sk_has_perm2(CRED, LABEL, SOCKSK, OP, REQUEST, PROFILE, AAD, \ + XXXX, 0, CALLBACKFN) + + +/* Early bailout for kernel_t - 2 init args before callback */ +#define sk_has_perm2(SOCKSK, OP, REQUEST, PROFILE, AAD, XXXXY, YYYYX, CALLBACKFN) \ +({ \ + struct aa_label *label; \ + struct aa_sk_ctx *ctx= aa_sock(SOCKSK); \ + int __ERROR = 0; \ + if (rcu_access_pointer(ctx->label) != kernel_t) { \ + \ + label = begin_current_label_crit_section(); \ + __ERROR = label_sk_has_perm2(current_cred(), label, SOCKSK, OP, REQUEST, PROFILE, AAD, XXXXY, YYYYX, CALLBACKFN); \ + end_current_label_crit_section(label); \ + } \ + __ERROR; \ +}) + +/* Early bailout for kernel_t - no init args before callback */ +#define sk_has_perm(SOCKSK, OP, REQUEST, PROFILE, AAD, CALLBACKFN) \ + sk_has_perm2(SOCKSK, OP, REQUEST, PROFILE, AAD, 0, 0, CALLBACKFN) + + +/* Early bailout for kernel_t - 1 init arg before callback */ +#define sk_has_perm1(SOCKSK, OP, REQUEST, PROFILE, AAD, XXXXY, CALLBACKFN) \ + sk_has_perm2(SOCKSK, OP, REQUEST, PROFILE, AAD, XXXXY, 0, CALLBACKFN) + + + +/* no kernel_t early bailout */ +/* NOTE: already lifted label_mediates into lsm.c */ +int aa_inet_create_perm(struct aa_label *label, int family, int type, + int protocol) +{ + struct aa_profile *profile; + int error = 0; + DEFINE_AUDIT_NET(ad, OP_CREATE, current_cred(), NULL, family, type, + protocol); + + ad.subj_cred = current_cred(); + set_ad_create(&ad, family, type, protocol); + error = fn_for_each(label, profile, + profile_create_perm(profile, family, type, + protocol, &ad)); + + + return error; +} + +int aa_inet_bind_perm(struct socket *sock, struct sockaddr *addr, + int addrlen) +{ + struct match_addr maddr; + + return sk_has_perm1(sock->sk, OP_BIND, AA_MAY_BIND, profile, ad, + bind_map_addr(sock->sk, addr, addrlen, &maddr, + &ad), + profile_bind_perm(profile, sock->sk, &maddr, &ad)); +} + + +int aa_inet_connect_perm(struct socket *sock, struct sockaddr *addr, + int addrlen) +{ + struct stored_match_addr laddr; + struct match_addr raddr; + + /* disconnect socket */ + if (addr->sa_family == AF_UNSPEC) + return 0; + if (addrlen < offsetofend(struct sockaddr, sa_family)) + return -EINVAL; + + /* do we need early bailout for !family ... */ + return sk_has_perm2(sock->sk, OP_CONNECT, AA_MAY_CONNECT, profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &laddr, &ad), + map_addr(addr, addrlen, 0, ADDR_REMOTE, &raddr, + &ad), + profile_remote_perm(profile, sock->sk, + AA_MAY_CONNECT, &raddr, + &laddr.maddr, &ad)); +} + +int aa_inet_listen_perm(struct socket *sock, int backlog) +{ + struct stored_match_addr maddr; + + /* do we need early bailout for !family ... */ + return sk_has_perm1(sock->sk, OP_LISTEN, AA_MAY_LISTEN, profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &maddr, &ad), + profile_listen_perm(profile, sock->sk, &maddr.maddr, + backlog, &ad)); +} + +/* ability of sock to connect, not peer address binding */ +int aa_inet_accept_perm(struct socket *sock, struct socket *newsock) +{ + struct stored_match_addr maddr; + int error; + + error = sk_has_perm1(sock->sk, OP_ACCEPT, AA_MAY_ACCEPT, profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &maddr, &ad), + profile_accept_perm(profile, sock->sk, + &maddr.maddr, + newsock->sk, &ad)); + + /* selinux updates inode - need to investigate this more */ + return error; +} + +/* sendmsg, recvmsg. */ +int aa_inet_msg_perm(const char *op, u32 request, struct socket *sock, + struct msghdr *msg, int size) +{ + struct stored_match_addr laddr; + struct match_addr raddr; + + /* do we need early bailout for !family ... */ + return sk_has_perm2(sock->sk, op, request, profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &laddr, &ad), + map_addr(msg->msg_name, msg->msg_namelen, 0, + ADDR_REMOTE, &raddr, &ad), + profile_remote_perm(profile, sock->sk, request, + &raddr, &laddr.maddr, &ad)); +} + +/* getopt, setopt */ +int aa_inet_opt_perm(const char *op, u32 request, struct socket *sock, + int level, int optname) +{ + struct stored_match_addr maddr; + + return sk_has_perm1(sock->sk, op, request, profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &maddr, &ad), + profile_opt_perm(profile, request, sock->sk, + &maddr.maddr, level, optname, &ad)); +} + +static int inet_label_sock_perm(const struct cred *cred, struct aa_label *label, + const char *op, u32 request, + struct socket *sock) +{ + struct stored_match_addr maddr; + + return label_sk_has_perm1(cred, label, sock->sk, op, request, profile, + ad, + map_sock_addr(sock, ADDR_LOCAL, &maddr, &ad), + profile_sk_perm(profile, request, sock->sk, + &maddr.maddr, &ad)); +} + +/* revaliation, get/set attr/getsockname/peername */ +int aa_inet_sock_perm(const char *op, u32 request, struct socket *sock) +{ + struct aa_sk_ctx *ctx= aa_sock(sock->sk); + struct aa_label *label; + int error; + + if (rcu_access_pointer(ctx->label) == kernel_t) + return 0; + + label = begin_current_label_crit_section(); + error = inet_label_sock_perm(current_cred(), label, op, request, sock); + end_current_label_crit_section(label); + + return error; +} + +int aa_inet_file_perm(const struct cred *subj_cred, struct aa_label *label, + const char *op, u32 request, struct socket *sock) +{ + u32 sk_req = request & ~NET_PEER_MASK; + struct stored_match_addr laddr; + struct sock *sk = sock->sk; + int error = 0; + + AA_BUG(!label); + AA_BUG(!sock); + AA_BUG(!sock->sk); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + /* access to the local sock */ + error = label_sk_has_perm1(subj_cred, label, sock->sk, op, request, + profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &laddr, &ad), + profile_sk_perm(profile, sk_req, sock->sk, &laddr.maddr, + &ad)); + + if (!error) { + struct stored_match_addr laddr, raddr; + + /* TODO: have ad here: instead of in CB so we do have to redo */ + error = map_sock_addr(sock, ADDR_REMOTE, &raddr, NULL); + if (!error && raddr.maddr.addrp) { + error = label_sk_has_perm1(subj_cred, label, sock->sk, + op, request, profile, ad, + set_ad_addr(&ad, raddr.addr.sa_family, + false, &raddr.maddr), + profile_remote_perm(profile, sock->sk, + request, + &raddr.maddr, + &laddr.maddr, &ad)); + } + } + + return error; +} diff --git a/security/apparmor/af_unix.c b/security/apparmor/af_unix.c index b9b22edae2029d..b70a1972277727 100644 --- a/security/apparmor/af_unix.c +++ b/security/apparmor/af_unix.c @@ -53,7 +53,7 @@ static int unix_fs_perm(const char *op, u32 mask, const struct cred *subj_cred, }; return aa_path_perm(op, subj_cred, label, path, - PATH_SOCK_COND, mask, &cond); + PATH_SOCK_COND, mask, &cond, NULL); } /* else implicitly delegated */ return 0; @@ -208,7 +208,7 @@ static int profile_create_perm(struct aa_profile *profile, int family, AA_BUG(!profile); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { state = aa_match_to_prot(rules->policy, state, AA_MAY_CREATE, PF_UNIX, type, protocol, NULL, @@ -218,8 +218,8 @@ static int profile_create_perm(struct aa_profile *profile, int family, NULL, ad); } - return aa_profile_af_perm(profile, ad, AA_MAY_CREATE, family, type, - protocol); + return aa_profile_af_compat_perm(profile, ad, AA_MAY_CREATE, family, + type); } static int profile_sk_perm(struct aa_profile *profile, @@ -234,7 +234,7 @@ static int profile_sk_perm(struct aa_profile *profile, AA_BUG(!sk); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { if (is_unix_fs(sk)) return unix_fs_perm(ad->op, request, ad->subj_cred, @@ -263,7 +263,7 @@ static int profile_bind_perm(struct aa_profile *profile, struct sock *sk, AA_BUG(!ad); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { if (is_unix_addr_fs(ad->net.addr, ad->net.addrlen)) /* under v7-9 fs hook handles bind */ @@ -294,7 +294,7 @@ static int profile_listen_perm(struct aa_profile *profile, struct sock *sk, AA_BUG(!ad); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { __be16 b = cpu_to_be16(backlog); @@ -331,7 +331,7 @@ static int profile_accept_perm(struct aa_profile *profile, AA_BUG(!ad); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { if (is_unix_fs(sk)) return unix_fs_perm(ad->op, AA_MAY_ACCEPT, @@ -361,7 +361,7 @@ static int profile_opt_perm(struct aa_profile *profile, u32 request, AA_BUG(!ad); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { __be16 b = cpu_to_be16(optname); if (is_unix_fs(sk)) @@ -402,7 +402,7 @@ static int profile_peer_perm(struct aa_profile *profile, u32 request, AA_BUG(!peer_label); AA_BUG(!ad); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { struct aa_profile *peerp; diff --git a/security/apparmor/apparmorfs.c b/security/apparmor/apparmorfs.c index 56155d7d5b2fc8..cfd99b54f09182 100644 --- a/security/apparmor/apparmorfs.c +++ b/security/apparmor/apparmorfs.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "include/apparmor.h" #include "include/apparmorfs.h" @@ -37,6 +38,7 @@ #include "include/policy.h" #include "include/policy_ns.h" #include "include/resource.h" +#include "include/path.h" #include "include/policy_unpack.h" #include "include/task.h" @@ -685,6 +687,368 @@ static const struct file_operations aa_fs_ns_revision_fops = { .release = ns_revision_release, }; + +/* file hook fn for notificaions of policy actions */ +static int listener_release(struct inode *inode, struct file *file) +{ + struct aa_listener_proxy *proxy = file->private_data; + + if (!aa_current_policy_admin_capable(NULL)) + return -EPERM; + AA_DEBUG(DEBUG_UPCALL, "file %p, listener %p, id %llu", file, proxy->listener, proxy->listener->listener_id); + if (proxy) { + AA_DEBUG(DEBUG_UPCALL, "file putting proxy"); + aa_delayed_free_listener_proxy(proxy); + } + return 0; +} + +static int listener_open(struct inode *inode, struct file *file) +{ + struct aa_listener_proxy *proxy; + struct aa_listener *listener; + struct aa_ns *ns = NULL; + + if (!aa_current_policy_admin_capable(NULL)) + return -EPERM; + listener = aa_new_listener(NULL, GFP_KERNEL); + if (!listener) + return -ENOMEM; + proxy = aa_new_listener_proxy(listener, ns); + aa_put_listener(listener); + if (!proxy) + return -ENOMEM; + AA_DEBUG(DEBUG_UPCALL, "Registered listener using protocol version %d", + listener->version); + file->private_data = proxy; + return 0; +} + +static bool notif_supported_version(struct apparmor_notif_common *unotif) +{ + return (unotif->version == 3 || unotif->version == 5); +} + +/* todo: separate register and set filter */ +static long notify_set_filter(struct aa_listener *listener, + unsigned long arg) +{ + union apparmor_notif_filters *unotif; + struct aa_ns *ns = NULL; + long ret; + u16 size; + void __user *buf = (void __user *)arg; + + if (copy_from_user(&size, buf, sizeof(size))) + return -EFAULT; + if (size < sizeof(unotif)) + return -EINVAL; + /* size is capped at U16_MAX by data type */ + unotif = kzalloc(size, GFP_KERNEL); + if (!unotif) + return -ENOMEM; + + if (copy_from_user(unotif, buf, size)) { + ret = -EFAULT; + goto out; + } + ret = size; + + if (!notif_supported_version((struct apparmor_notif_common *)unotif)) { + AA_DEBUG(DEBUG_UPCALL, "Failed to Register listener using unsupported protocol version %d", unotif->base.version); + ret = -EPROTONOSUPPORT; + goto out; + } + + listener->version = unotif->base.version; + /* todo validate to known modes */ + listener->mask = unotif->modeset; + AA_DEBUG(DEBUG_UPCALL, "setting filter mask to 0x%x", listener->mask); + if (unotif->ns) + /* todo */ + ns = NULL; + if (unotif->filter) { + struct aa_dfa *dfa; + void *pos = (void *) unotif + unotif->filter; + + if (unotif->filter >= size || + ALIGN((size_t) pos, 8) != (size_t)pos) { + ret = -EINVAL; + goto out; + } + dfa = aa_dfa_unpack(pos, size - ((void *) unotif - pos), + DFA_FLAG_VERIFY_STATES | + TO_ACCEPT1_FLAG(YYTD_DATA32)); + if (IS_ERR(dfa)) { + ret = PTR_ERR(dfa); + goto out; + } + listener->filter = dfa; + } + +out: + kfree(unotif); + + return ret; +} + + +static long notify_user_recv(struct aa_listener *listener, + unsigned long arg) +{ + struct apparmor_notif_common common; + void __user *buf = (void __user *)arg; + __u16 version; + + if (copy_from_user(&common.len, buf, sizeof(common.len))) + return -EFAULT; + if (listener->version >= 5) { + /* allow individual messages to specify version */ + if (common.len < sizeof(common)) + return -EMSGSIZE; + if (copy_from_user(&common, buf, sizeof(common))) + return -EFAULT; + version = common.version; + } else { + version = listener->version; + } + /* size check handled by individual message handlers */ + return aa_listener_unotif_recv(listener, buf, common.len, + version); +} + +static long notify_user_response(struct aa_listener *listener, + unsigned long arg) +{ + union apparmor_notif_resp uresp = {}; + union apparmor_notif_resp *big_resp = NULL; + long error; + u16 size; + void __user *buf = (void __user *)arg; + + if (copy_from_user(&size, buf, sizeof(size))) + return -EFAULT; + if (size > aa_g_path_max) + return -EMSGSIZE; + if (size > sizeof(uresp)) { + /* TODO: put max size on message */ + big_resp = (union apparmor_notif_resp *) aa_get_buffer(false); + if (big_resp) + return -ENOMEM; + if (copy_from_user(big_resp, buf, size)) { + kfree(big_resp); + return -EFAULT; + } + } else { + size = min_t(size_t, size, sizeof(uresp)); + if (copy_from_user(&uresp, buf, size)) + return -EFAULT; + } + + if (!notif_supported_version((struct apparmor_notif_common *)&uresp)) { + AA_DEBUG(DEBUG_UPCALL, "Failed response listener using unsupported protocol version %d", uresp.base.base.version); + error = -EPROTONOSUPPORT; + goto out; + } + error = aa_listener_unotif_response(listener, &uresp, size); +out: + aa_put_buffer((char *) big_resp); + + return error; +} + +static long notify_is_id_valid(struct aa_listener *listener, + unsigned long arg) +{ + void __user *buf = (void __user *)arg; + u64 id; + long ret = -ENOENT; + + if (copy_from_user(&id, buf, sizeof(id))) + return -EFAULT; + + spin_lock(&listener->lock); + if (__aa_find_notif(listener, id)) + ret = 0; + spin_unlock(&listener->lock); + + return ret; +} + +static long notify_user_register(struct aa_listener *listener, + unsigned long arg, struct file *file) +{ + struct apparmor_notif_register_v5 reg; + struct aa_listener *found = NULL; + void __user *buf = (void __user *)arg; + long res; + + if (copy_from_user(®.base.len, buf, sizeof(reg.base.len))) + return -EFAULT; + if (reg.base.len < sizeof(reg)) + return -EMSGSIZE; + if (copy_from_user(®, buf, sizeof(reg))) + return -EFAULT; + /* to balance potential put and retry, ideally would grab from + * file here, but need to refactor for that + */ + aa_get_listener(listener); +retry: + res = aa_register_listener_id(listener, ®.listener_id, &found); + AA_DEBUG(DEBUG_UPCALL, "registered id %llu found %p res %ld", reg.listener_id, found, res); + if (res >= 0) { + if (found) { + struct aa_listener *l; + + AA_DEBUG(DEBUG_UPCALL, "updating file"); + struct aa_listener_proxy *proxy; + + spin_lock(&file->f_lock); + proxy = file->private_data; + if (proxy->listener != listener) { + /* raced, try again */ + l = aa_get_listener(proxy->listener); + spin_unlock(&file->f_lock); + aa_put_listener(found); + aa_put_listener(listener); + listener = l; + found = NULL; + goto retry; + } + spin_lock(&listener->lock); + l = proxy->listener; + proxy->listener = NULL; + list_del_init(&proxy->llist); + spin_unlock(&listener->lock); + + spin_lock(&found->lock); + proxy->listener = found; /* transfer search ref */ + list_add_tail_entry(proxy, &found->ns_proxies, + llist); + spin_unlock(&found->lock); + spin_unlock(&file->f_lock); + aa_put_listener(l); + AA_DEBUG(DEBUG_UPCALL, "completed file update"); + } + res = sizeof(reg); + if (copy_to_user(buf, ®, sizeof(reg))) + res = -EFAULT; + } + aa_put_listener(listener); + /* size check handled by individual message handlers */ + + return res; +} + +static long notify_user_resend(struct aa_listener *listener, + unsigned long arg) +{ + struct apparmor_notif_resend_v5 resend; + void __user *buf = (void __user *)arg; + long res; + + if (copy_from_user(&resend.base.len, buf, sizeof(resend.base.len))) + return -EFAULT; + if (resend.base.len < sizeof(resend)) + return -EMSGSIZE; + if (copy_from_user(&resend, buf, sizeof(resend))) + return -EFAULT; + + /* size check handled by individual message handlers */ + res = aa_listener_unotif_resend(listener, &resend.ready, + &resend.pending); + if (!res) { + if (copy_to_user(buf, &resend, sizeof(resend))) + return -EFAULT; + res = sizeof(resend); + } + return res; +} + + +static long listener_ioctl_switch(struct file *file, + struct aa_listener *listener, + unsigned int cmd, unsigned long arg) +{ + /* todo permission to issue these commands */ + switch (cmd) { + case APPARMOR_NOTIF_SET_FILTER: + return notify_set_filter(listener, arg); + case APPARMOR_NOTIF_RECV: + return notify_user_recv(listener, arg); + case APPARMOR_NOTIF_SEND: + return notify_user_response(listener, arg); + case APPARMOR_NOTIF_IS_ID_VALID: + return notify_is_id_valid(listener, arg); + case APPARMOR_NOTIF_REGISTER: + return notify_user_register(listener, arg, file); + case APPARMOR_NOTIF_RESEND: + return notify_user_resend(listener, arg); + } + return -EINVAL; +} + +static long listener_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct aa_listener_proxy *proxy; + struct aa_listener *listener; + long error; + + if (!aa_current_policy_admin_capable(NULL)) + return -EPERM; + + spin_lock(&file->f_lock); + proxy = file->private_data; + listener = aa_get_listener(proxy->listener); + spin_unlock(&file->f_lock); + if (!listener) + return -EINVAL; + + error = listener_ioctl_switch(file, listener, cmd, arg); + aa_put_listener(listener); + + return error; +} + +static __poll_t listener_poll(struct file *file, poll_table *pt) +{ + struct aa_listener_proxy *proxy; + struct aa_listener *listener; + __poll_t mask = 0; + + if (!aa_current_policy_admin_capable(NULL)) + return EPOLLERR; + + spin_lock(&file->f_lock); + proxy = file->private_data; + listener = aa_get_listener(proxy->listener); + spin_unlock(&file->f_lock); + + if (listener) { + spin_lock(&listener->lock); + poll_wait(file, &listener->wait, pt); + if (!list_empty(&listener->notifications)) + mask |= EPOLLIN | EPOLLRDNORM; + if (!list_empty(&listener->pending)) + mask |= EPOLLOUT | EPOLLWRNORM; + spin_unlock(&listener->lock); + } + aa_put_listener(listener); + + return mask; +} + +static const struct file_operations aa_sfs_notify_fops = { + .owner = THIS_MODULE, + .open = listener_open, + .poll = listener_poll, +// .read = notification_read, + .llseek = generic_file_llseek, + .release = listener_release, + .unlocked_ioctl = listener_ioctl, +}; + static void profile_query_cb(struct aa_profile *profile, struct aa_perms *perms, const char *match_str, size_t match_len) { @@ -707,14 +1071,6 @@ static void profile_query_cb(struct aa_profile *profile, struct aa_perms *perms, } else if (rules->policy->dfa) { if (!RULE_MEDIATES(rules, *match_str)) return; /* no change to current perms */ - /* old user space does not correctly detect dbus mediation - * support so we may get dbus policy and requests when - * the abi doesn't support it. This can cause mediation - * regressions, so explicitly test for this situation. - */ - if (*match_str == AA_CLASS_DBUS && - !RULE_MEDIATES_v9NET(rules)) - return; /* no change to current perms */ state = aa_dfa_match_len(rules->policy->dfa, rules->policy->start[0], match_str, match_len); @@ -1083,6 +1439,10 @@ static int aa_sfs_seq_show(struct seq_file *seq, void *v) case AA_SFS_TYPE_BOOLEAN: seq_printf(seq, "%s\n", str_yes_no(fs_file->v.boolean)); break; + case AA_SFS_TYPE_BOOLEAN_INTPRINT: + // Allow printing the boolean as 0/1 for backwards compatibility + seq_printf(seq, "%s\n", fs_file->v.boolean ? "1" : "0"); + break; case AA_SFS_TYPE_STRING: seq_printf(seq, "%s\n", fs_file->v.string); break; @@ -1206,10 +1566,24 @@ static int seq_profile_hash_show(struct seq_file *seq, void *v) return 0; } +static int seq_profile_learning_count_show(struct seq_file *seq, void *v) +{ + struct aa_proxy *proxy = seq->private; + struct aa_label *label = aa_get_label_rcu(&proxy->label); + struct aa_profile *profile = labels_profile(label); + int count = READ_ONCE(profile->learning_cache.size); + + seq_printf(seq, "%d\n", count); + aa_put_label(label); + + return 0; +} + SEQ_PROFILE_FOPS(name); SEQ_PROFILE_FOPS(mode); SEQ_PROFILE_FOPS(attach); SEQ_PROFILE_FOPS(hash); +SEQ_PROFILE_FOPS(learning_count); /* * namespace based files @@ -1899,6 +2273,12 @@ int __aafs_profile_mkdir(struct aa_profile *profile, struct dentry *parent) goto fail; profile->dents[AAFS_PROF_ATTACH] = dent; + dent = create_profile_file(dir, "learning_count", profile, + &seq_profile_learning_count_fops); + if (IS_ERR(dent)) + goto fail; + profile->dents[AAFS_PROF_LEARNING_COUNT] = dent; + if (profile->hash) { dent = create_profile_file(dir, "sha256", profile, &seq_profile_hash_fops); @@ -2427,6 +2807,12 @@ static struct aa_sfs_entry aa_sfs_entry_file[] = { { } }; +static struct aa_sfs_entry aa_sfs_entry_ipc[] = { + AA_SFS_FILE_STRING("posix_mqueue", + "create read write open delete setattr getattr label"), + { } +}; + static struct aa_sfs_entry aa_sfs_entry_ptrace[] = { AA_SFS_FILE_STRING("mask", "read trace"), { } @@ -2452,7 +2838,9 @@ static struct aa_sfs_entry aa_sfs_entry_domain[] = { AA_SFS_FILE_BOOLEAN("post_nnp_subset", 1), AA_SFS_FILE_BOOLEAN("computed_longest_left", 1), AA_SFS_DIR("attach_conditions", aa_sfs_entry_attach), + AA_SFS_FILE_BOOLEAN("interruptible", 1), AA_SFS_FILE_BOOLEAN("disconnected.path", 1), + AA_SFS_FILE_BOOLEAN("disconnected.ipc", 1), AA_SFS_FILE_BOOLEAN("kill.signal", 1), AA_SFS_FILE_STRING("version", "1.2"), { } @@ -2460,6 +2848,11 @@ static struct aa_sfs_entry aa_sfs_entry_domain[] = { static struct aa_sfs_entry aa_sfs_entry_unconfined[] = { AA_SFS_FILE_BOOLEAN("change_profile", 1), + /* Retain backwards compatibility with Ubuntu userspace + * code that is expecting integer values for these sysctls + */ + AA_SFS_FILE_BOOLEAN_INTPRINT("userns", 1), + AA_SFS_FILE_BOOLEAN_INTPRINT("io_uring", 1), { } }; @@ -2472,6 +2865,21 @@ static struct aa_sfs_entry aa_sfs_entry_versions[] = { { } }; +static struct aa_sfs_entry aa_sfs_entry_notify[] = { + AA_SFS_FILE_STRING("user", "file tags"), + { } +}; + +static struct aa_sfs_entry aa_sfs_entry_notify_versions[] = { + AA_SFS_FILE_BOOLEAN("v3", 1), + AA_SFS_FILE_BOOLEAN("v5", 1), + { } +}; + +/* permstable v1: skipped + v2: accept1 index, no accept2 + v3: accept1 index, accept2 flags +*/ #define PERMS32STR "allow deny subtree cond kill complain prompt audit quiet hide xindex tag label" static struct aa_sfs_entry aa_sfs_entry_policy[] = { AA_SFS_DIR("versions", aa_sfs_entry_versions), @@ -2481,8 +2889,11 @@ static struct aa_sfs_entry aa_sfs_entry_policy[] = { AA_SFS_FILE_U64("outofband", MAX_OOB_SUPPORTED), AA_SFS_FILE_U64("permstable32_version", 3), AA_SFS_FILE_STRING("permstable32", PERMS32STR), + AA_SFS_FILE_U64("metadata_tagging_version", 1), AA_SFS_FILE_U64("state32", 1), AA_SFS_DIR("unconfined_restrictions", aa_sfs_entry_unconfined), + AA_SFS_DIR("notify", aa_sfs_entry_notify), + AA_SFS_DIR("notify_versions", aa_sfs_entry_notify_versions), { } }; @@ -2496,6 +2907,7 @@ static struct aa_sfs_entry aa_sfs_entry_ns[] = { AA_SFS_FILE_BOOLEAN("profile", 1), AA_SFS_FILE_BOOLEAN("pivot_root", 0), AA_SFS_FILE_STRING("mask", "userns_create"), + AA_SFS_FILE_STRING("userns_create", "pciu&"), { } }; @@ -2525,6 +2937,8 @@ static struct aa_sfs_entry aa_sfs_entry_features[] = { AA_SFS_DIR("policy", aa_sfs_entry_policy), AA_SFS_DIR("domain", aa_sfs_entry_domain), AA_SFS_DIR("file", aa_sfs_entry_file), + AA_SFS_DIR("network", aa_sfs_entry_network_compat), + AA_SFS_DIR("ipc", aa_sfs_entry_ipc), AA_SFS_DIR("network_v8", aa_sfs_entry_network), AA_SFS_DIR("network_v9", aa_sfs_entry_networkv9), AA_SFS_DIR("mount", aa_sfs_entry_mount), @@ -2542,6 +2956,7 @@ static struct aa_sfs_entry aa_sfs_entry_features[] = { static struct aa_sfs_entry aa_sfs_entry_apparmor[] = { AA_SFS_FILE_FOPS(".access", 0666, &aa_sfs_access), + AA_SFS_FILE_FOPS(".notify", 0666, &aa_sfs_notify_fops), AA_SFS_FILE_FOPS(".stacked", 0444, &seq_ns_stacked_fops), AA_SFS_FILE_FOPS(".ns_stacked", 0444, &seq_ns_nsstacked_fops), AA_SFS_FILE_FOPS(".ns_level", 0444, &seq_ns_level_fops), diff --git a/security/apparmor/audit.c b/security/apparmor/audit.c index 4a60b6fda75f14..015a827c22760c 100644 --- a/security/apparmor/audit.c +++ b/security/apparmor/audit.c @@ -289,3 +289,259 @@ int aa_audit_rule_match(struct lsm_prop *prop, u32 field, u32 op, void *vrule) } return 0; } + +/****************************** audit cache *******************************/ + +static int uid_cmp(kuid_t lhs, kuid_t rhs) +{ + if (uid_lt(lhs, rhs)) + return -1; + if (uid_gt(lhs, rhs)) + return 1; + return 0; +} + +/* std C cmp. negative is less than, 0 is equal, positive greater than */ +long aa_audit_data_cmp(struct apparmor_audit_data *lhs, + struct apparmor_audit_data *rhs) +{ + long res; + + /* don't compare type */ + res = lhs->class - rhs->class; + if (res) + return res; + /* don't compare op */ + if (lhs->flags & AUDIT_TAILGLOB_NAME) + /* lhs glob matches strings longer than it */ + res = strncmp(lhs->name, rhs->name, strlen(lhs->name)); + else + res = strcmp(lhs->name, rhs->name); + if (res) + return res; + res = aa_label_cmp(lhs->subj_label, rhs->subj_label); + if (res) + return res; + switch (lhs->class) { + case AA_CLASS_FILE: + if (lhs->subj_cred) { + if (rhs->subj_cred) { + return uid_cmp(lhs->subj_cred->fsuid, + rhs->subj_cred->fsuid); + } else { + return 1; + } + } else if (rhs->subj_cred) { + return -1; + } + res = uid_cmp(lhs->fs.ouid, rhs->fs.ouid); + if (res) + return res; + res = lhs->fs.target - rhs->fs.target; + if (res) + return res; + } + return 0; +} + +static void audit_node_free(struct aa_audit_node *node) +{ + if (!node) + return; + + AA_BUG(!list_empty(&node->list)); + + /* common data that needs freed */ + kfree(node->data.name); + aa_put_label(node->data.subj_label); + if (node->data.subj_cred) + put_cred(node->data.subj_cred); + + /* class specific data that needs freed */ + switch (node->data.class) { + case AA_CLASS_FILE: + aa_put_label(node->data.peer); + kfree(node->data.fs.target); + } + + kmem_cache_free(aa_audit_slab, node); +} + +void aa_audit_node_free_kref(struct kref *kref) +{ + struct aa_audit_node *node = container_of(kref, struct aa_audit_node, + count); + audit_node_free(node); +} + +struct aa_audit_node *aa_dup_audit_data(struct apparmor_audit_data *orig, + gfp_t gfp) +{ + struct aa_audit_node *copy; + + copy = kmem_cache_zalloc(aa_audit_slab, gfp); + if (!copy) + return NULL; + kref_init(©->count); + + copy->knotif.ad = ©->data; + INIT_LIST_HEAD(©->list); + /* copy class early so aa_free_audit_node can use switch on failure */ + copy->data.class = orig->class; + copy->data.flags = orig->flags; + + /* handle anything with possible failure first */ + if (orig->name) { + copy->data.name = kstrdup(orig->name, gfp); + if (!copy->data.name) + goto fail; + } + /* don't dup info */ + switch (orig->class) { + case AA_CLASS_FILE: + if (orig->fs.target) { + copy->data.fs.target = kstrdup(orig->fs.target, gfp); + if (!copy->data.fs.target) + goto fail; + } + break; + case AA_CLASS_MOUNT: + if (orig->mnt.src_name) { + copy->data.mnt.src_name = kstrdup(orig->mnt.src_name, gfp); + if (!copy->data.mnt.src_name) + goto fail; + } + if (orig->mnt.type) { + copy->data.mnt.type = kstrdup(orig->mnt.type, gfp); + if (!copy->data.mnt.type) + goto fail; + } + // copy->mnt.trans; not used atm + if (orig->mnt.data) { + copy->data.mnt.data = kstrdup(orig->mnt.data, gfp); + if (!copy->data.mnt.data) + goto fail; + } + break; + } + + /* now inc counts, and copy data that can't fail */ + copy->data.error = orig->error; + copy->data.type = orig->type; + copy->data.request = orig->request; + copy->data.denied = orig->denied; + copy->data.subj_label = aa_get_label(orig->subj_label); + + if (orig->subj_cred) + copy->data.subj_cred = get_cred(orig->subj_cred); + + switch (orig->class) { + case AA_CLASS_NET: + /* + * peer_sk; + * addr; + */ + fallthrough; + case AA_CLASS_FILE: + copy->data.fs.ouid = orig->fs.ouid; + break; + case AA_CLASS_RLIMITS: + case AA_CLASS_SIGNAL: + case AA_CLASS_POSIX_MQUEUE: + copy->data.peer = aa_get_label(orig->peer); + break; +/* + * case AA_CLASS_IFACE: + * copy->data.iface.profile = aa_get_label(orig.iface.profile); + * break; + */ + }; + + + return copy; +fail: + audit_node_free(copy); + return NULL; +} + +#define __audit_cache_find(C, AD, COND...) \ +({ \ + struct aa_audit_node *__node; \ + list_for_each_entry_rcu(__node, &(C)->head, list, COND) { \ + if (aa_audit_data_cmp(&__node->data, AD) == 0) \ + goto __out_skip; \ + } \ + __node = NULL; \ +__out_skip: \ + __node; \ +}) + +// increments refcount on node +struct aa_audit_node *aa_audit_cache_find(struct aa_audit_cache *cache, + struct apparmor_audit_data *ad) +{ + struct aa_audit_node *node; + + rcu_read_lock(); + node = __audit_cache_find(cache, ad); + aa_get_audit_node(node); + rcu_read_unlock(); + + return node; +} + +/** + * aa_audit_cache_insert - insert an audit node into the cache + * @cache: the cache to insert into + * @node: the audit node to insert into the cache + * + * Returns: refcounted matching node in cache OR @node if @node was inserted. + * + * Increments refcount on node if successfully inserted. Assumes caller + * already has valid ref count. + * Increments refcount on existing node if returned + */ +struct aa_audit_node *aa_audit_cache_insert(struct aa_audit_cache *cache, + struct aa_audit_node *node) + +{ + struct aa_audit_node *tmp; + + spin_lock(&cache->lock); + tmp = __audit_cache_find(cache, &node->data, + spin_is_lock(&cache->lock)); + if (!tmp) { + list_add_rcu(&node->list, &cache->head); + tmp = node; + cache->size++; + } + + aa_get_audit_node(tmp); + /* else raced another insert */ + spin_unlock(&cache->lock); + + return tmp; +} + +void aa_audit_cache_update_ent(struct aa_audit_cache *cache, + struct aa_audit_node *node, + struct apparmor_audit_data *data) +{ + spin_lock(&cache->lock); + node->data.denied |= data->denied; + node->data.request = (node->data.request | data->request) & + ~node->data.denied; + spin_unlock(&cache->lock); +} + +/* assumes rcu callback has already happened and list can not be walked */ +void aa_audit_cache_destroy(struct aa_audit_cache *cache) +{ + struct aa_audit_node *node, *tmp; + + list_for_each_entry_safe(node, tmp, &cache->head, list) { + list_del_init(&node->list); + aa_put_audit_node(node); + } + cache->size = 0; +} diff --git a/security/apparmor/domain.c b/security/apparmor/domain.c index d6958eb00e3045..7cad8b43c3d651 100644 --- a/security/apparmor/domain.c +++ b/security/apparmor/domain.c @@ -706,7 +706,7 @@ static struct aa_label *profile_transition(const struct cred *subj_cred, /* Don't cause error if auditing fails */ (void) aa_audit_file(subj_cred, profile, &perms, OP_EXEC, MAY_EXEC, name, target, new, cond->uid, - info, error); + info, error, false); } if (new) { AA_DEBUG(DEBUG_DOMAIN, "unconfined attached to new label"); @@ -779,9 +779,8 @@ static struct aa_label *profile_transition(const struct cred *subj_cred, } audit: - aa_audit_file(subj_cred, profile, &perms, OP_EXEC, MAY_EXEC, name, - target, new, - cond->uid, info, error); + aa_audit_file(subj_cred, profile, &perms, OP_EXEC, MAY_EXEC, name, target, new, + cond->uid, info, error, true); if (!new || nonewprivs) { aa_put_label(new); return ERR_PTR(error); @@ -860,7 +859,7 @@ static int profile_onexec(const struct cred *subj_cred, audit: return aa_audit_file(subj_cred, profile, &perms, OP_EXEC, AA_MAY_ONEXEC, xname, - NULL, onexec, cond->uid, info, error); + NULL, onexec, cond->uid, info, error, false); } /* ensure none ns domain transitions are correctly applied with onexec */ @@ -916,7 +915,7 @@ static struct aa_label *handle_onexec(const struct cred *subj_cred, AA_MAY_ONEXEC, bprm->filename, NULL, onexec, GLOBAL_ROOT_UID, "failed to build target label", - PTR_ERR(new))); + PTR_ERR(new), false)); return ERR_PTR(error); } @@ -1048,7 +1047,8 @@ int apparmor_bprm_creds_for_exec(struct linux_binprm *bprm) aa_audit_file(current_cred(), profile, &nullperms, OP_EXEC, MAY_EXEC, bprm->filename, NULL, new, - vfsuid_into_kuid(vfsuid), info, error)); + vfsuid_into_kuid(vfsuid), info, error, + false)); aa_put_label(new); goto done; } @@ -1099,7 +1099,7 @@ static struct aa_label *build_change_hat(const struct cred *subj_cred, AA_MAY_CHANGEHAT, name, hat ? hat->base.hname : NULL, hat ? &hat->label : NULL, GLOBAL_ROOT_UID, info, - error); + error, false); if (!hat || (error && error != -ENOENT)) return ERR_PTR(error); /* if hat && error - complain mode, already audited and we adjust for @@ -1219,7 +1219,7 @@ static struct aa_label *change_hat(const struct cred *subj_cred, aa_audit_file(subj_cred, profile, &nullperms, OP_CHANGE_HAT, AA_MAY_CHANGEHAT, name, NULL, NULL, - GLOBAL_ROOT_UID, info, error); + GLOBAL_ROOT_UID, info, error, false); } } mutex_unlock(&ns->lock); @@ -1377,7 +1377,7 @@ int aa_change_hat(const char *hats[], int count, u64 token, int flags) fn_for_each_in_scope(label, profile, aa_audit_file(subj_cred, profile, &perms, OP_CHANGE_HAT, AA_MAY_CHANGEHAT, NULL, NULL, target, - GLOBAL_ROOT_UID, info, error)); + GLOBAL_ROOT_UID, info, error, false)); goto out; } @@ -1401,7 +1401,7 @@ static int change_profile_perms_wrapper(const char *op, const char *name, error = aa_audit_file(subj_cred, profile, perms, op, request, name, NULL, target, GLOBAL_ROOT_UID, info, - error); + error, false); return error; } @@ -1485,7 +1485,8 @@ int aa_change_profile(const char *fqname, int flags) (void) fn_for_each_in_scope(label, profile, aa_audit_file(subj_cred, profile, &perms, op, request, auditname, NULL, target, - GLOBAL_ROOT_UID, stack_msg, 0)); + GLOBAL_ROOT_UID, stack_msg, 0, + false)); perms.audit = 0; } @@ -1610,7 +1611,7 @@ int aa_change_profile(const char *fqname, int flags) aa_audit_file(subj_cred, profile, &perms, op, request, auditname, NULL, new ? new : target, - GLOBAL_ROOT_UID, info, error)); + GLOBAL_ROOT_UID, info, error, false)); out: aa_put_label(new); diff --git a/security/apparmor/file.c b/security/apparmor/file.c index c9d55fe1086f90..80cd3f95e7bb8f 100644 --- a/security/apparmor/file.c +++ b/security/apparmor/file.c @@ -13,14 +13,17 @@ #include #include #include +#include #include "include/af_unix.h" #include "include/apparmor.h" #include "include/audit.h" #include "include/cred.h" #include "include/file.h" +#include "include/ipc.h" #include "include/match.h" #include "include/net.h" +#include "include/notify.h" #include "include/path.h" #include "include/policy.h" #include "include/label.h" @@ -76,6 +79,106 @@ static void file_audit_cb(struct audit_buffer *ab, void *va) } } +// ??? differentiate between +// cached - allow : no audit == 1 +// cached - deny : no audit < 0 +// cached - complain : no audit +// cached - partial : audit missing part : as miss +// not cached = 0 +static int check_cache(struct aa_profile *profile, + struct apparmor_audit_data *ad) +{ + struct aa_audit_node *hit; + + AA_BUG(!profile); + ad->subj_label = &profile->label; // normally set in aa_audit + + /* TODO: need rcu locking around whole check once we allow + * removing node from cache + */ + AA_DEBUG(DEBUG_UPCALL, "cache check: profile '%s', pid %d name:'%s'", + profile->base.hname, current->pid, ad->name); + hit = aa_audit_cache_find(&profile->learning_cache, ad); + if (hit) { + AA_DEBUG(DEBUG_UPCALL, " matched node in audit cache"); + if (ad->request & hit->data.denied) { + /* this request could only partly succeed prompting for + * the part and failing makes no sense + */ + AA_DEBUG(DEBUG_UPCALL, + " hit denied, request: 0x%x by cached deny 0x%x\n", + ad->request, hit->data.denied); + aa_put_audit_node(hit); + return ad->error; + } else if (ad->request & ~hit->data.request) { + /* asking for more perms than is cached */ + AA_DEBUG(DEBUG_UPCALL, + " miss insufficient perms, request: 0x%x cached 0x%x\n", + ad->request, hit->data.request); + /* continue to do prompt */ + } else { + AA_DEBUG(DEBUG_UPCALL, "cache hit->error %d. returning 0", + hit->data.error); + aa_put_audit_node(hit); + /* don't audit: if its in the cache already audited */ + return 0; + } + aa_put_audit_node(hit); + } else { + AA_DEBUG(DEBUG_UPCALL, "cache miss"); + } + + return 1; +} + +// error - immediate return +// - debug message do audit +// caching is handled on listener task side +static int check_user(struct aa_profile *profile, + struct apparmor_audit_data *ad, + struct aa_perms *perms) +{ + struct aa_audit_node *node = NULL; + int err; + + /* assume we are going to dispatch */ + node = aa_dup_audit_data(ad, GFP_KERNEL); + if (!node) { + AA_DEBUG(DEBUG_UPCALL, + "notifcation failed to duplicate with error -ENOMEM\n"); + /* do audit */ + return -ENOMEM; + } + + get_task_struct(current); + node->data.subjtsk = current; + node->data.type = AUDIT_APPARMOR_USER; + node->data.request = ad->request; + node->data.tags = ad->tags; + node->data.denied = ad->request & ~perms->allow; + AA_DEBUG_PROFILE(profile, DEBUG_UPCALL, "attempting upcall\n"); + err = aa_do_notification(APPARMOR_NOTIF_OP, node); + put_task_struct(node->data.subjtsk); + + if (err) { + // do we want to do something special with -ERESTARTSYS + AA_DEBUG(DEBUG_UPCALL, "notifcation failed with error %d\n", + err); + goto return_to_audit; + } + + /* update based on node data for audit */ + perms->deny = node->data.denied; + perms->allow = node->data.request & ~node->data.denied; + ad->request |= node->data.request; + ad->denied = node->data.denied; + ad->error = node->data.error; + +return_to_audit: + aa_put_audit_node(node); + return err; +} + /** * aa_audit_file - handle the auditing of file operations * @subj_cred: cred of the subject @@ -96,9 +199,10 @@ int aa_audit_file(const struct cred *subj_cred, struct aa_profile *profile, struct aa_perms *perms, const char *op, u32 request, const char *name, const char *target, struct aa_label *tlabel, - kuid_t ouid, const char *info, int error) + kuid_t ouid, const char *info, int error, bool prompt) { int type = AUDIT_APPARMOR_AUTO; + int err; DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_TASK, AA_CLASS_FILE, op); ad.subj_cred = subj_cred; @@ -111,6 +215,46 @@ int aa_audit_file(const struct cred *subj_cred, ad.info = info; ad.error = error; ad.common.u.tsk = NULL; + ad.subjtsk = NULL; + + ad.denied = denied_perms(perms, ad.request); + + if (unlikely(ad.error)) { + u32 implicit_deny; + + /* learning cache - not audit dedup yet */ + err = check_cache(profile, &ad); + if (err <= 0) { + AA_DEBUG(DEBUG_UPCALL, "cache early bail %d\n", err); + /* cached */ + return err; + } + implicit_deny = (ad.request & ~perms->allow) & ~perms->deny; + if (USER_MODE(profile)) + perms->prompt = ALL_PERMS_MASK; + + if (ad.request & MAY_EXEC) + AA_DEBUG(DEBUG_UPCALL, + "do prompt %d: exec req 0x%x, allow 0x%x, deny 0x%x, ideny 0x%x, prompt 0x%x", + prompt, ad.request, perms->allow, perms->deny, + implicit_deny, perms->prompt); + + /* don't prompt + * - if explicit deny + * - if implicit_deny is not entirely covered by prompt + * as no point asking user to just deny it anyway. + */ + if (prompt && !(request & perms->deny) && + (perms->prompt & implicit_deny) == implicit_deny) { + err = check_user(profile, &ad, perms); + if (err == -ERESTARTSYS) { + AA_DEBUG(DEBUG_UPCALL, " check user returned -ERESTART_SYS"); + /* are there other errors we should bail on */ + return err; + } + } else + AA_DEBUG_PROFILE(profile, DEBUG_UPCALL, "not prompting prompt %d, requiest 0x%x, deny 0x%x, prompt 0x%x implicit deny 0x%x", prompt, request, perms->deny, perms->prompt, implicit_deny); + } if (likely(!ad.error)) { u32 mask = perms->audit; @@ -142,14 +286,15 @@ int aa_audit_file(const struct cred *subj_cred, return ad.error; } - ad.denied = ad.request & ~perms->allow; - return aa_audit(type, profile, &ad, file_audit_cb); + err = aa_audit(type, profile, &ad, file_audit_cb); + return err; } static int path_name(const char *op, const struct cred *subj_cred, struct aa_label *label, const struct path *path, int flags, char *buffer, - const char **name, struct path_cond *cond, u32 request) + const char **name, struct path_cond *cond, u32 request, + bool prompt) { struct aa_profile *profile; const char *info = NULL; @@ -165,7 +310,8 @@ static int path_name(const char *op, const struct cred *subj_cred, fn_for_each_confined(label, profile, aa_audit_file(subj_cred, profile, &nullperms, op, request, *name, - NULL, NULL, cond->uid, info, error)); + NULL, NULL, cond->uid, info, error, + prompt)); return error; } @@ -226,13 +372,13 @@ aa_state_t aa_str_perms(struct aa_policydb *file_rules, aa_state_t start, int __aa_path_perm(const char *op, const struct cred *subj_cred, struct aa_profile *profile, const char *name, u32 request, struct path_cond *cond, int flags, - struct aa_perms *perms) + struct aa_perms *perms, bool prompt) { struct aa_ruleset *rules = profile->label.rules[0]; int e = 0; if (profile_unconfined(profile) || - ((flags & PATH_SOCK_COND) && !RULE_MEDIATES_v9NET(rules))) + ((flags & PATH_SOCK_COND) && !RULE_MEDIATES_UNIX(rules))) return 0; aa_str_perms(rules->file, rules->file->start[AA_CLASS_FILE], name, cond, perms); @@ -240,7 +386,7 @@ int __aa_path_perm(const char *op, const struct cred *subj_cred, e = -EACCES; return aa_audit_file(subj_cred, profile, perms, op, request, name, NULL, NULL, - cond->uid, NULL, e); + cond->uid, NULL, e, prompt); } @@ -248,7 +394,8 @@ static int profile_path_perm(const char *op, const struct cred *subj_cred, struct aa_profile *profile, const struct path *path, char *buffer, u32 request, struct path_cond *cond, int flags, - struct aa_perms *perms) + struct aa_perms *perms, + u32 *allow, bool prompt) { const char *name = NULL; int error; @@ -258,11 +405,16 @@ static int profile_path_perm(const char *op, const struct cred *subj_cred, error = path_name(op, subj_cred, &profile->label, path, flags | profile->path_flags, buffer, &name, cond, - request); + request, prompt); if (error) return error; - return __aa_path_perm(op, subj_cred, profile, name, request, cond, - flags, perms); + error = __aa_path_perm(op, subj_cred, profile, name, request, cond, + flags, perms, prompt); + /* accumulate intersection of allowed to set on object cache */ + if (!error && allow) + *allow &= perms->allow; + + return error; } /** @@ -274,13 +426,14 @@ static int profile_path_perm(const char *op, const struct cred *subj_cred, * @flags: any additional path flags beyond what the profile specifies * @request: requested permissions * @cond: conditional info for this request (NOT NULL) + * @allow: in/out intersected set of allowed permissions (MAYBE NULL) * * Returns: %0 else error if access denied or other error */ int aa_path_perm(const char *op, const struct cred *subj_cred, struct aa_label *label, const struct path *path, int flags, u32 request, - struct path_cond *cond) + struct path_cond *cond, u32 *allow) { struct aa_perms perms = {}; struct aa_profile *profile; @@ -294,7 +447,8 @@ int aa_path_perm(const char *op, const struct cred *subj_cred, return -ENOMEM; error = fn_for_each_confined(label, profile, profile_path_perm(op, subj_cred, profile, path, buffer, - request, cond, flags, &perms)); + request, cond, flags, &perms, allow, + true)); aa_put_buffer(buffer); @@ -337,14 +491,14 @@ static int profile_path_link(const struct cred *subj_cred, error = path_name(OP_LINK, subj_cred, &profile->label, link, profile->path_flags, - buffer, &lname, cond, AA_MAY_LINK); + buffer, &lname, cond, AA_MAY_LINK, false); if (error) goto audit; /* buffer2 freed below, tname is pointer in buffer2 */ error = path_name(OP_LINK, subj_cred, &profile->label, target, profile->path_flags, - buffer2, &tname, cond, AA_MAY_LINK); + buffer2, &tname, cond, AA_MAY_LINK, false); if (error) goto audit; @@ -403,9 +557,9 @@ static int profile_path_link(const struct cred *subj_cred, error = 0; audit: - return aa_audit_file(subj_cred, - profile, &lperms, OP_LINK, request, lname, tname, - NULL, cond->uid, info, error); + return aa_audit_file(subj_cred, profile, &lperms, OP_LINK, request, + lname, tname, + NULL, cond->uid, info, error, false); } /** @@ -460,7 +614,7 @@ int aa_path_link(const struct cred *subj_cred, } static void update_file_ctx(struct aa_file_ctx *fctx, struct aa_label *label, - u32 request) + u32 request, u32 allow) { struct aa_label *l, *old; @@ -475,42 +629,44 @@ static void update_file_ctx(struct aa_file_ctx *fctx, struct aa_label *label, aa_put_label(old); } else aa_put_label(l); - fctx->allow |= request; + /* TODO: reduction of perms here should result in revalidation + * of components not already checked. Only affects stacking + */ + fctx->allow = allow; } spin_unlock(&fctx->lock); } -static int __file_path_perm(const char *op, const struct cred *subj_cred, - struct aa_label *label, - struct aa_label *flabel, struct file *file, - u32 request, u32 denied, bool in_atomic) +static int __path_perm(const char *op, const struct cred *subj_cred, + struct aa_label *label, struct aa_label *flabel, + struct file *file, u32 request, u32 denied, + struct path_cond *cond, int flags, + bool in_atomic, bool is_mqueue, + struct apparmor_audit_data *ad) { struct aa_profile *profile; struct aa_perms perms = {}; - vfsuid_t vfsuid = i_uid_into_vfsuid(file_mnt_idmap(file), - file_inode(file)); - struct path_cond cond = { - .uid = vfsuid_into_kuid(vfsuid), - .mode = file_inode(file)->i_mode - }; char *buffer; - int flags, error; + u32 allow = ALL_PERMS_MASK; + int error; /* revalidation due to label out of date. No revocation at this time */ if (!denied && aa_label_is_subset(flabel, label)) /* TODO: check for revocation on stale profiles */ return 0; - flags = PATH_DELEGATE_DELETED | (S_ISDIR(cond.mode) ? PATH_IS_DIR : 0); buffer = aa_get_buffer(in_atomic); if (!buffer) return -ENOMEM; /* check every profile in task label not in current cache */ - error = fn_for_each_not_in_set(flabel, label, profile, + error = fn_for_each_not_in_set(flabel, label, profile, is_mqueue ? + aa_profile_mqueue_perm(profile, &file->f_path, + request, buffer, ad) : profile_path_perm(op, subj_cred, profile, &file->f_path, buffer, - request, &cond, flags, &perms)); + request, cond, flags, &perms, + &allow, false)); if (denied && !error) { /* * check every profile in file label that was not tested @@ -521,26 +677,51 @@ static int __file_path_perm(const char *op, const struct cred *subj_cred, * TODO: don't audit here */ if (label == flabel) - error = fn_for_each(label, profile, + error = fn_for_each(label, profile, is_mqueue ? + aa_profile_mqueue_perm(profile, &file->f_path, + request, buffer, ad) : profile_path_perm(op, subj_cred, profile, &file->f_path, - buffer, request, &cond, flags, - &perms)); + buffer, request, cond, flags, + &perms, &allow, false)); else - error = fn_for_each_not_in_set(label, flabel, profile, + error = fn_for_each_not_in_set(label, flabel, profile, is_mqueue ? + aa_profile_mqueue_perm(profile, &file->f_path, + request, buffer, ad) : profile_path_perm(op, subj_cred, profile, &file->f_path, - buffer, request, &cond, flags, - &perms)); + buffer, request, cond, flags, + &perms, &allow, false)); } if (!error) - update_file_ctx(file_ctx(file), label, request); + update_file_ctx(file_ctx(file), label, request, + is_mqueue ? request : allow); aa_put_buffer(buffer); return error; } +static int __file_path_perm(const char *op, const struct cred *subj_cred, + struct aa_label *label, + struct aa_label *flabel, struct file *file, + u32 request, u32 denied, bool in_atomic) +{ + vfsuid_t vfsuid = i_uid_into_vfsuid(file_mnt_idmap(file), + file_inode(file)); + struct path_cond cond = { + .uid = vfsuid_into_kuid(vfsuid), + .mode = file_inode(file)->i_mode + }; + int flags; + + flags = PATH_DELEGATE_DELETED | (S_ISDIR(cond.mode) ? PATH_IS_DIR : 0); + + return __path_perm(op, subj_cred, label, flabel, file, + request, denied, &cond, flags, in_atomic, + false, NULL); +} + static int __file_sock_perm(const char *op, const struct cred *subj_cred, struct aa_label *label, struct aa_label *flabel, struct file *file, @@ -561,11 +742,28 @@ static int __file_sock_perm(const char *op, const struct cred *subj_cred, request, file)); } if (!error) - update_file_ctx(file_ctx(file), label, request); + update_file_ctx(file_ctx(file), label, request, request); return error; } +static int __file_mqueue_perm(const char *op, const struct cred *subj_cred, + struct aa_label *label, + struct aa_label *flabel, struct file *file, + u32 request, u32 denied, bool in_atomic) +{ + DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_NONE, AA_CLASS_POSIX_MQUEUE, op); + + ad.subj_cred = subj_cred; + ad.request = request; + ad.peer = NULL; + ad.mq.ouid = file_inode(file)->i_uid; + + return __path_perm(op, subj_cred, label, flabel, file, + request, denied, NULL, 0, in_atomic, + true, &ad); +} + /* for now separate fn to indicate semantics of the check */ static bool __file_is_delegated(struct aa_label *obj_label) { @@ -657,7 +855,10 @@ int aa_file_perm(const char *op, const struct cred *subj_cred, flabel = aa_get_newest_label(flabel); rcu_read_unlock(); - if (path_mediated_fs(file->f_path.dentry)) + if (is_mqueue_inode(file_inode(file))) { + error = __file_mqueue_perm(op, subj_cred, label, flabel, file, + request, denied, true); + } else if (path_mediated_fs(file->f_path.dentry)) error = __file_path_perm(op, subj_cred, label, flabel, file, request, denied, in_atomic); diff --git a/security/apparmor/include/af_inet.h b/security/apparmor/include/af_inet.h new file mode 100644 index 00000000000000..c0e32ec55c054d --- /dev/null +++ b/security/apparmor/include/af_inet.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AppArmor security module + * + * This file contains AppArmor af_unix fine grained mediation + * + * Copyright 2024 Canonical Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + */ +#ifndef __AA_AF_INET_H + +#include "label.h" + +int aa_inet_peer_perm(const struct cred *subj_cred, + struct aa_label *label, const char *op, u32 request, + struct sock *sk, struct sock *peer_sk, + struct aa_label *peer_label); +int aa_inet_label_sk_perm(const struct cred *subj_cred, + struct aa_label *label, const char *op, u32 request, + struct sock *sk); +int aa_inet_sock_perm(const char *op, u32 request, struct socket *sock); +int aa_inet_create_perm(struct aa_label *label, int family, int type, + int protocol); +int aa_inet_bind_perm(struct socket *sock, struct sockaddr *address, + int addrlen); +int aa_inet_connect_perm(struct socket *sock, struct sockaddr *address, + int addrlen); +int aa_inet_listen_perm(struct socket *sock, int backlog); +int aa_inet_accept_perm(struct socket *sock, struct socket *newsock); +int aa_inet_msg_perm(const char *op, u32 request, struct socket *sock, + struct msghdr *msg, int size); +int aa_inet_opt_perm(const char *op, u32 request, struct socket *sock, int level, + int optname); +int aa_inet_file_perm(const struct cred *subj_cred, + struct aa_label *label, const char *op, u32 request, + struct socket *sock); + +#endif /* __AA_AF_INET_H */ diff --git a/security/apparmor/include/apparmor.h b/security/apparmor/include/apparmor.h index cc6e3df1bc62a4..f044c34ce8fa5a 100644 --- a/security/apparmor/include/apparmor.h +++ b/security/apparmor/include/apparmor.h @@ -20,7 +20,7 @@ #define AA_CLASS_UNKNOWN 1 #define AA_CLASS_FILE 2 #define AA_CLASS_CAP 3 -#define AA_CLASS_DEPRECATED 4 +#define AA_CLASS_NET_COMPAT 4 #define AA_CLASS_RLIMITS 5 #define AA_CLASS_DOMAIN 6 #define AA_CLASS_MOUNT 7 diff --git a/security/apparmor/include/apparmorfs.h b/security/apparmor/include/apparmorfs.h index 33243d11fd1060..9a1ba9bcfbed11 100644 --- a/security/apparmor/include/apparmorfs.h +++ b/security/apparmor/include/apparmorfs.h @@ -15,6 +15,8 @@ extern struct path aa_null; enum aa_sfs_type { AA_SFS_TYPE_BOOLEAN, + // Boolean that gets printed as 0/1 for backwards compatibility + AA_SFS_TYPE_BOOLEAN_INTPRINT, AA_SFS_TYPE_STRING, AA_SFS_TYPE_U64, AA_SFS_TYPE_FOPS, @@ -43,6 +45,10 @@ extern const struct file_operations aa_sfs_seq_file_ops; { .name = (_name), .mode = 0444, \ .v_type = AA_SFS_TYPE_BOOLEAN, .v.boolean = (_value), \ .file_ops = &aa_sfs_seq_file_ops } +#define AA_SFS_FILE_BOOLEAN_INTPRINT(_name, _value) \ + { .name = (_name), .mode = 0444, \ + .v_type = AA_SFS_TYPE_BOOLEAN_INTPRINT, .v.boolean = (_value), \ + .file_ops = &aa_sfs_seq_file_ops } #define AA_SFS_FILE_STRING(_name, _value) \ { .name = (_name), .mode = 0444, \ .v_type = AA_SFS_TYPE_STRING, .v.string = (_value), \ @@ -89,6 +95,7 @@ enum aafs_prof_type { AAFS_PROF_RAW_DATA, AAFS_PROF_RAW_HASH, AAFS_PROF_RAW_ABI, + AAFS_PROF_LEARNING_COUNT, AAFS_PROF_SIZEOF, }; diff --git a/security/apparmor/include/audit.h b/security/apparmor/include/audit.h index aa00b34404f9f9..f4df98be251b0e 100644 --- a/security/apparmor/include/audit.h +++ b/security/apparmor/include/audit.h @@ -19,6 +19,7 @@ #include "file.h" #include "label.h" +#include "notify.h" extern const char *const audit_mode_names[]; #define AUDIT_MAX_INDEX 5 @@ -38,6 +39,7 @@ enum audit_type { AUDIT_APPARMOR_STATUS, AUDIT_APPARMOR_ERROR, AUDIT_APPARMOR_KILL, + AUDIT_APPARMOR_USER, AUDIT_APPARMOR_AUTO }; @@ -58,6 +60,7 @@ enum audit_type { #define OP_CHMOD "chmod" #define OP_CHOWN "chown" #define OP_GETATTR "getattr" +#define OP_SETATTR "setattr" #define OP_OPEN "open" #define OP_FRECEIVE "file_receive" @@ -108,7 +111,9 @@ enum audit_type { #define OP_URING_OVERRIDE "uring_override" #define OP_URING_SQPOLL "uring_sqpoll" +#define AUDIT_TAILGLOB_NAME 1 struct apparmor_audit_data { + u32 flags; /* control flags not part of actual data */ int error; int type; u16 class; @@ -121,6 +126,8 @@ struct apparmor_audit_data { u32 denied; u32 tags; + struct task_struct *subjtsk; + union { /* these entries require a custom callback fn */ struct { @@ -147,6 +154,12 @@ struct apparmor_audit_data { int addrlen; } peer; } net; + struct { + const char *target; + } ns; + struct { + kuid_t ouid; + } mq; }; }; struct { @@ -169,6 +182,44 @@ struct apparmor_audit_data { struct common_audit_data common; }; +struct aa_audit_node { + struct kref count; + struct apparmor_audit_data data; + struct list_head list; + struct aa_knotif knotif; +}; +extern struct kmem_cache *aa_audit_slab; + +static inline struct aa_audit_node *aa_alloc_audit_node(gfp_t gfp) +{ + return kmem_cache_zalloc(aa_audit_slab, gfp); +} + + +struct aa_audit_cache { + spinlock_t lock; + int size; + struct list_head head; +}; + +static inline void aa_audit_cache_init(struct aa_audit_cache *cache) +{ + cache->size = 0; + spin_lock_init(&cache->lock); + INIT_LIST_HEAD(&cache->head); +} + +struct aa_audit_node *aa_audit_cache_find(struct aa_audit_cache *cache, + struct apparmor_audit_data *ad); +struct aa_audit_node *aa_audit_cache_insert(struct aa_audit_cache *cache, + struct aa_audit_node *node); +void aa_audit_cache_update_ent(struct aa_audit_cache *cache, + struct aa_audit_node *node, + struct apparmor_audit_data *data); +void aa_audit_cache_destroy(struct aa_audit_cache *cache); + + + /* macros for dealing with apparmor_audit_data structure */ #define aad(SA) (container_of(SA, struct apparmor_audit_data, common)) #define aad_of_va(VA) aad((struct common_audit_data *)(VA)) @@ -178,6 +229,7 @@ struct apparmor_audit_data { struct apparmor_audit_data NAME = { \ .class = (C), \ .op = (X), \ + .subjtsk = NULL, \ .common.type = (T), \ .common.u.tsk = NULL, \ .common.apparmor_audit_data = &NAME, \ @@ -209,4 +261,27 @@ int aa_audit_rule_init(u32 field, u32 op, char *rulestr, void **vrule, gfp_t gfp int aa_audit_rule_known(struct audit_krule *rule); int aa_audit_rule_match(struct lsm_prop *prop, u32 field, u32 op, void *vrule); + +void aa_audit_node_free_kref(struct kref *kref); +struct aa_audit_node *aa_dup_audit_data(struct apparmor_audit_data *orig, + gfp_t gfp); +long aa_audit_data_cmp(struct apparmor_audit_data *lhs, + struct apparmor_audit_data *rhs); + + +static inline struct aa_audit_node *aa_get_audit_node(struct aa_audit_node *node) +{ + if (node) + kref_get(&(node->count)); + + return node; +} + +static inline void aa_put_audit_node(struct aa_audit_node *node) +{ + if (node) + kref_put(&node->count, aa_audit_node_free_kref); +} + + #endif /* __AA_AUDIT_H */ diff --git a/security/apparmor/include/file.h b/security/apparmor/include/file.h index ef60f99bc5aed1..4e6fb486c56053 100644 --- a/security/apparmor/include/file.h +++ b/security/apparmor/include/file.h @@ -75,7 +75,7 @@ int aa_audit_file(const struct cred *cred, struct aa_profile *profile, struct aa_perms *perms, const char *op, u32 request, const char *name, const char *target, struct aa_label *tlabel, kuid_t ouid, - const char *info, int error); + const char *info, int error, bool prompt); struct aa_perms *aa_lookup_condperms(kuid_t subj_uid, struct aa_policydb *file_rules, @@ -87,10 +87,11 @@ aa_state_t aa_str_perms(struct aa_policydb *file_rules, aa_state_t start, int __aa_path_perm(const char *op, const struct cred *subj_cred, struct aa_profile *profile, const char *name, u32 request, struct path_cond *cond, int flags, - struct aa_perms *perms); + struct aa_perms *perms, bool prompt); int aa_path_perm(const char *op, const struct cred *subj_cred, struct aa_label *label, const struct path *path, - int flags, u32 request, struct path_cond *cond); + int flags, u32 request, struct path_cond *cond, + u32 *allow); int aa_path_link(const struct cred *subj_cred, struct aa_label *label, struct dentry *old_dentry, const struct path *new_dir, diff --git a/security/apparmor/include/inode.h b/security/apparmor/include/inode.h new file mode 100644 index 00000000000000..a9b3e4d6c968bf --- /dev/null +++ b/security/apparmor/include/inode.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AppArmor security module + * + * This file contains AppArmor file mediation function definitions. + * + * Copyright 2022 Canonical Ltd. + */ + +#ifndef __AA_INODE_H +#define __AA_INODE_H + +#include + +#include "lib.h" + +struct aa_inode_sec { + struct inode *inode; /* back pointer to inode object */ + struct aa_label *label; + u16 sclass; /* security class of this object */ + bool initialized; /* initialization flag */ + spinlock_t lock; +}; + +struct aa_superblock_sec { + struct aa_label *label; +}; + +static inline struct aa_inode_sec *apparmor_inode(const struct inode *inode) +{ + if (unlikely(!inode->i_security)) + return NULL; + return inode->i_security + apparmor_blob_sizes.lbs_inode; +} + +static inline struct aa_superblock_sec *apparmor_superblock( + const struct super_block *sb) +{ + return sb->s_security + apparmor_blob_sizes.lbs_superblock; +} + +#endif /* __AA_INODE_H */ diff --git a/security/apparmor/include/ipc.h b/security/apparmor/include/ipc.h index 323dd071afe9c2..72f2a6112892e1 100644 --- a/security/apparmor/include/ipc.h +++ b/security/apparmor/include/ipc.h @@ -11,13 +11,70 @@ #ifndef __AA_IPC_H #define __AA_IPC_H +#include #include +#include "inode.h" +#include "perms.h" #define SIGUNKNOWN 0 #define MAXMAPPED_SIG 35 +struct aa_msg_sec { + struct aa_label *label; +}; + +struct aa_ipc_sec { + struct aa_label *label; +}; + +static inline struct aa_ipc_sec *apparmor_ipc(const struct kern_ipc_perm *ipc) +{ + return ipc->security + apparmor_blob_sizes.lbs_ipc; +} + +static inline struct aa_msg_sec *apparmor_msg_msg(const struct msg_msg *msg_msg) +{ + return msg_msg->security + apparmor_blob_sizes.lbs_msg_msg; +} + + +static inline bool is_mqueue_sb(struct super_block *sb) +{ + if (!sb) + pr_warn("mqueue sb == NULL\n"); + if (!sb && !sb->s_type->name) + pr_warn("mqueue sb name == NULL\n"); + return sb && sb->s_type->name && strcmp(sb->s_type->name, "mqueue") == 0; +} + +static inline bool is_mqueue_inode(struct inode *i) +{ + struct aa_inode_sec *isec; + + if (!i) + return false; + + isec = apparmor_inode(i); + return isec && isec->sclass == AA_CLASS_POSIX_MQUEUE; +} + int aa_may_signal(const struct cred *subj_cred, struct aa_label *sender, const struct cred *target_cred, struct aa_label *target, int sig); +#define AA_AUDIT_POSIX_MQUEUE_MASK (AA_MAY_WRITE | AA_MAY_READ | \ + AA_MAY_CREATE | AA_MAY_DELETE | \ + AA_MAY_OPEN | AA_MAY_SETATTR | \ + AA_MAY_GETATTR) + + +int aa_profile_mqueue_perm(struct aa_profile *profile, + const struct path *path, + u32 request, char *buffer, + struct apparmor_audit_data *ad); + +int aa_mqueue_perm(const char *op, const struct cred *subj_cred, + struct aa_label *label, + const struct path *path, u32 request); + #endif /* __AA_IPC_H */ diff --git a/security/apparmor/include/label.h b/security/apparmor/include/label.h index b5a722a47fd2c8..da331076b40ede 100644 --- a/security/apparmor/include/label.h +++ b/security/apparmor/include/label.h @@ -91,7 +91,7 @@ enum label_flags { FLAG_PROFILE = 0x200, /* label is a profile */ FLAG_EXPLICIT = 0x400, /* explicit static label */ FLAG_STALE = 0x800, /* replaced/removed */ - FLAG_RENAMED = 0x1000, /* label has renaming in it */ + FLAG_INTERRUPTIBLE = 0x1000, FLAG_REVOKED = 0x2000, /* label has revocation in it */ FLAG_DEBUG1 = 0x4000, FLAG_DEBUG2 = 0x8000, @@ -258,6 +258,7 @@ static inline bool label_mediates_safe(struct aa_label *L, unsigned char C) return label_mediates(L, C); } +int aa_label_cmp(struct aa_label *a, struct aa_label *b); void aa_labelset_destroy(struct aa_labelset *ls); void aa_labelset_init(struct aa_labelset *ls); void __aa_labelset_update_subtree(struct aa_ns *ns); diff --git a/security/apparmor/include/lib.h b/security/apparmor/include/lib.h index e3c8cb044a90f3..e18ee4f9bdc316 100644 --- a/security/apparmor/include/lib.h +++ b/security/apparmor/include/lib.h @@ -18,12 +18,17 @@ extern struct aa_dfa *stacksplitdfa; +#define list_add_entry(ent, list, member) list_add(&(ent)->member, (list)) +#define list_add_tail_entry(ent, list, member) list_add_tail(&(ent)->member, (list)) + /* * split individual debug cases out in preparation for finer grained * debug controls in the future. */ #define dbg_printk(__fmt, __args...) pr_debug(__fmt, ##__args) +#define DEBUG_PROMPT 2 + #define DEBUG_NONE 0 #define DEBUG_LABEL_ABS_ROOT 1 #define DEBUG_LABEL 2 @@ -32,8 +37,9 @@ extern struct aa_dfa *stacksplitdfa; #define DEBUG_INTERFACE 0x10 #define DEBUG_UNPACK 0x20 #define DEBUG_TAGS 0x40 +#define DEBUG_UPCALL 0x80 -#define DEBUG_ALL 0x7f /* update if new DEBUG_X added */ +#define DEBUG_ALL 0xff /* update if new DEBUG_X added */ #define DEBUG_PARSE_ERROR (-1) #define DEBUG_ON (aa_g_debug != DEBUG_NONE) @@ -42,8 +48,9 @@ extern struct aa_dfa *stacksplitdfa; #define AA_DEBUG(opt, fmt, args...) \ do { \ if (aa_g_debug & opt) \ - pr_warn_ratelimited("%s: " fmt, __func__, ##args); \ + pr_warn("%s: " fmt, __func__, ##args); \ } while (0) +#define AA_DEBUG_ON(C, args...) do { if (C) AA_DEBUG(args); } while (0) #define AA_DEBUG_LABEL(LAB, X, fmt, args...) \ do { \ if ((LAB)->flags & FLAG_DEBUG1) \ @@ -143,6 +150,14 @@ static inline aa_state_t aa_dfa_null_transition(struct aa_dfa *dfa, return aa_dfa_next(dfa, start, 0); } +static inline aa_state_t aa_dfa_match_u16(struct aa_dfa *dfa, aa_state_t state, + u16 data) +{ + __be16 buffer = cpu_to_be16(data); + + return aa_dfa_match_len(dfa, state, (char *) &buffer, 2); +} + static inline bool path_mediated_fs(struct dentry *dentry) { return !(dentry->d_sb->s_flags & SB_NOUSER); diff --git a/security/apparmor/include/net.h b/security/apparmor/include/net.h index 0d0b0ce4272387..93fce294472d4a 100644 --- a/security/apparmor/include/net.h +++ b/security/apparmor/include/net.h @@ -52,6 +52,11 @@ struct aa_sk_ctx { struct aa_label __rcu *peer_lastupdate; /* ptr cmp only, no deref */ }; +static inline bool aa_secmark(void) +{ + return apparmor_blob_sizes.lbs_secmark; +} + static inline struct aa_sk_ctx *aa_sock(const struct sock *sk) { return sk->sk_security + apparmor_blob_sizes.lbs_sock; @@ -75,6 +80,18 @@ static inline struct aa_sk_ctx *aa_sock(const struct sock *sk) (SK)->sk_protocol) + +/* struct aa_net - network confinement data + * @allow: basic network families permissions + * @audit: which network permissions to force audit + * @quiet: which network permissions to quiet rejects + */ +struct aa_net_compat { + u16 allow[AF_MAX]; + u16 audit[AF_MAX]; + u16 quiet[AF_MAX]; +}; + struct aa_secmark { u8 audit; u8 deny; @@ -83,6 +100,7 @@ struct aa_secmark { }; extern struct aa_sfs_entry aa_sfs_entry_network[]; +extern struct aa_sfs_entry aa_sfs_entry_network_compat[]; extern struct aa_sfs_entry aa_sfs_entry_networkv9[]; int aa_do_perms(struct aa_profile *profile, struct aa_policydb *policy, @@ -93,19 +111,18 @@ aa_state_t aa_match_to_prot(struct aa_policydb *policy, aa_state_t state, u32 request, u16 af, int type, int protocol, struct aa_perms **p, const char **info); void audit_net_cb(struct audit_buffer *ab, void *va); -int aa_profile_af_perm(struct aa_profile *profile, - struct apparmor_audit_data *ad, - u32 request, u16 family, int type, int protocol); +int aa_profile_af_compat_perm(struct aa_profile *profile, + struct apparmor_audit_data *ad, + u32 request, u16 family, int type); int aa_af_perm(const struct cred *subj_cred, struct aa_label *label, const char *op, u32 request, u16 family, int type, int protocol); static inline int aa_profile_af_sk_perm(struct aa_profile *profile, struct apparmor_audit_data *ad, - u32 request, - struct sock *sk) + u32 request, struct sock *sk) { - return aa_profile_af_perm(profile, ad, request, sk->sk_family, - sk->sk_type, sk->sk_protocol); + return aa_profile_af_compat_perm(profile, ad, request, sk->sk_family, + sk->sk_type); } int aa_sk_perm(const char *op, u32 request, struct sock *sk); diff --git a/security/apparmor/include/notify.h b/security/apparmor/include/notify.h new file mode 100644 index 00000000000000..8fc8207e963e67 --- /dev/null +++ b/security/apparmor/include/notify.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AppArmor security module + * + * This file contains AppArmor notifications function definitions. + * + * Copyright 2019 Canonical Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + */ + +#ifndef __AA_NOTIFY_H +#define __AA_NOTIFY_H + +#include +#include +#include +#include +#include +#include + +#include + +#include "label.h" +#include "match.h" + +struct aa_ns; +struct aa_audit_node; +struct apparmor_audit_data; + +struct aa_listener { + struct kref count; + spinlock_t lock; + wait_queue_head_t wait; + struct list_head ns_proxies; /* aa_listener_proxy */ + struct list_head notifications; /* aa_audit_proxy */ + struct list_head pending; /* aa_audit_proxy */ + struct aa_ns *ns; /* counted - ns of listener */ + struct aa_dfa *filter; + struct aa_label *label; + u64 listener_id; /* unique id of listener */ + u64 last_id; + u32 mask; + u32 flags; + u16 version; +}; + +struct aa_listener_proxy { + struct aa_ns *ns; /* counted - ns listening to */ + struct aa_listener *listener; + struct list_head llist; + struct list_head nslist; + struct delayed_work work; +}; + +#define KNOTIF_ON_LIST 1 +#define KNOTIF_PULSE +#define KNOTIF_PENDING +#define KNOTIF_CANCELLED +#define KNOTIF_RESEND 2 + +/* need to split knofif into audit_proxy + * prompt notifications only go to first taker so no need for completion + * in the proxy, it increases size of proxy in non-prompt case + */ +struct aa_knotif { + struct apparmor_audit_data *ad; /* counted */ + struct list_head list; + struct completion ready; + u64 id; + u16 ntype; + u16 flags; +}; + +void aa_free_listener_proxy(struct aa_listener_proxy *proxy); +struct aa_listener_proxy *aa_new_listener_proxy(struct aa_listener *listener, + struct aa_ns *ns); +void aa_delayed_free_listener_proxy(struct aa_listener_proxy *proxy); +struct aa_listener *aa_new_listener(struct aa_ns *ns, gfp_t gfp); +struct aa_knotif *__aa_find_notif(struct aa_listener *listener, u64 id); +int aa_do_notification(u16 ntype, struct aa_audit_node *node); + +long aa_listener_unotif_recv(struct aa_listener *listener, void __user *buf, + u16 max_size, u16 version); +long aa_listener_unotif_response(struct aa_listener *listener, + union apparmor_notif_resp *uresp, + u16 size); +long aa_register_listener_id(struct aa_listener *listener, u64 *id, + struct aa_listener **found); +long aa_listener_unotif_resend(struct aa_listener *listener, u32 *ready, + u32 *pending); + +void aa_listener_kref(struct kref *kref); +void aa_listener_fskref(struct kref *kref); + +static inline struct aa_listener *aa_get_listener(struct aa_listener *listener) +{ + if (listener) + kref_get(&(listener->count)); + + return listener; +} + +static inline void aa_put_listener(struct aa_listener *listener) +{ + if (listener) + kref_put(&listener->count, aa_listener_kref); +} + +#endif /* __AA_NOTIFY_H */ diff --git a/security/apparmor/include/path.h b/security/apparmor/include/path.h index 8bb915d48dc7f4..c67d991f51626d 100644 --- a/security/apparmor/include/path.h +++ b/security/apparmor/include/path.h @@ -17,6 +17,7 @@ enum path_flags { PATH_CONNECT_PATH = 0x4, /* connect disconnected paths to / */ PATH_CHROOT_REL = 0x8, /* do path lookup relative to chroot */ PATH_CHROOT_NSCONNECT = 0x10, /* connect paths that are at ns root */ + PATH_CONNECT_IPC_PATH = 0x20, /* connect IPC disconnected paths to / */ PATH_DELEGATE_DELETED = 0x10000, /* delegate deleted files */ PATH_MEDIATE_DELETED = 0x20000, /* mediate deleted paths */ @@ -25,6 +26,8 @@ enum path_flags { int aa_path_name(const struct path *path, int flags, char *buffer, const char **name, const char **info, const char *disconnected); +int aa_disconnect(const struct path *path, char *buf, char **name, + int flags, int flags_match, const char *disconnected); #define IN_ATOMIC true char *aa_get_buffer(bool in_atomic); diff --git a/security/apparmor/include/perms.h b/security/apparmor/include/perms.h index 37a3781b99a083..d0e6d5d9bfea8f 100644 --- a/security/apparmor/include/perms.h +++ b/security/apparmor/include/perms.h @@ -204,6 +204,9 @@ void aa_perm_mask_to_str(char *str, size_t str_size, const char *chrs, u32 mask); void aa_audit_perm_names(struct audit_buffer *ab, const char * const *names, u32 mask); +void aa_audit_perms(struct audit_buffer *ab, struct apparmor_audit_data *ad, + const char *chrs, u32 chrsmask, const char * const *names, + u32 namesmask); void aa_audit_perm_mask(struct audit_buffer *ab, u32 mask, const char *chrs, u32 chrsmask, const char * const *names, u32 namesmask); void aa_apply_modes_to_perms(struct aa_profile *profile, @@ -213,6 +216,11 @@ void aa_perms_accum_raw(struct aa_perms *accum, struct aa_perms *addend); void aa_profile_match_label(struct aa_profile *profile, struct aa_ruleset *rules, struct aa_label *label, int type, u32 request, struct aa_perms *perms); +static inline u32 denied_perms(struct aa_perms *perms, u32 request) +{ + return request & (~perms->allow | perms->deny); +} + int aa_check_perms(struct aa_profile *profile, struct aa_perms *perms, u32 request, struct apparmor_audit_data *ad, void (*cb)(struct audit_buffer *, void *)); diff --git a/security/apparmor/include/policy.h b/security/apparmor/include/policy.h index 3895f8774a3f93..a1610cffdda824 100644 --- a/security/apparmor/include/policy.h +++ b/security/apparmor/include/policy.h @@ -34,7 +34,11 @@ struct aa_ns; extern int unprivileged_userns_apparmor_policy; +extern int aa_unprivileged_userns_restricted; +extern int aa_unprivileged_userns_restricted_force; +extern int aa_unprivileged_userns_restricted_complain; extern int aa_unprivileged_unconfined_restricted; +extern int aa_unprivileged_uring_restricted; extern const char *const aa_profile_mode_names[]; #define APPARMOR_MODE_NAMES_MAX_INDEX 4 @@ -202,6 +206,9 @@ struct aa_ruleset { struct aa_secmark *secmark; }; +void aa_free_ruleset(struct aa_ruleset *rules); +struct aa_ruleset *aa_new_ruleset(gfp_t gfp); +struct aa_ruleset *aa_clone_ruleset(struct aa_ruleset *rules); /* struct aa_attachment - data and rules for a profiles attachment * @list: @@ -232,6 +239,7 @@ struct aa_attachment { * @disconnected: what to prepend if attach_disconnected is specified * @attach: attachment rules for the profile * @rules: rules to be enforced + * @net_compat: v2 compat network controls for the profile * * learning_cache: the accesses learned in complain mode * raw_data: rawdata of the loaded profile policy @@ -267,8 +275,12 @@ struct aa_profile { u32 path_flags; int signal; const char *disconnected; + const char *disconnected_ipc; struct aa_attachment attach; + struct aa_net_compat *net_compat; + + struct aa_audit_cache learning_cache; struct aa_loaddata *rawdata; unsigned char *hash; @@ -351,7 +363,23 @@ static inline aa_state_t RULE_MEDIATES_NET(struct aa_ruleset *rules) /* fallback and check v7/8 if v9 is NOT mediated */ if (!state) state = RULE_MEDIATES(rules, AA_CLASS_NET); + return state; +} + +static inline aa_state_t RULE_MEDIATES_UNIX(struct aa_ruleset *rules) +{ + /* can not use RULE_MEDIATE_v9AF here, because AF match fail + * can not be distiguished from class match fail, and we only + * fallback to checking older class on class match failure + */ + aa_state_t state = RULE_MEDIATES(rules, AA_CLASS_NETV9); + /* fallback and check v7/8 if v9 is NOT mediated */ + if (!state) { + state = RULE_MEDIATES(rules, AA_CLASS_NET); + if (!state) + state = RULE_MEDIATES(rules, AA_CLASS_NET_COMPAT); + } return state; } diff --git a/security/apparmor/include/policy_ns.h b/security/apparmor/include/policy_ns.h index cc6e8415181209..bd30b39f31efa0 100644 --- a/security/apparmor/include/policy_ns.h +++ b/security/apparmor/include/policy_ns.h @@ -12,6 +12,7 @@ #define __AA_NAMESPACE_H #include +#include #include "apparmor.h" #include "apparmorfs.h" @@ -44,6 +45,12 @@ struct aa_ns_acct { * @uniq_null: uniq value used for null learning profiles * @uniq_id: a unique id count for the profiles in the namespace * @level: level of ns within the tree hierarchy + * @revision: policy revision for this ns + * @wait: waitq for tasks waiting on revision changes + * @listener_lock: lock for listeners + * @listeners: notification listeners' proxies list + * @labels: all the labels associated with this ns + * @rawdata_list: raw policy data for policy * @dents: dentries for the namespaces file entries in apparmorfs * * An aa_ns defines the set profiles that are searched to determine which @@ -67,9 +74,13 @@ struct aa_ns { atomic_t uniq_null; long uniq_id; int level; + long revision; wait_queue_head_t wait; + spinlock_t listener_lock; + struct list_head listeners; + struct aa_labelset labels; struct list_head rawdata_list; diff --git a/security/apparmor/include/policy_unpack.h b/security/apparmor/include/policy_unpack.h index 4ea9b6479a3ed7..b72af3e9605045 100644 --- a/security/apparmor/include/policy_unpack.h +++ b/security/apparmor/include/policy_unpack.h @@ -31,6 +31,7 @@ struct aa_load_ent *aa_load_ent_alloc(void); #define PACKED_FLAG_HAT 1 #define PACKED_FLAG_DEBUG1 2 #define PACKED_FLAG_DEBUG2 4 +#define PACKED_FLAG_INTERRUPTIBLE 8 #define PACKED_MODE_ENFORCE 0 #define PACKED_MODE_COMPLAIN 1 diff --git a/security/apparmor/include/task.h b/security/apparmor/include/task.h index b1aaaf60fa8b84..ff8bed8f60b274 100644 --- a/security/apparmor/include/task.h +++ b/security/apparmor/include/task.h @@ -99,7 +99,8 @@ int aa_may_ptrace(const struct cred *tracer_cred, struct aa_label *tracer, #define AA_USERNS_CREATE 8 -int aa_profile_ns_perm(struct aa_profile *profile, - struct apparmor_audit_data *ad, u32 request); +struct aa_label *aa_profile_ns_perm(struct aa_profile *profile, + struct apparmor_audit_data *ad, + u32 request); #endif /* __AA_TASK_H */ diff --git a/security/apparmor/ipc.c b/security/apparmor/ipc.c index df5712cea6855d..bdd2cc1899298f 100644 --- a/security/apparmor/ipc.c +++ b/security/apparmor/ipc.c @@ -9,10 +9,13 @@ */ #include +#include +#include #include "include/audit.h" #include "include/capability.h" #include "include/cred.h" +#include "include/path.h" #include "include/policy.h" #include "include/ipc.h" #include "include/sig_names.h" @@ -114,3 +117,127 @@ int aa_may_signal(const struct cred *subj_cred, struct aa_label *sender, profile_signal_perm(target_cred, profile, sender, MAY_READ, &ad)); } + + +static void audit_mqueue_cb(struct audit_buffer *ab, void *va) +{ + struct apparmor_audit_data *ad = aad_of_va(va); + + aa_audit_perms(ab, ad, NULL, 0, NULL, AA_AUDIT_POSIX_MQUEUE_MASK); + + /* move class into generic audit framse work */ + audit_log_format(ab, " class=\"posix_mqueue\""); + if (ad->request & AA_AUDIT_FILE_MASK) { + audit_log_format(ab, " fsuid=%u", + from_kuid(&init_user_ns, ad->subj_cred->fsuid)); + audit_log_format(ab, " ouid=%u", + from_kuid(&init_user_ns, ad->mq.ouid)); + } + if (ad->peer) { + audit_log_format(ab, " olabel="); + aa_label_xaudit(ab, labels_ns(ad->subj_label), ad->peer, + FLAGS_NONE, GFP_ATOMIC); + } +} + +int aa_profile_mqueue_perm(struct aa_profile *profile, const struct path *path, + u32 request, char *buffer, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms perms = { }; + unsigned int state; + char *name; + struct aa_inode_sec *isec; + + if (profile_unconfined(profile) || + !RULE_MEDIATES(rules, AA_CLASS_POSIX_MQUEUE)) + return 0; + + ad->subj_label = &profile->label; + + name = dentry_path_raw(path->dentry, buffer, aa_g_path_max); + if (IS_ERR(name)) + return PTR_ERR(name); + + if (path->mnt != current->nsproxy->ipc_ns->mq_mnt) { + /* check if enforced by userspace? */ + if (aa_disconnect(path, buffer, &name, profile->path_flags, + PATH_CONNECT_PATH | PATH_CONNECT_IPC_PATH, + profile->disconnected_ipc)) { + ad->info = "Failed name lookup - disconnected IPC path"; + return aa_check_perms(profile, &perms, request, + ad, audit_mqueue_cb); + } + } + + ad->name = name; + + state = aa_dfa_match(rules->policy->dfa, + rules->policy->start[AA_CLASS_POSIX_MQUEUE], + name); + perms = *aa_lookup_perms(rules->policy, state); + aa_apply_modes_to_perms(profile, &perms); + if (!denied_perms(&perms, request)) { + /* early bailout sufficient perms no need to do further + * checks + */ + return aa_check_perms(profile, &perms, request, ad, + audit_mqueue_cb); + } + /* continue check to see if we have label perms */ + if (!(request & AA_MAY_CREATE)) { + if (!d_backing_inode(path->dentry)) { + pr_warn("apparmor: could not get inode\n"); + goto err; + } + isec = apparmor_inode(d_backing_inode(path->dentry)); + if (!isec) { + pr_warn("apparmor: could not get inode sec context\n"); + goto err; + } + ad->peer = isec->label; + state = aa_dfa_null_transition(rules->policy->dfa, state); + aa_label_match(profile, rules, isec->label, state, false, request, &perms); + aa_apply_modes_to_perms(profile, &perms); + } +err: + return aa_check_perms(profile, &perms, request, ad, audit_mqueue_cb); +} + +/* mqueue - no label caching test */ +int aa_mqueue_perm(const char *op, const struct cred *subj_cred, + struct aa_label *label, + const struct path *path, u32 request) +{ + struct aa_profile *profile; + char *buffer; + int error; + DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_NONE, AA_CLASS_POSIX_MQUEUE, op); + + // do we need delegate deleted with mqueues? probably + //flags |= PATH_DELEGATE_DELETED; + + /* sadly due to rcu walk hairiness, we use dentry_path_raw instead + * of just accessing the name directly, which means we need to + * do the whole buffer allocation mess + */ + buffer = aa_get_buffer(false); + if (!buffer) + return -ENOMEM; + + /* audit fields that won't change during iteration */ + ad.subj_cred = subj_cred; + ad.request = request; + ad.peer = NULL; + ad.mq.ouid = d_backing_inode(path->dentry) ? + d_backing_inode(path->dentry)->i_uid : + subj_cred->fsuid; + + error = fn_for_each_confined(label, profile, + aa_profile_mqueue_perm(profile, path, request, + buffer, &ad)); + aa_put_buffer(buffer); + + return error; +} diff --git a/security/apparmor/label.c b/security/apparmor/label.c index 3fd384d8c41aaf..cba3b0dd8d0e08 100644 --- a/security/apparmor/label.c +++ b/security/apparmor/label.c @@ -465,7 +465,7 @@ struct aa_label *aa_label_alloc(int size, struct aa_proxy *proxy, gfp_t gfp) /** - * label_cmp - label comparison for set ordering + * aa_label_cmp - label comparison for set ordering * @a: label to compare (NOT NULL) * @b: label to compare (NOT NULL) * @@ -473,7 +473,7 @@ struct aa_label *aa_label_alloc(int size, struct aa_proxy *proxy, gfp_t gfp) * ==0 if a == b * >0 if a > b */ -static int label_cmp(struct aa_label *a, struct aa_label *b) +int aa_label_cmp(struct aa_label *a, struct aa_label *b) { AA_BUG(!b); @@ -688,7 +688,7 @@ static struct aa_label *__label_insert(struct aa_labelset *ls, new = &ls->root.rb_node; while (*new) { struct aa_label *this = rb_entry(*new, struct aa_label, node); - int result = label_cmp(label, this); + int result = aa_label_cmp(label, this); parent = *new; if (result == 0) { diff --git a/security/apparmor/lib.c b/security/apparmor/lib.c index e41ff57798b25e..8540d211c11674 100644 --- a/security/apparmor/lib.c +++ b/security/apparmor/lib.c @@ -46,6 +46,7 @@ static struct val_table_ent debug_values_table[] = { { "interface", DEBUG_INTERFACE }, { "unpack", DEBUG_UNPACK }, { "tags", DEBUG_TAGS }, + { "upcall", DEBUG_UPCALL }, { NULL, 0 } }; @@ -250,7 +251,7 @@ void aa_str_kref(struct kref *kref) const char aa_file_perm_chrs[] = "xwracd km l "; -const char *aa_file_perm_names[] = { +static const char * const aa_base_perm_names[] = { "exec", "write", "read", @@ -340,6 +341,10 @@ void aa_audit_perm_mask(struct audit_buffer *ab, u32 mask, const char *chrs, { char str[33]; + if (!chrs) + chrs = aa_file_perm_chrs; + if (!names) + names = aa_base_perm_names; audit_log_format(ab, "\""); if ((mask & chrsmask) && chrs) { aa_perm_mask_to_str(str, sizeof(str), chrs, mask & chrsmask); @@ -353,6 +358,22 @@ void aa_audit_perm_mask(struct audit_buffer *ab, u32 mask, const char *chrs, audit_log_format(ab, "\""); } +void aa_audit_perms(struct audit_buffer *ab, struct apparmor_audit_data *ad, + const char *chrs, u32 chrsmask, const char * const *names, + u32 namesmask) +{ + if (ad->request) { + audit_log_format(ab, " requested="); + aa_audit_perm_mask(ab, ad->request, chrs, chrsmask, + names, namesmask); + } + if (ad->denied) { + audit_log_format(ab, " denied="); + aa_audit_perm_mask(ab, ad->denied, chrs, chrsmask, + names, namesmask); + } +} + /** * aa_apply_modes_to_perms - apply namespace and profile flags to perms * @profile: that perms where computed from @@ -422,7 +443,7 @@ int aa_check_perms(struct aa_profile *profile, struct aa_perms *perms, void (*cb)(struct audit_buffer *, void *)) { int type, error; - u32 denied = request & (~perms->allow | perms->deny); + u32 denied = denied_perms(perms, request); if (likely(!denied)) { /* mask off perms that are not being force audited */ @@ -451,6 +472,7 @@ int aa_check_perms(struct aa_profile *profile, struct aa_perms *perms, } if (ad) { + // do_notification() ad->subj_label = &profile->label; ad->request = request; ad->denied = denied; diff --git a/security/apparmor/lsm.c b/security/apparmor/lsm.c index 88d12e89d115dd..0b791baef33b4a 100644 --- a/security/apparmor/lsm.c +++ b/security/apparmor/lsm.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include #include @@ -28,6 +30,7 @@ #include #include "include/af_unix.h" +#include "include/af_inet.h" #include "include/apparmor.h" #include "include/apparmorfs.h" #include "include/audit.h" @@ -35,6 +38,7 @@ #include "include/cred.h" #include "include/crypto.h" #include "include/file.h" +#include "include/inode.h" #include "include/ipc.h" #include "include/net.h" #include "include/path.h" @@ -67,6 +71,13 @@ static LIST_HEAD(aa_global_buffers); static DEFINE_SPINLOCK(aa_buffers_lock); static DEFINE_PER_CPU(struct aa_local_cache, aa_local_buffers); +struct kmem_cache *aa_audit_slab; + +static bool is_mqueue_dentry(struct dentry *dentry) +{ + return dentry && is_mqueue_inode(d_backing_inode(dentry)); +} + /* * LSM hook functions */ @@ -227,7 +238,7 @@ static int common_perm(const char *op, const struct path *path, u32 mask, label = __begin_current_label_crit_section(&needput); if (!unconfined(label)) error = aa_path_perm(op, current_cred(), label, path, 0, mask, - cond); + cond, NULL); __end_current_label_crit_section(label, needput); return error; @@ -417,12 +428,12 @@ static int apparmor_path_rename(const struct path *old_dir, struct dentry *old_d label, &new_path, 0, MAY_READ | AA_MAY_GETATTR | MAY_WRITE | AA_MAY_SETATTR | AA_MAY_DELETE, - &cond_exchange); + &cond_exchange, NULL); if (!error) error = aa_path_perm(OP_RENAME_DEST, current_cred(), label, &old_path, 0, MAY_WRITE | AA_MAY_SETATTR | - AA_MAY_CREATE, &cond_exchange); + AA_MAY_CREATE, &cond_exchange, NULL); } if (!error) @@ -430,12 +441,12 @@ static int apparmor_path_rename(const struct path *old_dir, struct dentry *old_d label, &old_path, 0, MAY_READ | AA_MAY_GETATTR | MAY_WRITE | AA_MAY_SETATTR | AA_MAY_DELETE, - &cond); + &cond, NULL); if (!error) error = aa_path_perm(OP_RENAME_DEST, current_cred(), label, &new_path, 0, MAY_WRITE | AA_MAY_SETATTR | - AA_MAY_CREATE, &cond); + AA_MAY_CREATE, &cond, NULL); } end_current_label_crit_section(label); @@ -453,11 +464,162 @@ static int apparmor_path_chown(const struct path *path, kuid_t uid, kgid_t gid) return common_perm_cond(OP_CHOWN, path, AA_MAY_CHOWN); } +static int common_mqueue_path_perm(const char *op, u32 request, + const struct path *path) +{ + struct aa_label *label; + int error = 0; + + label = begin_current_label_crit_section(); + if (!unconfined(label)) + error = aa_mqueue_perm(op, current_cred(), label, path, + request); + + end_current_label_crit_section(label); + + return error; +} + static int apparmor_inode_getattr(const struct path *path) { + if (is_mqueue_dentry(path->dentry)) + /* TODO: fn() for d_parent */ + return common_mqueue_path_perm(OP_GETATTR, AA_MAY_GETATTR, path); + return common_perm_cond(OP_GETATTR, path, AA_MAY_GETATTR); } +/* inode security operations */ + +/* alloced by infrastructure */ +static int apparmor_inode_alloc_security(struct inode *inode) +{ + struct aa_inode_sec *isec = apparmor_inode(inode); + + spin_lock_init(&isec->lock); + isec->inode = inode; + isec->label = NULL; + isec->sclass = 0; + isec->initialized = false; + + return 0; +} + +/* freed by infrastructure */ +static void apparmor_inode_free_security(struct inode *inode) +{ + struct aa_inode_sec *isec = apparmor_inode(inode); + + if (unlikely(!isec)) + return; + + aa_put_label(isec->label); +} + +static int inode_init_with_dentry(struct inode *inode, struct dentry *dentry) +{ + struct aa_inode_sec *isec = apparmor_inode(inode); + + if (isec->initialized) + return 0; + spin_lock(&isec->lock); + /* recheck under lock */ + if (isec->initialized) + goto unlock; + + if (is_mqueue_sb(inode->i_sb)) { + /* only initialize based on implied label atm */ + isec->label = aa_get_current_label(); + isec->sclass = AA_CLASS_POSIX_MQUEUE; + isec->initialized = true; + } + +unlock: + spin_unlock(&isec->lock); + + return 0; +} + +static int apparmor_inode_init_security(struct inode *inode, struct inode *dir, + const struct qstr *qstr, + struct xattr *xattrs, int *xattr_count) +{ + int error; + + error = inode_init_with_dentry(inode, NULL); + if (error) + return error; + + /* we aren't setting xattrs yet so -EOPNOTSUPP indicates + * that, not an error + */ + return -EOPNOTSUPP; +} + +static void apparmor_d_instantiate(struct dentry *dentry, struct inode *inode) +{ + if (inode) + inode_init_with_dentry(inode, dentry); +} + +static int apparmor_inode_create(struct inode *dir, struct dentry *dentry, + umode_t mode) +{ + struct aa_label *label; + int error = 0; + + label = begin_current_label_crit_section(); + if (!unconfined(label)) { + struct path path = { + .dentry = dentry, + .mnt = current->nsproxy->ipc_ns->mq_mnt, + }; + if (is_mqueue_inode(dir)) + error = aa_mqueue_perm(OP_CREATE, current_cred(), + label, &path, AA_MAY_CREATE); + } + end_current_label_crit_section(label); + + return error; +} + +static int common_mqueue_perm(const char *op, u32 request, struct inode *dir, struct dentry *dentry) +{ + /* can't directly determine ipc ns, but know for mqueues dir is mnt_root */ + bool isdir = d_inode(current->nsproxy->ipc_ns->mq_mnt->mnt_root) == dir; + struct path path = { + .dentry = dentry, + .mnt = isdir ? current->nsproxy->ipc_ns->mq_mnt : NULL, + }; + + if (dir != d_inode(current->nsproxy->ipc_ns->mq_mnt->mnt_root)) + pr_warn("apparmor: unlink dir != mnt_root - disconnected"); + + return common_mqueue_path_perm(op, request, &path); +} + +static int apparmor_inode_unlink(struct inode *dir, struct dentry *dentry) +{ + int error = 0; + + if (is_mqueue_dentry(dentry)) + error = common_mqueue_perm(OP_UNLINK, AA_MAY_DELETE, dir, dentry); + + return error; +} + +static int apparmor_inode_setattr(struct mnt_idmap *idmap, + struct dentry *dentry, struct iattr *iattr) +{ + /* TODO: extend to support iattr as a parameter */ + if (is_mqueue_dentry(dentry)) + /* TODO: fn() for d_parent */ + return common_mqueue_perm(OP_SETATTR, AA_MAY_SETATTR, + d_backing_inode(dentry->d_parent), dentry); + + return 0; +} + static int apparmor_file_open(struct file *file) { struct aa_file_ctx *fctx = file_ctx(file); @@ -485,17 +647,28 @@ static int apparmor_file_open(struct file *file) struct mnt_idmap *idmap = file_mnt_idmap(file); struct inode *inode = file_inode(file); vfsuid_t vfsuid; + u32 allow; struct path_cond cond = { .mode = inode->i_mode, }; vfsuid = i_uid_into_vfsuid(idmap, inode); cond.uid = vfsuid_into_kuid(vfsuid); - error = aa_path_perm(OP_OPEN, file->f_cred, - label, &file->f_path, 0, - aa_map_file_to_perms(file), &cond); - /* todo cache full allowed permissions set and state */ - fctx->allow = aa_map_file_to_perms(file); + if (is_mqueue_inode(file_inode(file))) { + error = aa_mqueue_perm(OP_OPEN, file->f_cred, + label, &file->f_path, + aa_map_file_to_perms(file)); + allow = aa_map_file_to_perms(file); + } else { + /* will be intersected and reduced with each profile */ + allow = ALL_PERMS_MASK; + error = aa_path_perm(OP_OPEN, file->f_cred, + label, &file->f_path, 0, + aa_map_file_to_perms(file), &cond, + &allow); + } + if (!error) + fctx->allow = allow; } aa_put_label_condref(label, needput); @@ -507,6 +680,7 @@ static int apparmor_file_alloc_security(struct file *file) struct aa_file_ctx *ctx = file_ctx(file); struct aa_label *label = begin_current_label_crit_section(); + /* no inode available here */ spin_lock_init(&ctx->lock); rcu_assign_pointer(ctx->label, aa_get_label(label)); end_current_label_crit_section(label); @@ -624,13 +798,40 @@ static int profile_uring(struct aa_profile *profile, u32 request, { unsigned int state; struct aa_ruleset *rules; - int error = 0; AA_BUG(!profile); rules = profile->label.rules[0]; + /* TODO: rework unconfined profile/dfa to mediate user ns, then + * we can drop the unconfined test + */ state = RULE_MEDIATES(rules, AA_CLASS_IO_URING); - if (state) { + if (!state) { + /* TODO: this gets replaced when the default unconfined + * profile dfa gets updated to handle this + */ + if (profile_unconfined(profile) && + profile == profiles_ns(profile)->unconfined) { + if (!aa_unprivileged_uring_restricted || + ns_capable_noaudit(current_user_ns(), cap)) + /* unconfined early bail out */ + return 0; + /* unconfined unprivileged user */ + /* don't just return: allow complain mode to override */ + } else { + /* Fallback to capability check if profile doesn't + * support io_uring rules. Note: special unconfined + * profiles as well. + */ + return aa_capable(current_cred(), &profile->label, + cap, CAP_OPT_NONE); + } + /* continue to mediation - !state means non-accepting + * but can be overidden by complain + */ + } + /* block so perms is not initialized unless mediating */ + do { struct aa_perms perms = { }; if (new) { @@ -640,11 +841,11 @@ static int profile_uring(struct aa_profile *profile, u32 request, perms = *aa_lookup_perms(rules->policy, state); } aa_apply_modes_to_perms(profile, &perms); - error = aa_check_perms(profile, &perms, request, ad, + return aa_check_perms(profile, &perms, request, ad, audit_uring_cb); - } + } while (0); - return error; + return 0; } /** @@ -1041,21 +1242,32 @@ static int apparmor_task_kill(struct task_struct *target, struct kernel_siginfo return error; } -static int apparmor_userns_create(const struct cred *cred) +static int apparmor_userns_create(const struct cred *new_cred) { struct aa_label *label; struct aa_profile *profile; int error = 0; - DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_TASK, AA_CLASS_NS, - OP_USERNS_CREATE); - - ad.subj_cred = current_cred(); label = begin_current_label_crit_section(); - if (!unconfined(label)) { - error = fn_for_each(label, profile, - aa_profile_ns_perm(profile, &ad, - AA_USERNS_CREATE)); + /* remove unprivileged_userns_restricted check when unconfined is updated */ + if (aa_unprivileged_userns_restricted || + label_mediates(label, AA_CLASS_NS)) { + struct aa_label *new; + DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_TASK, AA_CLASS_NS, + OP_USERNS_CREATE); + ad.subj_cred = current_cred(); + + new = fn_label_build(label, profile, GFP_KERNEL, + aa_profile_ns_perm(profile, &ad, + AA_USERNS_CREATE)); + if (IS_ERR(new)) { + error = PTR_ERR(new); + } else if (new && cred_label(new_cred) != new) { + aa_put_label(cred_label(new_cred)); + set_cred_label(new_cred, new); + } else { + aa_put_label(new); + } } end_current_label_crit_section(label); @@ -1259,13 +1471,21 @@ static int apparmor_socket_create(int family, int type, int protocol, int kern) label = begin_current_label_crit_section(); if (!unconfined(label)) { - if (family == PF_UNIX) + switch (family) { + case PF_UNIX: error = aa_unix_create_perm(label, family, type, protocol); - else + break; + case PF_INET: + case PF_INET6: + error = aa_inet_create_perm(label, family, type, + protocol); + break; + default: error = aa_af_perm(current_cred(), label, OP_CREATE, AA_MAY_CREATE, family, type, protocol); + } } end_current_label_crit_section(label); @@ -1359,8 +1579,13 @@ static int apparmor_socket_bind(struct socket *sock, AA_BUG(!address); AA_BUG(in_interrupt()); - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_bind_perm(sock, address, addrlen); + case PF_INET: + case PF_INET6: + return aa_inet_bind_perm(sock, address, addrlen); + } return aa_sk_perm(OP_BIND, AA_MAY_BIND, sock->sk); } @@ -1373,8 +1598,13 @@ static int apparmor_socket_connect(struct socket *sock, AA_BUG(in_interrupt()); /* PF_UNIX goes through unix_stream_connect && unix_may_send */ - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return 0; + case PF_INET: + case PF_INET6: + return aa_inet_connect_perm(sock, address, addrlen); + } return aa_sk_perm(OP_CONNECT, AA_MAY_CONNECT, sock->sk); } @@ -1384,8 +1614,13 @@ static int apparmor_socket_listen(struct socket *sock, int backlog) AA_BUG(!sock->sk); AA_BUG(in_interrupt()); - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_listen_perm(sock, backlog); + case PF_INET: + case PF_INET6: + return aa_inet_listen_perm(sock, backlog); + } return aa_sk_perm(OP_LISTEN, AA_MAY_LISTEN, sock->sk); } @@ -1400,8 +1635,13 @@ static int apparmor_socket_accept(struct socket *sock, struct socket *newsock) AA_BUG(!newsock); AA_BUG(in_interrupt()); - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_accept_perm(sock, newsock); + case PF_INET: + case PF_INET6: + return aa_inet_accept_perm(sock, newsock); + } return aa_sk_perm(OP_ACCEPT, AA_MAY_ACCEPT, sock->sk); } @@ -1414,8 +1654,14 @@ static int aa_sock_msg_perm(const char *op, u32 request, struct socket *sock, AA_BUG(in_interrupt()); /* PF_UNIX goes through unix_may_send */ - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return 0; + case PF_INET: + case PF_INET6: + return aa_inet_msg_perm(op, request, sock, msg, size); + } + return aa_sk_perm(op, request, sock->sk); } @@ -1452,8 +1698,13 @@ static int aa_sock_perm(const char *op, u32 request, struct socket *sock) AA_BUG(!sock->sk); AA_BUG(in_interrupt()); - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_sock_perm(op, request, sock); + case PF_INET: + case PF_INET6: + return aa_inet_sock_perm(op, request, sock); + } return aa_sk_perm(op, request, sock->sk); } @@ -1475,8 +1726,13 @@ static int aa_sock_opt_perm(const char *op, u32 request, struct socket *sock, AA_BUG(!sock->sk); AA_BUG(in_interrupt()); - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_opt_perm(op, request, sock, level, optname); + case PF_INET: + case PF_INET6: + return aa_inet_opt_perm(op, request, sock, level, optname); + } return aa_sk_perm(op, request, sock->sk); } @@ -1515,7 +1771,7 @@ static int apparmor_socket_sock_rcv_skb(struct sock *sk, struct sk_buff *skb) struct aa_sk_ctx *ctx = aa_sock(sk); int error; - if (!skb->secmark) + if (!aa_secmark() || !skb->secmark) return 0; /* @@ -1640,7 +1896,7 @@ static int apparmor_inet_conn_request(const struct sock *sk, struct sk_buff *skb struct aa_sk_ctx *ctx = aa_sock(sk); int error; - if (!skb->secmark) + if (!aa_secmark() || !skb->secmark) return 0; rcu_read_lock(); @@ -1658,8 +1914,13 @@ static int apparmor_inet_conn_request(const struct sock *sk, struct sk_buff *skb struct lsm_blob_sizes apparmor_blob_sizes __ro_after_init = { .lbs_cred = sizeof(struct aa_label *), .lbs_file = sizeof(struct aa_file_ctx), + .lbs_inode = sizeof(struct aa_inode_sec), .lbs_task = sizeof(struct aa_task_ctx), .lbs_sock = sizeof(struct aa_sk_ctx), + .lbs_secmark = true, + .lbs_ipc = sizeof(struct aa_ipc_sec), + .lbs_msg_msg = sizeof(struct aa_msg_sec), + .lbs_superblock = sizeof(struct aa_superblock_sec), }; static const struct lsm_id apparmor_lsmid = { @@ -1690,6 +1951,16 @@ static struct security_hook_list apparmor_hooks[] __ro_after_init = { LSM_HOOK_INIT(path_truncate, apparmor_path_truncate), LSM_HOOK_INIT(inode_getattr, apparmor_inode_getattr), + LSM_HOOK_INIT(inode_alloc_security, apparmor_inode_alloc_security), + LSM_HOOK_INIT(inode_free_security, apparmor_inode_free_security), + LSM_HOOK_INIT(inode_init_security, apparmor_inode_init_security), + LSM_HOOK_INIT(d_instantiate, apparmor_d_instantiate), + + LSM_HOOK_INIT(inode_create, apparmor_inode_create), + LSM_HOOK_INIT(inode_unlink, apparmor_inode_unlink), + LSM_HOOK_INIT(inode_setattr, apparmor_inode_setattr), + LSM_HOOK_INIT(inode_getattr, apparmor_inode_getattr), + LSM_HOOK_INIT(file_open, apparmor_file_open), LSM_HOOK_INIT(file_receive, apparmor_file_receive), LSM_HOOK_INIT(file_permission, apparmor_file_permission), @@ -2332,6 +2603,17 @@ static int apparmor_dointvec(const struct ctl_table *table, int write, return proc_dointvec(table, write, buffer, lenp, ppos); } +static int userns_restrict_dointvec(const struct ctl_table *table, int write, + void *buffer, size_t *lenp, loff_t *ppos) +{ + if (!apparmor_enabled) + return -EINVAL; + if (write && !aa_current_policy_admin_capable(NULL)) + return -EPERM; + + return proc_dointvec(table, write, buffer, lenp, ppos); +} + static const struct ctl_table apparmor_sysctl_table[] = { #ifdef CONFIG_USER_NS { @@ -2349,10 +2631,40 @@ static const struct ctl_table apparmor_sysctl_table[] = { .mode = 0600, .proc_handler = apparmor_dointvec, }, +#ifdef CONFIG_USER_NS + { + .procname = "apparmor_restrict_unprivileged_userns", + .data = &aa_unprivileged_userns_restricted, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = userns_restrict_dointvec, + }, + { + .procname = "apparmor_restrict_unprivileged_userns_force", + .data = &aa_unprivileged_userns_restricted_force, + .maxlen = sizeof(int), + .mode = 0600, + .proc_handler = apparmor_dointvec, + }, + { + .procname = "apparmor_restrict_unprivileged_userns_complain", + .data = &aa_unprivileged_userns_restricted_complain, + .maxlen = sizeof(int), + .mode = 0600, + .proc_handler = apparmor_dointvec, + }, +#endif /* CONFIG_USER_NS */ { .procname = "apparmor_restrict_unprivileged_unconfined", .data = &aa_unprivileged_unconfined_restricted, .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = userns_restrict_dointvec, + }, + { + .procname = "apparmor_restrict_unprivileged_io_uring", + .data = &aa_unprivileged_uring_restricted, + .maxlen = sizeof(int), .mode = 0600, .proc_handler = apparmor_dointvec, }, @@ -2378,7 +2690,7 @@ static unsigned int apparmor_ip_postroute(void *priv, struct sock *sk; int error; - if (!skb->secmark) + if (!aa_secmark() || !skb->secmark) return NF_ACCEPT; sk = skb_to_full_sk(skb); @@ -2512,7 +2824,16 @@ static void __init aa_teardown_dfa_engine(void) static int __init apparmor_init(void) { - int error; + int error = -ENOMEM; + + /* setup allocation caches */ + aa_audit_slab = kmem_cache_create("apparmor_auditcache", + sizeof(struct aa_audit_node), + 0, SLAB_PANIC, NULL); + if (!aa_audit_slab) { + AA_ERROR("Unable to setup auditdata slab cache\n"); + goto alloc_out; + } error = aa_setup_dfa_engine(); if (error) { @@ -2567,6 +2888,7 @@ static int __init apparmor_init(void) alloc_out: aa_destroy_aafs(); aa_teardown_dfa_engine(); + kmem_cache_destroy(aa_audit_slab); apparmor_enabled = false; return error; @@ -2574,7 +2896,7 @@ static int __init apparmor_init(void) DEFINE_LSM(apparmor) = { .id = &apparmor_lsmid, - .flags = LSM_FLAG_LEGACY_MAJOR | LSM_FLAG_EXCLUSIVE, + .flags = LSM_FLAG_LEGACY_MAJOR, .enabled = &apparmor_enabled, .blobs = &apparmor_blob_sizes, .init = apparmor_init, diff --git a/security/apparmor/net.c b/security/apparmor/net.c index cf590dd08540c8..5e682bed9da0a4 100644 --- a/security/apparmor/net.c +++ b/security/apparmor/net.c @@ -9,6 +9,7 @@ */ #include "include/af_unix.h" +#include "include/af_inet.h" #include "include/apparmor.h" #include "include/audit.h" #include "include/cred.h" @@ -22,14 +23,18 @@ struct aa_sfs_entry aa_sfs_entry_network[] = { AA_SFS_FILE_STRING("af_mask", AA_SFS_AF_MASK), - AA_SFS_FILE_BOOLEAN("tcp-fast-open", 1), + AA_SFS_FILE_BOOLEAN("af_inet", 1), { } }; struct aa_sfs_entry aa_sfs_entry_networkv9[] = { AA_SFS_FILE_STRING("af_mask", AA_SFS_AF_MASK), AA_SFS_FILE_BOOLEAN("af_unix", 1), - AA_SFS_FILE_BOOLEAN("tcp-fast-open", 1), + { } +}; +struct aa_sfs_entry aa_sfs_entry_network_compat[] = { + AA_SFS_FILE_STRING("af_mask", AA_SFS_AF_MASK), + AA_SFS_FILE_BOOLEAN("af_unix", 1), { } }; @@ -133,12 +138,12 @@ void audit_net_cb(struct audit_buffer *ab, void *va) audit_log_format(ab, " protocol=%d", ad->net.protocol); if (ad->request & NET_PERMS_MASK) { - audit_log_format(ab, " requested_mask="); + audit_log_format(ab, " requested="); aa_audit_perm_mask(ab, ad->request, NULL, 0, net_mask_names, NET_PERMS_MASK); if (ad->denied & NET_PERMS_MASK) { - audit_log_format(ab, " denied_mask="); + audit_log_format(ab, " denied="); aa_audit_perm_mask(ab, ad->denied, NULL, 0, net_mask_names, NET_PERMS_MASK); } @@ -248,10 +253,44 @@ aa_state_t aa_match_to_prot(struct aa_policydb *policy, aa_state_t state, return state; } -/* Generic af perm */ -int aa_profile_af_perm(struct aa_profile *profile, +int aa_profile_af_compat_perm(struct aa_profile *profile, struct apparmor_audit_data *ad, u32 request, u16 family, - int type, int protocol) + int type) +{ + AA_BUG(family >= AF_MAX); + AA_BUG(type < 0 || type >= SOCK_MAX); + + /* 2.x socket mediation was opt in, ie. only applied if net_compat + * struct is present + */ + if (profile->net_compat && !profile_unconfined(profile)) { + /* 2.x socket mediation compat */ + struct aa_ruleset *rules = profile->label.rules[0]; + aa_state_t state = DFA_NOMATCH; + + struct aa_perms perms = { }; + + perms.allow = (profile->net_compat->allow[family] & + (1 << type)) ? + ALL_PERMS_MASK : 0; + perms.audit = (profile->net_compat->audit[family] & + (1 << type)) ? + ALL_PERMS_MASK : 0; + perms.quiet = (profile->net_compat->quiet[family] & + (1 << type)) ? + ALL_PERMS_MASK : 0; + + return aa_do_perms(profile, rules->policy, state, request, + &perms, ad); + } + + return 0; +} + +/* Generic af perm */ +static int profile_af_perm(struct aa_profile *profile, + struct apparmor_audit_data *ad, u32 request, + u16 family, int type, int protocol) { struct aa_ruleset *rules = profile->label.rules[0]; struct aa_perms *p = NULL; @@ -259,16 +298,16 @@ int aa_profile_af_perm(struct aa_profile *profile, AA_BUG(family >= AF_MAX); AA_BUG(type < 0 || type >= SOCK_MAX); - AA_BUG(profile_unconfined(profile)); - if (profile_unconfined(profile)) - return 0; state = RULE_MEDIATES_NET(rules); - if (!state) - return 0; - state = aa_match_to_prot(rules->policy, state, request, family, type, - protocol, &p, &ad->info); - return aa_do_perms(profile, rules->policy, state, request, p, ad); + if (state) { + state = aa_match_to_prot(rules->policy, state, request, family, + type, protocol, &p, &ad->info); + return aa_do_perms(profile, rules->policy, state, request, p, + ad); + } /* else */ + + return aa_profile_af_compat_perm(profile, ad, request, family, type); } int aa_af_perm(const struct cred *subj_cred, struct aa_label *label, @@ -278,8 +317,8 @@ int aa_af_perm(const struct cred *subj_cred, struct aa_label *label, DEFINE_AUDIT_NET(ad, op, subj_cred, NULL, family, type, protocol); return fn_for_each_confined(label, profile, - aa_profile_af_perm(profile, &ad, request, family, - type, protocol)); + profile_af_perm(profile, &ad, request, family, type, + protocol)); } static int aa_label_sk_perm(const struct cred *subj_cred, @@ -299,7 +338,8 @@ static int aa_label_sk_perm(const struct cred *subj_cred, ad.subj_cred = subj_cred; error = fn_for_each_confined(label, profile, - aa_profile_af_sk_perm(profile, &ad, request, sk)); + profile_af_perm(profile, &ad, request, sk->sk_family, + sk->sk_type, sk->sk_protocol)); } return error; @@ -333,8 +373,15 @@ int aa_sock_file_perm(const struct cred *subj_cred, struct aa_label *label, if (!sock || !sock->sk) return 0; - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_file_perm(subj_cred, label, op, request, file); + break; + case PF_INET: + case PF_INET6: + return aa_inet_file_perm(subj_cred, label, op, request, sock); + break; + } return aa_label_sk_perm(subj_cred, label, op, request, sock->sk); } diff --git a/security/apparmor/notify.c b/security/apparmor/notify.c new file mode 100644 index 00000000000000..b5e0506d74937c --- /dev/null +++ b/security/apparmor/notify.c @@ -0,0 +1,1368 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AppArmor security module + * + * This file contains AppArmor notifications function definitions. + * + * Copyright 2019 Canonical Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + */ +#include +#include +#include +#include + +#include + +#include "include/audit.h" +#include "include/cred.h" +#include "include/lib.h" +#include "include/notify.h" +#include "include/policy.h" +#include "include/policy_ns.h" + + + +static DEFINE_SPINLOCK(notif_lock); +static u64 g_listener_id = 1; + +static u64 get_next_listener_id(void) +{ + u64 tmp; + + spin_lock(¬if_lock); + tmp = ++g_listener_id; + spin_unlock(¬if_lock); + + return tmp; +} + +/*****************************************************************/ + +/* TODO: when adding listener or ns propagate, on recursive add to child ns */ + +// TODO: currently all knotif will have audit_node but not all in future +static inline struct aa_knotif *aa_get_knotif(struct aa_knotif *knotif) +{ + if (knotif) + aa_get_audit_node(container_of(knotif, struct aa_audit_node, + knotif)); + + return knotif; +} + +static inline void aa_put_knotif(struct aa_knotif *knotif) +{ + if (knotif) + aa_put_audit_node(container_of(knotif, struct aa_audit_node, + knotif)); +} + +static void put_refs(struct aa_listener *listener, struct aa_knotif *knotif) +{ + aa_put_listener(listener); + aa_put_knotif(knotif); +} + +static void get_refs(struct aa_listener *listener, struct aa_knotif *knotif) +{ + aa_get_listener(listener); + aa_get_knotif(knotif); +} + +static void __knotif_del_and_hold(struct aa_knotif *knotif) +{ + list_del_init(&knotif->list); + knotif->flags &= ~KNOTIF_ON_LIST; + /* keep list refcounts */ +} + +static void __list_append_held(struct list_head *lh, struct aa_knotif *knotif) +{ + AA_BUG(!lh); + AA_BUG(!knotif); + + list_add_tail_entry(knotif, lh, list); + knotif->flags |= KNOTIF_ON_LIST; +} + +/* +static void __list_push_held(struct list_head *lh, struct aa_knotif *knotif) +{ + AA_BUG(!lh); + AA_BUG(!knotif); + + list_add_entry(knotif, lh, list); + knotif->flags |= KNOTIF_ON_LIST; +} +*/ + +static void __listener_add_knotif(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + AA_BUG(!listener); + AA_BUG(!knotif); + lockdep_assert_held(&listener->lock); + + get_refs(listener, knotif); + __list_append_held(&listener->notifications, knotif); +} + +// drops refs +static void __listener_del_knotif(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + AA_BUG(!listener); + AA_BUG(!knotif); + lockdep_assert_held(&listener->lock); + + list_del_init(&knotif->list); + if (knotif->flags & KNOTIF_ON_LIST) { + knotif->flags &= ~KNOTIF_ON_LIST; + put_refs(listener, knotif); + } +} + +void aa_free_listener_proxy(struct aa_listener_proxy *proxy) +{ + if (proxy->listener) { + spin_lock(&proxy->listener->lock); + list_del_init(&proxy->llist); + spin_unlock(&proxy->listener->lock); + } + if (proxy->ns) { + spin_lock(&proxy->ns->listener_lock); + list_del_init(&proxy->nslist); + spin_unlock(&proxy->ns->listener_lock); + } + aa_put_ns(proxy->ns); + aa_put_listener(proxy->listener); + kfree_sensitive(proxy); +} + +// transfers listeners refcount +struct aa_listener_proxy *aa_new_listener_proxy(struct aa_listener *listener, + struct aa_ns *ns) +{ + struct aa_listener_proxy *proxy; + + AA_BUG(!listener); + lockdep_assert_not_held(&listener->lock); + + proxy = kzalloc(sizeof(*proxy), GFP_KERNEL); + if (!proxy) + return NULL; + INIT_LIST_HEAD(&proxy->llist); + INIT_LIST_HEAD(&proxy->nslist); + + proxy->listener = aa_get_listener(listener); + if (ns) + ns = aa_get_ns(ns); + else + ns = aa_get_current_ns(); + proxy->ns = ns; + + spin_lock(&listener->lock); + list_add_tail_entry(proxy, &listener->ns_proxies, llist); + spin_unlock(&listener->lock); + + spin_lock(&ns->listener_lock); + list_add_tail_entry(proxy, &ns->listeners, nslist); + spin_unlock(&ns->listener_lock); + + AA_DEBUG(DEBUG_UPCALL, "Added new listener proxy for listener %lld", listener->listener_id); + return proxy; +} + +static void free_listener(struct aa_listener *listener) +{ + struct aa_listener_proxy *proxy; + struct aa_knotif *knotif; + + AA_DEBUG(DEBUG_UPCALL, "enter freeing listener_id %llu", listener->listener_id); + if (!listener) + return; + + wake_up_interruptible_poll(&listener->wait, EPOLLIN | EPOLLRDNORM); + + spin_lock(&listener->lock); + while (!list_empty(&listener->ns_proxies)) { + proxy = list_first_entry(&listener->ns_proxies, + struct aa_listener_proxy, + llist); + list_del_init(&proxy->llist); + spin_unlock(&listener->lock); + + spin_lock(&proxy->ns->listener_lock); + list_del_init(&proxy->nslist); + spin_unlock(&proxy->ns->listener_lock); + + aa_put_ns(proxy->ns); + kfree_sensitive(proxy); + + spin_lock(&listener->lock); + } + spin_unlock(&listener->lock); + + spin_lock(&listener->lock); + while (!list_empty(&listener->notifications)) { + knotif = list_first_entry(&listener->notifications, + struct aa_knotif, + list); + __listener_del_knotif(listener, knotif); + complete(&knotif->ready); + put_refs(listener, knotif); + } + spin_unlock(&listener->lock); + + spin_lock(&listener->lock); + while (!list_empty(&listener->pending)) { + knotif = list_first_entry(&listener->pending, + struct aa_knotif, + list); + __listener_del_knotif(listener, knotif); + complete(&knotif->ready); + put_refs(listener, knotif); + } + spin_unlock(&listener->lock); + + /* todo count on audit_data */ + aa_put_ns(listener->ns); + aa_put_dfa(listener->filter); + aa_put_label(listener->label); + + AA_DEBUG(DEBUG_UPCALL, "freeing listener_id %llu", listener->listener_id); + kfree_sensitive(listener); +} + +void aa_listener_kref(struct kref *kref) +{ + struct aa_listener *l = container_of(kref, struct aa_listener, count); + + AA_DEBUG(DEBUG_UPCALL, "going to free listener %p, label %p, id %llu", l, l->label, l->listener_id); + free_listener(l); +} + +#define from_delayed_work(var, callback_work, work_fieldname) \ + container_of(to_delayed_work(callback_work), typeof(*var), work_fieldname) + +static void proxy_work_function(struct work_struct *t) +{ + struct aa_listener_proxy *proxy = from_delayed_work(proxy, t, work); + AA_DEBUG(DEBUG_UPCALL, "listener reclaim timer fired. Putting listener %llu", proxy->listener->listener_id); + aa_free_listener_proxy(proxy); + /* don't want to remove here because may have been reclaimed */ + //aa_put_listener(proxy->listener); +} + + +//unsigned long seconds = 1; +void aa_delayed_free_listener_proxy(struct aa_listener_proxy *proxy) +{ + memset(&proxy->work, 0, sizeof(proxy->work)); + + AA_DEBUG(DEBUG_UPCALL, "before timer listener %p listener_id %llu label %p", proxy->listener, proxy->listener->listener_id, proxy->listener->label); + + /* delay putting the listener giving a chance to reclaim */ + INIT_DELAYED_WORK(&proxy->work, proxy_work_function); + schedule_delayed_work(&proxy->work, secs_to_jiffies(30)); + + AA_DEBUG(DEBUG_UPCALL, "after timer listener %p listener_id %llu label %p", proxy->listener, proxy->listener->listener_id, proxy->listener->label); +} + +struct aa_listener *aa_new_listener(struct aa_ns *ns, gfp_t gfp) +{ + struct aa_listener *listener = kzalloc(sizeof(*listener), gfp); + + if (!listener) + return NULL; + AA_DEBUG(DEBUG_UPCALL, "listener %p", listener); + + kref_init(&listener->count); + spin_lock_init(&listener->lock); + init_waitqueue_head(&listener->wait); + INIT_LIST_HEAD(&listener->ns_proxies); + INIT_LIST_HEAD(&listener->notifications); + INIT_LIST_HEAD(&listener->pending); + kref_init(&listener->count); + + if (ns) + ns = aa_get_ns(ns); + else + ns = aa_get_current_ns(); + listener->ns = ns; + listener->last_id = 1; + listener->listener_id = get_next_listener_id(); + + AA_DEBUG(DEBUG_UPCALL, "created listener %lld ns %p", listener->listener_id, ns); + return listener; +} + +/* increments proxy->listener ref count +* can still be on list because file callback to cleanup is delayed +*/ +static struct aa_listener *find_matching_listener_by_id(struct aa_ns *ns, + u64 id) +{ + struct aa_listener *listener = NULL; + struct aa_listener_proxy *proxy = NULL; + + spin_lock(&ns->listener_lock); + list_for_each_entry(proxy, &ns->listeners, nslist) { + AA_DEBUG(DEBUG_UPCALL, " comparing listener %p label %p id %llu to %llu", proxy->listener, proxy->listener->label, proxy->listener->listener_id, id); + spin_lock(&proxy->listener->lock); + if (proxy->listener->listener_id == id) { + listener = aa_get_listener(proxy->listener); + spin_unlock(&proxy->listener->lock); + AA_DEBUG(DEBUG_UPCALL, " found listener %p label %p id %llu to %llu", listener, listener->label, listener->listener_id, id); + break; + } + spin_unlock(&proxy->listener->lock); + } + spin_unlock(&ns->listener_lock); + + return listener; +} + +/* attempt to register a listener. If id is 0 get a new id else find + * existing listener + */ +long aa_register_listener_id(struct aa_listener *listener, u64 *id, + struct aa_listener **found) +{ + struct aa_label *label; + int error = 0; + + AA_BUG(!listener); + AA_BUG(!id); + + *found = NULL; + + label = begin_current_label_crit_section(); + if (*id == 0) { + spin_lock(&listener->ns->listener_lock); + if (listener->label) { + if (listener->label == label) { + *id = listener->listener_id; + } else { + error = -EPERM; + } + } else { + listener->label = aa_get_label(label); + *id = listener->listener_id; + AA_DEBUG(DEBUG_UPCALL, "assigned label %p to listener %p listener->label %p id %llu", label, listener, listener->label, listener->listener_id); + } + spin_unlock(&listener->ns->listener_lock); + } else { + struct aa_listener *tmp = find_matching_listener_by_id(listener->ns, *id); + if (tmp) { + if (tmp->label != label) { + AA_DEBUG(DEBUG_UPCALL, "confinement for listener %p id %llu search id %llu, listener->label %p != label %p", tmp, tmp->listener_id, *id, tmp->label , label); + aa_put_listener(tmp); + error = -EPERM; + } else { + *found = tmp; + } + } else { + AA_DEBUG(DEBUG_UPCALL, " no listener found"); + error = -ENOENT; + } + } + end_current_label_crit_section(label); + + return error; +} + +static struct aa_knotif *__aa_find_notif_pending(struct aa_listener *listener, + u64 id) +{ + struct aa_knotif *knotif; + + AA_BUG(!listener); + lockdep_assert_held(&listener->lock); + + list_for_each_entry(knotif, &listener->pending, list) { + if (knotif->id == id) + return knotif; + } + + return NULL; +} + +struct aa_knotif *__aa_find_notif(struct aa_listener *listener, u64 id) +{ + struct aa_knotif *knotif; + + AA_BUG(!listener); + lockdep_assert_held(&listener->lock); + + list_for_each_entry(knotif, &listener->notifications, list) { + if (knotif->id == id) + goto out; + } + + knotif = __aa_find_notif_pending(listener, id); +out: + + return knotif; +} + +// don't drop refcounts +/* TODO: replace use of pop/push with more correct append or enqueue/dequeue */ +static struct aa_knotif * +listener_pop_and_hold_knotif(struct aa_listener *listener) +{ + struct aa_knotif *knotif = NULL; + + spin_lock(&listener->lock); + if (!list_empty(&listener->notifications)) { + knotif = list_first_entry(&listener->notifications, typeof(*knotif), list); + __knotif_del_and_hold(knotif); + } + spin_unlock(&listener->lock); + + return knotif; +} + +// require refcounts held +/* +static void listener_push_held_knotif(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + spin_lock(&listener->lock); + // listener ref held from pop and hold + __list_push_held(&listener->notifications, knotif); + spin_unlock(&listener->lock); + wake_up_interruptible_poll(&listener->wait, EPOLLIN | EPOLLRDNORM); +} +*/ + +// require refcounts held +// list of knotifs waiting for response +static void listener_append_held_user_pending(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + spin_lock(&listener->lock); + __list_append_held(&listener->pending, knotif); + spin_unlock(&listener->lock); + //extraneous wakeup, called after reading notification + //wake_up_interruptible_poll(&listener->wait, EPOLLOUT | EPOLLWRNORM); +} + +// don't drop refcounts +static struct aa_knotif * +__del_and_hold_user_pending(struct aa_listener *listener, u64 id) +{ + struct aa_knotif *knotif; + + AA_BUG(!listener); + lockdep_assert_held(&listener->lock); + + list_for_each_entry(knotif, &listener->pending, list) { + if (knotif->id == id) { + __knotif_del_and_hold(knotif); + return knotif; + } + } + + return NULL; +} + + +/***************** kernel dispatching notification ********************/ + +/* + * cancelled notification message due to non-timer wake-up vs. + * keep alive message + * cancel notification because ns removed? + * - proxy pins ns + * - ns can remove its list of proxies + * - and remove queued notifications + */ + +/* TODO: allow registering on multiple namespaces */ +static bool notification_match(struct aa_listener *listener, + struct aa_audit_node *ad) +{ + if (!(listener->mask & (1 << ad->data.type))) { + AA_DEBUG(DEBUG_UPCALL, "listener mask failed 0x%x, type %d", listener->mask, ad->data.type); + return false; + } + + if (listener->filter) { + aa_state_t state; + unsigned int mask; + + AA_DEBUG(DEBUG_UPCALL, "using filter"); + if (!aa_ns_visible(listener->ns, labels_ns(ad->data.subj_label), + false)) + return false; + state = aa_dfa_next(listener->filter, DFA_START, ad->data.type); + state = aa_dfa_match(listener->filter, state, ad->data.subj_label->hname); + if (!state) + return false; + state = aa_dfa_null_transition(listener->filter, state); + state = aa_dfa_match_u16(listener->filter, state, ad->data.class); + mask = ACCEPT_TABLE(listener->filter)[state]; + if (ad->data.request & mask) + return true; + + /* allow for enhanced match conditions in the future + * if (mask & AA_MATCH_CONT) { + * // TODO: match extensions + * } + */ + AA_DEBUG(DEBUG_UPCALL, "failed filter match"); + return false; + } + AA_DEBUG(DEBUG_UPCALL, "matched type mask filter"); + return true; +} + +/* Add a notification to the listener queue and wake up listener??? */ +static void dispatch_notif(struct aa_listener *listener, u16 ntype, + struct aa_knotif *knotif) +{ + AA_BUG(!listener); + AA_BUG(!knotif); + lockdep_assert_held(&listener->lock); + + AA_DEBUG_ON(knotif->id, DEBUG_UPCALL, + "dispatching notification as new id %lld", + listener->last_id); + knotif->ntype = ntype; + knotif->id = ++listener->last_id; + knotif->flags = 0; + // only needed if syncrhonous notit + init_completion(&knotif->ready); + INIT_LIST_HEAD(&knotif->list); + __listener_add_knotif(listener, knotif); + AA_DEBUG(DEBUG_UPCALL, "id %lld: %s wake_up_interruptible", + knotif->id, __func__); + wake_up_interruptible_poll(&listener->wait, EPOLLIN | EPOLLRDNORM); +} + + +/* handle waiting for a user space reply to a notification + * Returns: <0 : error or -ERESTARTSYS if interrupted + * 0 : success + */ +static int handle_synchronous_notif(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + long werr; + int err; + + if (knotif->ad->subj_label->flags & FLAG_INTERRUPTIBLE) + werr = wait_for_completion_interruptible_timeout(&knotif->ready, + msecs_to_jiffies(60000)); + else + /* do not use close to long jiffies so cast is safe */ + werr = (long) wait_for_completion_timeout(&knotif->ready, + msecs_to_jiffies(60000)); + /* time out OR interrupt */ + if (werr <= 0) { + /* ensure knotif is not on list because of early exit */ + spin_lock(&listener->lock); + // puts refs but still have calling refs + __listener_del_knotif(listener, knotif); + spin_unlock(&listener->lock); + if (werr == 0) { + AA_DEBUG(DEBUG_UPCALL, "id %lld: prompt timed out", + knotif->id); + //err = -1; // TODO: ???; + err = 0; + } else if (werr == -ERESTARTSYS) { + // interrupt fired syscall needs to be restarted + // instead of mediated + AA_DEBUG(DEBUG_UPCALL, "id %lld: prompt interrupted, error %ld", + knotif->id, werr); + err = -ERESTARTSYS; + } else { + AA_DEBUG(DEBUG_UPCALL, "id %lld: prompt errored out error %ld", + knotif->id, werr); + err = (int) werr; + } + /* time out is not considered an error and will fallback + * to regular mediation + */ + } else { + err = 0; + spin_lock(&listener->lock); + if (!list_empty(&knotif->list)) { + // puts refs but still have calling refs + __listener_del_knotif(listener, knotif); + AA_DEBUG(DEBUG_UPCALL, + "id %lld: bug prompt knotif still on listener list at notif completion", + knotif->id); + } + spin_unlock(&listener->lock); + } + + return err; +} + +// permissions changed in ad +int aa_do_notification(u16 ntype, struct aa_audit_node *node) +{ + struct aa_ns *ns = labels_ns(node->data.subj_label); + struct aa_listener_proxy *proxy; + struct aa_listener *listener; + struct aa_knotif *knotif; + int count = 0, err = 0; + + AA_BUG(!node); + AA_BUG(!ns); + + knotif = &node->knotif; + + /* TODO: make read side of list walk lockless */ + spin_lock(&ns->listener_lock); + list_for_each_entry(proxy, &ns->listeners, nslist) { + + AA_BUG(!proxy); + listener = aa_get_listener(proxy->listener); + AA_BUG(!listener); + spin_lock(&listener->lock); + AA_DEBUG(DEBUG_UPCALL, "checking listener %lld for match", listener->listener_id); + if (!notification_match(listener, node)) { + spin_unlock(&listener->lock); + aa_put_listener(listener); + continue; + } + /* delvier notification - dispatch determines if we break */ + dispatch_notif(listener, ntype, knotif); + spin_unlock(&listener->lock); + AA_DEBUG(DEBUG_UPCALL, "id %lld: found listener\n", + knotif->id); + + /* break to prompt */ + if (node->data.type == AUDIT_APPARMOR_USER) { + spin_unlock(&ns->listener_lock); + err = handle_synchronous_notif(listener, knotif); + aa_put_listener(listener); + return err; + } + count++; + aa_put_listener(listener); + } + spin_unlock(&ns->listener_lock); + AA_DEBUG(DEBUG_UPCALL, "id %lld: %d listener matches\n", + knotif->id, count); + + /* count == 0 is no match found. No change to audit params + * long term need to fold prompt perms into denied + **/ + return err; +} + +long aa_listener_unotif_resend(struct aa_listener *listener, u32 *ready, + u32 *pending) +{ + struct aa_knotif *knotif; + *ready = 0; + *pending = 0; + + spin_lock(&listener->ns->listener_lock); + list_for_each_entry(knotif, &listener->notifications, list) { + (*ready)++; + } + list_for_each_entry(knotif, &listener->pending, list) { + knotif->flags = KNOTIF_RESEND; + AA_DEBUG_ON(knotif->id, DEBUG_UPCALL, + "redispatching notification id %lld", + knotif->id); + (*pending)++; + } + /* splice is like stack to move pending onto of notification + * but pulled from head like queue. ie pending is moving + * to the front of the queue. + */ + list_splice_init(&listener->pending, &listener->notifications); + AA_DEBUG(DEBUG_UPCALL, "id %lld: %s wake_up_interruptible", + knotif->id, __func__); + wake_up_interruptible_poll(&listener->wait, EPOLLIN | EPOLLRDNORM); + spin_unlock(&listener->ns->listener_lock); + + return 0; +} + +/******************** task responding to notification **********************/ + +// drop references +// complete anything pending on ready +static void __listener_complete_held_user_pending(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + AA_BUG(!listener); + lockdep_assert_held(&listener->lock); + + __knotif_del_and_hold(knotif); + complete(&knotif->ready); + put_refs(listener, knotif); +} + +static void listener_complete_held_user_pending(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + spin_lock(&listener->lock); + __listener_complete_held_user_pending(listener, knotif); + spin_unlock(&listener->lock); +} + +static bool response_is_valid_perm(struct apparmor_notif_resp_perm *reply, + struct aa_knotif *knotif, u16 size) +{ + if ((knotif->ad->denied) & ~(reply->allow | reply->deny)) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: response does not cover permission bits in the upcall request/reply 0x%x/0x%x deny/reply 0x%x/0x%x", + knotif->id, knotif->ad->request, reply->allow, knotif->ad->denied, + reply->deny); + return false; + } + return true; + /* TODO: this was disabled per snapd request, setup flag to do check + * // allow bits that were never requested + * if (reply->allow & ~knotif->ad->request) { + * AA_DEBUG(DEBUG_UPCALL, "response allows more than requested"); + * return false; + * } + * // denying perms not in either permission set in the original + * // notification + * if (reply->deny & ~(knotif->ad->request | knotif->ad->denied)) { + * AA_DEBUG(DEBUG_UPCALL, "response denies more than requested"); + * return false; + * } + */ +} + +static bool response_is_valid_name(struct apparmor_notif_resp_name *reply, + struct aa_knotif *knotif, u16 size) +{ + long i; + + if (size <= sizeof(*reply)) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply bad size %u < %ld", + knotif->id, size, sizeof(*reply)); + return -EMSGSIZE; + } + if (reply->name < sizeof(*reply)) { + /* inside of data declared fields */ + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply bad name offset in fields %u < %ld", + knotif->id, reply->name, sizeof(*reply)); + return -EINVAL; + } + if (reply->name > size) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply name pasted end of data size %u > %ld", + knotif->id, reply->name, sizeof(*reply)); + return -EINVAL; + } + /* currently supported flags */ + if ((reply->perm.base.flags != (URESPONSE_LOOKUP | URESPONSE_PROFILE))) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply bad flags 0x%x expected 0x%x", + knotif->id, reply->perm.base.flags, + URESPONSE_LOOKUP | URESPONSE_PROFILE); + return -EINVAL; + } + + if ((reply->perm.base.flags == URESPONSE_TAILGLOB) && + !response_is_valid_perm(&reply->perm, knotif, size)) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply bad tail glob perms", + knotif->id); + return false; + } + + /* check name for terminating null */ + for (i = reply->name - sizeof(*reply); i < size - sizeof(*reply); i++) { + if (reply->data[i] == 0) + return true; + } + /* reached end of data without finding null */ + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply bad no terminating null on name", + knotif->id); + + return false; +} + +/* base checks userspace respnse to a notification is valid */ +static bool response_is_valid(union apparmor_notif_resp *reply, + struct aa_knotif *knotif, u16 size) +{ + if (reply->base.ntype == APPARMOR_NOTIF_RESP_PERM) + return response_is_valid_perm(&reply->perm, knotif, size); + else if (reply->base.ntype == APPARMOR_NOTIF_RESP_NAME) + return response_is_valid_name(&reply->name, knotif, size); + else + return false; + return false; +} + + +/* copy uresponse into knotif */ +static void knotif_update_from_uresp_perm(struct aa_knotif *knotif, + struct apparmor_notif_resp_perm *uresp) +{ + u16 flags; + + if (uresp) { + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response allow/reply 0x%x/0x%x, denied/reply 0x%x/0x%x, error %d/%d", + knotif->id, knotif->ad->request, uresp->allow, + knotif->ad->denied, uresp->deny, knotif->ad->error, + uresp->base.error); + + knotif->ad->denied = uresp->deny; + knotif->ad->request = (knotif->ad->request | uresp->allow) & + ~uresp->deny; + flags = uresp->base.flags; + if (!knotif->ad->denied) { + /* no more denial, clear the error*/ + knotif->ad->error = 0; + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response allowed, clearing error\n", + knotif->id); + } else { + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response denied returning error %d\n", + knotif->id, knotif->ad->error); + } + } else { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: respons bad going with: allow 0x%x, denied 0x%x, error %d", + knotif->id, knotif->ad->request, knotif->ad->denied, + knotif->ad->error); + } + + if (!(flags & URESPONSE_NO_CACHE)) { + /* cache of response requested */ + struct aa_audit_node *node = container_of(knotif, + struct aa_audit_node, + knotif); + struct aa_audit_node *hit; + struct aa_profile *profile = labels_profile(node->data.subj_label); + + AA_DEBUG(DEBUG_UPCALL, "id %lld: inserting cache entry requ 0x%x denied 0x%x", + knotif->id, node->data.request, node->data.denied); + hit = aa_audit_cache_insert(&profile->learning_cache, + node); + AA_DEBUG(DEBUG_UPCALL, + "id %lld: (node %p, hit %p) cache insert %s: name %s node %s\n", + knotif->id, node, hit, hit != node ? "entry already exists" : "", + hit->data.name, node->data.name); + if (hit != node) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: updating existing cache entry", + knotif->id); + aa_audit_cache_update_ent(&profile->learning_cache, + hit, &node->data); + aa_put_audit_node(hit); + } else { + + AA_DEBUG(DEBUG_UPCALL, "inserted into cache"); + } + /* now to audit */ + } /* cache_response */ +} + + +void aa_free_ruleset(struct aa_ruleset *rules) +{ + if (!rules) + return; + aa_put_pdb(rules->policy); + aa_put_pdb(rules->file); + kfree_sensitive(rules); +} + +struct aa_ruleset *aa_new_ruleset(gfp_t gfp) +{ + struct aa_ruleset *rules = kzalloc(sizeof(*rules), gfp); + + return rules; +} + +struct aa_ruleset *aa_clone_ruleset(struct aa_ruleset *rules) +{ + struct aa_ruleset *clone; + + clone = aa_new_ruleset(GFP_KERNEL); + if (!clone) + return NULL; + clone->size = rules->size; + clone->policy = aa_get_pdb(rules->policy); + clone->file = aa_get_pdb(rules->file); + clone->caps = rules->caps; + clone->rlimits = rules->rlimits; + + /* TODO: secmark */ + return clone; +} + +static long knotif_update_from_uresp_name(struct aa_knotif *knotif, + struct apparmor_notif_resp_name *reply, + u16 size) +{ + struct aa_ruleset *rules; + struct aa_profile *profile; + struct aa_ns *ns; + char *name, *glob; + struct aa_audit_node *clone; + struct aa_audit_node *node = container_of(knotif, + struct aa_audit_node, + knotif); + + ns = aa_get_current_ns(); + name = (char *) &reply->data[reply->name - sizeof(*reply)]; + + if (reply->perm.base.flags == (URESPONSE_LOOKUP | URESPONSE_PROFILE)) { + profile = aa_lookupn_profile(ns, name, strlen(name)); + if (!profile) { + aa_put_ns(ns); + return -ENOENT; + } + aa_put_ns(ns); + + rules = aa_clone_ruleset(profile->label.rules[0]); + if (!rules) { + aa_put_profile(profile); + return -ENOMEM; + } + AA_DEBUG(DEBUG_UPCALL, + "id %lld: cloned profile '%s' rule set", knotif->id, + profile->base.hname); + aa_put_profile(profile); + + /* add list to profile rules TODO: improve locking*/ + profile = labels_profile(node->data.subj_label); + // list_add_tail_entry(rules, &profile->label.rules[0], list); + } else if (reply->perm.base.flags == URESPONSE_TAILGLOB) { + // TODO: dedup with cache update in perm + struct aa_audit_node *node = container_of(knotif, + struct aa_audit_node, + knotif); + struct aa_audit_node *hit; + struct aa_profile *profile = labels_profile(node->data.subj_label); + + clone = aa_dup_audit_data(&node->data, GFP_KERNEL); + glob = kstrdup(name, GFP_KERNEL); + if (!name) + return -ENOMEM; + if (!clone) { + kfree(name); + return -ENOMEM; + } + kfree(clone->data.name); + clone->data.name = glob; + clone->data.flags = AUDIT_TAILGLOB_NAME; + clone->knotif.id = knotif->id; + clone->knotif.ntype = knotif->ntype; + node = clone; + knotif = &clone->knotif; + + // now add it to the cache + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response allow/reply 0x%x/0x%x, denied/reply 0x%x/0x%x, error %d/%d", + knotif->id, knotif->ad->request, reply->perm.allow, + knotif->ad->denied, reply->perm.deny, knotif->ad->error, + reply->base.error); + + knotif->ad->denied = reply->perm.deny; + knotif->ad->request = reply->perm.allow | reply->perm.deny; + + if (!knotif->ad->denied) { + /* no more denial, clear the error*/ + knotif->ad->error = 0; + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response allowed, clearing error\n", + knotif->id); + } else { + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response denied returning error %d\n", + knotif->id, knotif->ad->error); + } + + AA_DEBUG(DEBUG_UPCALL, "id %lld: inserting cache entry requ 0x%x denied 0x%x", + knotif->id, node->data.request, node->data.denied); + hit = aa_audit_cache_insert(&profile->learning_cache, + node); + AA_DEBUG(DEBUG_UPCALL, "id %lld: cache insert %s: name %s node %s\n", + knotif->id, hit != node ? "lost race" : "", + hit->data.name, node->data.name); + if (hit != node) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: updating existing cache entry", + knotif->id); + aa_audit_cache_update_ent(&profile->learning_cache, + hit, &node->data); + aa_put_audit_node(hit); + } else { + + AA_DEBUG(DEBUG_UPCALL, "inserted into cache"); + } + aa_put_audit_node(clone); + } + return size; +} + +/* handle userspace responding to a synchronous notification */ +long aa_listener_unotif_response(struct aa_listener *listener, + union apparmor_notif_resp *uresp, + u16 size) +{ + struct aa_knotif *knotif = NULL; + long ret; + + spin_lock(&listener->lock); + knotif = __del_and_hold_user_pending(listener, uresp->base.id); + if (!knotif) { + ret = -ENOENT; + AA_DEBUG(DEBUG_UPCALL, "could not find id %lld", + uresp->base.id); + goto out; + } + if (!response_is_valid(uresp, knotif, size)) { + ret = -EINVAL; + AA_DEBUG(DEBUG_UPCALL, "id %lld: response not valid", knotif->id); + __listener_complete_held_user_pending(listener, knotif); + goto out; + } + + if (uresp->perm.base.ntype == APPARMOR_NOTIF_RESP_PERM) { + knotif_update_from_uresp_perm(knotif, &uresp->perm); + } else if (uresp->perm.base.ntype == APPARMOR_NOTIF_RESP_NAME) { + size = knotif_update_from_uresp_name(knotif, &uresp->name, size); + } else { + AA_DEBUG(DEBUG_UPCALL, "id %lld: unknown response type", knotif->id); + size = -EINVAL; + } + ret = size; + + AA_DEBUG(DEBUG_UPCALL, "id %lld: completing notif", knotif->id); + __listener_complete_held_user_pending(listener, knotif); +out: + spin_unlock(&listener->lock); + + return ret; +} + +/******************** task reading notification to userspace ****************/ + +static long append_bytes(void __user *pos, long remaining, const char *str, + u32 size) +{ + if (size > remaining) + return -EMSGSIZE; + if (copy_to_user(pos, str, size)) + return -EFAULT; + + return size; +} + +/* __POS will be updated + * __FIELD will be updated + * returns __SIZE or error + */ +#define build_append_bytes(__BUF, __POS, __MAX, __STR, __SIZE, __FIELD) \ +({ \ + long __tmp_size; \ + long __tmp_offset = __POS - __BUF; \ + __tmp_size = append_bytes(__POS, __MAX - __tmp_offset, __STR, __SIZE); \ + if (__tmp_size >= 0) { \ + __FIELD = __tmp_offset; \ + __POS += __tmp_size; \ + } \ + (__tmp_size); \ +}) + +/* __POS will be updated + * __FIELD will be updated + * returns __SIZE or error + */ +#define build_append_str(__BUF, __POS, __MAX, __STR, __FIELD) \ +({ \ + long __tmp_size = 0; \ + if (__STR) { \ + __tmp_size = build_append_bytes(__BUF, __POS, __MAX, __STR, \ + strlen(__STR)+1, __FIELD);\ + } \ + (__tmp_size); \ +}) + +/* returns amount written to tpos */ +static long build_tagset(void __user *buf, void __user *hpos, void __user *tpos, + u16 max_size, u32 mask, u32 count, const char *tagstr, + u32 tagsize) +{ + struct apparmor_tags_header_v5 th; + long size; + + th.mask = mask; + th.count = count; + th.tagset = tpos - buf; + size = build_append_bytes(buf, tpos, max_size, tagstr, tagsize, + th.tagset); + if (size < 0) { + AA_DEBUG(DEBUG_TAGS, "build_append_bytes %ld < 0, max %d, tagstr '%s', (long) pos %d, size %d", size, max_size, tagstr, th.tagset, tagsize); + return size; + } + AA_DEBUG(DEBUG_TAGS, " tagset: mask 0x%x, count %d, pos %d, str '%s', strlen %ld, size %ld, return size %ld\n", mask, count, th.tagset, tagstr, strlen(tagstr), (long) tagsize, size); + if (copy_to_user(hpos, &th, sizeof(th))) { + AA_DEBUG(DEBUG_TAGS, "failed: copy_to_user hpos %ld", (long) hpos); + return -EFAULT; + } + return size; +} + +/* build tags for a given tag index */ +static long build_tags(union apparmor_notif_all *unotif, + void __user *buf, void __user *pos, u16 max_size, + struct aa_tags_struct *metatags, u32 mask, u32 permidx) +{ + void __user *hpos, *tpos; + int i, c = 0; + + if (!metatags || permidx == 0) + return pos - buf; + + /* count number of header that need to be laid down */ + for (i = 0; i < metatags->sets.table[permidx]; i++) { + u32 idx = metatags->sets.table[permidx+1+i]; + if (mask & metatags->hdrs.table[idx].mask) { + c++; + AA_DEBUG(DEBUG_TAGS, "matched mask 0x%x, tag[%d].mask 0x%x\n", mask, i, metatags->hdrs.table[idx].mask); + } + } + if (c == 0) { + AA_DEBUG(DEBUG_TAGS, "No matching tag info"); + /* no tags match */ + return pos - buf; + } + + hpos = PTR_ALIGN(pos, 8); + tpos = hpos + (c * sizeof(struct apparmor_tags_header_v5)); //c * 96 + + unotif->file.tags = hpos - buf; + unotif->file.tags_count = c; + AA_DEBUG(DEBUG_TAGS, + "file tags header hpos %ld, tpos %ld tagset_count %d", + hpos - buf, tpos- buf, c); + for (i = 0; i < metatags->sets.table[permidx]; i++) { + u32 idx = metatags->sets.table[permidx+1+i]; + AA_DEBUG(DEBUG_TAGS, + " ... building loop %d, idx %d, mask 0x%x, tags mask 0x%x", + i, idx, mask, metatags->hdrs.table[idx].mask); + if (mask & metatags->hdrs.table[idx].mask) { + struct aa_tags_header *h = &metatags->hdrs.table[idx]; + long size; + + AA_DEBUG(DEBUG_TAGS, + " build_tagset hpos %ld, tpos %ld, index tagset %d tagstr '%s'", + hpos - buf, tpos - buf, h->tags, + metatags->strs.table[h->tags].strs); + size = build_tagset(buf, hpos, tpos, max_size, + h->mask, h->count, + metatags->strs.table[h->tags].strs, + h->size); + if (size < 0) { + AA_DEBUG(DEBUG_TAGS, "build_tagset failed"); + return size; + } + hpos += sizeof(struct apparmor_tags_header_v5); + tpos += size; + } else + AA_DEBUG(DEBUG_TAGS, " no build tagset %d", + mask & metatags->hdrs.table[idx].mask); + } + + AA_DEBUG(DEBUG_TAGS, + " build_tags completed pos %ld, buf %ld, size %ld", + (long) tpos, (long) buf, tpos-buf); + return tpos - buf; +} + +static long build_v35_unotif_common(struct aa_profile *profile, + u16 version, + struct aa_knotif *knotif, + union apparmor_notif_all *unotif, + void __user *buf, u16 max_size) +{ + struct user_namespace *user_ns; + + AA_DEBUG(DEBUG_UPCALL, "building notif max size %d", max_size); + if (sizeof(*unotif) > max_size) + return -EMSGSIZE; + + user_ns = get_user_ns(current->nsproxy->uts_ns->user_ns); + + /* build response */ + unotif->common.len = sizeof(*unotif); + unotif->common.version = version; + unotif->base.ntype = knotif->ntype; + if (knotif->flags & KNOTIF_RESEND) + unotif->base.flags |= UNOTIF_RESENT; + unotif->base.id = knotif->id; + unotif->base.error = knotif->ad->error; + unotif->op.allow = knotif->ad->request & ~knotif->ad->denied; + unotif->op.deny = knotif->ad->denied; + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: sent to user read request 0x%x, denied 0x%x, error %d", + knotif->id, knotif->ad->request, knotif->ad->denied, knotif->ad->error); + + if (knotif->ad->subjtsk != NULL) { + unotif->op.pid = task_pid_vnr(knotif->ad->subjtsk); + unotif->file.subj_uid = from_kuid(user_ns, task_uid(knotif->ad->subjtsk)); + } + unotif->op.class = knotif->ad->class; + unotif->file.obj_uid = from_kuid(user_ns, knotif->ad->fs.ouid); + + put_user_ns(user_ns); + + return sizeof(*unotif); +} + +/* returns total size */ +static long build_v35_unotif_file(struct aa_profile *profile, + struct aa_knotif *knotif, + union apparmor_notif_all *unotif, + void __user *buf, long size, u16 max_size) +{ + void __user *pos = buf + size; + size = build_append_str(buf, pos, max_size, profile->base.hname, + unotif->op.label); + if (size < 0) + return size; + size = build_append_str(buf, pos, max_size, knotif->ad->name, + unotif->file.name); + if (size < 0) + return size; + + if (unotif->common.version == 5) { + struct aa_ruleset *rules = profile->label.rules[0]; + size = build_tags(unotif, buf, pos, max_size, &rules->file->tags, + knotif->ad->request | knotif->ad->denied, + knotif->ad->tags); + if (size < 0) + return size; + pos = buf + size; + } + return pos - buf; +} + +/* copy to userspace: notification data */ +static long build_v35_unotif(u16 version, struct aa_knotif *knotif, + void __user *buf, u16 max_size) +{ + union apparmor_notif_all unotif = { }; + struct aa_profile *profile; + long size; + + profile = labels_profile(knotif->ad->subj_label); + AA_BUG(profile == NULL); + + size = build_v35_unotif_common(profile, version, knotif, &unotif, buf, + max_size); + if (size < 0) + return size; + size = build_v35_unotif_file(profile, knotif, &unotif, buf, size, + max_size); + if (size < 0) + return size; + + /* set size after appending variable length info */ + unotif.common.len = size; + /* now the struct, at the start of user mem */ + if (copy_to_user(buf, &unotif, sizeof(unotif))) + return -EFAULT; + + return size; +} + +// return < 0 == error +// 0 == repeat +// > 0 == built notification successfully +static long build_mediation_unotif(struct aa_listener *listener, + struct aa_knotif *knotif, + void __user *buf, u16 max_size, + u16 version) +{ + long ret; + + switch (knotif->ad->class) { + case AA_CLASS_FILE: + if (listener->version == APPARMOR_NOTIFY_V3 || + listener->version == APPARMOR_NOTIFY_V5) { + ret = build_v35_unotif(listener->version, knotif, + buf, max_size); + if (ret < 0) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: (error=%ld) failed to copy data to user reading size %ld, maxsize %d", + knotif->id, ret, + sizeof(union apparmor_notif_all), max_size); + goto out; + } + } else { + ret = -EPROTONOSUPPORT; + } + break; + default: + AA_BUG("unknown notification class"); + AA_DEBUG(DEBUG_UPCALL, "id %lld: unknown notification class", knotif->id); + /* skip and move onto the next notification */ + return 0; + } +out: + return ret; +} + +/* Handle the listener reading a notification into userspace */ +// TODO: output multiple messages in one recv +long aa_listener_unotif_recv(struct aa_listener *listener, void __user *buf, + u16 max_size, u16 version) +{ + struct aa_knotif *knotif; + long ret; + + do { + knotif = listener_pop_and_hold_knotif(listener); + if (!knotif) { + return -ENOENT; + } + AA_DEBUG(DEBUG_UPCALL, "id %lld: removed notif from listener queue", + knotif->id); + + ret = build_mediation_unotif(listener, knotif, buf, max_size, + version); + if (ret < 0) { + /* failed - drop notif and return error to reader */ + listener_complete_held_user_pending(listener, knotif); + return ret; + } else if (ret > 0) { + /* else notification copied */ + break; + } + /* unknown notification: drop and try next */ + listener_complete_held_user_pending(listener, knotif); + } while (ret == 0); + + /* success */ + if (knotif->ad->type == AUDIT_APPARMOR_USER) { + AA_DEBUG(DEBUG_UPCALL, "id %lld: adding notif to pending", knotif->id); + listener_append_held_user_pending(listener, knotif); + } else { + /* no one waiting on this notification drop it */ + AA_DEBUG(DEBUG_UPCALL, "id %lld: non-prompt audit notif delivered", knotif->id); + listener_complete_held_user_pending(listener, knotif); + } + + return ret; +} diff --git a/security/apparmor/path.c b/security/apparmor/path.c index 2494e810153841..4efa4960c9aebb 100644 --- a/security/apparmor/path.c +++ b/security/apparmor/path.c @@ -34,7 +34,16 @@ static int prepend(char **buffer, int buflen, const char *str, int namelen) #define CHROOT_NSCONNECT (PATH_CHROOT_REL | PATH_CHROOT_NSCONNECT) -/* If the path is not connected to the expected root, +/** + * aa_disconnect - handle paths not connected + * @path: path to lookup (NOT NULL) + * @buf: buffer to store path to (NOT NULL) + * @name: Returns - pointer for start of path name with in @buf (NOT NULL) + * @flags: profile flags perms controlling path lookup + * @flag_match: flags matching path lookup from enum path_flags + * @disconnected: string to prefix to disconnected paths + * + * If the path is not connected to the expected root, * check if it is a sysctl and handle specially else remove any * leading / that __d_path may have returned. * Unless @@ -45,12 +54,12 @@ static int prepend(char **buffer, int buflen, const char *str, int namelen) * of chroot) and specifically directed to connect paths to * namespace root. */ -static int disconnect(const struct path *path, char *buf, char **name, - int flags, const char *disconnected) +int aa_disconnect(const struct path *path, char *buf, char **name, + int flags, int flags_match, const char *disconnected) { int error = 0; - if (!(flags & PATH_CONNECT_PATH) && + if (!(flags & flags_match) && !(((flags & CHROOT_NSCONNECT) == CHROOT_NSCONNECT) && our_mnt(path->mnt))) { /* disconnected path, don't return pathname starting @@ -110,8 +119,9 @@ static int d_namespace_path(const struct path *path, char *buf, char **name, error = prepend(name, *name - buf, "/proc", 5); goto out; } else - error = disconnect(path, buf, name, flags, - disconnected); + error = aa_disconnect(path, buf, name, flags, + PATH_CONNECT_PATH, + disconnected); goto out; } @@ -149,7 +159,8 @@ static int d_namespace_path(const struct path *path, char *buf, char **name, *name = res; if (!connected) - error = disconnect(path, buf, name, flags, disconnected); + error = aa_disconnect(path, buf, name, flags, + PATH_CONNECT_PATH, disconnected); /* Handle two cases: * 1. A deleted dentry && profile is not allowing mediation of deleted diff --git a/security/apparmor/policy.c b/security/apparmor/policy.c index 94b4a7e727cc1d..5efc344cad6d45 100644 --- a/security/apparmor/policy.c +++ b/security/apparmor/policy.c @@ -88,7 +88,11 @@ #include "include/resource.h" int unprivileged_userns_apparmor_policy = 1; +int aa_unprivileged_userns_restricted = IS_ENABLED(CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS); +int aa_unprivileged_userns_restricted_force; +int aa_unprivileged_userns_restricted_complain; int aa_unprivileged_unconfined_restricted; +int aa_unprivileged_uring_restricted; const char *const aa_profile_mode_names[] = { "enforce", @@ -337,8 +341,17 @@ void aa_free_profile(struct aa_profile *profile) aa_put_ns(profile->ns); kfree_sensitive(profile->rename); kfree_sensitive(profile->disconnected); + /* + * If disconnected is specified while disconnected_ipc is not, + * disconnected_ipc will be set to disconnected in unpack_profile(). + * Thus, we need to check that the pointers are distinct in order to + * prevent a double free. + */ + if (profile->disconnected_ipc != profile->disconnected) + kfree_sensitive(profile->disconnected_ipc); free_attachment(&profile->attach); + kfree_sensitive(profile->net_compat); /* * at this point there are no tasks that can have a reference @@ -359,6 +372,7 @@ void aa_free_profile(struct aa_profile *profile) kfree_sensitive(profile->hash); aa_put_profile_loaddata(profile->rawdata); aa_label_destroy(&profile->label); + aa_audit_cache_destroy(&profile->learning_cache); kfree_sensitive(profile); } @@ -409,6 +423,8 @@ struct aa_profile *aa_alloc_profile(const char *hname, struct aa_proxy *proxy, profile->label.vec[0] = profile; profile->signal = SIGKILL; + aa_audit_cache_init(&profile->learning_cache); + /* refcount released by caller */ return profile; @@ -1341,7 +1357,8 @@ ssize_t aa_replace_profiles(struct aa_ns *policy_ns, struct aa_label *label, list_del_init(&ent->list); op = (!ent->old && !ent->rename) ? OP_PROF_LOAD : OP_PROF_REPL; - if (ent->old && ent->old->rawdata == ent->new->rawdata && + if (ent->old && ent->old->learning_cache.size == 0 && + ent->old->rawdata == ent->new->rawdata && ent->new->rawdata) { /* dedup actual profile replacement */ audit_policy(label, op, ns_name, ent->new->base.hname, diff --git a/security/apparmor/policy_compat.c b/security/apparmor/policy_compat.c index 5fc16d56fbf4ec..08a7a9d825ea42 100644 --- a/security/apparmor/policy_compat.c +++ b/security/apparmor/policy_compat.c @@ -107,6 +107,8 @@ static void compute_fperms_allow(struct aa_perms *perms, struct aa_dfa *dfa, perms->allow |= AA_MAY_CHANGE_PROFILE; if (ACCEPT_TABLE(dfa)[state] & 0x40000000) perms->allow |= AA_MAY_ONEXEC; + if (ACCEPT_TABLE(dfa)[state] & 0x10000000) + perms->allow |= AA_CONT_MATCH; } static struct aa_perms compute_fperms_user(struct aa_dfa *dfa, @@ -216,6 +218,8 @@ static struct aa_perms compute_perms_entry(struct aa_dfa *dfa, perms.allow = dfa_user_allow(dfa, state); perms.audit = dfa_user_audit(dfa, state); perms.quiet = dfa_user_quiet(dfa, state); + if (ACCEPT_TABLE(dfa)[state] & 0x10000000) + perms.allow |= AA_CONT_MATCH; /* * This mapping is convulated due to history. diff --git a/security/apparmor/policy_ns.c b/security/apparmor/policy_ns.c index 5a907a875d8f6c..9b8278a5968353 100644 --- a/security/apparmor/policy_ns.c +++ b/security/apparmor/policy_ns.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "include/apparmor.h" #include "include/cred.h" @@ -117,6 +118,8 @@ static struct aa_ns *alloc_ns(const char *prefix, const char *name) INIT_LIST_HEAD(&ns->rawdata_list); mutex_init(&ns->lock); init_waitqueue_head(&ns->wait); + spin_lock_init(&ns->listener_lock); + INIT_LIST_HEAD(&ns->listeners); /* released by aa_free_ns() */ ns->unconfined = alloc_unconfined("unconfined"); diff --git a/security/apparmor/policy_unpack.c b/security/apparmor/policy_unpack.c index d9dcff167c4801..d118bf3b2ec476 100644 --- a/security/apparmor/policy_unpack.c +++ b/security/apparmor/policy_unpack.c @@ -287,6 +287,19 @@ static bool unpack_u8(struct aa_ext *e, u8 *data, const char *name) return false; } +VISIBLE_IF_KUNIT bool unpack_u16(struct aa_ext *e, u16 *data, const char *name) +{ + if (aa_unpack_nameX(e, AA_U16, name)) { + if (!aa_inbounds(e, sizeof(u16))) + return 0; + if (data) + *data = le16_to_cpu(get_unaligned((__le16 *) e->pos)); + e->pos += sizeof(u16); + return 1; + } + return 0; +} + VISIBLE_IF_KUNIT bool aa_unpack_u32(struct aa_ext *e, u32 *data, const char *name) { void *pos = e->pos; @@ -1117,9 +1130,10 @@ static struct aa_profile *unpack_profile(struct aa_ext *e, char **ns_name) struct aa_profile *profile = NULL; const char *tmpname, *tmpns = NULL, *name = NULL; const char *info = "failed to unpack profile"; + u16 size = 0; size_t ns_len; struct rhashtable_params params = { 0 }; - char *key = NULL, *disconnected = NULL; + char *key = NULL, *disconnected = NULL, *disconnected_ipc = NULL; struct aa_data *data; int error = -EPROTO; kernel_cap_t tmpcap; @@ -1192,6 +1206,12 @@ static struct aa_profile *unpack_profile(struct aa_ext *e, char **ns_name) (void) aa_unpack_strdup(e, &disconnected, "disconnected"); profile->disconnected = disconnected; + /* disconnected attachment for ipc string is optional + * but it fallbacks to the plain disconnected if not present + */ + (void) aa_unpack_strdup(e, &disconnected_ipc, "disconnected_ipc"); + profile->disconnected_ipc = disconnected_ipc ? disconnected_ipc : disconnected; + /* optional */ (void) aa_unpack_u32(e, &profile->signal, "kill"); if (profile->signal < 1 || profile->signal > MAXMAPPED_SIG) { @@ -1212,6 +1232,8 @@ static struct aa_profile *unpack_profile(struct aa_ext *e, char **ns_name) profile->label.flags |= FLAG_DEBUG1; if (tmp & PACKED_FLAG_DEBUG2) profile->label.flags |= FLAG_DEBUG2; + if (tmp & PACKED_FLAG_INTERRUPTIBLE) + profile->label.flags |= FLAG_INTERRUPTIBLE; if (!aa_unpack_u32(e, &tmp, NULL)) goto fail; if (tmp == PACKED_MODE_COMPLAIN || (e->version & FORCE_COMPLAIN_FLAG)) { @@ -1295,6 +1317,45 @@ static struct aa_profile *unpack_profile(struct aa_ext *e, char **ns_name) goto fail; } + if (aa_unpack_array(e, "net_allowed_af", &size) || + VERSION_LT(e->version, v8)) { + u16 i; + + profile->net_compat = kzalloc(sizeof(struct aa_net_compat), + GFP_KERNEL); + if (!profile->net_compat) { + info = "out of memory"; + goto fail; + } + for (i = 0; i < size; i++) { + /* discard extraneous rules that this kernel will + * never request + */ + if (i >= AF_MAX) { + u16 tmp; + + if (!unpack_u16(e, &tmp, NULL) || + !unpack_u16(e, &tmp, NULL) || + !unpack_u16(e, &tmp, NULL)) + goto fail; + continue; + } + if (!unpack_u16(e, &profile->net_compat->allow[i], NULL)) + goto fail; + if (!unpack_u16(e, &profile->net_compat->audit[i], NULL)) + goto fail; + if (!unpack_u16(e, &profile->net_compat->quiet[i], NULL)) + goto fail; + } + if (size && !aa_unpack_nameX(e, AA_ARRAYEND, NULL)) + goto fail; + if (VERSION_LT(e->version, v7)) { + /* pre v7 policy always allowed these */ + profile->net_compat->allow[AF_UNIX] = 0xffff; + profile->net_compat->allow[AF_NETLINK] = 0xffff; + } + } + if (aa_unpack_nameX(e, AA_STRUCT, "policydb")) { /* generic policy dfa - optional and may be NULL */ info = "failed to unpack policydb"; diff --git a/security/apparmor/task.c b/security/apparmor/task.c index b9fb3738124e05..88c13c5fcf977d 100644 --- a/security/apparmor/task.c +++ b/security/apparmor/task.c @@ -334,7 +334,14 @@ static void audit_ns_cb(struct audit_buffer *ab, void *va) if (ad->denied & AA_USERNS_CREATE) audit_log_format(ab, " denied=\"userns_create\""); - + if (ad->peer) { + audit_log_format(ab, " target="); + aa_label_xaudit(ab, labels_ns(ad->subj_label), ad->peer, + FLAG_VIEW_SUBNS, GFP_KERNEL); + } else if (ad->ns.target) { + audit_log_format(ab, " target="); + audit_log_untrustedstring(ab, ad->ns.target); + } buffer = aa_get_buffer(false); if (!buffer) return; // OOM @@ -344,29 +351,157 @@ static void audit_ns_cb(struct audit_buffer *ab, void *va) aa_put_buffer(buffer); } -int aa_profile_ns_perm(struct aa_profile *profile, - struct apparmor_audit_data *ad, - u32 request) +/* + * Returns: refcounted label to change to, even if no change + * PTR_ERR on failure + */ +static struct aa_label *ns_x_to_label(struct aa_profile *profile, + u32 xindex, const char **lookupname, + const char **info) +{ + struct aa_label *new = NULL; + u32 xtype = xindex & AA_X_TYPE_MASK; + struct aa_label *stack = NULL; + + /* must be none or table */ + switch (xtype) { + case AA_X_NONE: + /* default not failure */ + *lookupname = NULL; + return NULL; + break; + case AA_X_TABLE: + /* TODO: fix when perm mapping done at unload */ + /* released by caller + * if null for both stack and direct want to try fallback + */ + new = x_table_lookup(profile, xindex, lookupname); + if (!new) { + *info = "failed to find transition profile"; + return ERR_PTR(-ENOMEM); + } + if (**lookupname == '&') { + stack = new; + new = NULL; + } + break; + default: + *info = "invalid profile transition type"; + return ERR_PTR(-EINVAL); + break; + } + + /* stack is true if !new */ + if (!new) { + if (xindex & AA_X_UNCONFINED) { + new = aa_get_newest_label(ns_unconfined(profile->ns)); + *info = "ux fallback"; + } else { + if (xindex & AA_X_INHERIT) { + /* (p|c|n)ix - don't change profile but do + * use the newest version + */ + *info = "ix fallback"; + /* no profile && no error */ + } /* else, stack is implicitly against current */ + new = aa_get_newest_label(&profile->label); + } + } + + if (stack) { + /* base the stack on post domain transition */ + struct aa_label *base = new; + + new = aa_label_merge(base, stack, GFP_KERNEL); + /* null on error */ + aa_put_label(base); + aa_put_label(stack); + if (!new) + return ERR_PTR(-ENOMEM); + } + + /* released by caller */ + return new; +} + +struct aa_label *aa_profile_ns_perm(struct aa_profile *profile, + struct apparmor_audit_data *ad, + u32 request) { + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_label *new; struct aa_perms perms = { }; - int error = 0; + aa_state_t state; ad->subj_label = &profile->label; ad->request = request; + int error; + + + /* TODO: rework unconfined profile/dfa to mediate user ns, then + * we can drop the unconfined test + */ + state = RULE_MEDIATES(rules, ad->class); + if (!state) { + /* TODO: this gets replaced when the default unconfined + * profile dfa gets updated to handle this + */ + if (profile_unconfined(profile) && + profile == profiles_ns(profile)->unconfined) { + if (!aa_unprivileged_userns_restricted || + ns_capable_noaudit(current_user_ns(), + CAP_SYS_ADMIN)) + return aa_get_newest_label(&profile->label); + ad->info = "User namespace creation restricted"; + /* unconfined unprivileged user */ + /* don't just return: allow complain mode to override */ +// hardcode unconfined transition for now + new = aa_label_parse(&profile->label, + "unprivileged_userns", GFP_KERNEL, + true, false); + if (IS_ERR(new)) { + ad->info = "Userns create restricted - failed to find unprivileged_userns profile"; + ad->error = PTR_ERR(new); + ad->ns.target = "unprivileged_userns"; + new = NULL; + perms.deny |= request; + goto hard_coded; + } + ad->info = "Userns create - transitioning profile"; + perms.audit = request; + perms.allow = request; + goto hard_coded; +// once we have special unconfined profile, jump to ns_x_to_label() +// end hardcode + } else if (!aa_unprivileged_userns_restricted_force) { + return aa_get_newest_label(&profile->label); + } + /* continue to mediation */ + } - if (!profile_unconfined(profile)) { - struct aa_ruleset *rules = profile->label.rules[0]; - aa_state_t state; - - state = RULE_MEDIATES(rules, ad->class); - if (!state) - /* TODO: add flag to complain about unmediated */ - return 0; - perms = *aa_lookup_perms(rules->policy, state); - aa_apply_modes_to_perms(profile, &perms); - error = aa_check_perms(profile, &perms, request, ad, - audit_ns_cb); + perms = *aa_lookup_perms(rules->policy, state); + new = ns_x_to_label(profile, perms.xindex, &ad->ns.target, &ad->info); + if (IS_ERR(new)) { + ad->error = PTR_ERR(new); + new = NULL; + perms.deny |= request; + } else if (!new) { + /* no transition - not done in x_to_label so we can track */ + new = aa_get_label(&profile->label); + } else { +hard_coded: + ad->peer = new; } + if (aa_unprivileged_userns_restricted_complain) + perms.complain = ALL_PERMS_MASK; + // TODO: nnp + // TODO: complain mode support for transitions - return error; + aa_apply_modes_to_perms(profile, &perms); + error = aa_check_perms(profile, &perms, request, ad, audit_ns_cb); + if (error) { + aa_put_label(new); + return ERR_PTR(error); + } + return new; } diff --git a/security/integrity/digsig.c b/security/integrity/digsig.c index 1ed686154d7a8b..791bcffa4e8e55 100644 --- a/security/integrity/digsig.c +++ b/security/integrity/digsig.c @@ -203,7 +203,7 @@ int __init integrity_load_x509(const unsigned int id, const char *path) rc = kernel_read_file_from_path(path, 0, &data, INT_MAX, NULL, READING_X509_CERTIFICATE); if (rc < 0) { - pr_err("Unable to open file: %s (%d)", path, rc); + pr_warn("Unable to open file: %s (%d)", path, rc); return rc; } size = rc; diff --git a/security/integrity/ima/ima_fs.c b/security/integrity/ima/ima_fs.c index 174a94740da1ac..5c6c52a987f335 100644 --- a/security/integrity/ima/ima_fs.c +++ b/security/integrity/ima/ima_fs.c @@ -539,7 +539,7 @@ static ssize_t ima_read_policy(char *path) rc = kernel_read_file_from_path(path, 0, &data, INT_MAX, NULL, READING_POLICY); if (rc < 0) { - pr_err("Unable to open file: %s (%d)", path, rc); + pr_warn("Unable to open file: %s (%d)", path, rc); return rc; } size = rc; diff --git a/security/integrity/platform_certs/keyring_handler.c b/security/integrity/platform_certs/keyring_handler.c index 13ea1720790293..327c20154f0f44 100644 --- a/security/integrity/platform_certs/keyring_handler.c +++ b/security/integrity/platform_certs/keyring_handler.c @@ -40,6 +40,7 @@ static __init void uefi_blacklist_binary(const char *source, static __init void uefi_revocation_list_x509(const char *source, const void *data, size_t len) { + pr_info("Revoking X.509 certificate: %s\n", source); add_key_to_revocation_list(data, len); } diff --git a/security/integrity/platform_certs/load_uefi.c b/security/integrity/platform_certs/load_uefi.c index c0d6948446c307..facdaa983a46bc 100644 --- a/security/integrity/platform_certs/load_uefi.c +++ b/security/integrity/platform_certs/load_uefi.c @@ -74,7 +74,8 @@ static __init void *get_cert_list(efi_char16_t *name, efi_guid_t *guid, return NULL; if (*status != EFI_BUFFER_TOO_SMALL) { - pr_err("Couldn't get size: 0x%lx\n", *status); + pr_err("Couldn't get size: %s (0x%lx)\n", + efi_status_to_str(*status), *status); return NULL; } @@ -85,7 +86,8 @@ static __init void *get_cert_list(efi_char16_t *name, efi_guid_t *guid, *status = efi.get_variable(name, guid, NULL, &lsize, db); if (*status != EFI_SUCCESS) { kfree(db); - pr_err("Error reading db var: 0x%lx\n", *status); + pr_err("Error reading db var: %s (0x%lx)\n", + efi_status_to_str(*status), *status); return NULL; } @@ -94,17 +96,18 @@ static __init void *get_cert_list(efi_char16_t *name, efi_guid_t *guid, } /* - * load_moklist_certs() - Load MokList certs + * load_moklist_certs() - Load Mok(X)List certs + * @load_db: Load MokListRT into db when true; MokListXRT into dbx when false * - * Load the certs contained in the UEFI MokListRT database into the - * platform trusted keyring. + * Load the certs contained in the UEFI MokList(X)RT database into the + * platform trusted/denied keyring. * * This routine checks the EFI MOK config table first. If and only if - * that fails, this routine uses the MokListRT ordinary UEFI variable. + * that fails, this routine uses the MokList(X)RT ordinary UEFI variable. * * Return: Status */ -static int __init load_moklist_certs(void) +static int __init load_moklist_certs(const bool load_db) { struct efi_mokvar_table_entry *mokvar_entry; efi_guid_t mok_var = EFI_SHIM_LOCK_GUID; @@ -112,41 +115,55 @@ static int __init load_moklist_certs(void) unsigned long moksize; efi_status_t status; int rc; + const char *mokvar_name = "MokListRT"; + /* Should be const, but get_cert_list() doesn't have it as const yet */ + efi_char16_t *efivar_name = L"MokListRT"; + const char *parse_mokvar_name = "UEFI:MokListRT (MOKvar table)"; + const char *parse_efivar_name = "UEFI:MokListRT"; + efi_element_handler_t (*get_handler_for_guid)(const efi_guid_t *) = get_handler_for_db; + + if (!load_db) { + mokvar_name = "MokListXRT"; + efivar_name = L"MokListXRT"; + parse_mokvar_name = "UEFI:MokListXRT (MOKvar table)"; + parse_efivar_name = "UEFI:MokListXRT"; + get_handler_for_guid = get_handler_for_dbx; + } /* First try to load certs from the EFI MOKvar config table. * It's not an error if the MOKvar config table doesn't exist * or the MokListRT entry is not found in it. */ - mokvar_entry = efi_mokvar_entry_find("MokListRT"); + mokvar_entry = efi_mokvar_entry_find(mokvar_name); if (mokvar_entry) { - rc = parse_efi_signature_list("UEFI:MokListRT (MOKvar table)", + rc = parse_efi_signature_list(parse_mokvar_name, mokvar_entry->data, mokvar_entry->data_size, - get_handler_for_mok); + get_handler_for_guid); /* All done if that worked. */ if (!rc) return rc; - pr_err("Couldn't parse MokListRT signatures from EFI MOKvar config table: %d\n", - rc); + pr_err("Couldn't parse %s signatures from EFI MOKvar config table: %d\n", + mokvar_name, rc); } /* Get MokListRT. It might not exist, so it isn't an error * if we can't get it. */ - mok = get_cert_list(L"MokListRT", &mok_var, &moksize, &status); + mok = get_cert_list(efivar_name, &mok_var, &moksize, &status); if (mok) { - rc = parse_efi_signature_list("UEFI:MokListRT", - mok, moksize, get_handler_for_mok); + rc = parse_efi_signature_list(parse_efivar_name, + mok, moksize, get_handler_for_guid); kfree(mok); if (rc) - pr_err("Couldn't parse MokListRT signatures: %d\n", rc); + pr_err("Couldn't parse %s signatures: %d\n", mokvar_name, rc); return rc; } if (status == EFI_NOT_FOUND) - pr_debug("MokListRT variable wasn't found\n"); + pr_debug("%s variable wasn't found\n", mokvar_name); else - pr_info("Couldn't get UEFI MokListRT\n"); + pr_info("Couldn't get UEFI %s\n", mokvar_name); return 0; } @@ -160,9 +177,8 @@ static int __init load_moklist_certs(void) static int __init load_uefi_certs(void) { efi_guid_t secure_var = EFI_IMAGE_SECURITY_DATABASE_GUID; - efi_guid_t mok_var = EFI_SHIM_LOCK_GUID; - void *db = NULL, *dbx = NULL, *mokx = NULL; - unsigned long dbsize = 0, dbxsize = 0, mokxsize = 0; + void *db = NULL, *dbx = NULL; + unsigned long dbsize = 0, dbxsize = 0; efi_status_t status; int rc = 0; const struct dmi_system_id *dmi_id; @@ -215,23 +231,15 @@ static int __init load_uefi_certs(void) if (!arch_get_secureboot()) return 0; - mokx = get_cert_list(L"MokListXRT", &mok_var, &mokxsize, &status); - if (!mokx) { - if (status == EFI_NOT_FOUND) - pr_debug("mokx variable wasn't found\n"); - else - pr_info("Couldn't get mokx list\n"); - } else { - rc = parse_efi_signature_list("UEFI:MokListXRT", - mokx, mokxsize, - get_handler_for_dbx); - if (rc) - pr_err("Couldn't parse mokx signatures %d\n", rc); - kfree(mokx); - } + /* Load the MokListXRT certs */ + rc = load_moklist_certs(false); + if (rc) + pr_err("Couldn't parse mokx signatures: %d\n", rc); /* Load the MokListRT certs */ - rc = load_moklist_certs(); + rc = load_moklist_certs(true); + if (rc) + pr_err("Couldn't parse mok signatures: %d\n", rc); return rc; } diff --git a/security/lockdown/Kconfig b/security/lockdown/Kconfig index e84ddf48401010..a598a4f95ee8d8 100644 --- a/security/lockdown/Kconfig +++ b/security/lockdown/Kconfig @@ -16,6 +16,19 @@ config SECURITY_LOCKDOWN_LSM_EARLY subsystem is fully initialised. If enabled, lockdown will unconditionally be called before any other LSMs. +config LOCK_DOWN_IN_SECURE_BOOT + bool "Lock down the kernel in Secure Boot mode" + default n + depends on (EFI || S390 || PPC) && SECURITY_LOCKDOWN_LSM_EARLY + help + Secure Boot provides a mechanism for ensuring that the firmware will + only load signed bootloaders and kernels. Secure boot mode + determination is platform-specific; examples include EFI secure boot + and SIPL on s390. + + Enabling this option results in kernel lockdown being triggered if + booted under secure boot. + choice prompt "Kernel default lockdown mode" default LOCK_DOWN_KERNEL_FORCE_NONE diff --git a/security/lockdown/lockdown.c b/security/lockdown/lockdown.c index 8d46886d2cca08..14a9cdff942b99 100644 --- a/security/lockdown/lockdown.c +++ b/security/lockdown/lockdown.c @@ -72,6 +72,17 @@ static int lockdown_is_locked_down(enum lockdown_reason what) return 0; } +/** + * security_lock_kernel_down() - Put the kernel into lock-down mode. + * + * @where: Where the lock-down is originating from (e.g. command line option) + * @level: The lock-down level (can only increase) + */ +int security_lock_kernel_down(const char *where, enum lockdown_reason level) +{ + return lock_kernel_down(where, level); +} + static struct security_hook_list lockdown_hooks[] __ro_after_init = { LSM_HOOK_INIT(locked_down, lockdown_is_locked_down), }; diff --git a/security/lsm_init.c b/security/lsm_init.c index 7c0fd17f1601f2..70c28507a3cf00 100644 --- a/security/lsm_init.c +++ b/security/lsm_init.c @@ -316,6 +316,14 @@ static void __init lsm_prepare(struct lsm_info *lsm) lsm_blob_size_update(&blobs->lbs_bpf_map, &blob_sizes.lbs_bpf_map); lsm_blob_size_update(&blobs->lbs_bpf_prog, &blob_sizes.lbs_bpf_prog); lsm_blob_size_update(&blobs->lbs_bpf_token, &blob_sizes.lbs_bpf_token); + + if (blobs->lbs_secmark) { + if (blob_sizes.lbs_secmark) + blobs->lbs_secmark = false; + else + blob_sizes.lbs_secmark = true; + } + } /** diff --git a/security/security.c b/security/security.c index 71aea8fdf01429..64885c10b4f4b7 100644 --- a/security/security.c +++ b/security/security.c @@ -514,6 +514,7 @@ int security_binder_set_context_mgr(const struct cred *mgr) { return call_int_hook(binder_set_context_mgr, mgr); } +EXPORT_SYMBOL(security_binder_set_context_mgr); /** * security_binder_transaction() - Check if a binder transaction is allowed @@ -529,6 +530,7 @@ int security_binder_transaction(const struct cred *from, { return call_int_hook(binder_transaction, from, to); } +EXPORT_SYMBOL(security_binder_transaction); /** * security_binder_transfer_binder() - Check if a binder transfer is allowed @@ -544,6 +546,7 @@ int security_binder_transfer_binder(const struct cred *from, { return call_int_hook(binder_transfer_binder, from, to); } +EXPORT_SYMBOL(security_binder_transfer_binder); /** * security_binder_transfer_file() - Check if a binder file xfer is allowed @@ -560,6 +563,7 @@ int security_binder_transfer_file(const struct cred *from, { return call_int_hook(binder_transfer_file, from, to, file); } +EXPORT_SYMBOL(security_binder_transfer_file); /** * security_ptrace_access_check() - Check if tracing is allowed @@ -3977,8 +3981,13 @@ EXPORT_SYMBOL(security_lsmprop_to_secctx); */ int security_secctx_to_secid(const char *secdata, u32 seclen, u32 *secid) { + struct lsm_static_call *scall; + *secid = 0; - return call_int_hook(secctx_to_secid, secdata, seclen, secid); + lsm_for_each_hook(scall, secctx_to_secid) { + return scall->hl->hook.secctx_to_secid(secdata, seclen, secid); + } + return LSM_RET_DEFAULT(secctx_to_secid); } EXPORT_SYMBOL(security_secctx_to_secid); @@ -4439,8 +4448,13 @@ EXPORT_SYMBOL(security_sock_rcv_skb); int security_socket_getpeersec_stream(struct socket *sock, sockptr_t optval, sockptr_t optlen, unsigned int len) { - return call_int_hook(socket_getpeersec_stream, sock, optval, optlen, - len); + struct lsm_static_call *scall; + + lsm_for_each_hook(scall, socket_getpeersec_stream) { + return scall->hl->hook.socket_getpeersec_stream(sock, optval, + optlen, len); + } + return LSM_RET_DEFAULT(socket_getpeersec_stream); } /** @@ -4460,7 +4474,13 @@ int security_socket_getpeersec_stream(struct socket *sock, sockptr_t optval, int security_socket_getpeersec_dgram(struct socket *sock, struct sk_buff *skb, u32 *secid) { - return call_int_hook(socket_getpeersec_dgram, sock, skb, secid); + struct lsm_static_call *scall; + + lsm_for_each_hook(scall, socket_getpeersec_dgram) { + return scall->hl->hook.socket_getpeersec_dgram(sock, skb, + secid); + } + return LSM_RET_DEFAULT(socket_getpeersec_dgram); } EXPORT_SYMBOL(security_socket_getpeersec_dgram); diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index 18dd28b2bb13d2..48d0bcda870fc4 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -166,7 +166,8 @@ __setup("checkreqprot=", checkreqprot_setup); */ static int selinux_secmark_enabled(void) { - return (selinux_policycap_alwaysnetwork() || + return selinux_blob_sizes.lbs_secmark && + (selinux_policycap_alwaysnetwork() || atomic_read(&selinux_secmark_refcount)); } @@ -7537,6 +7538,7 @@ struct lsm_blob_sizes selinux_blob_sizes __ro_after_init = { .lbs_bpf_map = sizeof(struct bpf_security_struct), .lbs_bpf_prog = sizeof(struct bpf_security_struct), .lbs_bpf_token = sizeof(struct bpf_security_struct), + .lbs_secmark = true, }; /* diff --git a/security/smack/smack.h b/security/smack/smack.h index 9b9eb262fe33e6..72341b765d77c8 100644 --- a/security/smack/smack.h +++ b/security/smack/smack.h @@ -400,6 +400,11 @@ static inline int smk_inode_transmutable(const struct inode *isp) return (sip->smk_flags & SMK_INODE_TRANSMUTE) != 0; } +static inline bool smack_secmark(void) +{ + return smack_blob_sizes.lbs_secmark; +} + /* * Present a pointer to the smack label entry in an inode blob. */ diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index ff115068c5c06f..5c662b7c0d52c2 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -4189,7 +4189,7 @@ static int smk_skb_to_addr_ipv6(struct sk_buff *skb, struct sockaddr_in6 *sip) #ifdef CONFIG_NETWORK_SECMARK static struct smack_known *smack_from_skb(struct sk_buff *skb) { - if (skb == NULL || skb->secmark == 0) + if (!smack_secmark() || skb == NULL || skb->secmark == 0) return NULL; return smack_from_secid(skb->secmark); @@ -5114,6 +5114,7 @@ struct lsm_blob_sizes smack_blob_sizes __ro_after_init = { .lbs_sock = sizeof(struct socket_smack), .lbs_superblock = sizeof(struct superblock_smack), .lbs_xattr_count = SMACK_INODE_INIT_XATTRS, + .lbs_secmark = true, }; static const struct lsm_id smack_lsmid = { diff --git a/security/smack/smack_netfilter.c b/security/smack/smack_netfilter.c index 17ba578b130887..1dcaba0d224ad3 100644 --- a/security/smack/smack_netfilter.c +++ b/security/smack/smack_netfilter.c @@ -26,7 +26,7 @@ static unsigned int smack_ip_output(void *priv, struct socket_smack *ssp; struct smack_known *skp; - if (sk) { + if (smack_secmark() && sk) { ssp = smack_sock(sk); skp = ssp->smk_out; skb->secmark = skp->smk_secid; @@ -54,12 +54,18 @@ static const struct nf_hook_ops smack_nf_ops[] = { static int __net_init smack_nf_register(struct net *net) { + if (!smack_secmark()) + return 0; + return nf_register_net_hooks(net, smack_nf_ops, ARRAY_SIZE(smack_nf_ops)); } static void __net_exit smack_nf_unregister(struct net *net) { + if (!smack_secmark()) + return; + nf_unregister_net_hooks(net, smack_nf_ops, ARRAY_SIZE(smack_nf_ops)); } @@ -70,7 +76,7 @@ static struct pernet_operations smack_net_ops = { int __init smack_nf_ip_init(void) { - if (smack_enabled == 0) + if (smack_enabled == 0 || !smack_secmark()) return 0; printk(KERN_DEBUG "Smack: Registering netfilter hooks\n"); diff --git a/sound/soc/codecs/lpass-macro-common.c b/sound/soc/codecs/lpass-macro-common.c index 6e3b8d0897dd62..7d2ff9fdf1497c 100644 --- a/sound/soc/codecs/lpass-macro-common.c +++ b/sound/soc/codecs/lpass-macro-common.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only // Copyright (c) 2022, The Linux Foundation. All rights reserved. +#include #include #include #include @@ -14,6 +15,10 @@ static DEFINE_MUTEX(lpass_codec_mutex); static enum lpass_codec_version lpass_codec_version; +static DEFINE_MUTEX(lpass_dmic_clk_mutex); +static void *lpass_dmic_clk_priv; +static const struct lpass_macro_dmic_clk_ops *lpass_dmic_clk_ops; + struct lpass_macro *lpass_macro_pds_init(struct device *dev) { struct lpass_macro *l_pds; @@ -89,5 +94,51 @@ enum lpass_codec_version lpass_macro_get_codec_version(void) } EXPORT_SYMBOL_GPL(lpass_macro_get_codec_version); +int lpass_macro_register_dmic_clk_provider(void *priv, const struct lpass_macro_dmic_clk_ops *ops) +{ + int ret = 0; + + if (!priv || !ops || !ops->request) + return -EINVAL; + + mutex_lock(&lpass_dmic_clk_mutex); + if (lpass_dmic_clk_priv && lpass_dmic_clk_priv != priv) { + ret = -EBUSY; + } else { + lpass_dmic_clk_priv = priv; + lpass_dmic_clk_ops = ops; + } + mutex_unlock(&lpass_dmic_clk_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(lpass_macro_register_dmic_clk_provider); + +void lpass_macro_unregister_dmic_clk_provider(void *priv) +{ + mutex_lock(&lpass_dmic_clk_mutex); + if (lpass_dmic_clk_priv == priv) { + lpass_dmic_clk_ops = NULL; + lpass_dmic_clk_priv = NULL; + } + mutex_unlock(&lpass_dmic_clk_mutex); +} +EXPORT_SYMBOL_GPL(lpass_macro_unregister_dmic_clk_provider); + +int lpass_macro_dmic_clk_request(unsigned int dmic, bool enable) +{ + int ret; + + mutex_lock(&lpass_dmic_clk_mutex); + if (!lpass_dmic_clk_ops) + ret = -ENODEV; + else + ret = lpass_dmic_clk_ops->request(lpass_dmic_clk_priv, dmic, enable); + mutex_unlock(&lpass_dmic_clk_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(lpass_macro_dmic_clk_request); + MODULE_DESCRIPTION("Common macro driver"); MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/lpass-macro-common.h b/sound/soc/codecs/lpass-macro-common.h index 10ad682019fa7b..7540d4fef88177 100644 --- a/sound/soc/codecs/lpass-macro-common.h +++ b/sound/soc/codecs/lpass-macro-common.h @@ -41,6 +41,13 @@ struct lpass_macro *lpass_macro_pds_init(struct device *dev); void lpass_macro_pds_exit(struct lpass_macro *pds); void lpass_macro_set_codec_version(enum lpass_codec_version version); enum lpass_codec_version lpass_macro_get_codec_version(void); +struct lpass_macro_dmic_clk_ops { + int (*request)(void *priv, unsigned int dmic, bool enable); +}; + +int lpass_macro_register_dmic_clk_provider(void *priv, const struct lpass_macro_dmic_clk_ops *ops); +void lpass_macro_unregister_dmic_clk_provider(void *priv); +int lpass_macro_dmic_clk_request(unsigned int dmic, bool enable); static inline void lpass_macro_pds_exit_action(void *pds) { diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c index 0cbf50647ff57c..7d8f2f98583adf 100644 --- a/sound/soc/codecs/lpass-tx-macro.c +++ b/sound/soc/codecs/lpass-tx-macro.c @@ -49,6 +49,7 @@ #define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n) #define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0) #define CDC_TX_MACRO_DMIC_MUX_SEL_MASK GENMASK(7, 4) +#define CDC_TX_MACRO_DEC_MUX_SEL_MASK GENMASK(1, 0) #define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100) #define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n) #define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104) @@ -285,6 +286,7 @@ struct tx_macro { int dec_mode[NUM_DECIMATORS]; struct lpass_macro *pds; bool bcs_clk_en; + bool sp11_va_dmic_active; }; #define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw) @@ -906,6 +908,63 @@ static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, return 1; } +static int tx_macro_sp11_va_dmic_request(struct snd_soc_component *component, + bool enable) +{ + struct tx_macro *tx = snd_soc_component_get_drvdata(component); + unsigned int dec0_src, dec1_src, dec0_dmic, dec1_dmic; + unsigned long expected = BIT(TX_MACRO_DEC0) | BIT(TX_MACRO_DEC1); + int ret, ret2; + + if (!of_machine_is_compatible("microsoft,denali")) + return 0; + + if (enable == tx->sp11_va_dmic_active) + return 0; + + if (!enable) { + ret = lpass_macro_dmic_clk_request(1, false); + ret2 = lpass_macro_dmic_clk_request(0, false); + if (!ret && ret2) + ret = ret2; + if (!ret) + tx->sp11_va_dmic_active = false; + return ret; + } + + if (tx->active_ch_mask[TX_MACRO_AIF1_CAP] != expected || + tx->active_ch_mask[TX_MACRO_AIF2_CAP] || + tx->active_ch_mask[TX_MACRO_AIF3_CAP]) + return -EINVAL; + + dec0_src = snd_soc_component_read(component, CDC_TX_INP_MUX_ADC_MUXn_CFG1(TX_MACRO_DEC0)); + dec0_src &= CDC_TX_MACRO_DEC_MUX_SEL_MASK; + dec1_src = snd_soc_component_read(component, CDC_TX_INP_MUX_ADC_MUXn_CFG1(TX_MACRO_DEC1)); + dec1_src &= CDC_TX_MACRO_DEC_MUX_SEL_MASK; + dec0_dmic = snd_soc_component_read(component, CDC_TX_INP_MUX_ADC_MUXn_CFG0(TX_MACRO_DEC0)); + dec0_dmic = FIELD_GET(CDC_TX_MACRO_DMIC_MUX_SEL_MASK, dec0_dmic); + dec1_dmic = snd_soc_component_read(component, CDC_TX_INP_MUX_ADC_MUXn_CFG0(TX_MACRO_DEC1)); + dec1_dmic = FIELD_GET(CDC_TX_MACRO_DMIC_MUX_SEL_MASK, dec1_dmic); + + /* Windows EP16 is DEC0 <- DMIC1 and DEC1 <- DMIC0, both MSM_DMIC. */ + if (dec0_src != MSM_DMIC || dec1_src != MSM_DMIC || + dec0_dmic != 2 || dec1_dmic != 1) + return -EINVAL; + + ret = lpass_macro_dmic_clk_request(1, true); + if (ret) + return ret; + + ret = lpass_macro_dmic_clk_request(0, true); + if (ret) { + lpass_macro_dmic_clk_request(1, false); + return ret; + } + + tx->sp11_va_dmic_active = true; + return 0; +} + static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -915,6 +974,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, u8 hpf_cut_off_freq; int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS; int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS; + int ret; u16 adc_mux_reg, adc_reg, adc_n, dmic; u16 dmic_clk_reg; struct tx_macro *tx = snd_soc_component_get_drvdata(component); @@ -949,6 +1009,9 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, CDC_TXn_PGA_MUTE_MASK, 0x1); break; case SND_SOC_DAPM_POST_PMU: + ret = tx_macro_sp11_va_dmic_request(component, true); + if (ret) + return ret; snd_soc_component_write_field(component, tx_vol_ctl_reg, CDC_TXn_CLK_EN_MASK, 0x1); if (!is_amic_enabled(component, tx, decimator)) { @@ -1047,6 +1110,9 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork); break; case SND_SOC_DAPM_POST_PMD: + ret = tx_macro_sp11_va_dmic_request(component, false); + if (ret) + return ret; snd_soc_component_write_field(component, tx_vol_ctl_reg, CDC_TXn_CLK_EN_MASK, 0x0); snd_soc_component_write_field(component, dec_cfg_reg, diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-macro.c index 58a5798823d7fd..b043dc06e16425 100644 --- a/sound/soc/codecs/lpass-va-macro.c +++ b/sound/soc/codecs/lpass-va-macro.c @@ -7,10 +7,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -723,6 +725,16 @@ static int va_dmic_clk_enable(struct snd_soc_component *component, return 0; } +static int va_macro_shared_dmic_clk_request(void *priv, unsigned int dmic, + bool enable) +{ + return va_dmic_clk_enable(priv, dmic, enable); +} + +static const struct lpass_macro_dmic_clk_ops va_macro_dmic_clk_ops = { + .request = va_macro_shared_dmic_clk_request, +}; + static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -1330,15 +1342,31 @@ static const struct snd_kcontrol_new va_macro_snd_controls[] = { static int va_macro_component_probe(struct snd_soc_component *component) { struct va_macro *va = snd_soc_component_get_drvdata(component); + int ret; snd_soc_component_init_regmap(component, va->regmap); + if (!of_machine_is_compatible("microsoft,denali")) + return 0; + + ret = lpass_macro_register_dmic_clk_provider(component, &va_macro_dmic_clk_ops); + if (ret) + return dev_err_probe(component->dev, ret, + "failed to register shared DMIC clock provider\n"); + return 0; } +static void va_macro_component_remove(struct snd_soc_component *component) +{ + if (of_machine_is_compatible("microsoft,denali")) + lpass_macro_unregister_dmic_clk_provider(component); +} + static const struct snd_soc_component_driver va_macro_component_drv = { .name = "VA MACRO", .probe = va_macro_component_probe, + .remove = va_macro_component_remove, .controls = va_macro_snd_controls, .num_controls = ARRAY_SIZE(va_macro_snd_controls), .dapm_widgets = va_macro_dapm_widgets, @@ -1353,18 +1381,22 @@ static int fsgen_gate_enable(struct clk_hw *hw) struct regmap *regmap = va->regmap; int ret; - if (va->has_swr_master) { - ret = clk_prepare_enable(va->mclk); - if (ret) - return ret; + ret = pm_runtime_get_sync(va->dev); + if (ret < 0) { + pm_runtime_put_noidle(va->dev); + return ret; } ret = va_macro_mclk_enable(va, true); + if (ret) { + pm_runtime_put_noidle(va->dev); + return ret; + } if (va->has_swr_master) regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL, CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE); - return ret; + return 0; } static void fsgen_gate_disable(struct clk_hw *hw) @@ -1377,8 +1409,24 @@ static void fsgen_gate_disable(struct clk_hw *hw) CDC_VA_SWR_CLK_EN_MASK, 0x0); va_macro_mclk_enable(va, false); - if (va->has_swr_master) - clk_disable_unprepare(va->mclk); + + pm_runtime_mark_last_busy(va->dev); + pm_runtime_put_autosuspend(va->dev); +} + +static int va_macro_setup_pm_clocks(struct device *dev, struct va_macro *va) +{ + int ret; + + ret = devm_pm_clk_create(dev); + if (ret) + return ret; + + ret = of_pm_clk_add_clks(dev); + if (ret < 0) + return ret; + + return 0; } static int fsgen_gate_is_enabled(struct clk_hw *hw) @@ -1433,6 +1481,14 @@ static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate, u32 div_factor; u32 mclk_rate = VA_MACRO_MCLK_FREQ; + /* + * Native Windows on Surface Pro 11 (Denali) votes the VA MCLK at + * 19.2 MHz and programs the DMIC clock selector from that rate. + * Linux already requests that same 19.2 MHz MCLK in probe. + */ + if (of_machine_is_compatible("microsoft,denali")) + mclk_rate = 2 * VA_MACRO_MCLK_FREQ; + if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0) goto undefined_rate; @@ -1539,6 +1595,7 @@ static int va_macro_probe(struct platform_device *pdev) void __iomem *base; u32 sample_rate = 0; int ret; + int rpm_ret; va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL); if (!va) @@ -1606,22 +1663,18 @@ static int va_macro_probe(struct platform_device *pdev) clk_set_rate(va->npl, 2 * VA_MACRO_MCLK_FREQ); } - ret = clk_prepare_enable(va->macro); - if (ret) - goto err; - - ret = clk_prepare_enable(va->dcodec); + ret = va_macro_setup_pm_clocks(dev, va); if (ret) - goto err_dcodec; + goto err_rpm_disable; - ret = clk_prepare_enable(va->mclk); - if (ret) - goto err_mclk; + pm_runtime_set_autosuspend_delay(dev, 3000); + pm_runtime_use_autosuspend(dev); + pm_runtime_enable(dev); - if (va->has_npl_clk) { - ret = clk_prepare_enable(va->npl); - if (ret) - goto err_npl; + rpm_ret = pm_runtime_resume_and_get(dev); + if (rpm_ret < 0) { + ret = rpm_ret; + goto err_rpm_disable; } /** @@ -1634,7 +1687,7 @@ static int va_macro_probe(struct platform_device *pdev) /* read version from register */ ret = va_macro_set_lpass_codec_version(va); if (ret) - goto err_clkout; + goto err_rpm_put; } if (va->has_swr_master) { @@ -1664,35 +1717,27 @@ static int va_macro_probe(struct platform_device *pdev) va_macro_dais, ARRAY_SIZE(va_macro_dais)); if (ret) - goto err_clkout; - - pm_runtime_set_autosuspend_delay(dev, 3000); - pm_runtime_use_autosuspend(dev); - pm_runtime_mark_last_busy(dev); - pm_runtime_set_active(dev); - pm_runtime_enable(dev); + goto err_rpm_put; ret = va_macro_register_fsgen_output(va); if (ret) - goto err_clkout; + goto err_rpm_put; va->fsgen = devm_clk_hw_get_clk(dev, &va->hw, "fsgen"); if (IS_ERR(va->fsgen)) { ret = PTR_ERR(va->fsgen); - goto err_clkout; + goto err_rpm_put; } + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + return 0; -err_clkout: - if (va->has_npl_clk) - clk_disable_unprepare(va->npl); -err_npl: - clk_disable_unprepare(va->mclk); -err_mclk: - clk_disable_unprepare(va->dcodec); -err_dcodec: - clk_disable_unprepare(va->macro); +err_rpm_put: + pm_runtime_put_noidle(dev); +err_rpm_disable: + pm_runtime_disable(dev); err: lpass_macro_pds_exit(va->pds); @@ -1703,12 +1748,7 @@ static void va_macro_remove(struct platform_device *pdev) { struct va_macro *va = dev_get_drvdata(&pdev->dev); - if (va->has_npl_clk) - clk_disable_unprepare(va->npl); - - clk_disable_unprepare(va->mclk); - clk_disable_unprepare(va->dcodec); - clk_disable_unprepare(va->macro); + pm_runtime_disable(&pdev->dev); lpass_macro_pds_exit(va->pds); } @@ -1720,12 +1760,7 @@ static int va_macro_runtime_suspend(struct device *dev) regcache_cache_only(va->regmap, true); regcache_mark_dirty(va->regmap); - if (va->has_npl_clk) - clk_disable_unprepare(va->npl); - - clk_disable_unprepare(va->mclk); - - return 0; + return pm_clk_suspend(dev); } static int va_macro_runtime_resume(struct device *dev) @@ -1733,25 +1768,13 @@ static int va_macro_runtime_resume(struct device *dev) struct va_macro *va = dev_get_drvdata(dev); int ret; - ret = clk_prepare_enable(va->mclk); - if (ret) { - dev_err(va->dev, "unable to prepare mclk\n"); + ret = pm_clk_resume(dev); + if (ret) return ret; - } - - if (va->has_npl_clk) { - ret = clk_prepare_enable(va->npl); - if (ret) { - clk_disable_unprepare(va->mclk); - dev_err(va->dev, "unable to prepare npl\n"); - return ret; - } - } regcache_cache_only(va->regmap, false); - regcache_sync(va->regmap); - return 0; + return regcache_sync(va->regmap); } diff --git a/sound/soc/codecs/lpass-wsa-macro.c b/sound/soc/codecs/lpass-wsa-macro.c index af521e0988db09..fae7b13f3d41bd 100644 --- a/sound/soc/codecs/lpass-wsa-macro.c +++ b/sound/soc/codecs/lpass-wsa-macro.c @@ -54,6 +54,18 @@ #define CDC_WSA_RX_MIX_TX0_SEL_MASK GENMASK(2, 0) #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (0x0114) #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (0x0118) +/* SP11 Windows qcaucd-proven VBAT/BCL producer block */ +#define CDC_WSA_VBAT_BCL_VBAT_PATH_CTL (0x0180) +#define CDC_WSA_VBAT_BCL_VBAT_CFG (0x0184) +#define CDC_WSA_VBAT_BCL_GAIN_UPD1 (0x01DC) +#define CDC_WSA_VBAT_BCL_GAIN_UPD2 (0x01E0) +#define CDC_WSA_VBAT_BCL_GAIN_UPD3 (0x01E4) +#define CDC_WSA_VBAT_BCL_GAIN_UPD4 (0x01E8) +#define CDC_WSA_VBAT_BCL_GAIN_UPD5 (0x01EC) +#define CDC_WSA_VBAT_BCL_GAIN_UPD6 (0x01F0) +#define CDC_WSA_VBAT_BCL_GAIN_UPD7 (0x01F4) +#define CDC_WSA_VBAT_BCL_GAIN_UPD8 (0x01F8) +#define CDC_WSA_VBAT_BCL_GAIN_UPD9 (0x01FC) #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL (0x0244) #define CDC_WSA_TX_SPKR_PROT_RESET_MASK BIT(5) #define CDC_WSA_TX_SPKR_PROT_RESET BIT(5) @@ -201,7 +213,7 @@ #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758) #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C) #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (0x0760) -#define WSA_MAX_OFFSET (0x0760) +#define WSA_MAX_OFFSET (0x0908) /* LPASS codec version <=2.4 register offsets */ #define CDC_WSA_COMPANDER1_CTL0 (0x05C0) @@ -261,6 +273,9 @@ #define CDC_2_5_WSA_SOFTCLIP0_SOFTCLIP_CTRL (0x0644) #define CDC_2_5_WSA_SOFTCLIP1_CRC (0x0660) #define CDC_2_5_WSA_SOFTCLIP1_SOFTCLIP_CTRL (0x0664) +#define CDC_2_5_WSA_CB_DECODE_CTL0 (0x0900) +#define CDC_2_5_WSA_CB_DECODE_CTL1 (0x0904) +#define CDC_2_5_WSA_CB_DECODE_CMD (0x0908) #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ @@ -285,6 +300,7 @@ #define WSA_MACRO_RX_PATH_OFFSET 0x80 #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10 #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C +#define WSA_MACRO_SOFTCLIP_CTRL_OFFSET 0x4 #define WSA_MACRO_FS_RATE_MASK 0x0F #define WSA_MACRO_EC_MIX_TX0_MASK 0x03 #define WSA_MACRO_EC_MIX_TX1_MASK 0x18 @@ -373,6 +389,7 @@ enum { WSA_MACRO_AIF_MIX1_PB, WSA_MACRO_AIF_VI, WSA_MACRO_AIF_ECHO, + WSA_MACRO_AIF_CPS, WSA_MACRO_MAX_DAIS, }; @@ -622,7 +639,7 @@ static const struct reg_default wsa_defaults[] = { { CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, { CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, { CDC_WSA_TOP_TOP_CFG0, 0x00}, - { CDC_WSA_TOP_TOP_CFG1, 0x00}, + { CDC_WSA_TOP_TOP_CFG1, 0x03}, { CDC_WSA_TOP_FREQ_MCLK, 0x00}, { CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00}, { CDC_WSA_TOP_DEBUG_EN0, 0x00}, @@ -652,7 +669,7 @@ static const struct reg_default wsa_defaults[] = { { CDC_WSA_INTR_CTRL_SET0, 0x00}, { CDC_WSA_RX0_RX_PATH_CTL, 0x04}, { CDC_WSA_RX0_RX_PATH_CFG0, 0x00}, - { CDC_WSA_RX0_RX_PATH_CFG1, 0x64}, + { CDC_WSA_RX0_RX_PATH_CFG1, 0x6C}, { CDC_WSA_RX0_RX_PATH_CFG2, 0x8F}, { CDC_WSA_RX0_RX_PATH_CFG3, 0x00}, { CDC_WSA_RX0_RX_VOL_CTL, 0x00}, @@ -670,7 +687,7 @@ static const struct reg_default wsa_defaults[] = { { CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00}, { CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00}, { CDC_WSA_RX1_RX_PATH_CFG0, 0x00}, - { CDC_WSA_RX1_RX_PATH_CFG1, 0x64}, + { CDC_WSA_RX1_RX_PATH_CFG1, 0x6C}, { CDC_WSA_RX1_RX_PATH_CFG2, 0x8F}, { CDC_WSA_RX1_RX_PATH_CFG3, 0x00}, { CDC_WSA_RX1_RX_VOL_CTL, 0x00}, @@ -702,7 +719,7 @@ static const struct reg_default wsa_defaults[] = { { CDC_WSA_COMPANDER0_CTL4, 0xFF}, { CDC_WSA_COMPANDER0_CTL5, 0x00}, { CDC_WSA_COMPANDER0_CTL6, 0x01}, - { CDC_WSA_COMPANDER0_CTL7, 0x28}, + { CDC_WSA_COMPANDER0_CTL7, 0x2E}, { CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00}, { CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01}, { CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00}, @@ -765,12 +782,12 @@ static const struct reg_default wsa_defaults_v2_5[] = { { CDC_2_5_WSA_COMPANDER0_CTL8, 0x00}, { CDC_2_5_WSA_COMPANDER0_CTL9, 0x00}, { CDC_2_5_WSA_COMPANDER0_CTL10, 0x06}, - { CDC_2_5_WSA_COMPANDER0_CTL11, 0x12}, - { CDC_2_5_WSA_COMPANDER0_CTL12, 0x1E}, - { CDC_2_5_WSA_COMPANDER0_CTL13, 0x24}, - { CDC_2_5_WSA_COMPANDER0_CTL14, 0x24}, - { CDC_2_5_WSA_COMPANDER0_CTL15, 0x24}, - { CDC_2_5_WSA_COMPANDER0_CTL16, 0x00}, + { CDC_2_5_WSA_COMPANDER0_CTL11, 0x0C}, + { CDC_2_5_WSA_COMPANDER0_CTL12, 0x15}, + { CDC_2_5_WSA_COMPANDER0_CTL13, 0x15}, + { CDC_2_5_WSA_COMPANDER0_CTL14, 0x15}, + { CDC_2_5_WSA_COMPANDER0_CTL15, 0x15}, + { CDC_2_5_WSA_COMPANDER0_CTL16, 0x0F}, { CDC_2_5_WSA_COMPANDER0_CTL17, 0x24}, { CDC_2_5_WSA_COMPANDER0_CTL18, 0x2A}, { CDC_2_5_WSA_COMPANDER0_CTL19, 0x16}, @@ -781,16 +798,16 @@ static const struct reg_default wsa_defaults_v2_5[] = { { CDC_2_5_WSA_COMPANDER1_CTL4, 0xFF}, { CDC_2_5_WSA_COMPANDER1_CTL5, 0x00}, { CDC_2_5_WSA_COMPANDER1_CTL6, 0x01}, - { CDC_2_5_WSA_COMPANDER1_CTL7, 0x28}, + { CDC_2_5_WSA_COMPANDER1_CTL7, 0x2E}, { CDC_2_5_WSA_COMPANDER1_CTL8, 0x00}, { CDC_2_5_WSA_COMPANDER1_CTL9, 0x00}, { CDC_2_5_WSA_COMPANDER1_CTL10, 0x06}, - { CDC_2_5_WSA_COMPANDER1_CTL11, 0x12}, - { CDC_2_5_WSA_COMPANDER1_CTL12, 0x1E}, - { CDC_2_5_WSA_COMPANDER1_CTL13, 0x24}, - { CDC_2_5_WSA_COMPANDER1_CTL14, 0x24}, - { CDC_2_5_WSA_COMPANDER1_CTL15, 0x24}, - { CDC_2_5_WSA_COMPANDER1_CTL16, 0x00}, + { CDC_2_5_WSA_COMPANDER1_CTL11, 0x0C}, + { CDC_2_5_WSA_COMPANDER1_CTL12, 0x15}, + { CDC_2_5_WSA_COMPANDER1_CTL13, 0x15}, + { CDC_2_5_WSA_COMPANDER1_CTL14, 0x15}, + { CDC_2_5_WSA_COMPANDER1_CTL15, 0x15}, + { CDC_2_5_WSA_COMPANDER1_CTL16, 0x0F}, { CDC_2_5_WSA_COMPANDER1_CTL17, 0x24}, { CDC_2_5_WSA_COMPANDER1_CTL18, 0x2A}, { CDC_2_5_WSA_COMPANDER1_CTL19, 0x16}, @@ -874,6 +891,9 @@ static bool wsa_is_rw_register_v2_5(struct device *dev, unsigned int reg) case CDC_2_5_WSA_SOFTCLIP0_SOFTCLIP_CTRL: case CDC_2_5_WSA_SOFTCLIP1_CRC: case CDC_2_5_WSA_SOFTCLIP1_SOFTCLIP_CTRL: + case CDC_2_5_WSA_CB_DECODE_CTL0: + case CDC_2_5_WSA_CB_DECODE_CTL1: + case CDC_2_5_WSA_CB_DECODE_CMD: return true; } @@ -906,6 +926,17 @@ static bool wsa_is_rw_register(struct device *dev, unsigned int reg) case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0: case CDC_WSA_RX_INP_MUX_RX_EC_CFG0: case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0: + case CDC_WSA_VBAT_BCL_VBAT_PATH_CTL: + case CDC_WSA_VBAT_BCL_VBAT_CFG: + case CDC_WSA_VBAT_BCL_GAIN_UPD1: + case CDC_WSA_VBAT_BCL_GAIN_UPD2: + case CDC_WSA_VBAT_BCL_GAIN_UPD3: + case CDC_WSA_VBAT_BCL_GAIN_UPD4: + case CDC_WSA_VBAT_BCL_GAIN_UPD5: + case CDC_WSA_VBAT_BCL_GAIN_UPD6: + case CDC_WSA_VBAT_BCL_GAIN_UPD7: + case CDC_WSA_VBAT_BCL_GAIN_UPD8: + case CDC_WSA_VBAT_BCL_GAIN_UPD9: case CDC_WSA_TX0_SPKR_PROT_PATH_CTL: case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0: case CDC_WSA_TX1_SPKR_PROT_PATH_CTL: @@ -1069,6 +1100,9 @@ static bool wsa_is_volatile_register_v2_5(struct device *dev, unsigned int reg) { switch (reg) { case CDC_2_5_WSA_COMPANDER1_CTL6: + case CDC_2_5_WSA_CB_DECODE_CTL0: + case CDC_2_5_WSA_CB_DECODE_CTL1: + case CDC_2_5_WSA_CB_DECODE_CMD: return true; } @@ -1084,6 +1118,17 @@ static bool wsa_is_volatile_register(struct device *dev, unsigned int reg) case CDC_WSA_INTR_CTRL_PIN1_STATUS0: case CDC_WSA_INTR_CTRL_PIN2_STATUS0: case CDC_WSA_COMPANDER0_CTL6: + case CDC_WSA_VBAT_BCL_VBAT_PATH_CTL: + case CDC_WSA_VBAT_BCL_VBAT_CFG: + case CDC_WSA_VBAT_BCL_GAIN_UPD1: + case CDC_WSA_VBAT_BCL_GAIN_UPD2: + case CDC_WSA_VBAT_BCL_GAIN_UPD3: + case CDC_WSA_VBAT_BCL_GAIN_UPD4: + case CDC_WSA_VBAT_BCL_GAIN_UPD5: + case CDC_WSA_VBAT_BCL_GAIN_UPD6: + case CDC_WSA_VBAT_BCL_GAIN_UPD7: + case CDC_WSA_VBAT_BCL_GAIN_UPD8: + case CDC_WSA_VBAT_BCL_GAIN_UPD9: case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: @@ -1277,6 +1322,18 @@ static int wsa_macro_hw_params(struct snd_pcm_substream *substream, struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); int ret; + if (dai->id == WSA_MACRO_AIF_VI) { + wsa->pcm_rate_vi = params_rate(params); + return 0; + } + + /* CPS is already framed by the WSA8845 SoundWire DP6 source. This + * logical macro endpoint only carries it to WSA_CODEC_DMA_TX_1 and must + * not reprogram the VI sensing rate/state machine. + */ + if (dai->id == WSA_MACRO_AIF_CPS) + return 0; + switch (substream->stream) { case SNDRV_PCM_STREAM_PLAYBACK: ret = wsa_macro_set_interpolator_rate(dai, params_rate(params)); @@ -1288,9 +1345,6 @@ static int wsa_macro_hw_params(struct snd_pcm_substream *substream, } break; case SNDRV_PCM_STREAM_CAPTURE: - if (dai->id == WSA_MACRO_AIF_VI) - wsa->pcm_rate_vi = params_rate(params); - break; default: break; @@ -1324,6 +1378,10 @@ static int wsa_macro_get_channel_map(const struct snd_soc_dai *dai, *rx_slot = mask; *rx_num = cnt; break; + case WSA_MACRO_AIF_CPS: + *tx_num = 2; + *tx_slot = GENMASK(1, 0); + break; case WSA_MACRO_AIF_ECHO: val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); if (val & WSA_MACRO_EC_MIX_TX1_MASK) { @@ -1381,6 +1439,19 @@ static struct snd_soc_dai_driver wsa_macro_dai[] = { { .name = "wsa_macro_vifeedback", .id = WSA_MACRO_AIF_VI, + .playback = { + /* + * Companion playback semantics make VI feedback start + * atomically with the protected render graph. + */ + .stream_name = "WSA_AIF_VI Protection", + .rates = SNDRV_PCM_RATE_8000, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rate_max = 8000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 4, + }, .capture = { .stream_name = "WSA_AIF_VI Capture", .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000, @@ -1406,6 +1477,20 @@ static struct snd_soc_dai_driver wsa_macro_dai[] = { }, .ops = &wsa_macro_dai_ops, }, + { + .name = "wsa_macro_cps", + .id = WSA_MACRO_AIF_CPS, + .playback = { + .stream_name = "WSA_AIF_CPS Protection", + .rates = SNDRV_PCM_RATE_24000, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rate_max = 24000, + .rate_min = 24000, + .channels_min = 2, + .channels_max = 2, + }, + .ops = &wsa_macro_dai_ops, + }, }; static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable) @@ -1477,6 +1562,10 @@ static void wsa_macro_enable_disable_vi_sense(struct snd_soc_component *componen snd_soc_component_update_bits(component, tx_reg1, CDC_WSA_TX_SPKR_PROT_RESET_MASK, CDC_WSA_TX_SPKR_PROT_NO_RESET); + + /* Windows qcaucd materializes TOP_CFG1 after each enabled VI pair. */ + if (of_machine_is_compatible("microsoft,denali")) + snd_soc_component_write(component, CDC_WSA_TOP_TOP_CFG1, 0x03); } else { snd_soc_component_update_bits(component, tx_reg0, CDC_WSA_TX_SPKR_PROT_RESET_MASK, @@ -1493,6 +1582,65 @@ static void wsa_macro_enable_disable_vi_sense(struct snd_soc_component *componen } } +/* + * SP11 Windows orders the protection-clock resource after both WSA8845 + * GLOBAL_PA_EN writes. Keep the register ownership in the WSA macro and let + * the amplifiers report only their PA lifecycle boundary. + */ +static DEFINE_MUTEX(sp11_protclk_lock); +static struct snd_soc_component *sp11_protclk_component; +static unsigned int sp11_pa_users; +static bool sp11_protclk_enabled; + +void wsa_macro_sp11_pa_event(bool enable) +{ + struct snd_soc_component *component; + + mutex_lock(&sp11_protclk_lock); + component = sp11_protclk_component; + if (!component) + goto out; + + if (enable) { + if (sp11_pa_users < 2) + sp11_pa_users++; + + if (sp11_pa_users == 2 && !sp11_protclk_enabled) { + wsa_macro_enable_disable_vi_sense(component, true, + CDC_WSA_TX0_SPKR_PROT_PATH_CTL, + CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0); + wsa_macro_enable_disable_vi_sense(component, true, + CDC_WSA_TX2_SPKR_PROT_PATH_CTL, + CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0); + sp11_protclk_enabled = true; + dev_info(component->dev, + "SP11POSTPA: WSA protection clocks enabled after both PAs\n"); + } + } else { + /* + * Conservative teardown: remove the feedback clocks while both + * PAs are still up, before the first amp executes its stop table. + */ + if (sp11_pa_users == 2 && sp11_protclk_enabled) { + wsa_macro_enable_disable_vi_sense(component, false, + CDC_WSA_TX0_SPKR_PROT_PATH_CTL, + CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0); + wsa_macro_enable_disable_vi_sense(component, false, + CDC_WSA_TX2_SPKR_PROT_PATH_CTL, + CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0); + sp11_protclk_enabled = false; + dev_info(component->dev, + "SP11POSTPA: WSA protection clocks disabled before PA teardown\n"); + } + + if (sp11_pa_users) + sp11_pa_users--; + } +out: + mutex_unlock(&sp11_protclk_lock); +} +EXPORT_SYMBOL_GPL(wsa_macro_sp11_pa_event); + static void wsa_macro_enable_disable_vi_feedback(struct snd_soc_component *component, bool enable, u32 rate) { @@ -1565,40 +1713,10 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w, static void wsa_macro_hd2_control(struct snd_soc_component *component, u16 reg, int event) { - u16 hd2_scale_reg; - u16 hd2_enable_reg; - - if (reg == CDC_WSA_RX0_RX_PATH_CTL) { - hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3; - hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0; - } - if (reg == CDC_WSA_RX1_RX_PATH_CTL) { - hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3; - hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0; - } - - if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { - snd_soc_component_update_bits(component, hd2_scale_reg, - CDC_WSA_RX_PATH_HD2_ALPHA_MASK, - 0x10); - snd_soc_component_update_bits(component, hd2_scale_reg, - CDC_WSA_RX_PATH_HD2_SCALE_MASK, - 0x1); - snd_soc_component_update_bits(component, hd2_enable_reg, - CDC_WSA_RX_PATH_HD2_EN_MASK, - CDC_WSA_RX_PATH_HD2_ENABLE); - } - - if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { - snd_soc_component_update_bits(component, hd2_enable_reg, - CDC_WSA_RX_PATH_HD2_EN_MASK, 0); - snd_soc_component_update_bits(component, hd2_scale_reg, - CDC_WSA_RX_PATH_HD2_SCALE_MASK, - 0); - snd_soc_component_update_bits(component, hd2_scale_reg, - CDC_WSA_RX_PATH_HD2_ALPHA_MASK, - 0); - } + /* SP11 Windows native WSA lifecycle never enables generic HD2. */ + (void)component; + (void)reg; + (void)event; } static int wsa_macro_config_compander(struct snd_soc_component *component, @@ -1687,6 +1805,85 @@ static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component, } } +/* + * SP11 Windows uses the legacy Qualcomm WSA VBAT/BCL attenuation stage on + * both internal-speaker paths. Keep this event independent of compander and + * WSA8845 CSR state so the candidate isolates producer topology only. + */ +static int wsa_macro_enable_vbat(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); + u16 vbat_path_cfg; + int softclip_path; + static const u16 bcl_regs[] = { + CDC_WSA_VBAT_BCL_GAIN_UPD1, CDC_WSA_VBAT_BCL_GAIN_UPD2, + CDC_WSA_VBAT_BCL_GAIN_UPD3, CDC_WSA_VBAT_BCL_GAIN_UPD4, + CDC_WSA_VBAT_BCL_GAIN_UPD5, CDC_WSA_VBAT_BCL_GAIN_UPD6, + CDC_WSA_VBAT_BCL_GAIN_UPD7, CDC_WSA_VBAT_BCL_GAIN_UPD8, + CDC_WSA_VBAT_BCL_GAIN_UPD9, + }; + static const u8 bcl_gain[] = { 0xff, 0x03, 0x00, 0xff, 0x03, 0x00, + 0xff, 0x03, 0x00 }; + int i; + + if (!snd_soc_dapm_widget_name_cmp(w, "WSA_RX INT0 VBAT")) { + vbat_path_cfg = CDC_WSA_RX0_RX_PATH_CFG1; + softclip_path = WSA_MACRO_SOFTCLIP0; + } else if (!snd_soc_dapm_widget_name_cmp(w, "WSA_RX INT1 VBAT")) { + vbat_path_cfg = CDC_WSA_RX1_RX_PATH_CFG1; + softclip_path = WSA_MACRO_SOFTCLIP1; + } else { + return -EINVAL; + } + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + snd_soc_component_update_bits(component, CDC_WSA_VBAT_BCL_VBAT_PATH_CTL, + 0x10, 0x10); + snd_soc_component_update_bits(component, CDC_WSA_VBAT_BCL_VBAT_CFG, + 0x01, 0x01); + snd_soc_component_update_bits(component, vbat_path_cfg, 0x80, 0x80); + snd_soc_component_update_bits(component, CDC_WSA_VBAT_BCL_VBAT_CFG, + 0x02, 0x00); + wsa_macro_enable_softclip_clk(component, wsa, softclip_path, true); + snd_soc_component_update_bits(component, vbat_path_cfg, 0x02, 0x02); + for (i = 0; i < ARRAY_SIZE(bcl_regs); i++) + snd_soc_component_write(component, bcl_regs[i], bcl_gain[i]); + + if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5) { + snd_soc_component_write(component, CDC_2_5_WSA_CB_DECODE_CTL0, 0x01); + snd_soc_component_write(component, CDC_2_5_WSA_CB_DECODE_CTL1, 0x01); + snd_soc_component_write(component, CDC_2_5_WSA_CB_DECODE_CMD, 0x01); + } + dev_info(component->dev, "SP11VBAT: %s enabled\n", w->name); + break; + + case SND_SOC_DAPM_POST_PMD: + if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5) { + snd_soc_component_write(component, CDC_2_5_WSA_CB_DECODE_CMD, 0x00); + snd_soc_component_write(component, CDC_2_5_WSA_CB_DECODE_CTL1, 0x00); + snd_soc_component_write(component, CDC_2_5_WSA_CB_DECODE_CTL0, 0x00); + } + snd_soc_component_update_bits(component, vbat_path_cfg, 0x80, 0x00); + snd_soc_component_update_bits(component, CDC_WSA_VBAT_BCL_VBAT_CFG, + 0x02, 0x02); + snd_soc_component_update_bits(component, vbat_path_cfg, 0x02, 0x00); + for (i = 0; i < ARRAY_SIZE(bcl_regs); i++) + snd_soc_component_write(component, bcl_regs[i], 0x00); + wsa_macro_enable_softclip_clk(component, wsa, softclip_path, false); + snd_soc_component_update_bits(component, CDC_WSA_VBAT_BCL_VBAT_CFG, + 0x01, 0x00); + snd_soc_component_update_bits(component, CDC_WSA_VBAT_BCL_VBAT_PATH_CTL, + 0x10, 0x00); + dev_info(component->dev, "SP11VBAT: %s disabled\n", w->name); + break; + } + + return 0; +} + static int wsa_macro_config_softclip(struct snd_soc_component *component, int path, int event) { @@ -1702,7 +1899,8 @@ static int wsa_macro_config_softclip(struct snd_soc_component *component, if (!wsa->is_softclip_on[softclip_path]) return 0; - softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL + + softclip_ctrl_reg = wsa->reg_layout->softclip0_reg_base + + WSA_MACRO_SOFTCLIP_CTRL_OFFSET + (softclip_path * wsa->reg_layout->softclip1_reg_offset); if (SND_SOC_DAPM_EVENT_ON(event)) { @@ -1867,7 +2065,7 @@ static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, CDC_WSA_RX0_RX_PATH_SEC1, CDC_WSA_RX_PGA_HALF_DB_MASK, - CDC_WSA_RX_PGA_HALF_DB_ENABLE); + CDC_WSA_RX_PGA_HALF_DB_DISABLE); snd_soc_component_update_bits(component, CDC_WSA_RX0_RX_PATH_MIX_SEC0, CDC_WSA_RX_PGA_HALF_DB_MASK, @@ -1875,7 +2073,7 @@ static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, CDC_WSA_RX1_RX_PATH_SEC1, CDC_WSA_RX_PGA_HALF_DB_MASK, - CDC_WSA_RX_PGA_HALF_DB_ENABLE); + CDC_WSA_RX_PGA_HALF_DB_DISABLE); snd_soc_component_update_bits(component, CDC_WSA_RX1_RX_PATH_MIX_SEC0, CDC_WSA_RX_PGA_HALF_DB_MASK, @@ -2064,7 +2262,7 @@ static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol, struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); - ucontrol->value.enumerated.item[0] = wsa->ear_spkr_gain; + ucontrol->value.integer.value[0] = wsa->ear_spkr_gain; return 0; } @@ -2075,7 +2273,7 @@ static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol, struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); - wsa->ear_spkr_gain = ucontrol->value.enumerated.item[0]; + wsa->ear_spkr_gain = ucontrol->value.integer.value[0]; return 0; } @@ -2088,7 +2286,7 @@ static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol, snd_soc_dapm_to_component(widget->dapm); struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); - ucontrol->value.enumerated.item[0] = + ucontrol->value.integer.value[0] = wsa->rx_port_value[widget->shift]; return 0; } @@ -2101,7 +2299,7 @@ static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol, snd_soc_dapm_to_component(widget->dapm); struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; struct snd_soc_dapm_update *update = NULL; - u32 rx_port_value = ucontrol->value.enumerated.item[0]; + u32 rx_port_value = ucontrol->value.integer.value[0]; u32 bit_input; u32 aif_rst; unsigned int dai_id; @@ -2311,8 +2509,16 @@ static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = { SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0, wsa_macro_enable_vi_feedback, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_AIF_IN_E("WSA AIF_VI Protection", + "WSA_AIF_VI Protection", 0, + SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0, + wsa_macro_enable_vi_feedback, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("WSA AIF_CPS Protection", + "WSA_AIF_CPS Protection", 0, + SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)), @@ -2364,6 +2570,13 @@ static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = { SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("WSA_RX INT0 VBAT", SND_SOC_NOPM, 0, 0, + NULL, 0, wsa_macro_enable_vbat, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("WSA_RX INT1 VBAT", SND_SOC_NOPM, 0, 0, + NULL, 0, wsa_macro_enable_vbat, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0, wsa_macro_spk_boost_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | @@ -2375,6 +2588,7 @@ static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = { SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_INPUT("VIINPUT_WSA"), + SND_SOC_DAPM_INPUT("CPSINPUT_WSA"), SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"), SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"), @@ -2416,6 +2630,12 @@ static const struct snd_soc_dapm_route wsa_audio_map[] = { {"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"}, {"WSA AIF_VI", NULL, "WSA_MCLK"}, + /* CPS feedback is a distinct transport from VI; only the shared macro + * clock is required here. DP6 framing is programmed by SoundWire. + */ + {"WSA AIF_CPS Protection", NULL, "CPSINPUT_WSA"}, + {"WSA AIF_CPS Protection", NULL, "WSA_MCLK"}, + {"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, {"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, {"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, @@ -2481,7 +2701,8 @@ static const struct snd_soc_dapm_route wsa_audio_map[] = { {"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"}, {"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"}, {"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"}, - {"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"}, + {"WSA_RX INT0 VBAT", NULL, "WSA_RX INT0 INTERP"}, + {"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 VBAT"}, {"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"}, {"WSA_SPK1 OUT", NULL, "WSA_MCLK"}, @@ -2521,7 +2742,8 @@ static const struct snd_soc_dapm_route wsa_audio_map[] = { {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"}, {"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"}, - {"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"}, + {"WSA_RX INT1 VBAT", NULL, "WSA_RX INT1 INTERP"}, + {"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 VBAT"}, {"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"}, {"WSA_SPK2 OUT", NULL, "WSA_MCLK"}, }; @@ -2563,6 +2785,12 @@ static int wsa_macro_component_probe(struct snd_soc_component *comp) snd_soc_component_init_regmap(comp, wsa->regmap); + mutex_lock(&sp11_protclk_lock); + sp11_protclk_component = comp; + sp11_pa_users = 0; + sp11_protclk_enabled = false; + mutex_unlock(&sp11_protclk_lock); + wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB; /* set SPKR rate to FS_2P4_3P072 */ @@ -2663,9 +2891,21 @@ static int wsa_macro_register_mclk_output(struct wsa_macro *wsa) return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); } +static void wsa_macro_component_remove(struct snd_soc_component *comp) +{ + mutex_lock(&sp11_protclk_lock); + if (sp11_protclk_component == comp) { + sp11_protclk_component = NULL; + sp11_pa_users = 0; + sp11_protclk_enabled = false; + } + mutex_unlock(&sp11_protclk_lock); +} + static const struct snd_soc_component_driver wsa_macro_component_drv = { .name = "WSA MACRO", .probe = wsa_macro_component_probe, + .remove = wsa_macro_component_remove, .controls = wsa_macro_snd_controls, .num_controls = ARRAY_SIZE(wsa_macro_snd_controls), .dapm_widgets = wsa_macro_dapm_widgets, diff --git a/sound/soc/codecs/lpass-wsa-macro.h b/sound/soc/codecs/lpass-wsa-macro.h index d3d62b3f6500c9..8a4d6787c4e0f4 100644 --- a/sound/soc/codecs/lpass-wsa-macro.h +++ b/sound/soc/codecs/lpass-wsa-macro.h @@ -13,5 +13,6 @@ enum { }; int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode); +void wsa_macro_sp11_pa_event(bool enable); #endif /* __LPASS_WSA_MACRO_H__ */ diff --git a/sound/soc/codecs/wsa884x.c b/sound/soc/codecs/wsa884x.c index 6c6b497657d0c8..28c3d829003e16 100644 --- a/sound/soc/codecs/wsa884x.c +++ b/sound/soc/codecs/wsa884x.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -13,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -21,12 +23,15 @@ #include #include #include +#include #include #include #include #include #include +#include "lpass-wsa-macro.h" + #define WSA884X_BASE 0x3000 #define WSA884X_ANA_BG_TSADC_BASE (WSA884X_BASE + 0x0001) #define WSA884X_BG_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x00) @@ -155,6 +160,7 @@ #define WSA884X_BBM_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x28) #define WSA884X_TOP_MISC1 (WSA884X_ANA_SPK_TOP_BASE + 0x29) #define WSA884X_DAC_VCM_CTRL_REG7 (WSA884X_ANA_SPK_TOP_BASE + 0x2a) +#define WSA884X_DAC_VCM_CTRL_REG7_FINAL_OVERRIDE_MASK 0x02 #define WSA884X_TOP_BIAS_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x2b) #define WSA884X_DRV_LF_MISC_CTL2 (WSA884X_ANA_SPK_TOP_BASE + 0x2c) #define WSA884X_SPK_TOP_SPARE_TUNE_2 (WSA884X_ANA_SPK_TOP_BASE + 0x2d) @@ -437,7 +443,9 @@ #define WSA884X_CLSH_CTL_0_INPUT_EN_SHIFT 1 #define WSA884X_CLSH_CTL_0_CLSH_EN_SHIFT 0 #define WSA884X_CLSH_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xd1) +#define WSA884X_CLSH_CTL_1_SLR_MAX_MASK 0xf0 #define WSA884X_CLSH_V_HD_PA (WSA884X_DIG_CTRL0_BASE + 0xd2) +#define WSA884X_CLSH_V_HD_PA_MASK 0x1f #define WSA884X_CLSH_V_PA_MIN (WSA884X_DIG_CTRL0_BASE + 0xd3) #define WSA884X_CLSH_OVRD_VAL (WSA884X_DIG_CTRL0_BASE + 0xd4) #define WSA884X_CLSH_HARD_MAX (WSA884X_DIG_CTRL0_BASE + 0xd5) @@ -725,19 +733,33 @@ #define WSA884X_LOW_TEMP_THRESHOLD 5 #define WSA884X_HIGH_TEMP_THRESHOLD 45 +#define WSA884X_PA_FSM_RESET_MASK BIT(4) +#define WSA884X_PA_ERROR_MASK GENMASK(4, 0) +#define WSA884X_PA_RECOVERY_RETRIES 3 +#define WSA884X_PA_RECOVERY_FAILURES 3 +#define WSA884X_PA_HEALTH_INTERVAL_MS 100 +#define WSA884X_SP11_OBSERVE_MAX_SAMPLES 40 + +static unsigned int sp11_observe_samples; +module_param_named(sp11_observe_samples, sp11_observe_samples, uint, 0644); +MODULE_PARM_DESC(sp11_observe_samples, + "read-only 100 ms WSA status snapshots on each speaker start (0=off, max=40)"); + struct wsa884x_priv { struct regmap *regmap; struct device *dev; struct regulator_bulk_data supplies[WSA884X_SUPPLIES_NUM]; struct sdw_slave *slave; - struct sdw_stream_config sconfig; - struct sdw_stream_runtime *sruntime; - struct sdw_port_config port_config[WSA884X_MAX_SWR_PORTS]; + struct sdw_stream_runtime *sruntime[3]; + u8 cps_offset1; + u8 visense_channel_mask; + bool cps_enabled; + bool sp11_windows_lifecycle; + bool sp11_protclk_reported; struct gpio_desc *sd_n; struct reset_control *sd_reset; bool port_prepared[WSA884X_MAX_SWR_PORTS]; bool port_enable[WSA884X_MAX_SWR_PORTS]; - int active_ports; int dev_mode; bool hw_init; /* @@ -747,6 +769,18 @@ struct wsa884x_priv { struct mutex sp_lock; unsigned int temperature; bool pa_on; + struct delayed_work pa_health_work; + unsigned int pa_recovery_failures; + unsigned int observe_remaining; + unsigned int observe_sequence; + unsigned int supply_config; +}; + +enum wsa884x_supply_config { + WSA884X_SUPPLY_EXT_ABOVE_3S, + WSA884X_SUPPLY_1S, + WSA884X_SUPPLY_2S, + WSA884X_SUPPLY_3S, }; enum { @@ -821,7 +855,7 @@ enum wsa884x_mode { static const struct soc_enum wsa884x_dev_mode_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa884x_dev_mode_text), wsa884x_dev_mode_text); -static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = { +static struct sdw_dpn_prop wsa884x_sink_dpn_prop[] = { [WSA884X_PORT_DAC] = { .num = WSA884X_PORT_DAC + 1, .type = SDW_DPN_SIMPLE, @@ -829,6 +863,7 @@ static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = { .max_ch = 1, .simple_ch_prep_sm = true, .read_only_wordlength = true, + .simple_transport_registers = SDW_DPN_SIMPLE_TRANSPORT_BLOCKCTRL3, }, [WSA884X_PORT_COMP] = { .num = WSA884X_PORT_COMP + 1, @@ -837,6 +872,7 @@ static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = { .max_ch = 1, .simple_ch_prep_sm = true, .read_only_wordlength = true, + .simple_transport_registers = SDW_DPN_SIMPLE_TRANSPORT_OFFSETCTRL2, }, [WSA884X_PORT_BOOST] = { .num = WSA884X_PORT_BOOST + 1, @@ -845,6 +881,7 @@ static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = { .max_ch = 1, .simple_ch_prep_sm = true, .read_only_wordlength = true, + .simple_transport_registers = SDW_DPN_SIMPLE_TRANSPORT_OFFSETCTRL2, }, [WSA884X_PORT_PBR] = { .num = WSA884X_PORT_PBR + 1, @@ -854,7 +891,10 @@ static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = { .simple_ch_prep_sm = true, .read_only_wordlength = true, }, - [WSA884X_PORT_VISENSE] = { +}; + +static struct sdw_dpn_prop wsa884x_source_dpn_prop[] = { + { .num = WSA884X_PORT_VISENSE + 1, .type = SDW_DPN_SIMPLE, .min_ch = 1, @@ -862,14 +902,21 @@ static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = { .simple_ch_prep_sm = true, .read_only_wordlength = true, }, - [WSA884X_PORT_CPS] = { + { .num = WSA884X_PORT_CPS + 1, .type = SDW_DPN_SIMPLE, .min_ch = 1, - .max_ch = 1, + .max_ch = 2, .simple_ch_prep_sm = true, - .read_only_wordlength = true, - } + /* CPS DP6 BlockCtrl1 is writable and Windows programs the + * master-derived 0x18 word-length value on both slaves. + */ + .read_only_wordlength = false, + .simple_transport_registers = + SDW_DPN_SIMPLE_TRANSPORT_BLOCKCTRL3 | + SDW_DPN_SIMPLE_TRANSPORT_SAMPLECTRL2 | + SDW_DPN_SIMPLE_TRANSPORT_HCTRL, + }, }; static const struct sdw_port_config wsa884x_pconfig[WSA884X_MAX_SWR_PORTS] = { @@ -1462,6 +1509,20 @@ static void wsa884x_set_gain_parameters(struct wsa884x_priv *wsa884x) struct regmap *regmap = wsa884x->regmap; unsigned int min_gain, igain, vgain, comp_offset; + /* + * Surface Pro 11 ACDB selects a 4 Ohm speaker load. Qualcomm's + * downstream WSA884x tables pair that load with G_18_DB system gain; + * its 2S configuration keeps compander offset/minimum/aux gain at 0 dB. + */ + if (wsa884x->supply_config == WSA884X_SUPPLY_2S && + wsa884x->dev_mode == WSA884X_SPEAKER) { + comp_offset = COMP_OFFSET0; + min_gain = G_0_DB; + igain = ISENSE_6_DB; + vgain = VSENSE_M21_DB; + goto apply; + } + /* * Downstream sets gain parameters customized per boards per use-case. * Choose here some sane values matching knowon users, like QRD8550 @@ -1484,6 +1545,7 @@ static void wsa884x_set_gain_parameters(struct wsa884x_priv *wsa884x) vgain = VSENSE_M24_DB; } +apply: regmap_update_bits(regmap, WSA884X_ISENSE2, WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK, FIELD_PREP(WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK, igain)); @@ -1509,18 +1571,274 @@ static void wsa884x_set_gain_parameters(struct wsa884x_priv *wsa884x) } } +/* + * Qualcomm's full WSA884x driver has board-specific supply initialization + * which is not represented by the upstream driver's QRD8550-oriented 1S + * defaults. VPHX_SYS_EN_STATUS is a hardware strap/status value, so use it + * to select the electrically correct initialization without depending on an + * incomplete board description. + */ +static void wsa884x_apply_supply_config(struct wsa884x_priv *wsa884x) +{ + struct regmap *regmap = wsa884x->regmap; + static const struct reg_sequence sp11_2s_4ohm_pbr[] = { + /* + * Qualcomm downstream G_18_DB / CONFIG_2S / WSA_4_OHMS: + * 808, 839, 894, 925, 973, 996, 1051, 1114, 1184, 1255, + * 1318, 1467, 1616, 1788 and 2000 (millivolts * 100). + */ + { WSA884X_CLSH_VTH1, WSA884X_VTH_TO_REG(808) }, + { WSA884X_CLSH_VTH2, WSA884X_VTH_TO_REG(839) }, + { WSA884X_CLSH_VTH3, WSA884X_VTH_TO_REG(894) }, + { WSA884X_CLSH_VTH4, WSA884X_VTH_TO_REG(925) }, + { WSA884X_CLSH_VTH5, WSA884X_VTH_TO_REG(973) }, + { WSA884X_CLSH_VTH6, WSA884X_VTH_TO_REG(996) }, + { WSA884X_CLSH_VTH7, WSA884X_VTH_TO_REG(1051) }, + { WSA884X_CLSH_VTH8, WSA884X_VTH_TO_REG(1114) }, + { WSA884X_CLSH_VTH9, WSA884X_VTH_TO_REG(1184) }, + { WSA884X_CLSH_VTH10, WSA884X_VTH_TO_REG(1255) }, + { WSA884X_CLSH_VTH11, WSA884X_VTH_TO_REG(1318) }, + { WSA884X_CLSH_VTH12, WSA884X_VTH_TO_REG(1467) }, + { WSA884X_CLSH_VTH13, WSA884X_VTH_TO_REG(1616) }, + { WSA884X_CLSH_VTH14, WSA884X_VTH_TO_REG(1788) }, + { WSA884X_CLSH_VTH15, WSA884X_VTH_TO_REG(2000) }, + }; + + if (wsa884x->supply_config != WSA884X_SUPPLY_2S) + return; + + /* + * Exact Surface ACDB 4 Ohm load policy plus the CONFIG_2S values + * observed on both physical amplifiers in the SP11 Windows qcaucd + * command-FIFO trace. Keep this after the generic init table so the + * board-specific values win. + */ + regmap_write(regmap, WSA884X_BOP2_PROG, 0x44); + regmap_write(regmap, WSA884X_UVLO_PROG, 0x33); + regmap_write(regmap, WSA884X_UVLO_PROG1, 0x60); + regmap_write(regmap, WSA884X_VBAT_SNS, 0x20); + regmap_write(regmap, WSA884X_OCP_CTL, 0xf6); + regmap_write(regmap, WSA884X_PDRV_HS_CTL, 0x5a); + regmap_write(regmap, WSA884X_PWRSTG_DBG, 0x0c); + regmap_write(regmap, WSA884X_PWRSTAGE_CTRL2, 0xf1); + regmap_write(regmap, WSA884X_SWR_RESET_EN, 0x07); + regmap_multi_reg_write(regmap, sp11_2s_4ohm_pbr, + ARRAY_SIZE(sp11_2s_4ohm_pbr)); + regmap_write(regmap, WSA884X_CDC_SPK_DSM_C_2, 0xf2); + regmap_write(regmap, WSA884X_DRE_IDLE_DET_CTL, 0x0f); + regmap_write(regmap, WSA884X_CLSH_CTL_0, 0x00); + regmap_write(regmap, WSA884X_CLSH_SOFT_MAX, 0xff); + regmap_write(regmap, WSA884X_OTP_REG_38, 0x08); + regmap_update_bits(regmap, WSA884X_CLSH_CTL_1, + WSA884X_CLSH_CTL_1_SLR_MAX_MASK, + FIELD_PREP(WSA884X_CLSH_CTL_1_SLR_MAX_MASK, 0x2)); + regmap_update_bits(regmap, WSA884X_CLSH_V_HD_PA, + WSA884X_CLSH_V_HD_PA_MASK, + FIELD_PREP(WSA884X_CLSH_V_HD_PA_MASK, 0x13)); + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG2, 0x06); + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG3, 0x14); + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG4, 0x19); + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG5, 0x1b); + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG6, 0x1c); + regmap_update_bits(regmap, WSA884X_DAC_VCM_CTRL_REG7, + WSA884X_DAC_VCM_CTRL_REG7_FINAL_OVERRIDE_MASK, + WSA884X_DAC_VCM_CTRL_REG7_FINAL_OVERRIDE_MASK); + + regmap_write(regmap, WSA884X_PA_FSM_TIMER0, 0xc0); + regmap_write(regmap, WSA884X_UVLO_DEGLITCH_CTL, 0x1d); + + regmap_update_bits(regmap, WSA884X_TOP_CTRL1, + WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK, 0); +} + + +/* + * Surface Pro 11 / Denali Windows programs this analog board/supply tail as + * one ordered transaction before normal speaker playback. Several final + * values are already reached elsewhere by generic Linux, but v12R proved + * that changing CURRENT_LIMIT history in isolation is cycle-unstable. Keep + * the Windows-proven transition coherent and SP11 2S-only. + */ +static void wsa884x_apply_sp11_windows_analog_tail(struct wsa884x_priv *wsa884x) +{ + struct regmap *regmap = wsa884x->regmap; + + if (wsa884x->supply_config != WSA884X_SUPPLY_2S) + return; + + regmap_write(regmap, WSA884X_REF_CTRL, 0xd1); /* 0x300b */ + regmap_write(regmap, WSA884X_UVLO_PROG, 0x33); /* 0x3005 */ + regmap_write(regmap, WSA884X_UVLO_PROG1, 0x60); /* 0x3006 */ + regmap_write(regmap, WSA884X_BOP1_PROG, 0x22); /* 0x3003 */ + regmap_write(regmap, WSA884X_BOP2_PROG, 0x44); /* 0x3004 */ + regmap_write(regmap, WSA884X_ZX_CTRL1, 0xf8); /* 0x30a0 */ + regmap_write(regmap, WSA884X_STB_CTRL1, 0x6a); /* 0x3090 */ + regmap_write(regmap, WSA884X_ILIM_CTRL1, 0xe3); /* 0x30aa */ + regmap_write(regmap, WSA884X_CURRENT_LIMIT, 0xd4); /* 0x3091 */ + regmap_write(regmap, WSA884X_TOP_CTRL1, 0xd2); /* 0x3040 */ + regmap_write(regmap, WSA884X_OCP_CTL, 0xf6); /* 0x304c */ + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG2, 0x06); /* 0x3045 */ + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG3, 0x14); /* 0x3046 */ + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG4, 0x19); /* 0x3047 */ + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG5, 0x1b); /* 0x3048 */ + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG6, 0x1c); /* 0x3049 */ + regmap_write(regmap, WSA884X_DAC_VCM_CTRL_REG7, 0x02); /* 0x306a */ + regmap_write(regmap, WSA884X_CKWD_CTL_1, 0x13); /* 0x30ba */ + regmap_write(regmap, WSA884X_PWRSTAGE_CTRL2, 0xf1); /* 0x30a5 */ + regmap_write(regmap, WSA884X_CURRENT_LIMIT, 0x44); /* 0x3091 */ +} + +/* + * Surface Pro 11 / Denali shipping Windows codec lifecycle, recovered from + * the complete qcaucd WSA8845 write oracle. The cold transaction is emitted + * once after SoundWire attachment; ordinary playback then uses only START and + * STOP below. Keep every write full-width and ordered: the transition history + * is part of the hardware contract. + */ +static const struct reg_sequence sp11_windows_cold_init[] = { + { WSA884X_PWRSTG_DBG, 0x0c }, + { WSA884X_PDRV_HS_CTL, 0x5a }, + { WSA884X_SWR_RESET_EN, 0x07 }, + { WSA884X_INTR_MASK0, 0xff }, + { WSA884X_INTR_MASK1, 0x03 }, + { WSA884X_PA_FSM_BYP_CTL, 0x00 }, + { WSA884X_VBAT_SNS, 0x20 }, + { WSA884X_CKWD_CTL_1, 0x1b }, + { WSA884X_CDC_SPK_DSM_A2_0, 0x0a }, + { WSA884X_CDC_SPK_DSM_A2_1, 0x08 }, + { WSA884X_CDC_SPK_DSM_A3_0, 0xf3 }, + { WSA884X_CDC_SPK_DSM_A3_1, 0x07 }, + { WSA884X_CDC_SPK_DSM_A4_0, 0x79 }, + { WSA884X_CDC_SPK_DSM_A4_1, 0x02 }, + { WSA884X_CDC_SPK_DSM_A5_0, 0x0b }, + { WSA884X_CDC_SPK_DSM_A5_1, 0x02 }, + { WSA884X_CDC_SPK_DSM_A6_0, 0x8a }, + { WSA884X_CDC_SPK_DSM_A7_0, 0x9b }, + { WSA884X_CDC_SPK_DSM_C_0, 0x68 }, + { WSA884X_CDC_SPK_DSM_C_2, 0xf2 }, + { WSA884X_CDC_SPK_DSM_C_3, 0x20 }, + { WSA884X_CDC_SPK_DSM_R1, 0x83 }, + { WSA884X_CDC_SPK_DSM_R2, 0x7f }, + { WSA884X_CDC_SPK_DSM_R3, 0x9d }, + { WSA884X_CDC_SPK_DSM_R4, 0x82 }, + { WSA884X_CDC_SPK_DSM_R5, 0x8b }, + { WSA884X_CDC_SPK_DSM_R6, 0x9b }, + { WSA884X_CDC_SPK_DSM_R7, 0x3f }, + { WSA884X_DRE_IDLE_DET_CTL, 0x0f }, + { WSA884X_PDM_WD_CTL, 0x01 }, + { WSA884X_DRE_CTL_0, 0xf0 }, + { WSA884X_DRE_CTL_1, 0x00 }, + { WSA884X_BOP_DEGLITCH_CTL, 0x11 }, + { WSA884X_VBAT_CAL_CTL, 0x05 }, + { WSA884X_VBAT_THRM_FLT_CTL, 0x79 }, + { WSA884X_GAIN_RAMPING_MIN, 0x0e }, + { WSA884X_CLSH_CTL_0, 0x00 }, + { WSA884X_CLSH_V_HD_PA, 0x13 }, + { WSA884X_CLSH_SOFT_MAX, 0xff }, + { WSA884X_ANA_WO_CTL_0, 0x9d }, + { WSA884X_ANA_WO_CTL_1, 0x00 }, + { WSA884X_OTP_REG_38, 0x08 }, + { WSA884X_OTP_REG_40, 0x20 }, + { WSA884X_REF_CTRL, 0xd1 }, + { WSA884X_UVLO_PROG, 0x33 }, + { WSA884X_UVLO_PROG1, 0x60 }, + { WSA884X_BOP1_PROG, 0x22 }, + { WSA884X_BOP2_PROG, 0x44 }, + { WSA884X_ZX_CTRL1, 0xf8 }, + { WSA884X_STB_CTRL1, 0x6a }, + { WSA884X_ILIM_CTRL1, 0xe3 }, + { WSA884X_CURRENT_LIMIT, 0xd4 }, + { WSA884X_TOP_CTRL1, 0xd2 }, + { WSA884X_OCP_CTL, 0xf6 }, + { WSA884X_DAC_VCM_CTRL_REG2, 0x06 }, + { WSA884X_DAC_VCM_CTRL_REG3, 0x14 }, + { WSA884X_DAC_VCM_CTRL_REG4, 0x19 }, + { WSA884X_DAC_VCM_CTRL_REG5, 0x1b }, + { WSA884X_DAC_VCM_CTRL_REG6, 0x1c }, + { WSA884X_DAC_VCM_CTRL_REG7, 0x02 }, + { WSA884X_CKWD_CTL_1, 0x13 }, + { WSA884X_PWRSTAGE_CTRL2, 0xf1 }, + { WSA884X_CURRENT_LIMIT, 0x44 }, +}; + +static const struct reg_sequence sp11_windows_start[] = { + { WSA884X_ISENSE2, 0x07 }, + { WSA884X_VSENSE1, 0x67 }, + { WSA884X_INTR_MASK0, 0x90 }, + { WSA884X_INTR_MASK1, 0x00 }, + { WSA884X_CLSH_CTL_0, 0x67 }, + { WSA884X_PWRSTG_DBG, 0x08 }, + { WSA884X_PDRV_HS_CTL, 0x52 }, + { WSA884X_PA_FSM_EN, 0x01 }, + { WSA884X_PWRSTG_DBG, 0x0c }, + { WSA884X_PDRV_HS_CTL, 0x5a }, +}; + +static const struct reg_sequence sp11_windows_stop[] = { + { WSA884X_PA_FSM_EN, 0x00 }, + { WSA884X_INTR_MASK0, 0xff }, + { WSA884X_INTR_MASK1, 0x03 }, + { WSA884X_INTR_CLEAR0, 0xff }, + { WSA884X_INTR_CLEAR1, 0x03 }, + { WSA884X_CLSH_CTL_0, 0x00 }, +}; + +static bool wsa884x_sp11_windows_profile(struct wsa884x_priv *wsa884x) +{ + return wsa884x->sp11_windows_lifecycle && + wsa884x->supply_config == WSA884X_SUPPLY_2S; +} + +static void wsa884x_sp11_write_sequence(struct wsa884x_priv *wsa884x, + const struct reg_sequence *sequence, + size_t count) +{ + size_t i; + + for (i = 0; i < count; i++) + regmap_write(wsa884x->regmap, sequence[i].reg, sequence[i].def); +} + static void wsa884x_init(struct wsa884x_priv *wsa884x) { unsigned int wo_ctl_0; + unsigned int supply_config; unsigned int variant = 0; if (!regmap_read(wsa884x->regmap, WSA884X_OTP_REG_0, &variant)) variant = variant & WSA884X_OTP_REG_0_ID_MASK; + if (regmap_read(wsa884x->regmap, WSA884X_VPHX_SYS_EN_STATUS, + &supply_config)) { + wsa884x->supply_config = WSA884X_SUPPLY_1S; + dev_warn(wsa884x->dev, + "cannot read VPHX supply configuration; retaining 1S defaults\n"); + } else { + wsa884x->supply_config = supply_config; + if (supply_config == WSA884X_SUPPLY_2S) + dev_info(wsa884x->dev, + "detected VPHX supply configuration: 2S\n"); + else if (supply_config != WSA884X_SUPPLY_1S) + dev_warn(wsa884x->dev, + "unsupported VPHX supply configuration %#x; retaining upstream defaults\n", + supply_config); + } + + if (wsa884x_sp11_windows_profile(wsa884x)) { + wsa884x_sp11_write_sequence(wsa884x, sp11_windows_cold_init, + ARRAY_SIZE(sp11_windows_cold_init)); + wsa884x->hw_init = true; + return; + } + regmap_multi_reg_write(wsa884x->regmap, wsa884x_reg_init, ARRAY_SIZE(wsa884x_reg_init)); + wsa884x_apply_supply_config(wsa884x); wo_ctl_0 = 0xc; + if (wsa884x->supply_config == WSA884X_SUPPLY_2S) + wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_MASK, + wsa884x->supply_config); wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK, WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MODE_SPEAKER); /* Assume that compander is enabled by default unless it is haptics sku */ @@ -1533,16 +1851,189 @@ static void wsa884x_init(struct wsa884x_priv *wsa884x) regmap_write(wsa884x->regmap, WSA884X_ANA_WO_CTL_0, wo_ctl_0); wsa884x_set_gain_parameters(wsa884x); + wsa884x_apply_sp11_windows_analog_tail(wsa884x); wsa884x->hw_init = true; } +static void wsa884x_reset_pa_fsm(struct wsa884x_priv *wsa884x) +{ + regmap_update_bits(wsa884x->regmap, WSA884X_PA_FSM_CTL0, + WSA884X_PA_FSM_RESET_MASK, 0); + regmap_update_bits(wsa884x->regmap, WSA884X_PA_FSM_CTL0, + WSA884X_PA_FSM_RESET_MASK, + WSA884X_PA_FSM_RESET_MASK); + regmap_update_bits(wsa884x->regmap, WSA884X_PA_FSM_CTL0, + WSA884X_PA_FSM_RESET_MASK, 0); +} + +/* + * Recover the PA state machine using the sequence from Qualcomm's downstream + * WSA884x driver. Caller serializes this with sp_lock. + */ +static int wsa884x_recover_pa(struct wsa884x_priv *wsa884x, bool reenable) +{ + unsigned int sta0 = 0, sta1 = 0, err0 = 0, err1 = 0; + int ret = -EIO; + int retry; + + regmap_update_bits(wsa884x->regmap, WSA884X_PA_FSM_EN, + WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK, 0); + regmap_read(wsa884x->regmap, WSA884X_PA_FSM_STA0, &sta0); + regmap_read(wsa884x->regmap, WSA884X_PA_FSM_STA1, &sta1); + regmap_read(wsa884x->regmap, WSA884X_PA_FSM_ERR_COND0, &err0); + regmap_read(wsa884x->regmap, WSA884X_PA_FSM_ERR_COND1, &err1); + + dev_warn_ratelimited(wsa884x->dev, + "PA fault: sta0=%#02x sta1=%#02x err0=%#02x err1=%#02x; resetting FSM\n", + sta0, sta1, err0, err1); + + wsa884x_reset_pa_fsm(wsa884x); + regmap_write(wsa884x->regmap, WSA884X_INTR_CLEAR1, BIT(1)); + if (!reenable) + return 0; + + for (retry = 0; retry < WSA884X_PA_RECOVERY_RETRIES; retry++) { + regmap_update_bits(wsa884x->regmap, WSA884X_PA_FSM_EN, + WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK, + WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK); + usleep_range(1000, 1100); + + ret = regmap_read(wsa884x->regmap, WSA884X_PA_FSM_STA1, &sta1); + if (!ret && !(sta1 & WSA884X_PA_ERROR_MASK)) { + regmap_write(wsa884x->regmap, WSA884X_INTR_CLEAR1, BIT(1)); + dev_info(wsa884x->dev, + "PA state machine recovered after %d attempt(s)\n", + retry + 1); + return 0; + } + + regmap_update_bits(wsa884x->regmap, WSA884X_PA_FSM_EN, + WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK, 0); + wsa884x_reset_pa_fsm(wsa884x); + } + + regmap_read(wsa884x->regmap, WSA884X_PA_FSM_ERR_COND0, &err0); + regmap_read(wsa884x->regmap, WSA884X_PA_FSM_ERR_COND1, &err1); + dev_err_ratelimited(wsa884x->dev, + "PA recovery failed: sta1=%#02x err0=%#02x err1=%#02x; amplifier left disabled\n", + sta1, err0, err1); + + return ret ?: -EIO; +} + +static void wsa884x_pa_health_work(struct work_struct *work) +{ + struct wsa884x_priv *wsa884x = + container_of(to_delayed_work(work), struct wsa884x_priv, + pa_health_work); + static const unsigned int observe_regs[] = { + WSA884X_PA_FSM_EN, + WSA884X_PA_FSM_STA0, + WSA884X_PA_FSM_STA1, + WSA884X_PA_FSM_ERR_COND0, + WSA884X_PA_FSM_ERR_COND1, + WSA884X_INTR_STATUS0, + WSA884X_INTR_STATUS1, + WSA884X_DOUT_MSB, + WSA884X_DOUT_LSB, + WSA884X_TEMP_DOUT_MSB, + WSA884X_TEMP_DOUT_LSB, + WSA884X_VBAT_DOUT_MSB, + WSA884X_VBAT_DOUT_LSB, + WSA884X_WAVG_STA, + WSA884X_CPS_CTL, + WSA884X_CURRENT_LIMIT, + }; + unsigned int observe[ARRAY_SIZE(observe_regs)] = {}; + unsigned int sta1 = 0; + unsigned long read_failures = 0; + bool rearm; + unsigned int i; + int ret; + + ret = pm_runtime_resume_and_get(wsa884x->dev); + if (ret < 0) + goto out_rearm; + + mutex_lock(&wsa884x->sp_lock); + if (!wsa884x->pa_on) + goto out_unlock; + + ret = regmap_read(wsa884x->regmap, WSA884X_PA_FSM_STA1, &sta1); + if (!ret && (sta1 & WSA884X_PA_ERROR_MASK) && + wsa884x->pa_recovery_failures < WSA884X_PA_RECOVERY_FAILURES) { + ret = wsa884x_recover_pa(wsa884x, true); + if (ret) + wsa884x->pa_recovery_failures++; + else + wsa884x->pa_recovery_failures = 0; + } + + if (wsa884x->observe_remaining) { + for (i = 0; i < ARRAY_SIZE(observe_regs); i++) { + ret = regmap_read(wsa884x->regmap, observe_regs[i], + &observe[i]); + if (ret) + read_failures |= BIT(i); + } + + dev_info(wsa884x->dev, + "SP11 WSA live sample=%u failed=%#lx pa=%02x sta=%02x/%02x err=%02x/%02x intr=%02x/%02x adc=%02x%02x temp=%02x%02x vbat=%02x%02x wavg=%02x cps=%02x ilim=%02x\n", + wsa884x->observe_sequence++, read_failures, + observe[0], observe[1], observe[2], observe[3], observe[4], + observe[5], observe[6], observe[7], observe[8], observe[9], + observe[10], observe[11], observe[12], observe[13], + observe[14], observe[15]); + wsa884x->observe_remaining--; + } + +out_unlock: + mutex_unlock(&wsa884x->sp_lock); + pm_runtime_mark_last_busy(wsa884x->dev); + pm_runtime_put_autosuspend(wsa884x->dev); + +out_rearm: + rearm = READ_ONCE(wsa884x->pa_on); + if (rearm) + schedule_delayed_work(&wsa884x->pa_health_work, + msecs_to_jiffies(WSA884X_PA_HEALTH_INTERVAL_MS)); +} + static int wsa884x_update_status(struct sdw_slave *slave, enum sdw_slave_status status) { struct wsa884x_priv *wsa884x = dev_get_drvdata(&slave->dev); int ret; + /* + * On Denali the ordinary SoundWire clock-stop path transiently reports + * UNATTACHED even though the WSA8845 supplies/reset stay resident. + * Shipping Windows initializes the codec once and does not replay its + * 63-write cold transaction on normal speaker wakes. Retain that + * initialized state across the resident clock-stop detach/attach pair; + * cache-only still protects accesses while the link is unavailable. + * + * The first attach is unchanged because hw_init is false. Full context + * loss/system-suspend recovery remains a separate lifecycle gate. + */ + if (wsa884x_sp11_windows_profile(wsa884x) && wsa884x->hw_init) { + if (status == SDW_SLAVE_UNATTACHED) { + regcache_cache_only(wsa884x->regmap, true); + return 0; + } + + if (status == SDW_SLAVE_ATTACHED) { + regcache_cache_only(wsa884x->regmap, false); + ret = regcache_sync(wsa884x->regmap); + if (ret < 0) { + dev_err(&slave->dev, "Cannot sync retained regmap cache\n"); + return ret; + } + return 0; + } + } + if (status == SDW_SLAVE_UNATTACHED) { wsa884x->hw_init = false; regcache_cache_only(wsa884x->regmap, true); @@ -1630,6 +2121,20 @@ static int wsa884x_set_swr_port(struct snd_kcontrol *kcontrol, struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; int portidx = mixer->reg; + /* + * A DT-enabled CPS path is part of the board wiring, not an optional + * userspace route. In particular, alsa-restore may replay an older + * control state that predates CPS support and otherwise disable port 6 + * after probe. Keep the firmware-selected sidechain enabled. + */ + if (portidx == WSA884X_PORT_CPS && wsa884x->cps_enabled) { + if (wsa884x->port_enable[portidx]) + return 0; + + wsa884x->port_enable[portidx] = true; + return 1; + } + if (ucontrol->value.integer.value[0]) { if (wsa884x->port_enable[portidx]) return 0; @@ -1659,6 +2164,9 @@ static void wsa884x_spkr_post_pmu(struct snd_soc_component *component, { unsigned int curr_limit, curr_ovrd_en; + if (wsa884x_sp11_windows_profile(wsa884x)) + return; + wsa884x_set_gain_parameters(wsa884x); if (wsa884x->dev_mode == WSA884X_RECEIVER) { snd_soc_component_write_field(component, WSA884X_DRE_CTL_0, @@ -1677,7 +2185,10 @@ static void wsa884x_spkr_post_pmu(struct snd_soc_component *component, if (wsa884x->port_enable[WSA884X_PORT_PBR]) { curr_ovrd_en = 0x0; - curr_limit = 0x15; + if (wsa884x->supply_config == WSA884X_SUPPLY_2S) + curr_limit = 0x11; + else + curr_limit = 0x15; } else { curr_ovrd_en = 0x1; if (wsa884x->dev_mode == WSA884X_RECEIVER) @@ -1703,23 +2214,39 @@ static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w, case SND_SOC_DAPM_POST_PMU: mutex_lock(&wsa884x->sp_lock); wsa884x->pa_on = true; + wsa884x->pa_recovery_failures = 0; + wsa884x->observe_remaining = min_t(unsigned int, + READ_ONCE(sp11_observe_samples), + WSA884X_SP11_OBSERVE_MAX_SAMPLES); + wsa884x->observe_sequence = 0; mutex_unlock(&wsa884x->sp_lock); + if (wsa884x->observe_remaining) + dev_info(wsa884x->dev, + "SP11 WSA live observer armed: samples=%u interval=%u ms\n", + wsa884x->observe_remaining, + WSA884X_PA_HEALTH_INTERVAL_MS); wsa884x_spkr_post_pmu(component, wsa884x); - snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL, - WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK, - 0x1); + if (!wsa884x_sp11_windows_profile(wsa884x)) + snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL, + WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK, + 0x1); + mod_delayed_work(system_wq, &wsa884x->pa_health_work, + msecs_to_jiffies(WSA884X_PA_HEALTH_INTERVAL_MS)); break; case SND_SOC_DAPM_PRE_PMD: - snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL, - WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK, - 0x0); - mutex_lock(&wsa884x->sp_lock); wsa884x->pa_on = false; + wsa884x->observe_remaining = 0; mutex_unlock(&wsa884x->sp_lock); + cancel_delayed_work_sync(&wsa884x->pa_health_work); + + if (!wsa884x_sp11_windows_profile(wsa884x)) + snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL, + WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK, + 0x0); break; } @@ -1773,22 +2300,79 @@ static int wsa884x_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev); + struct sdw_port_config port_config[WSA884X_MAX_SWR_PORTS]; + struct sdw_stream_config sconfig = { + .ch_count = 1, + .bps = 1, + .type = SDW_STREAM_PDM, + }; + u32 enabled_mask = 0; + u32 selected_mask = 0; + int active_ports = 0; int i; - wsa884x->active_ports = 0; for (i = 0; i < WSA884X_MAX_SWR_PORTS; i++) { if (!wsa884x->port_enable[i]) continue; - wsa884x->port_config[wsa884x->active_ports] = wsa884x_pconfig[i]; - wsa884x->active_ports++; + enabled_mask |= BIT(i); + + if (dai->id == 0) { + /* + * Playback uses the three receive data ports. PBR, + * VISENSE and CPS are not PCM playback lanes. + */ + if (i != WSA884X_PORT_DAC && + i != WSA884X_PORT_COMP && + i != WSA884X_PORT_BOOST) + continue; + } else if (dai->id == 1) { + if (i != WSA884X_PORT_VISENSE) + continue; + } else if (dai->id == 2) { + if (!wsa884x->cps_enabled || i != WSA884X_PORT_CPS) + continue; + } else { + continue; + } + + selected_mask |= BIT(i); + port_config[active_ports] = wsa884x_pconfig[i]; + if (i == WSA884X_PORT_VISENSE) + port_config[active_ports].ch_mask = + wsa884x->visense_channel_mask; + if (i == WSA884X_PORT_CPS) { + port_config[active_ports].transport_params_override_mask = + SDW_PORT_CONFIG_OVERRIDE_OFFSET1; + port_config[active_ports].transport_params_override.offset1 = + wsa884x->cps_offset1; + } + active_ports++; } - wsa884x->sconfig.frame_rate = params_rate(params); - - return sdw_stream_add_slave(wsa884x->slave, &wsa884x->sconfig, - wsa884x->port_config, wsa884x->active_ports, - wsa884x->sruntime); + dev_info(dai->dev, + "SP11 SoundWire selection: dai=%d enabled-mask=%#x selected-mask=%#x rate=%u\n", + dai->id, enabled_mask, selected_mask, params_rate(params)); + + if (!active_ports) + return -ENODEV; + + sconfig.frame_rate = params_rate(params); + sconfig.direction = dai->id == 0 ? SDW_DATA_DIR_RX : SDW_DATA_DIR_TX; + + dev_info(dai->dev, + "SP11 %s stream: rate=%u ports=%d direction=%s\n", + dai->id == 0 ? "speaker playback" : + dai->id == 1 ? "VI feedback" : "CPS feedback", + sconfig.frame_rate, active_ports, + sconfig.direction == SDW_DATA_DIR_TX ? "source" : "sink"); + for (i = 0; i < active_ports; i++) + dev_info(dai->dev, + "SP11 SoundWire port[%d]: num=%u ch-mask=%#x\n", + i, port_config[i].num, port_config[i].ch_mask); + + return sdw_stream_add_slave(wsa884x->slave, &sconfig, port_config, + active_ports, wsa884x->sruntime[dai->id]); } static int wsa884x_hw_free(struct snd_pcm_substream *substream, @@ -1796,7 +2380,7 @@ static int wsa884x_hw_free(struct snd_pcm_substream *substream, { struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev); - sdw_stream_remove_slave(wsa884x->slave, wsa884x->sruntime); + sdw_stream_remove_slave(wsa884x->slave, wsa884x->sruntime[dai->id]); return 0; } @@ -1804,6 +2388,46 @@ static int wsa884x_hw_free(struct snd_pcm_substream *substream, static int wsa884x_mute_stream(struct snd_soc_dai *dai, int mute, int stream) { struct snd_soc_component *component = dai->component; + struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component); + unsigned int sta1 = 0; + + /* The VI sidechain is modelled as a playback DAI for DPCM linkage. */ + if (dai->id != 0) + return 0; + + guard(mutex)(&wsa884x->sp_lock); + + if (wsa884x_sp11_windows_profile(wsa884x)) { + if (mute) { + if (wsa884x->sp11_protclk_reported) { + wsa_macro_sp11_pa_event(false); + wsa884x->sp11_protclk_reported = false; + } + + wsa884x_sp11_write_sequence(wsa884x, sp11_windows_stop, + ARRAY_SIZE(sp11_windows_stop)); + } else { + /* Recovery is contingency-only; the clean path adds no writes. */ + if (!regmap_read(wsa884x->regmap, WSA884X_PA_FSM_STA1, &sta1) && + (sta1 & WSA884X_PA_ERROR_MASK)) + wsa884x_recover_pa(wsa884x, false); + + wsa884x_sp11_write_sequence(wsa884x, sp11_windows_start, + ARRAY_SIZE(sp11_windows_start)); + usleep_range(1000, 1100); + + if (!regmap_read(wsa884x->regmap, WSA884X_PA_FSM_STA1, &sta1) && + (sta1 & WSA884X_PA_ERROR_MASK)) + wsa884x_recover_pa(wsa884x, true); + + if (!wsa884x->sp11_protclk_reported) { + wsa_macro_sp11_pa_event(true); + wsa884x->sp11_protclk_reported = true; + } + } + + return 0; + } if (mute) { snd_soc_component_write_field(component, WSA884X_DRE_CTL_1, @@ -1812,14 +2436,46 @@ static int wsa884x_mute_stream(struct snd_soc_dai *dai, int mute, int stream) snd_soc_component_write_field(component, WSA884X_PA_FSM_EN, WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK, 0x0); + if (wsa884x->supply_config == WSA884X_SUPPLY_2S) + regmap_write(wsa884x->regmap, WSA884X_CLSH_CTL_0, 0x00); } else { + /* + * A PA_ON_ERR can remain latched across a normal graph + * teardown. Clear it before trying to start the amplifier. + */ + if (!regmap_read(wsa884x->regmap, WSA884X_PA_FSM_STA1, &sta1) && + (sta1 & WSA884X_PA_ERROR_MASK)) + wsa884x_recover_pa(wsa884x, false); + + /* Exact SP11 state-2 qcaucd ordering around GLOBAL_PA_EN. */ + if (wsa884x->supply_config == WSA884X_SUPPLY_2S) { + regmap_write(wsa884x->regmap, WSA884X_CLSH_CTL_0, 0x67); + regmap_write(wsa884x->regmap, WSA884X_PWRSTG_DBG, 0x08); + regmap_write(wsa884x->regmap, WSA884X_PDRV_HS_CTL, 0x52); + } + + /* + * Windows leaves DRE_CTL_1 at 0x00 for normal SP11 speaker + * playback. The compander path is active, so do not enable + * the generic CSR fallback gain on the 2S Surface profile. + */ snd_soc_component_write_field(component, WSA884X_DRE_CTL_1, WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, - 0x1); + wsa884x->supply_config == WSA884X_SUPPLY_2S ? + 0x0 : 0x1); snd_soc_component_write_field(component, WSA884X_PA_FSM_EN, WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK, 0x1); + if (wsa884x->supply_config == WSA884X_SUPPLY_2S) { + regmap_write(wsa884x->regmap, WSA884X_PWRSTG_DBG, 0x0c); + regmap_write(wsa884x->regmap, WSA884X_PDRV_HS_CTL, 0x5a); + } + usleep_range(1000, 1100); + + if (!regmap_read(wsa884x->regmap, WSA884X_PA_FSM_STA1, &sta1) && + (sta1 & WSA884X_PA_ERROR_MASK)) + wsa884x_recover_pa(wsa884x, true); } return 0; @@ -1830,7 +2486,7 @@ static int wsa884x_set_stream(struct snd_soc_dai *dai, { struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev); - wsa884x->sruntime = stream; + wsa884x->sruntime[dai->id] = stream; return 0; } @@ -1846,6 +2502,7 @@ static const struct snd_soc_dai_ops wsa884x_dai_ops = { static struct snd_soc_dai_driver wsa884x_dais[] = { { .name = "SPKR", + .id = 0, .playback = { .stream_name = "SPKR Playback", .rates = WSA884X_RATES | WSA884X_FRAC_RATES, @@ -1857,6 +2514,39 @@ static struct snd_soc_dai_driver wsa884x_dais[] = { }, .ops = &wsa884x_dai_ops, }, + { + .name = "SPKR_VI", + .id = 1, + .playback = { + /* + * ASoC playback semantics make this feedback backend a + * companion of speaker rendering. The SoundWire stream + * itself is slave-to-master (SDW_DATA_DIR_TX). + */ + .stream_name = "SPKR VI Protection", + .rates = SNDRV_PCM_RATE_8000, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rate_min = 8000, + .rate_max = 8000, + .channels_min = 1, + .channels_max = 1, + }, + .ops = &wsa884x_dai_ops, + }, + { + .name = "SPKR_CPS", + .id = 2, + .playback = { + .stream_name = "SPKR CPS Protection", + .rates = SNDRV_PCM_RATE_24000, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rate_min = 24000, + .rate_max = 24000, + .channels_min = 1, + .channels_max = 1, + }, + .ops = &wsa884x_dai_ops, + }, }; static int wsa884x_get_temp(struct wsa884x_priv *wsa884x, long *temp) @@ -2040,12 +2730,21 @@ static int wsa884x_get_reset(struct device *dev, struct wsa884x_priv *wsa884x) return 0; } +static void wsa884x_cancel_pa_health_work(void *data) +{ + struct wsa884x_priv *wsa884x = data; + + cancel_delayed_work_sync(&wsa884x->pa_health_work); +} + static int wsa884x_probe(struct sdw_slave *pdev, const struct sdw_device_id *id) { struct device *dev = &pdev->dev; struct wsa884x_priv *wsa884x; unsigned int i; + u32 cps_offset1; + u32 visense_channel_mask; int ret; wsa884x = devm_kzalloc(dev, sizeof(*wsa884x), GFP_KERNEL); @@ -2053,6 +2752,12 @@ static int wsa884x_probe(struct sdw_slave *pdev, return -ENOMEM; mutex_init(&wsa884x->sp_lock); + INIT_DELAYED_WORK(&wsa884x->pa_health_work, wsa884x_pa_health_work); + + ret = devm_add_action_or_reset(dev, wsa884x_cancel_pa_health_work, + wsa884x); + if (ret) + return ret; for (i = 0; i < WSA884X_SUPPLIES_NUM; i++) wsa884x->supplies[i].supply = wsa884x_supply_name[i]; @@ -2079,11 +2784,41 @@ static int wsa884x_probe(struct sdw_slave *pdev, wsa884x->slave = pdev; wsa884x->dev = dev; wsa884x->dev_mode = WSA884X_SPEAKER; - wsa884x->sconfig.ch_count = 1; - wsa884x->sconfig.bps = 1; - wsa884x->sconfig.direction = SDW_DATA_DIR_RX; - wsa884x->sconfig.type = SDW_STREAM_PDM; - + wsa884x->sp11_windows_lifecycle = + of_machine_is_compatible("microsoft,denali"); + if (wsa884x->sp11_windows_lifecycle) + dev_info(dev, "SP11 Windows WSA8845 three-state lifecycle enabled\n"); + wsa884x->visense_channel_mask = + wsa884x_pconfig[WSA884X_PORT_VISENSE].ch_mask; + if (!of_property_read_u32(dev->of_node, "qcom,visense-channel-mask", + &visense_channel_mask)) { + if (!visense_channel_mask || visense_channel_mask > U8_MAX) + return dev_err_probe(dev, -EINVAL, + "invalid qcom,visense-channel-mask\n"); + wsa884x->visense_channel_mask = visense_channel_mask; + } + /* + * SoundWire supplies its own primary firmware node for the slave device, + * so the generic device-property helpers do not reach the codec's OF + * child node. Port mapping below already uses dev->of_node directly; + * read the adjacent CPS properties from that same authoritative node. + */ + wsa884x->cps_enabled = + of_property_read_bool(dev->of_node, "qcom,enable-cps"); + if (wsa884x->cps_enabled) { + ret = of_property_read_u32(dev->of_node, "qcom,cps-offset1", + &cps_offset1); + if (ret || cps_offset1 > U8_MAX) + return dev_err_probe(dev, ret ?: -ERANGE, + "invalid qcom,cps-offset1\n"); + wsa884x->cps_offset1 = cps_offset1; + /* The dedicated DT sidechain is active without requiring an + * unreleased userspace mixer profile to know about CPS. + */ + wsa884x->port_enable[WSA884X_PORT_CPS] = true; + dev_info(dev, "SP11 CPS enabled with offset1=%u\n", + wsa884x->cps_offset1); + } /* * Port map index starts with 0, however the data port for this codec * are from index 1 @@ -2092,9 +2827,16 @@ static int wsa884x_probe(struct sdw_slave *pdev, WSA884X_MAX_SWR_PORTS)) dev_dbg(dev, "Static Port mapping not specified\n"); - pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS - 1, 0); + pdev->prop.sink_ports = BIT(WSA884X_PORT_DAC + 1) | + BIT(WSA884X_PORT_COMP + 1) | + BIT(WSA884X_PORT_BOOST + 1) | + BIT(WSA884X_PORT_PBR + 1); + pdev->prop.source_ports = BIT(WSA884X_PORT_VISENSE + 1); + if (wsa884x->cps_enabled) + pdev->prop.source_ports |= BIT(WSA884X_PORT_CPS + 1); pdev->prop.simple_clk_stop_capable = true; pdev->prop.sink_dpn_prop = wsa884x_sink_dpn_prop; + pdev->prop.src_dpn_prop = wsa884x_source_dpn_prop; pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; wsa884x_reset_deassert(wsa884x); @@ -2138,8 +2880,17 @@ static int wsa884x_runtime_suspend(struct device *dev) { struct regmap *regmap = dev_get_regmap(dev, NULL); + /* + * Runtime PM only clock-stops the internal SoundWire link on SP11; the + * WSA supplies and reset remain asserted and the codec advertises simple + * clock-stop capability. Do not mark the entire 390-entry cache dirty as + * though hardware context had been lost. Regmap already marks the cache + * dirty for writes made while cache-only, so runtime_resume's sync still + * flushes genuine suspended-time changes. The SoundWire UNATTACHED -> + * ATTACHED recovery path intentionally retains its full dirty-cache restore + * as a conservative context-loss fallback. + */ regcache_cache_only(regmap, true); - regcache_mark_dirty(regmap); return 0; } diff --git a/sound/soc/qcom/qdsp6/audioreach.c b/sound/soc/qcom/qdsp6/audioreach.c index e6e9eb2e85aa1f..3571b7f28efbca 100644 --- a/sound/soc/qcom/qdsp6/audioreach.c +++ b/sound/soc/qcom/qdsp6/audioreach.c @@ -3,6 +3,7 @@ #include #include +#include #include #include #include @@ -12,6 +13,8 @@ #include "q6apm.h" #include "audioreach.h" +#define AUDIOREACH_DSP_EUNSUPPORTED 3 + /* SubGraph Config */ struct apm_sub_graph_data { struct apm_sub_graph_cfg sub_graph_cfg; @@ -55,14 +58,22 @@ struct apm_container_obj { struct apm_cont_prop_id_domain domain; } __packed; +struct apm_container_extended_obj { + struct apm_container_obj common; + + struct apm_prop_data parent_data; + struct apm_cont_prop_id_parent_container parent; + + struct apm_prop_data heap_data; + struct apm_cont_prop_id_headp_id heap; +} __packed; + struct apm_container_params { struct apm_module_param_data param_data; uint32_t num_containers; - struct apm_container_obj cont_obj[]; + u8 cont_obj[]; } __packed; -#define APM_CONTAINER_PSIZE(p, n) ALIGN(struct_size(p, cont_obj, n), 8) - /* Module List config */ struct apm_mod_list_obj { /* Modules list cfg */ @@ -109,6 +120,15 @@ struct apm_mod_conn_list_params { #define APM_MOD_CONN_PSIZE(p, n) ALIGN(struct_size(p, conn_obj, n), 8) +struct apm_mod_ctrl_link_list_params { + struct apm_module_param_data param_data; + u32 num_ctrl_links; + u8 ctrl_link_cfg[]; +} __packed; + +#define APM_MOD_CTRL_LINK_PSIZE(p, n) \ + ALIGN(struct_size(p, ctrl_link_cfg, n), 8) + struct apm_graph_open_params { struct apm_cmd_header *cmd_header; struct apm_sub_graph_params *sg_data; @@ -116,6 +136,7 @@ struct apm_graph_open_params { struct apm_module_list_params *mod_list_data; struct apm_prop_list_params *mod_prop_data; struct apm_mod_conn_list_params *mod_conn_list_data; + struct apm_mod_ctrl_link_list_params *mod_ctrl_link_data; } __packed; struct apm_pcm_module_media_fmt_cmd { @@ -308,13 +329,21 @@ void audioreach_set_default_channel_mapping(u8 *ch_map, int num_channels) } EXPORT_SYMBOL_GPL(audioreach_set_default_channel_mapping); -static void apm_populate_container_config(struct apm_container_obj *cfg, +static size_t apm_container_obj_size(const struct audioreach_container *cont) +{ + return cont->has_extended_properties ? + sizeof(struct apm_container_extended_obj) : + sizeof(struct apm_container_obj); +} + +static void apm_populate_container_config(void *data, const struct audioreach_container *cont) { + struct apm_container_obj *cfg = data; /* Container Config */ cfg->container_cfg.container_id = cont->container_id; - cfg->container_cfg.num_prop = 4; + cfg->container_cfg.num_prop = cont->has_extended_properties ? 6 : 4; /* Capability list */ cfg->cap_data.prop_id = APM_CONTAINER_PROP_ID_CAPABILITY_LIST; @@ -336,6 +365,21 @@ static void apm_populate_container_config(struct apm_container_obj *cfg, cfg->domain_data.prop_id = APM_CONTAINER_PROP_ID_PROC_DOMAIN; cfg->domain_data.prop_size = sizeof(struct apm_cont_prop_id_domain); cfg->domain.proc_domain = cont->proc_domain; + + if (cont->has_extended_properties) { + struct apm_container_extended_obj *ext = data; + + ext->parent_data.prop_id = + APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID; + ext->parent_data.prop_size = + sizeof(struct apm_cont_prop_id_parent_container); + ext->parent.parent_container_id = cont->parent_container_id; + + ext->heap_data.prop_id = APM_CONTAINER_PROP_ID_HEAP_ID; + ext->heap_data.prop_size = + sizeof(struct apm_cont_prop_id_headp_id); + ext->heap.heap_id = cont->heap_id; + } } static void apm_populate_sub_graph_config(struct apm_sub_graph_data *cfg, @@ -398,6 +442,8 @@ static void audioreach_populate_graph(struct q6apm *apm, { struct apm_mod_conn_list_params *mc_data = open->mod_conn_list_data; struct apm_module_list_params *ml_data = open->mod_list_data; + struct apm_mod_ctrl_link_list_params *cl_data = open->mod_ctrl_link_data; + u8 *ctrl_link_cfg = cl_data ? cl_data->ctrl_link_cfg : NULL; struct apm_prop_list_params *mp_data = open->mod_prop_data; struct apm_container_params *c_data = open->cont_data; struct apm_sub_graph_params *sg_data = open->sg_data; @@ -407,14 +453,15 @@ static void audioreach_populate_graph(struct q6apm *apm, struct apm_module_conn_obj *conn_obj; struct audioreach_module *module; struct audioreach_sub_graph *sg; - struct apm_container_obj *cobj; + u8 *cobj = c_data->cont_obj; struct apm_mod_list_obj *mlobj; int i = 0; mlobj = &ml_data->mod_list_obj[0]; - if (info->dst_mod_inst_id && info->src_mod_inst_id) { + if (!info->internal_vmixer_connection && + info->dst_mod_inst_id && info->src_mod_inst_id) { conn_obj = &mc_data->conn_obj[nconn]; conn_obj->src_mod_inst_id = info->src_mod_inst_id; conn_obj->src_mod_op_port_id = info->src_mod_op_port_id; @@ -429,8 +476,6 @@ static void audioreach_populate_graph(struct q6apm *apm, apm_populate_sub_graph_config(sg_cfg, sg); list_for_each_entry(container, &sg->container_list, node) { - cobj = &c_data->cont_obj[ncontainer]; - apm_populate_container_config(cobj, container); apm_populate_module_list_obj(mlobj, container, sg->sub_graph_id); @@ -456,9 +501,25 @@ static void audioreach_populate_graph(struct q6apm *apm, nconn++; } } + + if (module->ctrl_link_data) { + u32 size = le32_to_cpu(module->ctrl_link_data->size); + + /* + * GRAPH_OPEN has one aggregate count, so omit each + * topology block's leading num_ctrl_link_cfg. + */ + if (size > sizeof(u32)) { + memcpy(ctrl_link_cfg, + (u8 *)module->ctrl_link_data->data + 4, + size - sizeof(u32)); + ctrl_link_cfg += size - sizeof(u32); + } + } } mlobj = (void *) mlobj + APM_MOD_LIST_OBJ_PSIZE(mlobj, container->num_modules); + cobj += apm_container_obj_size(container); ncontainer++; } @@ -468,14 +529,14 @@ static void audioreach_populate_graph(struct q6apm *apm, void *audioreach_alloc_graph_pkt(struct q6apm *apm, const struct audioreach_graph_info *info) { - int payload_size, sg_sz, cont_sz, ml_sz, mp_sz, mc_sz; + int payload_size, sg_sz, cont_sz, ml_sz, mp_sz, mc_sz, cl_sz = 0; struct apm_module_param_data *param_data; - struct apm_container_params *cont_params; struct audioreach_container *container; struct apm_sub_graph_params *sg_params; struct apm_mod_conn_list_params *mcon; struct apm_graph_open_params params; struct apm_prop_list_params *mprop; + struct apm_mod_ctrl_link_list_params *mctrl; struct audioreach_module *module; struct audioreach_sub_graph *sgs; struct apm_mod_list_obj *mlobj; @@ -483,6 +544,8 @@ void *audioreach_alloc_graph_pkt(struct q6apm *apm, int num_connections = 0; int num_containers = 0; int num_sub_graphs = 0; + int num_ctrl_links = 0; + int ctrl_link_cfg_size = 0; int num_modules = 0; int num_modules_list; struct gpr_pkt *pkt; @@ -490,9 +553,11 @@ void *audioreach_alloc_graph_pkt(struct q6apm *apm, sg_list = &info->sg_list; ml_sz = 0; + cont_sz = sizeof(struct apm_container_params); /* add FE-BE connections */ - if (info->dst_mod_inst_id && info->src_mod_inst_id) + if (!info->internal_vmixer_connection && + info->dst_mod_inst_id && info->src_mod_inst_id) num_connections++; list_for_each_entry(sgs, sg_list, node) { @@ -500,25 +565,35 @@ void *audioreach_alloc_graph_pkt(struct q6apm *apm, list_for_each_entry(container, &sgs->container_list, node) { num_containers++; num_modules += container->num_modules; + cont_sz += apm_container_obj_size(container); ml_sz = ml_sz + sizeof(struct apm_module_list_params) + APM_MOD_LIST_OBJ_PSIZE(mlobj, container->num_modules); list_for_each_entry(module, &container->modules_list, node) { num_connections += module->num_connections; + if (module->ctrl_link_data) { + u32 size = le32_to_cpu(module->ctrl_link_data->size); + + num_ctrl_links += + get_unaligned_le32(module->ctrl_link_data->data); + ctrl_link_cfg_size += size - sizeof(u32); + } } } } num_modules_list = num_containers; sg_sz = APM_SUB_GRAPH_PSIZE(sg_params, num_sub_graphs); - cont_sz = APM_CONTAINER_PSIZE(cont_params, num_containers); + cont_sz = ALIGN(cont_sz, 8); ml_sz = ALIGN(ml_sz, 8); mp_sz = APM_MOD_PROP_PSIZE(mprop, num_modules); mc_sz = APM_MOD_CONN_PSIZE(mcon, num_connections); + if (num_ctrl_links) + cl_sz = APM_MOD_CTRL_LINK_PSIZE(mctrl, ctrl_link_cfg_size); - payload_size = sg_sz + cont_sz + ml_sz + mp_sz + mc_sz; + payload_size = sg_sz + cont_sz + ml_sz + mp_sz + mc_sz + cl_sz; pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_GRAPH_OPEN, 0); if (IS_ERR(pkt)) return pkt; @@ -570,6 +645,23 @@ void *audioreach_alloc_graph_pkt(struct q6apm *apm, params.mod_conn_list_data->num_connections = num_connections; p += mc_sz; + /* Module Control Links */ + if (num_ctrl_links) { + params.mod_ctrl_link_data = p; + param_data = ¶ms.mod_ctrl_link_data->param_data; + param_data->module_instance_id = APM_MODULE_INSTANCE_ID; + param_data->param_id = APM_PARAM_ID_MODULE_CTRL_LINK_CFG; + /* + * Keep alignment bytes outside param_size. The DSP payload is + * the exact aggregate count followed by the topology bodies. + */ + param_data->param_size = sizeof(u32) + ctrl_link_cfg_size; + params.mod_ctrl_link_data->num_ctrl_links = num_ctrl_links; + p += cl_sz; + } else { + params.mod_ctrl_link_data = NULL; + } + audioreach_populate_graph(apm, info, ¶ms, sg_list, num_sub_graphs); return pkt; @@ -610,7 +702,10 @@ int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, rc = -ETIMEDOUT; } else if (result->status > 0) { dev_err(dev, "DSP returned error[%x] %x\n", hdr->opcode, result->status); - rc = -EINVAL; + if (result->status == AUDIOREACH_DSP_EUNSUPPORTED) + rc = -EOPNOTSUPP; + else + rc = -EINVAL; } else { /* DSP successfully finished the command */ rc = 0; @@ -764,7 +859,9 @@ int audioreach_send_u32_param(struct q6apm_graph *graph, int payload_size = sizeof(uint32_t) + APM_MODULE_PARAM_DATA_SIZE; void *p; - struct gpr_pkt *pkt __free(kfree) = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0); + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0, + graph->port->id, module->instance_id); if (IS_ERR(pkt)) return -ENOMEM; @@ -780,7 +877,7 @@ int audioreach_send_u32_param(struct q6apm_graph *graph, param = p; *param = param_val; - return q6apm_send_cmd_sync(graph->apm, pkt, 0); + return audioreach_graph_send_cmd_sync(graph, pkt, 0); } EXPORT_SYMBOL_GPL(audioreach_send_u32_param); @@ -805,6 +902,38 @@ static int audioreach_module_enable(struct q6apm_graph *graph, return audioreach_send_u32_param(graph, module, PARAM_ID_MODULE_ENABLE, enable); } +static int audioreach_sp11_set_protection_enabled(struct q6apm_graph *graph, + bool enable) +{ + const struct audioreach_module *sp = NULL, *spvi = NULL; + struct audioreach_container *container; + struct audioreach_sub_graph *sg; + struct audioreach_module *module; + int ret; + + list_for_each_entry(sg, &graph->info->sg_list, node) { + list_for_each_entry(container, &sg->container_list, node) { + list_for_each_entry(module, &container->modules_list, node) { + if (module->module_id == MODULE_ID_SPEAKER_PROTECTION) + sp = module; + else if (module->module_id == + MODULE_ID_SPEAKER_PROTECTION_VI) + spvi = module; + } + } + } + + if (!sp || !spvi) + return -ENODEV; + + /* Bring feedback up before render; tear render down before feedback. */ + ret = audioreach_module_enable(graph, enable ? spvi : sp, enable); + if (ret) + return ret; + + return audioreach_module_enable(graph, enable ? sp : spvi, enable); +} + static int audioreach_gapless_set_media_format(struct q6apm_graph *graph, const struct audioreach_module *module, const struct audioreach_module_config *cfg) @@ -831,6 +960,518 @@ static int audioreach_set_module_config(struct q6apm_graph *graph, return q6apm_send_cmd_sync(graph->apm, pkt, 0); } +static struct audioreach_module_priv_data * +audioreach_module_stage(const struct audioreach_module *module, u32 type) +{ + switch (type) { + case SND_SOC_AR_TPLG_GRAPH_CAL_CFG_TYPE: + return module->graph_cal_data; + case SND_SOC_AR_TPLG_RENDER_EP_CFG_TYPE: + return module->render_ep_data; + case SND_SOC_AR_TPLG_SP_TAG_CFG_TYPE: + return module->sp_tag_data; + case SND_SOC_AR_TPLG_SPVI_TAG_CFG_TYPE: + return module->spvi_tag_data; + case SND_SOC_AR_TPLG_VI_EP_CFG_TYPE: + return module->vi_ep_data; + case SND_SOC_AR_TPLG_PROTECTION_DYNAMIC_CFG_TYPE: + return module->protection_dynamic_data; + case SND_SOC_AR_TPLG_VOLUME_GAIN_CFG_TYPE: + return module->volume_gain_data; + case SND_SOC_AR_TPLG_VOLUME_FILTER_CFG_TYPE: + return module->volume_filter_data; + case SND_SOC_AR_TPLG_VOLUME_MUTE_CFG_TYPE: + return module->volume_mute_data; + case SND_SOC_AR_TPLG_CHANNEL_MIXER_CFG_TYPE: + return module->channel_mixer_data; + default: + return NULL; + } +} + +static struct audioreach_module_priv_data * +audioreach_find_stage(const struct audioreach_graph_info *info, u32 type) +{ + struct audioreach_module_priv_data *found = NULL; + struct audioreach_container *container; + struct audioreach_sub_graph *sg; + struct audioreach_module *module; + + list_for_each_entry(sg, &info->sg_list, node) { + list_for_each_entry(container, &sg->container_list, node) { + list_for_each_entry(module, &container->modules_list, node) { + struct audioreach_module_priv_data *candidate; + + candidate = audioreach_module_stage(module, type); + if (!candidate) + continue; + if (found) + return ERR_PTR(-EEXIST); + found = candidate; + } + } + } + + return found; +} + +bool audioreach_graph_has_protected_calibration( + const struct audioreach_graph_info *info) +{ + return audioreach_find_stage( + info, SND_SOC_AR_TPLG_GRAPH_CAL_CFG_TYPE) != NULL; +} +EXPORT_SYMBOL_GPL(audioreach_graph_has_protected_calibration); + +static bool audioreach_graph_has_iid(const struct audioreach_graph_info *info, + u32 iid) +{ + struct audioreach_container *container; + struct audioreach_sub_graph *sg; + struct audioreach_module *module; + + list_for_each_entry(sg, &info->sg_list, node) + list_for_each_entry(container, &sg->container_list, node) + list_for_each_entry(module, &container->modules_list, node) + if (module->instance_id == iid) + return true; + + return false; +} + +static int audioreach_validate_stage_modules( + const struct audioreach_graph_info *info, + const struct audioreach_module_priv_data *stage) +{ + size_t size = le32_to_cpu(stage->size); + const u8 *cursor = (const u8 *)stage->data; + const u8 *end = cursor + size; + + while (cursor < end) { + size_t frame_size; + u32 iid = get_unaligned_le32(cursor); + u32 param_size = get_unaligned_le32(cursor + 2 * sizeof(u32)); + + if (!audioreach_graph_has_iid(info, iid)) + return -ENOENT; + frame_size = ALIGN(sizeof(struct apm_module_param_data) + + param_size, 8); + cursor += frame_size; + } + + return cursor == end ? 0 : -EINVAL; +} + +static int audioreach_send_inband_frame(struct q6apm_graph *graph, + const u8 *frame) +{ + u32 param_size = get_unaligned_le32(frame + 2 * sizeof(u32)); + size_t frame_size = ALIGN(sizeof(struct apm_module_param_data) + + param_size, 8); + void *payload; + + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_cmd_pkt( + frame_size, APM_CMD_SET_CFG, 0, graph->port->id, + get_unaligned_le32(frame)); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + payload = (u8 *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + memcpy(payload, frame, frame_size); + return audioreach_graph_send_cmd_sync(graph, pkt, 0); +} + +static int audioreach_send_get_cfg(struct q6apm_graph *graph, u32 iid, + u32 param_id, u32 param_size) +{ + struct apm_module_param_data *param; + size_t payload_size = + ALIGN(APM_MODULE_PARAM_DATA_SIZE + param_size, 8); + void *payload; + + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_cmd_pkt(payload_size, APM_CMD_GET_CFG, 0, + graph->port->id, iid); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + payload = (u8 *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + memset(payload, 0, payload_size); + param = payload; + param->module_instance_id = iid; + param->param_id = param_id; + param->param_size = param_size; + + return audioreach_graph_send_cmd_sync( + graph, pkt, APM_CMD_RSP_GET_CFG); +} + +static const u8 *audioreach_stage_frame( + const struct audioreach_module_priv_data *stage, unsigned int index) +{ + size_t size = le32_to_cpu(stage->size); + const u8 *cursor = (const u8 *)stage->data; + const u8 *end = cursor + size; + unsigned int frame_index = 0; + + while (cursor < end) { + u32 param_size = get_unaligned_le32(cursor + 2 * sizeof(u32)); + size_t frame_size = + ALIGN(sizeof(struct apm_module_param_data) + param_size, 8); + + if (frame_index++ == index) + return cursor; + cursor += frame_size; + } + + return NULL; +} + +static int audioreach_log_stage(struct q6apm_graph *graph, + const char *name, int ret) +{ + if (ret) + dev_err(graph->dev, "SP11 stage %s failed: %d\n", name, ret); + else + dev_info(graph->dev, "SP11 stage %s accepted\n", name); + + return ret; +} + +static int audioreach_validate_protection_profile( + const struct audioreach_graph_info *info, + const struct audioreach_module_priv_data *graph_cal, + const struct audioreach_module_priv_data *render_ep, + const struct audioreach_module_priv_data *sp_tag, + const struct audioreach_module_priv_data *spvi_tag, + const struct audioreach_module_priv_data *vi_ep, + const struct audioreach_module_priv_data *dynamic, + const struct audioreach_module_priv_data *volume_gain, + const struct audioreach_module_priv_data *volume_filter, + const struct audioreach_module_priv_data *volume_mute, + const struct audioreach_module_priv_data *channel_mixer) +{ + static const struct { + u32 iid; + u32 param_id; + u32 param_size; + } dynamic_layout[] = { + { 0x4027, 0x080011e9, 8 }, + { 0x4024, 0x080011f5, 24 }, + { 0x4024, 0x080011f4, 24 }, + { 0x4024, 0x080011ff, 8 }, + }; + const struct audioreach_module_priv_data *stages[] = { + graph_cal, render_ep, sp_tag, spvi_tag, vi_ep, dynamic, + volume_gain, volume_filter, volume_mute, channel_mixer, + }; + const size_t expected_sizes[] = { + 10464, 64, 1888, 1328, 64, 128, 120, 216, 120, 40, + }; + const u8 *frame; + int i, ret; + + for (i = 0; i < ARRAY_SIZE(stages); i++) { + if (!stages[i] || + le32_to_cpu(stages[i]->size) != expected_sizes[i]) + return -EINVAL; + ret = audioreach_validate_stage_modules(info, stages[i]); + if (ret) + return ret; + } + + for (i = 0; i < ARRAY_SIZE(dynamic_layout); i++) { + frame = audioreach_stage_frame(dynamic, i); + if (!frame || + get_unaligned_le32(frame) != dynamic_layout[i].iid || + get_unaligned_le32(frame + sizeof(u32)) != + dynamic_layout[i].param_id || + get_unaligned_le32(frame + 2 * sizeof(u32)) != + dynamic_layout[i].param_size) + return -EINVAL; + } + if (audioreach_stage_frame(dynamic, ARRAY_SIZE(dynamic_layout))) + return -EINVAL; + + /* Both static GET-response layouts and the dynamic stage select 2 speakers. */ + frame = audioreach_stage_frame(sp_tag, 0); + if (!frame || + get_unaligned_le32(frame) != 0x4027 || + get_unaligned_le32(frame + sizeof(u32)) != 0x080011e8 || + get_unaligned_le32(frame + sizeof(struct apm_module_param_data) + 8) != 2) + return -EINVAL; + frame = audioreach_stage_frame(spvi_tag, 0); + if (!frame || + get_unaligned_le32(frame) != 0x4024 || + get_unaligned_le32(frame + sizeof(u32)) != 0x080011f6 || + get_unaligned_le32(frame + sizeof(struct apm_module_param_data)) != 2) + return -EINVAL; + + return 0; +} + +static atomic_t sp11_frame_diag_done = ATOMIC_INIT(0); + +static void audioreach_diagnose_oob_frames(struct audioreach_graph *graph, + const u8 *data, size_t size) +{ + const u8 *cursor = data; + const u8 *end = data + size; + int first_rejected = -1; + unsigned int accepted = 0; + unsigned int rejected = 0; + unsigned int index = 0; + + if (atomic_xchg(&sp11_frame_diag_done, 1)) + return; + + while (cursor < end) { + u32 iid = get_unaligned_le32(cursor); + u32 param_id = get_unaligned_le32(cursor + sizeof(u32)); + u32 param_size = get_unaligned_le32(cursor + 2 * sizeof(u32)); + size_t frame_size = + ALIGN(sizeof(struct apm_module_param_data) + param_size, 8); + int ret; + + ret = q6apm_send_oob_config(graph, cursor, frame_size); + if (ret) { + if (first_rejected < 0) + first_rejected = index; + rejected++; + dev_err(graph->apm->dev, + "SP11 OOB frame %u offset %zu iid 0x%08x param 0x%08x size %u rejected: %d\n", + index, cursor - data, iid, param_id, + param_size, ret); + } else { + accepted++; + } + cursor += frame_size; + index++; + } + + pr_info("sp11 graph-cal frame diagnostic: frames=%u accepted=%u rejected=%u first-rejected=%d\n", + index, accepted, rejected, first_rejected); +} + +int audioreach_send_protected_graph_calibration(struct audioreach_graph *graph) +{ + const __le32 enable[] = { + cpu_to_le32(0x00004027), + cpu_to_le32(0x08001026), + cpu_to_le32(sizeof(u32)), + 0, + cpu_to_le32(1), + 0, + }; + struct audioreach_module_priv_data *graph_cal; + const u8 *cal; + u32 cal_size; + int ib, ob, tail, ret; + + graph_cal = audioreach_find_stage(graph->info, + SND_SOC_AR_TPLG_GRAPH_CAL_CFG_TYPE); + if (IS_ERR(graph_cal)) + return PTR_ERR(graph_cal); + if (!graph_cal) + return 0; + if (le32_to_cpu(graph_cal->size) != 10464) + return -EINVAL; + ret = audioreach_validate_stage_modules(graph->info, graph_cal); + if (ret) + return ret; + + cal = (const u8 *)graph_cal->data; + cal_size = le32_to_cpu(graph_cal->size); + ret = q6apm_send_oob_config(graph, cal, cal_size); + if (ret == -EOPNOTSUPP) { + /* + * Match Qualcomm GSL's graph-calibration policy. ACDB can + * include query-only parameters in this aggregate; SPF reports + * AR_EUNSUPPORTED after applying the supported records and GSL + * deliberately lets graph open continue. + */ + dev_warn(graph->apm->dev, + "graph calibration returned AR_EUNSUPPORTED; continuing as Qualcomm GSL does\n"); + + /* + * 2026-07-31 DIAGNOSTIC KERNEL ONLY. Do not merge into a daily kernel. + * + * Nothing has ever established whether SPF applies the supported + * records of this aggregate or discards all of them. The frame walk + * below answers that, but it is NOT passive: it re-sends each of the + * ~111 records individually, costing that many extra SET_CFG round + * trips during graph setup, which could stall bring-up on a slow DSP. + * Guarded by sp11_frame_diag_done so it runs at most once per boot. + * + * Behaviour is otherwise unchanged: ret is still forced to 0 below, + * exactly as Qualcomm GSL does. + */ + audioreach_diagnose_oob_frames(graph, cal, cal_size); + + ret = 0; + } + if (ret) { + ib = q6apm_send_inband_config(graph, enable, sizeof(enable)); + ob = q6apm_send_oob_config(graph, enable, sizeof(enable)); + tail = q6apm_send_oob_config(graph, cal + 24, cal_size - 24); + pr_info("sp11 graph-cal diagnostic: original=%d inband-enable=%d oob-enable=%d aggregate-without-sal-sentinel=%d\n", + ret, ib, ob, tail); + audioreach_diagnose_oob_frames(graph, cal, cal_size); + return ret; + } + return 0; +} +EXPORT_SYMBOL_GPL(audioreach_send_protected_graph_calibration); + +int audioreach_configure_protection(struct q6apm_graph *graph) +{ + struct audioreach_graph *ar_graph = graph->ar_graph; + struct audioreach_module_priv_data *graph_cal, *render_ep, *sp_tag; + struct audioreach_module_priv_data *spvi_tag, *vi_ep, *dynamic; + struct audioreach_module_priv_data *volume_gain, *volume_filter; + struct audioreach_module_priv_data *volume_mute, *channel_mixer; + const u8 *frame; + int ret; + + graph_cal = audioreach_find_stage(graph->info, + SND_SOC_AR_TPLG_GRAPH_CAL_CFG_TYPE); + if (IS_ERR(graph_cal)) + return PTR_ERR(graph_cal); + if (!graph_cal) + return 0; + + mutex_lock(&ar_graph->protection_lock); + if (ar_graph->protection_configured) { + ret = 0; + goto out; + } + + render_ep = audioreach_find_stage(graph->info, + SND_SOC_AR_TPLG_RENDER_EP_CFG_TYPE); + sp_tag = audioreach_find_stage(graph->info, + SND_SOC_AR_TPLG_SP_TAG_CFG_TYPE); + spvi_tag = audioreach_find_stage(graph->info, + SND_SOC_AR_TPLG_SPVI_TAG_CFG_TYPE); + vi_ep = audioreach_find_stage(graph->info, + SND_SOC_AR_TPLG_VI_EP_CFG_TYPE); + dynamic = audioreach_find_stage( + graph->info, SND_SOC_AR_TPLG_PROTECTION_DYNAMIC_CFG_TYPE); + volume_gain = audioreach_find_stage( + graph->info, SND_SOC_AR_TPLG_VOLUME_GAIN_CFG_TYPE); + volume_filter = audioreach_find_stage( + graph->info, SND_SOC_AR_TPLG_VOLUME_FILTER_CFG_TYPE); + volume_mute = audioreach_find_stage( + graph->info, SND_SOC_AR_TPLG_VOLUME_MUTE_CFG_TYPE); + channel_mixer = audioreach_find_stage( + graph->info, SND_SOC_AR_TPLG_CHANNEL_MIXER_CFG_TYPE); + if (IS_ERR(render_ep) || IS_ERR(sp_tag) || IS_ERR(spvi_tag) || + IS_ERR(vi_ep) || IS_ERR(dynamic) || IS_ERR(volume_gain) || + IS_ERR(volume_filter) || IS_ERR(volume_mute) || + IS_ERR(channel_mixer)) { + ret = -EEXIST; + goto out; + } + + ret = audioreach_validate_protection_profile( + graph->info, graph_cal, render_ep, sp_tag, spvi_tag, vi_ep, + dynamic, volume_gain, volume_filter, volume_mute, + channel_mixer); + if (ret) + goto out; + + if (!q6apm_sp11_vi_ready() || !q6apm_sp11_cps_ready()) { + ret = audioreach_sp11_set_protection_enabled(graph, false); + audioreach_log_stage(graph, "SP/SPVI fail-safe bypass", ret); + if (ret) + goto out; + dev_warn(graph->dev, + "SP11 protection feedback incomplete (VI=%s CPS=%s); speaker protection is bypassed\n", + q6apm_sp11_vi_ready() ? "ready" : "missing", + q6apm_sp11_cps_ready() ? "ready" : "missing"); + goto volume_config; + } + + /* Exact Windows order, with topology-critical GET counts prevalidated. */ + frame = audioreach_stage_frame(dynamic, 0); + ret = audioreach_send_inband_frame(graph, frame); + audioreach_log_stage(graph, "SP operating mode", ret); + if (ret) + goto out; + ret = q6apm_send_graph_oob_config(graph, sp_tag->data, + le32_to_cpu(sp_tag->size)); + audioreach_log_stage(graph, "SP tag calibration", ret); + if (ret) + goto out; + ret = audioreach_send_get_cfg(graph, 0x4027, 0x080011e8, 68); + audioreach_log_stage(graph, "SP configuration query", ret); + if (ret) + goto out; + ret = audioreach_send_get_cfg(graph, 0x4024, 0x080011f6, 44); + audioreach_log_stage(graph, "SPVI configuration query", ret); + if (ret) + goto out; + for (int i = 1; i < 4; i++) { + frame = audioreach_stage_frame(dynamic, i); + ret = audioreach_send_inband_frame(graph, frame); + audioreach_log_stage( + graph, i == 1 ? "SPVI R0/T0" : + i == 2 ? "SPVI channel mode" : + "SPVI processing mode", + ret); + if (ret) + goto out; + } + ret = q6apm_send_graph_oob_config(graph, spvi_tag->data, + le32_to_cpu(spvi_tag->size)); + audioreach_log_stage(graph, "SPVI tag calibration", ret); + if (ret) + goto out; + ret = q6apm_send_graph_oob_config(graph, render_ep->data, + le32_to_cpu(render_ep->size)); + audioreach_log_stage(graph, "render endpoint calibration", ret); + if (ret) + goto out; + ret = q6apm_send_graph_oob_config(graph, vi_ep->data, + le32_to_cpu(vi_ep->size)); + audioreach_log_stage(graph, "VI endpoint calibration", ret); + if (ret) + goto out; + ret = audioreach_sp11_set_protection_enabled(graph, true); + audioreach_log_stage(graph, "SP/SPVI enabled with VI+CPS feedback", ret); + if (ret) + goto out; + +volume_config: + frame = audioreach_stage_frame(volume_gain, 0); + ret = audioreach_send_inband_frame(graph, frame); + audioreach_log_stage(graph, "VOL_CTRL gain", ret); + if (ret) + goto out; + ret = q6apm_send_graph_oob_config(graph, volume_filter->data, + le32_to_cpu(volume_filter->size)); + audioreach_log_stage(graph, "full-volume MSIIR calibration", ret); + if (ret) + goto out; + frame = audioreach_stage_frame(volume_mute, 0); + ret = audioreach_send_inband_frame(graph, frame); + audioreach_log_stage(graph, "VOL_CTRL mute", ret); + if (ret) + goto out; + ret = q6apm_send_graph_oob_config( + graph, channel_mixer->data, + le32_to_cpu(channel_mixer->size)); + audioreach_log_stage(graph, "channel-mixer calibration", ret); + if (ret) + goto out; + + ar_graph->protection_configured = true; +out: + mutex_unlock(&ar_graph->protection_lock); + return ret; +} +EXPORT_SYMBOL_GPL(audioreach_configure_protection); + static int audioreach_mfc_set_media_format(struct q6apm_graph *graph, const struct audioreach_module *module, const struct audioreach_module_config *cfg) @@ -843,7 +1484,9 @@ static int audioreach_mfc_set_media_format(struct q6apm_graph *graph, int i; void *p; - struct gpr_pkt *pkt __free(kfree) = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0); + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0, + graph->port->id, module->instance_id); if (IS_ERR(pkt)) return PTR_ERR(pkt); @@ -863,7 +1506,7 @@ static int audioreach_mfc_set_media_format(struct q6apm_graph *graph, for (i = 0; i < num_channels; i++) media_format->channel_mapping[i] = cfg->channel_map[i]; - return q6apm_send_cmd_sync(graph->apm, pkt, 0); + return audioreach_graph_send_cmd_sync(graph, pkt, 0); } static int audioreach_set_compr_media_format(struct media_format *media_fmt_hdr, @@ -955,7 +1598,7 @@ int audioreach_compr_set_param(struct q6apm_graph *graph, struct media_format *header; int rc; void *p; - int iid = graph->shm_iid; + int iid = q6apm_graph_get_rx_shmem_module_iid(graph); int payload_size = sizeof(struct apm_sh_module_media_fmt_cmd); struct gpr_pkt *pkt __free(kfree) = audioreach_alloc_cmd_pkt(payload_size, @@ -1089,7 +1732,8 @@ static int audioreach_pcm_set_media_format(struct q6apm_graph *graph, payload_size = APM_PCM_MODULE_FMT_CMD_PSIZE(num_channels); struct gpr_pkt *pkt __free(kfree) = - audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0); + audioreach_alloc_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0, + graph->port->id, module->instance_id); if (IS_ERR(pkt)) return PTR_ERR(pkt); @@ -1115,44 +1759,8 @@ static int audioreach_pcm_set_media_format(struct q6apm_graph *graph, media_cfg->bits_per_sample = mcfg->bit_width; memcpy(media_cfg->channel_mapping, mcfg->channel_map, mcfg->num_channels); - return q6apm_send_cmd_sync(graph->apm, pkt, 0); -} - -int audioreach_shmem_register_event(struct q6apm_graph *graph, int bytes, int num_levels) -{ - struct apm_module_register_events *event; - struct event_cfg_sh_mem_pull_push_mode_watermark_t *level; - int i, payload_size; - struct gpr_pkt *pkt __free(kfree) = NULL; - void *p; - - if (num_levels <= 0 || bytes <= 0) - return -EINVAL; - - payload_size = sizeof(*event) + sizeof(*level) + num_levels * sizeof(uint32_t); - - pkt = audioreach_alloc_cmd_pkt(payload_size, APM_CMD_REGISTER_MODULE_EVENTS, 0, - graph->port->id, graph->shm_iid); - if (IS_ERR(pkt)) - return PTR_ERR(pkt); - - p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; - - event = p; - event->module_instance_id = graph->shm_iid; - event->event_id = EVENT_ID_SH_MEM_PULL_PUSH_MODE_WATERMARK; - event->is_register = 1; - event->event_config_payload_size = sizeof(*level) + num_levels * sizeof(uint32_t); - p += sizeof(*event); - level = p; - level->num_water_mark_levels = num_levels; - - for (i = 0; i < num_levels; i++) - level->level[i] = (i + 1) * bytes; - return audioreach_graph_send_cmd_sync(graph, pkt, 0); } -EXPORT_SYMBOL_GPL(audioreach_shmem_register_event); static int audioreach_shmem_set_media_format(struct q6apm_graph *graph, const struct audioreach_module *module, @@ -1238,6 +1846,192 @@ int audioreach_gain_set_vol_ctrl(struct q6apm *apm, } EXPORT_SYMBOL_GPL(audioreach_gain_set_vol_ctrl); +/* + * SP11 runtime module-parameter injection (added 2026-08-01). + * + * Windows does not filter audio in user space. DolbyAPOvlldp150 analyses the + * stream, computes filter coefficients, and injects them into the MSIIR + * modules that already live in the DSP graph, via gsl_set_custom_config. + * The DSP does the filtering, ahead of speaker protection. + * + * Linux had no equivalent: every module parameter was only ever sent during + * graph setup, so MSIIR sits at whatever the topology loaded (currently unity + * on 0x489e) for the life of the stream. A user-space processor could compute + * the right coefficients but had no way to deliver them. + * + * This provides that delivery path. It deliberately mirrors + * audioreach_gain_set_vol_ctrl(): build an APM_CMD_SET_CFG packet addressed to + * one module instance and send it to the live graph. + * + * SAFETY: the caller is user space, and the modules adjacent to these live in + * the speaker-protection subgraph. Both the target instance and the parameter + * id are checked against an allowlist below. Do not widen it without + * understanding what the module does; a wrong write next to SP/SP_VI is not a + * cosmetic bug. + */ + +/* MSIIR instances present in the deployed SP11 topology. */ +#define SP11_MSIIR_IID_A 0x489e +#define SP11_MSIIR_IID_B 0x48a1 + +/* MSIIR tuning parameters. Per firmware analysis these are gated behind the + * module's CAPI-initialised flag, so they are only accepted after the graph + * has started and media format has been applied. + */ +#define SP11_PARAM_MSIIR_ENABLE 0x08001020 +#define SP11_PARAM_MSIIR_PREGAIN 0x08001021 +#define SP11_PARAM_MSIIR_COEFFS 0x08001022 + +#define SP11_MAX_INJECT_PAYLOAD 1024 + +static bool sp11_inject_target_allowed(u32 iid, u32 param_id) +{ + if (iid != SP11_MSIIR_IID_A && iid != SP11_MSIIR_IID_B) + return false; + + switch (param_id) { + case SP11_PARAM_MSIIR_ENABLE: + case SP11_PARAM_MSIIR_PREGAIN: + case SP11_PARAM_MSIIR_COEFFS: + return true; + default: + return false; + } +} + +/* + * audioreach_sp11_inject_module_param() - push one parameter to a live module + * @apm:the APM instance + * @iid:target module instance id (allowlisted) + * @param_id:parameter id (allowlisted) + * @payload:parameter body + * @size:length of @payload in bytes + * + * Returns 0 on success. -EPERM if the target is not allowlisted, -EINVAL on a + * bad size, or the DSP's error if it rejects the parameter. A rejection of -22 + * typically means the module has not been initialised through the media-format + * path yet, i.e. the graph is not running. + */ +static int +audioreach_sp11_send_module_param(struct q6apm *apm, u32 iid, u32 param_id, + const void *payload, size_t size) +{ + struct apm_module_param_data *param_data; + int pkt_size; + void *p; + + if (!apm || !payload || !size || size > SP11_MAX_INJECT_PAYLOAD) + return -EINVAL; + + pkt_size = ALIGN(size, 8) + APM_MODULE_PARAM_DATA_SIZE; + + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_apm_cmd_pkt(pkt_size, APM_CMD_SET_CFG, 0); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + + param_data = p; + param_data->module_instance_id = iid; + param_data->error_code = 0; + param_data->param_id = param_id; + param_data->param_size = ALIGN(size, 8); + + p += APM_MODULE_PARAM_DATA_SIZE; + memcpy(p, payload, size); + + return q6apm_send_cmd_sync(apm, pkt, 0); +} + +int audioreach_sp11_inject_module_param(struct q6apm *apm, u32 iid, u32 param_id, + const void *payload, size_t size) +{ + if (!apm || !payload) + return -EINVAL; + + if (!size || size > SP11_MAX_INJECT_PAYLOAD) + return -EINVAL; + + if (!sp11_inject_target_allowed(iid, param_id)) { + dev_warn(apm->dev, + "SP11 inject refused: iid %#x param %#x not allowlisted\n", + iid, param_id); + return -EPERM; + } + + return audioreach_sp11_send_module_param(apm, iid, param_id, payload, size); +} +EXPORT_SYMBOL_GPL(audioreach_sp11_inject_module_param); + +#define SP11_FINAL_VOL_CTRL_IID 0x4a63 +#define SP11_PARAM_VOL_CTRL_MULTICH_GAIN 0x08001038 +#define SP11_PARAM_VOL_CTRL_MULTICH_MUTE 0x08001039 +#define SP11_VOL_CTRL_Q28_UNITY 0x10000000 +#define SP11_VOL_CTRL_NUM_CONFIGS 8 + +struct sp11_vol_ctrl_channel_gain { + u32 channel_mask_lsw; + u32 channel_mask_msw; + u32 gain_q28; +} __packed; + +struct sp11_vol_ctrl_multichannel_gain { + u32 num_config; + struct sp11_vol_ctrl_channel_gain channel[SP11_VOL_CTRL_NUM_CONFIGS]; + u32 padding; +} __packed; + +static_assert(sizeof(struct sp11_vol_ctrl_multichannel_gain) == 0x68); + +struct sp11_vol_ctrl_channel_mute { + u32 channel_mask_lsw; + u32 channel_mask_msw; + u32 mute; +} __packed; + +struct sp11_vol_ctrl_multichannel_mute { + u32 num_config; + struct sp11_vol_ctrl_channel_mute channel[SP11_VOL_CTRL_NUM_CONFIGS]; + u32 padding; +} __packed; + +static_assert(sizeof(struct sp11_vol_ctrl_multichannel_mute) == 0x68); + +int audioreach_sp11_set_final_volume_q28(struct q6apm *apm, u32 left_q28, + u32 right_q28) +{ + struct sp11_vol_ctrl_multichannel_gain cfg = { + .num_config = SP11_VOL_CTRL_NUM_CONFIGS, + .channel[0] = { .channel_mask_lsw = 0x2, .gain_q28 = left_q28 }, + .channel[1] = { .channel_mask_lsw = 0x4, .gain_q28 = right_q28 }, + }; + + if (!apm || left_q28 > SP11_VOL_CTRL_Q28_UNITY || + right_q28 > SP11_VOL_CTRL_Q28_UNITY) + return -EINVAL; + + return audioreach_sp11_send_module_param(apm, SP11_FINAL_VOL_CTRL_IID, + SP11_PARAM_VOL_CTRL_MULTICH_GAIN, &cfg, sizeof(cfg)); +} +EXPORT_SYMBOL_GPL(audioreach_sp11_set_final_volume_q28); + +int audioreach_sp11_set_final_mute(struct q6apm *apm, bool muted) +{ + struct sp11_vol_ctrl_multichannel_mute cfg = { + .num_config = SP11_VOL_CTRL_NUM_CONFIGS, + .channel[0] = { .channel_mask_lsw = 0x2, .mute = muted ? 1 : 0 }, + .channel[1] = { .channel_mask_lsw = 0x4, .mute = muted ? 1 : 0 }, + }; + + if (!apm) + return -EINVAL; + + return audioreach_sp11_send_module_param(apm, SP11_FINAL_VOL_CTRL_IID, + SP11_PARAM_VOL_CTRL_MULTICH_MUTE, &cfg, sizeof(cfg)); +} +EXPORT_SYMBOL_GPL(audioreach_sp11_set_final_mute); + static int audioreach_gain_set(struct q6apm_graph *graph, const struct audioreach_module *module) { @@ -1400,6 +2194,9 @@ int audioreach_set_media_format(struct q6apm_graph *graph, rc = audioreach_gapless_set_media_format(graph, module, cfg); break; case MODULE_ID_SPEAKER_PROTECTION: + if (module->speaker_protection_bypass) + return 0; + rc = audioreach_speaker_protection(graph, module, PARAM_ID_SP_OP_MODE_NORMAL); if (!rc) @@ -1407,6 +2204,9 @@ int audioreach_set_media_format(struct q6apm_graph *graph, break; case MODULE_ID_SPEAKER_PROTECTION_VI: + if (module->speaker_protection_bypass) + return 0; + rc = audioreach_speaker_protection_vi(graph, module, cfg); if (!rc) rc = audioreach_module_enable(graph, module, true); @@ -1438,48 +2238,10 @@ void audioreach_graph_free_buf(struct q6apm_graph *graph) } EXPORT_SYMBOL_GPL(audioreach_graph_free_buf); -int audioreach_setup_push_pull(struct q6apm_graph *graph, phys_addr_t bphys, - phys_addr_t pphys, uint32_t mem_map_handle, - uint32_t pos_buf_mem_map_handle, uint32_t size) -{ - struct param_id_sh_mem_pull_push_mode_cfg *cfg; - struct apm_module_param_data *param_data; - int payload_size; - struct gpr_pkt *pkt __free(kfree) = NULL; - void *p; - - payload_size = sizeof(*cfg) + APM_MODULE_PARAM_DATA_SIZE; - pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0); - if (IS_ERR(pkt)) - return PTR_ERR(pkt); - - p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; - - param_data = p; - param_data->module_instance_id = graph->shm_iid; - param_data->error_code = 0; - param_data->param_id = PARAM_ID_SH_MEM_PULL_PUSH_MODE_CFG; - param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE; - - p = p + APM_MODULE_PARAM_DATA_SIZE; - cfg = p; - - cfg->shared_circ_buf_addr_lsw = lower_32_bits(bphys); - cfg->shared_circ_buf_addr_msw = upper_32_bits(bphys); - cfg->shared_circ_buf_size = size; - cfg->circ_buf_mem_map_handle = mem_map_handle; - cfg->shared_pos_buf_addr_lsw = lower_32_bits(pphys); - cfg->shared_pos_buf_addr_msw = upper_32_bits(pphys); - cfg->pos_buf_mem_map_handle = pos_buf_mem_map_handle; - - return q6apm_send_cmd_sync(graph->apm, pkt, 0); -} -EXPORT_SYMBOL_GPL(audioreach_setup_push_pull); - int audioreach_shared_memory_send_eos(struct q6apm_graph *graph) { struct data_cmd_wr_sh_mem_ep_eos *eos; - int iid = graph->shm_iid; + int iid = q6apm_graph_get_rx_shmem_module_iid(graph); struct gpr_pkt *pkt __free(kfree) = audioreach_alloc_cmd_pkt(sizeof(*eos), DATA_CMD_WR_SH_MEM_EP_EOS, 0, graph->port->id, iid); if (IS_ERR(pkt)) diff --git a/sound/soc/qcom/qdsp6/audioreach.h b/sound/soc/qcom/qdsp6/audioreach.h index 62a2fd79bbcb93..27c590210cda5f 100644 --- a/sound/soc/qcom/qdsp6/audioreach.h +++ b/sound/soc/qcom/qdsp6/audioreach.h @@ -8,6 +8,7 @@ #include struct q6apm; struct q6apm_graph; +struct audioreach_graph; /* Module IDs */ #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 @@ -17,7 +18,6 @@ struct q6apm_graph; #define MODULE_ID_PCM_ENC 0x07001004 #define MODULE_ID_PCM_DEC 0x07001005 #define MODULE_ID_SH_MEM_PULL_MODE 0x07001006 -#define MODULE_ID_SH_MEM_PUSH_MODE 0x07001007 #define MODULE_ID_PLACEHOLDER_ENCODER 0x07001008 #define MODULE_ID_PLACEHOLDER_DECODER 0x07001009 #define MODULE_ID_I2S_SINK 0x0700100A @@ -62,59 +62,15 @@ struct q6apm_graph; #define APM_CMD_GET_CFG 0x01001007 #define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C #define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D -#define APM_CMD_REGISTER_MODULE_EVENTS 0x0100100E -#define APM_EVENT_MODULE_TO_CLIENT 0x03001000 #define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001 -#define APM_MMAP_TOKEN_GID_MASK GENMASK(15, 0) -#define APM_MMAP_TOKEN_MAP_TYPE_POS_BUF BIT(16) -#define APM_MMAP_TOKEN_MAP_TYPE_SHIFT 16 #define APM_CMD_RSP_GET_CFG 0x02001000 #define APM_CMD_CLOSE_ALL 0x01001013 #define APM_CMD_REGISTER_SHARED_CFG 0x0100100A -#define EVENT_ID_SH_MEM_PULL_PUSH_MODE_WATERMARK 0x0800101C - -/** - * struct event_cfg_sh_mem_pull_push_mode_watermark_t - Watermark config - * @num_water_mark_levels: Number of watermark levels. - * @level: Watermark levels. - * - * If @num_water_mark_levels is zero, no watermark levels are specified - * and watermark events are not supported. - */ -struct event_cfg_sh_mem_pull_push_mode_watermark_t { - uint32_t num_water_mark_levels; - uint32_t level[]; -} __packed; - -/** - * struct apm_module_register_events - Register or unregister module events - * @module_instance_id: Module instance identifier. - * @event_id: Module event identifier. - * @is_register: 1 to register the event, 0 to unregister it. - * @error_code: Error code for out-of-band command mode. - * @event_config_payload_size: Event configuration payload size in bytes. - * @reserved: Reserved for alignment; must be zero. - */ -struct apm_module_register_events { - uint32_t module_instance_id; - uint32_t event_id; - uint32_t is_register; - uint32_t error_code; - uint32_t event_config_payload_size; - uint32_t reserved; -} __packed; - -/** - * struct apm_module_event - Module event descriptor - * @event_id: Module event identifier. - * @event_payload_size: Event payload size in bytes. - */ -struct apm_module_event { - uint32_t event_id; - uint32_t event_payload_size; -} __packed; +#define APM_CMD_REGISTER_MODULE_EVENTS 0x0100100E +#define APM_EVENT_MODULE_TO_CLIENT 0x03001000 #define APM_MEMORY_MAP_SHMEM8_4K_POOL 3 +#define APM_MEMORY_MAP_FLAG_UNCACHED BIT(1) struct apm_cmd_shared_mem_map_regions { uint16_t mem_pool_id; @@ -136,6 +92,20 @@ struct apm_cmd_rsp_shared_mem_map_regions { uint32_t mem_map_handle; } __packed; +struct apm_module_register_events { + uint32_t module_instance_id; + uint32_t event_id; + uint32_t is_register; + uint32_t error_code; + uint32_t event_config_payload_size; + uint32_t reserved; +} __packed; + +struct apm_module_event { + uint32_t event_id; + uint32_t event_payload_size; +} __packed; + /* APM module */ #define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005 @@ -169,6 +139,8 @@ struct apm_module_conn_obj { uint32_t dst_mod_ip_port_id; } __packed; +#define APM_PARAM_ID_MODULE_CTRL_LINK_CFG 0x08001061 + #define APM_PARAM_ID_GAIN 0x08001006 struct param_id_gain_cfg { @@ -281,6 +253,33 @@ struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 { #define PARAM_ID_MEDIA_FORMAT 0x0800100C #define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001 +#define PARAM_ID_SH_MEM_PULL_PUSH_MODE_CFG 0x0800100A +#define EVENT_ID_SH_MEM_PULL_PUSH_MODE_WATERMARK 0x0800101C +#define EVENT_ID_SOFT_PAUSE_PAUSE_COMPLETE 0x0800103F +#define EVENT_ID_SOFT_PAUSE_RESUME_COMPLETE 0x08001043 + +struct sh_mem_pull_push_mode_cfg { + uint32_t shared_circ_buf_addr_lsw; + uint32_t shared_circ_buf_addr_msw; + uint32_t shared_circ_buf_size; + uint32_t circ_buf_mem_map_handle; + uint32_t shared_pos_buf_addr_lsw; + uint32_t shared_pos_buf_addr_msw; + uint32_t pos_buf_mem_map_handle; +} __packed; + +struct sh_mem_pull_push_mode_position_buffer { + uint32_t frame_counter; + uint32_t index; + uint32_t timestamp_us_lsw; + uint32_t timestamp_us_msw; +} __packed; + +struct event_cfg_sh_mem_pull_push_mode_watermark { + uint32_t num_water_mark_levels; + uint32_t watermark_level_bytes[]; +} __packed; + struct apm_media_format { uint32_t data_format; uint32_t fmt_id; @@ -759,46 +758,6 @@ struct param_id_placeholder_real_module_id { uint32_t real_module_id; } __packed; - -#define PARAM_ID_SH_MEM_PULL_PUSH_MODE_CFG 0x0800100A - -/** - * struct param_id_sh_mem_pull_push_mode_cfg - Shared memory push/pull config - * @shared_circ_buf_addr_lsw: Lower 32 bits of the circular buffer address. - * @shared_circ_buf_addr_msw: Upper 32 bits of the circular buffer address. - * @shared_circ_buf_size: Circular buffer size in bytes. - * @circ_buf_mem_map_handle: Circular buffer memory map handle. - * @shared_pos_buf_addr_lsw: Lower 32 bits of the position buffer address. - * @shared_pos_buf_addr_msw: Upper 32 bits of the position buffer address. - * @pos_buf_mem_map_handle: Position buffer memory map handle. - */ -struct param_id_sh_mem_pull_push_mode_cfg { - uint32_t shared_circ_buf_addr_lsw; - uint32_t shared_circ_buf_addr_msw; - uint32_t shared_circ_buf_size; - uint32_t circ_buf_mem_map_handle; - uint32_t shared_pos_buf_addr_lsw; - uint32_t shared_pos_buf_addr_msw; - uint32_t pos_buf_mem_map_handle; -} __packed; - -/** - * struct sh_mem_pull_push_mode_position_buffer - Shared position buffer - * @frame_counter: Synchronization counter. - * @index: Current read/write index in bytes. - * @timestamp_us_lsw: Lower 32 bits of the timestamp in microseconds. - * @timestamp_us_msw: Upper 32 bits of the timestamp in microseconds. - * - * The frame counter should be read before and after the other fields to - * ensure the DSP did not update them while they were being read. - */ -struct sh_mem_pull_push_mode_position_buffer { - uint32_t frame_counter; - uint32_t index; - uint32_t timestamp_us_lsw; - uint32_t timestamp_us_msw; -} __packed; - /* Graph */ struct audioreach_connection { /* Connections */ @@ -812,15 +771,18 @@ struct audioreach_connection { struct audioreach_graph_info { int id; uint32_t mem_map_handle; - uint32_t pos_buf_mem_map_handle; uint32_t num_sub_graphs; struct list_head sg_list; - bool is_push_pull_mode; /* DPCM connection from FE Graph to BE graph */ uint32_t src_mod_inst_id; uint32_t src_mod_op_port_id; uint32_t dst_mod_inst_id; uint32_t dst_mod_ip_port_id; + /* + * The DAPM mixer can represent an edge already described by module + * topology tokens when a frontend and backend share one graph. + */ + bool internal_vmixer_connection; }; struct audioreach_sub_graph { @@ -841,6 +803,9 @@ struct audioreach_container { uint32_t graph_pos; uint32_t stack_size; uint32_t proc_domain; + uint32_t parent_container_id; + uint32_t heap_id; + bool has_extended_properties; struct list_head node; uint32_t num_modules; @@ -887,12 +852,25 @@ struct audioreach_module { uint32_t log_code; uint32_t log_tap_point_id; uint32_t log_mode; + bool speaker_protection_bypass; + uint32_t integrated_backend_id; /* bookkeeping */ struct list_head node; struct audioreach_container *container; struct snd_soc_dapm_widget *widget; struct audioreach_module_priv_data *data; + struct audioreach_module_priv_data *ctrl_link_data; + struct audioreach_module_priv_data *graph_cal_data; + struct audioreach_module_priv_data *render_ep_data; + struct audioreach_module_priv_data *sp_tag_data; + struct audioreach_module_priv_data *spvi_tag_data; + struct audioreach_module_priv_data *vi_ep_data; + struct audioreach_module_priv_data *protection_dynamic_data; + struct audioreach_module_priv_data *volume_gain_data; + struct audioreach_module_priv_data *volume_filter_data; + struct audioreach_module_priv_data *volume_mute_data; + struct audioreach_module_priv_data *channel_mixer_data; }; struct audioreach_module_config { @@ -938,18 +916,22 @@ int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, const struct gpr_p int audioreach_set_media_format(struct q6apm_graph *graph, const struct audioreach_module *module, const struct audioreach_module_config *cfg); +int audioreach_send_protected_graph_calibration(struct audioreach_graph *graph); +bool audioreach_graph_has_protected_calibration( + const struct audioreach_graph_info *info); +int audioreach_configure_protection(struct q6apm_graph *graph); int audioreach_shared_memory_send_eos(struct q6apm_graph *graph); int audioreach_gain_set_vol_ctrl(struct q6apm *apm, const struct audioreach_module *module, int vol); +int audioreach_sp11_inject_module_param(struct q6apm *apm, u32 iid, u32 param_id, + const void *payload, size_t size); +int audioreach_sp11_set_final_volume_q28(struct q6apm *apm, u32 left_q28, + u32 right_q28); +int audioreach_sp11_set_final_mute(struct q6apm *apm, bool muted); int audioreach_send_u32_param(struct q6apm_graph *graph, const struct audioreach_module *module, uint32_t param_id, uint32_t param_val); int audioreach_compr_set_param(struct q6apm_graph *graph, const struct audioreach_module_config *mcfg); -int audioreach_setup_push_pull(struct q6apm_graph *graph, phys_addr_t bphys, - phys_addr_t pphys, uint32_t mem_map_handle, - uint32_t pos_buf_mem_map_handle, uint32_t size); -int audioreach_map_memory_position_buffer(struct q6apm_graph *graph, unsigned int dir); -int audioreach_shmem_register_event(struct q6apm_graph *graph, int bytes, int num_levels); #endif /* __AUDIOREACH_H__ */ diff --git a/sound/soc/qcom/qdsp6/q6apm-dai.c b/sound/soc/qcom/qdsp6/q6apm-dai.c index bf1f872a09f45a..1a3582dff38d20 100644 --- a/sound/soc/qcom/qdsp6/q6apm-dai.c +++ b/sound/soc/qcom/qdsp6/q6apm-dai.c @@ -14,11 +14,12 @@ #include #include #include +#include +#include #include #include "q6apm.h" #define DRV_NAME "q6apm-dai" -#define POS_BUFFER_BYTES 4096 #define PLAYBACK_MIN_NUM_PERIODS 2 #define PLAYBACK_MAX_NUM_PERIODS 8 @@ -30,6 +31,17 @@ #define CAPTURE_MIN_PERIOD_SIZE 6144 #define BUFFER_BYTES_MAX (PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE) #define BUFFER_BYTES_MIN (PLAYBACK_MIN_NUM_PERIODS * PLAYBACK_MIN_PERIOD_SIZE) +#define SP11_PULL_PERIOD_BYTES 1920 +#define SP11_PULL_BUFFER_BYTES 3840 +/* Current Windows DEFAULT 0x466b timing: 0x102d rampdown=20 ms, + * 0x103e downstream delay=25 ms, and qcadcm adds a 5 ms completion margin. + */ +#define SP11_SOFT_PAUSE_RAMPDOWN_MS 20 +#define SP11_SOFT_PAUSE_DOWNSTREAM_DELAY_MS 25 +#define SP11_SOFT_PAUSE_COMPLETION_MARGIN_MS 5 +#define SP11_SOFT_PAUSE_TIMEOUT_MS \ + (SP11_SOFT_PAUSE_RAMPDOWN_MS + SP11_SOFT_PAUSE_DOWNSTREAM_DELAY_MS + \ + SP11_SOFT_PAUSE_COMPLETION_MARGIN_MS) #define COMPR_PLAYBACK_MAX_FRAGMENT_SIZE (128 * 1024) #define COMPR_PLAYBACK_MAX_NUM_FRAGMENTS (16 * 4) #define COMPR_PLAYBACK_MIN_FRAGMENT_SIZE (8 * 1024) @@ -63,12 +75,8 @@ struct q6apm_dai_rtd { struct snd_codec codec; struct snd_compr_params codec_param; struct snd_dma_buffer dma_buffer; - struct sh_mem_pull_push_mode_position_buffer *pos_buffer; - uint32_t last_pos_index; phys_addr_t phys; - phys_addr_t pos_phys; unsigned int pcm_size; - unsigned int push_pull_size; unsigned int pcm_count; unsigned int periods; uint64_t bytes_sent; @@ -81,6 +89,9 @@ struct q6apm_dai_rtd { struct q6apm_graph *graph; spinlock_t lock; bool notify_on_drain; + bool soft_paused; + struct completion soft_pause_done; + struct completion soft_resume_done; }; struct q6apm_dai_data { @@ -127,21 +138,52 @@ static const struct snd_pcm_hardware q6apm_dai_hardware_playback = { .fifo_size = 0, }; +static const struct snd_pcm_hardware q6apm_dai_hardware_sp11_pull = { + .info = (SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME | + SNDRV_PCM_INFO_NO_REWINDS | + SNDRV_PCM_INFO_SYNC_APPLPTR | + SNDRV_PCM_INFO_BATCH), + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + .buffer_bytes_max = SP11_PULL_BUFFER_BYTES, + .period_bytes_min = SP11_PULL_PERIOD_BYTES, + .period_bytes_max = SP11_PULL_PERIOD_BYTES, + .periods_min = 2, + .periods_max = 2, + .fifo_size = 0, +}; + static void event_handler(uint32_t opcode, uint32_t token, void *payload, void *priv) { struct q6apm_dai_rtd *prtd = priv; struct snd_pcm_substream *substream = prtd->substream; switch (opcode) { - case APM_CLIENT_EVENT_WATERMARK_EVENT: - snd_pcm_period_elapsed(substream); - break; case APM_CLIENT_EVENT_CMD_EOS_DONE: prtd->state = Q6APM_STREAM_STOPPED; break; case APM_CLIENT_EVENT_DATA_WRITE_DONE: snd_pcm_period_elapsed(substream); + break; + case APM_CLIENT_EVENT_PULL_WATERMARK: + if (prtd->state == Q6APM_STREAM_RUNNING) + snd_pcm_period_elapsed(substream); + break; + case APM_CLIENT_EVENT_SOFT_PAUSE_COMPLETE: + complete(&prtd->soft_pause_done); + break; + case APM_CLIENT_EVENT_SOFT_RESUME_COMPLETE: + complete(&prtd->soft_resume_done); break; case APM_CLIENT_EVENT_DATA_READ_DONE: snd_pcm_period_elapsed(substream); @@ -230,6 +272,19 @@ static int q6apm_dai_prepare(struct snd_soc_component *component, return -EINVAL; } + /* + * The SP11 pull endpoint is configured once for the lifetime of its + * graph. ALSA may call prepare again on the same open stream, including + * after STOP. Re-sending the pull-ring parameter is rejected by the DSP + * with AR_EALREADY, while the fixed 48 kHz stereo format cannot change. + * Keep the persistent graph running and only re-arm the host-side state. + */ + if (prtd->graph->pull_mode && prtd->state != Q6APM_STREAM_IDLE) { + prtd->state = Q6APM_STREAM_RUNNING; + dev_info(dev, "SP11 stage duplicate prepare reused pull graph\n"); + return 0; + } + cfg.direction = substream->stream; cfg.sample_rate = runtime->rate; cfg.num_channels = runtime->channels; @@ -239,37 +294,22 @@ static int q6apm_dai_prepare(struct snd_soc_component *component, if (prtd->state) { /* clear the previous setup if any */ q6apm_graph_stop(prtd->graph); - q6apm_free_fragments(prtd->graph, substream->stream); + if (!prtd->graph->pull_mode) + q6apm_free_fragments(prtd->graph, substream->stream); } - prtd->last_pos_index = 0; prtd->pcm_count = snd_pcm_lib_period_bytes(substream); - if (q6apm_is_graph_in_push_pull_mode(prtd->graph)) { - if (prtd->pcm_size != prtd->push_pull_size) { - ret = q6apm_push_pull_config(prtd->graph, prtd->phys, prtd->pos_phys, - prtd->pcm_size); - if (ret < 0) { - dev_err(dev, "Push/Pull config failed rc = %d\n", ret); - return ret; - } - - ret = q6apm_register_watermark_event(prtd->graph, - prtd->pcm_size / prtd->periods, - prtd->periods); - if (ret < 0) { - dev_err(dev, "WaterMark event config failed rc = %d\n", ret); - return ret; - } - prtd->push_pull_size = prtd->pcm_size; - } - } else { - ret = q6apm_alloc_fragments(prtd->graph, substream->stream, prtd->phys, - (prtd->pcm_size / prtd->periods), prtd->periods); - if (ret < 0) { - dev_err(dev, "Audio Start: Buffer Allocation failed rc = %d\n", ret); - return ret; - } - + /* rate and channels are sent to audio driver */ + if (prtd->graph->pull_mode) + ret = q6apm_graph_configure_pull( + prtd->graph, &cfg, prtd->phys, prtd->pcm_size, + prtd->pcm_count); + else + ret = q6apm_graph_media_format_shmem(prtd->graph, &cfg); + if (ret < 0) { + dev_err(dev, "%s: shared-memory setup failed: %d\n", + __func__, ret); + return ret; } ret = q6apm_graph_media_format_pcm(prtd->graph, &cfg); @@ -278,11 +318,16 @@ static int q6apm_dai_prepare(struct snd_soc_component *component, return ret; } - /* rate and channels are sent to audio driver */ - ret = q6apm_graph_media_format_shmem(prtd->graph, &cfg); + if (!prtd->graph->pull_mode) + ret = q6apm_alloc_fragments( + prtd->graph, substream->stream, prtd->phys, + (prtd->pcm_size / prtd->periods), prtd->periods); + else + ret = 0; + if (ret < 0) { - dev_err(dev, "Failed to set media format %d\n", ret); - return ret; + dev_err(dev, "Audio Start: Buffer Allocation failed rc = %d\n", ret); + return -ENOMEM; } ret = q6apm_graph_prepare(prtd->graph); @@ -296,13 +341,13 @@ static int q6apm_dai_prepare(struct snd_soc_component *component, dev_err(dev, "Failed to Start Graph %d\n", ret); return ret; } - if (!q6apm_is_graph_in_push_pull_mode(prtd->graph)) { - if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { - int i; - /* Queue the buffers for Capture ONLY after graph is started */ - for (i = 0; i < runtime->periods; i++) - q6apm_read(prtd->graph); - } + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + int i; + /* Queue the buffers for Capture ONLY after graph is started */ + for (i = 0; i < runtime->periods; i++) + q6apm_read(prtd->graph); + } /* Now that graph as been prepared and started update the internal state accordingly */ @@ -317,10 +362,9 @@ static int q6apm_dai_ack(struct snd_soc_component *component, struct snd_pcm_sub struct q6apm_dai_rtd *prtd = runtime->private_data; int i, ret = 0, avail_periods; - if (q6apm_is_graph_in_push_pull_mode(prtd->graph)) - return 0; - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (prtd->graph->pull_mode) + return 0; avail_periods = (runtime->control->appl_ptr - prtd->queue_ptr)/runtime->period_size; for (i = 0; i < avail_periods; i++) { ret = q6apm_write_async(prtd->graph, prtd->pcm_count, 0, 0, NO_TIMESTAMP); @@ -335,6 +379,52 @@ static int q6apm_dai_ack(struct snd_soc_component *component, struct snd_pcm_sub return ret; } +static int q6apm_dai_sp11_soft_pause(struct snd_soc_component *component, + struct q6apm_dai_rtd *prtd, + bool pause) +{ + struct completion *done = pause ? &prtd->soft_pause_done : + &prtd->soft_resume_done; + unsigned long timeout; + int ret; + + if (!prtd->graph->pull_mode) + return -EOPNOTSUPP; + + /* + * ALSA calls trigger() with the PCM stream lock held. A pull watermark + * delivered while that lock is held must not call snd_pcm_period_elapsed() + * ahead of the SOFT_PAUSE completion event on the same GPR receive path, + * or completion delivery is blocked behind the trigger waiter. Windows + * likewise enters PAUSE/state 3 before it sends the value-1 TKV. + */ + if (pause) + prtd->state = Q6APM_STREAM_STOPPED; + + reinit_completion(done); + ret = q6apm_graph_sp11_soft_pause(prtd->graph, pause); + if (ret) { + if (pause) + prtd->state = Q6APM_STREAM_RUNNING; + return ret; + } + + /* The DSP accepted the command. Track requested state even if its + * completion event is delayed/lost so STOP can safely clean up a + * possibly outstanding pause. + */ + prtd->soft_paused = pause; + + timeout = wait_for_completion_timeout(done, msecs_to_jiffies(SP11_SOFT_PAUSE_TIMEOUT_MS)); + if (!timeout) { + dev_err(component->dev, "SP11 soft-%s completion timed out\n", + pause ? "pause" : "resume"); + return -ETIMEDOUT; + } + + return 0; +} + static int q6apm_dai_trigger(struct snd_soc_component *component, struct snd_pcm_substream *substream, int cmd) { @@ -344,17 +434,51 @@ static int q6apm_dai_trigger(struct snd_soc_component *component, switch (cmd) { case SNDRV_PCM_TRIGGER_START: + break; case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK || + !prtd->graph->pull_mode || !prtd->soft_paused) + break; + ret = q6apm_dai_sp11_soft_pause(component, prtd, false); + if (ret == -EOPNOTSUPP) { + ret = 0; + } else if (!ret) { + prtd->soft_paused = false; + prtd->state = Q6APM_STREAM_RUNNING; + } break; case SNDRV_PCM_TRIGGER_STOP: - /* TODO support be handled via SoftPause Module */ + /* + * ALSA STOP is an intermediate host lifecycle transition for this + * persistent pull graph, not the Windows graph teardown boundary. + * If a Windows PAUSE is outstanding, release it exactly before the + * host reprepare; q6apm_dai_close() retains the real graph STOP. + */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && + prtd->graph->pull_mode && prtd->soft_paused) { + ret = q6apm_dai_sp11_soft_pause(component, prtd, false); + if (ret == -EOPNOTSUPP) + ret = 0; + else if (!ret) + prtd->soft_paused = false; + } prtd->state = Q6APM_STREAM_STOPPED; prtd->queue_ptr = 0; - prtd->last_pos_index = 0; break; case SNDRV_PCM_TRIGGER_SUSPEND: + break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK || + !prtd->graph->pull_mode || prtd->soft_paused) + break; + ret = q6apm_dai_sp11_soft_pause(component, prtd, true); + if (ret == -EOPNOTSUPP) { + ret = 0; + } else if (!ret) { + prtd->soft_paused = true; + prtd->state = Q6APM_STREAM_STOPPED; + } break; default: ret = -EINVAL; @@ -388,6 +512,8 @@ static int q6apm_dai_open(struct snd_soc_component *component, return -ENOMEM; spin_lock_init(&prtd->lock); + init_completion(&prtd->soft_pause_done); + init_completion(&prtd->soft_resume_done); prtd->substream = substream; prtd->graph = q6apm_graph_open(dev, event_handler, prtd, graph_id, substream->stream); if (IS_ERR(prtd->graph)) { @@ -396,8 +522,12 @@ static int q6apm_dai_open(struct snd_soc_component *component, goto err; } - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - runtime->hw = q6apm_dai_hardware_playback; + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (prtd->graph->pull_mode) + runtime->hw = q6apm_dai_hardware_sp11_pull; + else + runtime->hw = q6apm_dai_hardware_playback; + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) runtime->hw = q6apm_dai_hardware_capture; @@ -408,7 +538,8 @@ static int q6apm_dai_open(struct snd_soc_component *component, goto err; } - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && + !prtd->graph->pull_mode) { ret = snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, BUFFER_BYTES_MIN, BUFFER_BYTES_MAX); if (ret < 0) { @@ -431,20 +562,13 @@ static int q6apm_dai_open(struct snd_soc_component *component, } runtime->private_data = prtd; - runtime->dma_bytes = BUFFER_BYTES_MAX; + runtime->dma_bytes = prtd->graph->pull_mode ? + PAGE_SIZE : BUFFER_BYTES_MAX; if (pdata->sid < 0) prtd->phys = substream->dma_buffer.addr; else prtd->phys = substream->dma_buffer.addr | (pdata->sid << 32); - if (q6apm_is_graph_in_push_pull_mode(prtd->graph)) { - void *pos_buffer; - - prtd->pos_phys = prtd->phys + BUFFER_BYTES_MAX; - pos_buffer = (void *)(substream->dma_buffer.area + BUFFER_BYTES_MAX); - prtd->pos_buffer = (struct sh_mem_pull_push_mode_position_buffer *)(pos_buffer); - } - return 0; err: kfree(prtd); @@ -461,7 +585,8 @@ static int q6apm_dai_close(struct snd_soc_component *component, if (prtd->state) { /* only stop graph that is started */ q6apm_graph_stop(prtd->graph); - q6apm_free_fragments(prtd->graph, substream->stream); + if (!prtd->graph->pull_mode) + q6apm_free_fragments(prtd->graph, substream->stream); } q6apm_graph_close(prtd->graph); @@ -479,25 +604,9 @@ static snd_pcm_uframes_t q6apm_dai_pointer(struct snd_soc_component *component, struct q6apm_dai_rtd *prtd = runtime->private_data; snd_pcm_uframes_t ptr; - if (q6apm_is_graph_in_push_pull_mode(prtd->graph)) { - int retries = 10; - uint32_t index, fc1, fc2; - - /* index is valid if frame_counter does not change while reading. */ - do { - fc1 = READ_ONCE(prtd->pos_buffer->frame_counter); - index = READ_ONCE(prtd->pos_buffer->index); - fc2 = READ_ONCE(prtd->pos_buffer->frame_counter); - } while (fc1 != fc2 && --retries); + if (prtd->graph->pull_mode) + return q6apm_get_pull_hw_pointer(prtd->graph, runtime); - if (fc1 != fc2) - index = prtd->last_pos_index; - else - prtd->last_pos_index = index; - - ptr = bytes_to_frames(runtime, index); - return ptr; - } ptr = q6apm_get_hw_pointer(prtd->graph, substream->stream) * runtime->period_size; if (ptr) return ptr - 1; @@ -530,11 +639,11 @@ static int q6apm_dai_hw_params(struct snd_soc_component *component, } static int q6apm_dai_memory_map(struct snd_soc_component *component, - struct snd_pcm_substream *substream, - int graph_id, bool is_push_pull) + struct snd_pcm_substream *substream, int graph_id) { struct q6apm_dai_data *pdata; struct device *dev = component->dev; + size_t map_size; phys_addr_t phys; int ret; @@ -549,23 +658,12 @@ static int q6apm_dai_memory_map(struct snd_soc_component *component, else phys = substream->dma_buffer.addr | (pdata->sid << 32); - ret = q6apm_map_memory_fixed_region(dev, graph_id, phys, BUFFER_BYTES_MAX); + map_size = q6apm_graph_is_pull_mode(dev, graph_id) ? + PAGE_SIZE : BUFFER_BYTES_MAX; + ret = q6apm_map_memory_fixed_region(dev, graph_id, phys, map_size); if (ret < 0) dev_err(dev, "Audio Start: Buffer Allocation failed rc = %d\n", ret); - if (is_push_pull) { - if (pdata->sid < 0) - phys = substream->dma_buffer.addr + BUFFER_BYTES_MAX; - else - phys = (substream->dma_buffer.addr + BUFFER_BYTES_MAX) | (pdata->sid << 32); - - ret = q6apm_map_pos_buffer(dev, graph_id, phys, POS_BUFFER_BYTES); - if (ret < 0) - dev_err(dev, "Audio Start: Buffer Allocation failed rc = %d\n", ret); - } else { - - } - return ret; } @@ -578,32 +676,29 @@ static int q6apm_dai_pcm_new(struct snd_soc_component *component, struct snd_soc * address arithmetic can overflow when the buffer is placed near the * end of the addressable range. */ - int size = BUFFER_BYTES_MAX + PAGE_SIZE; + int size; int graph_id, ret; - bool is_push_pull; - struct snd_pcm_substream *substream = NULL; + struct snd_pcm_substream *substream; graph_id = cpu_dai->driver->id; + size = (q6apm_graph_is_pull_mode(component->dev, graph_id) ? + PAGE_SIZE : BUFFER_BYTES_MAX) + PAGE_SIZE; + + ret = snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, component->dev, size); + if (ret) + return ret; /* Note: DSP backend dais are uni-directional ONLY(either playback or capture) */ - if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) + if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; - else if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) - substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; - - - if (substream) { - is_push_pull = q6apm_is_graph_in_push_pull_mode_from_id(component->dev, - graph_id, - substream->stream); - if (is_push_pull) - size += POS_BUFFER_BYTES; - - ret = snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, component->dev, size); + ret = q6apm_dai_memory_map(component, substream, graph_id); if (ret) return ret; + } - ret = q6apm_dai_memory_map(component, substream, graph_id, is_push_pull); + if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { + substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; + ret = q6apm_dai_memory_map(component, substream, graph_id); if (ret) return ret; } @@ -628,9 +723,6 @@ static void q6apm_dai_memory_unmap(struct snd_soc_component *component, graph_id = cpu_dai->driver->id; q6apm_unmap_memory_fixed_region(component->dev, graph_id); - - if (q6apm_is_graph_in_push_pull_mode_from_id(component->dev, graph_id, substream->stream)) - q6apm_unmap_pos_buffer(component->dev, graph_id); } static void q6apm_dai_pcm_free(struct snd_soc_component *component, struct snd_pcm *pcm) diff --git a/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c b/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c index 006b283484d9e9..c9dbcbda9f6ee3 100644 --- a/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c +++ b/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c @@ -189,9 +189,12 @@ static int q6apm_lpass_dai_prepare(struct snd_pcm_substream *substream, struct s struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); struct audioreach_module_config *cfg = &dai_data->module_config[dai->id]; struct q6apm_graph *graph; - int graph_id = dai->id; + int graph_id = q6apm_graph_id_for_backend(dai->dev, dai->id); int rc; + if (graph_id < 0) + return graph_id; + if (dai_data->is_port_started[dai->id]) { q6apm_graph_stop(dai_data->graph[dai->id]); dai_data->is_port_started[dai->id] = false; @@ -209,7 +212,21 @@ static int q6apm_lpass_dai_prepare(struct snd_pcm_substream *substream, struct s rc = PTR_ERR(graph); return rc; } - dai_data->graph[graph_id] = graph; + dai_data->graph[dai->id] = graph; + } + + /* + * The integrated SP11 pull graph has one Windows-ordered configuration + * owner: its frontend. Generic backend prepare runs first in the DPCM + * sequence, before the pull ring and event registrations exist. Sending + * PCM/MFC/protection configuration here therefore changes the captured + * order and is rejected by the DSP. The frontend configures the same + * shared graph completely before start. + */ + if (dai_data->graph[dai->id]->pull_mode) { + dev_info_once(dai->dev, + "SP11 pull graph: backend configuration deferred to frontend\n"); + return 0; } cfg->direction = substream->stream; @@ -237,7 +254,10 @@ static int q6apm_lpass_dai_startup(struct snd_pcm_substream *substream, struct s { struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6apm_graph *graph; - int graph_id = dai->id; + int graph_id = q6apm_graph_id_for_backend(dai->dev, dai->id); + + if (graph_id < 0) + return graph_id; if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { graph = q6apm_graph_open(dai->dev, NULL, dai->dev, graph_id, substream->stream); @@ -245,7 +265,7 @@ static int q6apm_lpass_dai_startup(struct snd_pcm_substream *substream, struct s dev_err(dai->dev, "Failed to open graph (%d)\n", graph_id); return PTR_ERR(graph); } - dai_data->graph[graph_id] = graph; + dai_data->graph[dai->id] = graph; } return 0; diff --git a/sound/soc/qcom/qdsp6/q6apm.c b/sound/soc/qcom/qdsp6/q6apm.c index 641d6d24322990..b8b9a1472ed8c0 100644 --- a/sound/soc/qcom/qdsp6/q6apm.c +++ b/sound/soc/qcom/qdsp6/q6apm.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,17 @@ #include "q6apm.h" /* Graph Management */ +#define Q6APM_OOB_MAP_TOKEN BIT(31) +#define Q6APM_POSITION_MAP_TOKEN BIT(30) +#define Q6APM_OOB_BUFFER_SIZE SZ_16K +#define Q6APM_DSP_SID_MASK GENMASK(3, 0) + +/* Windows DEFAULT speaker SOFT_PAUSE lifecycle, evidence-locked on SP11. */ +#define SP11_MODULE_ID_SOFT_PAUSE 0x07001019 +#define SP11_SOFT_PAUSE_IID 0x0000466b +#define SP11_PARAM_SOFT_PAUSE_PAUSE 0x0800102e +#define SP11_PARAM_SOFT_PAUSE_RESUME 0x0800102f + struct apm_graph_mgmt_cmd { struct apm_module_param_data param_data; uint32_t num_sub_graphs; @@ -28,6 +40,53 @@ struct apm_graph_mgmt_cmd { #define APM_GRAPH_MGMT_PSIZE(p, n) ALIGN(struct_size(p, sub_graph_id_list, n), 8) static struct q6apm *g_apm; +static bool sp11_vi_ready; +static bool sp11_cps_ready; + +void q6apm_sp11_set_vi_ready(bool ready) +{ + WRITE_ONCE(sp11_vi_ready, ready); +} +EXPORT_SYMBOL_GPL(q6apm_sp11_set_vi_ready); + +bool q6apm_sp11_vi_ready(void) +{ + return READ_ONCE(sp11_vi_ready); +} +EXPORT_SYMBOL_GPL(q6apm_sp11_vi_ready); + +void q6apm_sp11_set_cps_ready(bool ready) +{ + WRITE_ONCE(sp11_cps_ready, ready); +} +EXPORT_SYMBOL_GPL(q6apm_sp11_set_cps_ready); + +bool q6apm_sp11_cps_ready(void) +{ + return READ_ONCE(sp11_cps_ready); +} +EXPORT_SYMBOL_GPL(q6apm_sp11_cps_ready); + +static int audioreach_graph_mgmt_cmd(struct audioreach_graph *graph, + uint32_t opcode); +static int audioreach_graph_client_mgmt_cmd(struct q6apm_graph *graph, + uint32_t opcode); + +static phys_addr_t q6apm_dsp_addr(struct device *dev, dma_addr_t dma_addr) +{ + struct of_phandle_args args; + phys_addr_t dsp_addr = dma_addr; + + if (!dev->of_node || + of_parse_phandle_with_fixed_args(dev->of_node, "iommus", 1, 0, + &args)) + return dsp_addr; + + dsp_addr |= (phys_addr_t)(args.args[0] & Q6APM_DSP_SID_MASK) << 32; + of_node_put(args.np); + + return dsp_addr; +} int q6apm_send_cmd_sync(struct q6apm *apm, const struct gpr_pkt *pkt, uint32_t rsp_opcode) @@ -38,7 +97,271 @@ int q6apm_send_cmd_sync(struct q6apm *apm, const struct gpr_pkt *pkt, NULL, &apm->wait, pkt, rsp_opcode); } -static struct audioreach_graph *q6apm_get_audioreach_graph(struct q6apm *apm, uint32_t graph_id) +static int q6apm_map_oob_buffer(struct audioreach_graph *graph) +{ + struct apm_shared_map_region_payload *region; + struct apm_cmd_shared_mem_map_regions *cmd; + struct q6apm *apm = graph->apm; + u32 token = Q6APM_OOB_MAP_TOKEN | graph->id; + int payload_size = sizeof(*cmd) + sizeof(*region); + void *p; + + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_apm_cmd_pkt(payload_size, + APM_CMD_SHARED_MEM_MAP_REGIONS, + token); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + graph->oob_size = Q6APM_OOB_BUFFER_SIZE; + graph->oob_virt = dma_alloc_coherent(graph->dma_dev, graph->oob_size, + &graph->oob_phys, GFP_KERNEL); + if (!graph->oob_virt) + return -ENOMEM; + graph->oob_dsp_addr = q6apm_dsp_addr(graph->dma_dev, graph->oob_phys); + + p = (u8 *)pkt + GPR_HDR_SIZE; + cmd = p; + cmd->mem_pool_id = APM_MEMORY_MAP_SHMEM8_4K_POOL; + cmd->num_regions = 1; + cmd->property_flag = 0; + region = p + sizeof(*cmd); + region->shm_addr_lsw = lower_32_bits(graph->oob_dsp_addr); + region->shm_addr_msw = upper_32_bits(graph->oob_dsp_addr); + region->mem_size_bytes = graph->oob_size; + + int ret = q6apm_send_cmd_sync(apm, pkt, + APM_CMD_RSP_SHARED_MEM_MAP_REGIONS); + if (ret) { + dma_free_coherent(graph->dma_dev, graph->oob_size, + graph->oob_virt, graph->oob_phys); + graph->oob_virt = NULL; + graph->oob_phys = 0; + graph->oob_dsp_addr = 0; + graph->oob_size = 0; + } else { + dev_info(graph->dma_dev, + "protection OOB map DMA %pad DSP %pap handle %#x\n", + &graph->oob_phys, &graph->oob_dsp_addr, + graph->oob_mem_map_handle); + } + return ret; +} + +static int q6apm_map_position_buffer(struct audioreach_graph *graph) +{ + struct apm_shared_map_region_payload *region; + struct apm_cmd_shared_mem_map_regions *cmd; + u32 token = Q6APM_POSITION_MAP_TOKEN | graph->id; + int payload_size = sizeof(*cmd) + sizeof(*region); + void *p; + int ret; + + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_apm_cmd_pkt(payload_size, + APM_CMD_SHARED_MEM_MAP_REGIONS, + token); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + graph->position_size = PAGE_SIZE; + graph->position_virt = + dma_alloc_coherent(graph->dma_dev, graph->position_size, + &graph->position_phys, GFP_KERNEL); + if (!graph->position_virt) + return -ENOMEM; + memset(graph->position_virt, 0, graph->position_size); + graph->position_dsp_addr = + q6apm_dsp_addr(graph->dma_dev, graph->position_phys); + + p = (u8 *)pkt + GPR_HDR_SIZE; + cmd = p; + cmd->mem_pool_id = APM_MEMORY_MAP_SHMEM8_4K_POOL; + cmd->num_regions = 1; + /* + * The pull-mode position structure is shared live between the DSP and + * HLOS. AudioReach updates it without cache maintenance and therefore + * requires this mapping to be uncached. + */ + cmd->property_flag = APM_MEMORY_MAP_FLAG_UNCACHED; + region = p + sizeof(*cmd); + region->shm_addr_lsw = lower_32_bits(graph->position_dsp_addr); + region->shm_addr_msw = upper_32_bits(graph->position_dsp_addr); + region->mem_size_bytes = graph->position_size; + + ret = q6apm_send_cmd_sync(graph->apm, pkt, + APM_CMD_RSP_SHARED_MEM_MAP_REGIONS); + if (ret) { + dma_free_coherent(graph->dma_dev, graph->position_size, + graph->position_virt, graph->position_phys); + graph->position_virt = NULL; + graph->position_phys = 0; + graph->position_dsp_addr = 0; + graph->position_size = 0; + return ret; + } + + dev_info(graph->dma_dev, + "pull position map DMA %pad DSP %pap handle %#x\n", + &graph->position_phys, &graph->position_dsp_addr, + graph->position_mem_map_handle); + return 0; +} + +static int q6apm_unmap_position_buffer(struct audioreach_graph *graph) +{ + struct apm_cmd_shared_mem_unmap_regions *cmd; + u32 token = Q6APM_POSITION_MAP_TOKEN | graph->id; + int ret = 0; + + if (graph->position_mem_map_handle) { + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_apm_cmd_pkt( + sizeof(*cmd), + APM_CMD_SHARED_MEM_UNMAP_REGIONS, token); + + if (IS_ERR(pkt)) { + ret = PTR_ERR(pkt); + } else { + cmd = (void *)pkt + GPR_HDR_SIZE; + cmd->mem_map_handle = graph->position_mem_map_handle; + ret = q6apm_send_cmd_sync( + graph->apm, pkt, + APM_CMD_SHARED_MEM_UNMAP_REGIONS); + } + } + + if (graph->position_virt) { + dma_free_coherent(graph->dma_dev, graph->position_size, + graph->position_virt, graph->position_phys); + graph->position_virt = NULL; + graph->position_phys = 0; + graph->position_dsp_addr = 0; + graph->position_size = 0; + } + return ret; +} + +static int q6apm_unmap_oob_buffer(struct audioreach_graph *graph) +{ + struct q6apm *apm = graph->apm; + u32 token = Q6APM_OOB_MAP_TOKEN | graph->id; + struct apm_cmd_shared_mem_unmap_regions *cmd; + int ret = 0; + + if (graph->oob_mem_map_handle) { + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_apm_cmd_pkt( + sizeof(*cmd), + APM_CMD_SHARED_MEM_UNMAP_REGIONS, token); + + if (IS_ERR(pkt)) { + ret = PTR_ERR(pkt); + } else { + cmd = (void *)pkt + GPR_HDR_SIZE; + cmd->mem_map_handle = graph->oob_mem_map_handle; + ret = q6apm_send_cmd_sync( + apm, pkt, APM_CMD_SHARED_MEM_UNMAP_REGIONS); + } + } + + if (graph->oob_virt) { + dma_free_coherent(graph->dma_dev, graph->oob_size, + graph->oob_virt, graph->oob_phys); + graph->oob_virt = NULL; + graph->oob_phys = 0; + graph->oob_dsp_addr = 0; + graph->oob_size = 0; + } + return ret; +} + +int q6apm_send_oob_config(struct audioreach_graph *graph, + const void *data, size_t size) +{ + struct apm_cmd_header *cmd; + int ret; + + if (!graph->oob_virt || !graph->oob_mem_map_handle || + !size || size > graph->oob_size) + return -EINVAL; + + memset(graph->oob_virt, 0, graph->oob_size); + memcpy(graph->oob_virt, data, size); + dma_wmb(); + + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_apm_cmd_pkt(0, APM_CMD_SET_CFG, 0); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + cmd = (void *)pkt + GPR_HDR_SIZE; + cmd->payload_address_lsw = lower_32_bits(graph->oob_dsp_addr); + cmd->payload_address_msw = upper_32_bits(graph->oob_dsp_addr); + cmd->mem_map_handle = graph->oob_mem_map_handle; + cmd->payload_size = size; + ret = q6apm_send_cmd_sync(graph->apm, pkt, 0); + return ret; +} +EXPORT_SYMBOL_GPL(q6apm_send_oob_config); + +int q6apm_send_graph_oob_config(struct q6apm_graph *graph, + const void *data, size_t size) +{ + struct audioreach_graph *ar_graph = graph->ar_graph; + struct apm_cmd_header *cmd; + + if (!ar_graph || !ar_graph->oob_virt || + !ar_graph->oob_mem_map_handle || !size || + size > ar_graph->oob_size) + return -EINVAL; + + memset(ar_graph->oob_virt, 0, ar_graph->oob_size); + memcpy(ar_graph->oob_virt, data, size); + dma_wmb(); + + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_cmd_pkt(0, APM_CMD_SET_CFG, 0, + graph->port->id, + APM_MODULE_INSTANCE_ID); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + cmd = (void *)pkt + GPR_HDR_SIZE; + cmd->payload_address_lsw = + lower_32_bits(ar_graph->oob_dsp_addr); + cmd->payload_address_msw = + upper_32_bits(ar_graph->oob_dsp_addr); + cmd->mem_map_handle = ar_graph->oob_mem_map_handle; + cmd->payload_size = size; + + return audioreach_graph_send_cmd_sync(graph, pkt, 0); +} +EXPORT_SYMBOL_GPL(q6apm_send_graph_oob_config); + +int q6apm_send_inband_config(struct audioreach_graph *graph, + const void *data, size_t size) +{ + void *payload; + + if (!data || !size) + return -EINVAL; + + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_apm_cmd_pkt(size, APM_CMD_SET_CFG, 0); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + payload = (u8 *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + memcpy(payload, data, size); + + return q6apm_send_cmd_sync(graph->apm, pkt, 0); +} +EXPORT_SYMBOL_GPL(q6apm_send_inband_config); + +static struct audioreach_graph * +q6apm_get_audioreach_graph(struct q6apm *apm, struct device *dma_dev, + uint32_t graph_id) { struct audioreach_graph_info *info; struct audioreach_graph *graph; @@ -65,6 +388,8 @@ static struct audioreach_graph *q6apm_get_audioreach_graph(struct q6apm *apm, ui graph->apm = apm; graph->info = info; graph->id = graph_id; + graph->dma_dev = dma_dev; + mutex_init(&graph->protection_lock); graph->graph = audioreach_alloc_graph_pkt(apm, info); if (IS_ERR(graph->graph)) { @@ -87,9 +412,39 @@ static struct audioreach_graph *q6apm_get_audioreach_graph(struct q6apm *apm, ui kref_init(&graph->refcount); - q6apm_send_cmd_sync(apm, graph->graph, 0); + if (audioreach_graph_has_protected_calibration(info)) { + id = q6apm_map_position_buffer(graph); + if (id) + goto remove_graph; + } + + id = q6apm_send_cmd_sync(apm, graph->graph, 0); + if (id) + goto unmap_position; + if (audioreach_graph_has_protected_calibration(info)) { + id = q6apm_map_oob_buffer(graph); + if (id) + goto close_graph; + id = audioreach_send_protected_graph_calibration(graph); + if (id) + goto unmap_oob; + } return graph; + +unmap_oob: + q6apm_unmap_oob_buffer(graph); +close_graph: + audioreach_graph_mgmt_cmd(graph, APM_CMD_GRAPH_CLOSE); +unmap_position: + q6apm_unmap_position_buffer(graph); +remove_graph: + mutex_lock(&apm->lock); + idr_remove(&apm->graph_idr, graph->id); + mutex_unlock(&apm->lock); + kfree(graph->graph); + kfree(graph); + return ERR_PTR(id); } static int audioreach_graph_mgmt_cmd(struct audioreach_graph *graph, uint32_t opcode) @@ -121,6 +476,65 @@ static int audioreach_graph_mgmt_cmd(struct audioreach_graph *graph, uint32_t op return q6apm_send_cmd_sync(apm, pkt, 0); } +/* + * The SP11 Windows transaction addresses run-state commands through the + * graph's client port and lists the render graph before its two protection + * subgraphs. Keep this separate from the generic APM management path used + * by existing AudioReach topologies. + */ +static int audioreach_graph_client_mgmt_cmd(struct q6apm_graph *graph, + uint32_t opcode) +{ + static const u32 sp11_sub_graph_order[] = { + 0xb0000001, 0xb000007f, 0xb000007e, + }; + struct audioreach_graph_info *info = graph->info; + struct apm_module_param_data *param_data; + struct apm_graph_mgmt_cmd *mgmt_cmd; + struct audioreach_sub_graph *sg; + int payload_size; + int i; + + if (!graph->pull_mode) + return audioreach_graph_mgmt_cmd(graph->ar_graph, opcode); + + if (info->num_sub_graphs != ARRAY_SIZE(sp11_sub_graph_order)) + return -EINVAL; + + payload_size = APM_GRAPH_MGMT_PSIZE(mgmt_cmd, + ARRAY_SIZE(sp11_sub_graph_order)); + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_cmd_pkt(payload_size, opcode, 0, + graph->port->id, + APM_MODULE_INSTANCE_ID); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + mgmt_cmd = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + mgmt_cmd->num_sub_graphs = ARRAY_SIZE(sp11_sub_graph_order); + + param_data = &mgmt_cmd->param_data; + param_data->module_instance_id = APM_MODULE_INSTANCE_ID; + param_data->param_id = APM_PARAM_ID_SUB_GRAPH_LIST; + param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE; + + for (i = 0; i < ARRAY_SIZE(sp11_sub_graph_order); i++) { + bool found = false; + + list_for_each_entry(sg, &info->sg_list, node) { + if (sg->sub_graph_id != sp11_sub_graph_order[i]) + continue; + mgmt_cmd->sub_graph_id_list[i] = sg->sub_graph_id; + found = true; + break; + } + if (!found) + return -ENODEV; + } + + return audioreach_graph_send_cmd_sync(graph, pkt, 0); +} + static void q6apm_put_audioreach_graph(struct kref *ref) { struct audioreach_graph *graph; @@ -129,7 +543,9 @@ static void q6apm_put_audioreach_graph(struct kref *ref) graph = container_of(ref, struct audioreach_graph, refcount); apm = graph->apm; + q6apm_unmap_oob_buffer(graph); audioreach_graph_mgmt_cmd(graph, APM_CMD_GRAPH_CLOSE); + q6apm_unmap_position_buffer(graph); mutex_lock(&apm->lock); graph = idr_remove(&apm->graph_idr, graph->id); @@ -181,32 +597,193 @@ static struct audioreach_module *__q6apm_find_module_by_mid(struct q6apm *apm, return NULL; } +static struct audioreach_module * +__q6apm_find_module_by_iid(struct audioreach_graph_info *info, uint32_t iid) +{ + struct audioreach_container *container; + struct audioreach_sub_graph *sg; + struct audioreach_module *module; + + list_for_each_entry(sg, &info->sg_list, node) + list_for_each_entry(container, &sg->container_list, node) + list_for_each_entry(module, &container->modules_list, node) + if (iid == module->instance_id) + return module; + + return NULL; +} + +bool q6apm_graph_is_pull_mode(struct device *dev, unsigned int graph_id) +{ + struct q6apm *apm = dev_get_drvdata(dev->parent); + struct audioreach_graph_info *info; + + if (!apm) + return false; + + info = idr_find(&apm->graph_info_idr, graph_id); + if (!info) + return false; + + return __q6apm_find_module_by_mid(apm, info, + MODULE_ID_SH_MEM_PULL_MODE) != NULL; +} +EXPORT_SYMBOL_GPL(q6apm_graph_is_pull_mode); + int q6apm_graph_media_format_shmem(struct q6apm_graph *graph, struct audioreach_module_config *cfg) { struct audioreach_module *module; - if (cfg->direction == SNDRV_PCM_STREAM_CAPTURE) { - module = q6apm_find_module_by_mid(graph, MODULE_ID_SH_MEM_PUSH_MODE); - if (!module) - module = q6apm_find_module_by_mid(graph, MODULE_ID_RD_SHARED_MEM_EP); - } else { - module = q6apm_find_module_by_mid(graph, MODULE_ID_SH_MEM_PULL_MODE); - if (!module) - module = q6apm_find_module_by_mid(graph, MODULE_ID_WR_SHARED_MEM_EP); - } + if (cfg->direction == SNDRV_PCM_STREAM_CAPTURE) + module = q6apm_find_module_by_mid(graph, MODULE_ID_RD_SHARED_MEM_EP); + else if (audioreach_graph_has_protected_calibration(graph->info)) + module = q6apm_find_module_by_mid( + graph, MODULE_ID_SH_MEM_PULL_MODE); + else + module = q6apm_find_module_by_mid(graph, MODULE_ID_WR_SHARED_MEM_EP); - if (!module) { - dev_err(graph->dev, "No SHMEM module found in graph\n"); + if (!module) return -ENODEV; - } return audioreach_set_media_format(graph, module, cfg); + } EXPORT_SYMBOL_GPL(q6apm_graph_media_format_shmem); -static int __q6apm_map_memory_fixed_region(struct device *dev, unsigned int graph_id, - phys_addr_t phys, size_t sz, bool is_pos_buf) +static int q6apm_register_module_event(struct q6apm_graph *graph, u32 iid, + u32 event_id, const void *config, + size_t config_size) +{ + struct apm_module_register_events *event; + size_t payload_size = ALIGN(sizeof(*event) + config_size, 8); + void *p; + + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_cmd_pkt(payload_size, + APM_CMD_REGISTER_MODULE_EVENTS, 0, + graph->port->id, iid); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + p = (u8 *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + memset(p, 0, payload_size); + event = p; + event->module_instance_id = iid; + event->event_id = event_id; + event->is_register = 1; + event->event_config_payload_size = config_size; + if (config_size) + memcpy(event + 1, config, config_size); + + return audioreach_graph_send_cmd_sync(graph, pkt, 0); +} + +int q6apm_graph_configure_pull(struct q6apm_graph *graph, + struct audioreach_module_config *media_cfg, + phys_addr_t ring_addr, size_t ring_size, + size_t period_size) +{ + struct sh_mem_pull_push_mode_cfg *cfg; + struct apm_module_param_data *param; + struct audioreach_module *pull, *pause; + struct { + u32 num_water_mark_levels; + u32 levels[2]; + } __packed watermarks; + size_t payload_size; + void *p; + int ret; + + if (!graph->pull_mode || !graph->ar_graph || + !graph->ar_graph->position_virt || + !graph->ar_graph->position_mem_map_handle || + !graph->info->mem_map_handle) + return -ENODEV; + if (ring_size != 3840 || period_size != 1920 || + media_cfg->sample_rate != 48000 || media_cfg->bit_width != 16 || + media_cfg->num_channels != 2) + return -EINVAL; + + pull = __q6apm_find_module_by_iid(graph->info, 0x4660); + pause = __q6apm_find_module_by_iid(graph->info, 0x466b); + if (!pull || pull->module_id != MODULE_ID_SH_MEM_PULL_MODE || + !pause) + return -ENODEV; + + payload_size = ALIGN(APM_MODULE_PARAM_DATA_SIZE + sizeof(*cfg), 8); + struct gpr_pkt *pkt __free(kfree) = + audioreach_alloc_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0, + graph->port->id, pull->instance_id); + if (IS_ERR(pkt)) + return PTR_ERR(pkt); + + p = (u8 *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + memset(p, 0, payload_size); + param = p; + param->module_instance_id = pull->instance_id; + param->param_id = PARAM_ID_SH_MEM_PULL_PUSH_MODE_CFG; + param->param_size = sizeof(*cfg); + cfg = p + APM_MODULE_PARAM_DATA_SIZE; + cfg->shared_circ_buf_addr_lsw = lower_32_bits(ring_addr); + cfg->shared_circ_buf_addr_msw = upper_32_bits(ring_addr); + cfg->shared_circ_buf_size = ring_size; + cfg->circ_buf_mem_map_handle = graph->info->mem_map_handle; + cfg->shared_pos_buf_addr_lsw = + lower_32_bits(graph->ar_graph->position_dsp_addr); + cfg->shared_pos_buf_addr_msw = + upper_32_bits(graph->ar_graph->position_dsp_addr); + cfg->pos_buf_mem_map_handle = + graph->ar_graph->position_mem_map_handle; + + ret = audioreach_graph_send_cmd_sync(graph, pkt, 0); + if (ret) { + dev_err(graph->dev, + "SP11 stage pull-ring-config iid %#x param %#x failed: %d\n", + pull->instance_id, PARAM_ID_SH_MEM_PULL_PUSH_MODE_CFG, + ret); + return ret; + } + dev_info(graph->dev, + "SP11 stage pull-ring-config accepted: ring=%zu period=%zu\n", + ring_size, period_size); + + watermarks.num_water_mark_levels = 2; + watermarks.levels[0] = period_size; + watermarks.levels[1] = ring_size; + ret = q6apm_register_module_event( + graph, pull->instance_id, + EVENT_ID_SH_MEM_PULL_PUSH_MODE_WATERMARK, + &watermarks, sizeof(watermarks)); + if (ret) + return ret; + ret = q6apm_register_module_event( + graph, pause->instance_id, + EVENT_ID_SOFT_PAUSE_PAUSE_COMPLETE, NULL, 0); + if (ret) + return ret; + ret = q6apm_register_module_event( + graph, pause->instance_id, + EVENT_ID_SOFT_PAUSE_RESUME_COMPLETE, NULL, 0); + if (ret) + return ret; + dev_info(graph->dev, + "SP11 stages pull-watermarks and soft-pause events accepted\n"); + + ret = audioreach_set_media_format(graph, pull, media_cfg); + if (ret) + dev_err(graph->dev, + "SP11 stage pull-media-format iid %#x param %#x failed: %d\n", + pull->instance_id, PARAM_ID_MEDIA_FORMAT, ret); + else + dev_info(graph->dev, + "SP11 stage pull-media-format accepted\n"); + return ret; +} +EXPORT_SYMBOL_GPL(q6apm_graph_configure_pull); + +int q6apm_map_memory_fixed_region(struct device *dev, unsigned int graph_id, phys_addr_t phys, + size_t sz) { struct audioreach_graph_info *info; struct q6apm *apm = dev_get_drvdata(dev->parent); @@ -215,10 +792,8 @@ static int __q6apm_map_memory_fixed_region(struct device *dev, unsigned int grap int payload_size = sizeof(*cmd) + (sizeof(*mregions)); uint32_t buf_sz; void *p; - uint32_t pos_mask = is_pos_buf ? APM_MMAP_TOKEN_MAP_TYPE_POS_BUF : 0; struct gpr_pkt *pkt __free(kfree) = audioreach_alloc_apm_cmd_pkt(payload_size, - APM_CMD_SHARED_MEM_MAP_REGIONS, (graph_id | pos_mask)); - + APM_CMD_SHARED_MEM_MAP_REGIONS, graph_id); if (IS_ERR(pkt)) return PTR_ERR(pkt); @@ -226,13 +801,8 @@ static int __q6apm_map_memory_fixed_region(struct device *dev, unsigned int grap if (!info) return -ENODEV; - if (is_pos_buf) { - if (info->pos_buf_mem_map_handle) - return 0; - } else { - if (info->mem_map_handle) - return 0; - } + if (info->mem_map_handle) + return 0; /* DSP expects size should be aligned to 4K */ buf_sz = ALIGN(sz, 4096); @@ -241,10 +811,7 @@ static int __q6apm_map_memory_fixed_region(struct device *dev, unsigned int grap cmd = p; cmd->mem_pool_id = APM_MEMORY_MAP_SHMEM8_4K_POOL; cmd->num_regions = 1; - if (is_pos_buf) - cmd->property_flag = 0x2; - else - cmd->property_flag = 0x0; + cmd->property_flag = 0x0; mregions = p + sizeof(*cmd); @@ -254,18 +821,6 @@ static int __q6apm_map_memory_fixed_region(struct device *dev, unsigned int grap return q6apm_send_cmd_sync(apm, pkt, APM_CMD_RSP_SHARED_MEM_MAP_REGIONS); } - -int q6apm_map_pos_buffer(struct device *dev, unsigned int graph_id, phys_addr_t phys, size_t sz) -{ - return __q6apm_map_memory_fixed_region(dev, graph_id, phys, sz, true); -} -EXPORT_SYMBOL_GPL(q6apm_map_pos_buffer); - -int q6apm_map_memory_fixed_region(struct device *dev, unsigned int graph_id, - phys_addr_t phys, size_t sz) -{ - return __q6apm_map_memory_fixed_region(dev, graph_id, phys, sz, false); -} EXPORT_SYMBOL_GPL(q6apm_map_memory_fixed_region); int q6apm_alloc_fragments(struct q6apm_graph *graph, unsigned int dir, phys_addr_t phys, @@ -319,13 +874,11 @@ int q6apm_alloc_fragments(struct q6apm_graph *graph, unsigned int dir, phys_addr } EXPORT_SYMBOL_GPL(q6apm_alloc_fragments); -static int __q6apm_unmap_memory_fixed_region(struct device *dev, unsigned int graph_id, - bool is_pos_buf) +int q6apm_unmap_memory_fixed_region(struct device *dev, unsigned int graph_id) { struct apm_cmd_shared_mem_unmap_regions *cmd; struct q6apm *apm = dev_get_drvdata(dev->parent); struct audioreach_graph_info *info; - uint32_t mem_map_handle; struct gpr_pkt *pkt __free(kfree) = audioreach_alloc_apm_cmd_pkt(sizeof(*cmd), APM_CMD_SHARED_MEM_UNMAP_REGIONS, graph_id); if (IS_ERR(pkt)) @@ -335,35 +888,16 @@ static int __q6apm_unmap_memory_fixed_region(struct device *dev, unsigned int gr if (!info) return -ENODEV; - if (is_pos_buf) { - if (!info->pos_buf_mem_map_handle) - return 0; - mem_map_handle = info->pos_buf_mem_map_handle; - } else { - - if (!info->mem_map_handle) - return 0; - mem_map_handle = info->mem_map_handle; - } + if (!info->mem_map_handle) + return 0; cmd = (void *)pkt + GPR_HDR_SIZE; - cmd->mem_map_handle = mem_map_handle; + cmd->mem_map_handle = info->mem_map_handle; return q6apm_send_cmd_sync(apm, pkt, APM_CMD_SHARED_MEM_UNMAP_REGIONS); } - -int q6apm_unmap_memory_fixed_region(struct device *dev, unsigned int graph_id) -{ - return __q6apm_unmap_memory_fixed_region(dev, graph_id, false); -} EXPORT_SYMBOL_GPL(q6apm_unmap_memory_fixed_region); -int q6apm_unmap_pos_buffer(struct device *dev, unsigned int graph_id) -{ - return __q6apm_unmap_memory_fixed_region(dev, graph_id, true); -} -EXPORT_SYMBOL_GPL(q6apm_unmap_pos_buffer); - int q6apm_free_fragments(struct q6apm_graph *graph, unsigned int dir) { audioreach_graph_free_buf(graph); @@ -448,13 +982,37 @@ int q6apm_graph_media_format_pcm(struct q6apm_graph *graph, struct audioreach_mo struct audioreach_module *module; int ret; + if (audioreach_graph_has_protected_calibration(info)) { + struct audioreach_module *pcm, *mfc; + + if (cfg->direction != SNDRV_PCM_STREAM_PLAYBACK || + cfg->sample_rate != 48000 || cfg->bit_width != 16 || + cfg->num_channels != 2) + return -EINVAL; + + pcm = __q6apm_find_module_by_iid(info, 0x465f); + mfc = __q6apm_find_module_by_iid(info, 0x466a); + if (!pcm || pcm->module_id != MODULE_ID_PCM_CNV || + !mfc || mfc->module_id != MODULE_ID_MFC) + return -ENODEV; + ret = audioreach_set_media_format(graph, pcm, cfg); + if (ret) + return ret; + dev_info(graph->dev, + "SP11 stage PCM_CNV media format accepted\n"); + ret = audioreach_set_media_format(graph, mfc, cfg); + if (ret) + return ret; + dev_info(graph->dev, + "SP11 stage MFC media format accepted\n"); + return audioreach_configure_protection(graph); + } + list_for_each_entry(sgs, &info->sg_list, node) { list_for_each_entry(container, &sgs->container_list, node) { list_for_each_entry(module, &container->modules_list, node) { if ((module->module_id == MODULE_ID_WR_SHARED_MEM_EP) || - (module->module_id == MODULE_ID_RD_SHARED_MEM_EP) || - (module->module_id == MODULE_ID_SH_MEM_PULL_MODE) || - (module->module_id == MODULE_ID_SH_MEM_PUSH_MODE)) + (module->module_id == MODULE_ID_RD_SHARED_MEM_EP)) continue; ret = audioreach_set_media_format(graph, module, cfg); @@ -469,6 +1027,34 @@ int q6apm_graph_media_format_pcm(struct q6apm_graph *graph, struct audioreach_mo } EXPORT_SYMBOL_GPL(q6apm_graph_media_format_pcm); +static int q6apm_graph_get_tx_shmem_module_iid(struct q6apm_graph *graph) +{ + struct audioreach_module *module; + + module = q6apm_find_module_by_mid(graph, MODULE_ID_RD_SHARED_MEM_EP); + if (!module) + return -ENODEV; + + return module->instance_id; + +} + +int q6apm_graph_get_rx_shmem_module_iid(struct q6apm_graph *graph) +{ + struct audioreach_module *module; + + module = q6apm_find_module_by_mid(graph, MODULE_ID_WR_SHARED_MEM_EP); + if (!module && audioreach_graph_has_protected_calibration(graph->info)) + module = q6apm_find_module_by_mid( + graph, MODULE_ID_SH_MEM_PULL_MODE); + if (!module) + return -ENODEV; + + return module->instance_id; + +} +EXPORT_SYMBOL_GPL(q6apm_graph_get_rx_shmem_module_iid); + int q6apm_write_async(struct q6apm_graph *graph, uint32_t len, uint32_t msw_ts, uint32_t lsw_ts, uint32_t wflags) { @@ -553,32 +1139,131 @@ int q6apm_get_hw_pointer(struct q6apm_graph *graph, int dir) } EXPORT_SYMBOL_GPL(q6apm_get_hw_pointer); +snd_pcm_uframes_t q6apm_get_pull_hw_pointer(struct q6apm_graph *graph, + struct snd_pcm_runtime *runtime) +{ + struct sh_mem_pull_push_mode_position_buffer *position; + u32 before, after, index; + int retries = 4; + + if (!graph->pull_mode || !graph->ar_graph || + !graph->ar_graph->position_virt) + return 0; + + position = graph->ar_graph->position_virt; + do { + before = READ_ONCE(position->frame_counter); + dma_rmb(); + index = READ_ONCE(position->index); + dma_rmb(); + after = READ_ONCE(position->frame_counter); + } while ((!before || before != after) && --retries); + + if (!before || before != after || + index >= frames_to_bytes(runtime, runtime->buffer_size)) + index = atomic_read(&graph->rx_data.hw_ptr); + else + atomic_set(&graph->rx_data.hw_ptr, index); + + return bytes_to_frames(runtime, index); +} +EXPORT_SYMBOL_GPL(q6apm_get_pull_hw_pointer); + static int graph_callback(const struct gpr_resp_pkt *data, void *priv, int op) { struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 *rd_done; struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 *done; - struct apm_module_event *event; const struct gpr_ibasic_rsp_result_t *result; struct q6apm_graph *graph = priv; const struct gpr_hdr *hdr = &data->hdr; struct device *dev = graph->dev; uint32_t client_event; phys_addr_t phys; + size_t dump_len; int token; result = data->payload; switch (hdr->opcode) { - case APM_EVENT_MODULE_TO_CLIENT: - event = data->payload; - switch (event->event_id) { - case EVENT_ID_SH_MEM_PULL_PUSH_MODE_WATERMARK: - client_event = APM_CLIENT_EVENT_WATERMARK_EVENT; - graph->cb(client_event, hdr->token, data->payload, graph->priv); + case APM_CMD_RSP_GET_CFG: + graph->result.opcode = hdr->opcode; + if (data->payload_size < sizeof(u32)) { + dev_err(dev, + "SP11 GET_CFG response token=%#x is truncated: %d bytes\n", + hdr->token, data->payload_size); + graph->result.status = -EPROTO; + wake_up(&graph->cmd_wait); + break; + } + + graph->result.status = *(const u32 *)data->payload; + dump_len = min_t(size_t, data->payload_size, 512); + dev_info(dev, + "SP11 GET_CFG response token=%#x bytes=%d status=%#x%s\n", + hdr->token, data->payload_size, graph->result.status, + data->payload_size > dump_len ? " (dump truncated)" : ""); + print_hex_dump(KERN_INFO, "sp11-getcfg: ", DUMP_PREFIX_OFFSET, + 16, 1, data->payload, dump_len, false); + wake_up(&graph->cmd_wait); + break; + case APM_EVENT_MODULE_TO_CLIENT: { + const struct apm_module_event *event = data->payload; + + if (data->payload_size < sizeof(*event)) { + dev_warn(dev, "SP11 truncated module event: %d bytes\n", + data->payload_size); + break; + } + + /* + * SP11 2026-08-01: log every module->client event. + * + * Upstream drops anything that is not the pull-mode watermark, so + * if the DSP reports speaker-protection activity nobody sees it. + * Windows registers ADSP callbacks (EVENT_ID_VI_CALIBRATION, + * EVENT_ID_SPv5_SPEAKER_DIAGNOSTICS per Ghidra of qcadcm8380.sys) + * and persists the resulting R0Cal/T0Cal to the registry. Linux has + * no equivalent return path, which is why protection can be shown + * CONFIGURED but never shown to be ACTING. + * + * The SPv5 diagnostics event id is NOT known: prior analysis found + * 0x0800138C belongs to instance 0x4ac1 in an unrelated graph, and + * 0x08001511 is used by the Windows driver directly via GSL and is + * absent from the CDDE. So do not guess an id. Log whatever + * arrives, with its source instance, and let evidence name it. + */ + if (event->event_id != EVENT_ID_SH_MEM_PULL_PUSH_MODE_WATERMARK) + dev_info(graph->dev, + "SP11 module event: src %#x event %#x payload %u\n", + data->hdr.src_port, event->event_id, + event->event_payload_size); + + if (!graph->pull_mode) break; + + if (data->hdr.src_port == SP11_SOFT_PAUSE_IID && graph->cb) { + if (event->event_id == EVENT_ID_SOFT_PAUSE_PAUSE_COMPLETE) { + graph->cb(APM_CLIENT_EVENT_SOFT_PAUSE_COMPLETE, 0, + (u8 *)data->payload + sizeof(*event), + graph->priv); + break; + } + if (event->event_id == EVENT_ID_SOFT_PAUSE_RESUME_COMPLETE) { + graph->cb(APM_CLIENT_EVENT_SOFT_RESUME_COMPLETE, 0, + (u8 *)data->payload + sizeof(*event), + graph->priv); + break; + } } + if (event->event_id != EVENT_ID_SH_MEM_PULL_PUSH_MODE_WATERMARK) + break; + if (graph->cb) + graph->cb(APM_CLIENT_EVENT_PULL_WATERMARK, 0, + (u8 *)data->payload + sizeof(*event), + graph->priv); break; + } case DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2: if (!graph->ar_graph) break; @@ -642,8 +1327,12 @@ static int graph_callback(const struct gpr_resp_pkt *data, void *priv, int op) switch (result->opcode) { case APM_CMD_SHARED_MEM_MAP_REGIONS: case DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT: - case APM_CMD_REGISTER_MODULE_EVENTS: case APM_CMD_SET_CFG: + case APM_CMD_GET_CFG: + case APM_CMD_REGISTER_MODULE_EVENTS: + case APM_CMD_GRAPH_START: + case APM_CMD_GRAPH_STOP: + case APM_CMD_GRAPH_FLUSH: graph->result.opcode = result->opcode; graph->result.status = result->status; if (result->status) @@ -661,69 +1350,15 @@ static int graph_callback(const struct gpr_resp_pkt *data, void *priv, int op) return 0; } -int q6apm_register_watermark_event(struct q6apm_graph *graph, int water_mark_level_bytes, - int num_levels) -{ - return audioreach_shmem_register_event(graph, water_mark_level_bytes, num_levels); -} -EXPORT_SYMBOL_GPL(q6apm_register_watermark_event); - -int q6apm_push_pull_config(struct q6apm_graph *graph, phys_addr_t bphys, - phys_addr_t pphys, uint32_t size) -{ - struct audioreach_graph_info *info = graph->info; - - return audioreach_setup_push_pull(graph, bphys, pphys, info->mem_map_handle, - info->pos_buf_mem_map_handle, size); -} -EXPORT_SYMBOL_GPL(q6apm_push_pull_config); - -bool q6apm_is_graph_in_push_pull_mode_from_id(struct device *dev, unsigned int graph_id, int dir) -{ - struct audioreach_graph_info *info; - struct q6apm *apm = dev_get_drvdata(dev->parent); - struct audioreach_module *module; - - info = idr_find(&apm->graph_info_idr, graph_id); - if (!info) - return false; - - if (dir == SNDRV_PCM_STREAM_PLAYBACK) - module = __q6apm_find_module_by_mid(apm, info, MODULE_ID_SH_MEM_PULL_MODE); - else - module = __q6apm_find_module_by_mid(apm, info, MODULE_ID_SH_MEM_PUSH_MODE); - - return !!module; - -} -EXPORT_SYMBOL_GPL(q6apm_is_graph_in_push_pull_mode_from_id); - -bool q6apm_is_graph_in_push_pull_mode(struct q6apm_graph *graph) -{ - return graph->info->is_push_pull_mode; -} -EXPORT_SYMBOL_GPL(q6apm_is_graph_in_push_pull_mode); - -static int q6apm_graph_get_module_iid(struct q6apm_graph *graph, uint32_t mid) -{ - struct audioreach_module *module; - - module = q6apm_find_module_by_mid(graph, mid); - if (!module) - return -ENODEV; - - return module->instance_id; -} - struct q6apm_graph *q6apm_graph_open(struct device *dev, q6apm_cb cb, void *priv, int graph_id, int dir) { struct q6apm *apm = dev_get_drvdata(dev->parent); struct audioreach_graph *ar_graph; struct q6apm_graph *graph; - int ret, iid = 0; + int ret; - ar_graph = q6apm_get_audioreach_graph(apm, graph_id); + ar_graph = q6apm_get_audioreach_graph(apm, dev, graph_id); if (IS_ERR(ar_graph)) { dev_err(dev, "No graph found with id %d\n", graph_id); return ERR_CAST(ar_graph); @@ -742,24 +1377,15 @@ struct q6apm_graph *q6apm_graph_open(struct device *dev, q6apm_cb cb, graph->ar_graph = ar_graph; graph->id = ar_graph->id; graph->dev = dev; + graph->pull_mode = + dir == SNDRV_PCM_STREAM_PLAYBACK && + audioreach_graph_has_protected_calibration(graph->info); - if (dir == SNDRV_PCM_STREAM_PLAYBACK) { - iid = q6apm_graph_get_module_iid(graph, MODULE_ID_SH_MEM_PULL_MODE); - if (iid < 0) - iid = q6apm_graph_get_module_iid(graph, MODULE_ID_WR_SHARED_MEM_EP); - else - graph->info->is_push_pull_mode = true; - - } else { - iid = q6apm_graph_get_module_iid(graph, MODULE_ID_SH_MEM_PUSH_MODE); - if (iid < 0) - iid = q6apm_graph_get_module_iid(graph, MODULE_ID_RD_SHARED_MEM_EP); - else - graph->info->is_push_pull_mode = true; - } + if (dir == SNDRV_PCM_STREAM_PLAYBACK) + graph->shm_iid = q6apm_graph_get_rx_shmem_module_iid(graph); + else + graph->shm_iid = q6apm_graph_get_tx_shmem_module_iid(graph); - if (iid > 0) - graph->shm_iid = iid; mutex_init(&graph->lock); init_waitqueue_head(&graph->cmd_wait); @@ -795,6 +1421,9 @@ EXPORT_SYMBOL_GPL(q6apm_graph_close); int q6apm_graph_prepare(struct q6apm_graph *graph) { + if (graph->pull_mode) + return 0; + return audioreach_graph_mgmt_cmd(graph->ar_graph, APM_CMD_GRAPH_PREPARE); } EXPORT_SYMBOL_GPL(q6apm_graph_prepare); @@ -804,10 +1433,16 @@ int q6apm_graph_start(struct q6apm_graph *graph) struct audioreach_graph *ar_graph = graph->ar_graph; int ret = 0; - if (ar_graph->start_count == 0) - ret = audioreach_graph_mgmt_cmd(ar_graph, APM_CMD_GRAPH_START); + if (ar_graph->start_count == 0) { + ret = audioreach_graph_client_mgmt_cmd(graph, + APM_CMD_GRAPH_START); + if (!ret && graph->pull_mode) + dev_info(graph->dev, + "SP11 stage GRAPH_START accepted\n"); + } - ar_graph->start_count++; + if (!ret) + ar_graph->start_count++; return ret; } @@ -820,18 +1455,373 @@ int q6apm_graph_stop(struct q6apm_graph *graph) if (--ar_graph->start_count > 0) return 0; - return audioreach_graph_mgmt_cmd(ar_graph, APM_CMD_GRAPH_STOP); + return audioreach_graph_client_mgmt_cmd(graph, APM_CMD_GRAPH_STOP); } EXPORT_SYMBOL_GPL(q6apm_graph_stop); int q6apm_graph_flush(struct q6apm_graph *graph) { - return audioreach_graph_mgmt_cmd(graph->ar_graph, APM_CMD_GRAPH_FLUSH); + return audioreach_graph_client_mgmt_cmd(graph, APM_CMD_GRAPH_FLUSH); } EXPORT_SYMBOL_GPL(q6apm_graph_flush); +/* + * Reproduce qcadcm SetStreamPause() for the SP11 protected pull graph. + * REV_0D tag 0x04010008 / key 0x01000021 resolves to a zero-length + * parameter command on iid 0x466b: value 1 -> 0x0800102e (pause), + * value 0 -> 0x0800102f (resume/release). The Aug-10 common-GPR Windows + * capture independently observed both exact SET_CFG headers. + */ +int q6apm_graph_sp11_soft_pause(struct q6apm_graph *graph, bool pause) +{ + struct audioreach_module *module; + struct apm_module_param_data param = { 0 }; + + if (!graph || !graph->pull_mode || !graph->ar_graph) + return -EOPNOTSUPP; + + module = q6apm_find_module_by_mid(graph, SP11_MODULE_ID_SOFT_PAUSE); + if (!module || module->instance_id != SP11_SOFT_PAUSE_IID) + return -EOPNOTSUPP; + + param.module_instance_id = module->instance_id; + param.param_id = pause ? SP11_PARAM_SOFT_PAUSE_PAUSE : + SP11_PARAM_SOFT_PAUSE_RESUME; + param.param_size = 0; + param.error_code = 0; + + return q6apm_send_inband_config(graph->ar_graph, ¶m, sizeof(param)); +} +EXPORT_SYMBOL_GPL(q6apm_graph_sp11_soft_pause); + +/* + * SP11 MSIIR parameter injection control (added 2026-08-01). + * + * Mirrors what DolbyAPOvlldp150 does on Windows: a user-space processor + * analyses the stream, computes MSIIR coefficients, and injects them into the + * DSP module that is already in the graph. The DSP filters; user space only + * decides the coefficients. Audio never leaves the DSP path, so speaker + * protection still sees the processed signal exactly as it does on Windows. + * + * Write format (little-endian): + * + * u32 instance_id + * u32 param_id + * u32 payload_size + * u8 payload[payload_size] + * + * Both instance_id and param_id are allowlisted in + * audioreach_sp11_inject_module_param(). A write while no graph is running + * will be rejected by the DSP, typically with -22, because MSIIR gates its + * tuning parameters behind CAPI initialisation. + */ +#define SND_SOC_TLV_HDR (2 * sizeof(u32)) +#define SP11_INJECT_CTL_HDR (3 * sizeof(u32)) +#define SP11_INJECT_CTL_MAX 1152 + +#define SP11_VOLUME_TRANSACTION_NORMAL_SIZE 216 +#define SP11_VOLUME_TRANSACTION_LARGE_SIZE 272 +#define SP11_VOLUME_TRANSACTION_PAYLOAD_MAX (2 * sizeof(u32) + \ + SP11_VOLUME_TRANSACTION_LARGE_SIZE) +#define SP11_VOLUME_TRANSACTION_CONTROL_MAX (SND_SOC_TLV_HDR + \ + SP11_VOLUME_TRANSACTION_PAYLOAD_MAX) +#define SP11_GAINSTEP_IID 0x489e +#define SP11_VOLUME_ONLY_CONTROL_MAX (SND_SOC_TLV_HDR + 2 * sizeof(u32)) +#define SP11_ENDPOINT_MUTE_CONTROL_MAX (SND_SOC_TLV_HDR + sizeof(u32)) + +static DEFINE_MUTEX(sp11_volume_transaction_lock); + +static int q6apm_sp11_validate_gainstep_delta(const u8 *data, size_t size) +{ + static const u32 expected_param_ids[] = { + 0x08001020, 0x08001021, 0x08001022, 0x08001026, + }; + static const u32 expected_param_sizes[] = { 28, 16, 0, 4 }; + size_t offset = 0; + u32 coeff_size; + int i; + + if (size == SP11_VOLUME_TRANSACTION_NORMAL_SIZE) + coeff_size = 96; + else if (size == SP11_VOLUME_TRANSACTION_LARGE_SIZE) + coeff_size = 152; + else + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(expected_param_ids); i++) { + size_t frame_size, padding; + u32 param_size; + + if (size - offset < APM_MODULE_PARAM_DATA_SIZE) + return -EINVAL; + if (get_unaligned_le32(data + offset) != SP11_GAINSTEP_IID || + get_unaligned_le32(data + offset + sizeof(u32)) != + expected_param_ids[i] || + get_unaligned_le32(data + offset + 3 * sizeof(u32)) != 0) + return -EPERM; + + param_size = get_unaligned_le32(data + offset + 2 * sizeof(u32)); + if (param_size != (i == 2 ? coeff_size : expected_param_sizes[i])) + return -EINVAL; + + frame_size = ALIGN(APM_MODULE_PARAM_DATA_SIZE + param_size, 8); + if (frame_size > size - offset) + return -EINVAL; + padding = frame_size - APM_MODULE_PARAM_DATA_SIZE - param_size; + if (padding && memchr_inv(data + offset + APM_MODULE_PARAM_DATA_SIZE + + param_size, 0, padding)) + return -EINVAL; + offset += frame_size; + } + + return offset == size ? 0 : -EINVAL; +} + +static struct audioreach_graph * +q6apm_sp11_get_running_protected_graph(struct q6apm *apm) +{ + struct audioreach_graph *graph; + int id; + + mutex_lock(&apm->lock); + idr_for_each_entry(&apm->graph_idr, graph, id) { + if (!audioreach_graph_has_protected_calibration(graph->info) || + READ_ONCE(graph->start_count) <= 0) + continue; + kref_get(&graph->refcount); + mutex_unlock(&apm->lock); + return graph; + } + mutex_unlock(&apm->lock); + + return ERR_PTR(-ENODEV); +} + +static int q6apm_sp11_apply_volume_transaction(struct q6apm *apm, u32 left_q28, + u32 right_q28, const u8 *delta, + size_t delta_size) +{ + struct audioreach_graph *graph; + int ret; + + ret = q6apm_sp11_validate_gainstep_delta(delta, delta_size); + if (ret) + return ret; + + graph = q6apm_sp11_get_running_protected_graph(apm); + if (IS_ERR(graph)) + return PTR_ERR(graph); + + mutex_lock(&sp11_volume_transaction_lock); + ret = audioreach_sp11_set_final_volume_q28(apm, left_q28, right_q28); + if (!ret) + ret = q6apm_send_oob_config(graph, delta, delta_size); + mutex_unlock(&sp11_volume_transaction_lock); + + if (ret) + dev_dbg(apm->dev, + "SP11 volume transaction L %#x R %#x delta %zu -> %d\n", + left_q28, right_q28, delta_size, ret); + + kref_put(&graph->refcount, q6apm_put_audioreach_graph); + return ret; +} + +static int +q6apm_sp11_volume_only_put(struct snd_kcontrol *kcontrol, + const unsigned int __user *bytes, + unsigned int size) +{ + struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); + struct q6apm *apm = dev_get_drvdata(c->dev); + struct audioreach_graph *graph; + u32 gain_q28[2]; + u32 left_q28, right_q28; + int ret; + + if (size != SP11_VOLUME_ONLY_CONTROL_MAX) + return -EINVAL; + + bytes += 2; + if (copy_from_user(gain_q28, bytes, sizeof(gain_q28))) + return -EFAULT; + left_q28 = le32_to_cpu(gain_q28[0]); + right_q28 = le32_to_cpu(gain_q28[1]); + + graph = q6apm_sp11_get_running_protected_graph(apm); + if (IS_ERR(graph)) + return PTR_ERR(graph); + + mutex_lock(&sp11_volume_transaction_lock); + ret = audioreach_sp11_set_final_volume_q28(apm, left_q28, right_q28); + mutex_unlock(&sp11_volume_transaction_lock); + + if (ret) + dev_dbg(apm->dev, + "SP11 volume-only L %#x R %#x -> %d\n", + left_q28, right_q28, ret); + + kref_put(&graph->refcount, q6apm_put_audioreach_graph); + return ret; +} + +static int +q6apm_sp11_endpoint_mute_put(struct snd_kcontrol *kcontrol, + const unsigned int __user *bytes, + unsigned int size) +{ + struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); + struct q6apm *apm = dev_get_drvdata(c->dev); + struct audioreach_graph *graph; + u32 mute; + int ret; + + if (size != SP11_ENDPOINT_MUTE_CONTROL_MAX) + return -EINVAL; + + bytes += 2; + if (copy_from_user(&mute, bytes, sizeof(mute))) + return -EFAULT; + mute = le32_to_cpu(mute); + if (mute > 1) + return -EINVAL; + + graph = q6apm_sp11_get_running_protected_graph(apm); + if (IS_ERR(graph)) + return PTR_ERR(graph); + + mutex_lock(&sp11_volume_transaction_lock); + ret = audioreach_sp11_set_final_mute(apm, mute != 0); + mutex_unlock(&sp11_volume_transaction_lock); + + if (ret) + dev_dbg(apm->dev, "SP11 endpoint mute %u -> %d\n", mute, ret); + + kref_put(&graph->refcount, q6apm_put_audioreach_graph); + return ret; +} + +static int q6apm_sp11_inject_put(struct snd_kcontrol *kcontrol, + const unsigned int __user *bytes, + unsigned int size) +{ + struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); + struct q6apm *apm = dev_get_drvdata(c->dev); + u32 hdr[3], iid, param_id, psize; + void *payload; + int ret; + + /* + * snd_soc_bytes_tlv_callback() hands us the whole TLV buffer, which + * begins with the two-word ALSA TLV header (type, length). Skip it; + * our own header starts after that. + */ + if (size < SND_SOC_TLV_HDR + SP11_INJECT_CTL_HDR || + size > SND_SOC_TLV_HDR + SP11_INJECT_CTL_MAX) + return -EINVAL; + + bytes += 2; + size -= SND_SOC_TLV_HDR; + + if (copy_from_user(hdr, bytes, sizeof(hdr))) + return -EFAULT; + + iid = le32_to_cpu(hdr[0]); + param_id = le32_to_cpu(hdr[1]); + psize = le32_to_cpu(hdr[2]); + + if (psize == 0 || psize > size - SP11_INJECT_CTL_HDR) + return -EINVAL; + + payload = kzalloc(psize, GFP_KERNEL); + if (!payload) + return -ENOMEM; + + if (copy_from_user(payload, + (const u8 __user *)bytes + SP11_INJECT_CTL_HDR, + psize)) { + kfree(payload); + return -EFAULT; + } + + ret = audioreach_sp11_inject_module_param(apm, iid, param_id, + payload, psize); + if (ret) + dev_dbg(apm->dev, + "SP11 inject iid %#x param %#x size %u -> %d\n", + iid, param_id, psize, ret); + + kfree(payload); + return ret; +} + +static int +q6apm_sp11_volume_transaction_put(struct snd_kcontrol *kcontrol, + const unsigned int __user *bytes, + unsigned int size) +{ + struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); + struct q6apm *apm = dev_get_drvdata(c->dev); + u8 data[SP11_VOLUME_TRANSACTION_PAYLOAD_MAX]; + size_t payload_size, gain_size, delta_size; + u32 left_q28, right_q28; + + if (size < SND_SOC_TLV_HDR + sizeof(left_q28)) + return -EINVAL; + payload_size = size - SND_SOC_TLV_HDR; + + /* + * Preserve the deployed one-Q28 ABI while adding the exact Windows master + * volume form: left Q28 + right Q28 + one GainStep delta. The extended + * form permits the intermediate L=new/R=old body observed by KDNET. + */ + if (payload_size == sizeof(left_q28) + SP11_VOLUME_TRANSACTION_NORMAL_SIZE || + payload_size == sizeof(left_q28) + SP11_VOLUME_TRANSACTION_LARGE_SIZE) + gain_size = sizeof(left_q28); + else if (payload_size == 2 * sizeof(left_q28) + + SP11_VOLUME_TRANSACTION_NORMAL_SIZE || + payload_size == 2 * sizeof(left_q28) + + SP11_VOLUME_TRANSACTION_LARGE_SIZE) + gain_size = 2 * sizeof(left_q28); + else + return -EINVAL; + + bytes += 2; + if (copy_from_user(data, bytes, payload_size)) + return -EFAULT; + left_q28 = get_unaligned_le32(data); + right_q28 = gain_size == 2 * sizeof(left_q28) ? + get_unaligned_le32(data + sizeof(left_q28)) : left_q28; + delta_size = payload_size - gain_size; + + return q6apm_sp11_apply_volume_transaction(apm, left_q28, right_q28, + data + gain_size, delta_size); +} + +static const struct snd_kcontrol_new q6apm_sp11_controls[] = { + SND_SOC_BYTES_TLV("SP11 MSIIR Inject", SP11_INJECT_CTL_MAX, + NULL, q6apm_sp11_inject_put), + SND_SOC_BYTES_TLV("SP11 Windows Volume Transaction", + SP11_VOLUME_TRANSACTION_CONTROL_MAX, NULL, + q6apm_sp11_volume_transaction_put), + SND_SOC_BYTES_TLV("SP11 Windows Volume Only", + SP11_VOLUME_ONLY_CONTROL_MAX, NULL, + q6apm_sp11_volume_only_put), + SND_SOC_BYTES_TLV("SP11 Windows Endpoint Mute", + SP11_ENDPOINT_MUTE_CONTROL_MAX, NULL, + q6apm_sp11_endpoint_mute_put), +}; + static int q6apm_audio_probe(struct snd_soc_component *component) { + int ret; + + ret = snd_soc_add_component_controls(component, + q6apm_sp11_controls, + ARRAY_SIZE(q6apm_sp11_controls)); + if (ret) + return ret; + return audioreach_tplg_init(component); } @@ -907,16 +1897,47 @@ struct audioreach_module *q6apm_find_module_by_mid(struct q6apm_graph *graph, ui } +int q6apm_graph_id_for_backend(struct device *dev, int backend_id) +{ + struct q6apm *apm = dev_get_drvdata(dev->parent); + struct audioreach_graph_info *info; + struct audioreach_container *container; + struct audioreach_sub_graph *sg; + struct audioreach_module *module; + int id; + + if (!apm) + return -ENODEV; + + mutex_lock(&apm->lock); + idr_for_each_entry(&apm->graph_info_idr, info, id) { + list_for_each_entry(sg, &info->sg_list, node) { + list_for_each_entry(container, &sg->container_list, node) { + list_for_each_entry(module, &container->modules_list, node) { + if (module->integrated_backend_id == backend_id) { + mutex_unlock(&apm->lock); + return info->id; + } + } + } + } + } + mutex_unlock(&apm->lock); + + return backend_id; +} +EXPORT_SYMBOL_GPL(q6apm_graph_id_for_backend); + static int apm_callback(const struct gpr_resp_pkt *data, void *priv, int op) { gpr_device_t *gdev = priv; + struct audioreach_graph *graph; struct audioreach_graph_info *info; struct q6apm *apm = dev_get_drvdata(&gdev->dev); struct apm_cmd_rsp_shared_mem_map_regions *rsp; struct device *dev = &gdev->dev; struct gpr_ibasic_rsp_result_t *result; const struct gpr_hdr *hdr = &data->hdr; - int graph_id, is_pos_buf; result = data->payload; @@ -946,14 +1967,31 @@ static int apm_callback(const struct gpr_resp_pkt *data, void *priv, int op) wake_up(&apm->wait); break; case APM_CMD_SHARED_MEM_UNMAP_REGIONS: - apm->result.opcode = hdr->opcode; + apm->result.opcode = result->opcode; apm->result.status = 0; rsp = data->payload; - info = idr_find(&apm->graph_info_idr, hdr->token); - if (info) - info->mem_map_handle = 0; - else + if (hdr->token & Q6APM_OOB_MAP_TOKEN) { + graph = idr_find( + &apm->graph_idr, + hdr->token & ~Q6APM_OOB_MAP_TOKEN); + if (graph) + graph->oob_mem_map_handle = 0; + } else if (hdr->token & Q6APM_POSITION_MAP_TOKEN) { + graph = idr_find( + &apm->graph_idr, + hdr->token & ~Q6APM_POSITION_MAP_TOKEN); + if (graph) + graph->position_mem_map_handle = 0; + } else { + info = idr_find(&apm->graph_info_idr, + hdr->token); + if (info) + info->mem_map_handle = 0; + } + if (!(hdr->token & + (Q6APM_OOB_MAP_TOKEN | Q6APM_POSITION_MAP_TOKEN)) && + !info) dev_err(dev, "Error (%d) Processing 0x%08x cmd\n", result->status, result->opcode); @@ -967,19 +2005,29 @@ static int apm_callback(const struct gpr_resp_pkt *data, void *priv, int op) apm->result.opcode = hdr->opcode; apm->result.status = 0; rsp = data->payload; - graph_id = hdr->token & APM_MMAP_TOKEN_GID_MASK; - is_pos_buf = hdr->token & APM_MMAP_TOKEN_MAP_TYPE_POS_BUF; - - info = idr_find(&apm->graph_info_idr, graph_id); - if (info) { - if (is_pos_buf) - info->pos_buf_mem_map_handle = rsp->mem_map_handle; - else - info->mem_map_handle = rsp->mem_map_handle; + + if (hdr->token & Q6APM_OOB_MAP_TOKEN) { + graph = idr_find(&apm->graph_idr, + hdr->token & ~Q6APM_OOB_MAP_TOKEN); + if (graph) + graph->oob_mem_map_handle = rsp->mem_map_handle; + } else if (hdr->token & Q6APM_POSITION_MAP_TOKEN) { + graph = idr_find( + &apm->graph_idr, + hdr->token & ~Q6APM_POSITION_MAP_TOKEN); + if (graph) + graph->position_mem_map_handle = + rsp->mem_map_handle; } else { + info = idr_find(&apm->graph_info_idr, hdr->token); + if (info) + info->mem_map_handle = rsp->mem_map_handle; + } + if (!(hdr->token & + (Q6APM_OOB_MAP_TOKEN | Q6APM_POSITION_MAP_TOKEN)) && + !info) dev_err(dev, "Error (%d) Processing 0x%08x cmd\n", result->status, result->opcode); - } wake_up(&apm->wait); break; diff --git a/sound/soc/qcom/qdsp6/q6apm.h b/sound/soc/qcom/qdsp6/q6apm.h index 5cb51ca491dc4f..2d028577670c7f 100644 --- a/sound/soc/qcom/qdsp6/q6apm.h +++ b/sound/soc/qcom/qdsp6/q6apm.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -41,7 +42,9 @@ #define APM_CLIENT_EVENT_CMD_RUN_DONE 0x1008 #define APM_CLIENT_EVENT_DATA_WRITE_DONE 0x1009 #define APM_CLIENT_EVENT_DATA_READ_DONE 0x100a -#define APM_CLIENT_EVENT_WATERMARK_EVENT 0x100b +#define APM_CLIENT_EVENT_PULL_WATERMARK 0x100b +#define APM_CLIENT_EVENT_SOFT_PAUSE_COMPLETE 0x100c +#define APM_CLIENT_EVENT_SOFT_RESUME_COMPLETE 0x100d #define APM_WRITE_TOKEN_MASK GENMASK(15, 0) #define APM_WRITE_TOKEN_LEN_MASK GENMASK(31, 16) #define APM_WRITE_TOKEN_LEN_SHIFT 16 @@ -87,6 +90,19 @@ struct audioreach_graph { uint32_t id; int state; int start_count; + bool protection_configured; + struct mutex protection_lock; + struct device *dma_dev; + void *oob_virt; + dma_addr_t oob_phys; + phys_addr_t oob_dsp_addr; + size_t oob_size; + uint32_t oob_mem_map_handle; + void *position_virt; + dma_addr_t position_phys; + phys_addr_t position_dsp_addr; + size_t position_size; + uint32_t position_mem_map_handle; /* Cached Graph data */ void *graph; struct kref refcount; @@ -110,6 +126,7 @@ struct q6apm_graph { struct mutex lock; struct audioreach_graph *ar_graph; struct audioreach_graph_info *info; + bool pull_mode; }; /* Graph Operations */ @@ -120,6 +137,8 @@ int q6apm_graph_prepare(struct q6apm_graph *graph); int q6apm_graph_start(struct q6apm_graph *graph); int q6apm_graph_stop(struct q6apm_graph *graph); int q6apm_graph_flush(struct q6apm_graph *graph); +int q6apm_graph_sp11_soft_pause(struct q6apm_graph *graph, bool pause); +bool q6apm_graph_is_pull_mode(struct device *dev, unsigned int graph_id); /* Media Format */ int q6apm_graph_media_format_pcm(struct q6apm_graph *graph, @@ -127,6 +146,10 @@ int q6apm_graph_media_format_pcm(struct q6apm_graph *graph, int q6apm_graph_media_format_shmem(struct q6apm_graph *graph, struct audioreach_module_config *cfg); +int q6apm_graph_configure_pull(struct q6apm_graph *graph, + struct audioreach_module_config *cfg, + phys_addr_t ring_addr, size_t ring_size, + size_t period_size); /* read/write related */ int q6apm_read(struct q6apm_graph *graph); @@ -137,10 +160,6 @@ int q6apm_write_async(struct q6apm_graph *graph, uint32_t len, uint32_t msw_ts, int q6apm_map_memory_fixed_region(struct device *dev, unsigned int graph_id, phys_addr_t phys, size_t sz); -int q6apm_map_pos_buffer(struct device *dev, - unsigned int graph_id, phys_addr_t phys, - size_t sz); -int q6apm_unmap_pos_buffer(struct device *dev, unsigned int graph_id); int q6apm_alloc_fragments(struct q6apm_graph *graph, unsigned int dir, phys_addr_t phys, size_t period_sz, unsigned int periods); @@ -149,21 +168,30 @@ int q6apm_unmap_memory_fixed_region(struct device *dev, unsigned int graph_id); /* Helpers */ int q6apm_send_cmd_sync(struct q6apm *apm, const struct gpr_pkt *pkt, uint32_t rsp_opcode); +int q6apm_graph_id_for_backend(struct device *dev, int backend_id); +int q6apm_send_oob_config(struct audioreach_graph *graph, + const void *data, size_t size); +int q6apm_send_graph_oob_config(struct q6apm_graph *graph, + const void *data, size_t size); +int q6apm_send_inband_config(struct audioreach_graph *graph, + const void *data, size_t size); /* Callback for graph specific */ struct audioreach_module *q6apm_find_module_by_mid(struct q6apm_graph *graph, uint32_t mid); +int q6apm_graph_get_rx_shmem_module_iid(struct q6apm_graph *graph); + bool q6apm_is_adsp_ready(void); +void q6apm_sp11_set_vi_ready(bool ready); +bool q6apm_sp11_vi_ready(void); +void q6apm_sp11_set_cps_ready(bool ready); +bool q6apm_sp11_cps_ready(void); int q6apm_enable_compress_module(struct device *dev, struct q6apm_graph *graph, bool en); int q6apm_remove_initial_silence(struct device *dev, struct q6apm_graph *graph, uint32_t samples); int q6apm_remove_trailing_silence(struct device *dev, struct q6apm_graph *graph, uint32_t samples); int q6apm_set_real_module_id(struct device *dev, struct q6apm_graph *graph, uint32_t codec_id); int q6apm_get_hw_pointer(struct q6apm_graph *graph, int dir); -bool q6apm_is_graph_in_push_pull_mode(struct q6apm_graph *graph); -bool q6apm_is_graph_in_push_pull_mode_from_id(struct device *dev, unsigned int graph_id, int dir); -int q6apm_push_pull_config(struct q6apm_graph *graph, phys_addr_t bphys, - phys_addr_t pphys, uint32_t size); - -int q6apm_register_watermark_event(struct q6apm_graph *graph, int watermark_bytes, int num_levels); +snd_pcm_uframes_t q6apm_get_pull_hw_pointer(struct q6apm_graph *graph, + struct snd_pcm_runtime *runtime); #endif /* __APM_GRAPH_ */ diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c index e5cd82f77b5520..5f3b9b4722360e 100644 --- a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c @@ -79,6 +79,60 @@ .id = did, \ } +#define Q6AFE_CDC_DMA_CPS_DAI(did) { \ + .playback = { \ + .stream_name = #did " Protection", \ + .rates = SNDRV_PCM_RATE_24000, \ + .formats = SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 2, \ + .channels_max = 2, \ + .rate_min = 24000, \ + .rate_max = 24000, \ + }, \ + .capture = { \ + .stream_name = #did " Capture", \ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_176400, \ + .formats = SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 1, \ + .channels_max = 8, \ + .rate_min = 8000, \ + .rate_max = 176400, \ + }, \ + .name = #did, \ + .id = did, \ + } + +#define Q6AFE_CDC_DMA_VI_DAI(did) { \ + .playback = { \ + .stream_name = #did" Protection", \ + .rates = SNDRV_PCM_RATE_8000, \ + .formats = SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 2, \ + .channels_max = 2, \ + .rate_min = 8000, \ + .rate_max = 8000, \ + }, \ + .capture = { \ + .stream_name = #did" Capture", \ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_176400, \ + .formats = SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 1, \ + .channels_max = 8, \ + .rate_min = 8000, \ + .rate_max = 176400, \ + }, \ + .name = #did, \ + .id = did, \ + } + #define Q6AFE_DP_RX_DAI(did) { \ .playback = { \ .stream_name = #did" Playback", \ @@ -647,9 +701,9 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_6), Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_7), Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_0), - Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_0), + Q6AFE_CDC_DMA_VI_DAI(WSA_CODEC_DMA_TX_0), Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_1), - Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_1), + Q6AFE_CDC_DMA_CPS_DAI(WSA_CODEC_DMA_TX_1), Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_2), Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_0), Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_1), diff --git a/sound/soc/qcom/qdsp6/topology.c b/sound/soc/qcom/qdsp6/topology.c index 1f69fba6de26d1..3c59e630a589f2 100644 --- a/sound/soc/qcom/qdsp6/topology.c +++ b/sound/soc/qcom/qdsp6/topology.c @@ -2,6 +2,7 @@ // Copyright (c) 2020, Linaro Limited #include +#include #include #include #include @@ -305,34 +306,212 @@ audioreach_get_module_array(const struct snd_soc_tplg_private *private) return NULL; } +static bool audioreach_is_raw_private_type(u32 type) +{ + return type == SND_SOC_AR_TPLG_MODULE_CFG_TYPE || + type == SND_SOC_AR_TPLG_CTRL_LINK_CFG_TYPE || + type == SND_SOC_AR_TPLG_GRAPH_CAL_CFG_TYPE || + type == SND_SOC_AR_TPLG_RENDER_EP_CFG_TYPE || + type == SND_SOC_AR_TPLG_SP_TAG_CFG_TYPE || + type == SND_SOC_AR_TPLG_SPVI_TAG_CFG_TYPE || + type == SND_SOC_AR_TPLG_VI_EP_CFG_TYPE || + type == SND_SOC_AR_TPLG_PROTECTION_DYNAMIC_CFG_TYPE || + type == SND_SOC_AR_TPLG_VOLUME_GAIN_CFG_TYPE || + type == SND_SOC_AR_TPLG_VOLUME_FILTER_CFG_TYPE || + type == SND_SOC_AR_TPLG_VOLUME_MUTE_CFG_TYPE || + type == SND_SOC_AR_TPLG_CHANNEL_MIXER_CFG_TYPE; +} + static struct audioreach_module_priv_data * -audioreach_get_module_priv_data(const struct snd_soc_tplg_private *private) +audioreach_get_module_priv_data(const struct snd_soc_tplg_private *private, + u32 requested_type) { - int sz; + size_t private_size = le32_to_cpu(private->size); + size_t sz; - for (sz = 0; sz < le32_to_cpu(private->size); ) { + for (sz = 0; sz < private_size; ) { const struct snd_soc_tplg_vendor_array *mod_array; + size_t array_size, remaining = private_size - sz; + u32 type; mod_array = (struct snd_soc_tplg_vendor_array *)((u8 *)private->array + sz); - if (le32_to_cpu(mod_array->type) == SND_SOC_AR_TPLG_MODULE_CFG_TYPE) { + if (remaining < sizeof(*mod_array)) + return ERR_PTR(-EINVAL); + + array_size = le32_to_cpu(mod_array->size); + type = le32_to_cpu(mod_array->type); + if (audioreach_is_raw_private_type(type)) { struct audioreach_module_priv_data *pdata; + size_t block_size; + + if (check_add_overflow(sizeof(*pdata), array_size, &block_size) || + block_size > remaining) + return ERR_PTR(-EINVAL); + + if (type != requested_type) { + sz += block_size; + continue; + } pdata = kzalloc_flex(*pdata, data, - le32_to_cpu(mod_array->size)); + array_size); if (!pdata) return ERR_PTR(-ENOMEM); - memcpy(pdata, ((u8 *)private->data + sz), struct_size(pdata, data, - le32_to_cpu(mod_array->size))); + memcpy(pdata, (u8 *)private->data + sz, block_size); return pdata; } - sz = sz + le32_to_cpu(mod_array->size); + if (array_size < sizeof(*mod_array) || array_size > remaining) + return ERR_PTR(-EINVAL); + sz += array_size; } return NULL; } +static int audioreach_validate_ctrl_links(const struct audioreach_module_priv_data *pdata) +{ + size_t size = le32_to_cpu(pdata->size); + const u8 *cursor = (const u8 *)pdata->data; + const u8 *end = cursor + size; + u32 links, link, property; + + if (size < sizeof(u32)) + return -EINVAL; + + links = get_unaligned_le32(cursor); + cursor += sizeof(u32); + for (link = 0; link < links; link++) { + u32 properties; + + if (end - cursor < 5 * sizeof(u32)) + return -EINVAL; + properties = get_unaligned_le32(cursor + 4 * sizeof(u32)); + cursor += 5 * sizeof(u32); + + for (property = 0; property < properties; property++) { + u32 property_size; + + if (end - cursor < 2 * sizeof(u32)) + return -EINVAL; + property_size = get_unaligned_le32(cursor + sizeof(u32)); + cursor += 2 * sizeof(u32); + if (property_size > (size_t)(end - cursor)) + return -EINVAL; + cursor += property_size; + } + } + + return cursor == end ? 0 : -EINVAL; +} + +static int audioreach_validate_param_frames(const struct audioreach_module_priv_data *pdata) +{ + size_t size = le32_to_cpu(pdata->size); + const u8 *cursor = (const u8 *)pdata->data; + const u8 *end = cursor + size; + + if (!size || !IS_ALIGNED(size, 8)) + return -EINVAL; + + while (cursor < end) { + size_t frame_size; + u32 param_size; + + if (end - cursor < sizeof(struct apm_module_param_data)) + return -EINVAL; + param_size = get_unaligned_le32(cursor + 2 * sizeof(u32)); + if (!param_size) + return -EINVAL; + if (check_add_overflow(sizeof(struct apm_module_param_data), + (size_t)param_size, &frame_size)) + return -EINVAL; + frame_size = ALIGN(frame_size, 8); + if (frame_size > end - cursor) + return -EINVAL; + if (get_unaligned_le32(cursor + 3 * sizeof(u32))) + return -EINVAL; + cursor += frame_size; + } + + return cursor == end ? 0 : -EINVAL; +} + +static void audioreach_free_protected_data(struct audioreach_module *mod) +{ + kfree(mod->graph_cal_data); + kfree(mod->render_ep_data); + kfree(mod->sp_tag_data); + kfree(mod->spvi_tag_data); + kfree(mod->vi_ep_data); + kfree(mod->protection_dynamic_data); + kfree(mod->volume_gain_data); + kfree(mod->volume_filter_data); + kfree(mod->volume_mute_data); + kfree(mod->channel_mixer_data); + mod->graph_cal_data = NULL; + mod->render_ep_data = NULL; + mod->sp_tag_data = NULL; + mod->spvi_tag_data = NULL; + mod->vi_ep_data = NULL; + mod->protection_dynamic_data = NULL; + mod->volume_gain_data = NULL; + mod->volume_filter_data = NULL; + mod->volume_mute_data = NULL; + mod->channel_mixer_data = NULL; +} + +static int audioreach_load_protected_data( + struct audioreach_module *mod, + const struct snd_soc_tplg_private *private) +{ + static const u32 types[] = { + SND_SOC_AR_TPLG_GRAPH_CAL_CFG_TYPE, + SND_SOC_AR_TPLG_RENDER_EP_CFG_TYPE, + SND_SOC_AR_TPLG_SP_TAG_CFG_TYPE, + SND_SOC_AR_TPLG_SPVI_TAG_CFG_TYPE, + SND_SOC_AR_TPLG_VI_EP_CFG_TYPE, + SND_SOC_AR_TPLG_PROTECTION_DYNAMIC_CFG_TYPE, + SND_SOC_AR_TPLG_VOLUME_GAIN_CFG_TYPE, + SND_SOC_AR_TPLG_VOLUME_FILTER_CFG_TYPE, + SND_SOC_AR_TPLG_VOLUME_MUTE_CFG_TYPE, + SND_SOC_AR_TPLG_CHANNEL_MIXER_CFG_TYPE, + }; + struct audioreach_module_priv_data **destinations[] = { + &mod->graph_cal_data, + &mod->render_ep_data, + &mod->sp_tag_data, + &mod->spvi_tag_data, + &mod->vi_ep_data, + &mod->protection_dynamic_data, + &mod->volume_gain_data, + &mod->volume_filter_data, + &mod->volume_mute_data, + &mod->channel_mixer_data, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(types); i++) { + *destinations[i] = + audioreach_get_module_priv_data(private, types[i]); + if (IS_ERR(*destinations[i])) { + int ret = PTR_ERR(*destinations[i]); + + *destinations[i] = NULL; + audioreach_free_protected_data(mod); + return ret; + } + if (*destinations[i] && + audioreach_validate_param_frames(*destinations[i])) { + audioreach_free_protected_data(mod); + return -EINVAL; + } + } + + return 0; +} + static struct audioreach_sub_graph *audioreach_parse_sg_tokens(struct q6apm *apm, const struct snd_soc_tplg_private *private) { @@ -423,6 +602,14 @@ static struct audioreach_container *audioreach_parse_cont_tokens(struct q6apm *a case AR_TKN_U32_CONTAINER_PROC_DOMAIN: cont->proc_domain = le32_to_cpu(cont_elem->value); break; + case AR_TKN_U32_CONTAINER_PARENT_ID: + cont->parent_container_id = le32_to_cpu(cont_elem->value); + cont->has_extended_properties = true; + break; + case AR_TKN_U32_CONTAINER_HEAP_ID: + cont->heap_id = le32_to_cpu(cont_elem->value); + cont->has_extended_properties = true; + break; default: dev_err(apm->dev, "Not a valid token %d for graph\n", cont_elem->token); break; @@ -558,6 +745,14 @@ static struct audioreach_module *audioreach_parse_common_tokens(struct q6apm *ap case AR_TKN_U32_MODULE_DST_IN_PORT_ID7: dst_mod_ip_port_id[7] = le32_to_cpu(mod_elem->value); break; + case AR_TKN_U32_MODULE_SPEAKER_PROTECTION_BYPASS: + mod->speaker_protection_bypass = + !!le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_INTEGRATED_BACKEND_ID: + mod->integrated_backend_id = + le32_to_cpu(mod_elem->value); + break; default: break; @@ -610,12 +805,52 @@ static int audioreach_widget_load_module_common(struct snd_soc_component *compon if (IS_ERR_OR_NULL(mod)) return mod ? PTR_ERR(mod) : -ENODEV; - mod->data = audioreach_get_module_priv_data(&tplg_w->priv); - dobj = &w->dobj; dobj->private = mod; - return 0; + mod->data = audioreach_get_module_priv_data(&tplg_w->priv, + SND_SOC_AR_TPLG_MODULE_CFG_TYPE); + if (IS_ERR(mod->data)) { + int ret = PTR_ERR(mod->data); + + mod->data = NULL; + return ret; + } + + mod->ctrl_link_data = + audioreach_get_module_priv_data(&tplg_w->priv, + SND_SOC_AR_TPLG_CTRL_LINK_CFG_TYPE); + if (IS_ERR(mod->ctrl_link_data)) { + int ret = PTR_ERR(mod->ctrl_link_data); + + kfree(mod->data); + mod->data = NULL; + mod->ctrl_link_data = NULL; + return ret; + } + if (mod->ctrl_link_data) { + int ret = audioreach_validate_ctrl_links(mod->ctrl_link_data); + + if (ret) { + kfree(mod->ctrl_link_data); + mod->ctrl_link_data = NULL; + kfree(mod->data); + mod->data = NULL; + return ret; + } + } + + { + int ret = audioreach_load_protected_data(mod, &tplg_w->priv); + + if (!ret) + return 0; + kfree(mod->ctrl_link_data); + mod->ctrl_link_data = NULL; + kfree(mod->data); + mod->data = NULL; + return ret; + } } static int audioreach_widget_load_enc_dec_cnv(struct snd_soc_component *component, @@ -795,6 +1030,15 @@ static int audioreach_widget_load_buffer(struct snd_soc_component *component, mod_array = audioreach_get_module_array(&tplg_w->priv); switch (mod->module_id) { + case MODULE_ID_WR_SHARED_MEM_EP: + case MODULE_ID_RD_SHARED_MEM_EP: + case MODULE_ID_SH_MEM_PULL_MODE: + /* + * Shared-memory endpoints have no endpoint-specific topology + * tokens. The common loader above has already populated the + * module, subgraph, container and connection metadata. + */ + break; case MODULE_ID_CODEC_DMA_SINK: case MODULE_ID_CODEC_DMA_SOURCE: audioreach_widget_dma_module_load(mod, mod_array); @@ -919,16 +1163,13 @@ static int audioreach_widget_ready(struct snd_soc_component *component, switch (w->id) { case snd_soc_dapm_aif_in: case snd_soc_dapm_aif_out: - audioreach_widget_load_buffer(component, index, w, tplg_w); - break; + return audioreach_widget_load_buffer(component, index, w, tplg_w); case snd_soc_dapm_decoder: case snd_soc_dapm_encoder: case snd_soc_dapm_src: - audioreach_widget_load_enc_dec_cnv(component, index, w, tplg_w); - break; + return audioreach_widget_load_enc_dec_cnv(component, index, w, tplg_w); case snd_soc_dapm_buffer: - audioreach_widget_load_buffer(component, index, w, tplg_w); - break; + return audioreach_widget_load_buffer(component, index, w, tplg_w); case snd_soc_dapm_mixer: return audioreach_widget_load_mixer(component, index, w, tplg_w); case snd_soc_dapm_pga: @@ -972,6 +1213,8 @@ static int audioreach_widget_unload(struct snd_soc_component *scomp, list_del(&mod->node); kfree(mod->data); + kfree(mod->ctrl_link_data); + audioreach_free_protected_data(mod); kfree(mod); /* Graph Info has N sub-graphs, sub-graph has N containers, Container has N Modules */ if (list_empty(&cont->modules_list)) { /* if no modules in the container then remove it */ @@ -1115,12 +1358,14 @@ static void audioreach_connect_sub_graphs(struct q6apm *apm, info->src_mod_op_port_id = 1; info->dst_mod_inst_id = m2->module_instance_id; info->dst_mod_ip_port_id = 2; + info->internal_vmixer_connection = m1->graph_id == m2->graph_id; } else { info->src_mod_inst_id = 0; info->src_mod_op_port_id = 0; info->dst_mod_inst_id = 0; info->dst_mod_ip_port_id = 0; + info->internal_vmixer_connection = false; } } @@ -1199,8 +1444,29 @@ static int audioreach_put_vol_ctrl_audio_mixer(struct snd_kcontrol *kcontrol, { struct snd_soc_dapm_widget *dw = snd_soc_dapm_kcontrol_to_widget(kcontrol); struct audioreach_module *mod = dw->dobj.private; + struct snd_soc_component *c = snd_soc_dapm_to_component(dw->dapm); + struct q6apm *apm = dev_get_drvdata(c->dev); + int vol = ucontrol->value.integer.value[0]; + + if (mod->gain == vol) + return 0; - mod->gain = ucontrol->value.integer.value[0]; + mod->gain = vol; + + /* + * 2026-07-31: upstream stores the value here and returns, so nothing is + * ever sent to the DSP. audioreach_gain_set_vol_ctrl() is only called + * from audioreach_pga_event() on POST_PMU, meaning DSP gain is fixed at + * whatever mod->gain held when the widget powered up, and every later + * userspace volume change is silently dropped. + * + * Push the new gain through immediately, but only while the widget is + * powered: sending SET_CFG for a module that has no live graph instance + * fails and would spam the log on every volume change at idle. When the + * widget is off, the stored value is applied by the POST_PMU path. + */ + if (dw->power) + audioreach_gain_set_vol_ctrl(apm, mod, vol); return 1; } diff --git a/sound/soc/qcom/x1e80100.c b/sound/soc/qcom/x1e80100.c index c81df41ace8839..0a2f1193d5337e 100644 --- a/sound/soc/qcom/x1e80100.c +++ b/sound/soc/qcom/x1e80100.c @@ -6,18 +6,27 @@ #include #include #include +#include #include #include #include #include "common.h" #include "qdsp6/q6afe.h" +#include "qdsp6/q6apm.h" #include "qdsp6/q6dsp-common.h" #include "sdw.h" +struct x1e80100_snd_cfg { + const char *driver_name; + const unsigned int *channels_map; + int channels_num; +}; + struct x1e80100_snd_data { bool stream_prepared[AFE_PORT_MAX]; struct snd_soc_card *card; + const struct x1e80100_snd_cfg *cfg; struct snd_soc_jack jack; struct snd_soc_jack dp_jack[8]; bool jack_setup; @@ -35,21 +44,35 @@ static int x1e80100_snd_init(struct snd_soc_pcm_runtime *rtd) case WSA_CODEC_DMA_RX_0: case WSA_CODEC_DMA_RX_1: /* - * Set limit of -3 dB on Digital Volume and 0 dB on PA Volume - * to reduce the risk of speaker damage until we have active - * speaker protection in place. + * PA Volume limit REMOVED 2026-08-01. The control now exposes the + * full hardware range, 0..31 (-9 dB .. +37.5 dB, 1.5 dB steps). + * + * Upstream capped this at 6 (0 dB) "to reduce the risk of speaker + * damage until we have active speaker protection in place". Both + * the author and reviewer of that series said the cap should go + * once protection exists. On this machine it does, verified live: + * SP 0x4027 + SP_VI 0x4024 enabled with VI feedback at 8 kHz on + * both amps, R0/T0 byte-identical to Windows, 106/107 calibration + * frames accepted, 20 protection stages accepted at graph start. + * + * WARNING: protection limits excursion and coil temperature. It + * does NOT make arbitrary levels safe on 4 ohm micro-speakers. + * Sustained operation near the top of this range will damage them. + * The operating point is set independently in UCM (SP11-HiFi.conf), + * currently 24 (+27 dB). Do not confuse that PA control with the + * codec's separate PA_AUX setting when comparing deployments. + * + * Digital Volume stays capped at 81 (-3 dB) as upstream, and is the + * runtime knob for fine adjustment in 1 dB steps. */ snd_soc_limit_volume(card, "WSA WSA_RX0 Digital Volume", 81); snd_soc_limit_volume(card, "WSA WSA_RX1 Digital Volume", 81); snd_soc_limit_volume(card, "WSA2 WSA_RX0 Digital Volume", 81); snd_soc_limit_volume(card, "WSA2 WSA_RX1 Digital Volume", 81); - snd_soc_limit_volume(card, "SpkrLeft PA Volume", 6); - snd_soc_limit_volume(card, "SpkrRight PA Volume", 6); - snd_soc_limit_volume(card, "WooferLeft PA Volume", 6); - snd_soc_limit_volume(card, "TweeterLeft PA Volume", 6); - snd_soc_limit_volume(card, "WooferRight PA Volume", 6); - snd_soc_limit_volume(card, "TweeterRight PA Volume", 6); break; + case WSA_CODEC_DMA_TX_0: + case WSA_CODEC_DMA_TX_1: + return 0; case DISPLAY_PORT_RX_0: dp_pcm_id = 0; dp_jack = &data->dp_jack[dp_pcm_id]; @@ -76,6 +99,8 @@ static int x1e80100_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, SNDRV_PCM_HW_PARAM_RATE); struct snd_interval *channels = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); + struct snd_mask *format = hw_param_mask(params, + SNDRV_PCM_HW_PARAM_FORMAT); rate->min = rate->max = 48000; switch (cpu_dai->id) { @@ -85,6 +110,20 @@ static int x1e80100_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, case TX_CODEC_DMA_TX_3: channels->min = 1; break; + case WSA_CODEC_DMA_TX_0: + rate->min = rate->max = 8000; + channels->min = channels->max = 2; + snd_mask_none(format); + snd_mask_set_format(format, SNDRV_PCM_FORMAT_S32_LE); + break; + case WSA_CODEC_DMA_TX_1: + rate->min = 24000; + rate->max = 24000; + channels->min = 2; + channels->max = 2; + snd_mask_none(format); + snd_mask_set_format(format, SNDRV_PCM_FORMAT_S32_LE); + break; default: break; } @@ -92,8 +131,16 @@ static int x1e80100_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, return 0; } -static int x1e80100_snd_hw_map_channels(unsigned int *ch_map, int num) +static int x1e80100_snd_hw_map_channels(struct x1e80100_snd_data *data, + unsigned int *ch_map, int num) { + if (data->cfg->channels_map) { + for (int i = 0; i < data->cfg->channels_num; i++) + ch_map[i] = data->cfg->channels_map[i]; + + return 0; + } + switch (num) { case 1: ch_map[0] = PCM_CHANNEL_FC; @@ -127,12 +174,13 @@ static int x1e80100_snd_prepare(struct snd_pcm_substream *substream) struct x1e80100_snd_data *data = snd_soc_card_get_drvdata(rtd->card); unsigned int channels = substream->runtime->channels; unsigned int rx_slot[4]; + unsigned int tx_slot[4]; int ret; switch (cpu_dai->id) { case WSA_CODEC_DMA_RX_0: case WSA_CODEC_DMA_RX_1: - ret = x1e80100_snd_hw_map_channels(rx_slot, channels); + ret = x1e80100_snd_hw_map_channels(data, rx_slot, channels); if (ret) return ret; @@ -141,11 +189,46 @@ static int x1e80100_snd_prepare(struct snd_pcm_substream *substream) if (ret) return ret; break; + case WSA_CODEC_DMA_TX_0: + case WSA_CODEC_DMA_TX_1: + ret = x1e80100_snd_hw_map_channels(data, tx_slot, channels); + if (ret) + return ret; + + ret = snd_soc_dai_set_channel_map(cpu_dai, channels, tx_slot, + 0, NULL); + if (ret) + return ret; + break; default: break; } - return qcom_snd_sdw_prepare(substream, &data->stream_prepared[cpu_dai->id]); + ret = qcom_snd_sdw_prepare(substream, + &data->stream_prepared[cpu_dai->id]); + if (cpu_dai->id == WSA_CODEC_DMA_TX_0) { + q6apm_sp11_set_vi_ready(ret == 0); + dev_info(rtd->dev, "SP11 VI feedback %s\n", + ret ? "unavailable; protection will bypass" : + "ready on WSA_CODEC_DMA_TX_0"); + /* + * VI is a protection sidechain, not the render transport. + * Keep playback available if its SoundWire allocation fails; + * the frontend will explicitly bypass SP/SPVI before start. + */ + if (ret) + return 0; + } + if (cpu_dai->id == WSA_CODEC_DMA_TX_1) { + q6apm_sp11_set_cps_ready(ret == 0); + dev_info(rtd->dev, "SP11 CPS feedback %s\n", + ret ? "unavailable; protection will bypass" : + "ready on WSA_CODEC_DMA_TX_1"); + if (ret) + return 0; + } + + return ret; } static int x1e80100_snd_hw_free(struct snd_pcm_substream *substream) @@ -154,6 +237,11 @@ static int x1e80100_snd_hw_free(struct snd_pcm_substream *substream) struct x1e80100_snd_data *data = snd_soc_card_get_drvdata(rtd->card); struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); + if (cpu_dai->id == WSA_CODEC_DMA_TX_0) + q6apm_sp11_set_vi_ready(false); + else if (cpu_dai->id == WSA_CODEC_DMA_TX_1) + q6apm_sp11_set_cps_ready(false); + return qcom_snd_sdw_hw_free(substream, &data->stream_prepared[cpu_dai->id]); } @@ -202,15 +290,39 @@ static int x1e80100_platform_probe(struct platform_device *pdev) if (ret) return ret; - card->driver_name = of_device_get_match_data(dev); + data->cfg = of_device_get_match_data(dev); + + card->driver_name = data->cfg->driver_name; x1e80100_add_be_ops(card); return devm_snd_soc_register_card(dev, card); } +static const struct x1e80100_snd_cfg x1e80100_cfg = { + .driver_name = "x1e80100", +}; + +static const struct x1e80100_snd_cfg glymur_cfg = { + .driver_name = "glymur", +}; + +static const unsigned int right_left_4_channels_map[] = { + PCM_CHANNEL_FR, + PCM_CHANNEL_RB, + PCM_CHANNEL_FL, + PCM_CHANNEL_LB, +}; + +static const struct x1e80100_snd_cfg dell_xps13_9345_cfg = { + .driver_name = "x1e80100", + .channels_map = right_left_4_channels_map, + .channels_num = ARRAY_SIZE(right_left_4_channels_map), +}; + static const struct of_device_id snd_x1e80100_dt_match[] = { - { .compatible = "qcom,x1e80100-sndcard", .data = "x1e80100" }, - { .compatible = "qcom,glymur-sndcard", .data = "glymur" }, + { .compatible = "qcom,x1e80100-sndcard", .data = &x1e80100_cfg, }, + { .compatible = "dell,xps13-9345-sndcard", .data = &dell_xps13_9345_cfg, }, + { .compatible = "qcom,glymur-sndcard", .data = &glymur_cfg, }, {} }; MODULE_DEVICE_TABLE(of, snd_x1e80100_dt_match); diff --git a/tools/hv/hv_kvp_daemon.8 b/tools/hv/hv_kvp_daemon.8 new file mode 100644 index 00000000000000..0fb4577a1f072e --- /dev/null +++ b/tools/hv/hv_kvp_daemon.8 @@ -0,0 +1,26 @@ +.\" This page Copyright (C) 2012 Andy Whitcroft +.\" Distributed under the GPL v2 or later. +.TH HV_KVP_DAEMON 8 +.SH NAME +hv_kvp_daemon \- Hyper-V Key Value Pair daemon +.SH SYNOPSIS +.ft B +.B hv_kvp_daemon +.br +.SH DESCRIPTION +\fBhv_kvp_daemon\fP +is the userspace component of the Hyper-V key value pair functionality, +communicating via a netlink socket with the kernel HV-KVP driver. +This pairing allows the Hyper-V host to pass configuration information +(such as IP addresses) to the guest and allows the host to obtain guest +version information. + +.SH FILES +.ta +.nf +/var/opt/hyperv/.kvp_pool_* +.fi + +.SH AUTHORS +.nf +Written by K. Y. Srinivasan diff --git a/tools/hv/lsvmbus.8 b/tools/hv/lsvmbus.8 new file mode 100644 index 00000000000000..ba07d664950ebc --- /dev/null +++ b/tools/hv/lsvmbus.8 @@ -0,0 +1,23 @@ +.\" This page Copyright (C) 2016 Andy Whitcroft +.\" Distributed under the GPL v2 or later. +.TH LSVMBUS 8 +.SH NAME +lsvmbus \- List Hyper-V VMBus devices +.SH SYNOPSIS +.ft B +.B lsvmbus [-vv] +.br +.SH DESCRIPTION +\fBlsvmbus\fP +displays devices attached to the Hyper-V VMBus. +.SH OPTIONS +.\" +.TP +.B -v +With -v more information is printed including the VMBus Rel_ID, class ID, +Rel_ID, and which channel is bound to which virtual processor. Use -vv +for additional detail including the Device_ID and the sysfs path. +.\" +.SH AUTHORS +.nf +Written by Dexuan Cui diff --git a/tools/objtool/check.c b/tools/objtool/check.c index f03dd59e7fca18..4d4caf17474281 100644 --- a/tools/objtool/check.c +++ b/tools/objtool/check.c @@ -4208,7 +4208,10 @@ static int validate_retpoline(struct objtool_file *file) } } - return warnings; + /* RETPOLINE is an optional security safety feature, make it + * fatal to ensure no new code is introduced that fails + * RETPOLINE */ + return -warnings; } static bool is_kasan_insn(struct instruction *insn) @@ -4699,7 +4702,9 @@ static int validate_sls(struct objtool_file *file) } } - return warnings; + /* SLS is an optional security safety feature, make it fatal + * to ensure no new code is introduced that fails SLS */ + return -warnings; } static int validate_reachable_instructions(struct objtool_file *file) diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 0ba307e78fe1f3..5660e0f1043b4b 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -884,6 +884,11 @@ ifneq ($(NO_JEVENTS),1) endif endif +ifdef HAVE_NO_LIBBFD + feature-libbfd := 0 + $(info libbfd overidden OFF) +else + ifdef BUILD_NONDISTRO # call all detections now so we get correct status in VF output $(call feature_check,libbfd) @@ -920,6 +925,8 @@ ifdef BUILD_NONDISTRO endif endif +endif + ifndef NO_LIBLLVM $(call feature_check,llvm-perf) ifeq ($(feature-llvm-perf), 1) @@ -1145,7 +1152,7 @@ ifndef NO_RUST RUST_TARGET_FLAGS_m68k := m68k-unknown-linux-gnu RUST_TARGET_FLAGS_mips := mipsel-unknown-linux-gnu RUST_TARGET_FLAGS_powerpc := powerpc64le-unknown-linux-gnu - RUST_TARGET_FLAGS_riscv := riscv64gc-unknown-linux-gnu + RUST_TARGET_FLAGS_riscv := riscv64a23-unknown-linux-gnu RUST_TARGET_FLAGS_s390 := s390x-unknown-linux-gnu RUST_TARGET_FLAGS_x86 := x86_64-unknown-linux-gnu RUST_TARGET_FLAGS_x86_64 := x86_64-unknown-linux-gnu diff --git a/tools/testing/selftests/ftrace/test.d/trigger/trigger-trace-marker-snapshot.tc b/tools/testing/selftests/ftrace/test.d/trigger/trigger-trace-marker-snapshot.tc index 27da2dba9b9e32..e954bc8d254c7d 100644 --- a/tools/testing/selftests/ftrace/test.d/trigger/trigger-trace-marker-snapshot.tc +++ b/tools/testing/selftests/ftrace/test.d/trigger/trigger-trace-marker-snapshot.tc @@ -14,12 +14,12 @@ test_trace() { x=$2 cat $file | while read line; do - comment=`echo $line | sed -e 's/^#//'` + comment=`echo "$line" | sed -e 's/^#//'` if [ "$line" != "$comment" ]; then continue fi echo "testing $line for >$x<" - match=`echo $line | sed -e "s/>$x$x$x< in it" fi diff --git a/tools/testing/selftests/kselftest/runner.sh b/tools/testing/selftests/kselftest/runner.sh index 311811dc55a074..4b59d34b36d2ce 100644 --- a/tools/testing/selftests/kselftest/runner.sh +++ b/tools/testing/selftests/kselftest/runner.sh @@ -39,7 +39,7 @@ tap_prefix() tap_timeout() { # Make sure tests will time out if utility is available. - if [ -x /usr/bin/timeout ] ; then + if [ -x /usr/bin/timeout ] && [ $kselftest_timeout -gt 0 ] ; then /usr/bin/timeout --foreground "$kselftest_timeout" \ /usr/bin/timeout "$kselftest_timeout" $1 else diff --git a/tools/testing/selftests/memory-hotplug/settings b/tools/testing/selftests/memory-hotplug/settings new file mode 100644 index 00000000000000..a62d2fa1275c6b --- /dev/null +++ b/tools/testing/selftests/memory-hotplug/settings @@ -0,0 +1 @@ +timeout=600 diff --git a/tools/testing/selftests/net/settings b/tools/testing/selftests/net/settings index ed8418e8217a09..e7b9417537fbc4 100644 --- a/tools/testing/selftests/net/settings +++ b/tools/testing/selftests/net/settings @@ -1 +1 @@ -timeout=3600 +timeout=0 diff --git a/tools/testing/selftests/net/socket.c b/tools/testing/selftests/net/socket.c index 9e270548dad804..01a46db066c873 100644 --- a/tools/testing/selftests/net/socket.c +++ b/tools/testing/selftests/net/socket.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "kselftest.h" @@ -26,7 +27,10 @@ struct socket_testcase { }; static struct socket_testcase tests[] = { - { AF_MAX, 0, 0, -EAFNOSUPPORT, 0 }, + /* libc might have a smaller value of AF_MAX than the kernel + * actually supports, so use INT_MAX instead. + */ + { INT_MAX, 0, 0, -EAFNOSUPPORT, 0 }, { AF_INET, SOCK_STREAM, IPPROTO_TCP, 0, 1 }, { AF_INET, SOCK_DGRAM, IPPROTO_TCP, -EPROTONOSUPPORT, 1 }, { AF_INET, SOCK_DGRAM, IPPROTO_UDP, 0, 1 }, diff --git a/tools/testing/selftests/net/tls.c b/tools/testing/selftests/net/tls.c index 9d3cd4fff062b5..0c160f24987a9f 100644 --- a/tools/testing/selftests/net/tls.c +++ b/tools/testing/selftests/net/tls.c @@ -468,64 +468,6 @@ TEST_F(tls, send_then_sendfile) close(filefd); } -static void chunked_sendfile(struct __test_metadata *_metadata, - struct _test_data_tls *self, - uint16_t chunk_size, - uint16_t extra_payload_size) -{ - char buf[TLS_PAYLOAD_MAX_LEN]; - uint16_t test_payload_size; - int size = 0; - int ret; - char filename[] = "/tmp/mytemp.XXXXXX"; - int fd = mkstemp(filename); - off_t offset = 0; - - unlink(filename); - ASSERT_GE(fd, 0); - EXPECT_GE(chunk_size, 1); - test_payload_size = chunk_size + extra_payload_size; - ASSERT_GE(TLS_PAYLOAD_MAX_LEN, test_payload_size); - memset(buf, 1, test_payload_size); - size = write(fd, buf, test_payload_size); - EXPECT_EQ(size, test_payload_size); - fsync(fd); - - while (size > 0) { - ret = sendfile(self->fd, fd, &offset, chunk_size); - EXPECT_GE(ret, 0); - size -= ret; - } - - EXPECT_EQ(recv(self->cfd, buf, test_payload_size, MSG_WAITALL), - test_payload_size); - - close(fd); -} - -TEST_F(tls, multi_chunk_sendfile) -{ - chunked_sendfile(_metadata, self, 4096, 4096); - chunked_sendfile(_metadata, self, 4096, 0); - chunked_sendfile(_metadata, self, 4096, 1); - chunked_sendfile(_metadata, self, 4096, 2048); - chunked_sendfile(_metadata, self, 8192, 2048); - chunked_sendfile(_metadata, self, 4096, 8192); - chunked_sendfile(_metadata, self, 8192, 4096); - chunked_sendfile(_metadata, self, 12288, 1024); - chunked_sendfile(_metadata, self, 12288, 2000); - chunked_sendfile(_metadata, self, 15360, 100); - chunked_sendfile(_metadata, self, 15360, 300); - chunked_sendfile(_metadata, self, 1, 4096); - chunked_sendfile(_metadata, self, 2048, 4096); - chunked_sendfile(_metadata, self, 2048, 8192); - chunked_sendfile(_metadata, self, 4096, 8192); - chunked_sendfile(_metadata, self, 1024, 12288); - chunked_sendfile(_metadata, self, 2000, 12288); - chunked_sendfile(_metadata, self, 100, 15360); - chunked_sendfile(_metadata, self, 300, 15360); -} - TEST_F(tls, recv_max) { unsigned int send_len = TLS_PAYLOAD_MAX_LEN; diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile index 59ca01d8567e23..d3de9b76b9c514 100644 --- a/tools/testing/selftests/powerpc/ptrace/Makefile +++ b/tools/testing/selftests/powerpc/ptrace/Makefile @@ -34,7 +34,7 @@ TESTS_64 := $(patsubst %,$(OUTPUT)/%,$(TESTS_64)) $(TESTS_64): CFLAGS += -m64 $(TM_TESTS): CFLAGS += -I../tm -mhtm -CFLAGS += $(KHDR_INCLUDES) -fno-pie +CFLAGS += $(KHDR_INCLUDES) -fno-pie -Wno-error=deprecated $(OUTPUT)/ptrace-gpr: ptrace-gpr.S $(OUTPUT)/ptrace-perf-hwbreak: ptrace-perf-asm.S diff --git a/tools/testing/selftests/seccomp/settings b/tools/testing/selftests/seccomp/settings index a953c96aa16e1e..694d70710ff08a 100644 --- a/tools/testing/selftests/seccomp/settings +++ b/tools/testing/selftests/seccomp/settings @@ -1 +1 @@ -timeout=180 +timeout=300 diff --git a/tools/testing/selftests/timers/rtcpie.c b/tools/testing/selftests/timers/rtcpie.c index 4ba42d198b7ecf..990facb06e5db8 100644 --- a/tools/testing/selftests/timers/rtcpie.c +++ b/tools/testing/selftests/timers/rtcpie.c @@ -111,11 +111,11 @@ int main(int argc, char **argv) timersub(&end, &start, &diff); if (diff.tv_sec > 0 || diff.tv_usec > ((1000000L / tmp) * 1.10)) { - fprintf(stderr, "\nPIE delta error: %ld.%06ld should be close to 0.%06ld\n", + fprintf(stderr, "\nUbuntu Testing Force Pass LP #1814234: PIE delta error: %ld.%06ld should be close to 0.%06ld\n", diff.tv_sec, diff.tv_usec, (1000000L / tmp)); fflush(stdout); - exit(-1); + break; // LP: #1814234 } fprintf(stderr, " %d",i); diff --git a/tools/usb/usbip/configure.ac b/tools/usb/usbip/configure.ac index 8debf934f8b79c..ef74eb7e56684d 100644 --- a/tools/usb/usbip/configure.ac +++ b/tools/usb/usbip/configure.ac @@ -18,7 +18,7 @@ LT_INIT # Silent build for automake >= 1.11 m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])]) -AC_SUBST([EXTRA_CFLAGS], ["-Wall -Werror -Wextra -std=gnu99"]) +AC_SUBST([EXTRA_CFLAGS], ["-Wall -Werror -Wextra -Wno-address-of-packed-member -std=gnu99"]) # Checks for programs. AC_PROG_CC diff --git a/ubuntu/Kconfig b/ubuntu/Kconfig new file mode 100644 index 00000000000000..78204b35cddef0 --- /dev/null +++ b/ubuntu/Kconfig @@ -0,0 +1,28 @@ +menu "Ubuntu Supplied Third-Party Device Drivers" + + +config UBUNTU_ODM_DRIVERS + bool "Ubuntu ODM supplied drivers" + help + Turn on support for Ubuntu ODM supplied drivers + +# +# NOTE: to allow drivers to be added and removed without causing merge +# collisions you should add new entries in the middle of the six lines +# of ## at the bottom of the list. Always add three lines of ## above +# your new entry and maintain the six lines below. +# + +## +## +## +source "ubuntu/ubuntu-host/Kconfig" +## +## +## +source "ubuntu/igh-ecat/Kconfig" +## +## +## + +endmenu diff --git a/ubuntu/Makefile b/ubuntu/Makefile new file mode 100644 index 00000000000000..b1efc1732b3b14 --- /dev/null +++ b/ubuntu/Makefile @@ -0,0 +1,22 @@ +# +# Makefile for the Linux kernel ubuntu supplied third-party device drivers. +# + +# +# NOTE: to allow drivers to be added and removed without causing merge +# collisions you should add new entries in the middle of the six lines +# of ## at the bottom of the list. Always add three lines of ## above +# your new entry and maintain the six lines below. +# + +## +## +## +obj-$(CONFIG_UBUNTU_HOST) += ubuntu-host/ +## +## +## +obj-$(CONFIG_IGH_ECAT) += igh-ecat/ +## +## +## diff --git a/ubuntu/hio/Makefile b/ubuntu/hio/Makefile new file mode 100644 index 00000000000000..b03e6273a127d7 --- /dev/null +++ b/ubuntu/hio/Makefile @@ -0,0 +1,69 @@ +ifneq ($(KERNELRELEASE),) +# hio-y := hio_main.o +# obj-$(CONFIG_HIO_DRIVER) += hio.o + obj-m += hio.o +else + +KVER= +ifeq ($(KVER),) + KVER=$(shell uname -r) +endif + +PDIR= +ifeq ($(PDIR),) + PDIR=extra +endif + +PREFIX= + +MODDIR=/lib/modules/$(KVER)/$(PDIR)/hio/ +MOD=hio.ko + +ifeq ($(KVER),2.6.32-300.3.1.el6uek.x86_64) + FLAGS += -DSSD_QUEUE_PBIO +endif +ifeq ($(KVER),2.6.32-220.el6.x86_64) + FLAGS += -DSSD_QUEUE_PBIO +endif +ifeq ($(KVER),2.6.32-358.el6.x86_64) + FLAGS += -DSSD_QUEUE_PBIO +endif +ifeq ($(KVER),2.6.32-358.23.2.el6.x86_64) + FLAGS += -DSSD_QUEUE_PBIO +endif +ifeq ($(KVER),3.0.58-0.6.6-xen) + FLAGS += -DSSD_QUEUE_PBIO +endif +ifeq ($(KVER),3.2.0-4-amd64) + FLAGS += -DSSD_BIOVEC_PHYS_MERGEABLE_FIXED +endif +ifeq ($(KVER),2.6.39-400.209.1.el5uek) #Oracle Linux Server release 5.10 + FLAGS += -DSSD_BIOVEC_PHYS_MERGEABLE_FIXED +endif +ifeq ($(KVER),2.6.39-400.215.10.el5uek) #Oracle Linux Server release 5.11 + FLAGS += -DSSD_BIOVEC_PHYS_MERGEABLE_FIXED +endif +ifeq ($(KVER),2.6.39-200.24.1.el6uek.x86_64) #Oracle Linux Server release 6.3 + FLAGS += -DSSD_BIOVEC_PHYS_MERGEABLE_FIXED +endif +ifeq ($(KVER),2.6.39-400.17.1.el6uek.x86_64) #Oracle Linux Server release 6.4 + FLAGS += -DSSD_BIOVEC_PHYS_MERGEABLE_FIXED +endif + + +KERNELDIR ?= /lib/modules/$(KVER)/build +PWD := $(shell pwd) + +default: + $(MAKE) -C $(KERNELDIR) M=$(PWD) EXTRA_CFLAGS="$(FLAGS)" modules +clean: + rm -rf *.o *~ core .depend .*.cmd *.ko *.mod.c .tmp_versions Module.* + +install: default + mkdir -p $(PREFIX)/$(MODDIR) + install -m 444 $(MOD) $(PREFIX)/$(MODDIR) + @if [ "$(PREFIX)" = "" ]; then /sbin/depmod -a ;\ + else echo " *** Run 'depmod -a' to update the module database.";\ + fi +endif + diff --git a/ubuntu/hio/hio.c b/ubuntu/hio/hio.c new file mode 100644 index 00000000000000..4ea98d8647f347 --- /dev/null +++ b/ubuntu/hio/hio.c @@ -0,0 +1,12527 @@ +/* +* Huawei SSD device driver +* Copyright (c) 2016, Huawei Technologies Co., Ltd. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ + +#ifndef LINUX_VERSION_CODE +#include +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* HDIO_GETGEO */ +#include +#include +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) +#include +#endif +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,2,0)) +#include +#include +#else +#include +#endif +#include +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)) +#include +#endif + +/* driver */ +#define MODULE_NAME "hio" +#define DRIVER_VERSION "2.1.0.23" +#define DRIVER_VERSION_LEN 16 + +#define SSD_FW_MIN 0x1 + +#define SSD_DEV_NAME MODULE_NAME +#define SSD_DEV_NAME_LEN 16 +#define SSD_CDEV_NAME "c"SSD_DEV_NAME +#define SSD_SDEV_NAME "s"SSD_DEV_NAME + + +#define SSD_CMAJOR 0 +#define SSD_MAJOR 0 +#define SSD_MAJOR_SL 0 +#define SSD_MINORS 16 + +#define SSD_MAX_DEV 702 +#define SSD_ALPHABET_NUM 26 + +#define hio_info(f, arg...) printk(KERN_INFO MODULE_NAME"info: " f , ## arg) +#define hio_note(f, arg...) printk(KERN_NOTICE MODULE_NAME"note: " f , ## arg) +#define hio_warn(f, arg...) printk(KERN_WARNING MODULE_NAME"warn: " f , ## arg) +#define hio_err(f, arg...) printk(KERN_ERR MODULE_NAME"err: " f , ## arg) + +/* slave port */ +#define SSD_SLAVE_PORT_DEVID 0x000a + +/* int mode */ + +/* 2.6.9 msi affinity bug, should turn msi & msi-x off */ +//#define SSD_MSI +#define SSD_ESCAPE_IRQ + +//#define SSD_MSIX +#ifndef MODULE +#define SSD_MSIX +#endif +#define SSD_MSIX_VEC 8 +#ifdef SSD_MSIX +#undef SSD_MSI +//#undef SSD_ESCAPE_IRQ +#define SSD_MSIX_AFFINITY_FORCE +#endif + +#define SSD_TRIM + +/* Over temperature protect */ +#define SSD_OT_PROTECT + +#ifdef SSD_QUEUE_PBIO +#define BIO_SSD_PBIO 20 +#endif + +/* debug */ +//#define SSD_DEBUG_ERR + +/* cmd timer */ +#define SSD_CMD_TIMEOUT (60*HZ) + +/* i2c & smbus */ +#define SSD_SPI_TIMEOUT (5*HZ) +#define SSD_I2C_TIMEOUT (5*HZ) + +#define SSD_I2C_MAX_DATA (127) +#define SSD_SMBUS_BLOCK_MAX (32) +#define SSD_SMBUS_DATA_MAX (SSD_SMBUS_BLOCK_MAX + 2) + +/* wait for init */ +#define SSD_INIT_WAIT (1000) //1s +#define SSD_CONTROLLER_WAIT (20*1000/SSD_INIT_WAIT) //20s +#define SSD_INIT_MAX_WAIT (500*1000/SSD_INIT_WAIT) //500s +#define SSD_INIT_MAX_WAIT_V3_2 (1400*1000/SSD_INIT_WAIT) //1400s +#define SSD_RAM_INIT_MAX_WAIT (10*1000/SSD_INIT_WAIT) //10s +#define SSD_CH_INFO_MAX_WAIT (10*1000/SSD_INIT_WAIT) //10s + +/* blkdev busy wait */ +#define SSD_DEV_BUSY_WAIT 1000 //ms +#define SSD_DEV_BUSY_MAX_WAIT (8*1000/SSD_DEV_BUSY_WAIT) //8s + +/* smbus retry */ +#define SSD_SMBUS_RETRY_INTERVAL (5) //ms +#define SSD_SMBUS_RETRY_MAX (1000/SSD_SMBUS_RETRY_INTERVAL) + +#define SSD_BM_RETRY_MAX 7 + +/* bm routine interval */ +#define SSD_BM_CAP_LEARNING_DELAY (10*60*1000) + +/* routine interval */ +#define SSD_ROUTINE_INTERVAL (10*1000) //10s +#define SSD_HWMON_ROUTINE_TICK (60*1000/SSD_ROUTINE_INTERVAL) +#define SSD_CAPMON_ROUTINE_TICK ((3600*1000/SSD_ROUTINE_INTERVAL)*24*30) +#define SSD_CAPMON2_ROUTINE_TICK (10*60*1000/SSD_ROUTINE_INTERVAL) //fault recover + +/* dma align */ +#define SSD_DMA_ALIGN (16) + +/* some hw defalut */ +#define SSD_LOG_MAX_SZ 4096 + +#define SSD_NAND_OOB_SZ 1024 +#define SSD_NAND_ID_SZ 8 +#define SSD_NAND_ID_BUFF_SZ 1024 +#define SSD_NAND_MAX_CE 2 + +#define SSD_BBT_RESERVED 8 + +#define SSD_ECC_MAX_FLIP (64+1) + +#define SSD_RAM_ALIGN 16 + + +#define SSD_RELOAD_FLAG 0x3333CCCC +#define SSD_RELOAD_FW 0xAA5555AA +#define SSD_RESET_NOINIT 0xAA5555AA +#define SSD_RESET 0x55AAAA55 +#define SSD_RESET_FULL 0x5A +//#define SSD_RESET_WAIT 1000 //1s +//#define SSD_RESET_MAX_WAIT (200*1000/SSD_RESET_WAIT) //200s + + +/* reverion 1 */ +#define SSD_PROTOCOL_V1 0x0 + +#define SSD_ROM_SIZE (16*1024*1024) +#define SSD_ROM_BLK_SIZE (256*1024) +#define SSD_ROM_PAGE_SIZE (256) +#define SSD_ROM_NR_BRIDGE_FW 2 +#define SSD_ROM_NR_CTRL_FW 2 +#define SSD_ROM_BRIDGE_FW_BASE 0 +#define SSD_ROM_BRIDGE_FW_SIZE (2*1024*1024) +#define SSD_ROM_CTRL_FW_BASE (SSD_ROM_NR_BRIDGE_FW*SSD_ROM_BRIDGE_FW_SIZE) +#define SSD_ROM_CTRL_FW_SIZE (5*1024*1024) +#define SSD_ROM_LABEL_BASE (SSD_ROM_CTRL_FW_BASE+SSD_ROM_CTRL_FW_SIZE*SSD_ROM_NR_CTRL_FW) +#define SSD_ROM_VP_BASE (SSD_ROM_LABEL_BASE+SSD_ROM_BLK_SIZE) + +/* reverion 3 */ +#define SSD_PROTOCOL_V3 0x3000000 +#define SSD_PROTOCOL_V3_1_1 0x3010001 +#define SSD_PROTOCOL_V3_1_3 0x3010003 +#define SSD_PROTOCOL_V3_2 0x3020000 +#define SSD_PROTOCOL_V3_2_1 0x3020001 /* <4KB improved */ +#define SSD_PROTOCOL_V3_2_2 0x3020002 /* ot protect */ +#define SSD_PROTOCOL_V3_2_4 0x3020004 + + +#define SSD_PV3_ROM_NR_BM_FW 1 +#define SSD_PV3_ROM_BM_FW_SZ (64*1024*8) + +#define SSD_ROM_LOG_SZ (64*1024*4) + +#define SSD_ROM_NR_SMART_MAX 2 +#define SSD_PV3_ROM_NR_SMART SSD_ROM_NR_SMART_MAX +#define SSD_PV3_ROM_SMART_SZ (64*1024) + +/* reverion 3.2 */ +#define SSD_PV3_2_ROM_LOG_SZ (64*1024*80) /* 5MB */ +#define SSD_PV3_2_ROM_SEC_SZ (256*1024) /* 256KB */ + + +/* register */ +#define SSD_REQ_FIFO_REG 0x0000 +#define SSD_RESP_FIFO_REG 0x0008 //0x0010 +#define SSD_RESP_PTR_REG 0x0010 //0x0018 +#define SSD_INTR_INTERVAL_REG 0x0018 +#define SSD_READY_REG 0x001C +#define SSD_BRIDGE_TEST_REG 0x0020 +#define SSD_STRIPE_SIZE_REG 0x0028 +#define SSD_CTRL_VER_REG 0x0030 //controller +#define SSD_BRIDGE_VER_REG 0x0034 //bridge +#define SSD_PCB_VER_REG 0x0038 +#define SSD_BURN_FLAG_REG 0x0040 +#define SSD_BRIDGE_INFO_REG 0x0044 + +#define SSD_WL_VAL_REG 0x0048 //32-bit + +#define SSD_BB_INFO_REG 0x004C + +#define SSD_ECC_TEST_REG 0x0050 //test only +#define SSD_ERASE_TEST_REG 0x0058 //test only +#define SSD_WRITE_TEST_REG 0x0060 //test only + +#define SSD_RESET_REG 0x0068 +#define SSD_RELOAD_FW_REG 0x0070 + +#define SSD_RESERVED_BLKS_REG 0x0074 +#define SSD_VALID_PAGES_REG 0x0078 +#define SSD_CH_INFO_REG 0x007C + +#define SSD_CTRL_TEST_REG_SZ 0x8 +#define SSD_CTRL_TEST_REG0 0x0080 +#define SSD_CTRL_TEST_REG1 0x0088 +#define SSD_CTRL_TEST_REG2 0x0090 +#define SSD_CTRL_TEST_REG3 0x0098 +#define SSD_CTRL_TEST_REG4 0x00A0 +#define SSD_CTRL_TEST_REG5 0x00A8 +#define SSD_CTRL_TEST_REG6 0x00B0 +#define SSD_CTRL_TEST_REG7 0x00B8 + +#define SSD_FLASH_INFO_REG0 0x00C0 +#define SSD_FLASH_INFO_REG1 0x00C8 +#define SSD_FLASH_INFO_REG2 0x00D0 +#define SSD_FLASH_INFO_REG3 0x00D8 +#define SSD_FLASH_INFO_REG4 0x00E0 +#define SSD_FLASH_INFO_REG5 0x00E8 +#define SSD_FLASH_INFO_REG6 0x00F0 +#define SSD_FLASH_INFO_REG7 0x00F8 + +#define SSD_RESP_INFO_REG 0x01B8 +#define SSD_NAND_BUFF_BASE 0x01BC //for nand write + +#define SSD_CHIP_INFO_REG_SZ 0x10 +#define SSD_CHIP_INFO_REG0 0x0100 //128 bit +#define SSD_CHIP_INFO_REG1 0x0110 +#define SSD_CHIP_INFO_REG2 0x0120 +#define SSD_CHIP_INFO_REG3 0x0130 +#define SSD_CHIP_INFO_REG4 0x0140 +#define SSD_CHIP_INFO_REG5 0x0150 +#define SSD_CHIP_INFO_REG6 0x0160 +#define SSD_CHIP_INFO_REG7 0x0170 + +#define SSD_RAM_INFO_REG 0x01C4 + +#define SSD_BBT_BASE_REG 0x01C8 +#define SSD_ECT_BASE_REG 0x01CC + +#define SSD_CLEAR_INTR_REG 0x01F0 + +#define SSD_INIT_STATE_REG_SZ 0x8 +#define SSD_INIT_STATE_REG0 0x0200 +#define SSD_INIT_STATE_REG1 0x0208 +#define SSD_INIT_STATE_REG2 0x0210 +#define SSD_INIT_STATE_REG3 0x0218 +#define SSD_INIT_STATE_REG4 0x0220 +#define SSD_INIT_STATE_REG5 0x0228 +#define SSD_INIT_STATE_REG6 0x0230 +#define SSD_INIT_STATE_REG7 0x0238 + +#define SSD_ROM_INFO_REG 0x0600 +#define SSD_ROM_BRIDGE_FW_INFO_REG 0x0604 +#define SSD_ROM_CTRL_FW_INFO_REG 0x0608 +#define SSD_ROM_VP_INFO_REG 0x060C + +#define SSD_LOG_INFO_REG 0x0610 +#define SSD_LED_REG 0x0614 +#define SSD_MSG_BASE_REG 0x06F8 + +/*spi reg */ +#define SSD_SPI_REG_CMD 0x0180 +#define SSD_SPI_REG_CMD_HI 0x0184 +#define SSD_SPI_REG_WDATA 0x0188 +#define SSD_SPI_REG_ID 0x0190 +#define SSD_SPI_REG_STATUS 0x0198 +#define SSD_SPI_REG_RDATA 0x01A0 +#define SSD_SPI_REG_READY 0x01A8 + +/* i2c register */ +#define SSD_I2C_CTRL_REG 0x06F0 +#define SSD_I2C_RDATA_REG 0x06F4 + +/* temperature reg */ +#define SSD_BRIGE_TEMP_REG 0x0618 + +#define SSD_CTRL_TEMP_REG0 0x0700 +#define SSD_CTRL_TEMP_REG1 0x0708 +#define SSD_CTRL_TEMP_REG2 0x0710 +#define SSD_CTRL_TEMP_REG3 0x0718 +#define SSD_CTRL_TEMP_REG4 0x0720 +#define SSD_CTRL_TEMP_REG5 0x0728 +#define SSD_CTRL_TEMP_REG6 0x0730 +#define SSD_CTRL_TEMP_REG7 0x0738 + +/* reversion 3 reg */ +#define SSD_PROTOCOL_VER_REG 0x01B4 + +#define SSD_FLUSH_TIMEOUT_REG 0x02A4 +#define SSD_BM_FAULT_REG 0x0660 + +#define SSD_PV3_RAM_STATUS_REG_SZ 0x4 +#define SSD_PV3_RAM_STATUS_REG0 0x0260 +#define SSD_PV3_RAM_STATUS_REG1 0x0264 +#define SSD_PV3_RAM_STATUS_REG2 0x0268 +#define SSD_PV3_RAM_STATUS_REG3 0x026C +#define SSD_PV3_RAM_STATUS_REG4 0x0270 +#define SSD_PV3_RAM_STATUS_REG5 0x0274 +#define SSD_PV3_RAM_STATUS_REG6 0x0278 +#define SSD_PV3_RAM_STATUS_REG7 0x027C + +#define SSD_PV3_CHIP_INFO_REG_SZ 0x40 +#define SSD_PV3_CHIP_INFO_REG0 0x0300 +#define SSD_PV3_CHIP_INFO_REG1 0x0340 +#define SSD_PV3_CHIP_INFO_REG2 0x0380 +#define SSD_PV3_CHIP_INFO_REG3 0x03B0 +#define SSD_PV3_CHIP_INFO_REG4 0x0400 +#define SSD_PV3_CHIP_INFO_REG5 0x0440 +#define SSD_PV3_CHIP_INFO_REG6 0x0480 +#define SSD_PV3_CHIP_INFO_REG7 0x04B0 + +#define SSD_PV3_INIT_STATE_REG_SZ 0x20 +#define SSD_PV3_INIT_STATE_REG0 0x0500 +#define SSD_PV3_INIT_STATE_REG1 0x0520 +#define SSD_PV3_INIT_STATE_REG2 0x0540 +#define SSD_PV3_INIT_STATE_REG3 0x0560 +#define SSD_PV3_INIT_STATE_REG4 0x0580 +#define SSD_PV3_INIT_STATE_REG5 0x05A0 +#define SSD_PV3_INIT_STATE_REG6 0x05C0 +#define SSD_PV3_INIT_STATE_REG7 0x05E0 + +/* reversion 3.1.1 reg */ +#define SSD_FULL_RESET_REG 0x01B0 + +#define SSD_CTRL_REG_ZONE_SZ 0x800 + +#define SSD_BB_THRESHOLD_L1_REG 0x2C0 +#define SSD_BB_THRESHOLD_L2_REG 0x2C4 + +#define SSD_BB_ACC_REG_SZ 0x4 +#define SSD_BB_ACC_REG0 0x21C0 +#define SSD_BB_ACC_REG1 0x29C0 +#define SSD_BB_ACC_REG2 0x31C0 + +#define SSD_EC_THRESHOLD_L1_REG 0x2C8 +#define SSD_EC_THRESHOLD_L2_REG 0x2CC + +#define SSD_EC_ACC_REG_SZ 0x4 +#define SSD_EC_ACC_REG0 0x21E0 +#define SSD_EC_ACC_REG1 0x29E0 +#define SSD_EC_ACC_REG2 0x31E0 + +/* reversion 3.1.2 & 3.1.3 reg */ +#define SSD_HW_STATUS_REG 0x02AC + +#define SSD_PLP_INFO_REG 0x0664 + +/*reversion 3.2 reg*/ +#define SSD_POWER_ON_REG 0x01EC +#define SSD_PCIE_LINKSTATUS_REG 0x01F8 +#define SSD_PL_CAP_LEARN_REG 0x01FC + +#define SSD_FPGA_1V0_REG0 0x2070 +#define SSD_FPGA_1V8_REG0 0x2078 +#define SSD_FPGA_1V0_REG1 0x2870 +#define SSD_FPGA_1V8_REG1 0x2878 + +/*reversion 3.2 reg*/ +#define SSD_READ_OT_REG0 0x2260 +#define SSD_WRITE_OT_REG0 0x2264 +#define SSD_READ_OT_REG1 0x2A60 +#define SSD_WRITE_OT_REG1 0x2A64 + + +/* function */ +#define SSD_FUNC_READ 0x01 +#define SSD_FUNC_WRITE 0x02 +#define SSD_FUNC_NAND_READ_WOOB 0x03 +#define SSD_FUNC_NAND_READ 0x04 +#define SSD_FUNC_NAND_WRITE 0x05 +#define SSD_FUNC_NAND_ERASE 0x06 +#define SSD_FUNC_NAND_READ_ID 0x07 +#define SSD_FUNC_READ_LOG 0x08 +#define SSD_FUNC_TRIM 0x09 +#define SSD_FUNC_RAM_READ 0x10 +#define SSD_FUNC_RAM_WRITE 0x11 +#define SSD_FUNC_FLUSH 0x12 //cache / bbt + +/* spi function */ +#define SSD_SPI_CMD_PROGRAM 0x02 +#define SSD_SPI_CMD_READ 0x03 +#define SSD_SPI_CMD_W_DISABLE 0x04 +#define SSD_SPI_CMD_READ_STATUS 0x05 +#define SSD_SPI_CMD_W_ENABLE 0x06 +#define SSD_SPI_CMD_ERASE 0xd8 +#define SSD_SPI_CMD_CLSR 0x30 +#define SSD_SPI_CMD_READ_ID 0x9f + +/* i2c */ +#define SSD_I2C_CTRL_READ 0x00 +#define SSD_I2C_CTRL_WRITE 0x01 + +/* i2c internal register */ +#define SSD_I2C_CFG_REG 0x00 +#define SSD_I2C_DATA_REG 0x01 +#define SSD_I2C_CMD_REG 0x02 +#define SSD_I2C_STATUS_REG 0x03 +#define SSD_I2C_SADDR_REG 0x04 +#define SSD_I2C_LEN_REG 0x05 +#define SSD_I2C_RLEN_REG 0x06 +#define SSD_I2C_WLEN_REG 0x07 +#define SSD_I2C_RESET_REG 0x08 //write for reset +#define SSD_I2C_PRER_REG 0x09 + + +/* hw mon */ +/* FPGA volt = ADC_value / 4096 * 3v */ +#define SSD_FPGA_1V0_ADC_MIN 1228 // 0.9v +#define SSD_FPGA_1V0_ADC_MAX 1502 // 1.1v +#define SSD_FPGA_1V8_ADC_MIN 2211 // 1.62v +#define SSD_FPGA_1V8_ADC_MAX 2703 // 1.98 + +/* ADC value */ +#define SSD_FPGA_VOLT_MAX(val) (((val) & 0xffff) >> 4) +#define SSD_FPGA_VOLT_MIN(val) (((val >> 16) & 0xffff) >> 4) +#define SSD_FPGA_VOLT_CUR(val) (((val >> 32) & 0xffff) >> 4) +#define SSD_FPGA_VOLT(val) ((val * 3000) >> 12) + +#define SSD_VOLT_LOG_DATA(idx, ctrl, volt) (((uint32_t)idx << 24) | ((uint32_t)ctrl << 16) | ((uint32_t)volt)) + +enum ssd_fpga_volt +{ + SSD_FPGA_1V0 = 0, + SSD_FPGA_1V8, + SSD_FPGA_VOLT_NR +}; + +enum ssd_clock +{ + SSD_CLOCK_166M_LOST = 0, + SSD_CLOCK_166M_SKEW, + SSD_CLOCK_156M_LOST, + SSD_CLOCK_156M_SKEW, + SSD_CLOCK_NR +}; + +/* sensor */ +#define SSD_SENSOR_LM75_SADDRESS (0x49 << 1) +#define SSD_SENSOR_LM80_SADDRESS (0x28 << 1) + +#define SSD_SENSOR_CONVERT_TEMP(val) ((int)(val >> 8)) + +#define SSD_INLET_OT_TEMP (55) //55 DegC +#define SSD_INLET_OT_HYST (50) //50 DegC +#define SSD_FLASH_OT_TEMP (70) //70 DegC +#define SSD_FLASH_OT_HYST (65) //65 DegC + +enum ssd_sensor +{ + SSD_SENSOR_LM80 = 0, + SSD_SENSOR_LM75, + SSD_SENSOR_NR +}; + + +/* lm75 */ +enum ssd_lm75_reg +{ + SSD_LM75_REG_TEMP = 0, + SSD_LM75_REG_CONF, + SSD_LM75_REG_THYST, + SSD_LM75_REG_TOS +}; + +/* lm96080 */ +#define SSD_LM80_REG_IN_MAX(nr) (0x2a + (nr) * 2) +#define SSD_LM80_REG_IN_MIN(nr) (0x2b + (nr) * 2) +#define SSD_LM80_REG_IN(nr) (0x20 + (nr)) + +#define SSD_LM80_REG_FAN1 0x28 +#define SSD_LM80_REG_FAN2 0x29 +#define SSD_LM80_REG_FAN_MIN(nr) (0x3b + (nr)) + +#define SSD_LM80_REG_TEMP 0x27 +#define SSD_LM80_REG_TEMP_HOT_MAX 0x38 +#define SSD_LM80_REG_TEMP_HOT_HYST 0x39 +#define SSD_LM80_REG_TEMP_OS_MAX 0x3a +#define SSD_LM80_REG_TEMP_OS_HYST 0x3b + +#define SSD_LM80_REG_CONFIG 0x00 +#define SSD_LM80_REG_ALARM1 0x01 +#define SSD_LM80_REG_ALARM2 0x02 +#define SSD_LM80_REG_MASK1 0x03 +#define SSD_LM80_REG_MASK2 0x04 +#define SSD_LM80_REG_FANDIV 0x05 +#define SSD_LM80_REG_RES 0x06 + +#define SSD_LM80_CONVERT_VOLT(val) ((val * 10) >> 8) + +#define SSD_LM80_3V3_VOLT(val) ((val)*33/19) + +#define SSD_LM80_CONV_INTERVAL (1000) + +enum ssd_lm80_in +{ + SSD_LM80_IN_CAP = 0, + SSD_LM80_IN_1V2, + SSD_LM80_IN_1V2a, + SSD_LM80_IN_1V5, + SSD_LM80_IN_1V8, + SSD_LM80_IN_FPGA_3V3, + SSD_LM80_IN_3V3, + SSD_LM80_IN_NR +}; + +struct ssd_lm80_limit +{ + uint8_t low; + uint8_t high; +}; + +/* +/- 5% except cap in*/ +static struct ssd_lm80_limit ssd_lm80_limit[SSD_LM80_IN_NR] = { + {171, 217}, /* CAP in: 1710 ~ 2170 */ + {114, 126}, + {114, 126}, + {142, 158}, + {171, 189}, + {180, 200}, + {180, 200}, +}; + +/* temperature sensors */ +enum ssd_temp_sensor +{ + SSD_TEMP_INLET = 0, + SSD_TEMP_FLASH, + SSD_TEMP_CTRL, + SSD_TEMP_NR +}; + + +#ifdef SSD_OT_PROTECT +#define SSD_OT_DELAY (60) //ms + +#define SSD_OT_TEMP (90) //90 DegC + +#define SSD_OT_TEMP_HYST (85) //85 DegC +#endif + +/* fpga temperature */ +//#define CONVERT_TEMP(val) ((float)(val)*503.975f/4096.0f-273.15f) +#define CONVERT_TEMP(val) ((val)*504/4096-273) + +#define MAX_TEMP(val) CONVERT_TEMP(((val & 0xffff) >> 4)) +#define MIN_TEMP(val) CONVERT_TEMP((((val>>16) & 0xffff) >> 4)) +#define CUR_TEMP(val) CONVERT_TEMP((((val>>32) & 0xffff) >> 4)) + + +/* CAP monitor */ +#define SSD_PL_CAP_U1 SSD_LM80_REG_IN(SSD_LM80_IN_CAP) +#define SSD_PL_CAP_U2 SSD_LM80_REG_IN(SSD_LM80_IN_1V8) +#define SSD_PL_CAP_LEARN(u1, u2, t) ((t*(u1+u2))/(2*162*(u1-u2))) +#define SSD_PL_CAP_LEARN_WAIT (20) //20ms +#define SSD_PL_CAP_LEARN_MAX_WAIT (1000/SSD_PL_CAP_LEARN_WAIT) //1s + +#define SSD_PL_CAP_CHARGE_WAIT (1000) +#define SSD_PL_CAP_CHARGE_MAX_WAIT ((120*1000)/SSD_PL_CAP_CHARGE_WAIT) //120s + +#define SSD_PL_CAP_VOLT(val) (val*7) + +#define SSD_PL_CAP_VOLT_FULL (13700) +#define SSD_PL_CAP_VOLT_READY (12880) + +#define SSD_PL_CAP_THRESHOLD (8900) +#define SSD_PL_CAP_CP_THRESHOLD (5800) +#define SSD_PL_CAP_THRESHOLD_HYST (100) + +enum ssd_pl_cap_status +{ + SSD_PL_CAP = 0, + SSD_PL_CAP_NR +}; + +enum ssd_pl_cap_type +{ + SSD_PL_CAP_DEFAULT = 0, /* 4 cap */ + SSD_PL_CAP_CP /* 3 cap */ +}; + + +/* hwmon offset */ +#define SSD_HWMON_OFFS_TEMP (0) +#define SSD_HWMON_OFFS_SENSOR (SSD_HWMON_OFFS_TEMP + SSD_TEMP_NR) +#define SSD_HWMON_OFFS_PL_CAP (SSD_HWMON_OFFS_SENSOR + SSD_SENSOR_NR) +#define SSD_HWMON_OFFS_LM80 (SSD_HWMON_OFFS_PL_CAP + SSD_PL_CAP_NR) +#define SSD_HWMON_OFFS_CLOCK (SSD_HWMON_OFFS_LM80 + SSD_LM80_IN_NR) +#define SSD_HWMON_OFFS_FPGA (SSD_HWMON_OFFS_CLOCK + SSD_CLOCK_NR) + +#define SSD_HWMON_TEMP(idx) (SSD_HWMON_OFFS_TEMP + idx) +#define SSD_HWMON_SENSOR(idx) (SSD_HWMON_OFFS_SENSOR + idx) +#define SSD_HWMON_PL_CAP(idx) (SSD_HWMON_OFFS_PL_CAP + idx) +#define SSD_HWMON_LM80(idx) (SSD_HWMON_OFFS_LM80 + idx) +#define SSD_HWMON_CLOCK(idx) (SSD_HWMON_OFFS_CLOCK + idx) +#define SSD_HWMON_FPGA(ctrl, idx) (SSD_HWMON_OFFS_FPGA + (ctrl * SSD_FPGA_VOLT_NR) + idx) + + + +/* fifo */ +typedef struct sfifo +{ + uint32_t in; + uint32_t out; + uint32_t size; + uint32_t esize; + uint32_t mask; + spinlock_t lock; + void *data; +} sfifo_t; + +static int sfifo_alloc(struct sfifo *fifo, uint32_t size, uint32_t esize) +{ + uint32_t __size = 1; + + if (!fifo || size > INT_MAX || esize == 0) { + return -EINVAL; + } + + while (__size < size) __size <<= 1; + + if (__size < 2) { + return -EINVAL; + } + + fifo->data = vmalloc(esize * __size); + if (!fifo->data) { + return -ENOMEM; + } + + fifo->in = 0; + fifo->out = 0; + fifo->mask = __size - 1; + fifo->size = __size; + fifo->esize = esize; + spin_lock_init(&fifo->lock); + + return 0; +} + +static void sfifo_free(struct sfifo *fifo) +{ + if (!fifo) { + return; + } + + vfree(fifo->data); + fifo->data = NULL; + fifo->in = 0; + fifo->out = 0; + fifo->mask = 0; + fifo->size = 0; + fifo->esize = 0; +} + +static int __sfifo_put(struct sfifo *fifo, void *val) +{ + if (((fifo->in + 1) & fifo->mask) == fifo->out) { + return -1; + } + + memcpy((fifo->data + (fifo->in * fifo->esize)), val, fifo->esize); + fifo->in = (fifo->in + 1) & fifo->mask; + + return 0; +} + +static int sfifo_put(struct sfifo *fifo, void *val) +{ + int ret = 0; + + if (!fifo || !val) { + return -EINVAL; + } + + if (!in_interrupt()) { + spin_lock_irq(&fifo->lock); + ret = __sfifo_put(fifo, val); + spin_unlock_irq(&fifo->lock); + } else { + spin_lock(&fifo->lock); + ret = __sfifo_put(fifo, val); + spin_unlock(&fifo->lock); + } + + return ret; +} + +static int __sfifo_get(struct sfifo *fifo, void *val) +{ + if (fifo->out == fifo->in) { + return -1; + } + + memcpy(val, (fifo->data + (fifo->out * fifo->esize)), fifo->esize); + fifo->out = (fifo->out + 1) & fifo->mask; + + return 0; +} + +static int sfifo_get(struct sfifo *fifo, void *val) +{ + int ret = 0; + + if (!fifo || !val) { + return -EINVAL; + } + + if (!in_interrupt()) { + spin_lock_irq(&fifo->lock); + ret = __sfifo_get(fifo, val); + spin_unlock_irq(&fifo->lock); + } else { + spin_lock(&fifo->lock); + ret = __sfifo_get(fifo, val); + spin_unlock(&fifo->lock); + } + + return ret; +} + +/* bio list */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +struct ssd_blist { + struct bio *prev; + struct bio *next; +}; + +static inline void ssd_blist_init(struct ssd_blist *ssd_bl) +{ + ssd_bl->prev = NULL; + ssd_bl->next = NULL; +} + +static inline struct bio *ssd_blist_get(struct ssd_blist *ssd_bl) +{ + struct bio *bio = ssd_bl->prev; + + ssd_bl->prev = NULL; + ssd_bl->next = NULL; + + return bio; +} + +static inline void ssd_blist_add(struct ssd_blist *ssd_bl, struct bio *bio) +{ + bio->bi_next = NULL; + + if (ssd_bl->next) { + ssd_bl->next->bi_next = bio; + } else { + ssd_bl->prev = bio; + } + + ssd_bl->next = bio; +} + +#else +#define ssd_blist bio_list +#define ssd_blist_init bio_list_init +#define ssd_blist_get bio_list_get +#define ssd_blist_add bio_list_add +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) +#define bio_start(bio) (bio->bi_sector) +#else +#define bio_start(bio) (bio->bi_iter.bi_sector) +#endif + +/* mutex */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) +#define mutex_lock down +#define mutex_unlock up +#define mutex semaphore +#define mutex_init init_MUTEX +#endif + +/* i2c */ +typedef union ssd_i2c_ctrl { + uint32_t val; + struct { + uint8_t wdata; + uint8_t addr; + uint16_t rw:1; + uint16_t pad:15; + } bits; +}__attribute__((packed)) ssd_i2c_ctrl_t; + +typedef union ssd_i2c_data { + uint32_t val; + struct { + uint32_t rdata:8; + uint32_t valid:1; + uint32_t pad:23; + } bits; +}__attribute__((packed)) ssd_i2c_data_t; + +/* write mode */ +enum ssd_write_mode +{ + SSD_WMODE_BUFFER = 0, + SSD_WMODE_BUFFER_EX, + SSD_WMODE_FUA, + /* dummy */ + SSD_WMODE_AUTO, + SSD_WMODE_DEFAULT +}; + +/* reset type */ +enum ssd_reset_type +{ + SSD_RST_NOINIT = 0, + SSD_RST_NORMAL, + SSD_RST_FULL +}; + +/* ssd msg */ +typedef struct ssd_sg_entry +{ + uint64_t block:48; + uint64_t length:16; + uint64_t buf; +}__attribute__((packed))ssd_sg_entry_t; + +typedef struct ssd_rw_msg +{ + uint8_t tag; + uint8_t flag; + uint8_t nsegs; + uint8_t fun; + uint32_t reserved; //for 64-bit align + struct ssd_sg_entry sge[1]; //base +}__attribute__((packed))ssd_rw_msg_t; + +typedef struct ssd_resp_msg +{ + uint8_t tag; + uint8_t status:2; + uint8_t bitflip:6; + uint8_t log; + uint8_t fun; + uint32_t reserved; +}__attribute__((packed))ssd_resp_msg_t; + +typedef struct ssd_flush_msg +{ + uint8_t tag; + uint8_t flag:2; //flash cache 0 or bbt 1 + uint8_t flash:6; + uint8_t ctrl_idx; + uint8_t fun; + uint32_t reserved; //align +}__attribute__((packed))ssd_flush_msg_t; + +typedef struct ssd_nand_op_msg +{ + uint8_t tag; + uint8_t flag; + uint8_t ctrl_idx; + uint8_t fun; + uint32_t reserved; //align + uint16_t page_count; + uint8_t chip_ce; + uint8_t chip_no; + uint32_t page_no; + uint64_t buf; +}__attribute__((packed))ssd_nand_op_msg_t; + +typedef struct ssd_ram_op_msg +{ + uint8_t tag; + uint8_t flag; + uint8_t ctrl_idx; + uint8_t fun; + uint32_t reserved; //align + uint32_t start; + uint32_t length; + uint64_t buf; +}__attribute__((packed))ssd_ram_op_msg_t; + + +/* log msg */ +typedef struct ssd_log_msg +{ + uint8_t tag; + uint8_t flag; + uint8_t ctrl_idx; + uint8_t fun; + uint32_t reserved; //align + uint64_t buf; +}__attribute__((packed))ssd_log_msg_t; + +typedef struct ssd_log_op_msg +{ + uint8_t tag; + uint8_t flag; + uint8_t ctrl_idx; + uint8_t fun; + uint32_t reserved; //align + uint64_t reserved1; //align + uint64_t buf; +}__attribute__((packed))ssd_log_op_msg_t; + +typedef struct ssd_log_resp_msg +{ + uint8_t tag; + uint16_t status :2; + uint16_t reserved1 :2; //align with the normal resp msg + uint16_t nr_log :12; + uint8_t fun; + uint32_t reserved; +}__attribute__((packed))ssd_log_resp_msg_t; + + +/* resp msg */ +typedef union ssd_response_msq +{ + ssd_resp_msg_t resp_msg; + ssd_log_resp_msg_t log_resp_msg; + uint64_t u64_msg; + uint32_t u32_msg[2]; +} ssd_response_msq_t; + + +/* custom struct */ +typedef struct ssd_protocol_info +{ + uint32_t ver; + uint32_t init_state_reg; + uint32_t init_state_reg_sz; + uint32_t chip_info_reg; + uint32_t chip_info_reg_sz; +} ssd_protocol_info_t; + +typedef struct ssd_hw_info +{ + uint32_t bridge_ver; + uint32_t ctrl_ver; + + uint32_t cmd_fifo_sz; + uint32_t cmd_fifo_sz_mask; + uint32_t cmd_max_sg; + uint32_t sg_max_sec; + uint32_t resp_ptr_sz; + uint32_t resp_msg_sz; + + uint16_t nr_ctrl; + + uint16_t nr_data_ch; + uint16_t nr_ch; + uint16_t max_ch; + uint16_t nr_chip; + + uint8_t pcb_ver; + uint8_t upper_pcb_ver; + + uint8_t nand_vendor_id; + uint8_t nand_dev_id; + + uint8_t max_ce; + uint8_t id_size; + uint16_t oob_size; + + uint16_t bbf_pages; + uint16_t bbf_seek; // + + uint16_t page_count; //per block + uint32_t page_size; + uint32_t block_count; //per flash + + uint64_t ram_size; + uint32_t ram_align; + uint32_t ram_max_len; + + uint64_t bbt_base; + uint32_t bbt_size; + uint64_t md_base; //metadata + uint32_t md_size; + uint32_t md_entry_sz; + + uint32_t log_sz; + + uint64_t nand_wbuff_base; + + uint32_t md_reserved_blks; + uint32_t reserved_blks; + uint32_t valid_pages; + uint32_t max_valid_pages; + uint64_t size; +} ssd_hw_info_t; + +typedef struct ssd_hw_info_extend +{ + uint8_t board_type; + uint8_t cap_type; + uint8_t plp_type; + uint8_t work_mode; + uint8_t form_factor; + + uint8_t pad[59]; +}ssd_hw_info_extend_t; + +typedef struct ssd_rom_info +{ + uint32_t size; + uint32_t block_size; + uint16_t page_size; + uint8_t nr_bridge_fw; + uint8_t nr_ctrl_fw; + uint8_t nr_bm_fw; + uint8_t nr_smart; + uint32_t bridge_fw_base; + uint32_t bridge_fw_sz; + uint32_t ctrl_fw_base; + uint32_t ctrl_fw_sz; + uint32_t bm_fw_base; + uint32_t bm_fw_sz; + uint32_t log_base; + uint32_t log_sz; + uint32_t smart_base; + uint32_t smart_sz; + uint32_t vp_base; + uint32_t label_base; +} ssd_rom_info_t; + +/* debug info */ +enum ssd_debug_type +{ + SSD_DEBUG_NONE = 0, + SSD_DEBUG_READ_ERR, + SSD_DEBUG_WRITE_ERR, + SSD_DEBUG_RW_ERR, + SSD_DEBUG_READ_TO, + SSD_DEBUG_WRITE_TO, + SSD_DEBUG_RW_TO, + SSD_DEBUG_LOG, + SSD_DEBUG_OFFLINE, + SSD_DEBUG_NR +}; + +typedef struct ssd_debug_info +{ + int type; + union { + struct { + uint64_t off; + uint32_t len; + } loc; + struct { + int event; + uint32_t extra; + } log; + } data; +}ssd_debug_info_t; + +/* label */ +#define SSD_LABEL_FIELD_SZ 32 +#define SSD_SN_SZ 16 + +typedef struct ssd_label +{ + char date[SSD_LABEL_FIELD_SZ]; + char sn[SSD_LABEL_FIELD_SZ]; + char part[SSD_LABEL_FIELD_SZ]; + char desc[SSD_LABEL_FIELD_SZ]; + char other[SSD_LABEL_FIELD_SZ]; + char maf[SSD_LABEL_FIELD_SZ]; +} ssd_label_t; + +#define SSD_LABEL_DESC_SZ 256 + +typedef struct ssd_labelv3 +{ + char boardtype[SSD_LABEL_FIELD_SZ]; + char barcode[SSD_LABEL_FIELD_SZ]; + char item[SSD_LABEL_FIELD_SZ]; + char description[SSD_LABEL_DESC_SZ]; + char manufactured[SSD_LABEL_FIELD_SZ]; + char vendorname[SSD_LABEL_FIELD_SZ]; + char issuenumber[SSD_LABEL_FIELD_SZ]; + char cleicode[SSD_LABEL_FIELD_SZ]; + char bom[SSD_LABEL_FIELD_SZ]; +} ssd_labelv3_t; + +/* battery */ +typedef struct ssd_battery_info +{ + uint32_t fw_ver; +} ssd_battery_info_t; + +/* ssd power stat */ +typedef struct ssd_power_stat +{ + uint64_t nr_poweron; + uint64_t nr_powerloss; + uint64_t init_failed; +} ssd_power_stat_t; + +/* io stat */ +typedef struct ssd_io_stat +{ + uint64_t run_time; + uint64_t nr_to; + uint64_t nr_ioerr; + uint64_t nr_rwerr; + uint64_t nr_read; + uint64_t nr_write; + uint64_t rsectors; + uint64_t wsectors; +} ssd_io_stat_t; + +/* ecc */ +typedef struct ssd_ecc_info +{ + uint64_t bitflip[SSD_ECC_MAX_FLIP]; +} ssd_ecc_info_t; + +/* log */ +enum ssd_log_level +{ + SSD_LOG_LEVEL_INFO = 0, + SSD_LOG_LEVEL_NOTICE, + SSD_LOG_LEVEL_WARNING, + SSD_LOG_LEVEL_ERR, + SSD_LOG_NR_LEVEL +}; + +typedef struct ssd_log_info +{ + uint64_t nr_log; + uint64_t stat[SSD_LOG_NR_LEVEL]; +} ssd_log_info_t; + +/* S.M.A.R.T. */ +#define SSD_SMART_MAGIC (0x5452414D53445353ull) + +typedef struct ssd_smart +{ + struct ssd_power_stat pstat; + struct ssd_io_stat io_stat; + struct ssd_ecc_info ecc_info; + struct ssd_log_info log_info; + uint64_t version; + uint64_t magic; +} ssd_smart_t; + +/* internal log */ +typedef struct ssd_internal_log +{ + uint32_t nr_log; + void *log; +} ssd_internal_log_t; + +/* ssd cmd */ +typedef struct ssd_cmd +{ + struct bio *bio; + struct scatterlist *sgl; + struct list_head list; + void *dev; + int nsegs; + int flag; /*pbio(1) or bio(0)*/ + + int tag; + void *msg; + dma_addr_t msg_dma; + + unsigned long start_time; + + int errors; + unsigned int nr_log; + + struct timer_list cmd_timer; + struct completion *waiting; +} ssd_cmd_t; + +typedef void (*send_cmd_func)(struct ssd_cmd *); +typedef int (*ssd_event_call)(struct gendisk *, int, int); /* gendisk, event id, event level */ + +/* dcmd sz */ +#define SSD_DCMD_MAX_SZ 32 + +typedef struct ssd_dcmd +{ + struct list_head list; + void *dev; + uint8_t msg[SSD_DCMD_MAX_SZ]; +} ssd_dcmd_t; + + +enum ssd_state { + SSD_INIT_WORKQ, + SSD_INIT_BD, + SSD_ONLINE, + /* full reset */ + SSD_RESETING, + /* hw log */ + SSD_LOG_HW, + /* log err */ + SSD_LOG_ERR +}; + +#define SSD_QUEUE_NAME_LEN 16 +typedef struct ssd_queue { + char name[SSD_QUEUE_NAME_LEN]; + void *dev; + + int idx; + + uint32_t resp_idx; + uint32_t resp_idx_mask; + uint32_t resp_msg_sz; + + void *resp_msg; + void *resp_ptr; + + struct ssd_cmd *cmd; + + struct ssd_io_stat io_stat; + struct ssd_ecc_info ecc_info; +} ssd_queue_t; + +typedef struct ssd_device { + char name[SSD_DEV_NAME_LEN]; + + int idx; + int major; + int readonly; + + int int_mode; +#ifdef SSD_ESCAPE_IRQ + int irq_cpu; +#endif + + int reload_fw; + + int ot_delay; //in ms + + atomic_t refcnt; + atomic_t tocnt; + atomic_t in_flight[2]; //r&w + + uint64_t uptime; + + struct list_head list; + struct pci_dev *pdev; + + unsigned long mmio_base; + unsigned long mmio_len; + void __iomem *ctrlp; + + struct mutex spi_mutex; + struct mutex i2c_mutex; + + struct ssd_protocol_info protocol_info; + struct ssd_hw_info hw_info; + struct ssd_rom_info rom_info; + struct ssd_label label; + + struct ssd_smart smart; + + atomic_t in_sendq; + spinlock_t sendq_lock; + struct ssd_blist sendq; + struct task_struct *send_thread; + wait_queue_head_t send_waitq; + + atomic_t in_doneq; + spinlock_t doneq_lock; + struct ssd_blist doneq; + struct task_struct *done_thread; + wait_queue_head_t done_waitq; + + struct ssd_dcmd *dcmd; + spinlock_t dcmd_lock; + struct list_head dcmd_list; /* direct cmd list */ + wait_queue_head_t dcmd_wq; + + unsigned long *tag_map; + wait_queue_head_t tag_wq; + + spinlock_t cmd_lock; + struct ssd_cmd *cmd; + send_cmd_func scmd; + + ssd_event_call event_call; + void *msg_base; + dma_addr_t msg_base_dma; + + uint32_t resp_idx; + void *resp_msg_base; + void *resp_ptr_base; + dma_addr_t resp_msg_base_dma; + dma_addr_t resp_ptr_base_dma; + + int nr_queue; + struct msix_entry entry[SSD_MSIX_VEC]; + struct ssd_queue queue[SSD_MSIX_VEC]; + + struct request_queue *rq; /* The device request queue */ + struct gendisk *gd; /* The gendisk structure */ + + struct mutex internal_log_mutex; + struct ssd_internal_log internal_log; + struct workqueue_struct *workq; + struct work_struct log_work; /* get log */ + void *log_buf; + + unsigned long state; /* device state, for example, block device inited */ + + struct module *owner; + + /* extend */ + + int slave; + int cmajor; + int save_md; + int ot_protect; + + struct kref kref; + + struct mutex gd_mutex; + struct ssd_log_info log_info; /* volatile */ + + atomic_t queue_depth; + struct mutex barrier_mutex; + struct mutex fw_mutex; + + struct ssd_hw_info_extend hw_info_ext; + struct ssd_labelv3 labelv3; + + int wmode; + int user_wmode; + struct mutex bm_mutex; + struct work_struct bm_work; /* check bm */ + struct timer_list bm_timer; + struct sfifo log_fifo; + + struct timer_list routine_timer; + unsigned long routine_tick; + unsigned long hwmon; + + struct work_struct hwmon_work; /* check hw */ + struct work_struct capmon_work; /* check battery */ + struct work_struct tempmon_work; /* check temp */ + + /* debug info */ + struct ssd_debug_info db_info; +} ssd_device_t; + + +/* Ioctl struct */ +typedef struct ssd_acc_info { + uint32_t threshold_l1; + uint32_t threshold_l2; + uint32_t val; +} ssd_acc_info_t; + +typedef struct ssd_reg_op_info +{ + uint32_t offset; + uint32_t value; +} ssd_reg_op_info_t; + +typedef struct ssd_spi_op_info +{ + void __user *buf; + uint32_t off; + uint32_t len; +} ssd_spi_op_info_t; + +typedef struct ssd_i2c_op_info +{ + uint8_t saddr; + uint8_t wsize; + uint8_t rsize; + void __user *wbuf; + void __user *rbuf; +} ssd_i2c_op_info_t; + +typedef struct ssd_smbus_op_info +{ + uint8_t saddr; + uint8_t cmd; + uint8_t size; + void __user *buf; +} ssd_smbus_op_info_t; + +typedef struct ssd_ram_op_info { + uint8_t ctrl_idx; + uint32_t length; + uint64_t start; + uint8_t __user *buf; +} ssd_ram_op_info_t; + +typedef struct ssd_flash_op_info { + uint32_t page; + uint16_t flash; + uint8_t chip; + uint8_t ctrl_idx; + uint8_t __user *buf; +} ssd_flash_op_info_t; + +typedef struct ssd_sw_log_info { + uint16_t event; + uint16_t pad; + uint32_t data; +} ssd_sw_log_info_t; + +typedef struct ssd_version_info +{ + uint32_t bridge_ver; /* bridge fw version */ + uint32_t ctrl_ver; /* controller fw version */ + uint32_t bm_ver; /* battery manager fw version */ + uint8_t pcb_ver; /* main pcb version */ + uint8_t upper_pcb_ver; + uint8_t pad0; + uint8_t pad1; +} ssd_version_info_t; + +typedef struct pci_addr +{ + uint16_t domain; + uint8_t bus; + uint8_t slot; + uint8_t func; +} pci_addr_t; + +typedef struct ssd_drv_param_info { + int mode; + int status_mask; + int int_mode; + int threaded_irq; + int log_level; + int wmode; + int ot_protect; + int finject; + int pad[8]; +} ssd_drv_param_info_t; + + +/* form factor */ +enum ssd_form_factor +{ + SSD_FORM_FACTOR_HHHL = 0, + SSD_FORM_FACTOR_FHHL +}; + + +/* ssd power loss protect */ +enum ssd_plp_type +{ + SSD_PLP_SCAP = 0, + SSD_PLP_CAP, + SSD_PLP_NONE +}; + +/* ssd bm */ +#define SSD_BM_SLAVE_ADDRESS 0x16 +#define SSD_BM_CAP 5 + +/* SBS cmd */ +#define SSD_BM_SAFETYSTATUS 0x51 +#define SSD_BM_OPERATIONSTATUS 0x54 + +/* ManufacturerAccess */ +#define SSD_BM_MANUFACTURERACCESS 0x00 +#define SSD_BM_ENTER_CAP_LEARNING 0x0023 /* cap learning */ + +/* Data flash access */ +#define SSD_BM_DATA_FLASH_SUBCLASS_ID 0x77 +#define SSD_BM_DATA_FLASH_SUBCLASS_ID_PAGE1 0x78 +#define SSD_BM_SYSTEM_DATA_SUBCLASS_ID 56 +#define SSD_BM_CONFIGURATION_REGISTERS_ID 64 + +/* min cap voltage */ +#define SSD_BM_CAP_VOLT_MIN 500 + +/* +enum ssd_bm_cap +{ + SSD_BM_CAP_VINA = 1, + SSD_BM_CAP_JH = 3 +};*/ + +enum ssd_bmstatus +{ + SSD_BMSTATUS_OK = 0, + SSD_BMSTATUS_CHARGING, /* not fully charged */ + SSD_BMSTATUS_WARNING +}; + +enum sbs_unit { + SBS_UNIT_VALUE = 0, + SBS_UNIT_TEMPERATURE, + SBS_UNIT_VOLTAGE, + SBS_UNIT_CURRENT, + SBS_UNIT_ESR, + SBS_UNIT_PERCENT, + SBS_UNIT_CAPACITANCE +}; + +enum sbs_size { + SBS_SIZE_BYTE = 1, + SBS_SIZE_WORD, + SBS_SIZE_BLK, +}; + +struct sbs_cmd { + uint8_t cmd; + uint8_t size; + uint8_t unit; + uint8_t off; + uint16_t mask; + char *desc; +}; + +struct ssd_bm { + uint16_t temp; + uint16_t volt; + uint16_t curr; + uint16_t esr; + uint16_t rsoc; + uint16_t health; + uint16_t cap; + uint16_t chg_curr; + uint16_t chg_volt; + uint16_t cap_volt[SSD_BM_CAP]; + uint16_t sf_alert; + uint16_t sf_status; + uint16_t op_status; + uint16_t sys_volt; +}; + +struct ssd_bm_manufacturer_data +{ + uint16_t pack_lot_code; + uint16_t pcb_lot_code; + uint16_t firmware_ver; + uint16_t hardware_ver; +}; + +struct ssd_bm_configuration_registers +{ + struct { + uint16_t cc:3; + uint16_t rsvd:5; + uint16_t stack:1; + uint16_t rsvd1:2; + uint16_t temp:2; + uint16_t rsvd2:1; + uint16_t lt_en:1; + uint16_t rsvd3:1; + } operation_cfg; + uint16_t pad; + uint16_t fet_action; + uint16_t pad1; + uint16_t fault; +}; + +#define SBS_VALUE_MASK 0xffff + +#define bm_var_offset(var) ((size_t) &((struct ssd_bm *)0)->var) +#define bm_var(start, offset) ((void *) start + (offset)) + +static struct sbs_cmd ssd_bm_sbs[] = { + {0x08, SBS_SIZE_WORD, SBS_UNIT_TEMPERATURE, bm_var_offset(temp), SBS_VALUE_MASK, "Temperature"}, + {0x09, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, bm_var_offset(volt), SBS_VALUE_MASK, "Voltage"}, + {0x0a, SBS_SIZE_WORD, SBS_UNIT_CURRENT, bm_var_offset(curr), SBS_VALUE_MASK, "Current"}, + {0x0b, SBS_SIZE_WORD, SBS_UNIT_ESR, bm_var_offset(esr), SBS_VALUE_MASK, "ESR"}, + {0x0d, SBS_SIZE_BYTE, SBS_UNIT_PERCENT, bm_var_offset(rsoc), SBS_VALUE_MASK, "RelativeStateOfCharge"}, + {0x0e, SBS_SIZE_BYTE, SBS_UNIT_PERCENT, bm_var_offset(health), SBS_VALUE_MASK, "Health"}, + {0x10, SBS_SIZE_WORD, SBS_UNIT_CAPACITANCE, bm_var_offset(cap), SBS_VALUE_MASK, "Capacitance"}, + {0x14, SBS_SIZE_WORD, SBS_UNIT_CURRENT, bm_var_offset(chg_curr), SBS_VALUE_MASK, "ChargingCurrent"}, + {0x15, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, bm_var_offset(chg_volt), SBS_VALUE_MASK, "ChargingVoltage"}, + {0x3b, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[4]), SBS_VALUE_MASK, "CapacitorVoltage5"}, + {0x3c, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[3]), SBS_VALUE_MASK, "CapacitorVoltage4"}, + {0x3d, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[2]), SBS_VALUE_MASK, "CapacitorVoltage3"}, + {0x3e, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[1]), SBS_VALUE_MASK, "CapacitorVoltage2"}, + {0x3f, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[0]), SBS_VALUE_MASK, "CapacitorVoltage1"}, + {0x50, SBS_SIZE_WORD, SBS_UNIT_VALUE, bm_var_offset(sf_alert), 0x870F, "SafetyAlert"}, + {0x51, SBS_SIZE_WORD, SBS_UNIT_VALUE, bm_var_offset(sf_status), 0xE7BF, "SafetyStatus"}, + {0x54, SBS_SIZE_WORD, SBS_UNIT_VALUE, bm_var_offset(op_status), 0x79F4, "OperationStatus"}, + {0x5a, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, bm_var_offset(sys_volt), SBS_VALUE_MASK, "SystemVoltage"}, + {0, 0, 0, 0, 0, NULL}, +}; + +/* ssd ioctl */ +#define SSD_CMD_GET_PROTOCOL_INFO _IOR('H', 100, struct ssd_protocol_info) +#define SSD_CMD_GET_HW_INFO _IOR('H', 101, struct ssd_hw_info) +#define SSD_CMD_GET_ROM_INFO _IOR('H', 102, struct ssd_rom_info) +#define SSD_CMD_GET_SMART _IOR('H', 103, struct ssd_smart) +#define SSD_CMD_GET_IDX _IOR('H', 105, int) +#define SSD_CMD_GET_AMOUNT _IOR('H', 106, int) +#define SSD_CMD_GET_TO_INFO _IOR('H', 107, int) +#define SSD_CMD_GET_DRV_VER _IOR('H', 108, char[DRIVER_VERSION_LEN]) + +#define SSD_CMD_GET_BBACC_INFO _IOR('H', 109, struct ssd_acc_info) +#define SSD_CMD_GET_ECACC_INFO _IOR('H', 110, struct ssd_acc_info) + +#define SSD_CMD_GET_HW_INFO_EXT _IOR('H', 111, struct ssd_hw_info_extend) + +#define SSD_CMD_REG_READ _IOWR('H', 120, struct ssd_reg_op_info) +#define SSD_CMD_REG_WRITE _IOWR('H', 121, struct ssd_reg_op_info) + +#define SSD_CMD_SPI_READ _IOWR('H', 125, struct ssd_spi_op_info) +#define SSD_CMD_SPI_WRITE _IOWR('H', 126, struct ssd_spi_op_info) +#define SSD_CMD_SPI_ERASE _IOWR('H', 127, struct ssd_spi_op_info) + +#define SSD_CMD_I2C_READ _IOWR('H', 128, struct ssd_i2c_op_info) +#define SSD_CMD_I2C_WRITE _IOWR('H', 129, struct ssd_i2c_op_info) +#define SSD_CMD_I2C_WRITE_READ _IOWR('H', 130, struct ssd_i2c_op_info) + +#define SSD_CMD_SMBUS_SEND_BYTE _IOWR('H', 131, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_RECEIVE_BYTE _IOWR('H', 132, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_WRITE_BYTE _IOWR('H', 133, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_READ_BYTE _IOWR('H', 135, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_WRITE_WORD _IOWR('H', 136, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_READ_WORD _IOWR('H', 137, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_WRITE_BLOCK _IOWR('H', 138, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_READ_BLOCK _IOWR('H', 139, struct ssd_smbus_op_info) + +#define SSD_CMD_BM_GET_VER _IOR('H', 140, uint16_t) +#define SSD_CMD_BM_GET_NR_CAP _IOR('H', 141, int) +#define SSD_CMD_BM_CAP_LEARNING _IOW('H', 142, int) +#define SSD_CMD_CAP_LEARN _IOR('H', 143, uint32_t) +#define SSD_CMD_GET_CAP_STATUS _IOR('H', 144, int) + +#define SSD_CMD_RAM_READ _IOWR('H', 150, struct ssd_ram_op_info) +#define SSD_CMD_RAM_WRITE _IOWR('H', 151, struct ssd_ram_op_info) + +#define SSD_CMD_NAND_READ_ID _IOR('H', 160, struct ssd_flash_op_info) +#define SSD_CMD_NAND_READ _IOWR('H', 161, struct ssd_flash_op_info) //with oob +#define SSD_CMD_NAND_WRITE _IOWR('H', 162, struct ssd_flash_op_info) +#define SSD_CMD_NAND_ERASE _IOWR('H', 163, struct ssd_flash_op_info) +#define SSD_CMD_NAND_READ_EXT _IOWR('H', 164, struct ssd_flash_op_info) //ingore EIO + +#define SSD_CMD_UPDATE_BBT _IOW('H', 180, struct ssd_flash_op_info) + +#define SSD_CMD_CLEAR_ALARM _IOW('H', 190, int) +#define SSD_CMD_SET_ALARM _IOW('H', 191, int) + +#define SSD_CMD_RESET _IOW('H', 200, int) +#define SSD_CMD_RELOAD_FW _IOW('H', 201, int) +#define SSD_CMD_UNLOAD_DEV _IOW('H', 202, int) +#define SSD_CMD_LOAD_DEV _IOW('H', 203, int) +#define SSD_CMD_UPDATE_VP _IOWR('H', 205, uint32_t) +#define SSD_CMD_FULL_RESET _IOW('H', 206, int) + +#define SSD_CMD_GET_NR_LOG _IOR('H', 220, uint32_t) +#define SSD_CMD_GET_LOG _IOR('H', 221, void *) +#define SSD_CMD_LOG_LEVEL _IOW('H', 222, int) + +#define SSD_CMD_OT_PROTECT _IOW('H', 223, int) +#define SSD_CMD_GET_OT_STATUS _IOR('H', 224, int) + +#define SSD_CMD_CLEAR_LOG _IOW('H', 230, int) +#define SSD_CMD_CLEAR_SMART _IOW('H', 231, int) + +#define SSD_CMD_SW_LOG _IOW('H', 232, struct ssd_sw_log_info) + +#define SSD_CMD_GET_LABEL _IOR('H', 235, struct ssd_label) +#define SSD_CMD_GET_VERSION _IOR('H', 236, struct ssd_version_info) +#define SSD_CMD_GET_TEMPERATURE _IOR('H', 237, int) +#define SSD_CMD_GET_BMSTATUS _IOR('H', 238, int) +#define SSD_CMD_GET_LABEL2 _IOR('H', 239, void *) + + +#define SSD_CMD_FLUSH _IOW('H', 240, int) +#define SSD_CMD_SAVE_MD _IOW('H', 241, int) + +#define SSD_CMD_SET_WMODE _IOW('H', 242, int) +#define SSD_CMD_GET_WMODE _IOR('H', 243, int) +#define SSD_CMD_GET_USER_WMODE _IOR('H', 244, int) + +#define SSD_CMD_DEBUG _IOW('H', 250, struct ssd_debug_info) +#define SSD_CMD_DRV_PARAM_INFO _IOR('H', 251, struct ssd_drv_param_info) + + +/* log */ +#define SSD_LOG_MAX_SZ 4096 +#define SSD_LOG_LEVEL SSD_LOG_LEVEL_NOTICE + +enum ssd_log_data +{ + SSD_LOG_DATA_NONE = 0, + SSD_LOG_DATA_LOC, + SSD_LOG_DATA_HEX +}; + +typedef struct ssd_log_entry +{ + union { + struct { + uint32_t page:10; + uint32_t block:14; + uint32_t flash:8; + } loc; + struct { + uint32_t page:12; + uint32_t block:12; + uint32_t flash:8; + } loc1; + uint32_t val; + } data; + uint16_t event:10; + uint16_t mod:6; + uint16_t idx; +}__attribute__((packed))ssd_log_entry_t; + +typedef struct ssd_log +{ + uint64_t time:56; + uint64_t ctrl_idx:8; + ssd_log_entry_t le; +} __attribute__((packed)) ssd_log_t; + +typedef struct ssd_log_desc +{ + uint16_t event; + uint8_t level; + uint8_t data; + uint8_t sblock; + uint8_t spage; + char *desc; +} __attribute__((packed)) ssd_log_desc_t; + +#define SSD_LOG_SW_IDX 0xF +#define SSD_UNKNOWN_EVENT ((uint16_t)-1) +static struct ssd_log_desc ssd_log_desc[] = { + /* event, level, show flash, show block, show page, desc */ + {0x0, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 0, 0, "Create BBT failure"}, //g3 + {0x1, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 0, 0, "Read BBT failure"}, //g3 + {0x2, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Mark bad block"}, + {0x3, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Flush BBT failure"}, + {0x4, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0x7, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "No available blocks"}, + {0x8, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Bad EC header"}, + {0x9, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 1, 0, "Bad VID header"}, //g3 + {0xa, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 0, "Wear leveling"}, + {0xb, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "WL read back failure"}, + {0x11, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Data recovery failure"}, // err + {0x20, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: scan mapping table failure"}, // err g3 + {0x21, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0x22, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0x23, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0x24, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Merge: read mapping page failure"}, + {0x25, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Merge: read back failure"}, + {0x26, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0x27, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 1, 1, "Data corrupted for abnormal power down"}, //g3 + {0x28, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Merge: mapping page corrupted"}, + {0x29, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Init: no mapping page"}, + {0x2a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: mapping pages incomplete"}, + {0x2b, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Read back failure after programming failure"}, // err + {0xf1, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Read failure without recovery"}, // err + {0xf2, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 0, 0, "No available blocks"}, // maybe err g3 + {0xf3, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Init: RAID incomplete"}, // err g3 + {0xf4, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0xf5, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read failure in moving data"}, + {0xf6, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0xf7, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 1, 1, "Init: RAID not complete"}, + {0xf8, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Init: data moving interrupted"}, + {0xfe, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Data inspection failure"}, + {0xff, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "IO: ECC failed"}, + + /* new */ + {0x2e, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 0, 0, "No available reserved blocks" }, // err + {0x30, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PMT membership not found"}, + {0x31, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Init: PMT corrupted"}, + {0x32, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PBT membership not found"}, + {0x33, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PBT not found"}, + {0x34, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PBT corrupted"}, + {0x35, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PMT page read failure"}, + {0x36, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT page read failure"}, + {0x37, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT backup page read failure"}, + {0x38, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBMT read failure"}, + {0x39, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: PBMT scan failure"}, // err + {0x3a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: first page read failure"}, + {0x3b, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: first page scan failure"}, // err + {0x3c, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: scan unclosed block failure"}, // err + {0x3d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: write pointer mismatch"}, + {0x3e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PMT recovery: PBMT read failure"}, + {0x3f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Init: PMT recovery: PBMT scan failure"}, + {0x40, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: PMT recovery: data page read failure"}, //err + {0x41, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT write pointer mismatch"}, + {0x42, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT latest version corrupted"}, + {0x43, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Init: too many unclosed blocks"}, + {0x44, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Init: PDW block found"}, + {0x45, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "Init: more than one PDW block found"}, //err + {0x46, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: first page is blank or read failure"}, + {0x47, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PDW block not found"}, + + {0x50, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Cache: hit error data"}, // err + {0x51, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Cache: read back failure"}, // err + {0x52, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Cache: unknown command"}, //? + {0x53, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "GC/WL read back failure"}, // err + + {0x60, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Erase failure"}, + + {0x70, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "LPA not matched"}, + {0x71, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "PBN not matched"}, + {0x72, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read retry failure"}, + {0x73, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Need raid recovery"}, + {0x74, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 1, "Need read retry"}, + {0x75, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read invalid data page"}, + {0x76, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 1, "ECC error, data in cache, PBN matched"}, + {0x77, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC error, data in cache, PBN not matched"}, + {0x78, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC error, data in flash, PBN not matched"}, + {0x79, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC ok, data in cache, LPA not matched"}, + {0x7a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC ok, data in flash, LPA not matched"}, + {0x7b, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID data in cache, LPA not matched"}, + {0x7c, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID data in flash, LPA not matched"}, + {0x7d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read data page status error"}, + {0x7e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read blank page"}, + {0x7f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Access flash timeout"}, + + {0x80, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "EC overflow"}, + {0x81, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_NONE, 0, 0, "Scrubbing completed"}, + {0x82, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 0, "Unstable block(too much bit flip)"}, + {0x83, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: ram error"}, //? + {0x84, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: one PBMT read failure"}, + + {0x88, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: mark bad block"}, + {0x89, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: invalid page count error"}, // maybe err + {0x8a, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "Warning: Bad Block close to limit"}, + {0x8b, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Error: Bad Block over limit"}, + {0x8c, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "Warning: P/E cycles close to limit"}, + {0x8d, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Error: P/E cycles over limit"}, + + {0x90, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Over temperature"}, //xx + {0x91, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Temperature is OK"}, //xx + {0x92, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "Battery fault"}, + {0x93, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "SEU fault"}, //err + {0x94, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "DDR error"}, //err + {0x95, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Controller serdes error"}, //err + {0x96, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Bridge serdes 1 error"}, //err + {0x97, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Bridge serdes 2 error"}, //err + {0x98, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "SEU fault (corrected)"}, //err + {0x99, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Battery is OK"}, + {0x9a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Temperature close to limit"}, //xx + + {0x9b, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "SEU fault address (low)"}, + {0x9c, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "SEU fault address (high)"}, + {0x9d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "I2C fault" }, + {0x9e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "DDR single bit error" }, + {0x9f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Board voltage fault" }, + + {0xa0, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "LPA not matched"}, + {0xa1, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Re-read data in cache"}, + {0xa2, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read blank page"}, + {0xa3, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: Read blank page"}, + {0xa4, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: new data in cache"}, + {0xa5, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: PBN not matched"}, + {0xa6, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read data with error flag"}, + {0xa7, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: recoverd data with error flag"}, + {0xa8, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Blank page in cache, PBN matched"}, + {0xa9, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: Blank page in cache, PBN matched"}, + {0xaa, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Flash init failure"}, + {0xab, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Mapping table recovery failure"}, + {0xac, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: ECC failed"}, + {0xb0, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Temperature is up to degree 95"}, + {0xb1, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Temperature is up to degree 100"}, + + {0x300, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "CMD timeout"}, + {0x301, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Power on"}, + {0x302, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Power off"}, + {0x303, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Clear log"}, + {0x304, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Set capacity"}, + {0x305, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Clear data"}, + {0x306, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "BM safety status"}, + {0x307, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "I/O error"}, + {0x308, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "CMD error"}, + {0x309, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Set wmode"}, + {0x30a, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "DDR init failed" }, + {0x30b, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "PCIe link status" }, + {0x30c, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "Controller reset sync error" }, + {0x30d, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "Clock fault" }, + {0x30e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "FPGA voltage fault status" }, + {0x30f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Set capacity finished"}, + {0x310, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Clear data finished"}, + {0x311, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Reset"}, + {0x312, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_HEX, 0, 0, "CAP: voltage fault"}, + {0x313, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_NONE, 0, 0, "CAP: learn fault"}, + {0x314, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "CAP status"}, + {0x315, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Board voltage fault status"}, + {0x316, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Inlet over temperature"}, + {0x317, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Inlet temperature is OK"}, + {0x318, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Flash over temperature"}, + {0x319, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Flash temperature is OK"}, + {0x31a, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_NONE, 0, 0, "CAP: short circuit"}, + {0x31b, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_HEX, 0, 0, "Sensor fault"}, + {0x31c, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Erase all data"}, + {0x31d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Erase all data finished"}, + + {SSD_UNKNOWN_EVENT, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "unknown event"}, +}; +/* */ +#define SSD_LOG_OVER_TEMP 0x90 +#define SSD_LOG_NORMAL_TEMP 0x91 +#define SSD_LOG_WARN_TEMP 0x9a +#define SSD_LOG_SEU_FAULT 0x93 +#define SSD_LOG_SEU_FAULT1 0x98 +#define SSD_LOG_BATTERY_FAULT 0x92 +#define SSD_LOG_BATTERY_OK 0x99 +#define SSD_LOG_BOARD_VOLT_FAULT 0x9f + +/* software log */ +#define SSD_LOG_TIMEOUT 0x300 +#define SSD_LOG_POWER_ON 0x301 +#define SSD_LOG_POWER_OFF 0x302 +#define SSD_LOG_CLEAR_LOG 0x303 +#define SSD_LOG_SET_CAPACITY 0x304 +#define SSD_LOG_CLEAR_DATA 0x305 +#define SSD_LOG_BM_SFSTATUS 0x306 +#define SSD_LOG_EIO 0x307 +#define SSD_LOG_ECMD 0x308 +#define SSD_LOG_SET_WMODE 0x309 +#define SSD_LOG_DDR_INIT_ERR 0x30a +#define SSD_LOG_PCIE_LINK_STATUS 0x30b +#define SSD_LOG_CTRL_RST_SYNC 0x30c +#define SSD_LOG_CLK_FAULT 0x30d +#define SSD_LOG_VOLT_FAULT 0x30e +#define SSD_LOG_SET_CAPACITY_END 0x30F +#define SSD_LOG_CLEAR_DATA_END 0x310 +#define SSD_LOG_RESET 0x311 +#define SSD_LOG_CAP_VOLT_FAULT 0x312 +#define SSD_LOG_CAP_LEARN_FAULT 0x313 +#define SSD_LOG_CAP_STATUS 0x314 +#define SSD_LOG_VOLT_STATUS 0x315 +#define SSD_LOG_INLET_OVER_TEMP 0x316 +#define SSD_LOG_INLET_NORMAL_TEMP 0x317 +#define SSD_LOG_FLASH_OVER_TEMP 0x318 +#define SSD_LOG_FLASH_NORMAL_TEMP 0x319 +#define SSD_LOG_CAP_SHORT_CIRCUIT 0x31a +#define SSD_LOG_SENSOR_FAULT 0x31b +#define SSD_LOG_ERASE_ALL 0x31c +#define SSD_LOG_ERASE_ALL_END 0x31d + + +/* sw log fifo depth */ +#define SSD_LOG_FIFO_SZ 1024 + + +/* done queue */ +static DEFINE_PER_CPU(struct list_head, ssd_doneq); +static DEFINE_PER_CPU(struct tasklet_struct, ssd_tasklet); + + +/* unloading driver */ +static volatile int ssd_exiting = 0; + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) +static struct class_simple *ssd_class; +#else +static struct class *ssd_class; +#endif + +static int ssd_cmajor = SSD_CMAJOR; + +/* ssd block device major, minors */ +static int ssd_major = SSD_MAJOR; +static int ssd_major_sl = SSD_MAJOR_SL; +static int ssd_minors = SSD_MINORS; + +/* ssd device list */ +static struct list_head ssd_list; +static unsigned long ssd_index_bits[SSD_MAX_DEV / BITS_PER_LONG + 1]; +static unsigned long ssd_index_bits_sl[SSD_MAX_DEV / BITS_PER_LONG + 1]; +static atomic_t ssd_nr; + +/* module param */ +enum ssd_drv_mode +{ + SSD_DRV_MODE_STANDARD = 0, /* full */ + SSD_DRV_MODE_DEBUG = 2, /* debug */ + SSD_DRV_MODE_BASE /* base only */ +}; + +enum ssd_int_mode +{ + SSD_INT_LEGACY = 0, + SSD_INT_MSI, + SSD_INT_MSIX +}; + +#if (defined SSD_MSIX) +#define SSD_INT_MODE_DEFAULT SSD_INT_MSIX +#elif (defined SSD_MSI) +#define SSD_INT_MODE_DEFAULT SSD_INT_MSI +#else +/* auto select the defaut int mode according to the kernel version*/ +/* suse 11 sp1 irqbalance bug: use msi instead*/ +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR >= 6) || (defined RHEL_MAJOR && RHEL_MAJOR == 5 && RHEL_MINOR >= 5)) +#define SSD_INT_MODE_DEFAULT SSD_INT_MSIX +#else +#define SSD_INT_MODE_DEFAULT SSD_INT_MSI +#endif +#endif + +static int mode = SSD_DRV_MODE_STANDARD; +static int status_mask = 0xFF; +static int int_mode = SSD_INT_MODE_DEFAULT; +static int threaded_irq = 0; +static int log_level = SSD_LOG_LEVEL_WARNING; +static int ot_protect = 1; +static int wmode = SSD_WMODE_DEFAULT; +static int finject = 0; + +module_param(mode, int, 0); +module_param(status_mask, int, 0); +module_param(int_mode, int, 0); +module_param(threaded_irq, int, 0); +module_param(log_level, int, 0); +module_param(ot_protect, int, 0); +module_param(wmode, int, 0); +module_param(finject, int, 0); + + +MODULE_PARM_DESC(mode, "driver mode, 0 - standard, 1 - debug, 2 - debug without IO, 3 - basic debug mode"); +MODULE_PARM_DESC(status_mask, "command status mask, 0 - without command error, 0xff - with command error"); +MODULE_PARM_DESC(int_mode, "preferred interrupt mode, 0 - legacy, 1 - msi, 2 - msix"); +MODULE_PARM_DESC(threaded_irq, "threaded irq, 0 - normal irq, 1 - threaded irq"); +MODULE_PARM_DESC(log_level, "log level to display, 0 - info and above, 1 - notice and above, 2 - warning and above, 3 - error only"); +MODULE_PARM_DESC(ot_protect, "over temperature protect, 0 - disable, 1 - enable"); +MODULE_PARM_DESC(wmode, "write mode, 0 - write buffer (with risk for the 6xx firmware), 1 - write buffer ex, 2 - write through, 3 - auto, 4 - default"); +MODULE_PARM_DESC(finject, "enable fault simulation, 0 - off, 1 - on, for debug purpose only"); + + +#ifndef MODULE +static int __init ssd_drv_mode(char *str) +{ + mode = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_status_mask(char *str) +{ + status_mask = (int)simple_strtoul(str, NULL, 16); + + return 1; +} + +static int __init ssd_int_mode(char *str) +{ + int_mode = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_threaded_irq(char *str) +{ + threaded_irq = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_log_level(char *str) +{ + log_level = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_ot_protect(char *str) +{ + ot_protect = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_wmode(char *str) +{ + wmode = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_finject(char *str) +{ + finject = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +__setup(MODULE_NAME"_mode=", ssd_drv_mode); +__setup(MODULE_NAME"_status_mask=", ssd_status_mask); +__setup(MODULE_NAME"_int_mode=", ssd_int_mode); +__setup(MODULE_NAME"_threaded_irq=", ssd_threaded_irq); +__setup(MODULE_NAME"_log_level=", ssd_log_level); +__setup(MODULE_NAME"_ot_protect=", ssd_ot_protect); +__setup(MODULE_NAME"_wmode=", ssd_wmode); +__setup(MODULE_NAME"_finject=", ssd_finject); +#endif + + +#ifdef CONFIG_PROC_FS +#include +#include + +#define SSD_PROC_DIR MODULE_NAME +#define SSD_PROC_INFO "info" + +static struct proc_dir_entry *ssd_proc_dir = NULL; +static struct proc_dir_entry *ssd_proc_info = NULL; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)) +static int ssd_proc_read(char *page, char **start, + off_t off, int count, int *eof, void *data) +{ + struct ssd_device *dev = NULL; + struct ssd_device *n = NULL; + uint64_t size; + int idx; + int len = 0; + //char type; //xx + + if (ssd_exiting) { + return 0; + } + + len += snprintf((page + len), (count - len), "Driver Version:\t%s\n", DRIVER_VERSION); + + list_for_each_entry_safe(dev, n, &ssd_list, list) { + idx = dev->idx + 1; + size = dev->hw_info.size ; + do_div(size, 1000000000); + + len += snprintf((page + len), (count - len), "\n"); + + len += snprintf((page + len), (count - len), "HIO %d Size:\t%uGB\n", idx, (uint32_t)size); + + len += snprintf((page + len), (count - len), "HIO %d Bridge FW VER:\t%03X\n", idx, dev->hw_info.bridge_ver); + if (dev->hw_info.ctrl_ver != 0) { + len += snprintf((page + len), (count - len), "HIO %d Controller FW VER:\t%03X\n", idx, dev->hw_info.ctrl_ver); + } + + len += snprintf((page + len), (count - len), "HIO %d PCB VER:\t.%c\n", idx, dev->hw_info.pcb_ver); + + if (dev->hw_info.upper_pcb_ver >= 'A') { + len += snprintf((page + len), (count - len), "HIO %d Upper PCB VER:\t.%c\n", idx, dev->hw_info.upper_pcb_ver); + } + + len += snprintf((page + len), (count - len), "HIO %d Device:\t%s\n", idx, dev->name); + } + + return len; +} + +#else + +static int ssd_proc_show(struct seq_file *m, void *v) +{ + struct ssd_device *dev = NULL; + struct ssd_device *n = NULL; + uint64_t size; + int idx; + + if (ssd_exiting) { + return 0; + } + + seq_printf(m, "Driver Version:\t%s\n", DRIVER_VERSION); + + list_for_each_entry_safe(dev, n, &ssd_list, list) { + idx = dev->idx + 1; + size = dev->hw_info.size ; + do_div(size, 1000000000); + + seq_printf(m, "\n"); + + seq_printf(m, "HIO %d Size:\t%uGB\n", idx, (uint32_t)size); + + seq_printf(m, "HIO %d Bridge FW VER:\t%03X\n", idx, dev->hw_info.bridge_ver); + if (dev->hw_info.ctrl_ver != 0) { + seq_printf(m, "HIO %d Controller FW VER:\t%03X\n", idx, dev->hw_info.ctrl_ver); + } + + seq_printf(m, "HIO %d PCB VER:\t.%c\n", idx, dev->hw_info.pcb_ver); + + if (dev->hw_info.upper_pcb_ver >= 'A') { + seq_printf(m, "HIO %d Upper PCB VER:\t.%c\n", idx, dev->hw_info.upper_pcb_ver); + } + + seq_printf(m, "HIO %d Device:\t%s\n", idx, dev->name); + } + + return 0; +} + +static int ssd_proc_open(struct inode *inode, struct file *file) +{ +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0)) + return single_open(file, ssd_proc_show, PDE(inode)->data); +#else + return single_open(file, ssd_proc_show, PDE_DATA(inode)); +#endif +} + +static const struct file_operations ssd_proc_fops = { + .open = ssd_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; +#endif + + +static void ssd_cleanup_proc(void) +{ + if (ssd_proc_info) { + remove_proc_entry(SSD_PROC_INFO, ssd_proc_dir); + ssd_proc_info = NULL; + } + if (ssd_proc_dir) { + remove_proc_entry(SSD_PROC_DIR, NULL); + ssd_proc_dir = NULL; + } +} +static int ssd_init_proc(void) +{ + ssd_proc_dir = proc_mkdir(SSD_PROC_DIR, NULL); + if (!ssd_proc_dir) + goto out_proc_mkdir; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)) + ssd_proc_info = create_proc_entry(SSD_PROC_INFO, S_IFREG | S_IRUGO | S_IWUSR, ssd_proc_dir); + if (!ssd_proc_info) + goto out_create_proc_entry; + + ssd_proc_info->read_proc = ssd_proc_read; + +/* kernel bug */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) + ssd_proc_info->owner = THIS_MODULE; +#endif +#else + ssd_proc_info = proc_create(SSD_PROC_INFO, 0600, ssd_proc_dir, &ssd_proc_fops); + if (!ssd_proc_info) + goto out_create_proc_entry; +#endif + + return 0; + +out_create_proc_entry: + remove_proc_entry(SSD_PROC_DIR, NULL); +out_proc_mkdir: + return -ENOMEM; +} + +#else +static void ssd_cleanup_proc(void) +{ + return; +} +static int ssd_init_proc(void) +{ + return 0; +} +#endif /* CONFIG_PROC_FS */ + +/* sysfs */ +static void ssd_unregister_sysfs(struct ssd_device *dev) +{ + return; +} + +static int ssd_register_sysfs(struct ssd_device *dev) +{ + return 0; +} + +static void ssd_cleanup_sysfs(void) +{ + return; +} + +static int ssd_init_sysfs(void) +{ + return 0; +} + +static inline void ssd_put_index(int slave, int index) +{ + unsigned long *index_bits = ssd_index_bits; + + if (slave) { + index_bits = ssd_index_bits_sl; + } + + if (test_and_clear_bit(index, index_bits)) { + atomic_dec(&ssd_nr); + } +} + +static inline int ssd_get_index(int slave) +{ + unsigned long *index_bits = ssd_index_bits; + int index; + + if (slave) { + index_bits = ssd_index_bits_sl; + } + +find_index: + if ((index = find_first_zero_bit(index_bits, SSD_MAX_DEV)) >= SSD_MAX_DEV) { + return -1; + } + + if (test_and_set_bit(index, index_bits)) { + goto find_index; + } + + atomic_inc(&ssd_nr); + + return index; +} + +static void ssd_cleanup_index(void) +{ + return; +} + +static int ssd_init_index(void) +{ + INIT_LIST_HEAD(&ssd_list); + atomic_set(&ssd_nr, 0); + memset(ssd_index_bits, 0, (SSD_MAX_DEV / BITS_PER_LONG + 1)); + memset(ssd_index_bits_sl, 0, (SSD_MAX_DEV / BITS_PER_LONG + 1)); + + return 0; +} + +static void ssd_set_dev_name(char *name, size_t size, int idx) +{ + if(idx < SSD_ALPHABET_NUM) { + snprintf(name, size, "%c", 'a'+idx); + } else { + idx -= SSD_ALPHABET_NUM; + snprintf(name, size, "%c%c", 'a'+(idx/SSD_ALPHABET_NUM), 'a'+(idx%SSD_ALPHABET_NUM)); + } +} + +/* pci register r&w */ +static inline void ssd_reg_write(void *addr, uint64_t val) +{ + iowrite32((uint32_t)val, addr); + iowrite32((uint32_t)(val >> 32), addr + 4); + wmb(); +} + +static inline uint64_t ssd_reg_read(void *addr) +{ + uint64_t val; + uint32_t val_lo, val_hi; + + val_lo = ioread32(addr); + val_hi = ioread32(addr + 4); + + rmb(); + val = val_lo | ((uint64_t)val_hi << 32); + + return val; +} + + +#define ssd_reg32_write(addr, val) writel(val, addr) +#define ssd_reg32_read(addr) readl(addr) + +/* alarm led */ +static void ssd_clear_alarm(struct ssd_device *dev) +{ + uint32_t val; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_LED_REG); + + /* firmware control */ + val &= ~0x2; + + ssd_reg32_write(dev->ctrlp + SSD_LED_REG, val); +} + +static void ssd_set_alarm(struct ssd_device *dev) +{ + uint32_t val; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_LED_REG); + + /* light up */ + val &= ~0x1; + /* software control */ + val |= 0x2; + + ssd_reg32_write(dev->ctrlp + SSD_LED_REG, val); +} + +#define u32_swap(x) \ + ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define u16_swap(x) \ + ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ff) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00) >> 8) )) + + +#if 0 +/* No lock, for init only*/ +static int ssd_spi_read_id(struct ssd_device *dev, uint32_t *id) +{ + uint32_t val; + unsigned long st; + int ret = 0; + + if (!dev || !id) { + return -EINVAL; + } + + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_ID); + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + + st = jiffies; + for (;;) { + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + if (val == 0x1000000) { + break; + } + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_ID); + *id = val; + +out: + return ret; +} +#endif + +/* spi access */ +static int ssd_init_spi(struct ssd_device *dev) +{ + uint32_t val; + unsigned long st; + int ret = 0; + + mutex_lock(&dev->spi_mutex); + st = jiffies; + for(;;) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_STATUS); + + do { + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } while (val != 0x1000000); + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_STATUS); + if (!(val & 0x1)) { + break; + } + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + +out: + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (val & 0x1) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_CLSR); + } + } + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_DISABLE); + mutex_unlock(&dev->spi_mutex); + + ret = 0; + + return ret; +} + +static int ssd_spi_page_read(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size) +{ + uint32_t val; + uint32_t rlen = 0; + unsigned long st; + int ret = 0; + + if (!dev || !buf) { + return -EINVAL; + } + + if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 || + ((uint64_t)off + (uint64_t)size) > dev->rom_info.size || size > dev->rom_info.page_size) { + return -EINVAL; + } + + mutex_lock(&dev->spi_mutex); + while (rlen < size) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD_HI, ((off + rlen) >> 24)); + wmb(); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, (((off + rlen) << 8) | SSD_SPI_CMD_READ)); + + (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + + st = jiffies; + for (;;) { + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + if (val == 0x1000000) { + break; + } + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_RDATA); + *(uint32_t *)(buf + rlen)= u32_swap(val); + + rlen += sizeof(uint32_t); + } + +out: + mutex_unlock(&dev->spi_mutex); + return ret; +} + +static int ssd_spi_page_write(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size) +{ + uint32_t val; + uint32_t wlen; + unsigned long st; + int i; + int ret = 0; + + if (!dev || !buf) { + return -EINVAL; + } + + if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 || + ((uint64_t)off + (uint64_t)size) > dev->rom_info.size || size > dev->rom_info.page_size || + (off / dev->rom_info.page_size) != ((off + size - 1) / dev->rom_info.page_size)) { + return -EINVAL; + } + + mutex_lock(&dev->spi_mutex); + + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_ENABLE); + + wlen = size / sizeof(uint32_t); + for (i=0; i<(int)wlen; i++) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_WDATA, u32_swap(*((uint32_t *)buf + i))); + } + + wmb(); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD_HI, (off >> 24)); + wmb(); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, ((off << 8) | SSD_SPI_CMD_PROGRAM)); + + udelay(1); + + st = jiffies; + for (;;) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_STATUS); + do { + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } while (val != 0x1000000); + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_STATUS); + if (!(val & 0x1)) { + break; + } + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if ((val >> 6) & 0x1) { + ret = -EIO; + goto out; + } + } + +out: + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (val & 0x1) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_CLSR); + } + } + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_DISABLE); + + mutex_unlock(&dev->spi_mutex); + + return ret; +} + +static int ssd_spi_block_erase(struct ssd_device *dev, uint32_t off) +{ + uint32_t val; + unsigned long st; + int ret = 0; + + if (!dev) { + return -EINVAL; + } + + if ((off % dev->rom_info.block_size) != 0 || off >= dev->rom_info.size) { + return -EINVAL; + } + + mutex_lock(&dev->spi_mutex); + + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_ENABLE); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_ENABLE); + + wmb(); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD_HI, (off >> 24)); + wmb(); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, ((off << 8) | SSD_SPI_CMD_ERASE)); + + st = jiffies; + for (;;) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_STATUS); + + do { + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } while (val != 0x1000000); + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_STATUS); + if (!(val & 0x1)) { + break; + } + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if ((val >> 5) & 0x1) { + ret = -EIO; + goto out; + } + } + +out: + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (val & 0x1) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_CLSR); + } + } + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_DISABLE); + + mutex_unlock(&dev->spi_mutex); + + return ret; +} + +static int ssd_spi_read(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size) +{ + uint32_t len = 0; + uint32_t roff; + uint32_t rsize; + int ret = 0; + + if (!dev || !buf) { + return -EINVAL; + } + + if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 || + ((uint64_t)off + (uint64_t)size) > dev->rom_info.size) { + return -EINVAL; + } + + while (len < size) { + roff = (off + len) % dev->rom_info.page_size; + rsize = dev->rom_info.page_size - roff; + if ((size - len) < rsize) { + rsize = (size - len); + } + roff = off + len; + + ret = ssd_spi_page_read(dev, (buf + len), roff, rsize); + if (ret) { + goto out; + } + + len += rsize; + + cond_resched(); + } + +out: + return ret; +} + +static int ssd_spi_write(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size) +{ + uint32_t len = 0; + uint32_t woff; + uint32_t wsize; + int ret = 0; + + if (!dev || !buf) { + return -EINVAL; + } + + if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 || + ((uint64_t)off + (uint64_t)size) > dev->rom_info.size) { + return -EINVAL; + } + + while (len < size) { + woff = (off + len) % dev->rom_info.page_size; + wsize = dev->rom_info.page_size - woff; + if ((size - len) < wsize) { + wsize = (size - len); + } + woff = off + len; + + ret = ssd_spi_page_write(dev, (buf + len), woff, wsize); + if (ret) { + goto out; + } + + len += wsize; + + cond_resched(); + } + +out: + return ret; +} + +static int ssd_spi_erase(struct ssd_device *dev, uint32_t off, uint32_t size) +{ + uint32_t len = 0; + uint32_t eoff; + int ret = 0; + + if (!dev) { + return -EINVAL; + } + + if (size == 0 || ((uint64_t)off + (uint64_t)size) > dev->rom_info.size || + (off % dev->rom_info.block_size) != 0 || (size % dev->rom_info.block_size) != 0) { + return -EINVAL; + } + + while (len < size) { + eoff = (off + len); + + ret = ssd_spi_block_erase(dev, eoff); + if (ret) { + goto out; + } + + len += dev->rom_info.block_size; + + cond_resched(); + } + +out: + return ret; +} + +/* i2c access */ +static uint32_t __ssd_i2c_reg32_read(void *addr) +{ + return ssd_reg32_read(addr); +} + +static void __ssd_i2c_reg32_write(void *addr, uint32_t val) +{ + ssd_reg32_write(addr, val); + ssd_reg32_read(addr); +} + +static int __ssd_i2c_clear(struct ssd_device *dev, uint8_t saddr) +{ + ssd_i2c_ctrl_t ctrl; + ssd_i2c_data_t data; + uint8_t status = 0; + int nr_data = 0; + unsigned long st; + int ret = 0; + +check_status: + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_STATUS_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + st = jiffies; + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + status = data.bits.rdata; + + if (!(status & 0x4)) { + /* clear read fifo data */ + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_DATA_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + st = jiffies; + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + + nr_data++; + if (nr_data <= SSD_I2C_MAX_DATA) { + goto check_status; + } else { + goto out_reset; + } + } + + if (status & 0x3) { + /* clear int */ + ctrl.bits.wdata = 0x04; + ctrl.bits.addr = SSD_I2C_CMD_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + } + + if (!(status & 0x8)) { +out_reset: + /* reset i2c controller */ + ctrl.bits.wdata = 0x0; + ctrl.bits.addr = SSD_I2C_RESET_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + } + +out: + return ret; +} + +static int ssd_i2c_write(struct ssd_device *dev, uint8_t saddr, uint8_t size, uint8_t *buf) +{ + ssd_i2c_ctrl_t ctrl; + ssd_i2c_data_t data; + uint8_t off = 0; + uint8_t status = 0; + unsigned long st; + int ret = 0; + + mutex_lock(&dev->i2c_mutex); + + ctrl.val = 0; + + /* slave addr */ + ctrl.bits.wdata = saddr; + ctrl.bits.addr = SSD_I2C_SADDR_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* data */ + while (off < size) { + ctrl.bits.wdata = buf[off]; + ctrl.bits.addr = SSD_I2C_DATA_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + off++; + } + + /* write */ + ctrl.bits.wdata = 0x01; + ctrl.bits.addr = SSD_I2C_CMD_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* wait */ + st = jiffies; + for (;;) { + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_STATUS_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + status = data.bits.rdata; + if (status & 0x1) { + break; + } + + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + if (!(status & 0x1)) { + ret = -1; + goto out_clear; + } + + /* busy ? */ + if (status & 0x20) { + ret = -2; + goto out_clear; + } + + /* ack ? */ + if (status & 0x10) { + ret = -3; + goto out_clear; + } + + /* clear */ +out_clear: + if (__ssd_i2c_clear(dev, saddr)) { + if (!ret) ret = -4; + } + + mutex_unlock(&dev->i2c_mutex); + + return ret; +} + +static int ssd_i2c_read(struct ssd_device *dev, uint8_t saddr, uint8_t size, uint8_t *buf) +{ + ssd_i2c_ctrl_t ctrl; + ssd_i2c_data_t data; + uint8_t off = 0; + uint8_t status = 0; + unsigned long st; + int ret = 0; + + mutex_lock(&dev->i2c_mutex); + + ctrl.val = 0; + + /* slave addr */ + ctrl.bits.wdata = saddr; + ctrl.bits.addr = SSD_I2C_SADDR_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* read len */ + ctrl.bits.wdata = size; + ctrl.bits.addr = SSD_I2C_LEN_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* read */ + ctrl.bits.wdata = 0x02; + ctrl.bits.addr = SSD_I2C_CMD_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* wait */ + st = jiffies; + for (;;) { + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_STATUS_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + status = data.bits.rdata; + if (status & 0x2) { + break; + } + + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + if (!(status & 0x2)) { + ret = -1; + goto out_clear; + } + + /* busy ? */ + if (status & 0x20) { + ret = -2; + goto out_clear; + } + + /* ack ? */ + if (status & 0x10) { + ret = -3; + goto out_clear; + } + + /* data */ + while (off < size) { + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_DATA_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + st = jiffies; + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + buf[off] = data.bits.rdata; + + off++; + } + + /* clear */ +out_clear: + if (__ssd_i2c_clear(dev, saddr)) { + if (!ret) ret = -4; + } + + mutex_unlock(&dev->i2c_mutex); + + return ret; +} + +static int ssd_i2c_write_read(struct ssd_device *dev, uint8_t saddr, uint8_t wsize, uint8_t *wbuf, uint8_t rsize, uint8_t *rbuf) +{ + ssd_i2c_ctrl_t ctrl; + ssd_i2c_data_t data; + uint8_t off = 0; + uint8_t status = 0; + unsigned long st; + int ret = 0; + + mutex_lock(&dev->i2c_mutex); + + ctrl.val = 0; + + /* slave addr */ + ctrl.bits.wdata = saddr; + ctrl.bits.addr = SSD_I2C_SADDR_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* data */ + off = 0; + while (off < wsize) { + ctrl.bits.wdata = wbuf[off]; + ctrl.bits.addr = SSD_I2C_DATA_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + off++; + } + + /* read len */ + ctrl.bits.wdata = rsize; + ctrl.bits.addr = SSD_I2C_LEN_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* write -> read */ + ctrl.bits.wdata = 0x03; + ctrl.bits.addr = SSD_I2C_CMD_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* wait */ + st = jiffies; + for (;;) { + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_STATUS_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + status = data.bits.rdata; + if (status & 0x2) { + break; + } + + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + if (!(status & 0x2)) { + ret = -1; + goto out_clear; + } + + /* busy ? */ + if (status & 0x20) { + ret = -2; + goto out_clear; + } + + /* ack ? */ + if (status & 0x10) { + ret = -3; + goto out_clear; + } + + /* data */ + off = 0; + while (off < rsize) { + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_DATA_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + st = jiffies; + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + rbuf[off] = data.bits.rdata; + + off++; + } + + /* clear */ +out_clear: + if (__ssd_i2c_clear(dev, saddr)) { + if (!ret) ret = -4; + } + mutex_unlock(&dev->i2c_mutex); + + return ret; +} + +static int ssd_smbus_send_byte(struct ssd_device *dev, uint8_t saddr, uint8_t *buf) +{ + int i = 0; + int ret = 0; + + for (;;) { + ret = ssd_i2c_write(dev, saddr, 1, buf); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_receive_byte(struct ssd_device *dev, uint8_t saddr, uint8_t *buf) +{ + int i = 0; + int ret = 0; + + for (;;) { + ret = ssd_i2c_read(dev, saddr, 1, buf); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_write_byte(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + memcpy((smb_data + 1), buf, 1); + + for (;;) { + ret = ssd_i2c_write(dev, saddr, 2, smb_data); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_read_byte(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + + for (;;) { + ret = ssd_i2c_write_read(dev, saddr, 1, smb_data, 1, buf); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_write_word(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + memcpy((smb_data + 1), buf, 2); + + for (;;) { + ret = ssd_i2c_write(dev, saddr, 3, smb_data); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_read_word(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + + for (;;) { + ret = ssd_i2c_write_read(dev, saddr, 1, smb_data, 2, buf); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_write_block(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t size, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + smb_data[1] = size; + memcpy((smb_data + 2), buf, size); + + for (;;) { + ret = ssd_i2c_write(dev, saddr, (2 + size), smb_data); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_read_block(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t size, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + uint8_t rsize; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + + for (;;) { + ret = ssd_i2c_write_read(dev, saddr, 1, smb_data, (SSD_SMBUS_BLOCK_MAX + 1), (smb_data + 1)); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + if (ret) { + return ret; + } + + rsize = smb_data[1]; + + if (rsize > size ) { + rsize = size; + } + + memcpy(buf, (smb_data + 2), rsize); + + return 0; +} + + +static int ssd_gen_swlog(struct ssd_device *dev, uint16_t event, uint32_t data); + +/* sensor */ +static int ssd_init_lm75(struct ssd_device *dev, uint8_t saddr) +{ + uint8_t conf = 0; + int ret = 0; + + ret = ssd_smbus_read_byte(dev, saddr, SSD_LM75_REG_CONF, &conf); + if (ret) { + goto out; + } + + conf &= (uint8_t)(~1u); + + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM75_REG_CONF, &conf); + if (ret) { + goto out; + } + +out: + return ret; +} + +static int ssd_lm75_read(struct ssd_device *dev, uint8_t saddr, uint16_t *data) +{ + uint16_t val = 0; + int ret; + + ret = ssd_smbus_read_word(dev, saddr, SSD_LM75_REG_TEMP, (uint8_t *)&val); + if (ret) { + return ret; + } + + *data = u16_swap(val); + + return 0; +} + +static int ssd_init_lm80(struct ssd_device *dev, uint8_t saddr) +{ + uint8_t val; + uint8_t low, high; + int i; + int ret = 0; + + /* init */ + val = 0x80; + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_CONFIG, &val); + if (ret) { + goto out; + } + + /* 11-bit temp */ + val = 0x08; + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_RES, &val); + if (ret) { + goto out; + } + + /* set volt limit */ + for (i=0; ihw_info.nr_ctrl <= 1 && SSD_LM80_IN_1V2 == i) { + high = 0xFF; + low = 0; + } + + /* high limit */ + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_IN_MAX(i), &high); + if (ret) { + goto out; + } + + /* low limit*/ + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_IN_MIN(i), &low); + if (ret) { + goto out; + } + } + + /* set interrupt mask: allow volt in interrupt except cap in*/ + val = 0x81; + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK1, &val); + if (ret) { + goto out; + } + + /* set interrupt mask: disable others */ + val = 0xFF; + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK2, &val); + if (ret) { + goto out; + } + + /* start */ + val = 0x03; + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_CONFIG, &val); + if (ret) { + goto out; + } + +out: + return ret; +} + +static int ssd_lm80_enable_in(struct ssd_device *dev, uint8_t saddr, int idx) +{ + uint8_t val = 0; + int ret = 0; + + if (idx >= SSD_LM80_IN_NR || idx < 0) { + return -EINVAL; + } + + ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_MASK1, &val); + if (ret) { + goto out; + } + + val &= ~(1UL << (uint32_t)idx); + + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK1, &val); + if (ret) { + goto out; + } + +out: + return ret; +} + +static int ssd_lm80_disable_in(struct ssd_device *dev, uint8_t saddr, int idx) +{ + uint8_t val = 0; + int ret = 0; + + if (idx >= SSD_LM80_IN_NR || idx < 0) { + return -EINVAL; + } + + ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_MASK1, &val); + if (ret) { + goto out; + } + + val |= (1UL << (uint32_t)idx); + + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK1, &val); + if (ret) { + goto out; + } + +out: + return ret; +} + +static int ssd_lm80_read_temp(struct ssd_device *dev, uint8_t saddr, uint16_t *data) +{ + uint16_t val = 0; + int ret; + + ret = ssd_smbus_read_word(dev, saddr, SSD_LM80_REG_TEMP, (uint8_t *)&val); + if (ret) { + return ret; + } + + *data = u16_swap(val); + + return 0; +} + +static int ssd_lm80_check_event(struct ssd_device *dev, uint8_t saddr) +{ + uint32_t volt; + uint16_t val = 0, status; + uint8_t alarm1 = 0, alarm2 = 0; + int i; + int ret = 0; + + /* read interrupt status to clear interrupt */ + ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_ALARM1, &alarm1); + if (ret) { + goto out; + } + + ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_ALARM2, &alarm2); + if (ret) { + goto out; + } + + status = (uint16_t)alarm1 | ((uint16_t)alarm2 << 8); + + /* parse inetrrupt status */ + for (i=0; i> (uint32_t)i) & 0x1)) { + if (test_and_clear_bit(SSD_HWMON_LM80(i), &dev->hwmon)) { + /* enable INx irq */ + ret = ssd_lm80_enable_in(dev, saddr, i); + if (ret) { + goto out; + } + } + + continue; + } + + /* disable INx irq */ + ret = ssd_lm80_disable_in(dev, saddr, i); + if (ret) { + goto out; + } + + if (test_and_set_bit(SSD_HWMON_LM80(i), &dev->hwmon)) { + continue; + } + + ret = ssd_smbus_read_word(dev, saddr, SSD_LM80_REG_IN(i), (uint8_t *)&val); + if (ret) { + goto out; + } + + volt = SSD_LM80_CONVERT_VOLT(u16_swap(val)); + + switch (i) { + case SSD_LM80_IN_CAP: { + if (0 == volt) { + ssd_gen_swlog(dev, SSD_LOG_CAP_SHORT_CIRCUIT, 0); + } else { + ssd_gen_swlog(dev, SSD_LOG_CAP_VOLT_FAULT, SSD_PL_CAP_VOLT(volt)); + } + break; + } + + case SSD_LM80_IN_1V2: + case SSD_LM80_IN_1V2a: + case SSD_LM80_IN_1V5: + case SSD_LM80_IN_1V8: { + ssd_gen_swlog(dev, SSD_LOG_VOLT_STATUS, SSD_VOLT_LOG_DATA(i, 0, volt)); + break; + } + case SSD_LM80_IN_FPGA_3V3: + case SSD_LM80_IN_3V3: { + ssd_gen_swlog(dev, SSD_LOG_VOLT_STATUS, SSD_VOLT_LOG_DATA(i, 0, SSD_LM80_3V3_VOLT(volt))); + break; + } + default: + break; + } + } + +out: + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, (uint32_t)saddr); + } + } else { + test_and_clear_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon); + } + return ret; +} + +static int ssd_init_sensor(struct ssd_device *dev) +{ + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + goto out; + } + + ret = ssd_init_lm75(dev, SSD_SENSOR_LM75_SADDRESS); + if (ret) { + hio_warn("%s: init lm75 failed\n", dev->name); + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM75), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM75_SADDRESS); + } + goto out; + } + + if (dev->hw_info.pcb_ver >= 'B' || dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_HHHL) { + ret = ssd_init_lm80(dev, SSD_SENSOR_LM80_SADDRESS); + if (ret) { + hio_warn("%s: init lm80 failed\n", dev->name); + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +/* board volt */ +static int ssd_mon_boardvolt(struct ssd_device *dev) +{ + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + return 0; + } + + return ssd_lm80_check_event(dev, SSD_SENSOR_LM80_SADDRESS); +} + +/* temperature */ +static int ssd_mon_temp(struct ssd_device *dev) +{ + int cur; + uint16_t val = 0; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + return 0; + } + + /* inlet */ + ret = ssd_lm80_read_temp(dev, SSD_SENSOR_LM80_SADDRESS, &val); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + test_and_clear_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon); + + cur = SSD_SENSOR_CONVERT_TEMP(val); + if (cur >= SSD_INLET_OT_TEMP) { + if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_INLET), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_INLET_OVER_TEMP, (uint32_t)cur); + } + } else if(cur < SSD_INLET_OT_HYST) { + if (test_and_clear_bit(SSD_HWMON_TEMP(SSD_TEMP_INLET), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_INLET_NORMAL_TEMP, (uint32_t)cur); + } + } + + /* flash */ + ret = ssd_lm75_read(dev, SSD_SENSOR_LM75_SADDRESS, &val); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM75), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM75_SADDRESS); + } + goto out; + } + test_and_clear_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM75), &dev->hwmon); + + cur = SSD_SENSOR_CONVERT_TEMP(val); + if (cur >= SSD_FLASH_OT_TEMP) { + if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_FLASH), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_FLASH_OVER_TEMP, (uint32_t)cur); + } + } else if(cur < SSD_FLASH_OT_HYST) { + if (test_and_clear_bit(SSD_HWMON_TEMP(SSD_TEMP_FLASH), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_FLASH_NORMAL_TEMP, (uint32_t)cur); + } + } + +out: + return ret; +} + +/* cmd tag */ +static inline void ssd_put_tag(struct ssd_device *dev, int tag) +{ + test_and_clear_bit(tag, dev->tag_map); + wake_up(&dev->tag_wq); +} + +static inline int ssd_get_tag(struct ssd_device *dev, int wait) +{ + int tag; + +find_tag: + while ((tag = find_first_zero_bit(dev->tag_map, dev->hw_info.cmd_fifo_sz)) >= atomic_read(&dev->queue_depth)) { + DEFINE_WAIT(__wait); + + if (!wait) { + return -1; + } + + prepare_to_wait_exclusive(&dev->tag_wq, &__wait, TASK_UNINTERRUPTIBLE); + schedule(); + + finish_wait(&dev->tag_wq, &__wait); + } + + if (test_and_set_bit(tag, dev->tag_map)) { + goto find_tag; + } + + return tag; +} + +static void ssd_barrier_put_tag(struct ssd_device *dev, int tag) +{ + test_and_clear_bit(tag, dev->tag_map); +} + +static int ssd_barrier_get_tag(struct ssd_device *dev) +{ + int tag = 0; + + if (test_and_set_bit(tag, dev->tag_map)) { + return -1; + } + + return tag; +} + +static void ssd_barrier_end(struct ssd_device *dev) +{ + atomic_set(&dev->queue_depth, dev->hw_info.cmd_fifo_sz); + wake_up_all(&dev->tag_wq); + + mutex_unlock(&dev->barrier_mutex); +} + +static int ssd_barrier_start(struct ssd_device *dev) +{ + int i; + + mutex_lock(&dev->barrier_mutex); + + atomic_set(&dev->queue_depth, 0); + + for (i=0; itag_map, dev->hw_info.cmd_fifo_sz) >= dev->hw_info.cmd_fifo_sz) { + return 0; + } + + __set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + } + + atomic_set(&dev->queue_depth, dev->hw_info.cmd_fifo_sz); + wake_up_all(&dev->tag_wq); + + mutex_unlock(&dev->barrier_mutex); + + return -EBUSY; +} + +static int ssd_busy(struct ssd_device *dev) +{ + if (find_first_bit(dev->tag_map, dev->hw_info.cmd_fifo_sz) >= dev->hw_info.cmd_fifo_sz) { + return 0; + } + + return 1; +} + +static int ssd_wait_io(struct ssd_device *dev) +{ + int i; + + for (i=0; itag_map, dev->hw_info.cmd_fifo_sz) >= dev->hw_info.cmd_fifo_sz) { + return 0; + } + + __set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + } + + return -EBUSY; +} + +#if 0 +static int ssd_in_barrier(struct ssd_device *dev) +{ + return (0 == atomic_read(&dev->queue_depth)); +} +#endif + +static void ssd_cleanup_tag(struct ssd_device *dev) +{ + kfree(dev->tag_map); +} + +static int ssd_init_tag(struct ssd_device *dev) +{ + int nr_ulongs = ALIGN(dev->hw_info.cmd_fifo_sz, BITS_PER_LONG) / BITS_PER_LONG; + + mutex_init(&dev->barrier_mutex); + + atomic_set(&dev->queue_depth, dev->hw_info.cmd_fifo_sz); + + dev->tag_map = kmalloc(nr_ulongs * sizeof(unsigned long), GFP_ATOMIC); + if (!dev->tag_map) { + return -ENOMEM; + } + + memset(dev->tag_map, 0, nr_ulongs * sizeof(unsigned long)); + + init_waitqueue_head(&dev->tag_wq); + + return 0; +} + +/* io stat */ +static void ssd_end_io_acct(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = cmd->dev; + struct bio *bio = cmd->bio; + unsigned long dur = jiffies - cmd->start_time; + int rw = bio_data_dir(bio); + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6 && RHEL_MINOR >= 7)) + int cpu = part_stat_lock(); + struct hd_struct *part = disk_map_sector_rcu(dev->gd, bio_start(bio)); + part_round_stats(cpu, part); + part_stat_add(cpu, part, ticks[rw], dur); + part_dec_in_flight(part, rw); + part_stat_unlock(); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)) + int cpu = part_stat_lock(); + struct hd_struct *part = &dev->gd->part0; + part_round_stats(cpu, part); + part_stat_add(cpu, part, ticks[rw], dur); + part_stat_unlock(); + part->in_flight[rw] = atomic_dec_return(&dev->in_flight[rw]); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14)) + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + disk_stat_add(dev->gd, ticks[rw], dur); + dev->gd->in_flight = atomic_dec_return(&dev->in_flight[0]); +#else + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + if (rw == WRITE) { + disk_stat_add(dev->gd, write_ticks, dur); + } else { + disk_stat_add(dev->gd, read_ticks, dur); + } + dev->gd->in_flight = atomic_dec_return(&dev->in_flight[0]); +#endif +} + +static void ssd_start_io_acct(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = cmd->dev; + struct bio *bio = cmd->bio; + int rw = bio_data_dir(bio); + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6 && RHEL_MINOR >= 7)) + int cpu = part_stat_lock(); + struct hd_struct *part = disk_map_sector_rcu(dev->gd, bio_start(bio)); + part_round_stats(cpu, part); + part_stat_inc(cpu, part, ios[rw]); + part_stat_add(cpu, part, sectors[rw], bio_sectors(bio)); + part_inc_in_flight(part, rw); + part_stat_unlock(); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)) + int cpu = part_stat_lock(); + struct hd_struct *part = &dev->gd->part0; + part_round_stats(cpu, part); + part_stat_inc(cpu, part, ios[rw]); + part_stat_add(cpu, part, sectors[rw], bio_sectors(bio)); + part_stat_unlock(); + part->in_flight[rw] = atomic_inc_return(&dev->in_flight[rw]); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14)) + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + disk_stat_inc(dev->gd, ios[rw]); + disk_stat_add(dev->gd, sectors[rw], bio_sectors(bio)); + dev->gd->in_flight = atomic_inc_return(&dev->in_flight[0]); +#else + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + if (rw == WRITE) { + disk_stat_inc(dev->gd, writes); + disk_stat_add(dev->gd, write_sectors, bio_sectors(bio)); + } else { + disk_stat_inc(dev->gd, reads); + disk_stat_add(dev->gd, read_sectors, bio_sectors(bio)); + } + dev->gd->in_flight = atomic_inc_return(&dev->in_flight[0]); +#endif + + cmd->start_time = jiffies; +} + +/* io */ +static void ssd_queue_bio(struct ssd_device *dev, struct bio *bio) +{ + spin_lock(&dev->sendq_lock); + ssd_blist_add(&dev->sendq, bio); + spin_unlock(&dev->sendq_lock); + + atomic_inc(&dev->in_sendq); + wake_up(&dev->send_waitq); +} + +static inline void ssd_end_request(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = cmd->dev; + struct bio *bio = cmd->bio; + int errors = cmd->errors; + int tag = cmd->tag; + + if (bio) { +#if (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))) + if (!(bio->bi_rw & REQ_DISCARD)) { + ssd_end_io_acct(cmd); + if (!cmd->flag) { + pci_unmap_sg(dev->pdev, cmd->sgl, cmd->nsegs, + bio_data_dir(bio) == READ ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE); + } + } +#elif (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32))) + if (!bio_rw_flagged(bio, BIO_RW_DISCARD)) { + ssd_end_io_acct(cmd); + if (!cmd->flag) { + pci_unmap_sg(dev->pdev, cmd->sgl, cmd->nsegs, + bio_data_dir(bio) == READ ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE); + } + } +#else + ssd_end_io_acct(cmd); + + if (!cmd->flag) { + pci_unmap_sg(dev->pdev, cmd->sgl, cmd->nsegs, + bio_data_dir(bio) == READ ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE); + } +#endif + + cmd->bio = NULL; + ssd_put_tag(dev, tag); + + if (SSD_INT_MSIX == dev->int_mode || tag < 16 || errors) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, errors); +#else + bio_endio(bio, bio->bi_size, errors); +#endif + } else /* if (bio->bi_idx >= bio->bi_vcnt)*/ { + spin_lock(&dev->doneq_lock); + ssd_blist_add(&dev->doneq, bio); + spin_unlock(&dev->doneq_lock); + + atomic_inc(&dev->in_doneq); + wake_up(&dev->done_waitq); + } + } else { + if (cmd->waiting) { + complete(cmd->waiting); + } + } +} + +static void ssd_end_timeout_request(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = cmd->dev; + struct ssd_rw_msg *msg = (struct ssd_rw_msg *)cmd->msg; + int i; + + for (i=0; inr_queue; i++) { + disable_irq(dev->entry[i].vector); + } + + atomic_inc(&dev->tocnt); + //if (cmd->bio) { + hio_err("%s: cmd timeout: tag %d fun %#x\n", dev->name, msg->tag, msg->fun); + cmd->errors = -ETIMEDOUT; + ssd_end_request(cmd); + //} + + for (i=0; inr_queue; i++) { + enable_irq(dev->entry[i].vector); + } + + /* alarm led */ + ssd_set_alarm(dev); +} + +/* cmd timer */ +static void ssd_cmd_add_timer(struct ssd_cmd *cmd, int timeout, void (*complt)(struct ssd_cmd *)) +{ + init_timer(&cmd->cmd_timer); + + cmd->cmd_timer.data = (unsigned long)cmd; + cmd->cmd_timer.expires = jiffies + timeout; + cmd->cmd_timer.function = (void (*)(unsigned long)) complt; + + add_timer(&cmd->cmd_timer); +} + +static int ssd_cmd_del_timer(struct ssd_cmd *cmd) +{ + return del_timer(&cmd->cmd_timer); +} + +static void ssd_add_timer(struct timer_list *timer, int timeout, void (*complt)(void *), void *data) +{ + init_timer(timer); + + timer->data = (unsigned long)data; + timer->expires = jiffies + timeout; + timer->function = (void (*)(unsigned long)) complt; + + add_timer(timer); +} + +static int ssd_del_timer(struct timer_list *timer) +{ + return del_timer(timer); +} + +static void ssd_cmd_timeout(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = cmd->dev; + uint32_t msg = *(uint32_t *)cmd->msg; + + ssd_end_timeout_request(cmd); + + ssd_gen_swlog(dev, SSD_LOG_TIMEOUT, msg); +} + + +static void __ssd_done(unsigned long data) +{ + struct ssd_cmd *cmd; + LIST_HEAD(localq); + + local_irq_disable(); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0)) + list_splice_init(&__get_cpu_var(ssd_doneq), &localq); +#else + list_splice_init(this_cpu_ptr(&ssd_doneq), &localq); +#endif + local_irq_enable(); + + while (!list_empty(&localq)) { + cmd = list_entry(localq.next, struct ssd_cmd, list); + list_del_init(&cmd->list); + + ssd_end_request(cmd); + } +} + +static void __ssd_done_db(unsigned long data) +{ + struct ssd_cmd *cmd; + struct ssd_device *dev; + struct bio *bio; + LIST_HEAD(localq); + + local_irq_disable(); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0)) + list_splice_init(&__get_cpu_var(ssd_doneq), &localq); +#else + list_splice_init(this_cpu_ptr(&ssd_doneq), &localq); +#endif + local_irq_enable(); + + while (!list_empty(&localq)) { + cmd = list_entry(localq.next, struct ssd_cmd, list); + list_del_init(&cmd->list); + + dev = (struct ssd_device *)cmd->dev; + bio = cmd->bio; + + if (bio) { + sector_t off = dev->db_info.data.loc.off; + uint32_t len = dev->db_info.data.loc.len; + + switch (dev->db_info.type) { + case SSD_DEBUG_READ_ERR: + if (bio_data_dir(bio) == READ && + !((off + len) <= bio_start(bio) || off >= (bio_start(bio) + bio_sectors(bio)))) { + cmd->errors = -EIO; + } + break; + case SSD_DEBUG_WRITE_ERR: + if (bio_data_dir(bio) == WRITE && + !((off + len) <= bio_start(bio) || off >= (bio_start(bio) + bio_sectors(bio)))) { + cmd->errors = -EROFS; + } + break; + case SSD_DEBUG_RW_ERR: + if (!((off + len) <= bio_start(bio) || off >= (bio_start(bio) + bio_sectors(bio)))) { + if (bio_data_dir(bio) == READ) { + cmd->errors = -EIO; + } else { + cmd->errors = -EROFS; + } + } + break; + default: + break; + } + } + + ssd_end_request(cmd); + } +} + +static inline void ssd_done_bh(struct ssd_cmd *cmd) +{ + unsigned long flags = 0; + + if (unlikely(!ssd_cmd_del_timer(cmd))) { + struct ssd_device *dev = cmd->dev; + struct ssd_rw_msg *msg = (struct ssd_rw_msg *)cmd->msg; + hio_err("%s: unknown cmd: tag %d fun %#x\n", dev->name, msg->tag, msg->fun); + + /* alarm led */ + ssd_set_alarm(dev); + return; + } + + local_irq_save(flags); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0)) + list_add_tail(&cmd->list, &__get_cpu_var(ssd_doneq)); + tasklet_hi_schedule(&__get_cpu_var(ssd_tasklet)); +#else + list_add_tail(&cmd->list, this_cpu_ptr(&ssd_doneq)); + tasklet_hi_schedule(this_cpu_ptr(&ssd_tasklet)); +#endif + local_irq_restore(flags); + + return; +} + +static inline void ssd_done(struct ssd_cmd *cmd) +{ + if (unlikely(!ssd_cmd_del_timer(cmd))) { + struct ssd_device *dev = cmd->dev; + struct ssd_rw_msg *msg = (struct ssd_rw_msg *)cmd->msg; + hio_err("%s: unknown cmd: tag %d fun %#x\n", dev->name, msg->tag, msg->fun); + + /* alarm led */ + ssd_set_alarm(dev); + return; + } + + ssd_end_request(cmd); + + return; +} + +static inline void ssd_dispatch_cmd(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = (struct ssd_device *)cmd->dev; + + ssd_cmd_add_timer(cmd, SSD_CMD_TIMEOUT, ssd_cmd_timeout); + + spin_lock(&dev->cmd_lock); + ssd_reg_write(dev->ctrlp + SSD_REQ_FIFO_REG, cmd->msg_dma); + spin_unlock(&dev->cmd_lock); +} + +static inline void ssd_send_cmd(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = (struct ssd_device *)cmd->dev; + + ssd_cmd_add_timer(cmd, SSD_CMD_TIMEOUT, ssd_cmd_timeout); + + ssd_reg32_write(dev->ctrlp + SSD_REQ_FIFO_REG, ((uint32_t)cmd->tag | ((uint32_t)cmd->nsegs << 16))); +} + +static inline void ssd_send_cmd_db(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = (struct ssd_device *)cmd->dev; + struct bio *bio = cmd->bio; + + ssd_cmd_add_timer(cmd, SSD_CMD_TIMEOUT, ssd_cmd_timeout); + + if (bio) { + switch (dev->db_info.type) { + case SSD_DEBUG_READ_TO: + if (bio_data_dir(bio) == READ) { + return; + } + break; + case SSD_DEBUG_WRITE_TO: + if (bio_data_dir(bio) == WRITE) { + return; + } + break; + case SSD_DEBUG_RW_TO: + return; + break; + default: + break; + } + } + + ssd_reg32_write(dev->ctrlp + SSD_REQ_FIFO_REG, ((uint32_t)cmd->tag | ((uint32_t)cmd->nsegs << 16))); +} + + +/* fixed for BIOVEC_PHYS_MERGEABLE */ +#ifdef SSD_BIOVEC_PHYS_MERGEABLE_FIXED +#include +#include +#include + +static bool xen_biovec_phys_mergeable_fixed(const struct bio_vec *vec1, + const struct bio_vec *vec2) +{ + unsigned long mfn1 = pfn_to_mfn(page_to_pfn(vec1->bv_page)); + unsigned long mfn2 = pfn_to_mfn(page_to_pfn(vec2->bv_page)); + + return __BIOVEC_PHYS_MERGEABLE(vec1, vec2) && + ((mfn1 == mfn2) || ((mfn1+1) == mfn2)); +} + +#ifdef BIOVEC_PHYS_MERGEABLE +#undef BIOVEC_PHYS_MERGEABLE +#endif +#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ + (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ + (!xen_domain() || xen_biovec_phys_mergeable_fixed(vec1, vec2))) + +#endif + +static inline int ssd_bio_map_sg(struct ssd_device *dev, struct bio *bio, struct scatterlist *sgl) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) + struct bio_vec *bvec, *bvprv = NULL; + struct scatterlist *sg = NULL; + int i = 0, nsegs = 0; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)) + sg_init_table(sgl, dev->hw_info.cmd_max_sg); +#endif + + /* + * for each segment in bio + */ + bio_for_each_segment(bvec, bio, i) { + if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) { + sg->length += bvec->bv_len; + } else { + if (unlikely(nsegs >= (int)dev->hw_info.cmd_max_sg)) { + break; + } + + sg = sg ? (sg + 1) : sgl; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset); +#else + sg->page = bvec->bv_page; + sg->length = bvec->bv_len; + sg->offset = bvec->bv_offset; +#endif + nsegs++; + } + bvprv = bvec; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + if (sg) { + sg_mark_end(sg); + } +#endif + + bio->bi_idx = i; + + return nsegs; +#else + struct bio_vec bvec, bvprv; + struct bvec_iter iter; + struct scatterlist *sg = NULL; + int nsegs = 0; + int first = 1; + + sg_init_table(sgl, dev->hw_info.cmd_max_sg); + + /* + * for each segment in bio + */ + bio_for_each_segment(bvec, bio, iter) { + if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) { + sg->length += bvec.bv_len; + } else { + if (unlikely(nsegs >= (int)dev->hw_info.cmd_max_sg)) { + break; + } + + sg = sg ? (sg + 1) : sgl; + + sg_set_page(sg, bvec.bv_page, bvec.bv_len, bvec.bv_offset); + + nsegs++; + first = 0; + } + bvprv = bvec; + } + + if (sg) { + sg_mark_end(sg); + } + + return nsegs; +#endif +} + + +static int __ssd_submit_pbio(struct ssd_device *dev, struct bio *bio, int wait) +{ + struct ssd_cmd *cmd; + struct ssd_rw_msg *msg; + struct ssd_sg_entry *sge; + sector_t block = bio_start(bio); + int tag; + int i; + + tag = ssd_get_tag(dev, wait); + if (tag < 0) { + return -EBUSY; + } + + cmd = &dev->cmd[tag]; + cmd->bio = bio; + cmd->flag = 1; + + msg = (struct ssd_rw_msg *)cmd->msg; + +#if (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))) + if (bio->bi_rw & REQ_DISCARD) { + unsigned int length = bio_sectors(bio); + + //printk(KERN_WARNING "%s: discard len %u, block %llu\n", dev->name, bio_sectors(bio), block); + msg->tag = tag; + msg->fun = SSD_FUNC_TRIM; + + sge = msg->sge; + for (i=0; i<(dev->hw_info.cmd_max_sg); i++) { + sge->block = block; + sge->length = (length >= dev->hw_info.sg_max_sec) ? dev->hw_info.sg_max_sec : length; + sge->buf = 0; + + block += sge->length; + length -= sge->length; + sge++; + + if (length <= 0) { + break; + } + } + msg->nsegs = cmd->nsegs = (i + 1); + + dev->scmd(cmd); + return 0; + } +#elif (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32))) + if (bio_rw_flagged(bio, BIO_RW_DISCARD)) { + unsigned int length = bio_sectors(bio); + + //printk(KERN_WARNING "%s: discard len %u, block %llu\n", dev->name, bio_sectors(bio), block); + msg->tag = tag; + msg->fun = SSD_FUNC_TRIM; + + sge = msg->sge; + for (i=0; i<(dev->hw_info.cmd_max_sg); i++) { + sge->block = block; + sge->length = (length >= dev->hw_info.sg_max_sec) ? dev->hw_info.sg_max_sec : length; + sge->buf = 0; + + block += sge->length; + length -= sge->length; + sge++; + + if (length <= 0) { + break; + } + } + msg->nsegs = cmd->nsegs = (i + 1); + + dev->scmd(cmd); + return 0; + } +#endif + + //msg->nsegs = cmd->nsegs = ssd_bio_map_sg(dev, bio, sgl); + msg->nsegs = cmd->nsegs = bio->bi_vcnt; + + //xx + if (bio_data_dir(bio) == READ) { + msg->fun = SSD_FUNC_READ; + msg->flag = 0; + } else { + msg->fun = SSD_FUNC_WRITE; + msg->flag = dev->wmode; + } + + sge = msg->sge; + for (i=0; ibi_vcnt; i++) { + sge->block = block; + sge->length = bio->bi_io_vec[i].bv_len >> 9; + sge->buf = (uint64_t)((void *)bio->bi_io_vec[i].bv_page + bio->bi_io_vec[i].bv_offset); + + block += sge->length; + sge++; + } + + msg->tag = tag; + +#ifdef SSD_OT_PROTECT + if (unlikely(dev->ot_delay > 0 && dev->ot_protect != 0)) { + msleep_interruptible(dev->ot_delay); + } +#endif + + ssd_start_io_acct(cmd); + dev->scmd(cmd); + + return 0; +} + +static inline int ssd_submit_bio(struct ssd_device *dev, struct bio *bio, int wait) +{ + struct ssd_cmd *cmd; + struct ssd_rw_msg *msg; + struct ssd_sg_entry *sge; + struct scatterlist *sgl; + sector_t block = bio_start(bio); + int tag; + int i; + + tag = ssd_get_tag(dev, wait); + if (tag < 0) { + return -EBUSY; + } + + cmd = &dev->cmd[tag]; + cmd->bio = bio; + cmd->flag = 0; + + msg = (struct ssd_rw_msg *)cmd->msg; + + sgl = cmd->sgl; + +#if (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))) + if (bio->bi_rw & REQ_DISCARD) { + unsigned int length = bio_sectors(bio); + + //printk(KERN_WARNING "%s: discard len %u, block %llu\n", dev->name, bio_sectors(bio), block); + msg->tag = tag; + msg->fun = SSD_FUNC_TRIM; + + sge = msg->sge; + for (i=0; i<(dev->hw_info.cmd_max_sg); i++) { + sge->block = block; + sge->length = (length >= dev->hw_info.sg_max_sec) ? dev->hw_info.sg_max_sec : length; + sge->buf = 0; + + block += sge->length; + length -= sge->length; + sge++; + + if (length <= 0) { + break; + } + } + msg->nsegs = cmd->nsegs = (i + 1); + + dev->scmd(cmd); + return 0; + } +#elif (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32))) + if (bio_rw_flagged(bio, BIO_RW_DISCARD)) { + unsigned int length = bio_sectors(bio); + + //printk(KERN_WARNING "%s: discard len %u, block %llu\n", dev->name, bio_sectors(bio), block); + msg->tag = tag; + msg->fun = SSD_FUNC_TRIM; + + sge = msg->sge; + for (i=0; i<(dev->hw_info.cmd_max_sg); i++) { + sge->block = block; + sge->length = (length >= dev->hw_info.sg_max_sec) ? dev->hw_info.sg_max_sec : length; + sge->buf = 0; + + block += sge->length; + length -= sge->length; + sge++; + + if (length <= 0) { + break; + } + } + msg->nsegs = cmd->nsegs = (i + 1); + + dev->scmd(cmd); + return 0; + } +#endif + + msg->nsegs = cmd->nsegs = ssd_bio_map_sg(dev, bio, sgl); + + //xx + if (bio_data_dir(bio) == READ) { + msg->fun = SSD_FUNC_READ; + msg->flag = 0; + pci_map_sg(dev->pdev, sgl, cmd->nsegs, PCI_DMA_FROMDEVICE); + } else { + msg->fun = SSD_FUNC_WRITE; + msg->flag = dev->wmode; + pci_map_sg(dev->pdev, sgl, cmd->nsegs, PCI_DMA_TODEVICE); + } + + sge = msg->sge; + for (i=0; insegs; i++) { + sge->block = block; + sge->length = sg_dma_len(sgl) >> 9; + sge->buf = sg_dma_address(sgl); + + block += sge->length; + sgl++; + sge++; + } + + msg->tag = tag; + +#ifdef SSD_OT_PROTECT + if (unlikely(dev->ot_delay > 0 && dev->ot_protect != 0)) { + msleep_interruptible(dev->ot_delay); + } +#endif + + ssd_start_io_acct(cmd); + dev->scmd(cmd); + + return 0; +} + +/* threads */ +static int ssd_done_thread(void *data) +{ + struct ssd_device *dev; + struct bio *bio; + struct bio *next; +#ifdef SSD_ESCAPE_IRQ + cpumask_t new_mask; +#endif + + if (!data) { + return -EINVAL; + } + dev = data; + + //set_user_nice(current, -5); + + while (!kthread_should_stop()) { + wait_event_interruptible(dev->done_waitq, (atomic_read(&dev->in_doneq) || kthread_should_stop())); + + while (atomic_read(&dev->in_doneq)) { + if (threaded_irq) { + spin_lock(&dev->doneq_lock); + bio = ssd_blist_get(&dev->doneq); + spin_unlock(&dev->doneq_lock); + } else { + spin_lock_irq(&dev->doneq_lock); + bio = ssd_blist_get(&dev->doneq); + spin_unlock_irq(&dev->doneq_lock); + } + + while (bio) { + next = bio->bi_next; + bio->bi_next = NULL; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, 0); +#else + bio_endio(bio, bio->bi_size, 0); +#endif + atomic_dec(&dev->in_doneq); + bio = next; + } + + cond_resched(); + +#ifdef SSD_ESCAPE_IRQ + if (unlikely(smp_processor_id() == dev->irq_cpu)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)) + cpumask_setall(&new_mask); + cpumask_clear_cpu(dev->irq_cpu, &new_mask); + set_cpus_allowed_ptr(current, &new_mask); +#else + cpus_setall(new_mask); + cpu_clear(dev->irq_cpu, new_mask); + set_cpus_allowed(current, new_mask); +#endif + } +#endif + } + } + return 0; +} + +static int ssd_send_thread(void *data) +{ + struct ssd_device *dev; + struct bio *bio; + struct bio *next; +#ifdef SSD_ESCAPE_IRQ + cpumask_t new_mask; +#endif + + if (!data) { + return -EINVAL; + } + dev = data; + + //set_user_nice(current, -5); + + while (!kthread_should_stop()) { + wait_event_interruptible(dev->send_waitq, (atomic_read(&dev->in_sendq) || kthread_should_stop())); + + while (atomic_read(&dev->in_sendq)) { + spin_lock(&dev->sendq_lock); + bio = ssd_blist_get(&dev->sendq); + spin_unlock(&dev->sendq_lock); + + while (bio) { + next = bio->bi_next; + bio->bi_next = NULL; +#ifdef SSD_QUEUE_PBIO + if (test_and_clear_bit(BIO_SSD_PBIO, &bio->bi_flags)) { + __ssd_submit_pbio(dev, bio, 1); + } else { + ssd_submit_bio(dev, bio, 1); + } +#else + ssd_submit_bio(dev, bio, 1); +#endif + atomic_dec(&dev->in_sendq); + bio = next; + } + + cond_resched(); + +#ifdef SSD_ESCAPE_IRQ + if (unlikely(smp_processor_id() == dev->irq_cpu)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)) + cpumask_setall(&new_mask); + cpumask_clear_cpu(dev->irq_cpu, &new_mask); + set_cpus_allowed_ptr(current, &new_mask); +#else + cpus_setall(new_mask); + cpu_clear(dev->irq_cpu, new_mask); + set_cpus_allowed(current, new_mask); +#endif + } +#endif + } + } + + return 0; +} + +static void ssd_cleanup_thread(struct ssd_device *dev) +{ + kthread_stop(dev->send_thread); + kthread_stop(dev->done_thread); +} + +static int ssd_init_thread(struct ssd_device *dev) +{ + int ret; + + atomic_set(&dev->in_doneq, 0); + atomic_set(&dev->in_sendq, 0); + + spin_lock_init(&dev->doneq_lock); + spin_lock_init(&dev->sendq_lock); + + ssd_blist_init(&dev->doneq); + ssd_blist_init(&dev->sendq); + + init_waitqueue_head(&dev->done_waitq); + init_waitqueue_head(&dev->send_waitq); + + dev->done_thread = kthread_run(ssd_done_thread, dev, "%s/d", dev->name); + if (IS_ERR(dev->done_thread)) { + ret = PTR_ERR(dev->done_thread); + goto out_done_thread; + } + + dev->send_thread = kthread_run(ssd_send_thread, dev, "%s/s", dev->name); + if (IS_ERR(dev->send_thread)) { + ret = PTR_ERR(dev->send_thread); + goto out_send_thread; + } + + return 0; + +out_send_thread: + kthread_stop(dev->done_thread); +out_done_thread: + return ret; +} + +/* dcmd pool */ +static void ssd_put_dcmd(struct ssd_dcmd *dcmd) +{ + struct ssd_device *dev = (struct ssd_device *)dcmd->dev; + + spin_lock(&dev->dcmd_lock); + list_add_tail(&dcmd->list, &dev->dcmd_list); + spin_unlock(&dev->dcmd_lock); +} + +static struct ssd_dcmd *ssd_get_dcmd(struct ssd_device *dev) +{ + struct ssd_dcmd *dcmd = NULL; + + spin_lock(&dev->dcmd_lock); + if (!list_empty(&dev->dcmd_list)) { + dcmd = list_entry(dev->dcmd_list.next, + struct ssd_dcmd, list); + list_del_init(&dcmd->list); + } + spin_unlock(&dev->dcmd_lock); + + return dcmd; +} + +static void ssd_cleanup_dcmd(struct ssd_device *dev) +{ + kfree(dev->dcmd); +} + +static int ssd_init_dcmd(struct ssd_device *dev) +{ + struct ssd_dcmd *dcmd; + int dcmd_sz = sizeof(struct ssd_dcmd)*dev->hw_info.cmd_fifo_sz; + int i; + + spin_lock_init(&dev->dcmd_lock); + INIT_LIST_HEAD(&dev->dcmd_list); + init_waitqueue_head(&dev->dcmd_wq); + + dev->dcmd = kmalloc(dcmd_sz, GFP_KERNEL); + if (!dev->dcmd) { + hio_warn("%s: can not alloc dcmd\n", dev->name); + goto out_alloc_dcmd; + } + memset(dev->dcmd, 0, dcmd_sz); + + for (i=0, dcmd=dev->dcmd; i<(int)dev->hw_info.cmd_fifo_sz; i++, dcmd++) { + dcmd->dev = dev; + INIT_LIST_HEAD(&dcmd->list); + list_add_tail(&dcmd->list, &dev->dcmd_list); + } + + return 0; + +out_alloc_dcmd: + return -ENOMEM; +} + +static void ssd_put_dmsg(void *msg) +{ + struct ssd_dcmd *dcmd = container_of(msg, struct ssd_dcmd, msg); + struct ssd_device *dev = (struct ssd_device *)dcmd->dev; + + memset(dcmd->msg, 0, SSD_DCMD_MAX_SZ); + ssd_put_dcmd(dcmd); + wake_up(&dev->dcmd_wq); +} + +static void *ssd_get_dmsg(struct ssd_device *dev) +{ + struct ssd_dcmd *dcmd = ssd_get_dcmd(dev); + + while (!dcmd) { + DEFINE_WAIT(wait); + prepare_to_wait_exclusive(&dev->dcmd_wq, &wait, TASK_UNINTERRUPTIBLE); + schedule(); + + dcmd = ssd_get_dcmd(dev); + + finish_wait(&dev->dcmd_wq, &wait); + } + return dcmd->msg; +} + +/* do direct cmd */ +static int ssd_do_request(struct ssd_device *dev, int rw, void *msg, int *done) +{ + DECLARE_COMPLETION(wait); + struct ssd_cmd *cmd; + int tag; + int ret = 0; + + tag = ssd_get_tag(dev, 1); + if (tag < 0) { + return -EBUSY; + } + + cmd = &dev->cmd[tag]; + cmd->nsegs = 1; + memcpy(cmd->msg, msg, SSD_DCMD_MAX_SZ); + ((struct ssd_rw_msg *)cmd->msg)->tag = tag; + + cmd->waiting = &wait; + + dev->scmd(cmd); + + wait_for_completion(cmd->waiting); + cmd->waiting = NULL; + + if (cmd->errors == -ETIMEDOUT) { + ret = cmd->errors; + } else if (cmd->errors) { + ret = -EIO; + } + + if (done != NULL) { + *done = cmd->nr_log; + } + ssd_put_tag(dev, cmd->tag); + + return ret; +} + +static int ssd_do_barrier_request(struct ssd_device *dev, int rw, void *msg, int *done) +{ + DECLARE_COMPLETION(wait); + struct ssd_cmd *cmd; + int tag; + int ret = 0; + + tag = ssd_barrier_get_tag(dev); + if (tag < 0) { + return -EBUSY; + } + + cmd = &dev->cmd[tag]; + cmd->nsegs = 1; + memcpy(cmd->msg, msg, SSD_DCMD_MAX_SZ); + ((struct ssd_rw_msg *)cmd->msg)->tag = tag; + + cmd->waiting = &wait; + + dev->scmd(cmd); + + wait_for_completion(cmd->waiting); + cmd->waiting = NULL; + + if (cmd->errors == -ETIMEDOUT) { + ret = cmd->errors; + } else if (cmd->errors) { + ret = -EIO; + } + + if (done != NULL) { + *done = cmd->nr_log; + } + ssd_barrier_put_tag(dev, cmd->tag); + + return ret; +} + +#ifdef SSD_OT_PROTECT +static void ssd_check_temperature(struct ssd_device *dev, int temp) +{ + uint64_t val; + uint32_t off; + int cur; + int i; + + if (mode != SSD_DRV_MODE_STANDARD) { + return; + } + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + } + + for (i=0; ihw_info.nr_ctrl; i++) { + off = SSD_CTRL_TEMP_REG0 + i * sizeof(uint64_t); + + val = ssd_reg_read(dev->ctrlp + off); + if (val == 0xffffffffffffffffull) { + continue; + } + + cur = (int)CUR_TEMP(val); + if (cur >= temp) { + if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_CTRL), &dev->hwmon)) { + if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2_2) { + hio_warn("%s: Over temperature, please check the fans.\n", dev->name); + dev->ot_delay = SSD_OT_DELAY; + } + } + return; + } + } + + if (test_and_clear_bit(SSD_HWMON_TEMP(SSD_TEMP_CTRL), &dev->hwmon)) { + if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2_2) { + hio_warn("%s: Temperature is OK.\n", dev->name); + dev->ot_delay = 0; + } + } +} +#endif + +static int ssd_get_ot_status(struct ssd_device *dev, int *status) +{ + uint32_t off; + uint32_t val; + int i; + + if (!dev || !status) { + return -EINVAL; + } + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2_2) { + for (i=0; ihw_info.nr_ctrl; i++) { + off = SSD_READ_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ); + val = ssd_reg32_read(dev->ctrlp + off); + if ((val >> 22) & 0x1) { + *status = 1; + goto out; + } + + + off = SSD_WRITE_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ); + val = ssd_reg32_read(dev->ctrlp + off); + if ((val >> 22) & 0x1) { + *status = 1; + goto out; + } + } + } else { + *status = !!dev->ot_delay; + } + +out: + return 0; +} + +static void ssd_set_ot_protect(struct ssd_device *dev, int protect) +{ + uint32_t off; + uint32_t val; + int i; + + mutex_lock(&dev->fw_mutex); + + dev->ot_protect = !!protect; + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2_2) { + for (i=0; ihw_info.nr_ctrl; i++) { + off = SSD_READ_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ); + val = ssd_reg32_read(dev->ctrlp + off); + if (dev->ot_protect) { + val |= (1U << 21); + } else { + val &= ~(1U << 21); + } + ssd_reg32_write(dev->ctrlp + off, val); + + + off = SSD_WRITE_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ); + val = ssd_reg32_read(dev->ctrlp + off); + if (dev->ot_protect) { + val |= (1U << 21); + } else { + val &= ~(1U << 21); + } + ssd_reg32_write(dev->ctrlp + off, val); + } + } + + mutex_unlock(&dev->fw_mutex); +} + +static int ssd_init_ot_protect(struct ssd_device *dev) +{ + ssd_set_ot_protect(dev, ot_protect); + +#ifdef SSD_OT_PROTECT + ssd_check_temperature(dev, SSD_OT_TEMP); +#endif + + return 0; +} + +/* log */ +static int ssd_read_log(struct ssd_device *dev, int ctrl_idx, void *buf, int *nr_log) +{ + struct ssd_log_op_msg *msg; + struct ssd_log_msg *lmsg; + dma_addr_t buf_dma; + size_t length = dev->hw_info.log_sz; + int ret = 0; + + if (ctrl_idx >= dev->hw_info.nr_ctrl) { + return -EINVAL; + } + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map read DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + msg = (struct ssd_log_op_msg *)ssd_get_dmsg(dev); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + lmsg = (struct ssd_log_msg *)msg; + lmsg->fun = SSD_FUNC_READ_LOG; + lmsg->ctrl_idx = ctrl_idx; + lmsg->buf = buf_dma; + } else { + msg->fun = SSD_FUNC_READ_LOG; + msg->ctrl_idx = ctrl_idx; + msg->buf = buf_dma; + } + + ret = ssd_do_request(dev, READ, msg, nr_log); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE); + +out_dma_mapping: + return ret; +} + +#define SSD_LOG_PRINT_BUF_SZ 256 +static int ssd_parse_log(struct ssd_device *dev, struct ssd_log *log, int print) +{ + struct ssd_log_desc *log_desc = ssd_log_desc; + struct ssd_log_entry *le; + char *sn = NULL; + char print_buf[SSD_LOG_PRINT_BUF_SZ]; + int print_len; + + le = &log->le; + + /* find desc */ + while (log_desc->event != SSD_UNKNOWN_EVENT) { + if (log_desc->event == le->event) { + break; + } + log_desc++; + } + + if (!print) { + goto out; + } + + if (log_desc->level < log_level) { + goto out; + } + + /* parse */ + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + sn = dev->label.sn; + } else { + sn = dev->labelv3.barcode; + } + + print_len = snprintf(print_buf, SSD_LOG_PRINT_BUF_SZ, "%s (%s): <%#x>", dev->name, sn, le->event); + + if (log->ctrl_idx != SSD_LOG_SW_IDX) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " controller %d", log->ctrl_idx); + } + + switch (log_desc->data) { + case SSD_LOG_DATA_NONE: + break; + case SSD_LOG_DATA_LOC: + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " flash %d", le->data.loc.flash); + if (log_desc->sblock) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " block %d", le->data.loc.block); + } + if (log_desc->spage) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " page %d", le->data.loc.page); + } + } else { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " flash %d", le->data.loc1.flash); + if (log_desc->sblock) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " block %d", le->data.loc1.block); + } + if (log_desc->spage) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " page %d", le->data.loc1.page); + } + } + break; + case SSD_LOG_DATA_HEX: + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " info %#x", le->data.val); + break; + default: + break; + } + /*print_len += */snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), ": %s", log_desc->desc); + + switch (log_desc->level) { + case SSD_LOG_LEVEL_INFO: + hio_info("%s\n", print_buf); + break; + case SSD_LOG_LEVEL_NOTICE: + hio_note("%s\n", print_buf); + break; + case SSD_LOG_LEVEL_WARNING: + hio_warn("%s\n", print_buf); + break; + case SSD_LOG_LEVEL_ERR: + hio_err("%s\n", print_buf); + //printk(KERN_ERR MODULE_NAME": some exception occurred, please check the data or refer to FAQ."); + break; + default: + hio_warn("%s\n", print_buf); + break; + } + +out: + return log_desc->level; +} + +static int ssd_bm_get_sfstatus(struct ssd_device *dev, uint16_t *status); +static int ssd_switch_wmode(struct ssd_device *dev, int wmode); + + +static int ssd_handle_event(struct ssd_device *dev, uint16_t event, int level) +{ + int ret = 0; + + switch (event) { + case SSD_LOG_OVER_TEMP: { +#ifdef SSD_OT_PROTECT + if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_CTRL), &dev->hwmon)) { + if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2_2) { + hio_warn("%s: Over temperature, please check the fans.\n", dev->name); + dev->ot_delay = SSD_OT_DELAY; + } + } +#endif + break; + } + + case SSD_LOG_NORMAL_TEMP: { +#ifdef SSD_OT_PROTECT + /* need to check all controller's temperature */ + ssd_check_temperature(dev, SSD_OT_TEMP_HYST); +#endif + break; + } + + case SSD_LOG_BATTERY_FAULT: { + uint16_t sfstatus; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + if (!ssd_bm_get_sfstatus(dev, &sfstatus)) { + ssd_gen_swlog(dev, SSD_LOG_BM_SFSTATUS, sfstatus); + } + } + + if (!test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ssd_switch_wmode(dev, dev->user_wmode); + } + break; + } + + case SSD_LOG_BATTERY_OK: { + if (test_and_clear_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ssd_switch_wmode(dev, dev->user_wmode); + } + break; + } + + case SSD_LOG_BOARD_VOLT_FAULT: { + ssd_mon_boardvolt(dev); + break; + } + + case SSD_LOG_CLEAR_LOG: { + /* update smart */ + memset(&dev->smart.log_info, 0, sizeof(struct ssd_log_info)); + break; + } + + case SSD_LOG_CAP_VOLT_FAULT: + case SSD_LOG_CAP_LEARN_FAULT: + case SSD_LOG_CAP_SHORT_CIRCUIT: { + if (!test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ssd_switch_wmode(dev, dev->user_wmode); + } + break; + } + + default: + break; + } + + /* ssd event call */ + if (dev->event_call) { + dev->event_call(dev->gd, event, level); + + /* FIXME */ + if (SSD_LOG_CAP_VOLT_FAULT == event || SSD_LOG_CAP_LEARN_FAULT == event || SSD_LOG_CAP_SHORT_CIRCUIT == event) { + dev->event_call(dev->gd, SSD_LOG_BATTERY_FAULT, level); + } + } + + return ret; +} + +static int ssd_save_log(struct ssd_device *dev, struct ssd_log *log) +{ + uint32_t off, size; + void *internal_log; + int ret = 0; + + mutex_lock(&dev->internal_log_mutex); + + size = sizeof(struct ssd_log); + off = dev->internal_log.nr_log * size; + + if (off == dev->rom_info.log_sz) { + if (dev->internal_log.nr_log == dev->smart.log_info.nr_log) { + hio_warn("%s: internal log is full\n", dev->name); + } + goto out; + } + + internal_log = dev->internal_log.log + off; + memcpy(internal_log, log, size); + + if (dev->protocol_info.ver > SSD_PROTOCOL_V3) { + off += dev->rom_info.log_base; + + ret = ssd_spi_write(dev, log, off, size); + if (ret) { + goto out; + } + } + + dev->internal_log.nr_log++; + +out: + mutex_unlock(&dev->internal_log_mutex); + return ret; +} + +static int ssd_save_swlog(struct ssd_device *dev, uint16_t event, uint32_t data) +{ + struct ssd_log log; + struct timeval tv; + int level; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + memset(&log, 0, sizeof(struct ssd_log)); + + do_gettimeofday(&tv); + log.ctrl_idx = SSD_LOG_SW_IDX; + log.time = tv.tv_sec; + log.le.event = event; + log.le.data.val = data; + + level = ssd_parse_log(dev, &log, 0); + if (level >= SSD_LOG_LEVEL) { + ret = ssd_save_log(dev, &log); + } + + /* set alarm */ + if (SSD_LOG_LEVEL_ERR == level) { + ssd_set_alarm(dev); + } + + /* update smart */ + dev->smart.log_info.nr_log++; + dev->smart.log_info.stat[level]++; + + /* handle event */ + ssd_handle_event(dev, event, level); + + return ret; +} + +static int ssd_gen_swlog(struct ssd_device *dev, uint16_t event, uint32_t data) +{ + struct ssd_log_entry le; + int ret; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + /* slave port ? */ + if (dev->slave) { + return 0; + } + + memset(&le, 0, sizeof(struct ssd_log_entry)); + le.event = event; + le.data.val = data; + + ret = sfifo_put(&dev->log_fifo, &le); + if (ret) { + return ret; + } + + if (test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->log_work); + } + + return 0; +} + +static int ssd_do_swlog(struct ssd_device *dev) +{ + struct ssd_log_entry le; + int ret = 0; + + memset(&le, 0, sizeof(struct ssd_log_entry)); + while (!sfifo_get(&dev->log_fifo, &le)) { + ret = ssd_save_swlog(dev, le.event, le.data.val); + if (ret) { + break; + } + } + + return ret; +} + +static int __ssd_clear_log(struct ssd_device *dev) +{ + uint32_t off, length; + int ret; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + if (dev->internal_log.nr_log == 0) { + return 0; + } + + mutex_lock(&dev->internal_log_mutex); + + off = dev->rom_info.log_base; + length = dev->rom_info.log_sz; + + ret = ssd_spi_erase(dev, off, length); + if (ret) { + hio_warn("%s: log erase: failed\n", dev->name); + goto out; + } + + dev->internal_log.nr_log = 0; + +out: + mutex_unlock(&dev->internal_log_mutex); + return ret; +} + +static int ssd_clear_log(struct ssd_device *dev) +{ + int ret; + + ret = __ssd_clear_log(dev); + if(!ret) { + ssd_gen_swlog(dev, SSD_LOG_CLEAR_LOG, 0); + } + + return ret; +} + +static int ssd_do_log(struct ssd_device *dev, int ctrl_idx, void *buf) +{ + struct ssd_log_entry *le; + struct ssd_log log; + struct timeval tv; + int nr_log = 0; + int level; + int ret = 0; + + ret = ssd_read_log(dev, ctrl_idx, buf, &nr_log); + if (ret) { + return ret; + } + + do_gettimeofday(&tv); + + log.time = tv.tv_sec; + log.ctrl_idx = ctrl_idx; + + le = (ssd_log_entry_t *)buf; + while (nr_log > 0) { + memcpy(&log.le, le, sizeof(struct ssd_log_entry)); + + level = ssd_parse_log(dev, &log, 1); + if (level >= SSD_LOG_LEVEL) { + ssd_save_log(dev, &log); + } + + /* set alarm */ + if (SSD_LOG_LEVEL_ERR == level) { + ssd_set_alarm(dev); + } + + dev->smart.log_info.nr_log++; + if (SSD_LOG_SEU_FAULT != le->event && SSD_LOG_SEU_FAULT1 != le->event) { + dev->smart.log_info.stat[level]++; + } else { + /* SEU fault */ + + /* log to the volatile log info */ + dev->log_info.nr_log++; + dev->log_info.stat[level]++; + + /* do something */ + dev->reload_fw = 1; + ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FLAG); + + /*dev->readonly = 1; + set_disk_ro(dev->gd, 1); + hio_warn("%s: switched to read-only mode.\n", dev->name);*/ + } + + /* handle event */ + ssd_handle_event(dev, le->event, level); + + le++; + nr_log--; + } + + return 0; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static void ssd_log_worker(void *data) +{ + struct ssd_device *dev = (struct ssd_device *)data; +#else +static void ssd_log_worker(struct work_struct *work) +{ + struct ssd_device *dev = container_of(work, struct ssd_device, log_work); +#endif + int i; + int ret; + + if (!test_bit(SSD_LOG_ERR, &dev->state) && test_bit(SSD_ONLINE, &dev->state)) { + /* alloc log buf */ + if (!dev->log_buf) { + dev->log_buf = kmalloc(dev->hw_info.log_sz, GFP_KERNEL); + if (!dev->log_buf) { + hio_warn("%s: ssd_log_worker: no mem\n", dev->name); + return; + } + } + + /* get log */ + if (test_and_clear_bit(SSD_LOG_HW, &dev->state)) { + for (i=0; ihw_info.nr_ctrl; i++) { + ret = ssd_do_log(dev, i, dev->log_buf); + if (ret) { + (void)test_and_set_bit(SSD_LOG_ERR, &dev->state); + hio_warn("%s: do log fail\n", dev->name); + } + } + } + } + + ret = ssd_do_swlog(dev); + if (ret) { + hio_warn("%s: do swlog fail\n", dev->name); + } +} + +static void ssd_cleanup_log(struct ssd_device *dev) +{ + if (dev->log_buf) { + kfree(dev->log_buf); + dev->log_buf = NULL; + } + + sfifo_free(&dev->log_fifo); + + if (dev->internal_log.log) { + vfree(dev->internal_log.log); + dev->internal_log.log = NULL; + } +} + +static int ssd_init_log(struct ssd_device *dev) +{ + struct ssd_log *log; + uint32_t off, size; + uint32_t len = 0; + int ret = 0; + + mutex_init(&dev->internal_log_mutex); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) + INIT_WORK(&dev->log_work, ssd_log_worker, dev); +#else + INIT_WORK(&dev->log_work, ssd_log_worker); +#endif + + off = dev->rom_info.log_base; + size = dev->rom_info.log_sz; + + dev->internal_log.log = vmalloc(size); + if (!dev->internal_log.log) { + ret = -ENOMEM; + goto out_alloc_log; + } + + ret = sfifo_alloc(&dev->log_fifo, SSD_LOG_FIFO_SZ, sizeof(struct ssd_log_entry)); + if (ret < 0) { + goto out_alloc_log_fifo; + } + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + log = (struct ssd_log *)dev->internal_log.log; + while (len < size) { + ret = ssd_spi_read(dev, log, off, sizeof(struct ssd_log)); + if (ret) { + goto out_read_log; + } + + if (log->ctrl_idx == 0xff) { + break; + } + + dev->internal_log.nr_log++; + log++; + len += sizeof(struct ssd_log); + off += sizeof(struct ssd_log); + } + + return 0; + +out_read_log: + sfifo_free(&dev->log_fifo); +out_alloc_log_fifo: + vfree(dev->internal_log.log); + dev->internal_log.log = NULL; + dev->internal_log.nr_log = 0; +out_alloc_log: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +/* work queue */ +static void ssd_stop_workq(struct ssd_device *dev) +{ + test_and_clear_bit(SSD_INIT_WORKQ, &dev->state); + flush_workqueue(dev->workq); +} + +static void ssd_start_workq(struct ssd_device *dev) +{ + (void)test_and_set_bit(SSD_INIT_WORKQ, &dev->state); + + /* log ? */ + queue_work(dev->workq, &dev->log_work); +} + +static void ssd_cleanup_workq(struct ssd_device *dev) +{ + flush_workqueue(dev->workq); + destroy_workqueue(dev->workq); + dev->workq = NULL; +} + +static int ssd_init_workq(struct ssd_device *dev) +{ + int ret = 0; + + dev->workq = create_singlethread_workqueue(dev->name); + if (!dev->workq) { + ret = -ESRCH; + goto out; + } + +out: + return ret; +} + +/* rom */ +static int ssd_init_rom_info(struct ssd_device *dev) +{ + uint32_t val; + + mutex_init(&dev->spi_mutex); + mutex_init(&dev->i2c_mutex); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + /* fix bug: read data to clear status */ + (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_RDATA); + + dev->rom_info.size = SSD_ROM_SIZE; + dev->rom_info.block_size = SSD_ROM_BLK_SIZE; + dev->rom_info.page_size = SSD_ROM_PAGE_SIZE; + + dev->rom_info.bridge_fw_base = SSD_ROM_BRIDGE_FW_BASE; + dev->rom_info.bridge_fw_sz = SSD_ROM_BRIDGE_FW_SIZE; + dev->rom_info.nr_bridge_fw = SSD_ROM_NR_BRIDGE_FW; + + dev->rom_info.ctrl_fw_base = SSD_ROM_CTRL_FW_BASE; + dev->rom_info.ctrl_fw_sz = SSD_ROM_CTRL_FW_SIZE; + dev->rom_info.nr_ctrl_fw = SSD_ROM_NR_CTRL_FW; + + dev->rom_info.log_sz = SSD_ROM_LOG_SZ; + + dev->rom_info.vp_base = SSD_ROM_VP_BASE; + dev->rom_info.label_base = SSD_ROM_LABEL_BASE; + } else if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_INFO_REG); + dev->rom_info.size = 0x100000 * (1U << (val & 0xFF)); + dev->rom_info.block_size = 0x10000 * (1U << ((val>>8) & 0xFF)); + dev->rom_info.page_size = (val>>16) & 0xFFFF; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_BRIDGE_FW_INFO_REG); + dev->rom_info.bridge_fw_base = dev->rom_info.block_size * (val & 0xFFFF); + dev->rom_info.bridge_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF); + dev->rom_info.nr_bridge_fw = ((val >> 30) & 0x3) + 1; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_CTRL_FW_INFO_REG); + dev->rom_info.ctrl_fw_base = dev->rom_info.block_size * (val & 0xFFFF); + dev->rom_info.ctrl_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF); + dev->rom_info.nr_ctrl_fw = ((val >> 30) & 0x3) + 1; + + dev->rom_info.bm_fw_base = dev->rom_info.ctrl_fw_base + (dev->rom_info.nr_ctrl_fw * dev->rom_info.ctrl_fw_sz); + dev->rom_info.bm_fw_sz = SSD_PV3_ROM_BM_FW_SZ; + dev->rom_info.nr_bm_fw = SSD_PV3_ROM_NR_BM_FW; + + dev->rom_info.log_base = dev->rom_info.bm_fw_base + (dev->rom_info.nr_bm_fw * dev->rom_info.bm_fw_sz); + dev->rom_info.log_sz = SSD_ROM_LOG_SZ; + + dev->rom_info.smart_base = dev->rom_info.log_base + dev->rom_info.log_sz; + dev->rom_info.smart_sz = SSD_PV3_ROM_SMART_SZ; + dev->rom_info.nr_smart = SSD_PV3_ROM_NR_SMART; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_VP_INFO_REG); + dev->rom_info.vp_base = dev->rom_info.block_size * val; + dev->rom_info.label_base = dev->rom_info.vp_base + dev->rom_info.block_size; + if (dev->rom_info.label_base >= dev->rom_info.size) { + dev->rom_info.label_base = dev->rom_info.vp_base - dev->rom_info.block_size; + } + } else { + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_INFO_REG); + dev->rom_info.size = 0x100000 * (1U << (val & 0xFF)); + dev->rom_info.block_size = 0x10000 * (1U << ((val>>8) & 0xFF)); + dev->rom_info.page_size = (val>>16) & 0xFFFF; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_BRIDGE_FW_INFO_REG); + dev->rom_info.bridge_fw_base = dev->rom_info.block_size * (val & 0xFFFF); + dev->rom_info.bridge_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF); + dev->rom_info.nr_bridge_fw = ((val >> 30) & 0x3) + 1; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_CTRL_FW_INFO_REG); + dev->rom_info.ctrl_fw_base = dev->rom_info.block_size * (val & 0xFFFF); + dev->rom_info.ctrl_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF); + dev->rom_info.nr_ctrl_fw = ((val >> 30) & 0x3) + 1; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_VP_INFO_REG); + dev->rom_info.vp_base = dev->rom_info.block_size * val; + dev->rom_info.label_base = dev->rom_info.vp_base - SSD_PV3_2_ROM_SEC_SZ; + + dev->rom_info.nr_smart = SSD_PV3_ROM_NR_SMART; + dev->rom_info.smart_sz = SSD_PV3_2_ROM_SEC_SZ; + dev->rom_info.smart_base = dev->rom_info.label_base - (dev->rom_info.smart_sz * dev->rom_info.nr_smart); + if (dev->rom_info.smart_sz > dev->rom_info.block_size) { + dev->rom_info.smart_sz = dev->rom_info.block_size; + } + + dev->rom_info.log_sz = SSD_PV3_2_ROM_LOG_SZ; + dev->rom_info.log_base = dev->rom_info.smart_base - dev->rom_info.log_sz; + } + + return ssd_init_spi(dev); +} + +/* smart */ +static int ssd_update_smart(struct ssd_device *dev, struct ssd_smart *smart) +{ + struct timeval tv; + uint64_t run_time; +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)) + struct hd_struct *part; + int cpu; +#endif + int i, j; + int ret = 0; + + if (!test_bit(SSD_INIT_BD, &dev->state)) { + return 0; + } + + do_gettimeofday(&tv); + if ((uint64_t)tv.tv_sec < dev->uptime) { + run_time = 0; + } else { + run_time = tv.tv_sec - dev->uptime; + } + + /* avoid frequently update */ + if (run_time >= 60) { + ret = 1; + } + + /* io stat */ + smart->io_stat.run_time += run_time; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)) + cpu = part_stat_lock(); + part = &dev->gd->part0; + part_round_stats(cpu, part); + part_stat_unlock(); + + smart->io_stat.nr_read += part_stat_read(part, ios[READ]); + smart->io_stat.nr_write += part_stat_read(part, ios[WRITE]); + smart->io_stat.rsectors += part_stat_read(part, sectors[READ]); + smart->io_stat.wsectors += part_stat_read(part, sectors[WRITE]); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14)) + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + + smart->io_stat.nr_read += disk_stat_read(dev->gd, ios[READ]); + smart->io_stat.nr_write += disk_stat_read(dev->gd, ios[WRITE]); + smart->io_stat.rsectors += disk_stat_read(dev->gd, sectors[READ]); + smart->io_stat.wsectors += disk_stat_read(dev->gd, sectors[WRITE]); +#else + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + + smart->io_stat.nr_read += disk_stat_read(dev->gd, reads); + smart->io_stat.nr_write += disk_stat_read(dev->gd, writes); + smart->io_stat.rsectors += disk_stat_read(dev->gd, read_sectors); + smart->io_stat.wsectors += disk_stat_read(dev->gd, write_sectors); +#endif + + smart->io_stat.nr_to += atomic_read(&dev->tocnt); + + for (i=0; inr_queue; i++) { + smart->io_stat.nr_rwerr += dev->queue[i].io_stat.nr_rwerr; + smart->io_stat.nr_ioerr += dev->queue[i].io_stat.nr_ioerr; + } + + for (i=0; inr_queue; i++) { + for (j=0; jecc_info.bitflip[j] += dev->queue[i].ecc_info.bitflip[j]; + } + } + + //dev->uptime = tv.tv_sec; + + return ret; +} + +static int ssd_clear_smart(struct ssd_device *dev) +{ + struct timeval tv; + uint64_t sversion; + uint32_t off, length; + int i; + int ret; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + /* clear smart */ + off = dev->rom_info.smart_base; + length = dev->rom_info.smart_sz * dev->rom_info.nr_smart; + + ret = ssd_spi_erase(dev, off, length); + if (ret) { + hio_warn("%s: info erase: failed\n", dev->name); + goto out; + } + + sversion = dev->smart.version; + + memset(&dev->smart, 0, sizeof(struct ssd_smart)); + dev->smart.version = sversion + 1; + dev->smart.magic = SSD_SMART_MAGIC; + + /* clear all tmp acc */ + for (i=0; inr_queue; i++) { + memset(&(dev->queue[i].io_stat), 0, sizeof(struct ssd_io_stat)); + memset(&(dev->queue[i].ecc_info), 0, sizeof(struct ssd_ecc_info)); + } + + atomic_set(&dev->tocnt, 0); + + /* clear tmp log info */ + memset(&dev->log_info, 0, sizeof(struct ssd_log_info)); + + do_gettimeofday(&tv); + dev->uptime = tv.tv_sec; + + /* clear alarm ? */ + //ssd_clear_alarm(dev); +out: + return ret; +} + +static int ssd_save_smart(struct ssd_device *dev) +{ + uint32_t off, size; + int i; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + if (!ssd_update_smart(dev, &dev->smart)) { + return 0; + } + + dev->smart.version++; + + for (i=0; irom_info.nr_smart; i++) { + off = dev->rom_info.smart_base + (dev->rom_info.smart_sz * i); + size = dev->rom_info.smart_sz; + + ret = ssd_spi_erase(dev, off, size); + if (ret) { + hio_warn("%s: info erase failed\n", dev->name); + goto out; + } + + size = sizeof(struct ssd_smart); + + ret = ssd_spi_write(dev, &dev->smart, off, size); + if (ret) { + hio_warn("%s: info write failed\n", dev->name); + goto out; + } + + //xx + } + +out: + return ret; +} + +static int ssd_init_smart(struct ssd_device *dev) +{ + struct ssd_smart *smart; + struct timeval tv; + uint32_t off, size; + int i; + int ret = 0; + + do_gettimeofday(&tv); + dev->uptime = tv.tv_sec; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + smart = kmalloc(sizeof(struct ssd_smart) * SSD_ROM_NR_SMART_MAX, GFP_KERNEL); + if (!smart) { + ret = -ENOMEM; + goto out_nomem; + } + + memset(&dev->smart, 0, sizeof(struct ssd_smart)); + + /* read smart */ + for (i=0; irom_info.nr_smart; i++) { + memset(&smart[i], 0, sizeof(struct ssd_smart)); + + off = dev->rom_info.smart_base + (dev->rom_info.smart_sz * i); + size = sizeof(struct ssd_smart); + + ret = ssd_spi_read(dev, &smart[i], off, size); + if (ret) { + hio_warn("%s: info read failed\n", dev->name); + goto out; + } + + if (smart[i].magic != SSD_SMART_MAGIC) { + smart[i].magic = 0; + smart[i].version = 0; + continue; + } + + if (smart[i].version > dev->smart.version) { + memcpy(&dev->smart, &smart[i], sizeof(struct ssd_smart)); + } + } + + if (dev->smart.magic != SSD_SMART_MAGIC) { + /* first time power up */ + dev->smart.magic = SSD_SMART_MAGIC; + dev->smart.version = 1; + } + + /* check log info */ + { + struct ssd_log_info log_info; + struct ssd_log *log = (struct ssd_log *)dev->internal_log.log; + + memset(&log_info, 0, sizeof(struct ssd_log_info)); + + while (log_info.nr_log < dev->internal_log.nr_log) { + /* skip the volatile log info */ + if (SSD_LOG_SEU_FAULT != log->le.event && SSD_LOG_SEU_FAULT1 != log->le.event) { + log_info.stat[ssd_parse_log(dev, log, 0)]++; + } + + log_info.nr_log++; + log++; + } + + /* check */ + for (i=(SSD_LOG_NR_LEVEL-1); i>=0; i--) { + if (log_info.stat[i] > dev->smart.log_info.stat[i]) { + /* unclean */ + memcpy(&dev->smart.log_info, &log_info, sizeof(struct ssd_log_info)); + dev->smart.version++; + break; + } + } + } + + for (i=0; irom_info.nr_smart; i++) { + if (smart[i].magic == SSD_SMART_MAGIC && smart[i].version == dev->smart.version) { + continue; + } + + off = dev->rom_info.smart_base + (dev->rom_info.smart_sz * i); + size = dev->rom_info.smart_sz; + + ret = ssd_spi_erase(dev, off, size); + if (ret) { + hio_warn("%s: info erase failed\n", dev->name); + goto out; + } + + size = sizeof(struct ssd_smart); + ret = ssd_spi_write(dev, &dev->smart, off, size); + if (ret) { + hio_warn("%s: info write failed\n", dev->name); + goto out; + } + + //xx + } + + /* sync smart with alarm led */ + if (dev->smart.io_stat.nr_to || dev->smart.io_stat.nr_rwerr || dev->smart.log_info.stat[SSD_LOG_LEVEL_ERR]) { + hio_warn("%s: some fault found in the history info\n", dev->name); + ssd_set_alarm(dev); + } + +out: + kfree(smart); +out_nomem: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +/* bm */ +static int __ssd_bm_get_version(struct ssd_device *dev, uint16_t *ver) +{ + struct ssd_bm_manufacturer_data bm_md = {0}; + uint16_t sc_id = SSD_BM_SYSTEM_DATA_SUBCLASS_ID; + uint8_t cmd; + int ret = 0; + + if (!dev || !ver) { + return -EINVAL; + } + + mutex_lock(&dev->bm_mutex); + + cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID; + ret = ssd_smbus_write_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&sc_id); + if (ret) { + goto out; + } + + cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID_PAGE1; + ret = ssd_smbus_read_block(dev, SSD_BM_SLAVE_ADDRESS, cmd, sizeof(struct ssd_bm_manufacturer_data), (uint8_t *)&bm_md); + if (ret) { + goto out; + } + + if (bm_md.firmware_ver & 0xF000) { + ret = -EIO; + goto out; + } + + *ver = bm_md.firmware_ver; + +out: + mutex_unlock(&dev->bm_mutex); + return ret; +} + +static int ssd_bm_get_version(struct ssd_device *dev, uint16_t *ver) +{ + uint16_t tmp = 0; + int i = SSD_BM_RETRY_MAX; + int ret = 0; + + while (i-- > 0) { + ret = __ssd_bm_get_version(dev, &tmp); + if (!ret) { + break; + } + } + if (ret) { + return ret; + } + + *ver = tmp; + + return 0; +} + +static int __ssd_bm_nr_cap(struct ssd_device *dev, int *nr_cap) +{ + struct ssd_bm_configuration_registers bm_cr; + uint16_t sc_id = SSD_BM_CONFIGURATION_REGISTERS_ID; + uint8_t cmd; + int ret; + + mutex_lock(&dev->bm_mutex); + + cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID; + ret = ssd_smbus_write_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&sc_id); + if (ret) { + goto out; + } + + cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID_PAGE1; + ret = ssd_smbus_read_block(dev, SSD_BM_SLAVE_ADDRESS, cmd, sizeof(struct ssd_bm_configuration_registers), (uint8_t *)&bm_cr); + if (ret) { + goto out; + } + + if (bm_cr.operation_cfg.cc == 0 || bm_cr.operation_cfg.cc > 4) { + ret = -EIO; + goto out; + } + + *nr_cap = bm_cr.operation_cfg.cc + 1; + +out: + mutex_unlock(&dev->bm_mutex); + return ret; +} + +static int ssd_bm_nr_cap(struct ssd_device *dev, int *nr_cap) +{ + int tmp = 0; + int i = SSD_BM_RETRY_MAX; + int ret = 0; + + while (i-- > 0) { + ret = __ssd_bm_nr_cap(dev, &tmp); + if (!ret) { + break; + } + } + if (ret) { + return ret; + } + + *nr_cap = tmp; + + return 0; +} + +static int ssd_bm_enter_cap_learning(struct ssd_device *dev) +{ + uint16_t buf = SSD_BM_ENTER_CAP_LEARNING; + uint8_t cmd = SSD_BM_MANUFACTURERACCESS; + int ret; + + ret = ssd_smbus_write_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&buf); + if (ret) { + goto out; + } + +out: + return ret; +} + +static int ssd_bm_get_sfstatus(struct ssd_device *dev, uint16_t *status) +{ + uint16_t val = 0; + uint8_t cmd = SSD_BM_SAFETYSTATUS; + int ret; + + ret = ssd_smbus_read_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&val); + if (ret) { + goto out; + } + + *status = val; +out: + return ret; +} + +static int ssd_bm_get_opstatus(struct ssd_device *dev, uint16_t *status) +{ + uint16_t val = 0; + uint8_t cmd = SSD_BM_OPERATIONSTATUS; + int ret; + + ret = ssd_smbus_read_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&val); + if (ret) { + goto out; + } + + *status = val; +out: + return ret; +} + +static int ssd_get_bmstruct(struct ssd_device *dev, struct ssd_bm *bm_status_out) +{ + struct sbs_cmd *bm_sbs = ssd_bm_sbs; + struct ssd_bm bm_status; + uint8_t buf[2] = {0, }; + uint16_t val = 0; + uint16_t cval; + int ret = 0; + + memset(&bm_status, 0, sizeof(struct ssd_bm)); + + while (bm_sbs->desc != NULL) { + switch (bm_sbs->size) { + case SBS_SIZE_BYTE: + ret = ssd_smbus_read_byte(dev, SSD_BM_SLAVE_ADDRESS, bm_sbs->cmd, buf); + if (ret) { + //printf("Error: smbus read byte %#x\n", bm_sbs->cmd); + goto out; + } + val = buf[0]; + break; + case SBS_SIZE_WORD: + ret = ssd_smbus_read_word(dev, SSD_BM_SLAVE_ADDRESS, bm_sbs->cmd, (uint8_t *)&val); + if (ret) { + //printf("Error: smbus read word %#x\n", bm_sbs->cmd); + goto out; + } + //val = *(uint16_t *)buf; + break; + default: + ret = -1; + goto out; + break; + } + + switch (bm_sbs->unit) { + case SBS_UNIT_VALUE: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val & bm_sbs->mask; + break; + case SBS_UNIT_TEMPERATURE: + cval = (uint16_t)(val - 2731) / 10; + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = cval; + break; + case SBS_UNIT_VOLTAGE: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val; + break; + case SBS_UNIT_CURRENT: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val; + break; + case SBS_UNIT_ESR: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val; + break; + case SBS_UNIT_PERCENT: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val; + break; + case SBS_UNIT_CAPACITANCE: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val; + break; + default: + ret = -1; + goto out; + break; + } + + bm_sbs++; + } + + memcpy(bm_status_out, &bm_status, sizeof(struct ssd_bm)); + +out: + return ret; +} + +static int __ssd_bm_status(struct ssd_device *dev, int *status) +{ + struct ssd_bm bm_status = {0}; + int nr_cap = 0; + int i; + int ret = 0; + + ret = ssd_get_bmstruct(dev, &bm_status); + if (ret) { + goto out; + } + + /* capacitor voltage */ + ret = ssd_bm_nr_cap(dev, &nr_cap); + if (ret) { + goto out; + } + + for (i=0; i> 12) & 0x1)) { + *status = SSD_BMSTATUS_CHARGING; + }else{ + *status = SSD_BMSTATUS_OK; + } + +out: + return ret; +} + +static void ssd_set_flush_timeout(struct ssd_device *dev, int mode); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static void ssd_bm_worker(void *data) +{ + struct ssd_device *dev = (struct ssd_device *)data; +#else +static void ssd_bm_worker(struct work_struct *work) +{ + struct ssd_device *dev = container_of(work, struct ssd_device, bm_work); +#endif + + uint16_t opstatus; + int ret = 0; + + if (mode != SSD_DRV_MODE_STANDARD) { + return; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) { + return; + } + + if (dev->hw_info_ext.plp_type != SSD_PLP_SCAP) { + return; + } + + ret = ssd_bm_get_opstatus(dev, &opstatus); + if (ret) { + hio_warn("%s: get bm operationstatus failed\n", dev->name); + return; + } + + /* need cap learning ? */ + if (!(opstatus & 0xF0)) { + ret = ssd_bm_enter_cap_learning(dev); + if (ret) { + hio_warn("%s: enter capacitance learning failed\n", dev->name); + return; + } + } +} + +static void ssd_bm_routine_start(void *data) +{ + struct ssd_device *dev; + + if (!data) { + return; + } + dev = data; + + if (test_bit(SSD_INIT_WORKQ, &dev->state)) { + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + queue_work(dev->workq, &dev->bm_work); + } else { + queue_work(dev->workq, &dev->capmon_work); + } + } +} + +/* CAP */ +static int ssd_do_cap_learn(struct ssd_device *dev, uint32_t *cap) +{ + uint32_t u1, u2, t; + uint16_t val = 0; + int wait = 0; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + *cap = 0; + return 0; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + *cap = 0; + return 0; + } + + /* make sure the lm80 voltage value is updated */ + msleep(SSD_LM80_CONV_INTERVAL); + + /* check if full charged */ + wait = 0; + for (;;) { + ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U1, (uint8_t *)&val); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + u1 = SSD_LM80_CONVERT_VOLT(u16_swap(val)); + if (SSD_PL_CAP_VOLT(u1) >= SSD_PL_CAP_VOLT_FULL) { + break; + } + + wait++; + if (wait > SSD_PL_CAP_CHARGE_MAX_WAIT) { + ret = -ETIMEDOUT; + goto out; + } + msleep(SSD_PL_CAP_CHARGE_WAIT); + } + + ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U2, (uint8_t *)&val); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + u2 = SSD_LM80_CONVERT_VOLT(u16_swap(val)); + + if (u1 == u2) { + ret = -EINVAL; + goto out; + } + + /* enter cap learn */ + ssd_reg32_write(dev->ctrlp + SSD_PL_CAP_LEARN_REG, 0x1); + + wait = 0; + for (;;) { + msleep(SSD_PL_CAP_LEARN_WAIT); + + t = ssd_reg32_read(dev->ctrlp + SSD_PL_CAP_LEARN_REG); + if (!((t >> 1) & 0x1)) { + break; + } + + wait++; + if (wait > SSD_PL_CAP_LEARN_MAX_WAIT) { + ret = -ETIMEDOUT; + goto out; + } + } + + if ((t >> 4) & 0x1) { + ret = -ETIMEDOUT; + goto out; + } + + t = (t >> 8); + if (0 == t) { + ret = -EINVAL; + goto out; + } + + *cap = SSD_PL_CAP_LEARN(u1, u2, t); + +out: + return ret; +} + +static int ssd_cap_learn(struct ssd_device *dev, uint32_t *cap) +{ + int ret = 0; + + if (!dev || !cap) { + return -EINVAL; + } + + mutex_lock(&dev->bm_mutex); + + ssd_stop_workq(dev); + + ret = ssd_do_cap_learn(dev, cap); + if (ret) { + ssd_gen_swlog(dev, SSD_LOG_CAP_LEARN_FAULT, 0); + goto out; + } + + ssd_gen_swlog(dev, SSD_LOG_CAP_STATUS, *cap); + +out: + ssd_start_workq(dev); + mutex_unlock(&dev->bm_mutex); + + return ret; +} + +static int ssd_check_pl_cap(struct ssd_device *dev) +{ + uint32_t u1; + uint16_t val = 0; + uint8_t low = 0; + int wait = 0; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + return 0; + } + + /* cap ready ? */ + wait = 0; + for (;;) { + ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U1, (uint8_t *)&val); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + u1 = SSD_LM80_CONVERT_VOLT(u16_swap(val)); + if (SSD_PL_CAP_VOLT(u1) >= SSD_PL_CAP_VOLT_READY) { + break; + } + + wait++; + if (wait > SSD_PL_CAP_CHARGE_MAX_WAIT) { + ret = -ETIMEDOUT; + ssd_gen_swlog(dev, SSD_LOG_CAP_VOLT_FAULT, SSD_PL_CAP_VOLT(u1)); + goto out; + } + msleep(SSD_PL_CAP_CHARGE_WAIT); + } + + low = ssd_lm80_limit[SSD_LM80_IN_CAP].low; + ret = ssd_smbus_write_byte(dev, SSD_SENSOR_LM80_SADDRESS, SSD_LM80_REG_IN_MIN(SSD_LM80_IN_CAP), &low); + if (ret) { + goto out; + } + + /* enable cap INx */ + ret = ssd_lm80_enable_in(dev, SSD_SENSOR_LM80_SADDRESS, SSD_LM80_IN_CAP); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +static int ssd_check_pl_cap_fast(struct ssd_device *dev) +{ + uint32_t u1; + uint16_t val = 0; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + return 0; + } + + /* cap ready ? */ + ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U1, (uint8_t *)&val); + if (ret) { + goto out; + } + u1 = SSD_LM80_CONVERT_VOLT(u16_swap(val)); + if (SSD_PL_CAP_VOLT(u1) < SSD_PL_CAP_VOLT_READY) { + ret = 1; + } + +out: + return ret; +} + +static int ssd_init_pl_cap(struct ssd_device *dev) +{ + int ret = 0; + + /* set here: user write mode */ + dev->user_wmode = wmode; + + mutex_init(&dev->bm_mutex); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + uint32_t val; + val = ssd_reg32_read(dev->ctrlp + SSD_BM_FAULT_REG); + if ((val >> 1) & 0x1) { + (void)test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon); + } + } else { + ret = ssd_check_pl_cap(dev); + if (ret) { + (void)test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon); + } + } + + return 0; +} + +/* label */ +static void __end_str(char *str, int len) +{ + int i; + + for(i=0; irom_info.label_base; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + size = sizeof(struct ssd_label); + + /* read label */ + ret = ssd_spi_read(dev, &dev->label, off, size); + if (ret) { + memset(&dev->label, 0, size); + goto out; + } + + __end_str(dev->label.date, SSD_LABEL_FIELD_SZ); + __end_str(dev->label.sn, SSD_LABEL_FIELD_SZ); + __end_str(dev->label.part, SSD_LABEL_FIELD_SZ); + __end_str(dev->label.desc, SSD_LABEL_FIELD_SZ); + __end_str(dev->label.other, SSD_LABEL_FIELD_SZ); + __end_str(dev->label.maf, SSD_LABEL_FIELD_SZ); + } else { + size = sizeof(struct ssd_labelv3); + + /* read label */ + ret = ssd_spi_read(dev, &dev->labelv3, off, size); + if (ret) { + memset(&dev->labelv3, 0, size); + goto out; + } + + __end_str(dev->labelv3.boardtype, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.barcode, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.item, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.description, SSD_LABEL_DESC_SZ); + __end_str(dev->labelv3.manufactured, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.vendorname, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.issuenumber, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.cleicode, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.bom, SSD_LABEL_FIELD_SZ); + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +int ssd_get_label(struct block_device *bdev, struct ssd_label *label) +{ + struct ssd_device *dev; + + if (!bdev || !label || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + memset(label, 0, sizeof(struct ssd_label)); + memcpy(label->date, dev->labelv3.manufactured, SSD_LABEL_FIELD_SZ); + memcpy(label->sn, dev->labelv3.barcode, SSD_LABEL_FIELD_SZ); + memcpy(label->desc, dev->labelv3.boardtype, SSD_LABEL_FIELD_SZ); + memcpy(label->maf, dev->labelv3.vendorname, SSD_LABEL_FIELD_SZ); + } else { + memcpy(label, &dev->label, sizeof(struct ssd_label)); + } + + return 0; +} + +static int __ssd_get_version(struct ssd_device *dev, struct ssd_version_info *ver) +{ + uint16_t bm_ver = 0; + int ret = 0; + + if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + ret = ssd_bm_get_version(dev, &bm_ver); + if(ret){ + goto out; + } + } + + ver->bridge_ver = dev->hw_info.bridge_ver; + ver->ctrl_ver = dev->hw_info.ctrl_ver; + ver->bm_ver = bm_ver; + ver->pcb_ver = dev->hw_info.pcb_ver; + ver->upper_pcb_ver = dev->hw_info.upper_pcb_ver; + +out: + return ret; + +} + +int ssd_get_version(struct block_device *bdev, struct ssd_version_info *ver) +{ + struct ssd_device *dev; + int ret; + + if (!bdev || !ver || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + mutex_lock(&dev->fw_mutex); + ret = __ssd_get_version(dev, ver); + mutex_unlock(&dev->fw_mutex); + + return ret; +} + +static int __ssd_get_temperature(struct ssd_device *dev, int *temp) +{ + uint64_t val; + uint32_t off; + int max = -300; + int cur; + int i; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + *temp = 0; + return 0; + } + + if (finject) { + if (dev->db_info.type == SSD_DEBUG_LOG && + (dev->db_info.data.log.event == SSD_LOG_OVER_TEMP || + dev->db_info.data.log.event == SSD_LOG_NORMAL_TEMP || + dev->db_info.data.log.event == SSD_LOG_WARN_TEMP)) { + *temp = (int)dev->db_info.data.log.extra; + return 0; + } + } + + for (i=0; ihw_info.nr_ctrl; i++) { + off = SSD_CTRL_TEMP_REG0 + i * sizeof(uint64_t); + + val = ssd_reg_read(dev->ctrlp + off); + if (val == 0xffffffffffffffffull) { + continue; + } + + cur = (int)CUR_TEMP(val); + if (cur >= max) { + max = cur; + } + } + + *temp = max; + + return 0; +} + +int ssd_get_temperature(struct block_device *bdev, int *temp) +{ + struct ssd_device *dev; + int ret; + + if (!bdev || !temp || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + + mutex_lock(&dev->fw_mutex); + ret = __ssd_get_temperature(dev, temp); + mutex_unlock(&dev->fw_mutex); + + return ret; +} + +int ssd_set_otprotect(struct block_device *bdev, int otprotect) + { + struct ssd_device *dev; + + if (!bdev || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + ssd_set_ot_protect(dev, !!otprotect); + + return 0; + } + +int ssd_bm_status(struct block_device *bdev, int *status) +{ + struct ssd_device *dev; + int ret = 0; + + if (!bdev || !status || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + mutex_lock(&dev->fw_mutex); + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + *status = SSD_BMSTATUS_WARNING; + } else { + *status = SSD_BMSTATUS_OK; + } + } else if(dev->protocol_info.ver > SSD_PROTOCOL_V3) { + ret = __ssd_bm_status(dev, status); + } else { + *status = SSD_BMSTATUS_OK; + } + mutex_unlock(&dev->fw_mutex); + + return ret; +} + +int ssd_get_pciaddr(struct block_device *bdev, struct pci_addr *paddr) +{ + struct ssd_device *dev; + + if (!bdev || !paddr || !bdev->bd_disk) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + paddr->domain = pci_domain_nr(dev->pdev->bus); + paddr->bus = dev->pdev->bus->number; + paddr->slot = PCI_SLOT(dev->pdev->devfn); + paddr->func= PCI_FUNC(dev->pdev->devfn); + + return 0; +} + +/* acc */ +static int ssd_bb_acc(struct ssd_device *dev, struct ssd_acc_info *acc) +{ + uint32_t val; + int ctrl, chip; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) { + return -EOPNOTSUPP; + } + + acc->threshold_l1 = ssd_reg32_read(dev->ctrlp + SSD_BB_THRESHOLD_L1_REG); + if (0xffffffffull == acc->threshold_l1) { + return -EIO; + } + acc->threshold_l2 = ssd_reg32_read(dev->ctrlp + SSD_BB_THRESHOLD_L2_REG); + if (0xffffffffull == acc->threshold_l2) { + return -EIO; + } + acc->val = 0; + + for (ctrl=0; ctrlhw_info.nr_ctrl; ctrl++) { + for (chip=0; chiphw_info.nr_chip; chip++) { + val = ssd_reg32_read(dev->ctrlp + SSD_BB_ACC_REG0 + (SSD_CTRL_REG_ZONE_SZ * ctrl) + (SSD_BB_ACC_REG_SZ * chip)); + if (0xffffffffull == acc->val) { + return -EIO; + } + if (val > acc->val) { + acc->val = val; + } + } + } + + return 0; +} + +static int ssd_ec_acc(struct ssd_device *dev, struct ssd_acc_info *acc) +{ + uint32_t val; + int ctrl, chip; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) { + return -EOPNOTSUPP; + } + + acc->threshold_l1 = ssd_reg32_read(dev->ctrlp + SSD_EC_THRESHOLD_L1_REG); + if (0xffffffffull == acc->threshold_l1) { + return -EIO; + } + acc->threshold_l2 = ssd_reg32_read(dev->ctrlp + SSD_EC_THRESHOLD_L2_REG); + if (0xffffffffull == acc->threshold_l2) { + return -EIO; + } + acc->val = 0; + + for (ctrl=0; ctrlhw_info.nr_ctrl; ctrl++) { + for (chip=0; chiphw_info.nr_chip; chip++) { + val = ssd_reg32_read(dev->ctrlp + SSD_EC_ACC_REG0 + (SSD_CTRL_REG_ZONE_SZ * ctrl) + (SSD_EC_ACC_REG_SZ * chip)); + if (0xffffffffull == acc->val) { + return -EIO; + } + + if (val > acc->val) { + acc->val = val; + } + } + } + + return 0; +} + + +/* ram r&w */ +static int ssd_ram_read_4k(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx) +{ + struct ssd_ram_op_msg *msg; + dma_addr_t buf_dma; + size_t len = length; + loff_t ofs_w = ofs; + int ret = 0; + + if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size + || !length || length > dev->hw_info.ram_max_len + || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) { + return -EINVAL; + } + + len /= dev->hw_info.ram_align; + do_div(ofs_w, dev->hw_info.ram_align); + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map read DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + msg = (struct ssd_ram_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_RAM_READ; + msg->ctrl_idx = ctrl_idx; + msg->start = (uint32_t)ofs_w; + msg->length = len; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, READ, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE); + +out_dma_mapping: + return ret; +} + +static int ssd_ram_write_4k(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx) +{ + struct ssd_ram_op_msg *msg; + dma_addr_t buf_dma; + size_t len = length; + loff_t ofs_w = ofs; + int ret = 0; + + if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size + || !length || length > dev->hw_info.ram_max_len + || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) { + return -EINVAL; + } + + len /= dev->hw_info.ram_align; + do_div(ofs_w, dev->hw_info.ram_align); + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_TODEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map write DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + msg = (struct ssd_ram_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_RAM_WRITE; + msg->ctrl_idx = ctrl_idx; + msg->start = (uint32_t)ofs_w; + msg->length = len; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_TODEVICE); + +out_dma_mapping: + return ret; + +} + +static int ssd_ram_read(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx) +{ + int left = length; + size_t len; + loff_t off = ofs; + int ret = 0; + + if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size || !length + || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) { + return -EINVAL; + } + + while (left > 0) { + len = dev->hw_info.ram_max_len; + if (left < (int)dev->hw_info.ram_max_len) { + len = left; + } + + ret = ssd_ram_read_4k(dev, buf, len, off, ctrl_idx); + if (ret) { + break; + } + + left -= len; + off += len; + buf += len; + } + + return ret; +} + +static int ssd_ram_write(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx) +{ + int left = length; + size_t len; + loff_t off = ofs; + int ret = 0; + + if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size || !length + || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) { + return -EINVAL; + } + + while (left > 0) { + len = dev->hw_info.ram_max_len; + if (left < (int)dev->hw_info.ram_max_len) { + len = left; + } + + ret = ssd_ram_write_4k(dev, buf, len, off, ctrl_idx); + if (ret) { + break; + } + + left -= len; + off += len; + buf += len; + } + + return ret; +} + + +/* flash op */ +static int ssd_check_flash(struct ssd_device *dev, int flash, int page, int ctrl_idx) +{ + int cur_ch = flash % dev->hw_info.max_ch; + int cur_chip = flash /dev->hw_info.max_ch; + + if (ctrl_idx >= dev->hw_info.nr_ctrl) { + return -EINVAL; + } + + if (cur_ch >= dev->hw_info.nr_ch || cur_chip >= dev->hw_info.nr_chip) { + return -EINVAL; + } + + if (page >= (int)(dev->hw_info.block_count * dev->hw_info.page_count)) { + return -EINVAL; + } + return 0; +} + +static int ssd_nand_read_id(struct ssd_device *dev, void *id, int flash, int chip, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + dma_addr_t buf_dma; + int ret = 0; + + if (unlikely(!id)) + return -EINVAL; + + buf_dma = pci_map_single(dev->pdev, id, SSD_NAND_ID_BUFF_SZ, PCI_DMA_FROMDEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map read DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + flash = ((uint32_t)flash << 1) | (uint32_t)chip; + chip = 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_NAND_READ_ID; + msg->chip_no = flash; + msg->chip_ce = chip; + msg->ctrl_idx = ctrl_idx; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, READ, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, SSD_NAND_ID_BUFF_SZ, PCI_DMA_FROMDEVICE); + +out_dma_mapping: + return ret; +} + +#if 0 +static int ssd_nand_read(struct ssd_device *dev, void *buf, + int flash, int chip, int page, int page_count, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + dma_addr_t buf_dma; + int length; + int ret = 0; + + if (!buf) { + return -EINVAL; + } + + if ((page + page_count) > dev->hw_info.block_count*dev->hw_info.page_count) { + return -EINVAL; + } + + ret = ssd_check_flash(dev, flash, page, ctrl_idx); + if (ret) { + return ret; + } + + length = page_count * dev->hw_info.page_size; + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map read DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + flash = (flash << 1) | chip; + chip = 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_NAND_READ; + msg->ctrl_idx = ctrl_idx; + msg->chip_no = flash; + msg->chip_ce = chip; + msg->page_no = page; + msg->page_count = page_count; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, READ, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE); + +out_dma_mapping: + return ret; +} +#endif + +static int ssd_nand_read_w_oob(struct ssd_device *dev, void *buf, + int flash, int chip, int page, int count, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + dma_addr_t buf_dma; + int length; + int ret = 0; + + if (!buf) { + return -EINVAL; + } + + if ((page + count) > (int)(dev->hw_info.block_count * dev->hw_info.page_count)) { + return -EINVAL; + } + + ret = ssd_check_flash(dev, flash, page, ctrl_idx); + if (ret) { + return ret; + } + + length = count * (dev->hw_info.page_size + dev->hw_info.oob_size); + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map read DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + flash = ((uint32_t)flash << 1) | (uint32_t)chip; + chip = 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_NAND_READ_WOOB; + msg->ctrl_idx = ctrl_idx; + msg->chip_no = flash; + msg->chip_ce = chip; + msg->page_no = page; + msg->page_count = count; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, READ, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE); + +out_dma_mapping: + return ret; +} + +/* write 1 page */ +static int ssd_nand_write(struct ssd_device *dev, void *buf, + int flash, int chip, int page, int count, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + dma_addr_t buf_dma; + int length; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + return -EINVAL; + } + + if (!buf) { + return -EINVAL; + } + + if (count != 1) { + return -EINVAL; + } + + ret = ssd_check_flash(dev, flash, page, ctrl_idx); + if (ret) { + return ret; + } + + length = count * (dev->hw_info.page_size + dev->hw_info.oob_size); + + /* write data to ram */ + /*ret = ssd_ram_write(dev, buf, length, dev->hw_info.nand_wbuff_base, ctrl_idx); + if (ret) { + return ret; + }*/ + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_TODEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map write DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + flash = ((uint32_t)flash << 1) | (uint32_t)chip; + chip = 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_NAND_WRITE; + msg->ctrl_idx = ctrl_idx; + msg->chip_no = flash; + msg->chip_ce = chip; + + msg->page_no = page; + msg->page_count = count; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_TODEVICE); + +out_dma_mapping: + return ret; +} + +static int ssd_nand_erase(struct ssd_device *dev, int flash, int chip, int page, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + int ret = 0; + + ret = ssd_check_flash(dev, flash, page, ctrl_idx); + if (ret) { + return ret; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + flash = ((uint32_t)flash << 1) | (uint32_t)chip; + chip = 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_NAND_ERASE; + msg->ctrl_idx = ctrl_idx; + msg->chip_no = flash; + msg->chip_ce = chip; + msg->page_no = page; + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +static int ssd_update_bbt(struct ssd_device *dev, int flash, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + struct ssd_flush_msg *fmsg; + int ret = 0; + + ret = ssd_check_flash(dev, flash, 0, ctrl_idx); + if (ret) { + return ret; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + fmsg = (struct ssd_flush_msg *)msg; + + fmsg->fun = SSD_FUNC_FLUSH; + fmsg->flag = 0x1; + fmsg->flash = flash; + fmsg->ctrl_idx = ctrl_idx; + } else { + msg->fun = SSD_FUNC_FLUSH; + msg->flag = 0x1; + msg->chip_no = flash; + msg->ctrl_idx = ctrl_idx; + } + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +/* flash controller init state */ +static int __ssd_check_init_state(struct ssd_device *dev) +{ + uint32_t *init_state = NULL; + int reg_base, reg_sz; + int max_wait = SSD_INIT_MAX_WAIT; + int init_wait = 0; + int i, j, k; + int ch_start = 0; + +/* + for (i=0; ihw_info.nr_ctrl; i++) { + ssd_reg32_write(dev->ctrlp + SSD_CTRL_TEST_REG0 + i * 8, test_data); + read_data = ssd_reg32_read(dev->ctrlp + SSD_CTRL_TEST_REG0 + i * 8); + if (read_data == ~test_data) { + //dev->hw_info.nr_ctrl++; + dev->hw_info.nr_ctrl_map |= 1<ctrlp + SSD_READY_REG); + j=0; + for (i=0; ihw_info.nr_ctrl; i++) { + if (((read_data>>i) & 0x1) == 0) { + j++; + } + } + + if (dev->hw_info.nr_ctrl != j) { + printk(KERN_WARNING "%s: nr_ctrl mismatch: %d %d\n", dev->name, dev->hw_info.nr_ctrl, j); + return -1; + } +*/ + +/* + init_state = ssd_reg_read(dev->ctrlp + SSD_FLASH_INFO_REG0); + for (j=1; jhw_info.nr_ctrl;j++) { + if (init_state != ssd_reg_read(dev->ctrlp + SSD_FLASH_INFO_REG0 + j*8)) { + printk(KERN_WARNING "SSD_FLASH_INFO_REG[%d], not match\n", j); + return -1; + } + } +*/ + +/* init_state = ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0); + for (j=1; jhw_info.nr_ctrl; j++) { + if (init_state != ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0 + j*16)) { + printk(KERN_WARNING "SSD_CHIP_INFO_REG Lo [%d], not match\n", j); + return -1; + } + } + + init_state = ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0 + 8); + for (j=1; jhw_info.nr_ctrl; j++) { + if (init_state != ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0 + 8 + j*16)) { + printk(KERN_WARNING "SSD_CHIP_INFO_REG Hi [%d], not match\n", j); + return -1; + } + } +*/ + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + max_wait = SSD_INIT_MAX_WAIT_V3_2; + } + + reg_base = dev->protocol_info.init_state_reg; + reg_sz = dev->protocol_info.init_state_reg_sz; + + init_state = (uint32_t *)kmalloc(reg_sz, GFP_KERNEL); + if (!init_state) { + return -ENOMEM; + } + + for (i=0; ihw_info.nr_ctrl; i++) { +check_init: + for (j=0, k=0; jctrlp + reg_base + j); + } + + if (dev->protocol_info.ver > SSD_PROTOCOL_V3) { + /* just check the last bit, no need to check all channel */ + ch_start = dev->hw_info.max_ch - 1; + } else { + ch_start = 0; + } + + for (j=0; jhw_info.nr_chip; j++) { + for (k=ch_start; khw_info.max_ch; k++) { + if (test_bit((j*dev->hw_info.max_ch + k), (void *)init_state)) { + continue; + } + + init_wait++; + if (init_wait <= max_wait) { + msleep(SSD_INIT_WAIT); + goto check_init; + } else { + if (k < dev->hw_info.nr_ch) { + hio_warn("%s: controller %d chip %d ch %d init failed\n", + dev->name, i, j, k); + } else { + hio_warn("%s: controller %d chip %d init failed\n", + dev->name, i, j); + } + + kfree(init_state); + return -1; + } + } + } + reg_base += reg_sz; + } + //printk(KERN_WARNING "%s: init wait %d\n", dev->name, init_wait); + + kfree(init_state); + return 0; +} + +static int ssd_check_init_state(struct ssd_device *dev) +{ + if (mode != SSD_DRV_MODE_STANDARD) { + return 0; + } + + return __ssd_check_init_state(dev); +} + +static void ssd_reset_resp_ptr(struct ssd_device *dev); + +/* reset flash controller etc */ +static int __ssd_reset(struct ssd_device *dev, int type) +{ + if (type < SSD_RST_NOINIT || type > SSD_RST_FULL) { + return -EINVAL; + } + + mutex_lock(&dev->fw_mutex); + + if (type == SSD_RST_NOINIT) { //no init + ssd_reg32_write(dev->ctrlp + SSD_RESET_REG, SSD_RESET_NOINIT); + } else if (type == SSD_RST_NORMAL) { //reset & init + ssd_reg32_write(dev->ctrlp + SSD_RESET_REG, SSD_RESET); + } else { // full reset + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + mutex_unlock(&dev->fw_mutex); + return -EINVAL; + } + + ssd_reg32_write(dev->ctrlp + SSD_FULL_RESET_REG, SSD_RESET_FULL); + + /* ?? */ + ssd_reset_resp_ptr(dev); + } + +#ifdef SSD_OT_PROTECT + dev->ot_delay = 0; +#endif + + msleep(1000); + + /* xx */ + ssd_set_flush_timeout(dev, dev->wmode); + + mutex_unlock(&dev->fw_mutex); + ssd_gen_swlog(dev, SSD_LOG_RESET, (uint32_t)type); + + return __ssd_check_init_state(dev); +} + +static int ssd_save_md(struct ssd_device *dev) +{ + struct ssd_nand_op_msg *msg; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + if (!dev->save_md) { + return 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_FLUSH; + msg->flag = 0x2; + msg->ctrl_idx = 0; + msg->chip_no = 0; + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +static int ssd_barrier_save_md(struct ssd_device *dev) +{ + struct ssd_nand_op_msg *msg; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + if (!dev->save_md) { + return 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_FLUSH; + msg->flag = 0x2; + msg->ctrl_idx = 0; + msg->chip_no = 0; + + ret = ssd_do_barrier_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +static int ssd_flush(struct ssd_device *dev) +{ + struct ssd_nand_op_msg *msg; + struct ssd_flush_msg *fmsg; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + fmsg = (struct ssd_flush_msg *)msg; + + fmsg->fun = SSD_FUNC_FLUSH; + fmsg->flag = 0; + fmsg->ctrl_idx = 0; + fmsg->flash = 0; + } else { + msg->fun = SSD_FUNC_FLUSH; + msg->flag = 0; + msg->ctrl_idx = 0; + msg->chip_no = 0; + } + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +static int ssd_barrier_flush(struct ssd_device *dev) +{ + struct ssd_nand_op_msg *msg; + struct ssd_flush_msg *fmsg; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + fmsg = (struct ssd_flush_msg *)msg; + + fmsg->fun = SSD_FUNC_FLUSH; + fmsg->flag = 0; + fmsg->ctrl_idx = 0; + fmsg->flash = 0; + } else { + msg->fun = SSD_FUNC_FLUSH; + msg->flag = 0; + msg->ctrl_idx = 0; + msg->chip_no = 0; + } + + ret = ssd_do_barrier_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +#define SSD_WMODE_BUFFER_TIMEOUT 0x00c82710 +#define SSD_WMODE_BUFFER_EX_TIMEOUT 0x000500c8 +#define SSD_WMODE_FUA_TIMEOUT 0x000503E8 +static void ssd_set_flush_timeout(struct ssd_device *dev, int m) +{ + uint32_t to; + uint32_t val = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) { + return; + } + + switch(m) { + case SSD_WMODE_BUFFER: + to = SSD_WMODE_BUFFER_TIMEOUT; + break; + case SSD_WMODE_BUFFER_EX: + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2_1) { + to = SSD_WMODE_BUFFER_EX_TIMEOUT; + } else { + to = SSD_WMODE_BUFFER_TIMEOUT; + } + break; + case SSD_WMODE_FUA: + to = SSD_WMODE_FUA_TIMEOUT; + break; + default: + return; + } + + val = (((uint32_t)((uint32_t)m & 0x3) << 28) | to); + + ssd_reg32_write(dev->ctrlp + SSD_FLUSH_TIMEOUT_REG, val); +} + +static int ssd_do_switch_wmode(struct ssd_device *dev, int m) +{ + int ret = 0; + + ret = ssd_barrier_start(dev); + if (ret) { + goto out; + } + + ret = ssd_barrier_flush(dev); + if (ret) { + goto out_barrier_end; + } + + /* set contoller flush timeout */ + ssd_set_flush_timeout(dev, m); + + dev->wmode = m; + mb(); + +out_barrier_end: + ssd_barrier_end(dev); +out: + return ret; +} + +static int ssd_switch_wmode(struct ssd_device *dev, int m) +{ + int default_wmode; + int next_wmode; + int ret = 0; + + if (!test_bit(SSD_ONLINE, &dev->state)) { + return -ENODEV; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + default_wmode = SSD_WMODE_BUFFER; + } else { + default_wmode = SSD_WMODE_BUFFER_EX; + } + + if (SSD_WMODE_AUTO == m) { + /* battery fault ? */ + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + next_wmode = SSD_WMODE_FUA; + } else { + next_wmode = default_wmode; + } + } else if (SSD_WMODE_DEFAULT == m) { + next_wmode = default_wmode; + } else { + next_wmode = m; + } + + if (next_wmode != dev->wmode) { + hio_warn("%s: switch write mode (%d -> %d)\n", dev->name, dev->wmode, next_wmode); + ret = ssd_do_switch_wmode(dev, next_wmode); + if (ret) { + hio_err("%s: can not switch write mode (%d -> %d)\n", dev->name, dev->wmode, next_wmode); + } + } + + return ret; +} + +static int ssd_init_wmode(struct ssd_device *dev) +{ + int default_wmode; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + default_wmode = SSD_WMODE_BUFFER; + } else { + default_wmode = SSD_WMODE_BUFFER_EX; + } + + /* dummy mode */ + if (SSD_WMODE_AUTO == dev->user_wmode) { + /* battery fault ? */ + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + dev->wmode = SSD_WMODE_FUA; + } else { + dev->wmode = default_wmode; + } + } else if (SSD_WMODE_DEFAULT == dev->user_wmode) { + dev->wmode = default_wmode; + } else { + dev->wmode = dev->user_wmode; + } + ssd_set_flush_timeout(dev, dev->wmode); + + return ret; +} + +static int __ssd_set_wmode(struct ssd_device *dev, int m) +{ + int ret = 0; + + /* not support old fw*/ + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) { + ret = -EOPNOTSUPP; + goto out; + } + + if (m < SSD_WMODE_BUFFER || m > SSD_WMODE_DEFAULT) { + ret = -EINVAL; + goto out; + } + + ssd_gen_swlog(dev, SSD_LOG_SET_WMODE, m); + + dev->user_wmode = m; + + ret = ssd_switch_wmode(dev, dev->user_wmode); + if (ret) { + goto out; + } + +out: + return ret; +} + +int ssd_set_wmode(struct block_device *bdev, int m) +{ + struct ssd_device *dev; + + if (!bdev || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + return __ssd_set_wmode(dev, m); +} + +static int ssd_do_reset(struct ssd_device *dev) +{ + int ret = 0; + + if (test_and_set_bit(SSD_RESETING, &dev->state)) { + return 0; + } + + ssd_stop_workq(dev); + + ret = ssd_barrier_start(dev); + if (ret) { + goto out; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + /* old reset */ + ret = __ssd_reset(dev, SSD_RST_NORMAL); + } else { + /* full reset */ + //ret = __ssd_reset(dev, SSD_RST_FULL); + ret = __ssd_reset(dev, SSD_RST_NORMAL); + } + if (ret) { + goto out_barrier_end; + } + +out_barrier_end: + ssd_barrier_end(dev); +out: + ssd_start_workq(dev); + test_and_clear_bit(SSD_RESETING, &dev->state); + return ret; +} + +static int ssd_full_reset(struct ssd_device *dev) +{ + int ret = 0; + + if (test_and_set_bit(SSD_RESETING, &dev->state)) { + return 0; + } + + ssd_stop_workq(dev); + + ret = ssd_barrier_start(dev); + if (ret) { + goto out; + } + + ret = ssd_barrier_flush(dev); + if (ret) { + goto out_barrier_end; + } + + ret = ssd_barrier_save_md(dev); + if (ret) { + goto out_barrier_end; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + /* old reset */ + ret = __ssd_reset(dev, SSD_RST_NORMAL); + } else { + /* full reset */ + //ret = __ssd_reset(dev, SSD_RST_FULL); + ret = __ssd_reset(dev, SSD_RST_NORMAL); + } + if (ret) { + goto out_barrier_end; + } + +out_barrier_end: + ssd_barrier_end(dev); +out: + ssd_start_workq(dev); + test_and_clear_bit(SSD_RESETING, &dev->state); + return ret; +} + +int ssd_reset(struct block_device *bdev) +{ + struct ssd_device *dev; + + if (!bdev || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + return ssd_full_reset(dev); +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static int ssd_issue_flush_fn(struct request_queue *q, struct gendisk *disk, + sector_t *error_sector) +{ + struct ssd_device *dev = q->queuedata; + + return ssd_flush(dev); +} +#endif + +void ssd_submit_pbio(struct request_queue *q, struct bio *bio) +{ + struct ssd_device *dev = q->queuedata; +#ifdef SSD_QUEUE_PBIO + int ret = -EBUSY; +#endif + + if (!test_bit(SSD_ONLINE, &dev->state)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -ENODEV); +#else + bio_endio(bio, bio->bi_size, -ENODEV); +#endif + goto out; + } + +#ifdef SSD_DEBUG_ERR + if (atomic_read(&dev->tocnt)) { + hio_warn("%s: IO rejected because of IO timeout!\n", dev->name); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EIO); +#else + bio_endio(bio, bio->bi_size, -EIO); +#endif + goto out; + } +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32)) + if (unlikely(bio_barrier(bio))) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)) + if (unlikely(bio_rw_flagged(bio, BIO_RW_BARRIER))) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) + if (unlikely(bio->bi_rw & REQ_HARDBARRIER)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#else + //xx + if (unlikely(bio->bi_rw & REQ_FUA)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#endif + + if (unlikely(dev->readonly && bio_data_dir(bio) == WRITE)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EROFS); +#else + bio_endio(bio, bio->bi_size, -EROFS); +#endif + goto out; + } + +#ifdef SSD_QUEUE_PBIO + if (0 == atomic_read(&dev->in_sendq)) { + ret = __ssd_submit_pbio(dev, bio, 0); + } + + if (ret) { + (void)test_and_set_bit(BIO_SSD_PBIO, &bio->bi_flags); + ssd_queue_bio(dev, bio); + } +#else + __ssd_submit_pbio(dev, bio, 1); +#endif + +out: + return; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)) +static int ssd_make_request(struct request_queue *q, struct bio *bio) +#else +static void ssd_make_request(struct request_queue *q, struct bio *bio) +#endif +{ + struct ssd_device *dev = q->queuedata; + int ret = -EBUSY; + + if (!test_bit(SSD_ONLINE, &dev->state)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -ENODEV); +#else + bio_endio(bio, bio->bi_size, -ENODEV); +#endif + goto out; + } + +#ifdef SSD_DEBUG_ERR + if (atomic_read(&dev->tocnt)) { + hio_warn("%s: IO rejected because of IO timeout!\n", dev->name); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EIO); +#else + bio_endio(bio, bio->bi_size, -EIO); +#endif + goto out; + } +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32)) + if (unlikely(bio_barrier(bio))) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)) + if (unlikely(bio_rw_flagged(bio, BIO_RW_BARRIER))) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) + if (unlikely(bio->bi_rw & REQ_HARDBARRIER)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#else + //xx + if (unlikely(bio->bi_rw & REQ_FUA)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } + + /* writeback_cache_control.txt: REQ_FLUSH requests without data can be completed successfully without doing any work */ + if (unlikely((bio->bi_rw & REQ_FLUSH) && !bio_sectors(bio))) { + bio_endio(bio, 0); + goto out; + } + +#endif + + if (0 == atomic_read(&dev->in_sendq)) { + ret = ssd_submit_bio(dev, bio, 0); + } + + if (ret) { + ssd_queue_bio(dev, bio); + } + +out: +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)) + return 0; +#else + return; +#endif +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)) +static int ssd_block_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct ssd_device *dev; + + if (!bdev) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } + + geo->heads = 4; + geo->sectors = 16; + geo->cylinders = (dev->hw_info.size & ~0x3f) >> 6; + return 0; +} +#endif + +static void ssd_cleanup_blkdev(struct ssd_device *dev); +static int ssd_init_blkdev(struct ssd_device *dev); +static int ssd_ioctl_common(struct ssd_device *dev, unsigned int cmd, unsigned long arg) +{ + void __user *argp = (void __user *)arg; + void __user *buf = NULL; + void *kbuf = NULL; + int ret = 0; + + switch (cmd) { + case SSD_CMD_GET_PROTOCOL_INFO: + if (copy_to_user(argp, &dev->protocol_info, sizeof(struct ssd_protocol_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_GET_HW_INFO: + if (copy_to_user(argp, &dev->hw_info, sizeof(struct ssd_hw_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_GET_ROM_INFO: + if (copy_to_user(argp, &dev->rom_info, sizeof(struct ssd_rom_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_GET_SMART: { + struct ssd_smart smart; + int i; + + memcpy(&smart, &dev->smart, sizeof(struct ssd_smart)); + + mutex_lock(&dev->gd_mutex); + ssd_update_smart(dev, &smart); + mutex_unlock(&dev->gd_mutex); + + /* combine the volatile log info */ + if (dev->log_info.nr_log) { + for (i=0; ilog_info.stat[i]; + } + } + + if (copy_to_user(argp, &smart, sizeof(struct ssd_smart))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_GET_IDX: + if (copy_to_user(argp, &dev->idx, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_GET_AMOUNT: { + int nr_ssd = atomic_read(&ssd_nr); + if (copy_to_user(argp, &nr_ssd, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_TO_INFO: { + int tocnt = atomic_read(&dev->tocnt); + + if (copy_to_user(argp, &tocnt, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_DRV_VER: { + char ver[] = DRIVER_VERSION; + int len = sizeof(ver); + + if (len > (DRIVER_VERSION_LEN - 1)) { + len = (DRIVER_VERSION_LEN - 1); + } + if (copy_to_user(argp, ver, len)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_BBACC_INFO: { + struct ssd_acc_info acc; + + mutex_lock(&dev->fw_mutex); + ret = ssd_bb_acc(dev, &acc); + mutex_unlock(&dev->fw_mutex); + if (ret) { + break; + } + + if (copy_to_user(argp, &acc, sizeof(struct ssd_acc_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_ECACC_INFO: { + struct ssd_acc_info acc; + + mutex_lock(&dev->fw_mutex); + ret = ssd_ec_acc(dev, &acc); + mutex_unlock(&dev->fw_mutex); + if (ret) { + break; + } + + if (copy_to_user(argp, &acc, sizeof(struct ssd_acc_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_HW_INFO_EXT: + if (copy_to_user(argp, &dev->hw_info_ext, sizeof(struct ssd_hw_info_extend))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_REG_READ: { + struct ssd_reg_op_info reg_info; + + if (copy_from_user(®_info, argp, sizeof(struct ssd_reg_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + if (reg_info.offset > dev->mmio_len-sizeof(uint32_t)) { + ret = -EINVAL; + break; + } + + reg_info.value = ssd_reg32_read(dev->ctrlp + reg_info.offset); + if (copy_to_user(argp, ®_info, sizeof(struct ssd_reg_op_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_REG_WRITE: { + struct ssd_reg_op_info reg_info; + + if (copy_from_user(®_info, argp, sizeof(struct ssd_reg_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + if (reg_info.offset > dev->mmio_len-sizeof(uint32_t)) { + ret = -EINVAL; + break; + } + + ssd_reg32_write(dev->ctrlp + reg_info.offset, reg_info.value); + + break; + } + + case SSD_CMD_SPI_READ: { + struct ssd_spi_op_info spi_info; + uint32_t off, size; + + if (copy_from_user(&spi_info, argp, sizeof(struct ssd_spi_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + off = spi_info.off; + size = spi_info.len; + buf = spi_info.buf; + + if (size > dev->rom_info.size || 0 == size || (off + size) > dev->rom_info.size) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(size, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + ret = ssd_spi_page_read(dev, kbuf, off, size); + if (ret) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, size)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_SPI_WRITE: { + struct ssd_spi_op_info spi_info; + uint32_t off, size; + + if (copy_from_user(&spi_info, argp, sizeof(struct ssd_spi_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + off = spi_info.off; + size = spi_info.len; + buf = spi_info.buf; + + if (size > dev->rom_info.size || 0 == size || (off + size) > dev->rom_info.size) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(size, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + if (copy_from_user(kbuf, buf, size)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + ret = ssd_spi_page_write(dev, kbuf, off, size); + if (ret) { + kfree(kbuf); + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_SPI_ERASE: { + struct ssd_spi_op_info spi_info; + uint32_t off; + + if (copy_from_user(&spi_info, argp, sizeof(struct ssd_spi_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + off = spi_info.off; + + if ((off + dev->rom_info.block_size) > dev->rom_info.size) { + ret = -EINVAL; + break; + } + + ret = ssd_spi_block_erase(dev, off); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_I2C_READ: { + struct ssd_i2c_op_info i2c_info; + uint8_t saddr; + uint8_t rsize; + + if (copy_from_user(&i2c_info, argp, sizeof(struct ssd_i2c_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = i2c_info.saddr; + rsize = i2c_info.rsize; + buf = i2c_info.rbuf; + + if (rsize <= 0 || rsize > SSD_I2C_MAX_DATA) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(rsize, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + ret = ssd_i2c_read(dev, saddr, rsize, kbuf); + if (ret) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, rsize)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_I2C_WRITE: { + struct ssd_i2c_op_info i2c_info; + uint8_t saddr; + uint8_t wsize; + + if (copy_from_user(&i2c_info, argp, sizeof(struct ssd_i2c_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = i2c_info.saddr; + wsize = i2c_info.wsize; + buf = i2c_info.wbuf; + + if (wsize <= 0 || wsize > SSD_I2C_MAX_DATA) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(wsize, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + if (copy_from_user(kbuf, buf, wsize)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + ret = ssd_i2c_write(dev, saddr, wsize, kbuf); + if (ret) { + kfree(kbuf); + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_I2C_WRITE_READ: { + struct ssd_i2c_op_info i2c_info; + uint8_t saddr; + uint8_t wsize; + uint8_t rsize; + uint8_t size; + + if (copy_from_user(&i2c_info, argp, sizeof(struct ssd_i2c_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = i2c_info.saddr; + wsize = i2c_info.wsize; + rsize = i2c_info.rsize; + buf = i2c_info.wbuf; + + if (wsize <= 0 || wsize > SSD_I2C_MAX_DATA) { + ret = -EINVAL; + break; + } + + if (rsize <= 0 || rsize > SSD_I2C_MAX_DATA) { + ret = -EINVAL; + break; + } + + size = wsize + rsize; + + kbuf = kmalloc(size, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + if (copy_from_user((kbuf + rsize), buf, wsize)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + buf = i2c_info.rbuf; + + ret = ssd_i2c_write_read(dev, saddr, wsize, (kbuf + rsize), rsize, kbuf); + if (ret) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, rsize)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_SMBUS_SEND_BYTE: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + buf = smbus_info.buf; + size = 1; + + if (copy_from_user(smb_data, buf, size)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = ssd_smbus_send_byte(dev, saddr, smb_data); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_SMBUS_RECEIVE_BYTE: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + buf = smbus_info.buf; + size = 1; + + ret = ssd_smbus_receive_byte(dev, saddr, smb_data); + if (ret) { + break; + } + + if (copy_to_user(buf, smb_data, size)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_SMBUS_WRITE_BYTE: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = 1; + + if (copy_from_user(smb_data, buf, size)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = ssd_smbus_write_byte(dev, saddr, command, smb_data); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_SMBUS_READ_BYTE: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = 1; + + ret = ssd_smbus_read_byte(dev, saddr, command, smb_data); + if (ret) { + break; + } + + if (copy_to_user(buf, smb_data, size)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_SMBUS_WRITE_WORD: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = 2; + + if (copy_from_user(smb_data, buf, size)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = ssd_smbus_write_word(dev, saddr, command, smb_data); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_SMBUS_READ_WORD: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = 2; + + ret = ssd_smbus_read_word(dev, saddr, command, smb_data); + if (ret) { + break; + } + + if (copy_to_user(buf, smb_data, size)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_SMBUS_WRITE_BLOCK: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = smbus_info.size; + + if (size > SSD_SMBUS_BLOCK_MAX) { + ret = -EINVAL; + break; + } + + if (copy_from_user(smb_data, buf, size)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = ssd_smbus_write_block(dev, saddr, command, size, smb_data); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_SMBUS_READ_BLOCK: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = smbus_info.size; + + if (size > SSD_SMBUS_BLOCK_MAX) { + ret = -EINVAL; + break; + } + + ret = ssd_smbus_read_block(dev, saddr, command, size, smb_data); + if (ret) { + break; + } + + if (copy_to_user(buf, smb_data, size)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_BM_GET_VER: { + uint16_t ver; + + ret = ssd_bm_get_version(dev, &ver); + if (ret) { + break; + } + + if (copy_to_user(argp, &ver, sizeof(uint16_t))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_BM_GET_NR_CAP: { + int nr_cap; + + ret = ssd_bm_nr_cap(dev, &nr_cap); + if (ret) { + break; + } + + if (copy_to_user(argp, &nr_cap, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_BM_CAP_LEARNING: { + ret = ssd_bm_enter_cap_learning(dev); + + if (ret) { + break; + } + + break; + } + + case SSD_CMD_CAP_LEARN: { + uint32_t cap = 0; + + ret = ssd_cap_learn(dev, &cap); + if (ret) { + break; + } + + if (copy_to_user(argp, &cap, sizeof(uint32_t))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_GET_CAP_STATUS: { + int cap_status = 0; + + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + cap_status = 1; + } + + if (copy_to_user(argp, &cap_status, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_RAM_READ: { + struct ssd_ram_op_info ram_info; + uint64_t ofs; + uint32_t length; + size_t rlen, len = dev->hw_info.ram_max_len; + int ctrl_idx; + + if (copy_from_user(&ram_info, argp, sizeof(struct ssd_ram_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ofs = ram_info.start; + length = ram_info.length; + buf = ram_info.buf; + ctrl_idx = ram_info.ctrl_idx; + + if (ofs >= dev->hw_info.ram_size || length > dev->hw_info.ram_size || 0 == length || (ofs + length) > dev->hw_info.ram_size) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(len, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + for (rlen=0; rlenhw_info.ram_max_len; + int ctrl_idx; + + if (copy_from_user(&ram_info, argp, sizeof(struct ssd_ram_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + ofs = ram_info.start; + length = ram_info.length; + buf = ram_info.buf; + ctrl_idx = ram_info.ctrl_idx; + + if (ofs >= dev->hw_info.ram_size || length > dev->hw_info.ram_size || 0 == length || (ofs + length) > dev->hw_info.ram_size) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(len, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + for (wlen=0; wlenname); + ret = -EFAULT; + break; + } + + chip_no = flash_info.flash; + chip_ce = flash_info.chip; + ctrl_idx = flash_info.ctrl_idx; + buf = flash_info.buf; + length = dev->hw_info.id_size; + + //kbuf = kmalloc(length, GFP_KERNEL); + kbuf = kmalloc(SSD_NAND_ID_BUFF_SZ, GFP_KERNEL); //xx + if (!kbuf) { + ret = -ENOMEM; + break; + } + memset(kbuf, 0, length); + + ret = ssd_nand_read_id(dev, kbuf, chip_no, chip_ce, ctrl_idx); + if (ret) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, length)) { + kfree(kbuf); + ret = -EFAULT; + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_NAND_READ: { //with oob + struct ssd_flash_op_info flash_info; + uint32_t length; + int flash, chip, page, ctrl_idx; + int err = 0; + + if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + flash = flash_info.flash; + chip = flash_info.chip; + page = flash_info.page; + buf = flash_info.buf; + ctrl_idx = flash_info.ctrl_idx; + + length = dev->hw_info.page_size + dev->hw_info.oob_size; + + kbuf = kmalloc(length, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + err = ret = ssd_nand_read_w_oob(dev, kbuf, flash, chip, page, 1, ctrl_idx); + if (ret && (-EIO != ret)) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, length)) { + kfree(kbuf); + ret = -EFAULT; + break; + } + + ret = err; + + kfree(kbuf); + break; + } + + case SSD_CMD_NAND_WRITE: { + struct ssd_flash_op_info flash_info; + int flash, chip, page, ctrl_idx; + uint32_t length; + + if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + flash = flash_info.flash; + chip = flash_info.chip; + page = flash_info.page; + buf = flash_info.buf; + ctrl_idx = flash_info.ctrl_idx; + + length = dev->hw_info.page_size + dev->hw_info.oob_size; + + kbuf = kmalloc(length, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + if (copy_from_user(kbuf, buf, length)) { + kfree(kbuf); + ret = -EFAULT; + break; + } + + ret = ssd_nand_write(dev, kbuf, flash, chip, page, 1, ctrl_idx); + if (ret) { + kfree(kbuf); + break; + } + + kfree(kbuf); + break; + } + + case SSD_CMD_NAND_ERASE: { + struct ssd_flash_op_info flash_info; + int flash, chip, page, ctrl_idx; + + if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + flash = flash_info.flash; + chip = flash_info.chip; + page = flash_info.page; + ctrl_idx = flash_info.ctrl_idx; + + if ((page % dev->hw_info.page_count) != 0) { + ret = -EINVAL; + break; + } + + //hio_warn("erase fs = %llx\n", ofs); + ret = ssd_nand_erase(dev, flash, chip, page, ctrl_idx); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_NAND_READ_EXT: { //ingore EIO + struct ssd_flash_op_info flash_info; + uint32_t length; + int flash, chip, page, ctrl_idx; + + if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + flash = flash_info.flash; + chip = flash_info.chip; + page = flash_info.page; + buf = flash_info.buf; + ctrl_idx = flash_info.ctrl_idx; + + length = dev->hw_info.page_size + dev->hw_info.oob_size; + + kbuf = kmalloc(length, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + ret = ssd_nand_read_w_oob(dev, kbuf, flash, chip, page, 1, ctrl_idx); + if (-EIO == ret) { //ingore EIO + ret = 0; + } + if (ret) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, length)) { + kfree(kbuf); + ret = -EFAULT; + break; + } + + kfree(kbuf); + break; + } + + case SSD_CMD_UPDATE_BBT: { + struct ssd_flash_op_info flash_info; + int ctrl_idx, flash; + + if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ctrl_idx = flash_info.ctrl_idx; + flash = flash_info.flash; + ret = ssd_update_bbt(dev, flash, ctrl_idx); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_CLEAR_ALARM: + ssd_clear_alarm(dev); + break; + + case SSD_CMD_SET_ALARM: + ssd_set_alarm(dev); + break; + + case SSD_CMD_RESET: + ret = ssd_do_reset(dev); + break; + + case SSD_CMD_RELOAD_FW: + dev->reload_fw = 1; + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FLAG); + } else if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_1_1) { + ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FW); + + } + break; + + case SSD_CMD_UNLOAD_DEV: { + if (atomic_read(&dev->refcnt)) { + ret = -EBUSY; + break; + } + + /* save smart */ + ssd_save_smart(dev); + + ret = ssd_flush(dev); + if (ret) { + break; + } + + /* cleanup the block device */ + if (test_and_clear_bit(SSD_INIT_BD, &dev->state)) { + mutex_lock(&dev->gd_mutex); + ssd_cleanup_blkdev(dev); + mutex_unlock(&dev->gd_mutex); + } + + break; + } + + case SSD_CMD_LOAD_DEV: { + + if (test_bit(SSD_INIT_BD, &dev->state)) { + ret = -EINVAL; + break; + } + + ret = ssd_init_smart(dev); + if (ret) { + hio_warn("%s: init info: failed\n", dev->name); + break; + } + + ret = ssd_init_blkdev(dev); + if (ret) { + hio_warn("%s: register block device: failed\n", dev->name); + break; + } + (void)test_and_set_bit(SSD_INIT_BD, &dev->state); + + break; + } + + case SSD_CMD_UPDATE_VP: { + uint32_t val; + uint32_t new_vp, new_vp1 = 0; + + if (test_bit(SSD_INIT_BD, &dev->state)) { + ret = -EINVAL; + break; + } + + if (copy_from_user(&new_vp, argp, sizeof(uint32_t))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + if (new_vp > dev->hw_info.max_valid_pages || new_vp <= 0) { + ret = -EINVAL; + break; + } + + while (new_vp <= dev->hw_info.max_valid_pages) { + ssd_reg32_write(dev->ctrlp + SSD_VALID_PAGES_REG, new_vp); + msleep(10); + val = ssd_reg32_read(dev->ctrlp + SSD_VALID_PAGES_REG); + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + new_vp1 = val & 0x3FF; + } else { + new_vp1 = val & 0x7FFF; + } + + if (new_vp1 == new_vp) { + break; + } + + new_vp++; + /*if (new_vp == dev->hw_info.valid_pages) { + new_vp++; + }*/ + } + + if (new_vp1 != new_vp || new_vp > dev->hw_info.max_valid_pages) { + /* restore */ + ssd_reg32_write(dev->ctrlp + SSD_VALID_PAGES_REG, dev->hw_info.valid_pages); + ret = -EINVAL; + break; + } + + if (copy_to_user(argp, &new_vp, sizeof(uint32_t))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ssd_reg32_write(dev->ctrlp + SSD_VALID_PAGES_REG, dev->hw_info.valid_pages); + ret = -EFAULT; + break; + } + + /* new */ + dev->hw_info.valid_pages = new_vp; + dev->hw_info.size = (uint64_t)dev->hw_info.valid_pages * dev->hw_info.page_size; + dev->hw_info.size *= (dev->hw_info.block_count - dev->hw_info.reserved_blks); + dev->hw_info.size *= ((uint64_t)dev->hw_info.nr_data_ch * (uint64_t)dev->hw_info.nr_chip * (uint64_t)dev->hw_info.nr_ctrl); + + break; + } + + case SSD_CMD_FULL_RESET: { + ret = ssd_full_reset(dev); + break; + } + + case SSD_CMD_GET_NR_LOG: { + if (copy_to_user(argp, &dev->internal_log.nr_log, sizeof(dev->internal_log.nr_log))) { + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_LOG: { + uint32_t length = dev->rom_info.log_sz; + + buf = argp; + + if (copy_to_user(buf, dev->internal_log.log, length)) { + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_LOG_LEVEL: { + int level = 0; + if (copy_from_user(&level, argp, sizeof(int))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + if (level >= SSD_LOG_NR_LEVEL || level < SSD_LOG_LEVEL_INFO) { + level = SSD_LOG_LEVEL_ERR; + } + + //just for showing log, no need to protect + log_level = level; + break; + } + + case SSD_CMD_OT_PROTECT: { + int protect = 0; + + if (copy_from_user(&protect, argp, sizeof(int))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ssd_set_ot_protect(dev, !!protect); + break; + } + + case SSD_CMD_GET_OT_STATUS: { + int status = ssd_get_ot_status(dev, &status); + + if (copy_to_user(argp, &status, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_CLEAR_LOG: { + ret = ssd_clear_log(dev); + break; + } + + case SSD_CMD_CLEAR_SMART: { + ret = ssd_clear_smart(dev); + break; + } + + case SSD_CMD_SW_LOG: { + struct ssd_sw_log_info sw_log; + + if (copy_from_user(&sw_log, argp, sizeof(struct ssd_sw_log_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = ssd_gen_swlog(dev, sw_log.event, sw_log.data); + break; + } + + case SSD_CMD_GET_LABEL: { + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + ret = -EINVAL; + break; + } + + if (copy_to_user(argp, &dev->label, sizeof(struct ssd_label))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_VERSION: { + struct ssd_version_info ver; + + mutex_lock(&dev->fw_mutex); + ret = __ssd_get_version(dev, &ver); + mutex_unlock(&dev->fw_mutex); + if (ret) { + break; + } + + if (copy_to_user(argp, &ver, sizeof(struct ssd_version_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_TEMPERATURE: { + int temp; + + mutex_lock(&dev->fw_mutex); + ret = __ssd_get_temperature(dev, &temp); + mutex_unlock(&dev->fw_mutex); + if (ret) { + break; + } + + if (copy_to_user(argp, &temp, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_BMSTATUS: { + int status; + + mutex_lock(&dev->fw_mutex); + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + status = SSD_BMSTATUS_WARNING; + } else { + status = SSD_BMSTATUS_OK; + } + } else if(dev->protocol_info.ver > SSD_PROTOCOL_V3) { + ret = __ssd_bm_status(dev, &status); + } else { + status = SSD_BMSTATUS_OK; + } + mutex_unlock(&dev->fw_mutex); + if (ret) { + break; + } + + if (copy_to_user(argp, &status, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_LABEL2: { + void *label; + int length; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + label = &dev->label; + length = sizeof(struct ssd_label); + } else { + label = &dev->labelv3; + length = sizeof(struct ssd_labelv3); + } + + if (copy_to_user(argp, label, length)) { + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_FLUSH: + ret = ssd_flush(dev); + if (ret) { + hio_warn("%s: ssd_flush: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_SAVE_MD: { + int save_md = 0; + + if (copy_from_user(&save_md, argp, sizeof(int))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + dev->save_md = !!save_md; + break; + } + + case SSD_CMD_SET_WMODE: { + int new_wmode = 0; + + if (copy_from_user(&new_wmode, argp, sizeof(int))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = __ssd_set_wmode(dev, new_wmode); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_GET_WMODE: { + if (copy_to_user(argp, &dev->wmode, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_GET_USER_WMODE: { + if (copy_to_user(argp, &dev->user_wmode, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_DEBUG: { + struct ssd_debug_info db_info; + + if (!finject) { + ret = -EOPNOTSUPP; + break; + } + + if (copy_from_user(&db_info, argp, sizeof(struct ssd_debug_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + if (db_info.type < SSD_DEBUG_NONE || db_info.type >= SSD_DEBUG_NR) { + ret = -EINVAL; + break; + } + + /* IO */ + if (db_info.type >= SSD_DEBUG_READ_ERR && db_info.type <= SSD_DEBUG_RW_ERR && + (db_info.data.loc.off + db_info.data.loc.len) > (dev->hw_info.size >> 9)) { + ret = -EINVAL; + break; + } + + memcpy(&dev->db_info, &db_info, sizeof(struct ssd_debug_info)); + +#ifdef SSD_OT_PROTECT + /* temperature */ + if (db_info.type == SSD_DEBUG_NONE) { + ssd_check_temperature(dev, SSD_OT_TEMP); + } else if (db_info.type == SSD_DEBUG_LOG) { + if (db_info.data.log.event == SSD_LOG_OVER_TEMP) { + dev->ot_delay = SSD_OT_DELAY; + } else if (db_info.data.log.event == SSD_LOG_NORMAL_TEMP) { + dev->ot_delay = 0; + } + } +#endif + + /* offline */ + if (db_info.type == SSD_DEBUG_OFFLINE) { + test_and_clear_bit(SSD_ONLINE, &dev->state); + } else if (db_info.type == SSD_DEBUG_NONE) { + (void)test_and_set_bit(SSD_ONLINE, &dev->state); + } + + /* log */ + if (db_info.type == SSD_DEBUG_LOG && dev->event_call && dev->gd) { + dev->event_call(dev->gd, db_info.data.log.event, 0); + } + + break; + } + + case SSD_CMD_DRV_PARAM_INFO: { + struct ssd_drv_param_info drv_param; + + memset(&drv_param, 0, sizeof(struct ssd_drv_param_info)); + + drv_param.mode = mode; + drv_param.status_mask = status_mask; + drv_param.int_mode = int_mode; + drv_param.threaded_irq = threaded_irq; + drv_param.log_level = log_level; + drv_param.wmode = wmode; + drv_param.ot_protect = ot_protect; + drv_param.finject = finject; + + if (copy_to_user(argp, &drv_param, sizeof(struct ssd_drv_param_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + default: + ret = -EINVAL; + break; + } + + return ret; +} + + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) +static int ssd_block_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct ssd_device *dev; + void __user *argp = (void __user *)arg; + int ret = 0; + + if (!inode) { + return -EINVAL; + } + dev = inode->i_bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } +#else +static int ssd_block_ioctl(struct block_device *bdev, fmode_t mode, + unsigned int cmd, unsigned long arg) +{ + struct ssd_device *dev; + void __user *argp = (void __user *)arg; + int ret = 0; + + if (!bdev) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } +#endif + + switch (cmd) { + case HDIO_GETGEO: { + struct hd_geometry geo; + geo.cylinders = (dev->hw_info.size & ~0x3f) >> 6; + geo.heads = 4; + geo.sectors = 16; +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) + geo.start = get_start_sect(inode->i_bdev); +#else + geo.start = get_start_sect(bdev); +#endif + if (copy_to_user(argp, &geo, sizeof(geo))) { + ret = -EFAULT; + break; + } + + break; + } + + case BLKFLSBUF: + ret = ssd_flush(dev); + if (ret) { + hio_warn("%s: ssd_flush: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + default: + if (!dev->slave) { + ret = ssd_ioctl_common(dev, cmd, arg); + } else { + ret = -EFAULT; + } + break; + } + + return ret; +} + + +static void ssd_free_dev(struct kref *kref) +{ + struct ssd_device *dev; + + if (!kref) { + return; + } + + dev = container_of(kref, struct ssd_device, kref); + + put_disk(dev->gd); + + ssd_put_index(dev->slave, dev->idx); + + kfree(dev); +} + +static void ssd_put(struct ssd_device *dev) +{ + kref_put(&dev->kref, ssd_free_dev); +} + +static int ssd_get(struct ssd_device *dev) +{ + kref_get(&dev->kref); + return 0; +} + +/* block device */ +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) +static int ssd_block_open(struct inode *inode, struct file *filp) +{ + struct ssd_device *dev; + + if (!inode) { + return -EINVAL; + } + + dev = inode->i_bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } +#else +static int ssd_block_open(struct block_device *bdev, fmode_t mode) +{ + struct ssd_device *dev; + + if (!bdev) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } +#endif + + /*if (!try_module_get(dev->owner)) + return -ENODEV; + */ + + ssd_get(dev); + + atomic_inc(&dev->refcnt); + + return 0; +} + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) +static int ssd_block_release(struct inode *inode, struct file *filp) +{ + struct ssd_device *dev; + + if (!inode) { + return -EINVAL; + } + + dev = inode->i_bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0)) +static int ssd_block_release(struct gendisk *disk, fmode_t mode) +{ + struct ssd_device *dev; + + if (!disk) { + return -EINVAL; + } + + dev = disk->private_data; + if (!dev) { + return -EINVAL; + } +#else +static void ssd_block_release(struct gendisk *disk, fmode_t mode) +{ + struct ssd_device *dev; + + if (!disk) { + return; + } + + dev = disk->private_data; + if (!dev) { + return; + } +#endif + + atomic_dec(&dev->refcnt); + + ssd_put(dev); + + //module_put(dev->owner); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0)) + return 0; +#endif +} + +static struct block_device_operations ssd_fops = { + .owner = THIS_MODULE, + .open = ssd_block_open, + .release = ssd_block_release, + .ioctl = ssd_block_ioctl, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)) + .getgeo = ssd_block_getgeo, +#endif +}; + +static void ssd_init_trim(ssd_device_t *dev) +{ +#if (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32))) + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return; + } + queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, dev->rq); + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33)) || (defined RHEL_MAJOR && RHEL_MAJOR >= 6)) + dev->rq->limits.discard_zeroes_data = 1; + dev->rq->limits.discard_alignment = 4096; + dev->rq->limits.discard_granularity = 4096; +#endif + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2_4) { + dev->rq->limits.max_discard_sectors = dev->hw_info.sg_max_sec; + } else { + dev->rq->limits.max_discard_sectors = (dev->hw_info.sg_max_sec) * (dev->hw_info.cmd_max_sg); + } +#endif +} + +static void ssd_cleanup_queue(struct ssd_device *dev) +{ + ssd_wait_io(dev); + + blk_cleanup_queue(dev->rq); + dev->rq = NULL; +} + +static int ssd_init_queue(struct ssd_device *dev) +{ + dev->rq = blk_alloc_queue(GFP_KERNEL); + if (dev->rq == NULL) { + hio_warn("%s: alloc queue: failed\n ", dev->name); + goto out_init_queue; + } + + /* must be first */ + blk_queue_make_request(dev->rq, ssd_make_request); + +#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)) && !(defined RHEL_MAJOR && RHEL_MAJOR == 6)) + blk_queue_max_hw_segments(dev->rq, dev->hw_info.cmd_max_sg); + blk_queue_max_phys_segments(dev->rq, dev->hw_info.cmd_max_sg); + blk_queue_max_sectors(dev->rq, dev->hw_info.sg_max_sec); +#else + blk_queue_max_segments(dev->rq, dev->hw_info.cmd_max_sg); + blk_queue_max_hw_sectors(dev->rq, dev->hw_info.sg_max_sec); +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)) + blk_queue_hardsect_size(dev->rq, 512); +#else + blk_queue_logical_block_size(dev->rq, 512); +#endif + /* not work for make_request based drivers(bio) */ + blk_queue_max_segment_size(dev->rq, dev->hw_info.sg_max_sec << 9); + + blk_queue_bounce_limit(dev->rq, BLK_BOUNCE_HIGH); + + dev->rq->queuedata = dev; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) + blk_queue_issue_flush_fn(dev->rq, ssd_issue_flush_fn); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)) + queue_flag_set_unlocked(QUEUE_FLAG_NONROT, dev->rq); +#endif + + ssd_init_trim(dev); + + return 0; + +out_init_queue: + return -ENOMEM; +} + +static void ssd_cleanup_blkdev(struct ssd_device *dev) +{ + del_gendisk(dev->gd); +} + +static int ssd_init_blkdev(struct ssd_device *dev) +{ + if (dev->gd) { + put_disk(dev->gd); + } + + dev->gd = alloc_disk(ssd_minors); + if (!dev->gd) { + hio_warn("%s: alloc_disk fail\n", dev->name); + goto out_alloc_gd; + } + dev->gd->major = dev->major; + dev->gd->first_minor = dev->idx * ssd_minors; + dev->gd->fops = &ssd_fops; + dev->gd->queue = dev->rq; + dev->gd->private_data = dev; + dev->gd->driverfs_dev = &dev->pdev->dev; + snprintf (dev->gd->disk_name, sizeof(dev->gd->disk_name), "%s", dev->name); + + set_capacity(dev->gd, dev->hw_info.size >> 9); + + add_disk(dev->gd); + + return 0; + +out_alloc_gd: + return -ENOMEM; +} + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,10)) +static int ssd_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +#else +static long ssd_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +#endif +{ + struct ssd_device *dev; + + if (!file) { + return -EINVAL; + } + + dev = file->private_data; + if (!dev) { + return -EINVAL; + } + + return (long)ssd_ioctl_common(dev, cmd, arg); +} + +static int ssd_open(struct inode *inode, struct file *file) +{ + struct ssd_device *dev = NULL; + struct ssd_device *n = NULL; + int idx; + int ret = -ENODEV; + + if (!inode || !file) { + return -EINVAL; + } + + idx = iminor(inode); + + list_for_each_entry_safe(dev, n, &ssd_list, list) { + if (dev->idx == idx) { + ret = 0; + break; + } + } + + if (ret) { + return ret; + } + + file->private_data = dev; + + ssd_get(dev); + + return 0; +} + +static int ssd_release(struct inode *inode, struct file *file) +{ + struct ssd_device *dev; + + if (!file) { + return -EINVAL; + } + + dev = file->private_data; + if (!dev) { + return -EINVAL; + } + + ssd_put(dev); + + file->private_data = NULL; + + return 0; +} + +static struct file_operations ssd_cfops = { + .owner = THIS_MODULE, + .open = ssd_open, + .release = ssd_release, +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,10)) + .ioctl = ssd_ioctl, +#else + .unlocked_ioctl = ssd_ioctl, +#endif +}; + +static void ssd_cleanup_chardev(struct ssd_device *dev) +{ + if (dev->slave) { + return; + } + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) + class_simple_device_remove(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx)); + devfs_remove("c%s", dev->name); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,14)) + class_device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx)); + devfs_remove("c%s", dev->name); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)) + class_device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx)); + devfs_remove("c%s", dev->name); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)) + class_device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx)); +#else + device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx)); +#endif +} + +static int ssd_init_chardev(struct ssd_device *dev) +{ + int ret = 0; + + if (dev->slave) { + return 0; + } + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) + ret = devfs_mk_cdev(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), S_IFCHR|S_IRUSR|S_IWUSR, "c%s", dev->name); + if (ret) { + goto out; + } + class_simple_device_add(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +out: +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,14)) + ret = devfs_mk_cdev(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), S_IFCHR|S_IRUSR|S_IWUSR, "c%s", dev->name); + if (ret) { + goto out; + } + class_device_create(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +out: +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)) + ret = devfs_mk_cdev(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), S_IFCHR|S_IRUSR|S_IWUSR, "c%s", dev->name); + if (ret) { + goto out; + } + class_device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +out: +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)) + class_device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), "c%s", dev->name); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) + device_create_drvdata(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +#else + device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +#endif + + return ret; +} + +static int ssd_check_hw(struct ssd_device *dev) +{ + uint32_t test_data = 0x55AA5AA5; + uint32_t read_data; + + ssd_reg32_write(dev->ctrlp + SSD_BRIDGE_TEST_REG, test_data); + read_data = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_TEST_REG); + if (read_data != ~(test_data)) { + //hio_warn("%s: check bridge error: %#x\n", dev->name, read_data); + return -1; + } + + return 0; +} + +static int ssd_check_fw(struct ssd_device *dev) +{ + uint32_t val = 0; + int i; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) { + return 0; + } + + for (i=0; ictrlp + SSD_HW_STATUS_REG); + if ((val & 0x1) && ((val >> 8) & 0x1)) { + break; + } + + msleep(SSD_INIT_WAIT); + } + + if (!(val & 0x1)) { + /* controller fw status */ + hio_warn("%s: controller firmware load failed: %#x\n", dev->name, val); + return -1; + } else if (!((val >> 8) & 0x1)) { + /* controller state */ + hio_warn("%s: controller state error: %#x\n", dev->name, val); + return -1; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_RELOAD_FW_REG); + if (val) { + dev->reload_fw = 1; + } + + return 0; +} + +static int ssd_init_fw_info(struct ssd_device *dev) +{ + uint32_t val; + int ret = 0; + + val = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_VER_REG); + dev->hw_info.bridge_ver = val & 0xFFF; + if (dev->hw_info.bridge_ver < SSD_FW_MIN) { + hio_warn("%s: bridge firmware version %03X is not supported\n", dev->name, dev->hw_info.bridge_ver); + return -EINVAL; + } + hio_info("%s: bridge firmware version: %03X\n", dev->name, dev->hw_info.bridge_ver); + + ret = ssd_check_fw(dev); + if (ret) { + goto out; + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +static int ssd_check_clock(struct ssd_device *dev) +{ + uint32_t val; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) { + return 0; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_HW_STATUS_REG); + + /* clock status */ + if (!((val >> 4 ) & 0x1)) { + if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_166M_LOST), &dev->hwmon)) { + hio_warn("%s: 166MHz clock losed: %#x\n", dev->name, val); + ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val); + } + ret = -1; + } + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (!((val >> 5 ) & 0x1)) { + if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_166M_SKEW), &dev->hwmon)) { + hio_warn("%s: 166MHz clock is skew: %#x\n", dev->name, val); + ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val); + } + ret = -1; + } + if (!((val >> 6 ) & 0x1)) { + if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_156M_LOST), &dev->hwmon)) { + hio_warn("%s: 156.25MHz clock lost: %#x\n", dev->name, val); + ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val); + } + ret = -1; + } + if (!((val >> 7 ) & 0x1)) { + if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_156M_SKEW), &dev->hwmon)) { + hio_warn("%s: 156.25MHz clock is skew: %#x\n", dev->name, val); + ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val); + } + ret = -1; + } + } + + return ret; +} + +static int ssd_check_volt(struct ssd_device *dev) +{ + int i = 0; + uint64_t val; + uint32_t adc_val; + int ret =0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + for (i=0; ihw_info.nr_ctrl; i++) { + /* 1.0v */ + if (!test_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V0), &dev->hwmon)) { + val = ssd_reg_read(dev->ctrlp + SSD_FPGA_1V0_REG0 + i * SSD_CTRL_REG_ZONE_SZ); + adc_val = SSD_FPGA_VOLT_MAX(val); + if (adc_val < SSD_FPGA_1V0_ADC_MIN || adc_val > SSD_FPGA_1V0_ADC_MAX) { + (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V0), &dev->hwmon); + hio_warn("%s: controller %d 1.0V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val)); + ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V0, i, adc_val)); + ret = -1; + } + + adc_val = SSD_FPGA_VOLT_MIN(val); + if (adc_val < SSD_FPGA_1V0_ADC_MIN || adc_val > SSD_FPGA_1V0_ADC_MAX) { + (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V0), &dev->hwmon); + hio_warn("%s: controller %d 1.0V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val)); + ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V0, i, adc_val)); + ret = -2; + } + } + + /* 1.8v */ + if (!test_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V8), &dev->hwmon)) { + val = ssd_reg_read(dev->ctrlp + SSD_FPGA_1V8_REG0 + i * SSD_CTRL_REG_ZONE_SZ); + adc_val = SSD_FPGA_VOLT_MAX(val); + if (adc_val < SSD_FPGA_1V8_ADC_MIN || adc_val > SSD_FPGA_1V8_ADC_MAX) { + (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V8), &dev->hwmon); + hio_warn("%s: controller %d 1.8V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val)); + ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V8, i, adc_val)); + ret = -3; + } + + adc_val = SSD_FPGA_VOLT_MIN(val); + if (adc_val < SSD_FPGA_1V8_ADC_MIN || adc_val > SSD_FPGA_1V8_ADC_MAX) { + (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V8), &dev->hwmon); + hio_warn("%s: controller %d 1.8V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val)); + ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V8, i, adc_val)); + ret = -4; + } + } + } + + return ret; +} + +static int ssd_check_reset_sync(struct ssd_device *dev) +{ + uint32_t val; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) { + return 0; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_HW_STATUS_REG); + if (!((val >> 8) & 0x1)) { + /* controller state */ + hio_warn("%s: controller state error: %#x\n", dev->name, val); + return -1; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + if (((val >> 9 ) & 0x1)) { + hio_warn("%s: controller reset asynchronously: %#x\n", dev->name, val); + ssd_gen_swlog(dev, SSD_LOG_CTRL_RST_SYNC, val); + return -1; + } + + return 0; +} + +static int ssd_check_hw_bh(struct ssd_device *dev) +{ + int ret; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) { + return 0; + } + + /* clock status */ + ret = ssd_check_clock(dev); + if (ret) { + goto out; + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +static int ssd_check_controller(struct ssd_device *dev) +{ + int ret; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) { + return 0; + } + + /* sync reset */ + ret = ssd_check_reset_sync(dev); + if (ret) { + goto out; + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +static int ssd_check_controller_bh(struct ssd_device *dev) +{ + uint32_t test_data = 0x55AA5AA5; + uint32_t val; + int reg_base, reg_sz; + int init_wait = 0; + int i; + int ret = 0; + + if (mode != SSD_DRV_MODE_STANDARD) { + return 0; + } + + /* controller */ + val = ssd_reg32_read(dev->ctrlp + SSD_READY_REG); + if (val & 0x1) { + hio_warn("%s: controller 0 not ready\n", dev->name); + return -1; + } + + for (i=0; ihw_info.nr_ctrl; i++) { + reg_base = SSD_CTRL_TEST_REG0 + i * SSD_CTRL_TEST_REG_SZ; + ssd_reg32_write(dev->ctrlp + reg_base, test_data); + val = ssd_reg32_read(dev->ctrlp + reg_base); + if (val != ~(test_data)) { + hio_warn("%s: check controller %d error: %#x\n", dev->name, i, val); + return -1; + } + } + + /* clock */ + ret = ssd_check_volt(dev); + if (ret) { + return ret; + } + + /* ddr */ + if (dev->protocol_info.ver > SSD_PROTOCOL_V3) { + reg_base = SSD_PV3_RAM_STATUS_REG0; + reg_sz = SSD_PV3_RAM_STATUS_REG_SZ; + + for (i=0; ihw_info.nr_ctrl; i++) { +check_ram_status: + val = ssd_reg32_read(dev->ctrlp + reg_base); + + if (!((val >> 1) & 0x1)) { + init_wait++; + if (init_wait <= SSD_RAM_INIT_MAX_WAIT) { + msleep(SSD_INIT_WAIT); + goto check_ram_status; + } else { + hio_warn("%s: controller %d ram init failed: %#x\n", dev->name, i, val); + ssd_gen_swlog(dev, SSD_LOG_DDR_INIT_ERR, i); + return -1; + } + } + + reg_base += reg_sz; + } + } + + /* ch info */ + for (i=0; ictrlp + SSD_CH_INFO_REG); + if (!((val >> 31) & 0x1)) { + break; + } + + msleep(SSD_INIT_WAIT); + } + if ((val >> 31) & 0x1) { + hio_warn("%s: channel info init failed: %#x\n", dev->name, val); + return -1; + } + + return 0; +} + +static int ssd_init_protocol_info(struct ssd_device *dev) +{ + uint32_t val; + + val = ssd_reg32_read(dev->ctrlp + SSD_PROTOCOL_VER_REG); + if (val == (uint32_t)-1) { + hio_warn("%s: protocol version error: %#x\n", dev->name, val); + return -EINVAL; + } + dev->protocol_info.ver = val; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + dev->protocol_info.init_state_reg = SSD_INIT_STATE_REG0; + dev->protocol_info.init_state_reg_sz = SSD_INIT_STATE_REG_SZ; + + dev->protocol_info.chip_info_reg = SSD_CHIP_INFO_REG0; + dev->protocol_info.chip_info_reg_sz = SSD_CHIP_INFO_REG_SZ; + } else { + dev->protocol_info.init_state_reg = SSD_PV3_INIT_STATE_REG0; + dev->protocol_info.init_state_reg_sz = SSD_PV3_INIT_STATE_REG_SZ; + + dev->protocol_info.chip_info_reg = SSD_PV3_CHIP_INFO_REG0; + dev->protocol_info.chip_info_reg_sz = SSD_PV3_CHIP_INFO_REG_SZ; + } + + return 0; +} + +static int ssd_init_hw_info(struct ssd_device *dev) +{ + uint64_t val64; + uint32_t val; + uint32_t nr_ctrl; + int ret = 0; + + /* base info */ + val = ssd_reg32_read(dev->ctrlp + SSD_RESP_INFO_REG); + dev->hw_info.resp_ptr_sz = 16 * (1U << (val & 0xFF)); + dev->hw_info.resp_msg_sz = 16 * (1U << ((val >> 8) & 0xFF)); + + if (0 == dev->hw_info.resp_ptr_sz || 0 == dev->hw_info.resp_msg_sz) { + hio_warn("%s: response info error\n", dev->name); + ret = -EINVAL; + goto out; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_INFO_REG); + dev->hw_info.cmd_fifo_sz = 1U << ((val >> 4) & 0xF); + dev->hw_info.cmd_max_sg = 1U << ((val >> 8) & 0xF); + dev->hw_info.sg_max_sec = 1U << ((val >> 12) & 0xF); + dev->hw_info.cmd_fifo_sz_mask = dev->hw_info.cmd_fifo_sz - 1; + + if (0 == dev->hw_info.cmd_fifo_sz || 0 == dev->hw_info.cmd_max_sg || 0 == dev->hw_info.sg_max_sec) { + hio_warn("%s: cmd info error\n", dev->name); + ret = -EINVAL; + goto out; + } + + /* check hw */ + if (ssd_check_hw_bh(dev)) { + hio_warn("%s: check hardware status failed\n", dev->name); + ret = -EINVAL; + goto out; + } + + if (ssd_check_controller(dev)) { + hio_warn("%s: check controller state failed\n", dev->name); + ret = -EINVAL; + goto out; + } + + /* nr controller : read again*/ + val = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_INFO_REG); + dev->hw_info.nr_ctrl = (val >> 16) & 0xF; + + /* nr ctrl configured */ + nr_ctrl = (val >> 20) & 0xF; + if (0 == dev->hw_info.nr_ctrl) { + hio_warn("%s: nr controller error: %u\n", dev->name, dev->hw_info.nr_ctrl); + ret = -EINVAL; + goto out; + } else if (0 != nr_ctrl && nr_ctrl != dev->hw_info.nr_ctrl) { + hio_warn("%s: nr controller error: configured %u but found %u\n", dev->name, nr_ctrl, dev->hw_info.nr_ctrl); + if (mode <= SSD_DRV_MODE_STANDARD) { + ret = -EINVAL; + goto out; + } + } + + if (ssd_check_controller_bh(dev)) { + hio_warn("%s: check controller failed\n", dev->name); + ret = -EINVAL; + goto out; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_PCB_VER_REG); + dev->hw_info.pcb_ver = (uint8_t) ((val >> 4) & 0xF) + 'A' -1; + if ((val & 0xF) != 0xF) { + dev->hw_info.upper_pcb_ver = (uint8_t) (val & 0xF) + 'A' -1; + } + + if (dev->hw_info.pcb_ver < 'A' || (0 != dev->hw_info.upper_pcb_ver && dev->hw_info.upper_pcb_ver < 'A')) { + hio_warn("%s: PCB version error: %#x %#x\n", dev->name, dev->hw_info.pcb_ver, dev->hw_info.upper_pcb_ver); + ret = -EINVAL; + goto out; + } + + /* channel info */ + if (mode <= SSD_DRV_MODE_DEBUG) { + val = ssd_reg32_read(dev->ctrlp + SSD_CH_INFO_REG); + dev->hw_info.nr_data_ch = val & 0xFF; + dev->hw_info.nr_ch = dev->hw_info.nr_data_ch + ((val >> 8) & 0xFF); + dev->hw_info.nr_chip = (val >> 16) & 0xFF; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + dev->hw_info.max_ch = 1; + while (dev->hw_info.max_ch < dev->hw_info.nr_ch) dev->hw_info.max_ch <<= 1; + } else { + /* set max channel 32 */ + dev->hw_info.max_ch = 32; + } + + if (0 == dev->hw_info.nr_chip) { + //for debug mode + dev->hw_info.nr_chip = 1; + } + + //xx + dev->hw_info.id_size = SSD_NAND_ID_SZ; + dev->hw_info.max_ce = SSD_NAND_MAX_CE; + + if (0 == dev->hw_info.nr_data_ch || 0 == dev->hw_info.nr_ch || 0 == dev->hw_info.nr_chip) { + hio_warn("%s: channel info error: data_ch %u ch %u chip %u\n", dev->name, dev->hw_info.nr_data_ch, dev->hw_info.nr_ch, dev->hw_info.nr_chip); + ret = -EINVAL; + goto out; + } + } + + /* ram info */ + if (mode <= SSD_DRV_MODE_DEBUG) { + val = ssd_reg32_read(dev->ctrlp + SSD_RAM_INFO_REG); + dev->hw_info.ram_size = 0x4000000ull * (1ULL << (val & 0xF)); + dev->hw_info.ram_align = 1U << ((val >> 12) & 0xF); + if (dev->hw_info.ram_align < SSD_RAM_ALIGN) { + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + dev->hw_info.ram_align = SSD_RAM_ALIGN; + } else { + hio_warn("%s: ram align error: %u\n", dev->name, dev->hw_info.ram_align); + ret = -EINVAL; + goto out; + } + } + dev->hw_info.ram_max_len = 0x1000 * (1U << ((val >> 16) & 0xF)); + + if (0 == dev->hw_info.ram_size || 0 == dev->hw_info.ram_align || 0 == dev->hw_info.ram_max_len || dev->hw_info.ram_align > dev->hw_info.ram_max_len) { + hio_warn("%s: ram info error\n", dev->name); + ret = -EINVAL; + goto out; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + dev->hw_info.log_sz = SSD_LOG_MAX_SZ; + } else { + val = ssd_reg32_read(dev->ctrlp + SSD_LOG_INFO_REG); + dev->hw_info.log_sz = 0x1000 * (1U << (val & 0xFF)); + } + if (0 == dev->hw_info.log_sz) { + hio_warn("%s: log size error\n", dev->name); + ret = -EINVAL; + goto out; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_BBT_BASE_REG); + dev->hw_info.bbt_base = 0x40000ull * (val & 0xFFFF); + dev->hw_info.bbt_size = 0x40000 * (((val >> 16) & 0xFFFF) + 1) / (dev->hw_info.max_ch * dev->hw_info.nr_chip); + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + if (dev->hw_info.bbt_base > dev->hw_info.ram_size || 0 == dev->hw_info.bbt_size) { + hio_warn("%s: bbt info error\n", dev->name); + ret = -EINVAL; + goto out; + } + } + + val = ssd_reg32_read(dev->ctrlp + SSD_ECT_BASE_REG); + dev->hw_info.md_base = 0x40000ull * (val & 0xFFFF); + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + dev->hw_info.md_size = 0x40000 * (((val >> 16) & 0xFFF) + 1) / (dev->hw_info.max_ch * dev->hw_info.nr_chip); + } else { + dev->hw_info.md_size = 0x40000 * (((val >> 16) & 0xFFF) + 1) / (dev->hw_info.nr_chip); + } + dev->hw_info.md_entry_sz = 8 * (1U << ((val >> 28) & 0xF)); + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3) { + if (dev->hw_info.md_base > dev->hw_info.ram_size || 0 == dev->hw_info.md_size || + 0 == dev->hw_info.md_entry_sz || dev->hw_info.md_entry_sz > dev->hw_info.md_size) { + hio_warn("%s: md info error\n", dev->name); + ret = -EINVAL; + goto out; + } + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + dev->hw_info.nand_wbuff_base = dev->hw_info.ram_size + 1; + } else { + val = ssd_reg32_read(dev->ctrlp + SSD_NAND_BUFF_BASE); + dev->hw_info.nand_wbuff_base = 0x8000ull * val; + } + } + + /* flash info */ + if (mode <= SSD_DRV_MODE_DEBUG) { + if (dev->hw_info.nr_ctrl > 1) { + val = ssd_reg32_read(dev->ctrlp + SSD_CTRL_VER_REG); + dev->hw_info.ctrl_ver = val & 0xFFF; + hio_info("%s: controller firmware version: %03X\n", dev->name, dev->hw_info.ctrl_ver); + } + + val64 = ssd_reg_read(dev->ctrlp + SSD_FLASH_INFO_REG0); + dev->hw_info.nand_vendor_id = ((val64 >> 56) & 0xFF); + dev->hw_info.nand_dev_id = ((val64 >> 48) & 0xFF); + + dev->hw_info.block_count = (((val64 >> 32) & 0xFFFF) + 1); + dev->hw_info.page_count = ((val64>>16) & 0xFFFF); + dev->hw_info.page_size = (val64 & 0xFFFF); + + val = ssd_reg32_read(dev->ctrlp + SSD_BB_INFO_REG); + dev->hw_info.bbf_pages = val & 0xFF; + dev->hw_info.bbf_seek = (val >> 8) & 0x1; + + if (0 == dev->hw_info.block_count || 0 == dev->hw_info.page_count || 0 == dev->hw_info.page_size || dev->hw_info.block_count > INT_MAX) { + hio_warn("%s: flash info error\n", dev->name); + ret = -EINVAL; + goto out; + } + + //xx + dev->hw_info.oob_size = SSD_NAND_OOB_SZ; //(dev->hw_info.page_size) >> 5; + + val = ssd_reg32_read(dev->ctrlp + SSD_VALID_PAGES_REG); + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + dev->hw_info.valid_pages = val & 0x3FF; + dev->hw_info.max_valid_pages = (val>>20) & 0x3FF; + } else { + dev->hw_info.valid_pages = val & 0x7FFF; + dev->hw_info.max_valid_pages = (val>>15) & 0x7FFF; + } + if (0 == dev->hw_info.valid_pages || 0 == dev->hw_info.max_valid_pages || + dev->hw_info.valid_pages > dev->hw_info.max_valid_pages || dev->hw_info.max_valid_pages > dev->hw_info.page_count) { + hio_warn("%s: valid page info error: valid_pages %d, max_valid_pages %d\n", dev->name, dev->hw_info.valid_pages, dev->hw_info.max_valid_pages); + ret = -EINVAL; + goto out; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_RESERVED_BLKS_REG); + dev->hw_info.reserved_blks = val & 0xFFFF; + dev->hw_info.md_reserved_blks = (val >> 16) & 0xFF; + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + dev->hw_info.md_reserved_blks = SSD_BBT_RESERVED; + } + if (dev->hw_info.reserved_blks > dev->hw_info.block_count || dev->hw_info.md_reserved_blks > dev->hw_info.block_count) { + hio_warn("%s: reserved blocks info error: reserved_blks %d, md_reserved_blks %d\n", dev->name, dev->hw_info.reserved_blks, dev->hw_info.md_reserved_blks); + ret = -EINVAL; + goto out; + } + } + + /* size */ + if (mode < SSD_DRV_MODE_DEBUG) { + dev->hw_info.size = (uint64_t)dev->hw_info.valid_pages * dev->hw_info.page_size; + dev->hw_info.size *= (dev->hw_info.block_count - dev->hw_info.reserved_blks); + dev->hw_info.size *= ((uint64_t)dev->hw_info.nr_data_ch * (uint64_t)dev->hw_info.nr_chip * (uint64_t)dev->hw_info.nr_ctrl); + } + + /* extend hardware info */ + val = ssd_reg32_read(dev->ctrlp + SSD_PCB_VER_REG); + dev->hw_info_ext.board_type = (val >> 24) & 0xF; + + dev->hw_info_ext.form_factor = SSD_FORM_FACTOR_FHHL; + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2_1) { + dev->hw_info_ext.form_factor = (val >> 31) & 0x1; + } + /* + dev->hw_info_ext.cap_type = (val >> 28) & 0x3; + if (SSD_BM_CAP_VINA != dev->hw_info_ext.cap_type && SSD_BM_CAP_JH != dev->hw_info_ext.cap_type) { + dev->hw_info_ext.cap_type = SSD_BM_CAP_VINA; + }*/ + + /* power loss protect */ + val = ssd_reg32_read(dev->ctrlp + SSD_PLP_INFO_REG); + dev->hw_info_ext.plp_type = (val & 0x3); + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + /* 3 or 4 cap */ + dev->hw_info_ext.cap_type = ((val >> 2)& 0x1); + } + + /* work mode */ + val = ssd_reg32_read(dev->ctrlp + SSD_CH_INFO_REG); + dev->hw_info_ext.work_mode = (val >> 25) & 0x1; + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +static void ssd_cleanup_response(struct ssd_device *dev) +{ + int resp_msg_sz = dev->hw_info.resp_msg_sz * dev->hw_info.cmd_fifo_sz * SSD_MSIX_VEC; + int resp_ptr_sz = dev->hw_info.resp_ptr_sz * SSD_MSIX_VEC; + + pci_free_consistent(dev->pdev, resp_ptr_sz, dev->resp_ptr_base, dev->resp_ptr_base_dma); + pci_free_consistent(dev->pdev, resp_msg_sz, dev->resp_msg_base, dev->resp_msg_base_dma); +} + +static int ssd_init_response(struct ssd_device *dev) +{ + int resp_msg_sz = dev->hw_info.resp_msg_sz * dev->hw_info.cmd_fifo_sz * SSD_MSIX_VEC; + int resp_ptr_sz = dev->hw_info.resp_ptr_sz * SSD_MSIX_VEC; + + dev->resp_msg_base = pci_alloc_consistent(dev->pdev, resp_msg_sz, &(dev->resp_msg_base_dma)); + if (!dev->resp_msg_base) { + hio_warn("%s: unable to allocate resp msg DMA buffer\n", dev->name); + goto out_alloc_resp_msg; + } + memset(dev->resp_msg_base, 0xFF, resp_msg_sz); + + dev->resp_ptr_base = pci_alloc_consistent(dev->pdev, resp_ptr_sz, &(dev->resp_ptr_base_dma)); + if (!dev->resp_ptr_base){ + hio_warn("%s: unable to allocate resp ptr DMA buffer\n", dev->name); + goto out_alloc_resp_ptr; + } + memset(dev->resp_ptr_base, 0, resp_ptr_sz); + dev->resp_idx = *(uint32_t *)(dev->resp_ptr_base) = dev->hw_info.cmd_fifo_sz * 2 - 1; + + ssd_reg_write(dev->ctrlp + SSD_RESP_FIFO_REG, dev->resp_msg_base_dma); + ssd_reg_write(dev->ctrlp + SSD_RESP_PTR_REG, dev->resp_ptr_base_dma); + + return 0; + +out_alloc_resp_ptr: + pci_free_consistent(dev->pdev, resp_msg_sz, dev->resp_msg_base, dev->resp_msg_base_dma); +out_alloc_resp_msg: + return -ENOMEM; +} + +static int ssd_cleanup_cmd(struct ssd_device *dev) +{ + int msg_sz = ALIGN(sizeof(struct ssd_rw_msg) + (dev->hw_info.cmd_max_sg - 1) * sizeof(struct ssd_sg_entry), SSD_DMA_ALIGN); + int i; + + for (i=0; i<(int)dev->hw_info.cmd_fifo_sz; i++) { + kfree(dev->cmd[i].sgl); + } + kfree(dev->cmd); + pci_free_consistent(dev->pdev, (msg_sz * dev->hw_info.cmd_fifo_sz), dev->msg_base, dev->msg_base_dma); + return 0; +} + +static int ssd_init_cmd(struct ssd_device *dev) +{ + int sgl_sz = sizeof(struct scatterlist) * dev->hw_info.cmd_max_sg; + int cmd_sz = sizeof(struct ssd_cmd) * dev->hw_info.cmd_fifo_sz; + int msg_sz = ALIGN(sizeof(struct ssd_rw_msg) + (dev->hw_info.cmd_max_sg - 1) * sizeof(struct ssd_sg_entry), SSD_DMA_ALIGN); + int i; + + spin_lock_init(&dev->cmd_lock); + + dev->msg_base = pci_alloc_consistent(dev->pdev, (msg_sz * dev->hw_info.cmd_fifo_sz), &dev->msg_base_dma); + if (!dev->msg_base) { + hio_warn("%s: can not alloc cmd msg\n", dev->name); + goto out_alloc_msg; + } + + dev->cmd = kmalloc(cmd_sz, GFP_KERNEL); + if (!dev->cmd) { + hio_warn("%s: can not alloc cmd\n", dev->name); + goto out_alloc_cmd; + } + memset(dev->cmd, 0, cmd_sz); + + for (i=0; i<(int)dev->hw_info.cmd_fifo_sz; i++) { + dev->cmd[i].sgl = kmalloc(sgl_sz, GFP_KERNEL); + if (!dev->cmd[i].sgl) { + hio_warn("%s: can not alloc cmd sgl %d\n", dev->name, i); + goto out_alloc_sgl; + } + + dev->cmd[i].msg = dev->msg_base + (msg_sz * i); + dev->cmd[i].msg_dma = dev->msg_base_dma + ((dma_addr_t)msg_sz * i); + + dev->cmd[i].dev = dev; + dev->cmd[i].tag = i; + dev->cmd[i].flag = 0; + + INIT_LIST_HEAD(&dev->cmd[i].list); + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + dev->scmd = ssd_dispatch_cmd; + } else { + ssd_reg_write(dev->ctrlp + SSD_MSG_BASE_REG, dev->msg_base_dma); + if (finject) { + dev->scmd = ssd_send_cmd_db; + } else { + dev->scmd = ssd_send_cmd; + } + } + + return 0; + +out_alloc_sgl: + for (i--; i>=0; i--) { + kfree(dev->cmd[i].sgl); + } + kfree(dev->cmd); +out_alloc_cmd: + pci_free_consistent(dev->pdev, (msg_sz * dev->hw_info.cmd_fifo_sz), dev->msg_base, dev->msg_base_dma); +out_alloc_msg: + return -ENOMEM; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) +static irqreturn_t ssd_interrupt_check(int irq, void *dev_id) +{ + struct ssd_queue *queue = (struct ssd_queue *)dev_id; + + if (*(uint32_t *)queue->resp_ptr == queue->resp_idx) { + return IRQ_NONE; + } + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t ssd_interrupt_threaded(int irq, void *dev_id) +{ + struct ssd_queue *queue = (struct ssd_queue *)dev_id; + struct ssd_device *dev = (struct ssd_device *)queue->dev; + struct ssd_cmd *cmd; + union ssd_response_msq __msg; + union ssd_response_msq *msg = &__msg; + uint64_t *u64_msg; + uint32_t resp_idx = queue->resp_idx; + uint32_t new_resp_idx = *(uint32_t *)queue->resp_ptr; + uint32_t end_resp_idx; + + if (unlikely(resp_idx == new_resp_idx)) { + return IRQ_NONE; + } + + end_resp_idx = new_resp_idx & queue->resp_idx_mask; + + do { + resp_idx = (resp_idx + 1) & queue->resp_idx_mask; + + /* the resp msg */ + u64_msg = (uint64_t *)(queue->resp_msg + queue->resp_msg_sz * resp_idx); + msg->u64_msg = *u64_msg; + + if (unlikely(msg->u64_msg == (uint64_t)(-1))) { + hio_err("%s: empty resp msg: queue %d idx %u\n", dev->name, queue->idx, resp_idx); + continue; + } + /* clear the resp msg */ + *u64_msg = (uint64_t)(-1); + + cmd = &queue->cmd[msg->resp_msg.tag]; + /*if (unlikely(!cmd->bio)) { + printk(KERN_WARNING "%s: unknown tag %d fun %#x\n", + dev->name, msg->resp_msg.tag, msg->resp_msg.fun); + continue; + }*/ + + if(unlikely(msg->resp_msg.status & (uint32_t)status_mask)) { + cmd->errors = -EIO; + } else { + cmd->errors = 0; + } + cmd->nr_log = msg->log_resp_msg.nr_log; + + ssd_done(cmd); + + if (unlikely(msg->resp_msg.fun != SSD_FUNC_READ_LOG && msg->resp_msg.log > 0)) { + (void)test_and_set_bit(SSD_LOG_HW, &dev->state); + if (test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->log_work); + } + } + + if (unlikely(msg->resp_msg.status)) { + if (msg->resp_msg.fun == SSD_FUNC_READ || msg->resp_msg.fun == SSD_FUNC_WRITE) { + hio_err("%s: I/O error %d: tag %d fun %#x\n", + dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun); + + /* alarm led */ + ssd_set_alarm(dev); + queue->io_stat.nr_rwerr++; + ssd_gen_swlog(dev, SSD_LOG_EIO, msg->u32_msg[0]); + } else { + hio_info("%s: CMD error %d: tag %d fun %#x\n", + dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun); + + ssd_gen_swlog(dev, SSD_LOG_ECMD, msg->u32_msg[0]); + } + queue->io_stat.nr_ioerr++; + } + + if (msg->resp_msg.fun == SSD_FUNC_READ || + msg->resp_msg.fun == SSD_FUNC_NAND_READ_WOOB || + msg->resp_msg.fun == SSD_FUNC_NAND_READ) { + + queue->ecc_info.bitflip[msg->resp_msg.bitflip]++; + } + }while (resp_idx != end_resp_idx); + + queue->resp_idx = new_resp_idx; + + return IRQ_HANDLED; +} +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)) +static irqreturn_t ssd_interrupt(int irq, void *dev_id, struct pt_regs *regs) +#else +static irqreturn_t ssd_interrupt(int irq, void *dev_id) +#endif +{ + struct ssd_queue *queue = (struct ssd_queue *)dev_id; + struct ssd_device *dev = (struct ssd_device *)queue->dev; + struct ssd_cmd *cmd; + union ssd_response_msq __msg; + union ssd_response_msq *msg = &__msg; + uint64_t *u64_msg; + uint32_t resp_idx = queue->resp_idx; + uint32_t new_resp_idx = *(uint32_t *)queue->resp_ptr; + uint32_t end_resp_idx; + + if (unlikely(resp_idx == new_resp_idx)) { + return IRQ_NONE; + } + +#if (defined SSD_ESCAPE_IRQ) + if (SSD_INT_MSIX != dev->int_mode) { + dev->irq_cpu = smp_processor_id(); + } +#endif + + end_resp_idx = new_resp_idx & queue->resp_idx_mask; + + do { + resp_idx = (resp_idx + 1) & queue->resp_idx_mask; + + /* the resp msg */ + u64_msg = (uint64_t *)(queue->resp_msg + queue->resp_msg_sz * resp_idx); + msg->u64_msg = *u64_msg; + + if (unlikely(msg->u64_msg == (uint64_t)(-1))) { + hio_err("%s: empty resp msg: queue %d idx %u\n", dev->name, queue->idx, resp_idx); + continue; + } + /* clear the resp msg */ + *u64_msg = (uint64_t)(-1); + + cmd = &queue->cmd[msg->resp_msg.tag]; + /*if (unlikely(!cmd->bio)) { + printk(KERN_WARNING "%s: unknown tag %d fun %#x\n", + dev->name, msg->resp_msg.tag, msg->resp_msg.fun); + continue; + }*/ + + if(unlikely(msg->resp_msg.status & (uint32_t)status_mask)) { + cmd->errors = -EIO; + } else { + cmd->errors = 0; + } + cmd->nr_log = msg->log_resp_msg.nr_log; + + ssd_done_bh(cmd); + + if (unlikely(msg->resp_msg.fun != SSD_FUNC_READ_LOG && msg->resp_msg.log > 0)) { + (void)test_and_set_bit(SSD_LOG_HW, &dev->state); + if (test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->log_work); + } + } + + if (unlikely(msg->resp_msg.status)) { + if (msg->resp_msg.fun == SSD_FUNC_READ || msg->resp_msg.fun == SSD_FUNC_WRITE) { + hio_err("%s: I/O error %d: tag %d fun %#x\n", + dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun); + + /* alarm led */ + ssd_set_alarm(dev); + queue->io_stat.nr_rwerr++; + ssd_gen_swlog(dev, SSD_LOG_EIO, msg->u32_msg[0]); + } else { + hio_info("%s: CMD error %d: tag %d fun %#x\n", + dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun); + + ssd_gen_swlog(dev, SSD_LOG_ECMD, msg->u32_msg[0]); + } + queue->io_stat.nr_ioerr++; + } + + if (msg->resp_msg.fun == SSD_FUNC_READ || + msg->resp_msg.fun == SSD_FUNC_NAND_READ_WOOB || + msg->resp_msg.fun == SSD_FUNC_NAND_READ) { + + queue->ecc_info.bitflip[msg->resp_msg.bitflip]++; + } + }while (resp_idx != end_resp_idx); + + queue->resp_idx = new_resp_idx; + + return IRQ_HANDLED; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)) +static irqreturn_t ssd_interrupt_legacy(int irq, void *dev_id, struct pt_regs *regs) +#else +static irqreturn_t ssd_interrupt_legacy(int irq, void *dev_id) +#endif +{ + irqreturn_t ret; + struct ssd_queue *queue = (struct ssd_queue *)dev_id; + struct ssd_device *dev = (struct ssd_device *)queue->dev; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)) + ret = ssd_interrupt(irq, dev_id, regs); +#else + ret = ssd_interrupt(irq, dev_id); +#endif + + /* clear intr */ + if (IRQ_HANDLED == ret) { + ssd_reg32_write(dev->ctrlp + SSD_CLEAR_INTR_REG, 1); + } + + return ret; +} + +static void ssd_reset_resp_ptr(struct ssd_device *dev) +{ + int i; + + for (i=0; inr_queue; i++) { + *(uint32_t *)dev->queue[i].resp_ptr = dev->queue[i].resp_idx = (dev->hw_info.cmd_fifo_sz * 2) - 1; + } +} + +static void ssd_free_irq(struct ssd_device *dev) +{ + int i; + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6)) + if (SSD_INT_MSIX == dev->int_mode) { + for (i=0; inr_queue; i++) { + irq_set_affinity_hint(dev->entry[i].vector, NULL); + } + } +#endif + + for (i=0; inr_queue; i++) { + free_irq(dev->entry[i].vector, &dev->queue[i]); + } + + if (SSD_INT_MSIX == dev->int_mode) { + pci_disable_msix(dev->pdev); + } else if (SSD_INT_MSI == dev->int_mode) { + pci_disable_msi(dev->pdev); + } + +} + +static int ssd_init_irq(struct ssd_device *dev) +{ +#if (!defined MODULE) && (defined SSD_MSIX_AFFINITY_FORCE) + const struct cpumask *cpu_mask; + static int cpu_affinity = 0; +#endif +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6)) + const struct cpumask *mask; + static int cpu = 0; + int j; +#endif + int i; + unsigned long flags = 0; + int ret = 0; + + ssd_reg32_write(dev->ctrlp + SSD_INTR_INTERVAL_REG, 0x800); + +#ifdef SSD_ESCAPE_IRQ + dev->irq_cpu = -1; +#endif + + if (int_mode >= SSD_INT_MSIX && pci_find_capability(dev->pdev, PCI_CAP_ID_MSIX)) { + dev->nr_queue = SSD_MSIX_VEC; + for (i=0; inr_queue; i++) { + dev->entry[i].entry = i; + } + for (;;) { + ret = pci_enable_msix(dev->pdev, dev->entry, dev->nr_queue); + if (ret == 0) { + break; + } else if (ret > 0) { + dev->nr_queue = ret; + } else { + hio_warn("%s: can not enable msix\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out; + } + } + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6)) + mask = (dev_to_node(&dev->pdev->dev) == -1) ? cpu_online_mask : cpumask_of_node(dev_to_node(&dev->pdev->dev)); + if ((0 == cpu) || (!cpumask_intersects(mask, cpumask_of(cpu)))) { + cpu = cpumask_first(mask); + } + for (i=0; inr_queue; i++) { + irq_set_affinity_hint(dev->entry[i].vector, cpumask_of(cpu)); + cpu = cpumask_next(cpu, mask); + if (cpu >= nr_cpu_ids) { + cpu = cpumask_first(mask); + } + } +#endif + + dev->int_mode = SSD_INT_MSIX; + } else if (int_mode >= SSD_INT_MSI && pci_find_capability(dev->pdev, PCI_CAP_ID_MSI)) { + ret = pci_enable_msi(dev->pdev); + if (ret) { + hio_warn("%s: can not enable msi\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out; + } + + dev->nr_queue = 1; + dev->entry[0].vector = dev->pdev->irq; + + dev->int_mode = SSD_INT_MSI; + } else { + dev->nr_queue = 1; + dev->entry[0].vector = dev->pdev->irq; + + dev->int_mode = SSD_INT_LEGACY; + } + + for (i=0; inr_queue; i++) { + if (dev->nr_queue > 1) { + snprintf(dev->queue[i].name, SSD_QUEUE_NAME_LEN, "%s_e100-%d", dev->name, i); + } else { + snprintf(dev->queue[i].name, SSD_QUEUE_NAME_LEN, "%s_e100", dev->name); + } + + dev->queue[i].dev = dev; + dev->queue[i].idx = i; + + dev->queue[i].resp_idx = (dev->hw_info.cmd_fifo_sz * 2) - 1; + dev->queue[i].resp_idx_mask = dev->hw_info.cmd_fifo_sz - 1; + + dev->queue[i].resp_msg_sz = dev->hw_info.resp_msg_sz; + dev->queue[i].resp_msg = dev->resp_msg_base + dev->hw_info.resp_msg_sz * dev->hw_info.cmd_fifo_sz * i; + dev->queue[i].resp_ptr = dev->resp_ptr_base + dev->hw_info.resp_ptr_sz * i; + *(uint32_t *)dev->queue[i].resp_ptr = dev->queue[i].resp_idx; + + dev->queue[i].cmd = dev->cmd; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) + flags = IRQF_SHARED; +#else + flags = SA_SHIRQ; +#endif + + for (i=0; inr_queue; i++) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) + if (threaded_irq) { + ret = request_threaded_irq(dev->entry[i].vector, ssd_interrupt_check, ssd_interrupt_threaded, flags, dev->queue[i].name, &dev->queue[i]); + } else if (dev->int_mode == SSD_INT_LEGACY) { + ret = request_irq(dev->entry[i].vector, &ssd_interrupt_legacy, flags, dev->queue[i].name, &dev->queue[i]); + } else { + ret = request_irq(dev->entry[i].vector, &ssd_interrupt, flags, dev->queue[i].name, &dev->queue[i]); + } +#else + if (dev->int_mode == SSD_INT_LEGACY) { + ret = request_irq(dev->entry[i].vector, &ssd_interrupt_legacy, flags, dev->queue[i].name, &dev->queue[i]); + } else { + ret = request_irq(dev->entry[i].vector, &ssd_interrupt, flags, dev->queue[i].name, &dev->queue[i]); + } +#endif + if (ret) { + hio_warn("%s: request irq failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_request_irq; + } + +#if (!defined MODULE) && (defined SSD_MSIX_AFFINITY_FORCE) + cpu_mask = (dev_to_node(&dev->pdev->dev) == -1) ? cpu_online_mask : cpumask_of_node(dev_to_node(&dev->pdev->dev)); + if (SSD_INT_MSIX == dev->int_mode) { + if ((0 == cpu_affinity) || (!cpumask_intersects(mask, cpumask_of(cpu_affinity)))) { + cpu_affinity = cpumask_first(cpu_mask); + } + + irq_set_affinity(dev->entry[i].vector, cpumask_of(cpu_affinity)); + cpu_affinity = cpumask_next(cpu_affinity, cpu_mask); + if (cpu_affinity >= nr_cpu_ids) { + cpu_affinity = cpumask_first(cpu_mask); + } + } +#endif + } + + return ret; + +out_request_irq: +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6)) + if (SSD_INT_MSIX == dev->int_mode) { + for (j=0; jnr_queue; j++) { + irq_set_affinity_hint(dev->entry[j].vector, NULL); + } + } +#endif + + for (i--; i>=0; i--) { + free_irq(dev->entry[i].vector, &dev->queue[i]); + } + + if (SSD_INT_MSIX == dev->int_mode) { + pci_disable_msix(dev->pdev); + } else if (SSD_INT_MSI == dev->int_mode) { + pci_disable_msi(dev->pdev); + } + +out: + return ret; +} + +static void ssd_initial_log(struct ssd_device *dev) +{ + uint32_t val; + uint32_t speed, width; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_POWER_ON_REG); + if (val) { + ssd_gen_swlog(dev, SSD_LOG_POWER_ON, dev->hw_info.bridge_ver); + } + + val = ssd_reg32_read(dev->ctrlp + SSD_PCIE_LINKSTATUS_REG); + speed = val & 0xF; + width = (val >> 4)& 0x3F; + if (0x1 == speed) { + hio_info("%s: PCIe: 2.5GT/s, x%u\n", dev->name, width); + } else if (0x2 == speed) { + hio_info("%s: PCIe: 5GT/s, x%u\n", dev->name, width); + } else { + hio_info("%s: PCIe: unknown GT/s, x%u\n", dev->name, width); + } + ssd_gen_swlog(dev, SSD_LOG_PCIE_LINK_STATUS, val); + + return; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static void ssd_hwmon_worker(void *data) +{ + struct ssd_device *dev = (struct ssd_device *)data; +#else +static void ssd_hwmon_worker(struct work_struct *work) +{ + struct ssd_device *dev = container_of(work, struct ssd_device, hwmon_work); +#endif + + if (ssd_check_hw(dev)) { + //hio_err("%s: check hardware failed\n", dev->name); + return; + } + + ssd_check_clock(dev); + ssd_check_volt(dev); + + ssd_mon_boardvolt(dev); +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static void ssd_tempmon_worker(void *data) +{ + struct ssd_device *dev = (struct ssd_device *)data; +#else +static void ssd_tempmon_worker(struct work_struct *work) +{ + struct ssd_device *dev = container_of(work, struct ssd_device, tempmon_work); +#endif + + if (ssd_check_hw(dev)) { + //hio_err("%s: check hardware failed\n", dev->name); + return; + } + + ssd_mon_temp(dev); +} + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static void ssd_capmon_worker(void *data) +{ + struct ssd_device *dev = (struct ssd_device *)data; +#else +static void ssd_capmon_worker(struct work_struct *work) +{ + struct ssd_device *dev = container_of(work, struct ssd_device, capmon_work); +#endif + uint32_t cap = 0; + uint32_t cap_threshold = SSD_PL_CAP_THRESHOLD; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + return; + } + + /* fault before? */ + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ret = ssd_check_pl_cap_fast(dev); + if (ret) { + return; + } + } + + /* learn */ + ret = ssd_do_cap_learn(dev, &cap); + if (ret) { + hio_err("%s: cap learn failed\n", dev->name); + ssd_gen_swlog(dev, SSD_LOG_CAP_LEARN_FAULT, 0); + return; + } + + ssd_gen_swlog(dev, SSD_LOG_CAP_STATUS, cap); + + if (SSD_PL_CAP_CP == dev->hw_info_ext.cap_type) { + cap_threshold = SSD_PL_CAP_CP_THRESHOLD; + } + + //use the fw event id? + if (cap < cap_threshold) { + if (!test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_BATTERY_FAULT, 0); + } + } else if (cap >= (cap_threshold + SSD_PL_CAP_THRESHOLD_HYST)) { + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_BATTERY_OK, 0); + } + } +} + +static void ssd_routine_start(void *data) +{ + struct ssd_device *dev; + + if (!data) { + return; + } + dev = data; + + dev->routine_tick++; + + if (test_bit(SSD_INIT_WORKQ, &dev->state) && !ssd_busy(dev)) { + (void)test_and_set_bit(SSD_LOG_HW, &dev->state); + queue_work(dev->workq, &dev->log_work); + } + + if ((dev->routine_tick % SSD_HWMON_ROUTINE_TICK) == 0 && test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->hwmon_work); + } + + if ((dev->routine_tick % SSD_CAPMON_ROUTINE_TICK) == 0 && test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->capmon_work); + } + + if ((dev->routine_tick % SSD_CAPMON2_ROUTINE_TICK) == 0 && test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon) && test_bit(SSD_INIT_WORKQ, &dev->state)) { + /* CAP fault? check again */ + queue_work(dev->workq, &dev->capmon_work); + } + + if (test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->tempmon_work); + } + + /* schedule routine */ + mod_timer(&dev->routine_timer, jiffies + msecs_to_jiffies(SSD_ROUTINE_INTERVAL)); +} + +static void ssd_cleanup_routine(struct ssd_device *dev) +{ + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return; + + (void)ssd_del_timer(&dev->routine_timer); + + (void)ssd_del_timer(&dev->bm_timer); +} + +static int ssd_init_routine(struct ssd_device *dev) +{ + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) + INIT_WORK(&dev->bm_work, ssd_bm_worker, dev); + INIT_WORK(&dev->hwmon_work, ssd_hwmon_worker, dev); + INIT_WORK(&dev->capmon_work, ssd_capmon_worker, dev); + INIT_WORK(&dev->tempmon_work, ssd_tempmon_worker, dev); +#else + INIT_WORK(&dev->bm_work, ssd_bm_worker); + INIT_WORK(&dev->hwmon_work, ssd_hwmon_worker); + INIT_WORK(&dev->capmon_work, ssd_capmon_worker); + INIT_WORK(&dev->tempmon_work, ssd_tempmon_worker); +#endif + + /* initial log */ + ssd_initial_log(dev); + + /* schedule bm routine */ + ssd_add_timer(&dev->bm_timer, msecs_to_jiffies(SSD_BM_CAP_LEARNING_DELAY), ssd_bm_routine_start, dev); + + /* schedule routine */ + ssd_add_timer(&dev->routine_timer, msecs_to_jiffies(SSD_ROUTINE_INTERVAL), ssd_routine_start, dev); + + return 0; +} + +static void +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38)) +__devexit +#endif +ssd_remove_one (struct pci_dev *pdev) +{ + struct ssd_device *dev; + + if (!pdev) { + return; + } + + dev = pci_get_drvdata(pdev); + if (!dev) { + return; + } + + list_del_init(&dev->list); + + ssd_unregister_sysfs(dev); + + /* offline firstly */ + test_and_clear_bit(SSD_ONLINE, &dev->state); + + /* clean work queue first */ + if (!dev->slave) { + test_and_clear_bit(SSD_INIT_WORKQ, &dev->state); + ssd_cleanup_workq(dev); + } + + /* flush cache */ + (void)ssd_flush(dev); + (void)ssd_save_md(dev); + + /* save smart */ + if (!dev->slave) { + ssd_save_smart(dev); + } + + if (test_and_clear_bit(SSD_INIT_BD, &dev->state)) { + ssd_cleanup_blkdev(dev); + } + + if (!dev->slave) { + ssd_cleanup_chardev(dev); + } + + /* clean routine */ + if (!dev->slave) { + ssd_cleanup_routine(dev); + } + + ssd_cleanup_queue(dev); + + ssd_cleanup_tag(dev); + ssd_cleanup_thread(dev); + + ssd_free_irq(dev); + + ssd_cleanup_dcmd(dev); + ssd_cleanup_cmd(dev); + ssd_cleanup_response(dev); + + if (!dev->slave) { + ssd_cleanup_log(dev); + } + + if (dev->reload_fw) { //reload fw + ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FW); + } + + /* unmap physical adress */ +#ifdef LINUX_SUSE_OS + iounmap(dev->ctrlp); +#else + pci_iounmap(pdev, dev->ctrlp); +#endif + + release_mem_region(dev->mmio_base, dev->mmio_len); + + pci_disable_device(pdev); + + pci_set_drvdata(pdev, NULL); + + ssd_put(dev); +} + +static int +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38)) +__devinit +#endif +ssd_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct ssd_device *dev; + int ret = 0; + + if (!pdev || !ent) { + ret = -EINVAL; + goto out; + } + + dev = kmalloc(sizeof(struct ssd_device), GFP_KERNEL); + if (!dev) { + ret = -ENOMEM; + goto out_alloc_dev; + } + memset(dev, 0, sizeof(struct ssd_device)); + + dev->owner = THIS_MODULE; + + if (SSD_SLAVE_PORT_DEVID == ent->device) { + dev->slave = 1; + } + + dev->idx = ssd_get_index(dev->slave); + if (dev->idx < 0) { + ret = -ENOMEM; + goto out_get_index; + } + + if (!dev->slave) { + snprintf(dev->name, SSD_DEV_NAME_LEN, SSD_DEV_NAME); + ssd_set_dev_name(&dev->name[strlen(SSD_DEV_NAME)], SSD_DEV_NAME_LEN-strlen(SSD_DEV_NAME), dev->idx); + + dev->major = ssd_major; + dev->cmajor = ssd_cmajor; + } else { + snprintf(dev->name, SSD_DEV_NAME_LEN, SSD_SDEV_NAME); + ssd_set_dev_name(&dev->name[strlen(SSD_SDEV_NAME)], SSD_DEV_NAME_LEN-strlen(SSD_SDEV_NAME), dev->idx); + dev->major = ssd_major_sl; + dev->cmajor = 0; + } + + atomic_set(&(dev->refcnt), 0); + atomic_set(&(dev->tocnt), 0); + + mutex_init(&dev->fw_mutex); + + //xx + mutex_init(&dev->gd_mutex); + + dev->pdev = pdev; + pci_set_drvdata(pdev, dev); + + kref_init(&dev->kref); + + ret = pci_enable_device(pdev); + if (ret) { + hio_warn("%s: can not enable device\n", dev->name); + goto out_enable_device; + } + + pci_set_master(pdev); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)) + ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK); +#else + ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); +#endif + if (ret) { + hio_warn("%s: set dma mask: failed\n", dev->name); + goto out_set_dma_mask; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)) + ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); +#else + ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); +#endif + if (ret) { + hio_warn("%s: set consistent dma mask: failed\n", dev->name); + goto out_set_dma_mask; + } + + dev->mmio_base = pci_resource_start(pdev, 0); + dev->mmio_len = pci_resource_len(pdev, 0); + + if (!request_mem_region(dev->mmio_base, dev->mmio_len, SSD_DEV_NAME)) { + hio_warn("%s: can not reserve MMIO region 0\n", dev->name); + ret = -EBUSY; + goto out_request_mem_region; + } + + /* 2.6.9 kernel bug */ + dev->ctrlp = pci_iomap(pdev, 0, 0); + if (!dev->ctrlp) { + hio_warn("%s: can not remap IO region 0\n", dev->name); + ret = -ENOMEM; + goto out_pci_iomap; + } + + ret = ssd_check_hw(dev); + if (ret) { + hio_err("%s: check hardware failed\n", dev->name); + goto out_check_hw; + } + + ret = ssd_init_protocol_info(dev); + if (ret) { + hio_err("%s: init protocol info failed\n", dev->name); + goto out_init_protocol_info; + } + + /* alarm led ? */ + ssd_clear_alarm(dev); + + ret = ssd_init_fw_info(dev); + if (ret) { + hio_err("%s: init firmware info failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_fw_info; + } + + /* slave port ? */ + if (dev->slave) { + goto init_next1; + } + + ret = ssd_init_rom_info(dev); + if (ret) { + hio_err("%s: init rom info failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_rom_info; + } + + ret = ssd_init_label(dev); + if (ret) { + hio_err("%s: init label failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_label; + } + + ret = ssd_init_workq(dev); + if (ret) { + hio_warn("%s: init workq failed\n", dev->name); + goto out_init_workq; + } + (void)test_and_set_bit(SSD_INIT_WORKQ, &dev->state); + + ret = ssd_init_log(dev); + if (ret) { + hio_err("%s: init log failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_log; + } + + ret = ssd_init_smart(dev); + if (ret) { + hio_err("%s: init info failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_smart; + } + +init_next1: + ret = ssd_init_hw_info(dev); + if (ret) { + hio_err("%s: init hardware info failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_hw_info; + } + + /* slave port ? */ + if (dev->slave) { + goto init_next2; + } + + ret = ssd_init_sensor(dev); + if (ret) { + hio_err("%s: init sensor failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_sensor; + } + + ret = ssd_init_pl_cap(dev); + if (ret) { + hio_err("%s: int pl_cap failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_pl_cap; + } + +init_next2: + ret = ssd_check_init_state(dev); + if (ret) { + hio_err("%s: check init state failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_check_init_state; + } + + ret = ssd_init_response(dev); + if (ret) { + hio_warn("%s: init resp_msg failed\n", dev->name); + goto out_init_response; + } + + ret = ssd_init_cmd(dev); + if (ret) { + hio_warn("%s: init msg failed\n", dev->name); + goto out_init_cmd; + } + + ret = ssd_init_dcmd(dev); + if (ret) { + hio_warn("%s: init cmd failed\n", dev->name); + goto out_init_dcmd; + } + + ret = ssd_init_irq(dev); + if (ret) { + hio_warn("%s: init irq failed\n", dev->name); + goto out_init_irq; + } + + ret = ssd_init_thread(dev); + if (ret) { + hio_warn("%s: init thread failed\n", dev->name); + goto out_init_thread; + } + + ret = ssd_init_tag(dev); + if(ret) { + hio_warn("%s: init tags failed\n", dev->name); + goto out_init_tags; + } + + /* */ + (void)test_and_set_bit(SSD_ONLINE, &dev->state); + + ret = ssd_init_queue(dev); + if (ret) { + hio_warn("%s: init queue failed\n", dev->name); + goto out_init_queue; + } + + /* slave port ? */ + if (dev->slave) { + goto init_next3; + } + + ret = ssd_init_ot_protect(dev); + if (ret) { + hio_err("%s: int ot_protect failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_int_ot_protect; + } + + ret = ssd_init_wmode(dev); + if (ret) { + hio_warn("%s: init write mode\n", dev->name); + goto out_init_wmode; + } + + /* init routine after hw is ready */ + ret = ssd_init_routine(dev); + if (ret) { + hio_warn("%s: init routine\n", dev->name); + goto out_init_routine; + } + + ret = ssd_init_chardev(dev); + if (ret) { + hio_warn("%s: register char device failed\n", dev->name); + goto out_init_chardev; + } + +init_next3: + ret = ssd_init_blkdev(dev); + if (ret) { + hio_warn("%s: register block device failed\n", dev->name); + goto out_init_blkdev; + } + (void)test_and_set_bit(SSD_INIT_BD, &dev->state); + + ret = ssd_register_sysfs(dev); + if (ret) { + hio_warn("%s: register sysfs failed\n", dev->name); + goto out_register_sysfs; + } + + dev->save_md = 1; + + list_add_tail(&dev->list, &ssd_list); + + return 0; + +out_register_sysfs: + test_and_clear_bit(SSD_INIT_BD, &dev->state); + ssd_cleanup_blkdev(dev); +out_init_blkdev: + /* slave port ? */ + if (!dev->slave) { + ssd_cleanup_chardev(dev); + } +out_init_chardev: + /* slave port ? */ + if (!dev->slave) { + ssd_cleanup_routine(dev); + } +out_init_routine: +out_init_wmode: +out_int_ot_protect: + ssd_cleanup_queue(dev); +out_init_queue: + test_and_clear_bit(SSD_ONLINE, &dev->state); + ssd_cleanup_tag(dev); +out_init_tags: + ssd_cleanup_thread(dev); +out_init_thread: + ssd_free_irq(dev); +out_init_irq: + ssd_cleanup_dcmd(dev); +out_init_dcmd: + ssd_cleanup_cmd(dev); +out_init_cmd: + ssd_cleanup_response(dev); +out_init_response: +out_check_init_state: +out_init_pl_cap: +out_init_sensor: +out_init_hw_info: +out_init_smart: + /* slave port ? */ + if (!dev->slave) { + ssd_cleanup_log(dev); + } +out_init_log: + /* slave port ? */ + if (!dev->slave) { + test_and_clear_bit(SSD_INIT_WORKQ, &dev->state); + ssd_cleanup_workq(dev); + } +out_init_workq: +out_init_label: +out_init_rom_info: +out_init_fw_info: +out_init_protocol_info: +out_check_hw: +#ifdef LINUX_SUSE_OS + iounmap(dev->ctrlp); +#else + pci_iounmap(pdev, dev->ctrlp); +#endif +out_pci_iomap: + release_mem_region(dev->mmio_base, dev->mmio_len); +out_request_mem_region: +out_set_dma_mask: + pci_disable_device(pdev); +out_enable_device: + pci_set_drvdata(pdev, NULL); +out_get_index: + kfree(dev); +out_alloc_dev: +out: + return ret; +} + +static void ssd_cleanup_tasklet(void) +{ + int i; + for_each_online_cpu(i) { + tasklet_kill(&per_cpu(ssd_tasklet, i)); + } +} + +static int ssd_init_tasklet(void) +{ + int i; + + for_each_online_cpu(i) { + INIT_LIST_HEAD(&per_cpu(ssd_doneq, i)); + + if (finject) { + tasklet_init(&per_cpu(ssd_tasklet, i), __ssd_done_db, 0); + } else { + tasklet_init(&per_cpu(ssd_tasklet, i), __ssd_done, 0); + } + } + + return 0; +} + +static struct pci_device_id ssd_pci_tbl[] = { + { 0x10ee, 0x0007, PCI_ANY_ID, PCI_ANY_ID, }, /* g3 */ + { 0x19e5, 0x0007, PCI_ANY_ID, PCI_ANY_ID, }, /* v1 */ + //{ 0x19e5, 0x0008, PCI_ANY_ID, PCI_ANY_ID, }, /* v1 sp*/ + { 0x19e5, 0x0009, PCI_ANY_ID, PCI_ANY_ID, }, /* v2 */ + { 0x19e5, 0x000a, PCI_ANY_ID, PCI_ANY_ID, }, /* v2 dp slave*/ + { 0, } +}; +MODULE_DEVICE_TABLE(pci, ssd_pci_tbl); + +static struct pci_driver ssd_driver = { + .name = MODULE_NAME, + .id_table = ssd_pci_tbl, + .probe = ssd_init_one, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38)) + .remove = __devexit_p(ssd_remove_one), +#else + .remove = ssd_remove_one, +#endif +}; + +/* notifier block to get a notify on system shutdown/halt/reboot */ +static int ssd_notify_reboot(struct notifier_block *nb, unsigned long event, void *buf) +{ + struct ssd_device *dev = NULL; + struct ssd_device *n = NULL; + + list_for_each_entry_safe(dev, n, &ssd_list, list) { + ssd_gen_swlog(dev, SSD_LOG_POWER_OFF, 0); + + (void)ssd_flush(dev); + (void)ssd_save_md(dev); + + /* slave port ? */ + if (!dev->slave) { + ssd_save_smart(dev); + + ssd_stop_workq(dev); + + if (dev->reload_fw) { + ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FW); + } + } + } + + return NOTIFY_OK; +} + +static struct notifier_block ssd_notifier = { + ssd_notify_reboot, NULL, 0 +}; + +static int __init ssd_init_module(void) +{ + int ret = 0; + + hio_info("driver version: %s\n", DRIVER_VERSION); + + ret = ssd_init_index(); + if (ret) { + hio_warn("init index failed\n"); + goto out_init_index; + } + + ret = ssd_init_proc(); + if (ret) { + hio_warn("init proc failed\n"); + goto out_init_proc; + } + + ret = ssd_init_sysfs(); + if (ret) { + hio_warn("init sysfs failed\n"); + goto out_init_sysfs; + } + + ret = ssd_init_tasklet(); + if (ret) { + hio_warn("init tasklet failed\n"); + goto out_init_tasklet; + } + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) + ssd_class = class_simple_create(THIS_MODULE, SSD_DEV_NAME); +#else + ssd_class = class_create(THIS_MODULE, SSD_DEV_NAME); +#endif + if (IS_ERR(ssd_class)) { + ret = PTR_ERR(ssd_class); + goto out_class_create; + } + + if (ssd_cmajor > 0) { + ret = register_chrdev(ssd_cmajor, SSD_CDEV_NAME, &ssd_cfops); + } else { + ret = ssd_cmajor = register_chrdev(ssd_cmajor, SSD_CDEV_NAME, &ssd_cfops); + } + if (ret < 0) { + hio_warn("unable to register chardev major number\n"); + goto out_register_chardev; + } + + if (ssd_major > 0) { + ret = register_blkdev(ssd_major, SSD_DEV_NAME); + } else { + ret = ssd_major = register_blkdev(ssd_major, SSD_DEV_NAME); + } + if (ret < 0) { + hio_warn("unable to register major number\n"); + goto out_register_blkdev; + } + + if (ssd_major_sl > 0) { + ret = register_blkdev(ssd_major_sl, SSD_SDEV_NAME); + } else { + ret = ssd_major_sl = register_blkdev(ssd_major_sl, SSD_SDEV_NAME); + } + if (ret < 0) { + hio_warn("unable to register slave major number\n"); + goto out_register_blkdev_sl; + } + + if (mode < SSD_DRV_MODE_STANDARD || mode > SSD_DRV_MODE_BASE) { + mode = SSD_DRV_MODE_STANDARD; + } + + /* for debug */ + if (mode != SSD_DRV_MODE_STANDARD) { + ssd_minors = 1; + } + + if (int_mode < SSD_INT_LEGACY || int_mode > SSD_INT_MSIX) { + int_mode = SSD_INT_MODE_DEFAULT; + } + + if (threaded_irq) { + int_mode = SSD_INT_MSI; + } + + if (log_level >= SSD_LOG_NR_LEVEL || log_level < SSD_LOG_LEVEL_INFO) { + log_level = SSD_LOG_LEVEL_ERR; + } + + if (wmode < SSD_WMODE_BUFFER || wmode > SSD_WMODE_DEFAULT) { + wmode = SSD_WMODE_DEFAULT; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) + ret = pci_module_init(&ssd_driver); +#else + ret = pci_register_driver(&ssd_driver); +#endif + if (ret) { + hio_warn("pci init failed\n"); + goto out_pci_init; + } + + ret = register_reboot_notifier(&ssd_notifier); + if (ret) { + hio_warn("register reboot notifier failed\n"); + goto out_register_reboot_notifier; + } + + return 0; + +out_register_reboot_notifier: +out_pci_init: + pci_unregister_driver(&ssd_driver); + unregister_blkdev(ssd_major_sl, SSD_SDEV_NAME); +out_register_blkdev_sl: + unregister_blkdev(ssd_major, SSD_DEV_NAME); +out_register_blkdev: + unregister_chrdev(ssd_cmajor, SSD_CDEV_NAME); +out_register_chardev: +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) + class_simple_destroy(ssd_class); +#else + class_destroy(ssd_class); +#endif +out_class_create: + ssd_cleanup_tasklet(); +out_init_tasklet: + ssd_cleanup_sysfs(); +out_init_sysfs: + ssd_cleanup_proc(); +out_init_proc: + ssd_cleanup_index(); +out_init_index: + return ret; + +} + +static void __exit ssd_cleanup_module(void) +{ + + hio_info("unload driver: %s\n", DRIVER_VERSION); + /* exiting */ + ssd_exiting = 1; + + unregister_reboot_notifier(&ssd_notifier); + + pci_unregister_driver(&ssd_driver); + + unregister_blkdev(ssd_major_sl, SSD_SDEV_NAME); + unregister_blkdev(ssd_major, SSD_DEV_NAME); + unregister_chrdev(ssd_cmajor, SSD_CDEV_NAME); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) + class_simple_destroy(ssd_class); +#else + class_destroy(ssd_class); +#endif + + ssd_cleanup_tasklet(); + ssd_cleanup_sysfs(); + ssd_cleanup_proc(); + ssd_cleanup_index(); +} + +int ssd_register_event_notifier(struct block_device *bdev, ssd_event_call event_call) +{ + struct ssd_device *dev; + struct timeval tv; + struct ssd_log *le; + uint64_t cur; + int log_nr; + + if (!bdev || !event_call || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + dev->event_call = event_call; + + do_gettimeofday(&tv); + cur = tv.tv_sec; + + le = (struct ssd_log *)(dev->internal_log.log); + log_nr = dev->internal_log.nr_log; + + while (log_nr--) { + if (le->time <= cur && le->time >= dev->uptime) { + (void)dev->event_call(dev->gd, le->le.event, ssd_parse_log(dev, le, 0)); + } + le++; + } + + return 0; +} + +int ssd_unregister_event_notifier(struct block_device *bdev) +{ + struct ssd_device *dev; + + if (!bdev || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + dev->event_call = NULL; + + return 0; +} + +EXPORT_SYMBOL(ssd_get_label); +EXPORT_SYMBOL(ssd_get_version); +EXPORT_SYMBOL(ssd_set_otprotect); +EXPORT_SYMBOL(ssd_bm_status); +EXPORT_SYMBOL(ssd_submit_pbio); +EXPORT_SYMBOL(ssd_get_pciaddr); +EXPORT_SYMBOL(ssd_get_temperature); +EXPORT_SYMBOL(ssd_register_event_notifier); +EXPORT_SYMBOL(ssd_unregister_event_notifier); +EXPORT_SYMBOL(ssd_reset); +EXPORT_SYMBOL(ssd_set_wmode); + + + +module_init(ssd_init_module); +module_exit(ssd_cleanup_module); +MODULE_VERSION(DRIVER_VERSION); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Huawei SSD DEV Team"); +MODULE_DESCRIPTION("Huawei SSD driver"); diff --git a/ubuntu/hio/hio.h b/ubuntu/hio/hio.h new file mode 100644 index 00000000000000..49fbb458c25cc8 --- /dev/null +++ b/ubuntu/hio/hio.h @@ -0,0 +1,104 @@ +/* +* Huawei SSD device driver +* Copyright (c) 2016, Huawei Technologies Co., Ltd. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ + +#ifndef _HIO_H +#define _HIO_H + +#include +#include +#include +#include + + + +typedef int (*ssd_event_call)(struct gendisk *, int, int); /* gendisk, event id, event level */ +extern int ssd_register_event_notifier(struct block_device *bdev, ssd_event_call event_call); +/* unregister event notifier before module exit */ +extern int ssd_unregister_event_notifier(struct block_device *bdev); + + +/* label */ +#define SSD_LABEL_FIELD_SZ 32 +#define SSD_SN_SZ 16 + +typedef struct ssd_label +{ + char date[SSD_LABEL_FIELD_SZ]; + char sn[SSD_LABEL_FIELD_SZ]; + char part[SSD_LABEL_FIELD_SZ]; + char desc[SSD_LABEL_FIELD_SZ]; + char other[SSD_LABEL_FIELD_SZ]; + char maf[SSD_LABEL_FIELD_SZ]; +} ssd_label_t; + + +/* version */ +typedef struct ssd_version_info +{ + uint32_t bridge_ver; /* bridge fw version: hex */ + uint32_t ctrl_ver; /* controller fw version: hex */ + uint32_t bm_ver; /* battery manager fw version: hex */ + uint8_t pcb_ver; /* main pcb version: char */ + uint8_t upper_pcb_ver; + uint8_t pad0; + uint8_t pad1; +} ssd_version_info_t; + +extern int ssd_get_label(struct block_device *bdev, struct ssd_label *label); +extern int ssd_get_version(struct block_device *bdev, struct ssd_version_info *ver); +extern int ssd_get_temperature(struct block_device *bdev, int *temp); + + +enum ssd_bmstatus +{ + SSD_BMSTATUS_OK = 0, + SSD_BMSTATUS_CHARGING, + SSD_BMSTATUS_WARNING +}; +extern int ssd_bm_status(struct block_device *bdev, int *status); + +enum ssd_otprotect +{ + SSD_OTPROTECT_OFF = 0, + SSD_OTPROTECT_ON +}; +extern int ssd_set_otprotect(struct block_device *bdev, int otprotect); + +typedef struct pci_addr +{ + uint16_t domain; + uint8_t bus; + uint8_t slot; + uint8_t func; +} pci_addr_t; +extern int ssd_get_pciaddr(struct block_device *bdev, struct pci_addr *paddr); + +/* submit phys bio: phys addr in iovec */ +extern void ssd_submit_pbio(struct request_queue *q, struct bio *bio); + +extern int ssd_reset(struct block_device *bdev); + +enum ssd_write_mode +{ + SSD_WMODE_BUFFER = 0, + SSD_WMODE_BUFFER_EX, + SSD_WMODE_FUA, + /* dummy */ + SSD_WMODE_AUTO, + SSD_WMODE_DEFAULT +}; +extern int ssd_set_wmode(struct block_device *bdev, int wmode); + +#endif + diff --git a/ubuntu/igh-ecat/Kconfig b/ubuntu/igh-ecat/Kconfig new file mode 100644 index 00000000000000..883592f1ca2730 --- /dev/null +++ b/ubuntu/igh-ecat/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only + +menuconfig IGH_ECAT + tristate "IgH EtherCAT master driver support" + depends on NET && ETHERNET + default m + help + This section contains options for IgH EtherCAT master support. + +if IGH_ECAT + +config IGH_ECAT_GENERIC_DEVICE + tristate "Enable IgH EtherCAT master generic device driver" + depends on IGH_ECAT + +config IGH_ECAT_ENABLE_EOE + bool "Enable Ethernet over EtherCAT (EoE) support" + depends on IGH_ECAT + default y + +endif # IGH_ECAT diff --git a/ubuntu/igh-ecat/Makefile b/ubuntu/igh-ecat/Makefile new file mode 100644 index 00000000000000..7f99d29763c7ac --- /dev/null +++ b/ubuntu/igh-ecat/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +IGH_ECAT_REV := 1.6.8 + +subdir-ccflags-y += -DREV=$(IGH_ECAT_REV) + +obj-$(CONFIG_IGH_ECAT) += devices/ master/ diff --git a/ubuntu/igh-ecat/config.h b/ubuntu/igh-ecat/config.h new file mode 100644 index 00000000000000..558fe7e327eb33 --- /dev/null +++ b/ubuntu/igh-ecat/config.h @@ -0,0 +1,100 @@ +/* config.h. Generated from config.h.in by configure. */ +/* config.h.in. Generated from configure.ac by autoheader. */ + +/* Debug interfaces enabled */ +/* #undef EC_DEBUG_IF */ + +/* Debug ring enabled */ +/* #undef EC_DEBUG_RING */ + +/* EoE support enabled */ +#define EC_EOE 1 + +/* Use CPU timestamp counter */ +/* #undef EC_HAVE_CYCLES */ + +/* Use vendor id / product code wildcards */ +/* #undef EC_IDENT_WILDCARDS */ + +/* Max. number of Ethernet devices per master */ +#define EC_MAX_NUM_DEVICES 1 + +/* Read alias adresses from register */ +/* #undef EC_REGALIAS */ + +/* RTDM interface enabled */ +/* #undef EC_RTDM */ + +/* Use Xenomai3 RTDM flavour */ +/* #undef EC_RTDM_XENOMAI_V3 */ + +/* Output to syslog in RT context */ +#define EC_RT_SYSLOG 1 + +/* Assign SII to PDI */ +#define EC_SII_ASSIGN 1 + +/* Use hrtimer for scheduling */ +/* #undef EC_USE_HRTIMER */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DLFCN_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_INTTYPES_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDIO_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDLIB_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRINGS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRING_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_STAT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_TYPES_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_UNISTD_H 1 + +/* Define to the sub-directory where libtool stores uninstalled libraries. */ +#define LT_OBJDIR ".libs/" + +/* Name of package */ +#define PACKAGE "ethercat" + +/* Define to the address where bug reports for this package should be sent. */ +#define PACKAGE_BUGREPORT "fp@igh.de" + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "ethercat" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "ethercat 1.6.8" + +/* Define to the one symbol short name of this package. */ +#define PACKAGE_TARNAME "ethercat" + +/* Define to the home page for this package. */ +#define PACKAGE_URL "" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "1.6.8" + +/* Define to 1 if all of the C89 standard headers exist (not just the ones + required in a freestanding environment). This macro is provided for + backward compatibility; new code need not use it. */ +#define STDC_HEADERS 1 + +/* Version number of package */ +#define VERSION "1.6.8" diff --git a/ubuntu/igh-ecat/devices/Makefile b/ubuntu/igh-ecat/devices/Makefile new file mode 100644 index 00000000000000..dd8d554117c24f --- /dev/null +++ b/ubuntu/igh-ecat/devices/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_IGH_ECAT_GENERIC_DEVICE) += ec_generic.o + +ec_generic-objs := generic.o diff --git a/ubuntu/igh-ecat/devices/ecdev.h b/ubuntu/igh-ecat/devices/ecdev.h new file mode 100644 index 00000000000000..2f2e51d50ef928 --- /dev/null +++ b/ubuntu/igh-ecat/devices/ecdev.h @@ -0,0 +1,71 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * + * EtherCAT interface for EtherCAT device drivers. + * + * \defgroup DeviceInterface EtherCAT Device Interface + * + * Master interface for EtherCAT-capable network device drivers. Through the + * EtherCAT device interface, EtherCAT-capable network device drivers are able + * to connect their device(s) to the master, pass received frames and notify + * the master about status changes. The master on his part, can send his + * frames through connected devices. + */ + +/****************************************************************************/ + +#ifndef __ECDEV_H__ +#define __ECDEV_H__ + +#include + +/****************************************************************************/ + +struct ec_device; +typedef struct ec_device ec_device_t; /**< \see ec_device */ + +/** Device poll function type. + */ +typedef void (*ec_pollfunc_t)(struct net_device *); + +/***************************************************************************** + * Offering/withdrawal functions + ****************************************************************************/ + +ec_device_t *ecdev_offer(struct net_device *net_dev, ec_pollfunc_t poll, + struct module *module); +void ecdev_withdraw(ec_device_t *device); + +/***************************************************************************** + * Device methods + ****************************************************************************/ + +int ecdev_open(ec_device_t *device); +void ecdev_close(ec_device_t *device); +void ecdev_receive(ec_device_t *device, const void *data, size_t size); +void ecdev_set_link(ec_device_t *device, uint8_t state); +uint8_t ecdev_get_link(const ec_device_t *device); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/devices/generic.c b/ubuntu/igh-ecat/devices/generic.c new file mode 100644 index 00000000000000..2368c8b3650d48 --- /dev/null +++ b/ubuntu/igh-ecat/devices/generic.c @@ -0,0 +1,483 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT generic Ethernet device module. + */ + +/****************************************************************************/ + +#include +#include +#include +#include +#include /* ARPHRD_ETHER */ +#include + +#include "../globals.h" +#include "ecdev.h" + +#define PFX "ec_generic: " + +#define ETH_P_ETHERCAT 0x88A4 + +#define EC_GEN_RX_BUF_SIZE 1600 + +#if defined(CONFIG_SUSE_KERNEL) && LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) +#include +#else +# ifndef SUSE_VERSION +# define SUSE_VERSION 0 +# endif +# ifndef SUSE_PATCHLEVEL +# define SUSE_PATCHLEVEL 0 +# endif +#endif + +/****************************************************************************/ + +int __init ec_gen_init_module(void); +void __exit ec_gen_cleanup_module(void); +void ec_gen_poll(struct net_device *); + +/****************************************************************************/ + +/** \cond */ + +MODULE_AUTHOR("Florian Pose "); +MODULE_DESCRIPTION("EtherCAT master generic Ethernet device module"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(EC_MASTER_VERSION); + +/** \endcond */ + +struct list_head generic_devices; + +typedef struct { + struct list_head list; + struct net_device *netdev; + struct net_device *used_netdev; + struct socket *socket; + ec_device_t *ecdev; + uint8_t *rx_buf; +} ec_gen_device_t; + +typedef struct { + struct list_head list; + struct net_device *netdev; + char name[IFNAMSIZ]; + int ifindex; + uint8_t dev_addr[ETH_ALEN]; +} ec_gen_interface_desc_t; + +int ec_gen_device_init(ec_gen_device_t *); +void ec_gen_device_clear(ec_gen_device_t *); +int ec_gen_device_create_socket(ec_gen_device_t *, ec_gen_interface_desc_t *); +int ec_gen_device_offer(ec_gen_device_t *, ec_gen_interface_desc_t *); +int ec_gen_device_open(ec_gen_device_t *); +int ec_gen_device_stop(ec_gen_device_t *); +int ec_gen_device_start_xmit(ec_gen_device_t *, struct sk_buff *); +void ec_gen_device_poll(ec_gen_device_t *); + +int offer_device(ec_gen_interface_desc_t *); +void clear_devices(void); + +/****************************************************************************/ + +static int ec_gen_netdev_open(struct net_device *dev) +{ + ec_gen_device_t *gendev = *((ec_gen_device_t **) netdev_priv(dev)); + return ec_gen_device_open(gendev); +} + +/****************************************************************************/ + +static int ec_gen_netdev_stop(struct net_device *dev) +{ + ec_gen_device_t *gendev = *((ec_gen_device_t **) netdev_priv(dev)); + return ec_gen_device_stop(gendev); +} + +/****************************************************************************/ + +static int ec_gen_netdev_start_xmit( + struct sk_buff *skb, + struct net_device *dev + ) +{ + ec_gen_device_t *gendev = *((ec_gen_device_t **) netdev_priv(dev)); + return ec_gen_device_start_xmit(gendev, skb); +} + +/****************************************************************************/ + +void ec_gen_poll(struct net_device *dev) +{ + ec_gen_device_t *gendev = *((ec_gen_device_t **) netdev_priv(dev)); + ec_gen_device_poll(gendev); +} + +/****************************************************************************/ + +static const struct net_device_ops ec_gen_netdev_ops = { + .ndo_open = ec_gen_netdev_open, + .ndo_stop = ec_gen_netdev_stop, + .ndo_start_xmit = ec_gen_netdev_start_xmit, +}; + +/****************************************************************************/ + +/** Init generic device. + */ +int ec_gen_device_init( + ec_gen_device_t *dev + ) +{ + ec_gen_device_t **priv; + char null = 0x00; + + dev->ecdev = NULL; + dev->socket = NULL; + dev->rx_buf = NULL; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) + dev->netdev = alloc_netdev(sizeof(ec_gen_device_t *), &null, + NET_NAME_UNKNOWN, ether_setup); +#else + dev->netdev = alloc_netdev(sizeof(ec_gen_device_t *), &null, ether_setup); +#endif + if (!dev->netdev) { + return -ENOMEM; + } + + dev->netdev->netdev_ops = &ec_gen_netdev_ops; + + priv = netdev_priv(dev->netdev); + *priv = dev; + + return 0; +} + +/****************************************************************************/ + +/** Clear generic device. + */ +void ec_gen_device_clear( + ec_gen_device_t *dev + ) +{ + if (dev->ecdev) { + ecdev_close(dev->ecdev); + ecdev_withdraw(dev->ecdev); + } + if (dev->socket) { + sock_release(dev->socket); + } + free_netdev(dev->netdev); + + if (dev->rx_buf) { + kfree(dev->rx_buf); + } +} + +/****************************************************************************/ + +/** Creates a network socket. + */ +int ec_gen_device_create_socket( + ec_gen_device_t *dev, + ec_gen_interface_desc_t *desc + ) +{ + int ret; + struct sockaddr_ll sa; + + dev->rx_buf = kmalloc(EC_GEN_RX_BUF_SIZE, GFP_KERNEL); + if (!dev->rx_buf) { + return -ENOMEM; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0) + ret = sock_create_kern(&init_net, PF_PACKET, SOCK_RAW, + htons(ETH_P_ETHERCAT), &dev->socket); +#else + ret = sock_create_kern(PF_PACKET, SOCK_RAW, htons(ETH_P_ETHERCAT), + &dev->socket); +#endif + if (ret) { + printk(KERN_ERR PFX "Failed to create socket (ret = %i).\n", ret); + return ret; + } + + printk(KERN_ERR PFX "Binding socket to interface %i (%s).\n", + desc->ifindex, desc->name); + + memset(&sa, 0x00, sizeof(sa)); + sa.sll_family = AF_PACKET; + sa.sll_protocol = htons(ETH_P_ETHERCAT); + sa.sll_ifindex = desc->ifindex; + ret = kernel_bind(dev->socket, (struct sockaddr_unsized *) &sa, sizeof(sa)); + if (ret) { + printk(KERN_ERR PFX "Failed to bind() socket to interface" + " (ret = %i).\n", ret); + sock_release(dev->socket); + dev->socket = NULL; + return ret; + } + + return 0; +} + +/****************************************************************************/ + +/** Offer generic device to master. + */ +int ec_gen_device_offer( + ec_gen_device_t *dev, + ec_gen_interface_desc_t *desc + ) +{ + int ret = 0; + + dev->used_netdev = desc->netdev; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) || (SUSE_VERSION == 15 && SUSE_PATCHLEVEL >= 5) + eth_hw_addr_set(dev->netdev, desc->dev_addr); +#else + memcpy(dev->netdev->dev_addr, desc->dev_addr, ETH_ALEN); +#endif + + dev->ecdev = ecdev_offer(dev->netdev, ec_gen_poll, THIS_MODULE); + if (dev->ecdev) { + if (ec_gen_device_create_socket(dev, desc)) { + ecdev_withdraw(dev->ecdev); + dev->ecdev = NULL; + } else if (ecdev_open(dev->ecdev)) { + ecdev_withdraw(dev->ecdev); + dev->ecdev = NULL; + } else { + ecdev_set_link(dev->ecdev, netif_carrier_ok(dev->used_netdev)); // FIXME + ret = 1; + } + } + + return ret; +} + +/****************************************************************************/ + +/** Open the device. + */ +int ec_gen_device_open( + ec_gen_device_t *dev + ) +{ + return 0; +} + +/****************************************************************************/ + +/** Stop the device. + */ +int ec_gen_device_stop( + ec_gen_device_t *dev + ) +{ + return 0; +} + +/****************************************************************************/ + +int ec_gen_device_start_xmit( + ec_gen_device_t *dev, + struct sk_buff *skb + ) +{ + struct msghdr msg; + struct kvec iov; + size_t len = skb->len; + int ret; + + ecdev_set_link(dev->ecdev, netif_carrier_ok(dev->used_netdev)); + + iov.iov_base = skb->data; + iov.iov_len = len; + memset(&msg, 0, sizeof(msg)); + + ret = kernel_sendmsg(dev->socket, &msg, &iov, 1, len); + + return ret == len ? NETDEV_TX_OK : NETDEV_TX_BUSY; +} + +/****************************************************************************/ + +/** Polls the device. + */ +void ec_gen_device_poll( + ec_gen_device_t *dev + ) +{ + struct msghdr msg; + struct kvec iov; + int ret, budget = 10; // FIXME + + ecdev_set_link(dev->ecdev, netif_carrier_ok(dev->used_netdev)); + + do { + iov.iov_base = dev->rx_buf; + iov.iov_len = EC_GEN_RX_BUF_SIZE; + memset(&msg, 0, sizeof(msg)); + + ret = kernel_recvmsg(dev->socket, &msg, &iov, 1, iov.iov_len, + MSG_DONTWAIT); + if (ret > 0) { + ecdev_receive(dev->ecdev, dev->rx_buf, ret); + } else if (ret < 0) { + break; + } + budget--; + } while (budget); +} + +/****************************************************************************/ + +/** Offer device. + */ +int offer_device( + ec_gen_interface_desc_t *desc + ) +{ + ec_gen_device_t *gendev; + int ret = 0; + + gendev = kmalloc(sizeof(ec_gen_device_t), GFP_KERNEL); + if (!gendev) { + return -ENOMEM; + } + + ret = ec_gen_device_init(gendev); + if (ret) { + kfree(gendev); + return ret; + } + + if (ec_gen_device_offer(gendev, desc)) { + list_add_tail(&gendev->list, &generic_devices); + } else { + ec_gen_device_clear(gendev); + kfree(gendev); + } + + return ret; +} + +/****************************************************************************/ + +/** Clear devices. + */ +void clear_devices(void) +{ + ec_gen_device_t *gendev, *next; + + list_for_each_entry_safe(gendev, next, &generic_devices, list) { + list_del(&gendev->list); + ec_gen_device_clear(gendev); + kfree(gendev); + } +} + +/****************************************************************************/ + +/** Module initialization. + * + * Initializes \a master_count masters. + * \return 0 on success, else < 0 + */ +int __init ec_gen_init_module(void) +{ + int ret = 0; + struct list_head descs; + struct net_device *netdev; + ec_gen_interface_desc_t *desc, *next; + + printk(KERN_INFO PFX "EtherCAT master generic Ethernet device module %s\n", + EC_MASTER_VERSION); + + INIT_LIST_HEAD(&generic_devices); + INIT_LIST_HEAD(&descs); + + rcu_read_lock(); + for_each_netdev_rcu(&init_net, netdev) { + if (netdev->type != ARPHRD_ETHER) + continue; + desc = kmalloc(sizeof(ec_gen_interface_desc_t), GFP_ATOMIC); + if (!desc) { + ret = -ENOMEM; + rcu_read_unlock(); + goto out_err; + } + strscpy(desc->name, netdev->name, IFNAMSIZ); + desc->netdev = netdev; + desc->ifindex = netdev->ifindex; + memcpy(desc->dev_addr, netdev->dev_addr, ETH_ALEN); + list_add_tail(&desc->list, &descs); + } + rcu_read_unlock(); + + list_for_each_entry_safe(desc, next, &descs, list) { + ret = offer_device(desc); + if (ret) { + goto out_err; + } + kfree(desc); + } + return ret; + +out_err: + list_for_each_entry_safe(desc, next, &descs, list) { + list_del(&desc->list); + kfree(desc); + } + clear_devices(); + return ret; +} + +/****************************************************************************/ + +/** Module cleanup. + * + * Clears all master instances. + */ +void __exit ec_gen_cleanup_module(void) +{ + clear_devices(); + printk(KERN_INFO PFX "Unloading.\n"); +} + +/****************************************************************************/ + +/** \cond */ + +module_init(ec_gen_init_module); +module_exit(ec_gen_cleanup_module); + +/** \endcond */ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/globals.h b/ubuntu/igh-ecat/globals.h new file mode 100644 index 00000000000000..d2a470e9ce8c7f --- /dev/null +++ b/ubuntu/igh-ecat/globals.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright (C) 2006-2021 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT master. + * + * The file is free software; you can redistribute it and/or modify it under + * the terms of the GNU Lesser General Public License as published by the + * Free Software Foundation; version 2.1 of the License. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + * License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this file. If not, see . + * + *****************************************************************************/ + +/** + \file + Global definitions and macros. +*/ + +/*****************************************************************************/ + +#ifndef __EC_GLOBALS_H__ +#define __EC_GLOBALS_H__ + +#include "config.h" + +/****************************************************************************** + * Overall macros + *****************************************************************************/ + +/** Helper macro for EC_STR(), literates a macro argument. + * + * \param X argument to literate. + */ +#define EC_LIT(X) #X + +/** Converts a macro argument to a string. + * + * \param X argument to stringify. + */ +#define EC_STR(X) EC_LIT(X) + +/** Master version string + */ +#define EC_MASTER_VERSION VERSION " " EC_STR(REV) + +/*****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/include/Makefile.am b/ubuntu/igh-ecat/include/Makefile.am new file mode 100644 index 00000000000000..3ae0eeff8bbf7a --- /dev/null +++ b/ubuntu/igh-ecat/include/Makefile.am @@ -0,0 +1,26 @@ +#----------------------------------------------------------------------------- +# +# Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH +# +# This file is part of the IgH EtherCAT Master. +# +# The IgH EtherCAT Master is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License version 2, as +# published by the Free Software Foundation. +# +# The IgH EtherCAT Master is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General +# Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with the IgH EtherCAT Master; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +#----------------------------------------------------------------------------- + +include_HEADERS = \ + ecrt.h \ + ectty.h + +#----------------------------------------------------------------------------- diff --git a/ubuntu/igh-ecat/include/ecrt.h b/ubuntu/igh-ecat/include/ecrt.h new file mode 100644 index 00000000000000..3ab462fbc2b59d --- /dev/null +++ b/ubuntu/igh-ecat/include/ecrt.h @@ -0,0 +1,3153 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT master userspace library. + * + * The IgH EtherCAT master userspace library is free software; you can + * redistribute it and/or modify it under the terms of the GNU Lesser General + * Public License as published by the Free Software Foundation; version 2.1 + * of the License. + * + * The IgH EtherCAT master userspace library is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with the IgH EtherCAT master userspace library. If not, see + * . + * + ****************************************************************************/ + +/** \file + * + * EtherCAT master application interface. + * + * \defgroup ApplicationInterface EtherCAT Application Interface + * + * EtherCAT interface for realtime applications. This interface is designed + * for realtime modules that want to use EtherCAT. There are functions to + * request a master, to map process data, to communicate with slaves via CoE + * and to configure and activate the bus. + * + * + * Changes in version 1.6.0: + * + * - Added the ecrt_master_scan_progress() method, the + * ec_master_scan_progress_t structure and the EC_HAVE_SCAN_PROGRESS + * definition to check for its existence. + * - Added the EoE configuration methods ecrt_slave_config_eoe_mac_address(), + * ecrt_slave_config_eoe_ip_address(), ecrt_slave_config_eoe_subnet_mask(), + * ecrt_slave_config_eoe_default_gateway(), + * ecrt_slave_config_eoe_dns_address(), + * ecrt_slave_config_eoe_hostname() and the EC_HAVE_SET_IP + * definition to check for its existence. + * - Added ecrt_slave_config_state_timeout() to set the application-layer + * state change timeout and EC_HAVE_STATE_TIMEOUT to check for its + * existence. + * + * Changes since version 1.5.2: + * + * - Added the ecrt_slave_config_flag() method and the EC_HAVE_FLAGS + * definition to check for its existence. + * - Added SoE IDN requests, including the datatype ec_soe_request_t and the + * methods ecrt_slave_config_create_soe_request(), + * ecrt_soe_request_object(), ecrt_soe_request_timeout(), + * ecrt_soe_request_data(), ecrt_soe_request_data_size(), + * ecrt_soe_request_state(), ecrt_soe_request_write() and + * ecrt_soe_request_read(). Use the EC_HAVE_SOE_REQUESTS to check, if the + * functionality is available. + * + * Changes in version 1.5.2: + * + * - Added redundancy_active flag to ec_domain_state_t. + * - Added ecrt_master_link_state() method and ec_master_link_state_t to query + * the state of a redundant link. + * - Added the EC_HAVE_REDUNDANCY define, to check, if the interface contains + * redundancy features. + * - Added ecrt_sdo_request_index() to change SDO index and subindex after + * request creation. + * - Added interface for retrieving CoE emergency messages, i. e. + * ecrt_slave_config_emerg_size(), ecrt_slave_config_emerg_pop(), + * ecrt_slave_config_emerg_clear(), ecrt_slave_config_emerg_overruns() and + * the defines EC_HAVE_EMERGENCY and EC_COE_EMERGENCY_MSG_SIZE. + * - Added interface for direct EtherCAT register access: Added data type + * ec_reg_request_t and methods ecrt_slave_config_create_reg_request(), + * ecrt_reg_request_data(), ecrt_reg_request_state(), + * ecrt_reg_request_write(), ecrt_reg_request_read() and the feature flag + * EC_HAVE_REG_ACCESS. + * - Added method to select the reference clock, + * ecrt_master_select_reference_clock() and the feature flag + * EC_HAVE_SELECT_REF_CLOCK to check, if the method is available. + * - Added method to get the reference clock time, + * ecrt_master_reference_clock_time() and the feature flag + * EC_HAVE_REF_CLOCK_TIME to have the possibility to synchronize the master + * clock to the reference clock. + * - Changed the data types of the shift times in ecrt_slave_config_dc() to + * int32_t to correctly display negative shift times. + * - Added ecrt_slave_config_reg_pdo_entry_pos() and the feature flag + * EC_HAVE_REG_BY_POS for registering PDO entries with non-unique indices + * via their positions in the mapping. + * + * Changes in version 1.5: + * + * - Added the distributed clocks feature and the respective method + * ecrt_slave_config_dc() to configure a slave for cyclic operation, and + * ecrt_master_application_time(), ecrt_master_sync_reference_clock() and + * ecrt_master_sync_slave_clocks() for offset and drift compensation. The + * EC_TIMEVAL2NANO() macro can be used for epoch time conversion, while the + * ecrt_master_sync_monitor_queue() and ecrt_master_sync_monitor_process() + * methods can be used to monitor the synchrony. + * - Improved the callback mechanism. ecrt_master_callbacks() now takes two + * callback functions for sending and receiving datagrams. + * ecrt_master_send_ext() is used to execute the sending of non-application + * datagrams. + * - Added watchdog configuration (method ecrt_slave_config_watchdog(), + * #ec_watchdog_mode_t, \a watchdog_mode parameter in ec_sync_info_t and + * ecrt_slave_config_sync_manager()). + * - Added ecrt_slave_config_complete_sdo() method to download an SDO during + * configuration via CompleteAccess. + * - Added ecrt_master_deactivate() to remove the master configuration. + * - Added ecrt_open_master() and ecrt_master_reserve() separation for + * userspace. + * - Added master information interface (methods ecrt_master(), + * ecrt_master_get_slave(), ecrt_master_get_sync_manager(), + * ecrt_master_get_pdo() and ecrt_master_get_pdo_entry()) to get information + * about the currently connected slaves and the PDO entries provided. + * - Added ecrt_master_sdo_download(), ecrt_master_sdo_download_complete() and + * ecrt_master_sdo_upload() methods to let an application transfer SDOs + * before activating the master. + * - Changed the meaning of the negative return values of + * ecrt_slave_config_reg_pdo_entry() and ecrt_slave_config_sdo*(). + * - Implemented the Vendor-specific over EtherCAT mailbox protocol. See + * ecrt_slave_config_create_voe_handler(). + * - Renamed ec_sdo_request_state_t to #ec_request_state_t, because it is also + * used by VoE handlers. + * - Removed 'const' from argument of ecrt_sdo_request_state(), because the + * userspace library has to modify object internals. + * - Added 64-bit data access macros. + * - Added ecrt_slave_config_idn() method for storing SoE IDN configurations, + * and ecrt_master_read_idn() and ecrt_master_write_idn() to read/write IDNs + * ad-hoc via the user-space library. + * - Added ecrt_master_reset() to initiate retrying to configure slaves. + * + * @{ + */ + +/****************************************************************************/ + +#ifndef __ECRT_H__ +#define __ECRT_H__ + +#ifdef __KERNEL__ +#include +#include +#include +#include // struct in_addr +#else +#include // for size_t +#include +#include // for struct timeval +#include // struct in_addr +#endif + +/***************************************************************************** + * Global definitions + ****************************************************************************/ + +/** EtherCAT realtime interface major version number. + */ +#define ECRT_VER_MAJOR 1 + +/** EtherCAT realtime interface minor version number. + */ +#define ECRT_VER_MINOR 6 + +/** EtherCAT realtime interface version word generator. + */ +#define ECRT_VERSION(a, b) (((a) << 8) + (b)) + +/** EtherCAT realtime interface version word. + */ +#define ECRT_VERSION_MAGIC ECRT_VERSION(ECRT_VER_MAJOR, ECRT_VER_MINOR) + +/***************************************************************************** + * Feature flags + ****************************************************************************/ + +/** Defined, if the redundancy features are available. + * + * I. e. if the \a redundancy_active flag in ec_domain_state_t and the + * ecrt_master_link_state() method are available. + */ +#define EC_HAVE_REDUNDANCY + +/** Defined, if the CoE emergency ring feature is available. + * + * I. e. if the ecrt_slave_config_emerg_*() methods are available. + */ +#define EC_HAVE_EMERGENCY + +/** Defined, if the register access interface is available. + * + * I. e. if the methods ecrt_slave_config_create_reg_request(), + * ecrt_reg_request_data(), ecrt_reg_request_state(), ecrt_reg_request_write() + * and ecrt_reg_request_read() are available. + */ +#define EC_HAVE_REG_ACCESS + +/** Defined if the method ecrt_master_select_reference_clock() is available. + */ +#define EC_HAVE_SELECT_REF_CLOCK + +/** Defined if the method ecrt_master_reference_clock_time() is available. + */ +#define EC_HAVE_REF_CLOCK_TIME + +/** Defined if the method ecrt_slave_config_reg_pdo_entry_pos() is available. + */ +#define EC_HAVE_REG_BY_POS + +/** Defined if the method ecrt_master_sync_reference_clock_to() is available. + */ +#define EC_HAVE_SYNC_TO + +/** Defined if the method ecrt_slave_config_flag() is available. + */ +#define EC_HAVE_FLAGS + +/** Defined if the methods ecrt_slave_config_create_soe_request(), + * ecrt_soe_request_object(), ecrt_soe_request_timeout(), + * ecrt_soe_request_data(), ecrt_soe_request_data_size(), + * ecrt_soe_request_state(), ecrt_soe_request_write() and + * ecrt_soe_request_read() and the datatype ec_soe_request_t are available. + */ +#define EC_HAVE_SOE_REQUESTS + +/** Defined, if the method ecrt_master_scan_progress() and the + * ec_master_scan_progress_t structure are available. + */ +#define EC_HAVE_SCAN_PROGRESS + +/** Defined, if the methods ecrt_slave_config_eoe_mac_address(), + * ecrt_slave_config_eoe_ip_address(), ecrt_slave_config_eoe_subnet_mask(), + * ecrt_slave_config_eoe_default_gateway(), + * ecrt_slave_config_eoe_dns_address(), ecrt_slave_config_eoe_hostname() are + * available. + */ +#define EC_HAVE_SET_IP + +/** Defined, if the method ecrt_slave_config_state_timeout() is available. + */ +#define EC_HAVE_STATE_TIMEOUT + +/****************************************************************************/ + +/** Symbol visibility control macro. + */ +#ifndef EC_PUBLIC_API +# if defined(ethercat_EXPORTS) && !defined(__KERNEL__) +# define EC_PUBLIC_API __attribute__ ((visibility ("default"))) +# else +# define EC_PUBLIC_API +# endif +#endif + +/****************************************************************************/ + +/** End of list marker. + * + * This can be used with ecrt_slave_config_pdos(). + */ +#define EC_END ~0U + +/** Maximum number of sync managers per slave. + */ +#define EC_MAX_SYNC_MANAGERS 16 + +/** Maximum string length. + * + * Used in ec_slave_info_t. + */ +#define EC_MAX_STRING_LENGTH 64 + +/** Maximum number of slave ports. */ +#define EC_MAX_PORTS 4 + +/** Timeval to nanoseconds conversion. + * + * This macro converts a Unix epoch time to EtherCAT DC time. + * + * \see void ecrt_master_application_time() + * + * \param TV struct timeval containing epoch time. + */ +#define EC_TIMEVAL2NANO(TV) \ + (((TV).tv_sec - 946684800ULL) * 1000000000ULL + (TV).tv_usec * 1000ULL) + +/** Size of a CoE emergency message in byte. + * + * \see ecrt_slave_config_emerg_pop(). + */ +#define EC_COE_EMERGENCY_MSG_SIZE 8 + +/***************************************************************************** + * Data types + ****************************************************************************/ + +struct ec_master; +typedef struct ec_master ec_master_t; /**< \see ec_master */ + +struct ec_slave_config; +typedef struct ec_slave_config ec_slave_config_t; /**< \see ec_slave_config */ + +struct ec_domain; +typedef struct ec_domain ec_domain_t; /**< \see ec_domain */ + +struct ec_sdo_request; +typedef struct ec_sdo_request ec_sdo_request_t; /**< \see ec_sdo_request. */ + +struct ec_soe_request; +typedef struct ec_soe_request ec_soe_request_t; /**< \see ec_soe_request. */ + +struct ec_voe_handler; +typedef struct ec_voe_handler ec_voe_handler_t; /**< \see ec_voe_handler. */ + +struct ec_reg_request; +typedef struct ec_reg_request ec_reg_request_t; /**< \see ec_reg_request. */ + +/****************************************************************************/ + +/** Master state. + * + * This is used for the output parameter of ecrt_master_state(). + * + * \see ecrt_master_state(). + */ +typedef struct { + unsigned int slaves_responding; /**< Sum of responding slaves on all + Ethernet devices. */ + unsigned int al_states : 4; /**< Application-layer states of all slaves. + The states are coded in the lower 4 bits. + If a bit is set, it means that at least one + slave in the network is in the corresponding + state: + - Bit 0: \a INIT + - Bit 1: \a PREOP + - Bit 2: \a SAFEOP + - Bit 3: \a OP */ + unsigned int link_up : 1; /**< \a true, if at least one Ethernet link is + up. */ +} ec_master_state_t; + +/****************************************************************************/ + +/** Redundant link state. + * + * This is used for the output parameter of ecrt_master_link_state(). + * + * \see ecrt_master_link_state(). + */ +typedef struct { + unsigned int slaves_responding; /**< Sum of responding slaves on the given + link. */ + unsigned int al_states : 4; /**< Application-layer states of the slaves on + the given link. The states are coded in the + lower 4 bits. If a bit is set, it means + that at least one slave in the network is in + the corresponding state: + - Bit 0: \a INIT + - Bit 1: \a PREOP + - Bit 2: \a SAFEOP + - Bit 3: \a OP */ + unsigned int link_up : 1; /**< \a true, if the given Ethernet link is up. + */ +} ec_master_link_state_t; + +/****************************************************************************/ + +/** Slave configuration state. + * + * This is used as an output parameter of ecrt_slave_config_state(). + * + * \see ecrt_slave_config_state(). + */ +typedef struct { + unsigned int online : 1; /**< The slave is online. */ + unsigned int operational : 1; /**< The slave was brought into \a OP state + using the specified configuration. */ + unsigned int al_state : 4; /**< The application-layer state of the slave. + - 1: \a INIT + - 2: \a PREOP + - 4: \a SAFEOP + - 8: \a OP + + Note that each state is coded in a different + bit! */ +} ec_slave_config_state_t; + +/****************************************************************************/ + +/** Master information. + * + * This is used as an output parameter of ecrt_master(). + * + * \see ecrt_master(). + */ +typedef struct { + unsigned int slave_count; /**< Number of slaves in the network. */ + unsigned int link_up : 1; /**< \a true, if the network link is up. */ + uint8_t scan_busy; /**< \a true, while the master is scanning the network. + */ + uint64_t app_time; /**< Application time. */ +} ec_master_info_t; + +/****************************************************************************/ + +/** Master scan progress information. + * + * This is used as an output parameter of ecrt_master_scan_progress(). + * + * \see ecrt_master_scan_progress(). + */ +typedef struct { + unsigned int slave_count; /**< Number of slaves detected. */ + unsigned int scan_index; /**< Index of the slave that is currently + scanned. If it is less than the \a + slave_count, the network scan is in progress. + */ +} ec_master_scan_progress_t; + +/****************************************************************************/ + +/** EtherCAT slave port descriptor. + */ +typedef enum { + EC_PORT_NOT_IMPLEMENTED, /**< Port is not implemented. */ + EC_PORT_NOT_CONFIGURED, /**< Port is not configured. */ + EC_PORT_EBUS, /**< Port is an E-Bus. */ + EC_PORT_MII /**< Port is a MII. */ +} ec_slave_port_desc_t; + +/****************************************************************************/ + +/** EtherCAT slave port information. + */ +typedef struct { + uint8_t link_up; /**< Link detected. */ + uint8_t loop_closed; /**< Loop closed. */ + uint8_t signal_detected; /**< Detected signal on RX port. */ +} ec_slave_port_link_t; + +/****************************************************************************/ + +/** Slave information. + * + * This is used as an output parameter of ecrt_master_get_slave(). + * + * \see ecrt_master_get_slave(). + */ +typedef struct { + uint16_t position; /**< Offset of the slave in the ring. */ + uint32_t vendor_id; /**< Vendor-ID stored on the slave. */ + uint32_t product_code; /**< Product-Code stored on the slave. */ + uint32_t revision_number; /**< Revision-Number stored on the slave. */ + uint32_t serial_number; /**< Serial-Number stored on the slave. */ + uint16_t alias; /**< The slaves alias if not equal to 0. */ + int16_t current_on_ebus; /**< Used current in mA. */ + struct { + ec_slave_port_desc_t desc; /**< Physical port type. */ + ec_slave_port_link_t link; /**< Port link state. */ + uint32_t receive_time; /**< Receive time on DC transmission delay + measurement. */ + uint16_t next_slave; /**< Ring position of next DC slave on that + port. */ + uint32_t delay_to_next_dc; /**< Delay [ns] to next DC slave. */ + } ports[EC_MAX_PORTS]; /**< Port information. */ + uint8_t al_state; /**< Current state of the slave. */ + uint8_t error_flag; /**< Error flag for that slave. */ + uint8_t sync_count; /**< Number of sync managers. */ + uint16_t sdo_count; /**< Number of SDOs. */ + char name[EC_MAX_STRING_LENGTH]; /**< Name of the slave. */ +} ec_slave_info_t; + +/****************************************************************************/ + +/** Domain working counter interpretation. + * + * This is used in ec_domain_state_t. + */ +typedef enum { + EC_WC_ZERO = 0, /**< No registered process data were exchanged. */ + EC_WC_INCOMPLETE, /**< Some of the registered process data were + exchanged. */ + EC_WC_COMPLETE /**< All registered process data were exchanged. */ +} ec_wc_state_t; + +/****************************************************************************/ + +/** Domain state. + * + * This is used for the output parameter of ecrt_domain_state(). + */ +typedef struct { + unsigned int working_counter; /**< Value of the last working counter. */ + ec_wc_state_t wc_state; /**< Working counter interpretation. */ + unsigned int redundancy_active; /**< Redundant link is in use. */ +} ec_domain_state_t; + +/****************************************************************************/ + +/** Direction type for PDO assignment functions. + */ +typedef enum { + EC_DIR_INVALID, /**< Invalid direction. Do not use this value. */ + EC_DIR_OUTPUT, /**< Values written by the master. */ + EC_DIR_INPUT, /**< Values read by the master. */ + EC_DIR_COUNT /**< Number of directions. For internal use only. */ +} ec_direction_t; + +/****************************************************************************/ + +/** Watchdog mode for sync manager configuration. + * + * Used to specify, if a sync manager's watchdog is to be enabled. + */ +typedef enum { + EC_WD_DEFAULT, /**< Use the default setting of the sync manager. */ + EC_WD_ENABLE, /**< Enable the watchdog. */ + EC_WD_DISABLE, /**< Disable the watchdog. */ +} ec_watchdog_mode_t; + +/****************************************************************************/ + +/** PDO entry configuration information. + * + * This is the data type of the \a entries field in ec_pdo_info_t. + * + * \see ecrt_slave_config_pdos(). + */ +typedef struct { + uint16_t index; /**< PDO entry index. */ + uint8_t subindex; /**< PDO entry subindex. */ + uint8_t bit_length; /**< Size of the PDO entry in bit. */ +} ec_pdo_entry_info_t; + +/****************************************************************************/ + +/** PDO configuration information. + * + * This is the data type of the \a pdos field in ec_sync_info_t. + * + * \see ecrt_slave_config_pdos(). + */ +typedef struct { + uint16_t index; /**< PDO index. */ + unsigned int n_entries; /**< Number of PDO entries in \a entries to map. + Zero means, that the default mapping shall be + used (this can only be done if the slave is + present at configuration time). */ + ec_pdo_entry_info_t const *entries; /**< Array of PDO entries to map. Can + either be \a NULL, or must contain + at least \a n_entries values. */ +} ec_pdo_info_t; + +/****************************************************************************/ + +/** Sync manager configuration information. + * + * This can be use to configure multiple sync managers including the PDO + * assignment and PDO mapping. It is used as an input parameter type in + * ecrt_slave_config_pdos(). + */ +typedef struct { + uint8_t index; /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS for a valid sync manager, + but can also be \a 0xff to mark the end of the list. */ + ec_direction_t dir; /**< Sync manager direction. */ + unsigned int n_pdos; /**< Number of PDOs in \a pdos. */ + ec_pdo_info_t const *pdos; /**< Array with PDOs to assign. This must + contain at least \a n_pdos PDOs. */ + ec_watchdog_mode_t watchdog_mode; /**< Watchdog mode. */ +} ec_sync_info_t; + +/****************************************************************************/ + +/** List record type for PDO entry mass-registration. + * + * This type is used for the array parameter of the + * ecrt_domain_reg_pdo_entry_list() + */ +typedef struct { + uint16_t alias; /**< Slave alias address. */ + uint16_t position; /**< Slave position. */ + uint32_t vendor_id; /**< Slave vendor ID. */ + uint32_t product_code; /**< Slave product code. */ + uint16_t index; /**< PDO entry index. */ + uint8_t subindex; /**< PDO entry subindex. */ + unsigned int *offset; /**< Pointer to a variable to store the PDO entry's + (byte-)offset in the process data. */ + unsigned int *bit_position; /**< Pointer to a variable to store a bit + position (0-7) within the \a offset. Can be + NULL, in which case an error is raised if + the PDO entry does not byte-align. */ +} ec_pdo_entry_reg_t; + +/****************************************************************************/ + +/** Request state. + * + * This is used as return type for ecrt_sdo_request_state() and + * ecrt_voe_handler_state(). + */ +typedef enum { + EC_REQUEST_UNUSED, /**< Not requested. */ + EC_REQUEST_BUSY, /**< Request is being processed. */ + EC_REQUEST_SUCCESS, /**< Request was processed successfully. */ + EC_REQUEST_ERROR, /**< Request processing failed. */ +} ec_request_state_t; + +/****************************************************************************/ + +/** Application-layer state. + */ +typedef enum { + EC_AL_STATE_INIT = 1, /**< Init. */ + EC_AL_STATE_PREOP = 2, /**< Pre-operational. */ + EC_AL_STATE_SAFEOP = 4, /**< Safe-operational. */ + EC_AL_STATE_OP = 8, /**< Operational. */ +} ec_al_state_t; + +/***************************************************************************** + * Global functions + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Returns the version magic of the realtime interface. + * + * \apiusage{master_any,rt_safe} + * + * \return Value of ECRT_VERSION_MAGIC() at EtherCAT master compile time. + */ +EC_PUBLIC_API unsigned int ecrt_version_magic(void); + +/** Requests an EtherCAT master for realtime operation. + * + * Before an application can access an EtherCAT master, it has to reserve one + * for exclusive use. + * + * In userspace, this is a convenience function for ecrt_open_master() and + * ecrt_master_reserve(). + * + * This function has to be the first function an application has to call to + * use EtherCAT. The function takes the index of the master as its argument. + * The first master has index 0, the n-th master has index n - 1. The number + * of masters has to be specified when loading the master module. + * + * \apiusage{master_idle,blocking} + * + * \return Pointer to the reserved master, otherwise \a NULL. + */ +EC_PUBLIC_API ec_master_t *ecrt_request_master( + unsigned int master_index /**< Index of the master to request. */ + ); + +#ifndef __KERNEL__ + +/** Opens an EtherCAT master for userspace access. + * + * This function has to be the first function an application has to call to + * use EtherCAT. The function takes the index of the master as its argument. + * The first master has index 0, the n-th master has index n - 1. The number + * of masters has to be specified when loading the master module. + * + * For convenience, the function ecrt_request_master() can be used. + * + * \apiusage{master_idle,blocking} + * + * \return Pointer to the opened master, otherwise \a NULL. + */ +EC_PUBLIC_API ec_master_t *ecrt_open_master( + unsigned int master_index /**< Index of the master to request. */ + ); + +#endif // #ifndef __KERNEL__ + +/** Releases a requested EtherCAT master. + * + * After use, a master it has to be released to make it available for other + * applications. + * + * This method frees all created data structures. It should not be called in + * realtime context. + * + * If the master was activated, ecrt_master_deactivate() is called internally. + * + * \apiusage{master_any,blocking} + */ +EC_PUBLIC_API void ecrt_release_master( + ec_master_t *master /**< EtherCAT master */ + ); + +/***************************************************************************** + * Master methods + ****************************************************************************/ + +#ifndef __KERNEL__ + +/** Reserves an EtherCAT master for realtime operation. + * + * Before an application can use PDO/domain registration functions or SDO + * request functions on the master, it has to reserve one for exclusive use. + * + * \apiusage{master_idle,blocking} + * + * \return 0 in case of success, else < 0 + */ +EC_PUBLIC_API int ecrt_master_reserve( + ec_master_t *master /**< EtherCAT master */ + ); + +#endif // #ifndef __KERNEL__ + +#ifdef __KERNEL__ + +/** Sets the locking callbacks. + * + * For concurrent master access, i. e. if other instances than the application + * want to send and receive datagrams on the network, the application has to + * provide a callback mechanism. This method takes two function pointers as + * its parameters. Asynchronous master access (like EoE processing) is only + * possible if the callbacks have been set. + * + * The task of the send callback (\a send_cb) is to decide, if the network + * hardware is currently accessible and whether or not to call the + * ecrt_master_send_ext() method. + * + * The task of the receive callback (\a receive_cb) is to decide, if a call to + * ecrt_master_receive() is allowed and to execute it respectively. + * + * \apiusage{master_idle,blocking} + * + * \attention This method has to be called before ecrt_master_activate(). + */ +void ecrt_master_callbacks( + ec_master_t *master, /**< EtherCAT master */ + void (*send_cb)(void *), /**< Datagram sending callback. */ + void (*receive_cb)(void *), /**< Receive callback. */ + void *cb_data /**< Arbitrary pointer passed to the callback functions. + */ + ); + +#endif /* __KERNEL__ */ + +/** Creates a new process data domain. + * + * For process data exchange, at least one process data domain is needed. + * This method creates a new process data domain and returns a pointer to the + * new domain object. This object can be used for registering PDOs and + * exchanging them in cyclic operation. + * + * This method allocates memory and should be called in non-realtime context + * before ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return Pointer to the new domain on success, else NULL. + */ +EC_PUBLIC_API ec_domain_t *ecrt_master_create_domain( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Obtains a slave configuration. + * + * Creates a slave configuration object for the given \a alias and \a position + * tuple and returns it. If a configuration with the same \a alias and \a + * position already exists, it will be re-used. In the latter case, the given + * vendor ID and product code are compared to the stored ones. On mismatch, an + * error message is raised and the function returns \a NULL. + * + * Slaves are addressed with the \a alias and \a position parameters. + * - If \a alias is zero, \a position is interpreted as the desired slave's + * ring position. + * - If \a alias is non-zero, it matches a slave with the given alias. In this + * case, \a position is interpreted as ring offset, starting from the + * aliased slave, so a position of zero means the aliased slave itself and a + * positive value matches the n-th slave behind the aliased one. + * + * If the slave with the given address is found during the configuration, + * its vendor ID and product code are matched against the given value. On + * mismatch, the slave is not configured and an error message is raised. + * + * If different slave configurations are pointing to the same slave during + * configuration, a warning is raised and only the first configuration is + * applied. + * + * This method allocates memory and should be called in non-realtime context + * before ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval >0 Pointer to the slave configuration structure. + * \retval NULL in the error case. + */ +EC_PUBLIC_API ec_slave_config_t *ecrt_master_slave_config( + ec_master_t *master, /**< EtherCAT master */ + uint16_t alias, /**< Slave alias. */ + uint16_t position, /**< Slave position. */ + uint32_t vendor_id, /**< Expected vendor ID. */ + uint32_t product_code /**< Expected product code. */ + ); + +/** Selects the reference clock for distributed clocks. + * + * If this method is not called for a certain master, or if the slave + * configuration pointer is NULL, then the first slave with DC functionality + * will provide the reference clock. + * + * \apiusage{master_idle,blocking} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_select_reference_clock( + ec_master_t *master, /**< EtherCAT master. */ + ec_slave_config_t *sc /**< Slave config of the slave to use as the + * reference slave (or NULL). */ + ); + +/** Obtains master information. + * + * No memory is allocated on the heap in this function. + * + * \apiusage{master_any,rt_safe} + * + * \attention The pointer to this structure must point to a valid variable. + * + * \return 0 in case of success, else < 0 + */ +EC_PUBLIC_API int ecrt_master( + ec_master_t *master, /**< EtherCAT master */ + ec_master_info_t *master_info /**< Structure that will output the + information */ + ); + +/** Obtains network scan progress information. + * + * No memory is allocated on the heap in this function. + * + * \apiusage{master_any,rt_safe} + * + * \attention The pointer to this structure must point to a valid variable. + * + * \return 0 in case of success, else < 0 + */ +EC_PUBLIC_API int ecrt_master_scan_progress( + ec_master_t *master, /**< EtherCAT master */ + ec_master_scan_progress_t *progress /**< Structure that will output + the progress information. */ + ); + +/** Obtains slave information. + * + * Tries to find the slave with the given ring position. The obtained + * information is stored in a structure. No memory is allocated on the heap in + * this function. + * + * \apiusage{master_any,blocking} + * + * \attention The pointer to this structure must point to a valid variable. + * + * \return 0 in case of success, else < 0 + */ +EC_PUBLIC_API int ecrt_master_get_slave( + ec_master_t *master, /**< EtherCAT master */ + uint16_t slave_position, /**< Slave position. */ + ec_slave_info_t *slave_info /**< Structure that will output the + information */ + ); + +#ifndef __KERNEL__ + +/** Returns the proposed configuration of a slave's sync manager. + * + * Fills a given ec_sync_info_t structure with the attributes of a sync + * manager. The \a pdos field of the return value is left empty. Use + * ecrt_master_get_pdo() to get the PDO information. + * + * \apiusage{master_any,blocking} + * + * \return zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_master_get_sync_manager( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint8_t sync_index, /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + ec_sync_info_t *sync /**< Pointer to output structure. */ + ); + +/** Returns information about a currently assigned PDO. + * + * Fills a given ec_pdo_info_t structure with the attributes of a currently + * assigned PDO of the given sync manager. The \a entries field of the return + * value is left empty. Use ecrt_master_get_pdo_entry() to get the PDO + * entry information. + * + * \apiusage{master_any,blocking} + * + * \retval zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_master_get_pdo( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint8_t sync_index, /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + uint16_t pos, /**< Zero-based PDO position. */ + ec_pdo_info_t *pdo /**< Pointer to output structure. */ + ); + +/** Returns information about a currently mapped PDO entry. + * + * Fills a given ec_pdo_entry_info_t structure with the attributes of a + * currently mapped PDO entry of the given PDO. + * + * \apiusage{master_any,blocking} + * + * \retval zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_master_get_pdo_entry( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint8_t sync_index, /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + uint16_t pdo_pos, /**< Zero-based PDO position. */ + uint16_t entry_pos, /**< Zero-based PDO entry position. */ + ec_pdo_entry_info_t *entry /**< Pointer to output structure. */ + ); + +#endif /* #ifndef __KERNEL__ */ + +/** Executes an SDO download request to write data to a slave. + * + * This request is processed by the master state machine. This method blocks, + * until the request has been processed and may not be called in realtime + * context. + * + * \apiusage{master_any,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_sdo_download( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint16_t index, /**< Index of the SDO. */ + uint8_t subindex, /**< Subindex of the SDO. */ + const uint8_t *data, /**< Data buffer to download. */ + size_t data_size, /**< Size of the data buffer. */ + uint32_t *abort_code /**< Abort code of the SDO download. */ + ); + +/** Executes an SDO download request to write data to a slave via complete + * access. + * + * This request is processed by the master state machine. This method blocks, + * until the request has been processed and may not be called in realtime + * context. + * + * \apiusage{master_any,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_sdo_download_complete( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint16_t index, /**< Index of the SDO. */ + const uint8_t *data, /**< Data buffer to download. */ + size_t data_size, /**< Size of the data buffer. */ + uint32_t *abort_code /**< Abort code of the SDO download. */ + ); + +/** Executes an SDO upload request to read data from a slave. + * + * This request is processed by the master state machine. This method blocks, + * until the request has been processed and may not be called in realtime + * context. + * + * \apiusage{master_any,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_sdo_upload( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint16_t index, /**< Index of the SDO. */ + uint8_t subindex, /**< Subindex of the SDO. */ + uint8_t *target, /**< Target buffer for the upload. */ + size_t target_size, /**< Size of the target buffer. */ + size_t *result_size, /**< Uploaded data size. */ + uint32_t *abort_code /**< Abort code of the SDO upload. */ + ); + +/** Executes an SoE write request. + * + * Starts writing an IDN and blocks until the request was processed, or an + * error occurred. + * + * \apiusage{master_any,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_write_idn( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint8_t drive_no, /**< Drive number. */ + uint16_t idn, /**< SoE IDN (see ecrt_slave_config_idn()). */ + const uint8_t *data, /**< Pointer to data to write. */ + size_t data_size, /**< Size of data to write. */ + uint16_t *error_code /**< Pointer to variable, where an SoE error code + can be stored. */ + ); + +/** Executes an SoE read request. + * + * Starts reading an IDN and blocks until the request was processed, or an + * error occurred. + * + * \apiusage{master_any,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_read_idn( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint8_t drive_no, /**< Drive number. */ + uint16_t idn, /**< SoE IDN (see ecrt_slave_config_idn()). */ + uint8_t *target, /**< Pointer to memory where the read data can be + stored. */ + size_t target_size, /**< Size of the memory \a target points to. */ + size_t *result_size, /**< Actual size of the received data. */ + uint16_t *error_code /**< Pointer to variable, where an SoE error code + can be stored. */ + ); + +/** Finishes the configuration phase and prepares for cyclic operation. + * + * This function tells the master that the configuration phase is finished and + * the realtime operation will begin. The function allocates internal memory + * for the domains and calculates the logical FMMU addresses for domain + * members. It tells the master state machine that the configuration is + * now to be applied to the network. + * + * \apiusage{master_idle,blocking} + * + * \attention After this function has been called, the realtime application is + * in charge of cyclically calling ecrt_master_send() and + * ecrt_master_receive() to ensure network communication. Before calling this + * function, the master thread is responsible for that, so these functions may + * not be called! The method itself allocates memory and should not be called + * in realtime context. + * + * \return 0 in case of success, else < 0 + */ +EC_PUBLIC_API int ecrt_master_activate( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Deactivates the master. + * + * Removes the master configuration. All objects created by + * ecrt_master_create_domain(), ecrt_master_slave_config(), ecrt_domain_data() + * ecrt_slave_config_create_sdo_request() and + * ecrt_slave_config_create_voe_handler() are freed, so pointers to them + * become invalid. + * + * \apiusage{master_op,blocking} + * + * This method should not be called in realtime context. + * \return 0 on success, otherwise negative error code. + * \retval 0 Success. + * \retval -EINVAL Master has not been activated before. + */ +EC_PUBLIC_API int ecrt_master_deactivate( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Set interval between calls to ecrt_master_send(). + * + * This information helps the master to decide, how much data can be appended + * to a frame by the master state machine. When the master is configured with + * --enable-hrtimers, this is used to calculate the scheduling of the master + * thread. + * + * \apiusage{master_idle,blocking} + * + * \retval 0 on success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_set_send_interval( + ec_master_t *master, /**< EtherCAT master. */ + size_t send_interval /**< Send interval in us */ + ); + +/** Sends all datagrams in the queue. + * + * This method takes all datagrams, that have been queued for transmission, + * puts them into frames, and passes them to the Ethernet device for sending. + * + * Has to be called cyclically by the application after ecrt_master_activate() + * has returned. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_send( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Fetches received frames from the hardware and processes the datagrams. + * + * Queries the network device for received frames by calling the interrupt + * service routine. Extracts received datagrams and dispatches the results to + * the datagram objects in the queue. Received datagrams, and the ones that + * timed out, will be marked, and dequeued. + * + * Has to be called cyclically by the realtime application after + * ecrt_master_activate() has returned. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_receive( + ec_master_t *master /**< EtherCAT master. */ + ); + +#ifdef __KERNEL__ +/** Sends non-application datagrams. + * + * This method has to be called in the send callback function passed via + * ecrt_master_callbacks() to allow the sending of non-application datagrams. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + * \retval -EAGAIN Lock could not be acquired, try again later. + */ +int ecrt_master_send_ext( + ec_master_t *master /**< EtherCAT master. */ + ); +#endif + +/** Reads the current master state. + * + * Stores the master state information in the given \a state structure. + * + * This method returns a global state. For the link-specific states in a + * redundant network topology, use the ecrt_master_link_state() method. + * + * \apiusage{master_any,rt_safe} + * + * \return Zero on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_state( + const ec_master_t *master, /**< EtherCAT master. */ + ec_master_state_t *state /**< Structure to store the information. */ + ); + +/** Reads the current state of a redundant link. + * + * Stores the link state information in the given \a state structure. + * + * \apiusage{master_any,rt_safe} + * + * \return Zero on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_link_state( + const ec_master_t *master, /**< EtherCAT master. */ + unsigned int dev_idx, /**< Index of the device (0 = main device, 1 = + first backup device, ...). */ + ec_master_link_state_t *state /**< Structure to store the information. + */ + ); + +/** Sets the application time. + * + * The master has to know the application's time when operating slaves with + * distributed clocks. The time is not incremented by the master itself, so + * this method has to be called cyclically. + * + * \attention The time passed to this method is used to calculate the phase of + * the slaves' SYNC0/1 interrupts. It should be called constantly at the same + * point of the realtime cycle. So it is recommended to call it at the start + * of the calculations to avoid deviancies due to changing execution times. + * Avoid calling this method before the realtime cycle is established. + * + * The time is used when setting the slaves' System Time Offset and + * Cyclic Operation Start Time registers and when synchronizing the + * DC reference clock to the application time via + * ecrt_master_sync_reference_clock(). + * + * The time is defined as nanoseconds from 2000-01-01 00:00. Converting an + * epoch time can be done with the EC_TIMEVAL2NANO() macro, but is not + * necessary, since the absolute value is not of any interest. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_application_time( + ec_master_t *master, /**< EtherCAT master. */ + uint64_t app_time /**< Application time. */ + ); + +/** Queues the DC reference clock drift compensation datagram for sending. + * + * The reference clock will by synchronized to the application time provided + * by the last call off ecrt_master_application_time(). + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + * \retval 0 Success. + * \retval -ENXIO No reference clock found. + */ +EC_PUBLIC_API int ecrt_master_sync_reference_clock( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Queues the DC reference clock drift compensation datagram for sending. + * + * The reference clock will by synchronized to the time passed in the + * sync_time parameter. + * + * Has to be called by the application after ecrt_master_activate() + * has returned. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + * \retval 0 Success. + * \retval -ENXIO No reference clock found. + */ +EC_PUBLIC_API int ecrt_master_sync_reference_clock_to( + ec_master_t *master, /**< EtherCAT master. */ + uint64_t sync_time /**< Sync reference clock to this time. */ + ); + +/** Queues the DC clock drift compensation datagram for sending. + * + * All slave clocks synchronized to the reference clock. + * + * Has to be called by the application after ecrt_master_activate() + * has returned. + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval 0 Success. + * \retval -ENXIO No reference clock found. + */ +EC_PUBLIC_API int ecrt_master_sync_slave_clocks( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Get the lower 32 bit of the reference clock system time. + * + * This method can be used to synchronize the master to the reference clock. + * + * The reference clock system time is queried via the + * ecrt_master_sync_slave_clocks() method, that reads the system time of the + * reference clock and writes it to the slave clocks (so be sure to call it + * cyclically to get valid data). + * + * \attention The returned time is the system time of the reference clock + * minus the transmission delay of the reference clock. + * + * Calling this method makes only sense in realtime context (after master + * activation), when the ecrt_master_sync_slave_clocks() method is called + * cyclically. + * + * \apiusage{master_op,rt_safe} + * + * \retval 0 success, system time was written into \a time. + * \retval -ENXIO No reference clock found. + * \retval -EIO Slave synchronization datagram was not received. + */ +EC_PUBLIC_API int ecrt_master_reference_clock_time( + const ec_master_t *master, /**< EtherCAT master. */ + uint32_t *time /**< Pointer to store the queried system time. */ + ); + +/** Queues the DC synchrony monitoring datagram for sending. + * + * The datagram broadcast-reads all "System time difference" registers (\a + * 0x092c) to get an upper estimation of the DC synchrony. The result can be + * checked with the ecrt_master_sync_monitor_process() method. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise a negative error code. + */ +EC_PUBLIC_API int ecrt_master_sync_monitor_queue( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Processes the DC synchrony monitoring datagram. + * + * If the sync monitoring datagram was sent before with + * ecrt_master_sync_monitor_queue(), the result can be queried with this + * method. + * + * \apiusage{master_op,rt_safe} + * + * \return Upper estimation of the maximum time difference in ns, -1 on error. + * \retval (uint32_t)-1 Error. + */ +EC_PUBLIC_API uint32_t ecrt_master_sync_monitor_process( + const ec_master_t *master /**< EtherCAT master. */ + ); + +/** Retry configuring slaves. + * + * Via this method, the application can tell the master to bring all slaves to + * OP state. In general, this is not necessary, because it is automatically + * done by the master. But with special slaves, that can be reconfigured by + * the vendor during runtime, it can be useful. + * + * Calling this method only makes sense in realtime context (after + * activation), because slaves will not be configured before. + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_reset( + ec_master_t *master /**< EtherCAT master. */ + ); + +/***************************************************************************** + * Slave configuration methods + ****************************************************************************/ + +/** Configure a sync manager. + * + * Sets the direction of a sync manager. This overrides the direction bits + * from the default control register from SII. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_slave_config_sync_manager( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t sync_index, /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + ec_direction_t direction, /**< Input/Output. */ + ec_watchdog_mode_t watchdog_mode /** Watchdog mode. */ + ); + +/** Configure a slave's watchdog times. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_slave_config_watchdog( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t watchdog_divider, /**< Number of 40 ns intervals (register + 0x0400). Used as a base unit for all + slave watchdogs^. If set to zero, the + value is not written, so the default is + used. */ + uint16_t watchdog_intervals /**< Number of base intervals for sync + manager watchdog (register 0x0420). If + set to zero, the value is not written, + so the default is used. */ + ); + +/** Add a PDO to a sync manager's PDO assignment. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \see ecrt_slave_config_pdos() + * \return zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_slave_config_pdo_assign_add( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t sync_index, /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + uint16_t index /**< Index of the PDO to assign. */ + ); + +/** Clear a sync manager's PDO assignment. + * + * This can be called before assigning PDOs via + * ecrt_slave_config_pdo_assign_add(), to clear the default assignment of a + * sync manager. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \see ecrt_slave_config_pdos() + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_slave_config_pdo_assign_clear( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t sync_index /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + ); + +/** Add a PDO entry to the given PDO's mapping. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \see ecrt_slave_config_pdos() + * \return zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_slave_config_pdo_mapping_add( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t pdo_index, /**< Index of the PDO. */ + uint16_t entry_index, /**< Index of the PDO entry to add to the PDO's + mapping. */ + uint8_t entry_subindex, /**< Subindex of the PDO entry to add to the + PDO's mapping. */ + uint8_t entry_bit_length /**< Size of the PDO entry in bit. */ + ); + +/** Clear the mapping of a given PDO. + * + * This can be called before mapping PDO entries via + * ecrt_slave_config_pdo_mapping_add(), to clear the default mapping. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \see ecrt_slave_config_pdos() + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_slave_config_pdo_mapping_clear( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t pdo_index /**< Index of the PDO. */ + ); + +/** Specify a complete PDO configuration. + * + * This function is a convenience wrapper for the functions + * ecrt_slave_config_sync_manager(), ecrt_slave_config_pdo_assign_clear(), + * ecrt_slave_config_pdo_assign_add(), ecrt_slave_config_pdo_mapping_clear() + * and ecrt_slave_config_pdo_mapping_add(), that are better suitable for + * automatic code generation. + * + * The following example shows, how to specify a complete configuration, + * including the PDO mappings. With this information, the master is able to + * reserve the complete process data, even if the slave is not present at + * configuration time: + * + * \code + * ec_pdo_entry_info_t el3162_channel1[] = { + * {0x3101, 1, 8}, // status + * {0x3101, 2, 16} // value + * }; + * + * ec_pdo_entry_info_t el3162_channel2[] = { + * {0x3102, 1, 8}, // status + * {0x3102, 2, 16} // value + * }; + * + * ec_pdo_info_t el3162_pdos[] = { + * {0x1A00, 2, el3162_channel1}, + * {0x1A01, 2, el3162_channel2} + * }; + * + * ec_sync_info_t el3162_syncs[] = { + * {2, EC_DIR_OUTPUT}, + * {3, EC_DIR_INPUT, 2, el3162_pdos}, + * {0xff} + * }; + * + * if (ecrt_slave_config_pdos(sc_ana_in, EC_END, el3162_syncs)) { + * // handle error + * } + * \endcode + * + * The next example shows, how to configure the PDO assignment only. The + * entries for each assigned PDO are taken from the PDO's default mapping. + * Please note, that PDO entry registration will fail, if the PDO + * configuration is left empty and the slave is offline. + * + * \code + * ec_pdo_info_t pdos[] = { + * {0x1600}, // Channel 1 + * {0x1601} // Channel 2 + * }; + * + * ec_sync_info_t syncs[] = { + * {3, EC_DIR_INPUT, 2, pdos}, + * }; + * + * if (ecrt_slave_config_pdos(slave_config_ana_in, 1, syncs)) { + * // handle error + * } + * \endcode + * + * Processing of \a syncs will stop, if + * - the number of processed items reaches \a n_syncs, or + * - the \a index member of an ec_sync_info_t item is 0xff. In this case, + * \a n_syncs should set to a number greater than the number of list items; + * using EC_END is recommended. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_slave_config_pdos( + ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int n_syncs, /**< Number of sync manager configurations in + \a syncs. */ + const ec_sync_info_t syncs[] /**< Array of sync manager + configurations. */ + ); + +/** Registers a PDO entry for process data exchange in a domain. + * + * Searches the assigned PDOs for the given PDO entry. An error is raised, if + * the given entry is not mapped. Otherwise, the corresponding sync manager + * and FMMU configurations are provided for slave configuration and the + * respective sync manager's assigned PDOs are appended to the given domain, + * if not already done. The offset of the requested PDO entry's data inside + * the domain's process data is returned. Optionally, the PDO entry bit + * position (0-7) can be retrieved via the \a bit_position output parameter. + * This pointer may be \a NULL, in this case an error is raised if the PDO + * entry does not byte-align. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval >=0 Success: Offset of the PDO entry's process data. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_reg_pdo_entry( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t entry_index, /**< Index of the PDO entry to register. */ + uint8_t entry_subindex, /**< Subindex of the PDO entry to register. */ + ec_domain_t *domain, /**< Domain. */ + unsigned int *bit_position /**< Optional address if bit addressing + is desired */ + ); + +/** Registers a PDO entry using its position. + * + * Similar to ecrt_slave_config_reg_pdo_entry(), but not using PDO indices but + * offsets in the PDO mapping, because PDO entry indices may not be unique + * inside a slave's PDO mapping. An error is raised, if + * one of the given positions is out of range. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval >=0 Success: Offset of the PDO entry's process data. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_reg_pdo_entry_pos( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t sync_index, /**< Sync manager index. */ + unsigned int pdo_pos, /**< Position of the PDO inside the SM. */ + unsigned int entry_pos, /**< Position of the entry inside the PDO. */ + ec_domain_t *domain, /**< Domain. */ + unsigned int *bit_position /**< Optional address if bit addressing + is desired */ + ); + +/** Configure distributed clocks. + * + * Sets the AssignActivate word and the cycle and shift times for the sync + * signals. + * + * The AssignActivate word is vendor-specific and can be taken from the XML + * device description file (Device -> Dc -> AssignActivate). Set this to zero, + * if the slave shall be operated without distributed clocks (default). + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \attention The \a sync1_shift time is ignored. + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_slave_config_dc( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t assign_activate, /**< AssignActivate word. */ + uint32_t sync0_cycle, /**< SYNC0 cycle time [ns]. */ + int32_t sync0_shift, /**< SYNC0 shift time [ns]. */ + uint32_t sync1_cycle, /**< SYNC1 cycle time [ns]. */ + int32_t sync1_shift /**< SYNC1 shift time [ns]. */ + ); + +/** Add an SDO configuration. + * + * An SDO configuration is stored in the slave configuration object and is + * downloaded to the slave whenever the slave is being configured by the + * master. This usually happens once on master activation, but can be repeated + * subsequently, for example after the slave's power supply failed. + * + * \attention The SDOs for PDO assignment (\p 0x1C10 - \p 0x1C2F) and PDO + * mapping (\p 0x1600 - \p 0x17FF and \p 0x1A00 - \p 0x1BFF) should not be + * configured with this function, because they are part of the slave + * configuration done by the master. Please use ecrt_slave_config_pdos() and + * friends instead. + * + * This is the generic function for adding an SDO configuration. Please note + * that the this function does not do any endianness correction. If + * datatype-specific functions are needed (that automatically correct the + * endianness), have a look at ecrt_slave_config_sdo8(), + * ecrt_slave_config_sdo16() and ecrt_slave_config_sdo32(). + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_sdo( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t index, /**< Index of the SDO to configure. */ + uint8_t subindex, /**< Subindex of the SDO to configure. */ + const uint8_t *data, /**< Pointer to the data. */ + size_t size /**< Size of the \a data. */ + ); + +/** Add a configuration value for an 8-bit SDO. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \see ecrt_slave_config_sdo(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_sdo8( + ec_slave_config_t *sc, /**< Slave configuration */ + uint16_t sdo_index, /**< Index of the SDO to configure. */ + uint8_t sdo_subindex, /**< Subindex of the SDO to configure. */ + uint8_t value /**< Value to set. */ + ); + +/** Add a configuration value for a 16-bit SDO. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \see ecrt_slave_config_sdo(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_sdo16( + ec_slave_config_t *sc, /**< Slave configuration */ + uint16_t sdo_index, /**< Index of the SDO to configure. */ + uint8_t sdo_subindex, /**< Subindex of the SDO to configure. */ + uint16_t value /**< Value to set. */ + ); + +/** Add a configuration value for a 32-bit SDO. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \see ecrt_slave_config_sdo(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_sdo32( + ec_slave_config_t *sc, /**< Slave configuration */ + uint16_t sdo_index, /**< Index of the SDO to configure. */ + uint8_t sdo_subindex, /**< Subindex of the SDO to configure. */ + uint32_t value /**< Value to set. */ + ); + +/** Add configuration data for a complete SDO. + * + * The SDO data are transferred via CompleteAccess. Data for the first + * subindex (0) have to be included. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \see ecrt_slave_config_sdo(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_complete_sdo( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t index, /**< Index of the SDO to configure. */ + const uint8_t *data, /**< Pointer to the data. */ + size_t size /**< Size of the \a data. */ + ); + +/** Set the size of the CoE emergency ring buffer. + * + * The initial size is zero, so all messages will be dropped. This method can + * be called even after master activation, but it will clear the ring buffer! + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return 0 on success, or negative error code. + */ +EC_PUBLIC_API int ecrt_slave_config_emerg_size( + ec_slave_config_t *sc, /**< Slave configuration. */ + size_t elements /**< Number of records of the CoE emergency ring. */ + ); + +/** Read and remove one record from the CoE emergency ring buffer. + * + * A record consists of 8 bytes: + * + * Byte 0-1: Error code (little endian) + * Byte 2: Error register + * Byte 3-7: Data + * + * Calling this method makes only sense in realtime context (after master + * activation). + * + * \return 0 on success (record popped), or negative error code (i. e. + * -ENOENT, if ring is empty). + * + * \apiusage{master_op,any_context} + */ +EC_PUBLIC_API int ecrt_slave_config_emerg_pop( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t *target /**< Pointer to target memory (at least + EC_COE_EMERGENCY_MSG_SIZE bytes). */ + ); + +/** Clears CoE emergency ring buffer and the overrun counter. + * + * Calling this method makes only sense in realtime context (after master + * activation). + * + * \apiusage{master_op,any_context} + * + * \return 0 on success, or negative error code. + * + */ +EC_PUBLIC_API int ecrt_slave_config_emerg_clear( + ec_slave_config_t *sc /**< Slave configuration. */ + ); + +/** Read the number of CoE emergency overruns. + * + * The overrun counter will be incremented when a CoE emergency message could + * not be stored in the ring buffer and had to be dropped. Call + * ecrt_slave_config_emerg_clear() to reset the counter. + * + * Calling this method makes only sense in realtime context (after master + * activation). + * + * \apiusage{master_op,any_context} + * + * \return Number of overruns since last clear, or negative error code. + * + */ +EC_PUBLIC_API int ecrt_slave_config_emerg_overruns( + const ec_slave_config_t *sc /**< Slave configuration. */ + ); + +/** Create an SDO request to exchange SDOs during realtime operation. + * + * The created SDO request object is freed automatically when the master is + * released. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return New SDO request, or NULL on error. + */ +EC_PUBLIC_API ec_sdo_request_t *ecrt_slave_config_create_sdo_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t index, /**< SDO index. */ + uint8_t subindex, /**< SDO subindex. */ + size_t size /**< Data size to reserve. */ + ); + +/** Create an SoE request to exchange SoE IDNs during realtime operation. + * + * The created SoE request object is freed automatically when the master is + * released. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return New SoE request, or NULL on error. + */ +EC_PUBLIC_API ec_soe_request_t *ecrt_slave_config_create_soe_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t drive_no, /**< Drive number. */ + uint16_t idn, /**< Sercos ID-Number. */ + size_t size /**< Data size to reserve. */ + ); + +/** Create an VoE handler to exchange vendor-specific data during realtime + * operation. + * + * The number of VoE handlers per slave configuration is not limited, but + * usually it is enough to create one for sending and one for receiving, if + * both can be done simultaneously. + * + * The created VoE handler object is freed automatically when the master is + * released. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return New VoE handler, or NULL on error. + */ +EC_PUBLIC_API ec_voe_handler_t *ecrt_slave_config_create_voe_handler( + ec_slave_config_t *sc, /**< Slave configuration. */ + size_t size /**< Data size to reserve. */ + ); + +/** Create a register request to exchange EtherCAT register contents during + * realtime operation. + * + * This interface should not be used to take over master functionality, + * instead it is intended for debugging and monitoring reasons. + * + * The created register request object is freed automatically when the master + * is released. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return New register request, or NULL on error. + */ +EC_PUBLIC_API ec_reg_request_t *ecrt_slave_config_create_reg_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + size_t size /**< Data size to reserve. */ + ); + +/** Outputs the state of the slave configuration. + * + * Stores the state information in the given \a state structure. The state + * information is updated by the master state machine, so it may take a few + * cycles, until it changes. + * + * \attention If the state of process data exchange shall be monitored in + * realtime, ecrt_domain_state() should be used. + * + * \apiusage{master_op,rt_safe} + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_state( + const ec_slave_config_t *sc, /**< Slave configuration */ + ec_slave_config_state_t *state /**< State object to write to. */ + ); + +/** Add an SoE IDN configuration. + * + * A configuration for a Sercos-over-EtherCAT IDN is stored in the slave + * configuration object and is written to the slave whenever the slave is + * being configured by the master. This usually happens once on master + * activation, but can be repeated subsequently, for example after the slave's + * power supply failed. + * + * The \a idn parameter can be separated into several sections: + * - Bit 15: Standard data (0) or Product data (1) + * - Bit 14 - 12: Parameter set (0 - 7) + * - Bit 11 - 0: Data block number (0 - 4095) + * + * Please note that the this function does not do any endianness correction. + * Multi-byte data have to be passed in EtherCAT endianness (little-endian). + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_idn( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t drive_no, /**< Drive number. */ + uint16_t idn, /**< SoE IDN. */ + ec_al_state_t state, /**< AL state in which to write the IDN (PREOP or + SAFEOP). */ + const uint8_t *data, /**< Pointer to the data. */ + size_t size /**< Size of the \a data. */ + ); + +/** Adds a feature flag to a slave configuration. + * + * Feature flags are a generic way to configure slave-specific behavior. + * + * Multiple calls with the same slave configuration and key will overwrite the + * configuration. + * + * The following flags may be available: + * - AssignToPdi: Zero (default) keeps the slave information interface (SII) + * assigned to EtherCAT (except during transition to PREOP). Non-zero + * assigns the SII to the slave controller side before going to PREOP and + * leaves it there until a write command happens. + * - WaitBeforeSAFEOPms: Number of milliseconds to wait before commanding the + * transition from PREOP to SAFEOP. This can be used as a workaround for + * slaves that need a little time to initialize. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_flag( + ec_slave_config_t *sc, /**< Slave configuration. */ + const char *key, /**< Key as null-terminated ASCII string. */ + int32_t value /**< Value to store. */ + ); + +/** Sets the link/MAC address for Ethernet-over-EtherCAT (EoE) operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The MAC address is stored in the slave configuration object and will be + * written to the slave during the configuration process. + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_mac_address( + ec_slave_config_t *sc, /**< Slave configuration. */ + const unsigned char *mac_address /**< MAC address. */ + ); + +/** Sets the IP address for Ethernet-over-EtherCAT (EoE) operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The IP address is stored in the slave configuration object and will be + * written to the slave during the configuration process. + * + * The IP address is passed by-value as a `struct in_addr`. This structure + * contains the 32-bit IPv4 address in network byte order (big endian). + * + * A string-represented IPv4 address can be converted to a `struct in_addr` + * for example via the POSIX function `inet_pton()` (see man 3 inet_pton): + * + * \code{.c} + * #include + * struct in_addr addr; + * if (inet_aton("192.168.0.1", &addr) == 0) { + * fprintf(stderr, "Failed to convert IP address.\n"); + * return -1; + * } + * if (ecrt_slave_config_eoe_ip_address(sc, addr)) { + * fprintf(stderr, "Failed to set IP address.\n"); + * return -1; + * } + * \endcode + * + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_ip_address( + ec_slave_config_t *sc, /**< Slave configuration. */ + struct in_addr ip_address /**< IPv4 address. */ + ); + +/** Sets the subnet mask for Ethernet-over-EtherCAT (EoE) operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The subnet mask is stored in the slave configuration object and will be + * written to the slave during the configuration process. + * + * The subnet mask is passed by-value as a `struct in_addr`. This structure + * contains the 32-bit mask in network byte order (big endian). + * + * See ecrt_slave_config_eoe_ip_address() on how to convert string-coded masks + * to `struct in_addr`. + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_subnet_mask( + ec_slave_config_t *sc, /**< Slave configuration. */ + struct in_addr subnet_mask /**< IPv4 subnet mask. */ + ); + +/** Sets the gateway address for Ethernet-over-EtherCAT (EoE) operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The gateway address is stored in the slave configuration object and will be + * written to the slave during the configuration process. + * + * The address is passed by-value as a `struct in_addr`. This structure + * contains the 32-bit IPv4 address in network byte order (big endian). + * + * See ecrt_slave_config_eoe_ip_address() on how to convert string-coded IPv4 + * addresses to `struct in_addr`. + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_default_gateway( + ec_slave_config_t *sc, /**< Slave configuration. */ + struct in_addr gateway_address /**< Gateway's IPv4 address. */ + ); + +/** Sets the IPv4 address of the DNS server for Ethernet-over-EtherCAT (EoE) + * operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The DNS server address is stored in the slave configuration object and will + * be written to the slave during the configuration process. + * + * The address is passed by-value as a `struct in_addr`. This structure + * contains the 32-bit IPv4 address in network byte order (big endian). + * + * See ecrt_slave_config_eoe_ip_address() on how to convert string-coded IPv4 + * addresses to `struct in_addr`. + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_dns_address( + ec_slave_config_t *sc, /**< Slave configuration. */ + struct in_addr dns_address /**< IPv4 address of the DNS server. */ + ); + +/** Sets the host name for Ethernet-over-EtherCAT (EoE) operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The host name is stored in the slave configuration object and will + * be written to the slave during the configuration process. + * + * The maximum size of the host name is 32 bytes (including the zero + * terminator). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_hostname( + ec_slave_config_t *sc, /**< Slave configuration. */ + const char *name /**< Zero-terminated host name. */ + ); + +/** Sets the application-layer state transition timeout in ms. + * + * Change the maximum allowed time for a slave to make an application-layer + * state transition for the given state transition (for example from PREOP to + * SAFEOP). The default values are defined in ETG.2000. + * + * A timeout value of zero ms will restore the default value. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_state_timeout( + ec_slave_config_t *sc, /**< Slave configuration. */ + ec_al_state_t from_state, /**< Initial state. */ + ec_al_state_t to_state, /**< Target state. */ + unsigned int timeout_ms /**< Timeout in [ms]. */ + ); + +/***************************************************************************** + * Domain methods + ****************************************************************************/ + +/** Registers a bunch of PDO entries for a domain. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \see ecrt_slave_config_reg_pdo_entry() + * + * \attention The registration array has to be terminated with an empty + * structure, or one with the \a index field set to zero! + * + * \apiusage{master_idle,blocking} + * + * \return 0 on success, else non-zero. + */ +EC_PUBLIC_API int ecrt_domain_reg_pdo_entry_list( + ec_domain_t *domain, /**< Domain. */ + const ec_pdo_entry_reg_t *pdo_entry_regs /**< Array of PDO + registrations. */ + ); + +/** Returns the current size of the domain's process data. + * + * The domain size is calculated after master activation. + * + * \apiusage{master_op,rt_safe} + * + * \return Size of the process data image, or a negative error code. + */ +EC_PUBLIC_API size_t ecrt_domain_size( + const ec_domain_t *domain /**< Domain. */ + ); + +#ifdef __KERNEL__ + +/** Provide external memory to store the domain's process data. + * + * Call this after all PDO entries have been registered and before activating + * the master. + * + * The size of the allocated memory must be at least ecrt_domain_size(), after + * all PDO entries have been registered. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + */ +void ecrt_domain_external_memory( + ec_domain_t *domain, /**< Domain. */ + uint8_t *memory /**< Address of the memory to store the process + data in. */ + ); + +#endif /* __KERNEL__ */ + +/** Returns the domain's process data. + * + * - In kernel context: If external memory was provided with + * ecrt_domain_external_memory(), the returned pointer will contain the + * address of that memory. Otherwise it will point to the internally allocated + * memory. In the latter case, this method may not be called before + * ecrt_master_activate(). + * + * - In userspace context: This method has to be called after + * ecrt_master_activate() to get the mapped domain process data memory. + * + * \apiusage{master_op,rt_safe} + * + * \return Pointer to the process data memory. + */ +EC_PUBLIC_API uint8_t *ecrt_domain_data( + const ec_domain_t *domain /**< Domain. */ + ); + +/** Determines the states of the domain's datagrams. + * + * Evaluates the working counters of the received datagrams and outputs + * statistics, if necessary. This must be called after ecrt_master_receive() + * is expected to receive the domain datagrams in order to make + * ecrt_domain_state() return the result of the last process data exchange. + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_domain_process( + ec_domain_t *domain /**< Domain. */ + ); + +/** (Re-)queues all domain datagrams in the master's datagram queue. + * + * Call this function to mark the domain's datagrams for exchanging at the + * next call of ecrt_master_send(). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_domain_queue( + ec_domain_t *domain /**< Domain. */ + ); + +/** Reads the state of a domain. + * + * Stores the domain state in the given \a state structure. + * + * Using this method, the process data exchange can be monitored in realtime. + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_domain_state( + const ec_domain_t *domain, /**< Domain. */ + ec_domain_state_t *state /**< Pointer to a state object to store the + information. */ + ); + +/***************************************************************************** + * SDO request methods. + ****************************************************************************/ + +/** Set the SDO index and subindex. + * + * \attention If the SDO index and/or subindex is changed while + * ecrt_sdo_request_state() returns EC_REQUEST_BUSY, this may lead to + * unexpected results. + * + * This method is meant to be called in realtime context (after master + * activation). To initialize the SDO request, the index and subindex can be + * set via ecrt_slave_config_create_sdo_request(). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_sdo_request_index( + ec_sdo_request_t *req, /**< SDO request. */ + uint16_t index, /**< SDO index. */ + uint8_t subindex /**< SDO subindex. */ + ); + +/** Set the timeout for an SDO request. + * + * If the request cannot be processed in the specified time, if will be marked + * as failed. + * + * The timeout is permanently stored in the request object and is valid until + * the next call of this method. + * + * The timeout should be defined in non-realtime context, but can also be + * changed afterwards. + * + * \apiusage{master_any,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_sdo_request_timeout( + ec_sdo_request_t *req, /**< SDO request. */ + uint32_t timeout /**< Timeout in milliseconds. Zero means no + timeout. */ + ); + +/** Access to the SDO request's data. + * + * This function returns a pointer to the request's internal SDO data memory. + * + * - After a read operation was successful, integer data can be evaluated + * using the EC_READ_*() macros as usual. Example: + * \code + * uint16_t value = EC_READ_U16(ecrt_sdo_request_data(sdo))); + * \endcode + * - If a write operation shall be triggered, the data have to be written to + * the internal memory. Use the EC_WRITE_*() macros, if you are writing + * integer data. Be sure, that the data fit into the memory. The memory size + * is a parameter of ecrt_slave_config_create_sdo_request(). + * \code + * EC_WRITE_U16(ecrt_sdo_request_data(sdo), 0xFFFF); + * \endcode + * + * \attention The return value can be invalid during a read operation, because + * the internal SDO data memory could be re-allocated if the read SDO data do + * not fit inside. + * + * This method is meant to be called in realtime context (after master + * activation), but can also be used to initialize data before. + * + * \apiusage{master_any,rt_safe} + * + * \return Pointer to the internal SDO data memory. + * + */ +EC_PUBLIC_API uint8_t *ecrt_sdo_request_data( + const ec_sdo_request_t *req /**< SDO request. */ + ); + +/** Returns the current SDO data size. + * + * When the SDO request is created, the data size is set to the size of the + * reserved memory. After a read operation the size is set to the size of the + * read data. The size is not modified in any other situation. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_any,rt_safe} + * + * \return SDO data size in bytes. + * + */ +EC_PUBLIC_API size_t ecrt_sdo_request_data_size( + const ec_sdo_request_t *req /**< SDO request. */ + ); + +/** Get the current state of the SDO request. + * + * The user-space implementation fetches incoming data and stores the received + * data size in the request object, so the request is not const. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return Request state. + * + */ +EC_PUBLIC_API ec_request_state_t ecrt_sdo_request_state( +#ifdef __KERNEL__ + const +#endif + ec_sdo_request_t *req /**< SDO request. */ + ); + +/** Schedule an SDO write operation. + * + * \attention This method may not be called while ecrt_sdo_request_state() + * returns EC_REQUEST_BUSY. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval -EINVAL Invalid input data, e.g. data size == 0. + * \retval -ENOBUFS Reserved memory in ecrt_slave_config_create_sdo_request() + * too small. + */ +EC_PUBLIC_API int ecrt_sdo_request_write( + ec_sdo_request_t *req /**< SDO request. */ + ); + +/** Schedule an SDO read operation. + * + * \attention This method may not be called while ecrt_sdo_request_state() + * returns EC_REQUEST_BUSY. + * + * \attention After calling this function, the return value of + * ecrt_sdo_request_data() must be considered as invalid while + * ecrt_sdo_request_state() returns EC_REQUEST_BUSY. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_sdo_request_read( + ec_sdo_request_t *req /**< SDO request. */ + ); + +/***************************************************************************** + * SoE request methods. + ****************************************************************************/ + +/** Set the request's drive and Sercos ID numbers. + * + * \attention If the drive number and/or IDN is changed while + * ecrt_soe_request_state() returns EC_REQUEST_BUSY, this may lead to + * unexpected results. + * + * This method is meant to be called in realtime context (after master + * activation). To initialize the SoE request, the drive_no and IDN can be + * set via ecrt_slave_config_create_soe_request(). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_soe_request_idn( + ec_soe_request_t *req, /**< IDN request. */ + uint8_t drive_no, /**< SDO index. */ + uint16_t idn /**< SoE IDN. */ + ); + +/** Set the timeout for an SoE request. + * + * If the request cannot be processed in the specified time, if will be marked + * as failed. + * + * The timeout is permanently stored in the request object and is valid until + * the next call of this method. + * + * The timeout should be defined in non-realtime context, but can also be + * changed afterwards. + * + * \apiusage{master_any,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_soe_request_timeout( + ec_soe_request_t *req, /**< SoE request. */ + uint32_t timeout /**< Timeout in milliseconds. Zero means no + timeout. */ + ); + +/** Access to the SoE request's data. + * + * This function returns a pointer to the request's internal IDN data memory. + * + * - After a read operation was successful, integer data can be evaluated + * using the EC_READ_*() macros as usual. Example: + * \code + * uint16_t value = EC_READ_U16(ecrt_soe_request_data(idn_req))); + * \endcode + * - If a write operation shall be triggered, the data have to be written to + * the internal memory. Use the EC_WRITE_*() macros, if you are writing + * integer data. Be sure, that the data fit into the memory. The memory size + * is a parameter of ecrt_slave_config_create_soe_request(). + * \code + * EC_WRITE_U16(ecrt_soe_request_data(idn_req), 0xFFFF); + * \endcode + * + * \attention The return value can be invalidated during a read operation, + * because the internal IDN data memory could be re-allocated if the read IDN + * data do not fit inside. + * + * This method is meant to be called in realtime context (after master + * activation), but can also be used to initialize data before. + * + * \apiusage{master_any,rt_safe} + * + * \return Pointer to the internal IDN data memory. + * + */ +EC_PUBLIC_API uint8_t *ecrt_soe_request_data( + const ec_soe_request_t *req /**< SoE request. */ + ); + +/** Returns the current IDN data size. + * + * When the SoE request is created, the data size is set to the size of the + * reserved memory. After a read operation the size is set to the size of the + * read data. The size is not modified in any other situation. + * + * \apiusage{master_any,rt_safe} + * + * \return IDN data size in bytes. + */ +EC_PUBLIC_API size_t ecrt_soe_request_data_size( + const ec_soe_request_t *req /**< SoE request. */ + ); + +/** Get the current state of the SoE request. + * + * \return Request state. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * In the user-space implementation, the method fetches the size of the + * incoming data, so the request object is not const. + * + * \apiusage{master_op,rt_safe} + */ +EC_PUBLIC_API ec_request_state_t ecrt_soe_request_state( +#ifdef __KERNEL__ + const +#endif + ec_soe_request_t *req /**< SoE request. */ + ); + +/** Schedule an SoE IDN write operation. + * + * \attention This method may not be called while ecrt_soe_request_state() + * returns EC_REQUEST_BUSY. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval -EINVAL Invalid input data, e.g. data size == 0. + * \retval -ENOBUFS Reserved memory in ecrt_slave_config_create_soe_request() + * too small. + */ +EC_PUBLIC_API int ecrt_soe_request_write( + ec_soe_request_t *req /**< SoE request. */ + ); + +/** Schedule an SoE IDN read operation. + * + * \attention This method may not be called while ecrt_soe_request_state() + * returns EC_REQUEST_BUSY. + * + * \attention After calling this function, the return value of + * ecrt_soe_request_data() must be considered as invalid while + * ecrt_soe_request_state() returns EC_REQUEST_BUSY. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_soe_request_read( + ec_soe_request_t *req /**< SoE request. */ + ); + +/***************************************************************************** + * VoE handler methods. + ****************************************************************************/ + +/** Sets the VoE header for future send operations. + * + * A VoE message shall contain a 4-byte vendor ID, followed by a 2-byte vendor + * type at as header. These numbers can be set with this function. The values + * are valid and will be used for future send operations until the next call + * of this method. + * + * This method is meant to be called in non-realtime context (before master + * activation) to initialize the header data, but it is also safe to + * change the header later on in realtime context. + * + * \apiusage{master_any,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_voe_handler_send_header( + ec_voe_handler_t *voe, /**< VoE handler. */ + uint32_t vendor_id, /**< Vendor ID. */ + uint16_t vendor_type /**< Vendor-specific type. */ + ); + +/** Reads the header data of a received VoE message. + * + * This method can be used to get the received VoE header information after a + * read operation has succeeded. + * + * The header information is stored at the memory given by the pointer + * parameters. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_voe_handler_received_header( + const ec_voe_handler_t *voe, /**< VoE handler. */ + uint32_t *vendor_id, /**< Vendor ID. */ + uint16_t *vendor_type /**< Vendor-specific type. */ + ); + +/** Access to the VoE handler's data. + * + * This function returns a pointer to the VoE handler's internal memory, that + * points to the actual VoE data right after the VoE header (see + * ecrt_voe_handler_send_header()). + * + * - After a read operation was successful, the memory contains the received + * data. The size of the received data can be determined via + * ecrt_voe_handler_data_size(). + * - Before a write operation is triggered, the data have to be written to the + * internal memory. Be sure, that the data fit into the memory. The reserved + * memory size is a parameter of ecrt_slave_config_create_voe_handler(). + * + * \attention The returned pointer is not necessarily persistent: After a read + * operation, the internal memory may have been reallocated. This can be + * avoided by reserving enough memory via the \a size parameter of + * ecrt_slave_config_create_voe_handler(). + * + * \apiusage{master_any,rt_safe} + * + * \return Pointer to the internal memory. + */ +EC_PUBLIC_API uint8_t *ecrt_voe_handler_data( + const ec_voe_handler_t *voe /**< VoE handler. */ + ); + +/** Returns the current data size. + * + * The data size is the size of the VoE data without the header (see + * ecrt_voe_handler_send_header()). + * + * When the VoE handler is created, the data size is set to the size of the + * reserved memory. At a write operation, the data size is set to the number + * of bytes to write. After a read operation the size is set to the size of + * the read data. The size is not modified in any other situation. + * + * \apiusage{master_any,rt_safe} + * + * \return Data size in bytes. + */ +EC_PUBLIC_API size_t ecrt_voe_handler_data_size( + const ec_voe_handler_t *voe /**< VoE handler. */ + ); + +/** Start a VoE write operation. + * + * After this function has been called, the ecrt_voe_handler_execute() method + * must be called in every realtime cycle as long as it returns + * EC_REQUEST_BUSY. No other operation may be started while the handler is + * busy. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval -ENOBUFS Reserved memory in ecrt_slave_config_create_voe_handler + * too small. + */ +EC_PUBLIC_API int ecrt_voe_handler_write( + ec_voe_handler_t *voe, /**< VoE handler. */ + size_t size /**< Number of bytes to write (without the VoE header). */ + ); + +/** Start a VoE read operation. + * + * After this function has been called, the ecrt_voe_handler_execute() method + * must be called in every realtime cycle as long as it returns + * EC_REQUEST_BUSY. No other operation may be started while the handler is + * busy. + * + * The state machine queries the slave's send mailbox for new data to be send + * to the master. If no data appear within the EC_VOE_RESPONSE_TIMEOUT + * (defined in master/voe_handler.c), the operation fails. + * + * On success, the size of the read data can be determined via + * ecrt_voe_handler_data_size(), while the VoE header of the received data + * can be retrieved with ecrt_voe_handler_received_header(). + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_voe_handler_read( + ec_voe_handler_t *voe /**< VoE handler. */ + ); + +/** Start a VoE read operation without querying the sync manager status. + * + * After this function has been called, the ecrt_voe_handler_execute() method + * must be called in every realtime cycle as long as it returns + * EC_REQUEST_BUSY. No other operation may be started while the handler is + * busy. + * + * The state machine queries the slave by sending an empty mailbox. The slave + * fills its data to the master in this mailbox. If no data appear within the + * EC_VOE_RESPONSE_TIMEOUT (defined in master/voe_handler.c), the operation + * fails. + * + * On success, the size of the read data can be determined via + * ecrt_voe_handler_data_size(), while the VoE header of the received data + * can be retrieved with ecrt_voe_handler_received_header(). + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_voe_handler_read_nosync( + ec_voe_handler_t *voe /**< VoE handler. */ + ); + +/** Execute the handler. + * + * This method executes the VoE handler. It has to be called in every realtime + * cycle as long as it returns EC_REQUEST_BUSY. + * + * \return Handler state. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + */ +EC_PUBLIC_API ec_request_state_t ecrt_voe_handler_execute( + ec_voe_handler_t *voe /**< VoE handler. */ + ); + +/***************************************************************************** + * Register request methods. + ****************************************************************************/ + +/** Access to the register request's data. + * + * This function returns a pointer to the request's internal memory. + * + * - After a read operation was successful, integer data can be evaluated + * using the EC_READ_*() macros as usual. Example: + * \code + * uint16_t value = EC_READ_U16(ecrt_reg_request_data(reg_request))); + * \endcode + * - If a write operation shall be triggered, the data have to be written to + * the internal memory. Use the EC_WRITE_*() macros, if you are writing + * integer data. Be sure, that the data fit into the memory. The memory size + * is a parameter of ecrt_slave_config_create_reg_request(). + * \code + * EC_WRITE_U16(ecrt_reg_request_data(reg_request), 0xFFFF); + * \endcode + * + * This method is meant to be called in realtime context (after master + * activation), but can also be used to initialize data before. + * + * \apiusage{master_any,rt_safe} + * + * \return Pointer to the internal memory. + * + */ +EC_PUBLIC_API uint8_t *ecrt_reg_request_data( + const ec_reg_request_t *req /**< Register request. */ + ); + +/** Get the current state of the register request. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return Request state. + * + */ +EC_PUBLIC_API ec_request_state_t ecrt_reg_request_state( + const ec_reg_request_t *req /**< Register request. */ + ); + +/** Schedule an register write operation. + * + * \attention This method may not be called while ecrt_reg_request_state() + * returns EC_REQUEST_BUSY. + * + * \attention The \a size parameter is truncated to the size given at request + * creation. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval -ENOBUFS Reserved memory in ecrt_slave_config_create_reg_request + * too small. + */ +EC_PUBLIC_API int ecrt_reg_request_write( + ec_reg_request_t *req, /**< Register request. */ + uint16_t address, /**< Register address. */ + size_t size /**< Size to write. */ + ); + +/** Schedule a register read operation. + * + * \attention This method may not be called while ecrt_reg_request_state() + * returns EC_REQUEST_BUSY. + * + * \attention The \a size parameter is truncated to the size given at request + * creation. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval -ENOBUFS Reserved memory in ecrt_slave_config_create_reg_request + * too small. + */ +EC_PUBLIC_API int ecrt_reg_request_read( + ec_reg_request_t *req, /**< Register request. */ + uint16_t address, /**< Register address. */ + size_t size /**< Size to write. */ + ); + +/***************************************************************************** + * Bitwise read/write macros + ****************************************************************************/ + +/** Read a certain bit of an EtherCAT data byte. + * + * \param DATA EtherCAT data pointer + * \param POS bit position + */ +#define EC_READ_BIT(DATA, POS) ((*((uint8_t *) (DATA)) >> (POS)) & 0x01) + +/** Write a certain bit of an EtherCAT data byte. + * + * \param DATA EtherCAT data pointer + * \param POS bit position + * \param VAL new bit value + */ +#define EC_WRITE_BIT(DATA, POS, VAL) \ + do { \ + if (VAL) *((uint8_t *) (DATA)) |= (1 << (POS)); \ + else *((uint8_t *) (DATA)) &= ~(1 << (POS)); \ + } while (0) + +/***************************************************************************** + * Byte-swapping functions for user space + ****************************************************************************/ + +#ifndef __KERNEL__ + +#if __BYTE_ORDER == __LITTLE_ENDIAN + +#define le16_to_cpu(x) x +#define le32_to_cpu(x) x +#define le64_to_cpu(x) x + +#define cpu_to_le16(x) x +#define cpu_to_le32(x) x +#define cpu_to_le64(x) x + +#elif __BYTE_ORDER == __BIG_ENDIAN + +#define swap16(x) \ + ((uint16_t)( \ + (((uint16_t)(x) & 0x00ffU) << 8) | \ + (((uint16_t)(x) & 0xff00U) >> 8) )) +#define swap32(x) \ + ((uint32_t)( \ + (((uint32_t)(x) & 0x000000ffUL) << 24) | \ + (((uint32_t)(x) & 0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & 0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & 0xff000000UL) >> 24) )) +#define swap64(x) \ + ((uint64_t)( \ + (((uint64_t)(x) & 0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & 0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & 0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & 0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & 0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & 0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & 0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & 0xff00000000000000ULL) >> 56) )) + +#define le16_to_cpu(x) swap16(x) +#define le32_to_cpu(x) swap32(x) +#define le64_to_cpu(x) swap64(x) + +#define cpu_to_le16(x) swap16(x) +#define cpu_to_le32(x) swap32(x) +#define cpu_to_le64(x) swap64(x) + +#endif + +#define le16_to_cpup(x) le16_to_cpu(*((uint16_t *)(x))) +#define le32_to_cpup(x) le32_to_cpu(*((uint32_t *)(x))) +#define le64_to_cpup(x) le64_to_cpu(*((uint64_t *)(x))) + +#endif /* ifndef __KERNEL__ */ + +/***************************************************************************** + * Read macros + ****************************************************************************/ + +/** Read an 8-bit unsigned value from EtherCAT data. + * + * \return EtherCAT data value + */ +#define EC_READ_U8(DATA) \ + ((uint8_t) *((uint8_t *) (DATA))) + +/** Read an 8-bit signed value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_S8(DATA) \ + ((int8_t) *((uint8_t *) (DATA))) + +/** Read a 16-bit unsigned value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_U16(DATA) \ + ((uint16_t) le16_to_cpup((void *) (DATA))) + +/** Read a 16-bit signed value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_S16(DATA) \ + ((int16_t) le16_to_cpup((void *) (DATA))) + +/** Read a 32-bit unsigned value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_U32(DATA) \ + ((uint32_t) le32_to_cpup((void *) (DATA))) + +/** Read a 32-bit signed value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_S32(DATA) \ + ((int32_t) le32_to_cpup((void *) (DATA))) + +/** Read a 64-bit unsigned value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_U64(DATA) \ + ((uint64_t) le64_to_cpup((void *) (DATA))) + +/** Read a 64-bit signed value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_S64(DATA) \ + ((int64_t) le64_to_cpup((void *) (DATA))) + +/***************************************************************************** + * Floating-point read functions and macros (userspace only) + ****************************************************************************/ + +#ifndef __KERNEL__ + +/** Read a 32-bit floating-point value from EtherCAT data. + * + * \apiusage{master_any,rt_safe} + * + * \param data EtherCAT data pointer + * \return EtherCAT data value + */ +EC_PUBLIC_API float ecrt_read_real(const void *data); + +/** Read a 32-bit floating-point value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_REAL(DATA) ecrt_read_real(DATA) + +/** Read a 64-bit floating-point value from EtherCAT data. + * + * \apiusage{master_any,rt_safe} + * + * \param data EtherCAT data pointer + * \return EtherCAT data value + */ +EC_PUBLIC_API double ecrt_read_lreal(const void *data); + +/** Read a 64-bit floating-point value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_LREAL(DATA) ecrt_read_lreal(DATA) + +#endif // ifndef __KERNEL__ + +/***************************************************************************** + * Write macros + ****************************************************************************/ + +/** Write an 8-bit unsigned value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_U8(DATA, VAL) \ + do { \ + *((uint8_t *)(DATA)) = ((uint8_t) (VAL)); \ + } while (0) + +/** Write an 8-bit signed value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_S8(DATA, VAL) EC_WRITE_U8(DATA, VAL) + +/** Write a 16-bit unsigned value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_U16(DATA, VAL) \ + do { \ + *((uint16_t *) (DATA)) = cpu_to_le16((uint16_t) (VAL)); \ + } while (0) + +/** Write a 16-bit signed value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_S16(DATA, VAL) EC_WRITE_U16(DATA, VAL) + +/** Write a 32-bit unsigned value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_U32(DATA, VAL) \ + do { \ + *((uint32_t *) (DATA)) = cpu_to_le32((uint32_t) (VAL)); \ + } while (0) + +/** Write a 32-bit signed value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_S32(DATA, VAL) EC_WRITE_U32(DATA, VAL) + +/** Write a 64-bit unsigned value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_U64(DATA, VAL) \ + do { \ + *((uint64_t *) (DATA)) = cpu_to_le64((uint64_t) (VAL)); \ + } while (0) + +/** Write a 64-bit signed value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_S64(DATA, VAL) EC_WRITE_U64(DATA, VAL) + +/***************************************************************************** + * Floating-point write functions and macros (userspace only) + ****************************************************************************/ + +#ifndef __KERNEL__ + +/** Write a 32-bit floating-point value to EtherCAT data. + * + * \apiusage{master_any,rt_safe} + * + * \param data EtherCAT data pointer + * \param value new value + */ +EC_PUBLIC_API void ecrt_write_real(void *data, float value); + +/** Write a 32-bit floating-point value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_REAL(DATA, VAL) ecrt_write_real(DATA, VAL) + +/** Write a 64-bit floating-point value to EtherCAT data. + * + * \apiusage{master_any,rt_safe} + * + * \param data EtherCAT data pointer + * \param value new value + */ +EC_PUBLIC_API void ecrt_write_lreal(void *data, double value); + +/** Write a 64-bit floating-point value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_LREAL(DATA, VAL) ecrt_write_lreal(DATA, VAL) + +#endif // ifndef __KERNEL__ + +/****************************************************************************/ + +#ifdef __cplusplus +} +#endif + +/****************************************************************************/ + +/** @} */ + +#endif diff --git a/ubuntu/igh-ecat/include/ectty.h b/ubuntu/igh-ecat/include/ectty.h new file mode 100644 index 00000000000000..3178d3ce9ba9f4 --- /dev/null +++ b/ubuntu/igh-ecat/include/ectty.h @@ -0,0 +1,106 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT master userspace library. + * + * The IgH EtherCAT master userspace library is free software; you can + * redistribute it and/or modify it under the terms of the GNU Lesser General + * Public License as published by the Free Software Foundation; version 2.1 + * of the License. + * + * The IgH EtherCAT master userspace library is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with the IgH EtherCAT master userspace library. If not, see + * . + * + ****************************************************************************/ + +/** \file + * + * EtherCAT virtual TTY interface. + * + * \defgroup TTYInterface EtherCAT Virtual TTY Interface + * + * @{ + */ + +/****************************************************************************/ + +#ifndef __ECTTY_H__ +#define __ECTTY_H__ + +#include + +/***************************************************************************** + * Data types + ****************************************************************************/ + +struct ec_tty; +typedef struct ec_tty ec_tty_t; /**< \see ec_tty */ + +/** Operations on the virtual TTY interface. + */ +typedef struct { + int (*cflag_changed)(void *, tcflag_t); /**< Called when the serial + * settings shall be changed. The + * \a cflag argument contains the + * new settings. */ +} ec_tty_operations_t; + +/***************************************************************************** + * Global functions + ****************************************************************************/ + +/** Create a virtual TTY interface. + * + * \param ops Set of callbacks. + * \param cb_data Arbitrary data, that is passed to any callback. + * + * \return Pointer to the interface object, otherwise an ERR_PTR value. + */ +ec_tty_t *ectty_create( + const ec_tty_operations_t *ops, + void *cb_data + ); + +/***************************************************************************** + * TTY interface methods + ****************************************************************************/ + +/** Releases a virtual TTY interface. + */ +void ectty_free( + ec_tty_t *tty /**< TTY interface. */ + ); + +/** Reads data to send from the TTY interface. + * + * If there are data to send, they are copied into the \a buffer. At maximum, + * \a size bytes are copied. The actual number of bytes copied is returned. + * + * \return Number of bytes copied. + */ +unsigned int ectty_tx_data( + ec_tty_t *tty, /**< TTY interface. */ + uint8_t *buffer, /**< Buffer for data to transmit. */ + size_t size /**< Available space in \a buffer. */ + ); + +/** Pushes received data to the TTY interface. + */ +void ectty_rx_data( + ec_tty_t *tty, /**< TTY interface. */ + const uint8_t *buffer, /**< Buffer with received data. */ + size_t size /**< Number of bytes in \a buffer. */ + ); + +/****************************************************************************/ + +/** @} */ + +#endif diff --git a/ubuntu/igh-ecat/master/Kbuild.in b/ubuntu/igh-ecat/master/Kbuild.in new file mode 100644 index 00000000000000..afba220236e8f3 --- /dev/null +++ b/ubuntu/igh-ecat/master/Kbuild.in @@ -0,0 +1,112 @@ +#----------------------------------------------------------------------------- +# +# Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH +# +# This file is part of the IgH EtherCAT Master. +# +# The IgH EtherCAT Master is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License version 2, as +# published by the Free Software Foundation. +# +# The IgH EtherCAT Master is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General +# Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with the IgH EtherCAT Master; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# --- +# +# vi: syntax=make +# +#----------------------------------------------------------------------------- + +src := @abs_srcdir@ +ccflags-y := -I@abs_top_builddir@ + +obj-m := ec_master.o + +ec_master-objs := \ + cdev.o \ + coe_emerg_ring.o \ + datagram.o \ + datagram_pair.o \ + device.o \ + domain.o \ + flag.o \ + fmmu_config.o \ + foe_request.o \ + fsm_change.o \ + fsm_coe.o \ + fsm_foe.o \ + fsm_master.o \ + fsm_pdo.o \ + fsm_pdo_entry.o \ + fsm_sii.o \ + fsm_slave.o \ + fsm_slave_config.o \ + fsm_slave_scan.o \ + fsm_soe.o \ + ioctl.o \ + mailbox.o \ + master.o \ + module.o \ + pdo.o \ + pdo_entry.o \ + pdo_list.o \ + reg_request.o \ + sdo.o \ + sdo_entry.o \ + sdo_request.o \ + slave.o \ + slave_config.o \ + soe_errors.o \ + soe_request.o \ + sync.o \ + sync_config.o \ + voe_handler.o + +ifeq (@ENABLE_EOE@,1) +ec_master-objs += eoe_request.o ethernet.o fsm_eoe.o +endif + +ifeq (@ENABLE_DEBUG_IF@,1) +ec_master-objs += debug.o +endif + +ifeq (@ENABLE_RTDM@,1) + +ifeq (@ENABLE_XENOMAI_V3@, 1) +ec_master-objs += rtdm_xenomai_v3.o +else +ec_master-objs += rtdm.o +endif + +ifeq (@ENABLE_XENOMAI@, 1) +CFLAGS_rtdm.o := @XENOMAI_RTDM_CFLAGS@ +CFLAGS_rtdm-ioctl.o := @XENOMAI_RTDM_CFLAGS@ +endif + +ifeq (@ENABLE_RTAI@, 1) +CFLAGS_rtdm.o := @RTAI_KERNEL_CFLAGS@ +CFLAGS_rtdm-ioctl.o := @RTAI_KERNEL_CFLAGS@ +endif + +ec_master-objs += rtdm-ioctl.o +CFLAGS_rtdm-ioctl.o += -DEC_IOCTL_RTDM + +endif # ENABLE_RTDM + +REV := $(shell if test -s $(src)/../revision; then \ + cat $(src)/../revision; \ + else \ + git -C $(src)/.. describe 2>/dev/null || echo "unknown"; \ + fi) + +CFLAGS_module.o := -DREV=$(REV) + +KBUILD_CFLAGS += -Wmaybe-uninitialized + +#----------------------------------------------------------------------------- diff --git a/ubuntu/igh-ecat/master/Makefile b/ubuntu/igh-ecat/master/Makefile new file mode 100644 index 00000000000000..8aef742ebb2f74 --- /dev/null +++ b/ubuntu/igh-ecat/master/Makefile @@ -0,0 +1,47 @@ +ccflags-y := -I$(src)/../ \ + -Wmaybe-uninitialized + +obj-$(CONFIG_IGH_ECAT) += ec_master.o + +ec_master-$(CONFIG_IGH_ECAT) := \ + cdev.o \ + coe_emerg_ring.o \ + datagram.o \ + datagram_pair.o \ + device.o \ + domain.o \ + flag.o \ + fmmu_config.o \ + foe_request.o \ + fsm_change.o \ + fsm_coe.o \ + fsm_foe.o \ + fsm_master.o \ + fsm_pdo.o \ + fsm_pdo_entry.o \ + fsm_sii.o \ + fsm_slave.o \ + fsm_slave_config.o \ + fsm_slave_scan.o \ + fsm_soe.o \ + ioctl.o \ + mailbox.o \ + master.o \ + module.o \ + pdo.o \ + pdo_entry.o \ + pdo_list.o \ + reg_request.o \ + sdo.o \ + sdo_entry.o \ + sdo_request.o \ + slave.o \ + slave_config.o \ + soe_errors.o \ + soe_request.o \ + sync.o \ + sync_config.o \ + voe_handler.o + +ec_master-$(CONFIG_IGH_ECAT_ENABLE_EOE) += eoe_request.o ethernet.o fsm_eoe.o + diff --git a/ubuntu/igh-ecat/master/Makefile.am b/ubuntu/igh-ecat/master/Makefile.am new file mode 100644 index 00000000000000..1a0ef30a70b025 --- /dev/null +++ b/ubuntu/igh-ecat/master/Makefile.am @@ -0,0 +1,76 @@ +#----------------------------------------------------------------------------- +# +# Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH +# +# This file is part of the IgH EtherCAT Master. +# +# The IgH EtherCAT Master is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License version 2, as +# published by the Free Software Foundation. +# +# The IgH EtherCAT Master is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General +# Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with the IgH EtherCAT Master; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +#----------------------------------------------------------------------------- + +include $(top_srcdir)/Makefile.kbuild + +# using HEADERS to enable tags target +noinst_HEADERS = \ + cdev.c cdev.h \ + coe_emerg_ring.c coe_emerg_ring.h \ + datagram.c datagram.h \ + datagram_pair.c datagram_pair.h \ + debug.c debug.h \ + device.c device.h \ + domain.c domain.h \ + doxygen.c \ + eoe_request.c eoe_request.h \ + ethernet.c ethernet.h \ + flag.c flag.h \ + fmmu_config.c fmmu_config.h \ + foe.h \ + foe_request.c foe_request.h \ + fsm_change.c fsm_change.h \ + fsm_coe.c fsm_coe.h \ + fsm_eoe.c fsm_eoe.h \ + fsm_foe.c fsm_foe.h \ + fsm_master.c fsm_master.h \ + fsm_pdo.c fsm_pdo.h \ + fsm_pdo_entry.c fsm_pdo_entry.h \ + fsm_sii.c fsm_sii.h \ + fsm_slave.c fsm_slave.h \ + fsm_slave_config.c fsm_slave_config.h \ + fsm_slave_scan.c fsm_slave_scan.h \ + fsm_soe.c fsm_soe.h \ + globals.h \ + ioctl.c ioctl.h \ + mailbox.c mailbox.h \ + master.c master.h \ + module.c \ + pdo.c pdo.h \ + pdo_entry.c pdo_entry.h \ + pdo_list.c pdo_list.h \ + reg_request.c reg_request.h \ + rtdm-ioctl.c \ + rtdm.c rtdm.h \ + rtdm_details.h \ + rtdm_xenomai_v3.c \ + sdo.c sdo.h \ + sdo_entry.c sdo_entry.h \ + sdo_request.c sdo_request.h \ + slave.c slave.h \ + slave_config.c slave_config.h \ + soe_errors.c \ + soe_request.c soe_request.h \ + sync.c sync.h \ + sync_config.c sync_config.h \ + voe_handler.c voe_handler.h + +#----------------------------------------------------------------------------- diff --git a/ubuntu/igh-ecat/master/api_usage_notes.md b/ubuntu/igh-ecat/master/api_usage_notes.md new file mode 100644 index 00000000000000..1880866d6772d9 --- /dev/null +++ b/ubuntu/igh-ecat/master/api_usage_notes.md @@ -0,0 +1,51 @@ +Notes regaring API Usage {#apiusage} +======================== + +There are some restrictions on the +[Application Interface](@ref ApplicationInterface) with respect to the state of +the master instance and the calling context, which are explained in the +following. + +## Rules of Thumb + +All configuration (`ecrt_slave_config_*()`) has to be done in Linux process +context. They can be blocking, so take care when holding locks. After +ecrt_master_activate() ing the master, your application must not alter the +slave configuration. Instead, update process data using ecrt_domain_queue() +and ecrt_domain_process() or use the asynchronous interface like +ecrt_sdo_request_read(). Don't forget to ecrt_master_receive() and +ecrt_master_send(). These functions can be called from non-process context +too, like Xenomai/RTAI applications or custom kernel modules. + +## Master Phase + +The first distinction of cases is whether ecrt_master_activate() has been +called or not. Before ecrt_master_activate() (or after +ecrt_master_deactivate()), the master is in idle phase. Sending and receiving +EtherCAT frames will be done by the master itself, the application (e. g. you) +can store slave configurations for later use. After ecrt_master_activate(), +the master switches into operation mode. The application is now in charge of +steering the communication. Process data can be exchanged under real time +constraints. Altering the slave configuration is not possible anymore. + +| Tag | Description | +|---------------|---------------------------------------------------------------------------------------| +| `master_op` | Master must be in operation phase, so after `ecrt_master_activate()` has been called. | +| `master_idle` | Master must be in idle phase, so before `ecrt_master_activate()` has been called. | +| `master_any` | Master can be in idle or operation phase. | + +## Allowed Context + +The second distinction of cases is the calling context, which means how the +application is run. Most of the functions of the +[Application Interface](@ref ApplicationInterface) have to acquire locks or +allocate memory, so they are potentially sleeping. They are tagged as +`blocking`. Sleeping is not allowed in all contexts, for instance when using +Xenomai/RTAI or a kernel timer. Only a very limited set of functions can be +called from any context, marked as `rt_safe`. They do not allocate memory and +will not block. + +| Tag | Description | +|------------|-----------------------------------------------------------------------------------------------| +| `rt_safe` | Realtime context (RT userspace, atomic/softirq context in kernel, Xenomai/RTAI RT task) safe. | +| `blocking` | Linux process context only (userspace or kernel), might block. | diff --git a/ubuntu/igh-ecat/master/cdev.c b/ubuntu/igh-ecat/master/cdev.c new file mode 100644 index 00000000000000..eb95bfe94372b3 --- /dev/null +++ b/ubuntu/igh-ecat/master/cdev.c @@ -0,0 +1,281 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2020 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT master character device. +*/ + +/****************************************************************************/ + +#include +#include +#include + +#include "cdev.h" +#include "master.h" +#include "slave_config.h" +#include "voe_handler.h" +#include "ethernet.h" +#include "ioctl.h" + +/** Set to 1 to enable device operations debugging. + */ +#define DEBUG 0 + +/****************************************************************************/ + +static int eccdev_open(struct inode *, struct file *); +static int eccdev_release(struct inode *, struct file *); +static long eccdev_ioctl(struct file *, unsigned int, unsigned long); +static int eccdev_mmap(struct file *, struct vm_area_struct *); + +/** This is the kernel version from which the .fault member of the + * vm_operations_struct is usable. + */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0) +# define FAULT_RETURN_TYPE int +#else +# define FAULT_RETURN_TYPE vm_fault_t +#endif + +static FAULT_RETURN_TYPE eccdev_vma_fault( +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0) + struct vm_area_struct *, +#endif + struct vm_fault *); + +/****************************************************************************/ + +/** File operation callbacks for the EtherCAT character device. + */ +static struct file_operations eccdev_fops = { + .owner = THIS_MODULE, + .open = eccdev_open, + .release = eccdev_release, + .unlocked_ioctl = eccdev_ioctl, + .mmap = eccdev_mmap +}; + +/** Callbacks for a virtual memory area retrieved with ecdevc_mmap(). + */ +struct vm_operations_struct eccdev_vm_ops = { + .fault = eccdev_vma_fault +}; + +/****************************************************************************/ + +/** Private data structure for file handles. + */ +typedef struct { + ec_cdev_t *cdev; /**< Character device. */ + ec_ioctl_context_t ctx; /**< Context. */ +} ec_cdev_priv_t; + +/****************************************************************************/ + +/** Constructor. + * + * \return 0 in case of success, else < 0 + */ +int ec_cdev_init( + ec_cdev_t *cdev, /**< EtherCAT master character device. */ + ec_master_t *master, /**< Parent master. */ + dev_t dev_num /**< Device number. */ + ) +{ + int ret; + + cdev->master = master; + + cdev_init(&cdev->cdev, &eccdev_fops); + cdev->cdev.owner = THIS_MODULE; + + ret = cdev_add(&cdev->cdev, + MKDEV(MAJOR(dev_num), master->index), 1); + if (ret) { + EC_MASTER_ERR(master, "Failed to add character device!\n"); + } + + return ret; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_cdev_clear(ec_cdev_t *cdev /**< EtherCAT XML device */) +{ + cdev_del(&cdev->cdev); +} + +/***************************************************************************** + * File operations + ****************************************************************************/ + +/** Called when the cdev is opened. + */ +int eccdev_open(struct inode *inode, struct file *filp) +{ + ec_cdev_t *cdev = container_of(inode->i_cdev, ec_cdev_t, cdev); + ec_cdev_priv_t *priv; + + priv = kmalloc(sizeof(ec_cdev_priv_t), GFP_KERNEL); + if (!priv) { + EC_MASTER_ERR(cdev->master, + "Failed to allocate memory for private data structure.\n"); + return -ENOMEM; + } + + priv->cdev = cdev; + priv->ctx.writable = (filp->f_mode & FMODE_WRITE) != 0; + priv->ctx.requested = 0; + priv->ctx.process_data = NULL; + priv->ctx.process_data_size = 0; + + filp->private_data = priv; + +#if DEBUG + EC_MASTER_DBG(cdev->master, 0, "File opened.\n"); +#endif + return 0; +} + +/****************************************************************************/ + +/** Called when the cdev is closed. + */ +int eccdev_release(struct inode *inode, struct file *filp) +{ + ec_cdev_priv_t *priv = (ec_cdev_priv_t *) filp->private_data; + ec_master_t *master = priv->cdev->master; + + if (priv->ctx.requested) { + ecrt_release_master(master); + } + + if (priv->ctx.process_data) { + vfree(priv->ctx.process_data); + } + +#if DEBUG + EC_MASTER_DBG(master, 0, "File closed.\n"); +#endif + + kfree(priv); + return 0; +} + +/****************************************************************************/ + +/** Called when an ioctl() command is issued. + */ +long eccdev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + ec_cdev_priv_t *priv = (ec_cdev_priv_t *) filp->private_data; + +#if DEBUG + EC_MASTER_DBG(priv->cdev->master, 0, + "ioctl(filp = 0x%p, cmd = 0x%08x (0x%02x), arg = 0x%lx)\n", + filp, cmd, _IOC_NR(cmd), arg); +#endif + + return ec_ioctl(priv->cdev->master, &priv->ctx, cmd, (void __user *) arg); +} + +/****************************************************************************/ + +#ifndef VM_DONTDUMP +/** VM_RESERVED disappeared in 3.7. + */ +#define VM_DONTDUMP VM_RESERVED +#endif + +/** Memory-map callback for the EtherCAT character device. + * + * The actual mapping will be done in the eccdev_vma_nopage() callback of the + * virtual memory area. + * + * \return Always zero (success). + */ +int eccdev_mmap( + struct file *filp, + struct vm_area_struct *vma + ) +{ + ec_cdev_priv_t *priv = (ec_cdev_priv_t *) filp->private_data; + + EC_MASTER_DBG(priv->cdev->master, 1, "mmap()\n"); + + vma->vm_ops = &eccdev_vm_ops; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + vm_flags_set(vma, VM_DONTDUMP); +#else + vma->vm_flags |= VM_DONTDUMP; /* Pages will not be swapped out */ +#endif + vma->vm_private_data = priv; + + return 0; +} + +/****************************************************************************/ + +/** Page fault callback for a virtual memory area. + * + * Called at the first access on a virtual-memory area retrieved with + * ecdev_mmap(). + * + * \return Zero on success, otherwise a negative error code. + */ +static FAULT_RETURN_TYPE eccdev_vma_fault( +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0) + struct vm_area_struct *vma, /**< Virtual memory area. */ +#endif + struct vm_fault *vmf /**< Fault data. */ + ) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) + struct vm_area_struct *vma = vmf->vma; +#endif + unsigned long offset = vmf->pgoff << PAGE_SHIFT; + ec_cdev_priv_t *priv = (ec_cdev_priv_t *) vma->vm_private_data; + struct page *page; + + if (offset >= priv->ctx.process_data_size) { + return VM_FAULT_SIGBUS; + } + + page = vmalloc_to_page(priv->ctx.process_data + offset); + if (!page) { + return VM_FAULT_SIGBUS; + } + + get_page(page); + vmf->page = page; + + EC_MASTER_DBG(priv->cdev->master, 1, "Vma fault," + " offset = %lu, page = %p\n", offset, page); + + return 0; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/cdev.h b/ubuntu/igh-ecat/master/cdev.h new file mode 100644 index 00000000000000..825d360ee0d553 --- /dev/null +++ b/ubuntu/igh-ecat/master/cdev.h @@ -0,0 +1,53 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT master character device. +*/ + +/****************************************************************************/ + +#ifndef __EC_CDEV_H__ +#define __EC_CDEV_H__ + +#include +#include + +#include "globals.h" + +/****************************************************************************/ + +/** EtherCAT master character device. +*/ +typedef struct { + ec_master_t *master; /**< Master owning the device. */ + struct cdev cdev; /**< Character device. */ +} ec_cdev_t; + +/****************************************************************************/ + +int ec_cdev_init(ec_cdev_t *, ec_master_t *, dev_t); +void ec_cdev_clear(ec_cdev_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/coe_emerg_ring.c b/ubuntu/igh-ecat/master/coe_emerg_ring.c new file mode 100644 index 00000000000000..b0026c3b808545 --- /dev/null +++ b/ubuntu/igh-ecat/master/coe_emerg_ring.c @@ -0,0 +1,169 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * vim: expandtab + * + ****************************************************************************/ + +/** \file + * EtherCAT CoE emergency ring buffer methods. + */ + +/****************************************************************************/ + +#include + +#include "coe_emerg_ring.h" + +/****************************************************************************/ + +/** Emergency ring buffer constructor. + */ +void ec_coe_emerg_ring_init( + ec_coe_emerg_ring_t *ring, /**< Emergency ring. */ + ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + ring->sc = sc; + ring->msgs = NULL; + ring->size = 0; + ring->read_index = 0; + ring->write_index = 0; + ring->overruns = 0; +} + +/****************************************************************************/ + +/** Emergency ring buffer destructor. + */ +void ec_coe_emerg_ring_clear( + ec_coe_emerg_ring_t *ring /**< Emergency ring. */ + ) +{ + if (ring->msgs) { + kfree(ring->msgs); + } +} + +/****************************************************************************/ + +/** Set the ring size. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_coe_emerg_ring_size( + ec_coe_emerg_ring_t *ring, /**< Emergency ring. */ + size_t size /**< Maximum number of messages in the ring. */ + ) +{ + ring->size = 0; + + if (size < 0) { + size = 0; + } + + ring->read_index = ring->write_index = 0; + + if (ring->msgs) { + kfree(ring->msgs); + } + ring->msgs = NULL; + + if (size == 0) { + return 0; + } + + ring->msgs = kmalloc(sizeof(ec_coe_emerg_msg_t) * (size + 1), GFP_KERNEL); + if (!ring->msgs) { + return -ENOMEM; + } + + ring->size = size; + return 0; +} + +/****************************************************************************/ + +/** Add a new emergency message. + */ +void ec_coe_emerg_ring_push( + ec_coe_emerg_ring_t *ring, /**< Emergency ring. */ + const u8 *msg /**< Emergency message. */ + ) +{ + if (!ring->size || + (ring->write_index + 1) % (ring->size + 1) == ring->read_index) { + ring->overruns++; + return; + } + + memcpy(ring->msgs[ring->write_index].data, msg, + EC_COE_EMERGENCY_MSG_SIZE); + ring->write_index = (ring->write_index + 1) % (ring->size + 1); +} + +/****************************************************************************/ + +/** Remove an emergency message from the ring. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_coe_emerg_ring_pop( + ec_coe_emerg_ring_t *ring, /**< Emergency ring. */ + u8 *msg /**< Memory to store the emergency message. */ + ) +{ + if (ring->read_index == ring->write_index) { + return -ENOENT; + } + + memcpy(msg, ring->msgs[ring->read_index].data, EC_COE_EMERGENCY_MSG_SIZE); + ring->read_index = (ring->read_index + 1) % (ring->size + 1); + return 0; +} + +/****************************************************************************/ + +/** Clear the ring. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_coe_emerg_ring_clear_ring( + ec_coe_emerg_ring_t *ring /**< Emergency ring. */ + ) +{ + ring->read_index = ring->write_index; + ring->overruns = 0; + return 0; +} + +/****************************************************************************/ + +/** Read the number of overruns. + * + * \return Number of overruns. + */ +int ec_coe_emerg_ring_overruns( + const ec_coe_emerg_ring_t *ring /**< Emergency ring. */ + ) +{ + return ring->overruns; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/coe_emerg_ring.h b/ubuntu/igh-ecat/master/coe_emerg_ring.h new file mode 100644 index 00000000000000..36ab2c41f43ca0 --- /dev/null +++ b/ubuntu/igh-ecat/master/coe_emerg_ring.h @@ -0,0 +1,70 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CoE emergency ring buffer structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_COE_EMERG_RING_H__ +#define __EC_COE_EMERG_RING_H__ + +#include "globals.h" + +/****************************************************************************/ + +/** EtherCAT CoE emergency message record. + */ +typedef struct { + u8 data[EC_COE_EMERGENCY_MSG_SIZE]; /**< Message data. */ +} ec_coe_emerg_msg_t; + +/****************************************************************************/ + +/** EtherCAT CoE emergency ring buffer. + */ +typedef struct { + ec_slave_config_t *sc; /**< Slave configuration owning the ring. */ + + ec_coe_emerg_msg_t *msgs; /**< Message ring. */ + size_t size; /**< Ring size. */ + + unsigned int read_index; /**< Read index. */ + unsigned int write_index; /**< Write index. */ + unsigned int overruns; /**< Number of overruns since last reset. */ +} ec_coe_emerg_ring_t; + +/****************************************************************************/ + +void ec_coe_emerg_ring_init(ec_coe_emerg_ring_t *, ec_slave_config_t *); +void ec_coe_emerg_ring_clear(ec_coe_emerg_ring_t *); + +int ec_coe_emerg_ring_size(ec_coe_emerg_ring_t *, size_t); +void ec_coe_emerg_ring_push(ec_coe_emerg_ring_t *, const u8 *); +int ec_coe_emerg_ring_pop(ec_coe_emerg_ring_t *, u8 *); +int ec_coe_emerg_ring_clear_ring(ec_coe_emerg_ring_t *); +int ec_coe_emerg_ring_overruns(const ec_coe_emerg_ring_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/datagram.c b/ubuntu/igh-ecat/master/datagram.c new file mode 100644 index 00000000000000..c0f3360afd6eff --- /dev/null +++ b/ubuntu/igh-ecat/master/datagram.c @@ -0,0 +1,644 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Methods of an EtherCAT datagram. +*/ + +/****************************************************************************/ + +#include + +#include "datagram.h" +#include "master.h" + +/****************************************************************************/ + +/** \cond */ + +#define EC_FUNC_HEADER \ + ret = ec_datagram_prealloc(datagram, data_size); \ + if (unlikely(ret)) \ + return ret; \ + datagram->index = 0; \ + datagram->working_counter = 0; \ + datagram->state = EC_DATAGRAM_INIT; + +#define EC_FUNC_FOOTER \ + datagram->data_size = data_size; \ + return 0; + +/** \endcond */ + +/****************************************************************************/ + +/** Array of datagram type strings used in ec_datagram_type_string(). + * + * \attention This is indexed by ec_datagram_type_t. + */ +static const char *type_strings[] = { + "?", + "APRD", + "APWR", + "APRW", + "FPRD", + "FPWR", + "FPRW", + "BRD", + "BWR", + "BRW", + "LRD", + "LWR", + "LRW", + "ARMW", + "FRMW" +}; + +/****************************************************************************/ + +/** Constructor. + */ +void ec_datagram_init(ec_datagram_t *datagram /**< EtherCAT datagram. */) +{ + INIT_LIST_HEAD(&datagram->queue); // mark as unqueued + datagram->device_index = EC_DEVICE_MAIN; + datagram->type = EC_DATAGRAM_NONE; + memset(datagram->address, 0x00, EC_ADDR_LEN); + datagram->data = NULL; + datagram->data_origin = EC_ORIG_INTERNAL; + datagram->mem_size = 0; + datagram->data_size = 0; + datagram->index = 0x00; + datagram->working_counter = 0x0000; + datagram->state = EC_DATAGRAM_INIT; +#ifdef EC_HAVE_CYCLES + datagram->cycles_sent = 0; +#endif + datagram->jiffies_sent = 0; +#ifdef EC_HAVE_CYCLES + datagram->cycles_received = 0; +#endif + datagram->jiffies_received = 0; + datagram->skip_count = 0; + datagram->stats_output_jiffies = 0; + memset(datagram->name, 0x00, EC_DATAGRAM_NAME_SIZE); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_datagram_clear(ec_datagram_t *datagram /**< EtherCAT datagram. */) +{ + ec_datagram_unqueue(datagram); + + if (datagram->data_origin == EC_ORIG_INTERNAL && datagram->data) { + kfree(datagram->data); + datagram->data = NULL; + } +} + +/****************************************************************************/ + +/** Unqueue datagram. + */ +void ec_datagram_unqueue(ec_datagram_t *datagram /**< EtherCAT datagram. */) +{ + if (!list_empty(&datagram->queue)) { + list_del_init(&datagram->queue); + } +} + +/****************************************************************************/ + +/** Allocates internal payload memory. + * + * If the allocated memory is already larger than requested, nothing ist done. + * + * \attention If external payload memory has been provided, no range checking + * is done! + * + * \return 0 in case of success, otherwise \a -ENOMEM. + */ +int ec_datagram_prealloc( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + size_t size /**< New payload size in bytes. */ + ) +{ + if (datagram->data_origin == EC_ORIG_EXTERNAL + || size <= datagram->mem_size) + return 0; + + if (datagram->data) { + kfree(datagram->data); + datagram->data = NULL; + datagram->mem_size = 0; + } + + if (!(datagram->data = kmalloc(size, GFP_KERNEL))) { + EC_ERR("Failed to allocate %zu bytes of datagram memory!\n", size); + return -ENOMEM; + } + + datagram->mem_size = size; + return 0; +} + +/****************************************************************************/ + +/** Fills the datagram payload memory with zeros. + */ +void ec_datagram_zero(ec_datagram_t *datagram /**< EtherCAT datagram. */) +{ + memset(datagram->data, 0x00, datagram->data_size); +} + +/****************************************************************************/ + +/** Initializes an EtherCAT APRD datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_aprd( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t ring_position, /**< Auto-increment address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to read. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_APRD; + EC_WRITE_S16(datagram->address, (int16_t) ring_position * (-1)); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT APWR datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_apwr( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t ring_position, /**< Auto-increment address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_APWR; + EC_WRITE_S16(datagram->address, (int16_t) ring_position * (-1)); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT APRW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_aprw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t ring_position, /**< Auto-increment address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_APRW; + EC_WRITE_S16(datagram->address, (int16_t) ring_position * (-1)); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT ARMW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_armw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t ring_position, /**< Auto-increment address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to read. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_ARMW; + EC_WRITE_S16(datagram->address, (int16_t) ring_position * (-1)); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT FPRD datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_fprd( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t configured_address, /**< Configured station address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to read. */ + ) +{ + int ret; + + if (unlikely(configured_address == 0x0000)) + EC_WARN("Using configured station address 0x0000!\n"); + + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_FPRD; + EC_WRITE_U16(datagram->address, configured_address); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT FPWR datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_fpwr( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t configured_address, /**< Configured station address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + + if (unlikely(configured_address == 0x0000)) + EC_WARN("Using configured station address 0x0000!\n"); + + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_FPWR; + EC_WRITE_U16(datagram->address, configured_address); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT FPRW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_fprw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t configured_address, /**< Configured station address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + + if (unlikely(configured_address == 0x0000)) + EC_WARN("Using configured station address 0x0000!\n"); + + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_FPRW; + EC_WRITE_U16(datagram->address, configured_address); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT FRMW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_frmw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t configured_address, /**< Configured station address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + + if (unlikely(configured_address == 0x0000)) + EC_WARN("Using configured station address 0x0000!\n"); + + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_FRMW; + EC_WRITE_U16(datagram->address, configured_address); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT BRD datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_brd( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to read. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_BRD; + EC_WRITE_U16(datagram->address, 0x0000); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT BWR datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_bwr( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_BWR; + EC_WRITE_U16(datagram->address, 0x0000); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT BRW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_brw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_BRW; + EC_WRITE_U16(datagram->address, 0x0000); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LRD datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lrd( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size /**< Number of bytes to read/write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LRD; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LWR datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lwr( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size /**< Number of bytes to read/write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LWR; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LRW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lrw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size /**< Number of bytes to read/write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LRW; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LRD datagram with external memory. + * + * \attention It is assumed, that the external memory is at least \a data_size + * bytes large. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lrd_ext( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size, /**< Number of bytes to read/write. */ + uint8_t *external_memory /**< Pointer to the memory to use. */ + ) +{ + int ret; + datagram->data = external_memory; + datagram->data_origin = EC_ORIG_EXTERNAL; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LRD; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LWR datagram with external memory. + * + * \attention It is assumed, that the external memory is at least \a data_size + * bytes large. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lwr_ext( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size, /**< Number of bytes to read/write. */ + uint8_t *external_memory /**< Pointer to the memory to use. */ + ) +{ + int ret; + datagram->data = external_memory; + datagram->data_origin = EC_ORIG_EXTERNAL; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LWR; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LRW datagram with external memory. + * + * \attention It is assumed, that the external memory is at least \a data_size + * bytes large. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lrw_ext( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size, /**< Number of bytes to read/write. */ + uint8_t *external_memory /**< Pointer to the memory to use. */ + ) +{ + int ret; + datagram->data = external_memory; + datagram->data_origin = EC_ORIG_EXTERNAL; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LRW; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Prints the state of a datagram. + * + * Outputs a text message. + */ +void ec_datagram_print_state( + const ec_datagram_t *datagram /**< EtherCAT datagram */ + ) +{ + printk(KERN_CONT "Datagram "); + switch (datagram->state) { + case EC_DATAGRAM_INIT: + printk(KERN_CONT "initialized"); + break; + case EC_DATAGRAM_QUEUED: + printk(KERN_CONT "queued"); + break; + case EC_DATAGRAM_SENT: + printk(KERN_CONT "sent"); + break; + case EC_DATAGRAM_RECEIVED: + printk(KERN_CONT "received"); + break; + case EC_DATAGRAM_TIMED_OUT: + printk(KERN_CONT "timed out"); + break; + case EC_DATAGRAM_ERROR: + printk(KERN_CONT "error"); + break; + default: + printk(KERN_CONT "???"); + } + + printk(KERN_CONT ".\n"); +} + +/****************************************************************************/ + +/** Evaluates the working counter of a single-cast datagram. + * + * Outputs an error message. + */ +void ec_datagram_print_wc_error( + const ec_datagram_t *datagram /**< EtherCAT datagram */ + ) +{ + if (datagram->working_counter == 0) { + printk(KERN_CONT "No response."); + } + else if (datagram->working_counter > 1) { + printk(KERN_CONT "%u slaves responded!", datagram->working_counter); + } + else { + printk(KERN_CONT "Success."); + } + printk(KERN_CONT "\n"); +} + +/****************************************************************************/ + +/** Outputs datagram statistics at most every second. + */ +void ec_datagram_output_stats( + ec_datagram_t *datagram + ) +{ + if (jiffies - datagram->stats_output_jiffies > HZ) { + datagram->stats_output_jiffies = jiffies; + + if (unlikely(datagram->skip_count)) { + EC_WARN("Datagram %p (%s) was SKIPPED %u time%s.\n", + datagram, datagram->name, + datagram->skip_count, + datagram->skip_count == 1 ? "" : "s"); + datagram->skip_count = 0; + } + } +} + +/****************************************************************************/ + +/** Returns a string describing the datagram type. + * + * \return Pointer on a static memory containing the requested string. + */ +const char *ec_datagram_type_string( + const ec_datagram_t *datagram /**< EtherCAT datagram. */ + ) +{ + return type_strings[datagram->type]; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/datagram.h b/ubuntu/igh-ecat/master/datagram.h new file mode 100644 index 00000000000000..13184928630065 --- /dev/null +++ b/ubuntu/igh-ecat/master/datagram.h @@ -0,0 +1,142 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT datagram structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_DATAGRAM_H__ +#define __EC_DATAGRAM_H__ + +#include +#include +#include + +#include "globals.h" + +/****************************************************************************/ + +/** EtherCAT datagram type. + */ +typedef enum { + EC_DATAGRAM_NONE = 0x00, /**< Dummy. */ + EC_DATAGRAM_APRD = 0x01, /**< Auto Increment Physical Read. */ + EC_DATAGRAM_APWR = 0x02, /**< Auto Increment Physical Write. */ + EC_DATAGRAM_APRW = 0x03, /**< Auto Increment Physical ReadWrite. */ + EC_DATAGRAM_FPRD = 0x04, /**< Configured Address Physical Read. */ + EC_DATAGRAM_FPWR = 0x05, /**< Configured Address Physical Write. */ + EC_DATAGRAM_FPRW = 0x06, /**< Configured Address Physical ReadWrite. */ + EC_DATAGRAM_BRD = 0x07, /**< Broadcast Read. */ + EC_DATAGRAM_BWR = 0x08, /**< Broadcast Write. */ + EC_DATAGRAM_BRW = 0x09, /**< Broadcast ReadWrite. */ + EC_DATAGRAM_LRD = 0x0A, /**< Logical Read. */ + EC_DATAGRAM_LWR = 0x0B, /**< Logical Write. */ + EC_DATAGRAM_LRW = 0x0C, /**< Logical ReadWrite. */ + EC_DATAGRAM_ARMW = 0x0D, /**< Auto Increment Physical Read Multiple + Write. */ + EC_DATAGRAM_FRMW = 0x0E, /**< Configured Address Physical Read Multiple + Write. */ +} ec_datagram_type_t; + +/****************************************************************************/ + +/** EtherCAT datagram state. + */ +typedef enum { + EC_DATAGRAM_INIT, /**< Initial state of a new datagram. */ + EC_DATAGRAM_QUEUED, /**< Queued for sending. */ + EC_DATAGRAM_SENT, /**< Sent (still in the queue). */ + EC_DATAGRAM_RECEIVED, /**< Received (dequeued). */ + EC_DATAGRAM_TIMED_OUT, /**< Timed out (dequeued). */ + EC_DATAGRAM_ERROR /**< Error while sending/receiving (dequeued). */ +} ec_datagram_state_t; + +/****************************************************************************/ + +/** EtherCAT datagram. + */ +typedef struct { + struct list_head queue; /**< Master datagram queue item, + protected by user-supplied mutex. */ + struct list_head ext_queue; /**< External datagram queue item, protected by ext_queue_sem. */ + struct list_head sent; /**< Master list item for sent datagrams. */ + ec_device_index_t device_index; /**< Device via which the datagram shall + be / was sent. */ + ec_datagram_type_t type; /**< Datagram type (APRD, BWR, etc.). */ + uint8_t address[EC_ADDR_LEN]; /**< Recipient address. */ + uint8_t *data; /**< Datagram payload. */ + ec_origin_t data_origin; /**< Origin of the \a data memory. */ + size_t mem_size; /**< Datagram \a data memory size. */ + size_t data_size; /**< Size of the data in \a data. */ + uint8_t index; /**< Index (set by master). */ + uint16_t working_counter; /**< Working counter. */ + ec_datagram_state_t state; /**< State. */ +#ifdef EC_HAVE_CYCLES + cycles_t cycles_sent; /**< Time, when the datagram was sent. */ +#endif + unsigned long jiffies_sent; /**< Jiffies, when the datagram was sent. */ +#ifdef EC_HAVE_CYCLES + cycles_t cycles_received; /**< Time, when the datagram was received. */ +#endif + unsigned long jiffies_received; /**< Jiffies, when the datagram was + received. */ + unsigned int skip_count; /**< Number of requeues when not yet received. */ + unsigned long stats_output_jiffies; /**< Last statistics output. */ + char name[EC_DATAGRAM_NAME_SIZE]; /**< Description of the datagram. */ +} ec_datagram_t; + +/****************************************************************************/ + +void ec_datagram_init(ec_datagram_t *); +void ec_datagram_clear(ec_datagram_t *); +void ec_datagram_unqueue(ec_datagram_t *); +int ec_datagram_prealloc(ec_datagram_t *, size_t); +void ec_datagram_zero(ec_datagram_t *); + +int ec_datagram_aprd(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_apwr(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_aprw(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_armw(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_fprd(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_fpwr(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_fprw(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_frmw(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_brd(ec_datagram_t *, uint16_t, size_t); +int ec_datagram_bwr(ec_datagram_t *, uint16_t, size_t); +int ec_datagram_brw(ec_datagram_t *, uint16_t, size_t); +int ec_datagram_lrd(ec_datagram_t *, uint32_t, size_t); +int ec_datagram_lwr(ec_datagram_t *, uint32_t, size_t); +int ec_datagram_lrw(ec_datagram_t *, uint32_t, size_t); +int ec_datagram_lrd_ext(ec_datagram_t *, uint32_t, size_t, uint8_t *); +int ec_datagram_lwr_ext(ec_datagram_t *, uint32_t, size_t, uint8_t *); +int ec_datagram_lrw_ext(ec_datagram_t *, uint32_t, size_t, uint8_t *); + +void ec_datagram_print_state(const ec_datagram_t *); +void ec_datagram_print_wc_error(const ec_datagram_t *); +void ec_datagram_output_stats(ec_datagram_t *); +const char *ec_datagram_type_string(const ec_datagram_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/datagram_pair.c b/ubuntu/igh-ecat/master/datagram_pair.c new file mode 100644 index 00000000000000..3e3d283886589e --- /dev/null +++ b/ubuntu/igh-ecat/master/datagram_pair.c @@ -0,0 +1,193 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT datagram pair methods. +*/ + +/****************************************************************************/ + +#include + +#include "master.h" +#include "datagram_pair.h" + +/****************************************************************************/ + +/** Datagram pair constructor. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_datagram_pair_init( + ec_datagram_pair_t *pair, /**< Datagram pair. */ + ec_domain_t *domain, /**< Parent domain. */ + uint32_t logical_offset, /**< Logical offset. */ + uint8_t *data, /**< Data pointer. */ + size_t data_size, /**< Data size. */ + const unsigned int used[] /**< input/output use count. */ + ) +{ + ec_device_index_t dev_idx; + int ret; + + INIT_LIST_HEAD(&pair->list); + pair->domain = domain; + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_init(&pair->datagrams[dev_idx]); + snprintf(pair->datagrams[dev_idx].name, + EC_DATAGRAM_NAME_SIZE, "domain%u-%u-%s", domain->index, + logical_offset, ec_device_names[dev_idx != 0]); + pair->datagrams[dev_idx].device_index = dev_idx; + } + + pair->expected_working_counter = 0U; + + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + /* backup datagrams have their own memory */ + ret = ec_datagram_prealloc(&pair->datagrams[dev_idx], data_size); + if (ret) { + goto out_datagrams; + } + } + +#if EC_MAX_NUM_DEVICES > 1 + if (!(pair->send_buffer = kmalloc(data_size, GFP_KERNEL))) { + EC_MASTER_ERR(domain->master, + "Failed to allocate domain send buffer!\n"); + ret = -ENOMEM; + goto out_datagrams; + } +#endif + + /* The ec_datagram_lxx() calls below can not fail, because either the + * datagram has external memory or it is preallocated. */ + + if (used[EC_DIR_OUTPUT] && used[EC_DIR_INPUT]) { // inputs and outputs + ec_datagram_lrw_ext(&pair->datagrams[EC_DEVICE_MAIN], + logical_offset, data_size, data); + + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_lrw(&pair->datagrams[dev_idx], + logical_offset, data_size); + } + + // If LRW is used, output FMMUs increment the working counter by 2, + // while input FMMUs increment it by 1. + pair->expected_working_counter = + used[EC_DIR_OUTPUT] * 2 + used[EC_DIR_INPUT]; + } else if (used[EC_DIR_OUTPUT]) { // outputs only + ec_datagram_lwr_ext(&pair->datagrams[EC_DEVICE_MAIN], + logical_offset, data_size, data); + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_lwr(&pair->datagrams[dev_idx], + logical_offset, data_size); + } + + pair->expected_working_counter = used[EC_DIR_OUTPUT]; + } else { // inputs only (or nothing) + ec_datagram_lrd_ext(&pair->datagrams[EC_DEVICE_MAIN], + logical_offset, data_size, data); + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_lrd(&pair->datagrams[dev_idx], logical_offset, + data_size); + } + + pair->expected_working_counter = used[EC_DIR_INPUT]; + } + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_zero(&pair->datagrams[dev_idx]); + } + + return 0; + +out_datagrams: + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_clear(&pair->datagrams[dev_idx]); + } + + return ret; +} + +/****************************************************************************/ + +/** Datagram pair destructor. + */ +void ec_datagram_pair_clear( + ec_datagram_pair_t *pair /**< Datagram pair. */ + ) +{ + unsigned int dev_idx; + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(pair->domain->master); + dev_idx++) { + ec_datagram_clear(&pair->datagrams[dev_idx]); + } + +#if EC_MAX_NUM_DEVICES > 1 + if (pair->send_buffer) { + kfree(pair->send_buffer); + } +#endif +} + +/****************************************************************************/ + +/** Process received data. + * + * \return Working counter sum over all devices. + */ +uint16_t ec_datagram_pair_process( + ec_datagram_pair_t *pair, /**< Datagram pair. */ + uint16_t wc_sum[] /**< Working counter sums. */ + ) +{ + unsigned int dev_idx; + uint16_t pair_wc = 0; + + for (dev_idx = 0; dev_idx < ec_master_num_devices(pair->domain->master); + dev_idx++) { + ec_datagram_t *datagram = &pair->datagrams[dev_idx]; + +#ifdef EC_RT_SYSLOG + ec_datagram_output_stats(datagram); +#endif + + if (datagram->state == EC_DATAGRAM_RECEIVED) { + pair_wc += datagram->working_counter; + wc_sum[dev_idx] += datagram->working_counter; + } + } + + return pair_wc; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/datagram_pair.h b/ubuntu/igh-ecat/master/datagram_pair.h new file mode 100644 index 00000000000000..0294a2162019db --- /dev/null +++ b/ubuntu/igh-ecat/master/datagram_pair.h @@ -0,0 +1,61 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT datagram pair structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_DATAGRAM_PAIR_H__ +#define __EC_DATAGRAM_PAIR_H__ + +#include + +#include "globals.h" +#include "datagram.h" + +/****************************************************************************/ + +/** Domain datagram pair. + */ +typedef struct { + struct list_head list; /**< List header. */ + ec_domain_t *domain; /**< Parent domain. */ + ec_datagram_t datagrams[EC_MAX_NUM_DEVICES]; /**< Datagrams. */ +#if EC_MAX_NUM_DEVICES > 1 + uint8_t *send_buffer; +#endif + unsigned int expected_working_counter; /**< Expectord working conter. */ +} ec_datagram_pair_t; + +/****************************************************************************/ + +int ec_datagram_pair_init(ec_datagram_pair_t *, ec_domain_t *, uint32_t, + uint8_t *, size_t, const unsigned int []); +void ec_datagram_pair_clear(ec_datagram_pair_t *); + +uint16_t ec_datagram_pair_process(ec_datagram_pair_t *, uint16_t[]); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/debug.c b/ubuntu/igh-ecat/master/debug.c new file mode 100644 index 00000000000000..268a6bb7128a8c --- /dev/null +++ b/ubuntu/igh-ecat/master/debug.c @@ -0,0 +1,258 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Ethernet interface for debugging purposes. +*/ + +/****************************************************************************/ + +#include +#include +#include + +#include "globals.h" +#include "master.h" +#include "debug.h" + +/****************************************************************************/ + +// net_device functions +int ec_dbgdev_open(struct net_device *); +int ec_dbgdev_stop(struct net_device *); +int ec_dbgdev_tx(struct sk_buff *, struct net_device *); +struct net_device_stats *ec_dbgdev_stats(struct net_device *); + +/** Device operations for debug interfaces. + */ +static const struct net_device_ops ec_dbg_netdev_ops = +{ + .ndo_open = ec_dbgdev_open, + .ndo_stop = ec_dbgdev_stop, + .ndo_start_xmit = ec_dbgdev_tx, + .ndo_get_stats = ec_dbgdev_stats, +}; + +/****************************************************************************/ + +/** Debug interface constructor. + * + * Initializes the debug object, creates a net_device and registeres it. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_debug_init( + ec_debug_t *dbg, /**< Debug object. */ + ec_device_t *device, /**< EtherCAT device. */ + const char *name /**< Interface name. */ + ) +{ + dbg->device = device; + dbg->registered = 0; + dbg->opened = 0; + + memset(&dbg->stats, 0, sizeof(struct net_device_stats)); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) + dbg->dev = alloc_netdev(sizeof(ec_debug_t *), name, NET_NAME_UNKNOWN, ether_setup); +#else + dbg->dev = alloc_netdev(sizeof(ec_debug_t *), name, ether_setup); +#endif + if (!(dbg->dev)) + { + EC_MASTER_ERR(device->master, "Unable to allocate net_device" + " for debug object!\n"); + return -ENODEV; + } + + // initialize net_device + dbg->dev->netdev_ops = &ec_dbg_netdev_ops; + + // initialize private data + *((ec_debug_t **) netdev_priv(dbg->dev)) = dbg; + + return 0; +} + +/****************************************************************************/ + +/** Debug interface destructor. + * + * Unregisters the net_device and frees allocated memory. + */ +void ec_debug_clear( + ec_debug_t *dbg /**< debug object */ + ) +{ + ec_debug_unregister(dbg); + free_netdev(dbg->dev); +} + +/****************************************************************************/ + +/** Register debug interface. + */ +void ec_debug_register( + ec_debug_t *dbg, /**< debug object */ + const struct net_device *net_dev /**< 'Real' Ethernet device. */ + ) +{ + int result; + + ec_debug_unregister(dbg); + + // use the Ethernet address of the physical device for the debug device +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) + eth_hw_addr_set(dbg->dev, net_dev->dev_addr); +#else + memcpy(dbg->dev->dev_addr, net_dev->dev_addr, ETH_ALEN); +#endif + + // connect the net_device to the kernel + if ((result = register_netdev(dbg->dev))) { + EC_MASTER_WARN(dbg->device->master, "Unable to register net_device:" + " error %i\n", result); + } else { + dbg->registered = 1; + } +} + +/****************************************************************************/ + +/** Unregister debug interface. + */ +void ec_debug_unregister( + ec_debug_t *dbg /**< debug object */ + ) +{ + if (dbg->registered) { + dbg->opened = 0; + dbg->registered = 0; + unregister_netdev(dbg->dev); + } +} + +/****************************************************************************/ + +/** Sends frame data to the interface. + */ +void ec_debug_send( + ec_debug_t *dbg, /**< debug object */ + const uint8_t *data, /**< frame data */ + size_t size /**< size of the frame data */ + ) +{ + struct sk_buff *skb; + + if (!dbg->opened) + return; + + // allocate socket buffer + if (!(skb = dev_alloc_skb(size))) { + dbg->stats.rx_dropped++; + return; + } + + // copy frame contents into socket buffer + memcpy(skb_put(skb, size), data, size); + + // update device statistics + dbg->stats.rx_packets++; + dbg->stats.rx_bytes += size; + + // pass socket buffer to network stack + skb->dev = dbg->dev; + skb->protocol = eth_type_trans(skb, dbg->dev); + skb->ip_summed = CHECKSUM_UNNECESSARY; + netif_rx(skb); +} + +/***************************************************************************** + * NET_DEVICE functions + ****************************************************************************/ + +/** Opens the virtual network device. + * + * \return Always zero (success). + */ +int ec_dbgdev_open( + struct net_device *dev /**< debug net_device */ + ) +{ + ec_debug_t *dbg = *((ec_debug_t **) netdev_priv(dev)); + dbg->opened = 1; + EC_MASTER_INFO(dbg->device->master, "Debug interface %s opened.\n", + dev->name); + return 0; +} + +/****************************************************************************/ + +/** Stops the virtual network device. + * + * \return Always zero (success). + */ +int ec_dbgdev_stop( + struct net_device *dev /**< debug net_device */ + ) +{ + ec_debug_t *dbg = *((ec_debug_t **) netdev_priv(dev)); + dbg->opened = 0; + EC_MASTER_INFO(dbg->device->master, "Debug interface %s stopped.\n", + dev->name); + return 0; +} + +/****************************************************************************/ + +/** Transmits data via the virtual network device. + * + * \return Always zero (success). + */ +int ec_dbgdev_tx( + struct sk_buff *skb, /**< transmit socket buffer */ + struct net_device *dev /**< EoE net_device */ + ) +{ + ec_debug_t *dbg = *((ec_debug_t **) netdev_priv(dev)); + + dev_kfree_skb(skb); + dbg->stats.tx_dropped++; + return 0; +} + +/****************************************************************************/ + +/** Gets statistics about the virtual network device. + * + * \return Statistics. + */ +struct net_device_stats *ec_dbgdev_stats( + struct net_device *dev /**< debug net_device */ + ) +{ + ec_debug_t *dbg = *((ec_debug_t **) netdev_priv(dev)); + return &dbg->stats; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/debug.h b/ubuntu/igh-ecat/master/debug.h new file mode 100644 index 00000000000000..5d435d4c788f29 --- /dev/null +++ b/ubuntu/igh-ecat/master/debug.h @@ -0,0 +1,58 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Network interface for debugging purposes. +*/ + +/****************************************************************************/ + +#ifndef __EC_DEBUG_H__ +#define __EC_DEBUG_H__ + +#include "../devices/ecdev.h" + +/****************************************************************************/ + +/** Debugging network interface. + */ +typedef struct +{ + ec_device_t *device; /**< Parent device. */ + struct net_device *dev; /**< net_device for virtual ethernet device */ + struct net_device_stats stats; /**< device statistics */ + uint8_t registered; /**< net_device is opened */ + uint8_t opened; /**< net_device is opened */ +} +ec_debug_t; + +/****************************************************************************/ + +int ec_debug_init(ec_debug_t *, ec_device_t *, const char *); +void ec_debug_clear(ec_debug_t *); +void ec_debug_register(ec_debug_t *, const struct net_device *); +void ec_debug_unregister(ec_debug_t *); +void ec_debug_send(ec_debug_t *, const uint8_t *, size_t); + +#endif + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/device.c b/ubuntu/igh-ecat/master/device.c new file mode 100644 index 00000000000000..598d163a972251 --- /dev/null +++ b/ubuntu/igh-ecat/master/device.c @@ -0,0 +1,716 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT device methods. +*/ + +/****************************************************************************/ + +#include +#include +#include +#include + +#include "device.h" +#include "master.h" + +#ifdef EC_DEBUG_RING +#define timersub(a, b, result) \ + do { \ + (result)->tv_sec = (a)->tv_sec - (b)->tv_sec; \ + (result)->tv_usec = (a)->tv_usec - (b)->tv_usec; \ + if ((result)->tv_usec < 0) { \ + --(result)->tv_sec; \ + (result)->tv_usec += 1000000; \ + } \ + } while (0) +#endif + +/****************************************************************************/ + +enum { + /* genet driver needs extra headroom in skb for status block */ + EXTRA_HEADROOM = 64, +}; + +/** Constructor. + * + * \return 0 in case of success, else < 0 + */ +int ec_device_init( + ec_device_t *device, /**< EtherCAT device */ + ec_master_t *master /**< master owning the device */ + ) +{ + int ret; + unsigned int i; + struct ethhdr *eth; +#ifdef EC_DEBUG_IF + char ifname[10]; + char mb = 'x'; +#endif + + device->master = master; + device->dev = NULL; + device->poll = NULL; + device->module = NULL; + device->open = 0; + device->link_state = 0; + for (i = 0; i < EC_TX_RING_SIZE; i++) { + device->tx_skb[i] = NULL; + } + device->tx_ring_index = 0; +#ifdef EC_HAVE_CYCLES + device->cycles_poll = 0; +#endif +#ifdef EC_DEBUG_RING + device->timeval_poll.tv_sec = 0; + device->timeval_poll.tv_usec = 0; +#endif + device->jiffies_poll = 0; + + ec_device_clear_stats(device); + +#ifdef EC_DEBUG_RING + for (i = 0; i < EC_DEBUG_RING_SIZE; i++) { + ec_debug_frame_t *df = &device->debug_frames[i]; + df->dir = TX; + df->t.tv_sec = 0; + df->t.tv_usec = 0; + memset(df->data, 0, EC_MAX_DATA_SIZE); + df->data_size = 0; + } +#endif +#ifdef EC_DEBUG_RING + device->debug_frame_index = 0; + device->debug_frame_count = 0; +#endif + +#ifdef EC_DEBUG_IF + if (device == &master->devices[EC_DEVICE_MAIN]) { + mb = 'm'; + } + else { + mb = 'b'; + } + + sprintf(ifname, "ecdbg%c%u", mb, master->index); + + ret = ec_debug_init(&device->dbg, device, ifname); + if (ret < 0) { + EC_MASTER_ERR(master, "Failed to init debug device!\n"); + goto out_return; + } +#endif + + for (i = 0; i < EC_TX_RING_SIZE; i++) { + if (!(device->tx_skb[i] = dev_alloc_skb(ETH_FRAME_LEN + EXTRA_HEADROOM))) { + EC_MASTER_ERR(master, "Error allocating device socket buffer!\n"); + ret = -ENOMEM; + goto out_tx_ring; + } + + // add Ethernet-II-header + skb_reserve(device->tx_skb[i], ETH_HLEN + EXTRA_HEADROOM); + eth = (struct ethhdr *) skb_push(device->tx_skb[i], ETH_HLEN); + eth->h_proto = htons(0x88A4); + memset(eth->h_dest, 0xFF, ETH_ALEN); + } + + return 0; + +out_tx_ring: + for (i = 0; i < EC_TX_RING_SIZE; i++) { + if (device->tx_skb[i]) { + dev_kfree_skb(device->tx_skb[i]); + } + } +#ifdef EC_DEBUG_IF + ec_debug_clear(&device->dbg); +out_return: +#endif + return ret; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_device_clear( + ec_device_t *device /**< EtherCAT device */ + ) +{ + unsigned int i; + + if (device->open) { + ec_device_close(device); + } + for (i = 0; i < EC_TX_RING_SIZE; i++) + dev_kfree_skb(device->tx_skb[i]); +#ifdef EC_DEBUG_IF + ec_debug_clear(&device->dbg); +#endif +} + +/****************************************************************************/ + +/** Associate with net_device. + */ +void ec_device_attach( + ec_device_t *device, /**< EtherCAT device */ + struct net_device *net_dev, /**< net_device structure */ + ec_pollfunc_t poll, /**< pointer to device's poll function */ + struct module *module /**< the device's module */ + ) +{ + unsigned int i; + struct ethhdr *eth; + + ec_device_detach(device); // resets fields + + device->dev = net_dev; + device->poll = poll; + device->module = module; + + for (i = 0; i < EC_TX_RING_SIZE; i++) { + device->tx_skb[i]->dev = net_dev; + eth = (struct ethhdr *) (device->tx_skb[i]->data); + memcpy(eth->h_source, net_dev->dev_addr, ETH_ALEN); + } + +#ifdef EC_DEBUG_IF + ec_debug_register(&device->dbg, net_dev); +#endif +} + +/****************************************************************************/ + +/** Disconnect from net_device. + */ +void ec_device_detach( + ec_device_t *device /**< EtherCAT device */ + ) +{ + unsigned int i; + +#ifdef EC_DEBUG_IF + ec_debug_unregister(&device->dbg); +#endif + + device->dev = NULL; + device->poll = NULL; + device->module = NULL; + device->open = 0; + device->link_state = 0; // down + + ec_device_clear_stats(device); + + for (i = 0; i < EC_TX_RING_SIZE; i++) { + device->tx_skb[i]->dev = NULL; + } +} + +/****************************************************************************/ + +/** Opens the EtherCAT device. + * + * \return 0 in case of success, else < 0 + */ +int ec_device_open( + ec_device_t *device /**< EtherCAT device */ + ) +{ + int ret; + + if (!device->dev) { + EC_MASTER_ERR(device->master, "No net_device to open!\n"); + return -ENODEV; + } + + if (device->open) { + EC_MASTER_WARN(device->master, "Device already opened!\n"); + return 0; + } + + device->link_state = 0; + + ec_device_clear_stats(device); + + ret = device->dev->netdev_ops->ndo_open(device->dev); + if (!ret) + device->open = 1; + + return ret; +} + +/****************************************************************************/ + +/** Stops the EtherCAT device. + * + * \return 0 in case of success, else < 0 + */ +int ec_device_close( + ec_device_t *device /**< EtherCAT device */ + ) +{ + int ret; + + if (!device->dev) { + EC_MASTER_ERR(device->master, "No device to close!\n"); + return -ENODEV; + } + + if (!device->open) { + EC_MASTER_WARN(device->master, "Device already closed!\n"); + return 0; + } + + ret = device->dev->netdev_ops->ndo_stop(device->dev); + if (!ret) + device->open = 0; + + return ret; +} + +/****************************************************************************/ + +/** Returns a pointer to the device's transmit memory. + * + * \return pointer to the TX socket buffer + */ +uint8_t *ec_device_tx_data( + ec_device_t *device /**< EtherCAT device */ + ) +{ + /* cycle through socket buffers, because otherwise there is a race + * condition, if multiple frames are sent and the DMA is not scheduled in + * between. */ + device->tx_ring_index++; + device->tx_ring_index %= EC_TX_RING_SIZE; + return device->tx_skb[device->tx_ring_index]->data + ETH_HLEN; +} + +/****************************************************************************/ + +/** Sends the content of the transmit socket buffer. + * + * Cuts the socket buffer content to the (now known) size, and calls the + * start_xmit() function of the assigned net_device. + */ +void ec_device_send( + ec_device_t *device, /**< EtherCAT device */ + size_t size /**< number of bytes to send */ + ) +{ + struct sk_buff *skb = device->tx_skb[device->tx_ring_index]; + + // set the right length for the data + skb->len = ETH_HLEN + size; + + if (unlikely(device->master->debug_level > 1)) { + EC_MASTER_DBG(device->master, 2, "Sending frame:\n"); + ec_print_data(skb->data, ETH_HLEN + size); + } + + // start sending + if (device->dev->netdev_ops->ndo_start_xmit(skb, device->dev) == + NETDEV_TX_OK) + { + device->tx_count++; + device->master->device_stats.tx_count++; + device->tx_bytes += ETH_HLEN + size; + device->master->device_stats.tx_bytes += ETH_HLEN + size; +#ifdef EC_DEBUG_IF + ec_debug_send(&device->dbg, skb->data, ETH_HLEN + size); +#endif +#ifdef EC_DEBUG_RING + ec_device_debug_ring_append( + device, TX, skb->data + ETH_HLEN, size); +#endif + } else { + device->tx_errors++; + } +} + +/****************************************************************************/ + +/** Clears the frame statistics. + */ +void ec_device_clear_stats( + ec_device_t *device /**< EtherCAT device */ + ) +{ + unsigned int i; + + // zero frame statistics + device->tx_count = 0; + device->last_tx_count = 0; + device->rx_count = 0; + device->last_rx_count = 0; + device->tx_bytes = 0; + device->last_tx_bytes = 0; + device->rx_bytes = 0; + device->last_rx_bytes = 0; + device->tx_errors = 0; + + for (i = 0; i < EC_RATE_COUNT; i++) { + device->tx_frame_rates[i] = 0; + device->rx_frame_rates[i] = 0; + device->tx_byte_rates[i] = 0; + device->rx_byte_rates[i] = 0; + } +} + +/****************************************************************************/ + +#ifdef EC_DEBUG_RING +/** Appends frame data to the debug ring. + */ +void ec_device_debug_ring_append( + ec_device_t *device, /**< EtherCAT device */ + ec_debug_frame_dir_t dir, /**< direction */ + const void *data, /**< frame data */ + size_t size /**< data size */ + ) +{ + ec_debug_frame_t *df = &device->debug_frames[device->debug_frame_index]; + + df->dir = dir; + if (dir == TX) { + do_gettimeofday(&df->t); + } + else { + df->t = device->timeval_poll; + } + memcpy(df->data, data, size); + df->data_size = size; + + device->debug_frame_index++; + device->debug_frame_index %= EC_DEBUG_RING_SIZE; + if (unlikely(device->debug_frame_count < EC_DEBUG_RING_SIZE)) + device->debug_frame_count++; +} + +/****************************************************************************/ + +/** Outputs the debug ring. + */ +void ec_device_debug_ring_print( + const ec_device_t *device /**< EtherCAT device */ + ) +{ + int i; + unsigned int ring_index; + const ec_debug_frame_t *df; + struct timeval t0, diff; + + // calculate index of the newest frame in the ring to get its time + ring_index = (device->debug_frame_index + EC_DEBUG_RING_SIZE - 1) + % EC_DEBUG_RING_SIZE; + t0 = device->debug_frames[ring_index].t; + + EC_MASTER_DBG(device->master, 1, "Debug ring %u:\n", ring_index); + + // calculate index of the oldest frame in the ring + ring_index = (device->debug_frame_index + EC_DEBUG_RING_SIZE + - device->debug_frame_count) % EC_DEBUG_RING_SIZE; + + for (i = 0; i < device->debug_frame_count; i++) { + df = &device->debug_frames[ring_index]; + timersub(&t0, &df->t, &diff); + + EC_MASTER_DBG(device->master, 1, "Frame %u, dt=%u.%06u s, %s:\n", + i + 1 - device->debug_frame_count, + (unsigned int) diff.tv_sec, + (unsigned int) diff.tv_usec, + (df->dir == TX) ? "TX" : "RX"); + ec_print_data(df->data, df->data_size); + + ring_index++; + ring_index %= EC_DEBUG_RING_SIZE; + } +} +#endif + +/****************************************************************************/ + +/** Calls the poll function of the assigned net_device. + * + * The master itself works without using interrupts. Therefore the processing + * of received data and status changes of the network device has to be + * done by the master calling the ISR "manually". + */ +void ec_device_poll( + ec_device_t *device /**< EtherCAT device */ + ) +{ +#ifdef EC_HAVE_CYCLES + device->cycles_poll = get_cycles(); +#endif + device->jiffies_poll = jiffies; +#ifdef EC_DEBUG_RING + do_gettimeofday(&device->timeval_poll); +#endif + device->poll(device->dev); +} + +/****************************************************************************/ + +/** Update device statistics. + */ +void ec_device_update_stats( + ec_device_t *device /**< EtherCAT device */ + ) +{ + unsigned int i; + + s32 tx_frame_rate = (device->tx_count - device->last_tx_count) * 1000; + s32 rx_frame_rate = (device->rx_count - device->last_rx_count) * 1000; + s32 tx_byte_rate = (device->tx_bytes - device->last_tx_bytes); + s32 rx_byte_rate = (device->rx_bytes - device->last_rx_bytes); + + /* Low-pass filter: + * Y_n = y_(n - 1) + T / tau * (x - y_(n - 1)) | T = 1 + * -> Y_n += (x - y_(n - 1)) / tau + */ + for (i = 0; i < EC_RATE_COUNT; i++) { + s32 n = rate_intervals[i]; + device->tx_frame_rates[i] += + (tx_frame_rate - device->tx_frame_rates[i]) / n; + device->rx_frame_rates[i] += + (rx_frame_rate - device->rx_frame_rates[i]) / n; + device->tx_byte_rates[i] += + (tx_byte_rate - device->tx_byte_rates[i]) / n; + device->rx_byte_rates[i] += + (rx_byte_rate - device->rx_byte_rates[i]) / n; + } + + device->last_tx_count = device->tx_count; + device->last_rx_count = device->rx_count; + device->last_tx_bytes = device->tx_bytes; + device->last_rx_bytes = device->rx_bytes; +} + +/***************************************************************************** + * Device interface + ****************************************************************************/ + +/** Withdraws an EtherCAT device from the master. + * + * The device is disconnected from the master and all device ressources + * are freed. + * + * \attention Before calling this function, the ecdev_stop() function has + * to be called, to be sure that the master does not use the device + * any more. + * \ingroup DeviceInterface + */ +void ecdev_withdraw(ec_device_t *device /**< EtherCAT device */) +{ + ec_master_t *master = device->master; + char dev_str[20], mac_str[20]; + + ec_mac_print(device->dev->dev_addr, mac_str); + + if (device == &master->devices[EC_DEVICE_MAIN]) { + sprintf(dev_str, "main"); + } else if (device == &master->devices[EC_DEVICE_BACKUP]) { + sprintf(dev_str, "backup"); + } else { + EC_MASTER_WARN(master, "%s() called with unknown device %s!\n", + __func__, mac_str); + sprintf(dev_str, "UNKNOWN"); + } + + EC_MASTER_INFO(master, "Releasing %s device %s.\n", dev_str, mac_str); + + down(&master->device_sem); + ec_device_detach(device); + up(&master->device_sem); +} + +/****************************************************************************/ + +/** Opens the network device and makes the master enter IDLE phase. + * + * \return 0 on success, else < 0 + * \ingroup DeviceInterface + */ +int ecdev_open(ec_device_t *device /**< EtherCAT device */) +{ + int ret; + ec_master_t *master = device->master; + unsigned int all_open = 1, dev_idx; + + ret = ec_device_open(device); + if (ret) { + EC_MASTER_ERR(master, "Failed to open device: error %d!\n", ret); + return ret; + } + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(device->master); dev_idx++) { + if (!master->devices[dev_idx].open) { + all_open = 0; + break; + } + } + + if (all_open) { + ret = ec_master_enter_idle_phase(device->master); + if (ret) { + EC_MASTER_ERR(device->master, "Failed to enter IDLE phase!\n"); + return ret; + } + } + + return 0; +} + +/****************************************************************************/ + +/** Makes the master leave IDLE phase and closes the network device. + * + * \return 0 on success, else < 0 + * \ingroup DeviceInterface + */ +void ecdev_close(ec_device_t *device /**< EtherCAT device */) +{ + ec_master_t *master = device->master; + + if (master->phase == EC_IDLE) { + ec_master_leave_idle_phase(master); + } + + if (ec_device_close(device)) { + EC_MASTER_WARN(master, "Failed to close device!\n"); + } +} + +/****************************************************************************/ + +/** Accepts a received frame. + * + * Forwards the received data to the master. The master will analyze the frame + * and dispatch the received commands to the sending instances. + * + * The data have to begin with the Ethernet header (target MAC address). + * + * \ingroup DeviceInterface + */ +void ecdev_receive( + ec_device_t *device, /**< EtherCAT device */ + const void *data, /**< pointer to received data */ + size_t size /**< number of bytes received */ + ) +{ + const void *ec_data = data + ETH_HLEN; + size_t ec_size = size - ETH_HLEN; + + if (unlikely(!data)) { + EC_MASTER_WARN(device->master, "%s() called with NULL data.\n", + __func__); + return; + } + + device->rx_count++; + device->master->device_stats.rx_count++; + device->rx_bytes += size; + device->master->device_stats.rx_bytes += size; + + if (unlikely(device->master->debug_level > 1)) { + EC_MASTER_DBG(device->master, 2, "Received frame:\n"); + ec_print_data(data, size); + } + +#ifdef EC_DEBUG_IF + ec_debug_send(&device->dbg, data, size); +#endif +#ifdef EC_DEBUG_RING + ec_device_debug_ring_append(device, RX, ec_data, ec_size); +#endif + + ec_master_receive_datagrams(device->master, device, ec_data, ec_size); +} + +/****************************************************************************/ + +/** Sets a new link state. + * + * If the device notifies the master about the link being down, the master + * will not try to send frames using this device. + * + * \ingroup DeviceInterface + */ +void ecdev_set_link( + ec_device_t *device, /**< EtherCAT device */ + uint8_t state /**< new link state */ + ) +{ + if (unlikely(!device)) { + EC_WARN("ecdev_set_link() called with null device!\n"); + return; + } + + if (likely(state != device->link_state)) { + device->link_state = state; + EC_MASTER_INFO(device->master, + "Link state of %s changed to %s.\n", + device->dev->name, (state ? "UP" : "DOWN")); + } +} + +/****************************************************************************/ + +/** Reads the link state. + * + * \ingroup DeviceInterface + * + * \return Link state. + */ +uint8_t ecdev_get_link( + const ec_device_t *device /**< EtherCAT device */ + ) +{ + if (unlikely(!device)) { + EC_WARN("ecdev_get_link() called with null device!\n"); + return 0; + } + + return device->link_state; +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecdev_withdraw); +EXPORT_SYMBOL(ecdev_open); +EXPORT_SYMBOL(ecdev_close); +EXPORT_SYMBOL(ecdev_receive); +EXPORT_SYMBOL(ecdev_get_link); +EXPORT_SYMBOL(ecdev_set_link); + +/** \endcond */ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/device.h b/ubuntu/igh-ecat/master/device.h new file mode 100644 index 00000000000000..7743093130c7bc --- /dev/null +++ b/ubuntu/igh-ecat/master/device.h @@ -0,0 +1,150 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT device structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_DEVICE_H__ +#define __EC_DEVICE_H__ + +#include + +#include "../devices/ecdev.h" +#include "globals.h" + +/** + * Size of the transmit ring. + * This memory ring is used to transmit frames. It is necessary to use + * different memory regions, because otherwise the network device DMA could + * send the same data twice, if it is called twice. + */ +#define EC_TX_RING_SIZE 2 + +#ifdef EC_DEBUG_IF +#include "debug.h" +#endif + +#ifdef EC_DEBUG_RING +#define EC_DEBUG_RING_SIZE 10 + +typedef enum { + TX, RX +} ec_debug_frame_dir_t; + +typedef struct { + ec_debug_frame_dir_t dir; + struct timeval t; + uint8_t data[EC_MAX_DATA_SIZE]; + unsigned int data_size; +} ec_debug_frame_t; + +#endif + +/****************************************************************************/ + +/** + EtherCAT device. + An EtherCAT device is a network interface card, that is owned by an + EtherCAT master to send and receive EtherCAT frames with. +*/ + +struct ec_device +{ + ec_master_t *master; /**< EtherCAT master */ + struct net_device *dev; /**< pointer to the assigned net_device */ + ec_pollfunc_t poll; /**< pointer to the device's poll function */ + struct module *module; /**< pointer to the device's owning module */ + uint8_t open; /**< true, if the net_device has been opened */ + uint8_t link_state; /**< device link state */ + struct sk_buff *tx_skb[EC_TX_RING_SIZE]; /**< transmit skb ring */ + unsigned int tx_ring_index; /**< last ring entry used to transmit */ +#ifdef EC_HAVE_CYCLES + cycles_t cycles_poll; /**< cycles of last poll */ +#endif +#ifdef EC_DEBUG_RING + struct timeval timeval_poll; +#endif + unsigned long jiffies_poll; /**< jiffies of last poll */ + + // Frame statistics + u64 tx_count; /**< Number of frames sent. */ + u64 last_tx_count; /**< Number of frames sent of last statistics cycle. */ + u64 rx_count; /**< Number of frames received. */ + u64 last_rx_count; /**< Number of frames received of last statistics + cycle. */ + u64 tx_bytes; /**< Number of bytes sent. */ + u64 last_tx_bytes; /**< Number of bytes sent of last statistics cycle. */ + u64 rx_bytes; /**< Number of bytes received. */ + u64 last_rx_bytes; /**< Number of bytes received of last statistics cycle. + */ + u64 tx_errors; /**< Number of transmit errors. */ + s32 tx_frame_rates[EC_RATE_COUNT]; /**< Transmit rates in frames/s for + different statistics cycle periods. + */ + s32 rx_frame_rates[EC_RATE_COUNT]; /**< Receive rates in frames/s for + different statistics cycle periods. + */ + s32 tx_byte_rates[EC_RATE_COUNT]; /**< Transmit rates in byte/s for + different statistics cycle periods. */ + s32 rx_byte_rates[EC_RATE_COUNT]; /**< Receive rates in byte/s for + different statistics cycle periods. */ + +#ifdef EC_DEBUG_IF + ec_debug_t dbg; /**< debug device */ +#endif +#ifdef EC_DEBUG_RING + ec_debug_frame_t debug_frames[EC_DEBUG_RING_SIZE]; + unsigned int debug_frame_index; + unsigned int debug_frame_count; +#endif +}; + +/****************************************************************************/ + +int ec_device_init(ec_device_t *, ec_master_t *); +void ec_device_clear(ec_device_t *); + +void ec_device_attach(ec_device_t *, struct net_device *, ec_pollfunc_t, + struct module *); +void ec_device_detach(ec_device_t *); + +int ec_device_open(ec_device_t *); +int ec_device_close(ec_device_t *); + +void ec_device_poll(ec_device_t *); +uint8_t *ec_device_tx_data(ec_device_t *); +void ec_device_send(ec_device_t *, size_t); +void ec_device_clear_stats(ec_device_t *); +void ec_device_update_stats(ec_device_t *); + +#ifdef EC_DEBUG_RING +void ec_device_debug_ring_append(ec_device_t *, ec_debug_frame_dir_t, + const void *, size_t); +void ec_device_debug_ring_print(const ec_device_t *); +#endif + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/domain.c b/ubuntu/igh-ecat/master/domain.c new file mode 100644 index 00000000000000..d74fd715b0e162 --- /dev/null +++ b/ubuntu/igh-ecat/master/domain.c @@ -0,0 +1,719 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT domain methods. +*/ + +/****************************************************************************/ + +#include + +#include "globals.h" +#include "master.h" +#include "slave_config.h" + +#include "domain.h" +#include "datagram_pair.h" + +/** Extra debug output for redundancy functions. + */ +#define DEBUG_REDUNDANCY 0 + +/****************************************************************************/ + +// prototypes for private methods +void ec_domain_clear_data(ec_domain_t *); +int ec_domain_add_datagram_pair(ec_domain_t *, uint32_t, size_t, uint8_t *, + const unsigned int []); +int shall_count(const ec_fmmu_config_t *, const ec_fmmu_config_t *); +#if EC_MAX_NUM_DEVICES > 1 +int data_changed(uint8_t *, const ec_datagram_t *, size_t, size_t); +#endif + +/****************************************************************************/ + +/** Domain constructor. + */ +void ec_domain_init( + ec_domain_t *domain, /**< EtherCAT domain. */ + ec_master_t *master, /**< Parent master. */ + unsigned int index /**< Index. */ + ) +{ + unsigned int dev_idx; + + domain->master = master; + domain->index = index; + INIT_LIST_HEAD(&domain->fmmu_configs); + domain->data_size = 0; + domain->data = NULL; + domain->data_origin = EC_ORIG_INTERNAL; + domain->logical_base_address = 0x00000000; + INIT_LIST_HEAD(&domain->datagram_pairs); + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + domain->working_counter[dev_idx] = 0x0000; + } + domain->expected_working_counter = 0x0000; + domain->working_counter_changes = 0; + domain->redundancy_active = 0; + domain->notify_jiffies = 0; +} + +/****************************************************************************/ + +/** Domain destructor. + */ +void ec_domain_clear(ec_domain_t *domain /**< EtherCAT domain */) +{ + ec_datagram_pair_t *datagram_pair, *next_pair; + + // dequeue and free datagrams + list_for_each_entry_safe(datagram_pair, next_pair, + &domain->datagram_pairs, list) { + ec_datagram_pair_clear(datagram_pair); + kfree(datagram_pair); + } + + ec_domain_clear_data(domain); +} + +/****************************************************************************/ + +/** Frees internally allocated memory. + */ +void ec_domain_clear_data( + ec_domain_t *domain /**< EtherCAT domain. */ + ) +{ + if (domain->data_origin == EC_ORIG_INTERNAL && domain->data) { + kfree(domain->data); + } + + domain->data = NULL; + domain->data_origin = EC_ORIG_INTERNAL; +} + +/****************************************************************************/ + +/** Adds an FMMU configuration to the domain. + */ +void ec_domain_add_fmmu_config( + ec_domain_t *domain, /**< EtherCAT domain. */ + ec_fmmu_config_t *fmmu /**< FMMU configuration. */ + ) +{ + fmmu->domain = domain; + + domain->data_size += fmmu->data_size; + list_add_tail(&fmmu->list, &domain->fmmu_configs); + + EC_MASTER_DBG(domain->master, 1, "Domain %u:" + " Added %u bytes, total %zu.\n", + domain->index, fmmu->data_size, domain->data_size); +} + +/****************************************************************************/ + +/** Allocates a domain datagram pair and appends it to the list. + * + * The datagrams' types and expected working counters are determined by the + * number of input and output fmmus that share the datagrams. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_domain_add_datagram_pair( + ec_domain_t *domain, /**< EtherCAT domain. */ + uint32_t logical_offset, /**< Logical offset. */ + size_t data_size, /**< Size of the data. */ + uint8_t *data, /**< Process data. */ + const unsigned int used[] /**< Slave config counter for in/out. */ + ) +{ + ec_datagram_pair_t *datagram_pair; + int ret; + + if (!(datagram_pair = kmalloc(sizeof(ec_datagram_pair_t), GFP_KERNEL))) { + EC_MASTER_ERR(domain->master, + "Failed to allocate domain datagram pair!\n"); + return -ENOMEM; + } + + ret = ec_datagram_pair_init(datagram_pair, domain, logical_offset, data, + data_size, used); + if (ret) { + kfree(datagram_pair); + return ret; + } + + domain->expected_working_counter += + datagram_pair->expected_working_counter; + + EC_MASTER_DBG(domain->master, 1, + "Adding datagram pair with expected WC %u.\n", + datagram_pair->expected_working_counter); + + + list_add_tail(&datagram_pair->list, &domain->datagram_pairs); + return 0; +} + +/****************************************************************************/ + +/** Domain finish helper function. + * + * Detects, if a slave configuration has already been taken into account for + * a datagram's expected working counter calculation. + * + * Walks through the list of all FMMU configurations for the current datagram + * and ends before the current datagram. + * + * \return Non-zero if slave connfig was already counted. + */ +int shall_count( + const ec_fmmu_config_t *cur_fmmu, /**< Current FMMU with direction to + search for. */ + const ec_fmmu_config_t *first_fmmu /**< Datagram's first FMMU. */ + ) +{ + for (; first_fmmu != cur_fmmu; + first_fmmu = list_entry(first_fmmu->list.next, + ec_fmmu_config_t, list)) { + + if (first_fmmu->sc == cur_fmmu->sc + && first_fmmu->dir == cur_fmmu->dir) { + return 0; // was already counted + } + } + + return 1; +} + +/****************************************************************************/ + +/** Finishes a domain. + * + * This allocates the necessary datagrams and writes the correct logical + * addresses to every configured FMMU. + * + * \todo Check for FMMUs that do not fit into any datagram. + * + * \retval 0 Success + * \retval <0 Error code. + */ +int ec_domain_finish( + ec_domain_t *domain, /**< EtherCAT domain. */ + uint32_t base_address /**< Logical base address. */ + ) +{ + uint32_t datagram_offset; + size_t datagram_size; + unsigned int datagram_count; + unsigned int datagram_used[EC_DIR_COUNT]; + ec_fmmu_config_t *fmmu; + const ec_fmmu_config_t *datagram_first_fmmu = NULL; + const ec_datagram_pair_t *datagram_pair; + int ret; + + domain->logical_base_address = base_address; + + if (domain->data_size && domain->data_origin == EC_ORIG_INTERNAL) { + if (!(domain->data = + (uint8_t *) kmalloc(domain->data_size, GFP_KERNEL))) { + EC_MASTER_ERR(domain->master, "Failed to allocate %zu bytes" + " internal memory for domain %u!\n", + domain->data_size, domain->index); + return -ENOMEM; + } + } + + // Cycle through all domain FMMUs and + // - correct the logical base addresses + // - set up the datagrams to carry the process data + // - calculate the datagrams' expected working counters + datagram_offset = 0; + datagram_size = 0; + datagram_count = 0; + datagram_used[EC_DIR_OUTPUT] = 0; + datagram_used[EC_DIR_INPUT] = 0; + + if (!list_empty(&domain->fmmu_configs)) { + datagram_first_fmmu = + list_entry(domain->fmmu_configs.next, ec_fmmu_config_t, list); + } + + list_for_each_entry(fmmu, &domain->fmmu_configs, list) { + + // Correct logical FMMU address + fmmu->logical_start_address += base_address; + + // If the current FMMU's data do not fit in the current datagram, + // allocate a new one. + if (datagram_size + fmmu->data_size > EC_MAX_DATA_SIZE) { + ret = ec_domain_add_datagram_pair(domain, + domain->logical_base_address + datagram_offset, + datagram_size, domain->data + datagram_offset, + datagram_used); + if (ret < 0) + return ret; + + datagram_offset += datagram_size; + datagram_size = 0; + datagram_count++; + datagram_used[EC_DIR_OUTPUT] = 0; + datagram_used[EC_DIR_INPUT] = 0; + datagram_first_fmmu = fmmu; + } + + // Increment Input/Output counter to determine datagram types + // and calculate expected working counters + if (shall_count(fmmu, datagram_first_fmmu)) { + datagram_used[fmmu->dir]++; + } + + datagram_size += fmmu->data_size; + } + + /* Allocate last datagram pair, if data are left (this is also the case if + * the process data fit into a single datagram) */ + if (datagram_size) { + ret = ec_domain_add_datagram_pair(domain, + domain->logical_base_address + datagram_offset, + datagram_size, domain->data + datagram_offset, + datagram_used); + if (ret < 0) + return ret; + datagram_count++; + } + + EC_MASTER_INFO(domain->master, "Domain%u: Logical address 0x%08x," + " %zu byte, expected working counter %u.\n", domain->index, + domain->logical_base_address, domain->data_size, + domain->expected_working_counter); + + list_for_each_entry(datagram_pair, &domain->datagram_pairs, list) { + const ec_datagram_t *datagram = + &datagram_pair->datagrams[EC_DEVICE_MAIN]; + EC_MASTER_INFO(domain->master, " Datagram %s: Logical offset 0x%08x," + " %zu byte, type %s.\n", datagram->name, + EC_READ_U32(datagram->address), datagram->data_size, + ec_datagram_type_string(datagram)); + } + + return 0; +} + +/****************************************************************************/ + +/** Get the number of FMMU configurations of the domain. + */ +unsigned int ec_domain_fmmu_count(const ec_domain_t *domain) +{ + const ec_fmmu_config_t *fmmu; + unsigned int num = 0; + + list_for_each_entry(fmmu, &domain->fmmu_configs, list) { + num++; + } + + return num; +} + +/****************************************************************************/ + +/** Get a certain FMMU configuration via its position in the list. + * + * \return FMMU at position \a pos, or NULL. + */ +const ec_fmmu_config_t *ec_domain_find_fmmu( + const ec_domain_t *domain, /**< EtherCAT domain. */ + unsigned int pos /**< List position. */ + ) +{ + const ec_fmmu_config_t *fmmu; + + list_for_each_entry(fmmu, &domain->fmmu_configs, list) { + if (pos--) + continue; + return fmmu; + } + + return NULL; +} + +/****************************************************************************/ + +#if EC_MAX_NUM_DEVICES > 1 + +/** Process received data. + */ +int data_changed( + uint8_t *send_buffer, + const ec_datagram_t *datagram, + size_t offset, + size_t size + ) +{ + uint8_t *sent = send_buffer + offset; + uint8_t *recv = datagram->data + offset; + size_t i; + + for (i = 0; i < size; i++) { + if (recv[i] != sent[i]) { + return 1; + } + } + + return 0; +} + +#endif + +/***************************************************************************** + * Application interface + ****************************************************************************/ + +int ecrt_domain_reg_pdo_entry_list(ec_domain_t *domain, + const ec_pdo_entry_reg_t *regs) +{ + const ec_pdo_entry_reg_t *reg; + ec_slave_config_t *sc; + int ret; + + EC_MASTER_DBG(domain->master, 1, "ecrt_domain_reg_pdo_entry_list(" + "domain = 0x%p, regs = 0x%p)\n", domain, regs); + + for (reg = regs; reg->index; reg++) { + sc = ecrt_master_slave_config_err(domain->master, reg->alias, + reg->position, reg->vendor_id, reg->product_code); + if (IS_ERR(sc)) + return PTR_ERR(sc); + + ret = ecrt_slave_config_reg_pdo_entry(sc, reg->index, + reg->subindex, domain, reg->bit_position); + if (ret < 0) + return ret; + + *reg->offset = ret; + } + + return 0; +} + +/****************************************************************************/ + +size_t ecrt_domain_size(const ec_domain_t *domain) +{ + return domain->data_size; +} + +/****************************************************************************/ + +void ecrt_domain_external_memory(ec_domain_t *domain, uint8_t *mem) +{ + EC_MASTER_DBG(domain->master, 1, "ecrt_domain_external_memory(" + "domain = 0x%p, mem = 0x%p)\n", domain, mem); + + down(&domain->master->master_sem); + + ec_domain_clear_data(domain); + + domain->data = mem; + domain->data_origin = EC_ORIG_EXTERNAL; + + up(&domain->master->master_sem); +} + +/****************************************************************************/ + +uint8_t *ecrt_domain_data(const ec_domain_t *domain) +{ + return domain->data; +} + +/****************************************************************************/ + +int ecrt_domain_process(ec_domain_t *domain) +{ + uint16_t wc_sum[EC_MAX_NUM_DEVICES] = {}, wc_total; + ec_datagram_pair_t *pair; +#if EC_MAX_NUM_DEVICES > 1 + uint16_t datagram_pair_wc, redundant_wc; + unsigned int datagram_offset; + ec_fmmu_config_t *fmmu = list_first_entry(&domain->fmmu_configs, + ec_fmmu_config_t, list); + unsigned int redundancy; +#endif + unsigned int dev_idx; +#ifdef EC_RT_SYSLOG + unsigned int wc_change; +#endif + +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, "domain %u process\n", domain->index); +#endif + + list_for_each_entry(pair, &domain->datagram_pairs, list) { +#if EC_MAX_NUM_DEVICES > 1 + datagram_pair_wc = ec_datagram_pair_process(pair, wc_sum); +#else + ec_datagram_pair_process(pair, wc_sum); +#endif + +#if EC_MAX_NUM_DEVICES > 1 + if (ec_master_num_devices(domain->master) > 1) { + ec_datagram_t *main_datagram = &pair->datagrams[EC_DEVICE_MAIN]; + uint32_t logical_datagram_address = + EC_READ_U32(main_datagram->address); + size_t datagram_size = main_datagram->data_size; + +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, "dgram %s log=%u\n", + main_datagram->name, logical_datagram_address); +#endif + + /* Redundancy: Go through FMMU configs to detect data changes. */ + list_for_each_entry_from(fmmu, &domain->fmmu_configs, list) { + ec_datagram_t *backup_datagram = + &pair->datagrams[EC_DEVICE_BACKUP]; + + if (fmmu->dir != EC_DIR_INPUT) { + continue; + } + + if (fmmu->logical_start_address >= + logical_datagram_address + datagram_size) { + // fmmu data contained in next datagram pair + break; + } + + datagram_offset = + fmmu->logical_start_address - logical_datagram_address; + +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, + "input fmmu log=%u size=%u offset=%u\n", + fmmu->logical_start_address, fmmu->data_size, + datagram_offset); + if (domain->master->debug_level > 0) { + ec_print_data(pair->send_buffer + datagram_offset, + fmmu->data_size); + ec_print_data(main_datagram->data + datagram_offset, + fmmu->data_size); + ec_print_data(backup_datagram->data + datagram_offset, + fmmu->data_size); + } +#endif + + if (data_changed(pair->send_buffer, main_datagram, + datagram_offset, fmmu->data_size)) { + /* data changed on main link: no copying necessary. */ +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, "main changed\n"); +#endif + } else if (data_changed(pair->send_buffer, backup_datagram, + datagram_offset, fmmu->data_size)) { + /* data changed on backup link: copy to main memory. */ +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, "backup changed\n"); +#endif + memcpy(main_datagram->data + datagram_offset, + backup_datagram->data + datagram_offset, + fmmu->data_size); + } else if (datagram_pair_wc == + pair->expected_working_counter) { + /* no change, but WC complete: use main data. */ +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, + "no change but complete\n"); +#endif + } else { + /* no change and WC incomplete: mark WC as zero to avoid + * data.dependent WC flickering. */ + datagram_pair_wc = 0; +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, + "no change and incomplete\n"); +#endif + } + } + } +#endif // EC_MAX_NUM_DEVICES > 1 + } + +#if EC_MAX_NUM_DEVICES > 1 + redundant_wc = 0; + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + redundant_wc += wc_sum[dev_idx]; + } + + redundancy = redundant_wc > 0; + if (redundancy != domain->redundancy_active) { +#ifdef EC_RT_SYSLOG + if (redundancy) { + EC_MASTER_WARN(domain->master, + "Domain %u: Redundant link in use!\n", + domain->index); + } else { + EC_MASTER_INFO(domain->master, + "Domain %u: Redundant link unused again.\n", + domain->index); + } +#endif + domain->redundancy_active = redundancy; + } +#else + domain->redundancy_active = 0; +#endif + +#ifdef EC_RT_SYSLOG + wc_change = 0; +#endif + wc_total = 0; + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + if (wc_sum[dev_idx] != domain->working_counter[dev_idx]) { +#ifdef EC_RT_SYSLOG + wc_change = 1; +#endif + domain->working_counter[dev_idx] = wc_sum[dev_idx]; + } + wc_total += wc_sum[dev_idx]; + } + +#ifdef EC_RT_SYSLOG + if (wc_change) { + domain->working_counter_changes++; + } + + if (domain->working_counter_changes && + jiffies - domain->notify_jiffies > HZ) { + domain->notify_jiffies = jiffies; + if (domain->working_counter_changes == 1) { + EC_MASTER_INFO(domain->master, "Domain %u: Working counter" + " changed to %u/%u", domain->index, + wc_total, domain->expected_working_counter); + } else { + EC_MASTER_INFO(domain->master, "Domain %u: %u working counter" + " changes - now %u/%u", domain->index, + domain->working_counter_changes, + wc_total, domain->expected_working_counter); + } +#if EC_MAX_NUM_DEVICES > 1 + if (ec_master_num_devices(domain->master) > 1) { + printk(KERN_CONT " ("); + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); + dev_idx++) { + printk(KERN_CONT "%u", domain->working_counter[dev_idx]); + if (dev_idx + 1 < ec_master_num_devices(domain->master)) { + printk(KERN_CONT "+"); + } + } + printk(KERN_CONT ")"); + } +#endif + printk(KERN_CONT ".\n"); + + domain->working_counter_changes = 0; + } +#endif + return 0; +} + +/****************************************************************************/ + +int ecrt_domain_queue(ec_domain_t *domain) +{ + ec_datagram_pair_t *datagram_pair; + ec_device_index_t dev_idx; + + list_for_each_entry(datagram_pair, &domain->datagram_pairs, list) { + +#if EC_MAX_NUM_DEVICES > 1 + /* copy main data to send buffer */ + memcpy(datagram_pair->send_buffer, + datagram_pair->datagrams[EC_DEVICE_MAIN].data, + datagram_pair->datagrams[EC_DEVICE_MAIN].data_size); +#endif + ec_master_queue_datagram(domain->master, + &datagram_pair->datagrams[EC_DEVICE_MAIN]); + + /* copy main data to backup datagram */ + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + memcpy(datagram_pair->datagrams[dev_idx].data, + datagram_pair->datagrams[EC_DEVICE_MAIN].data, + datagram_pair->datagrams[EC_DEVICE_MAIN].data_size); + ec_master_queue_datagram(domain->master, + &datagram_pair->datagrams[dev_idx]); + } + } + return 0; +} + +/****************************************************************************/ + +int ecrt_domain_state(const ec_domain_t *domain, ec_domain_state_t *state) +{ + unsigned int dev_idx; + uint16_t wc = 0; + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + wc += domain->working_counter[dev_idx]; + } + + state->working_counter = wc; + + if (wc) { + if (wc == domain->expected_working_counter) { + state->wc_state = EC_WC_COMPLETE; + } else { + state->wc_state = EC_WC_INCOMPLETE; + } + } else { + state->wc_state = EC_WC_ZERO; + } + + state->redundancy_active = domain->redundancy_active; + return 0; +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_domain_reg_pdo_entry_list); +EXPORT_SYMBOL(ecrt_domain_size); +EXPORT_SYMBOL(ecrt_domain_external_memory); +EXPORT_SYMBOL(ecrt_domain_data); +EXPORT_SYMBOL(ecrt_domain_process); +EXPORT_SYMBOL(ecrt_domain_queue); +EXPORT_SYMBOL(ecrt_domain_state); + +/** \endcond */ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/domain.h b/ubuntu/igh-ecat/master/domain.h new file mode 100644 index 00000000000000..5408628b3f09a8 --- /dev/null +++ b/ubuntu/igh-ecat/master/domain.h @@ -0,0 +1,82 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT domain structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_DOMAIN_H__ +#define __EC_DOMAIN_H__ + +#include + +#include "globals.h" +#include "datagram.h" +#include "master.h" +#include "fmmu_config.h" + +/****************************************************************************/ + +/** EtherCAT domain. + * + * Handles the process data and the therefore needed datagrams of a certain + * group of slaves. + */ +struct ec_domain +{ + struct list_head list; /**< List item. */ + ec_master_t *master; /**< EtherCAT master owning the domain. */ + unsigned int index; /**< Index (just a number). */ + + struct list_head fmmu_configs; /**< FMMU configurations contained. */ + size_t data_size; /**< Size of the process data. */ + uint8_t *data; /**< Memory for the process data. */ + ec_origin_t data_origin; /**< Origin of the \a data memory. */ + uint32_t logical_base_address; /**< Logical offset address of the + process data. */ + struct list_head datagram_pairs; /**< Datagrams pairs (main/backup) for + process data exchange. */ + uint16_t working_counter[EC_MAX_NUM_DEVICES]; /**< Last working counter + values. */ + uint16_t expected_working_counter; /**< Expected working counter. */ + unsigned int working_counter_changes; /**< Working counter changes + since last notification. */ + unsigned int redundancy_active; /**< Non-zero, if redundancy is in use. */ + unsigned long notify_jiffies; /**< Time of last notification. */ +}; + +/****************************************************************************/ + +void ec_domain_init(ec_domain_t *, ec_master_t *, unsigned int); +void ec_domain_clear(ec_domain_t *); + +void ec_domain_add_fmmu_config(ec_domain_t *, ec_fmmu_config_t *); +int ec_domain_finish(ec_domain_t *, uint32_t); + +unsigned int ec_domain_fmmu_count(const ec_domain_t *); +const ec_fmmu_config_t *ec_domain_find_fmmu(const ec_domain_t *, unsigned int); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/doxygen.c b/ubuntu/igh-ecat/master/doxygen.c new file mode 100644 index 00000000000000..a036af2c8d5499 --- /dev/null +++ b/ubuntu/igh-ecat/master/doxygen.c @@ -0,0 +1,82 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +// This file only contains the doxygen mainpage. + +/** \file + * Doxygen mainpage only. + */ + +/****************************************************************************/ + +/** + \mainpage + + \section sec_general General information + + This HTML contains the complete code documentation. + + The API documentations are in the modules + section. + + A list of all native network card drivers can be found + here. + + A second userspace library can be used for a dry-run mode + or simulating Process Data. + + For information how to build and install, see the INSTALL file in the source + root. + + \section sec_contact Contact + + \verbatim + Florian Pose + Ingenieurgemeinschaft IgH + Nordsternstraße 66 + D-45329 Essen + http://igh.de + \endverbatim + + \section sec_license License + + \verbatim + Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + + This file is part of the IgH EtherCAT Master. + + The IgH EtherCAT Master is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License version 2, as + published by the Free Software Foundation. + + The IgH EtherCAT Master is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + Public License for more details. + + You should have received a copy of the GNU General Public License along + with the IgH EtherCAT Master; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + \endverbatim +*/ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/eoe_request.c b/ubuntu/igh-ecat/master/eoe_request.c new file mode 100644 index 00000000000000..f336cf340f411a --- /dev/null +++ b/ubuntu/igh-ecat/master/eoe_request.c @@ -0,0 +1,80 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Ethernet-over-EtherCAT request functions. + */ + +/****************************************************************************/ + +#include +#include +#include + +#include "eoe_request.h" + +/****************************************************************************/ + +/** EoE request constructor. + */ +void ec_eoe_request_init( + ec_eoe_request_t *req /**< EoE request. */ + ) +{ + INIT_LIST_HEAD(&req->list); + req->state = EC_INT_REQUEST_INIT; + req->jiffies_sent = 0U; + + req->mac_address_included = 0; + req->ip_address_included = 0; + req->subnet_mask_included = 0; + req->gateway_included = 0; + req->dns_included = 0; + req->name_included = 0; + + memset(req->mac_address, 0x00, ETH_ALEN); + req->ip_address.s_addr = 0; + req->subnet_mask.s_addr = 0; + req->gateway.s_addr = 0; + req->dns.s_addr = 0; + req->name[0] = 0x00; + + req->result = 0x0000; +} + +/****************************************************************************/ + +/** Checks if EoE request has something to set. + */ +int ec_eoe_request_valid( + const ec_eoe_request_t *req /**< EoE request. */ + ) +{ + return + req->mac_address_included || + req->ip_address_included || + req->subnet_mask_included || + req->gateway_included || + req->dns_included || + req->name_included; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/eoe_request.h b/ubuntu/igh-ecat/master/eoe_request.h new file mode 100644 index 00000000000000..6751f1f99b0973 --- /dev/null +++ b/ubuntu/igh-ecat/master/eoe_request.h @@ -0,0 +1,70 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2014 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT EoE request structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_EOE_REQUEST_H__ +#define __EC_EOE_REQUEST_H__ + +#include +#include // ETH_ALEN + +#include "globals.h" + +/****************************************************************************/ + +/** Ethernet-over-EtherCAT set IP parameter request. + */ +typedef struct { + struct list_head list; /**< List item. */ + ec_internal_request_state_t state; /**< Request state. */ + unsigned long jiffies_sent; /**< Jiffies, when the request was sent. */ + + uint8_t mac_address_included; + uint8_t ip_address_included; + uint8_t subnet_mask_included; + uint8_t gateway_included; + uint8_t dns_included; + uint8_t name_included; + + unsigned char mac_address[ETH_ALEN]; + struct in_addr ip_address; + struct in_addr subnet_mask; + struct in_addr gateway; + struct in_addr dns; + char name[EC_MAX_HOSTNAME_SIZE]; + + uint16_t result; +} ec_eoe_request_t; + +/****************************************************************************/ + +void ec_eoe_request_init(ec_eoe_request_t *); +int ec_eoe_request_valid(const ec_eoe_request_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/ethernet.c b/ubuntu/igh-ecat/master/ethernet.c new file mode 100644 index 00000000000000..55cff3119cd42c --- /dev/null +++ b/ubuntu/igh-ecat/master/ethernet.c @@ -0,0 +1,886 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Ethernet over EtherCAT (EoE). +*/ + +/****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "globals.h" +#include "master.h" +#include "slave.h" +#include "mailbox.h" +#include "ethernet.h" + +#if defined(CONFIG_SUSE_KERNEL) && LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) +#include +#else +# ifndef SUSE_VERSION +# define SUSE_VERSION 0 +# endif +# ifndef SUSE_PATCHLEVEL +# define SUSE_PATCHLEVEL 0 +# endif +#endif + +/****************************************************************************/ + +/** Defines the debug level of EoE processing. + * + * 0 = No debug messages. + * 1 = Output warnings. + * 2 = Output actions. + * 3 = Output actions and frame data. + */ +#define EOE_DEBUG_LEVEL 1 + +/** Size of the EoE tx queue. + */ +#define EC_EOE_TX_QUEUE_SIZE 100 + +/** Number of tries. + */ +#define EC_EOE_TRIES 100 + +/****************************************************************************/ + +// prototypes for private methods +void ec_eoe_flush(ec_eoe_t *); +int ec_eoe_send(ec_eoe_t *); + +/****************************************************************************/ + +// state functions +void ec_eoe_state_rx_start(ec_eoe_t *); +void ec_eoe_state_rx_check(ec_eoe_t *); +void ec_eoe_state_rx_fetch(ec_eoe_t *); +void ec_eoe_state_tx_start(ec_eoe_t *); +void ec_eoe_state_tx_sent(ec_eoe_t *); + +// net_device functions +int ec_eoedev_open(struct net_device *); +int ec_eoedev_stop(struct net_device *); +int ec_eoedev_tx(struct sk_buff *, struct net_device *); +struct net_device_stats *ec_eoedev_stats(struct net_device *); + +/****************************************************************************/ + +/** Device operations for EoE interfaces. + */ +static const struct net_device_ops ec_eoedev_ops = { + .ndo_open = ec_eoedev_open, + .ndo_stop = ec_eoedev_stop, + .ndo_start_xmit = ec_eoedev_tx, + .ndo_get_stats = ec_eoedev_stats, +}; + +/****************************************************************************/ + +/** EoE constructor. + * + * Initializes the EoE handler, creates a net_device and registers it. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_eoe_init( + ec_eoe_t *eoe, /**< EoE handler */ + ec_slave_t *slave /**< EtherCAT slave */ + ) +{ + ec_eoe_t **priv; + int ret = 0; + char name[EC_DATAGRAM_NAME_SIZE]; + u8 mac_addr[ETH_ALEN] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55}; + + eoe->slave = slave; + + ec_datagram_init(&eoe->datagram); + eoe->queue_datagram = 0; + eoe->state = ec_eoe_state_rx_start; + eoe->opened = 0; + eoe->rx_skb = NULL; + eoe->rx_expected_fragment = 0; + INIT_LIST_HEAD(&eoe->tx_queue); + eoe->tx_frame = NULL; + eoe->tx_queue_active = 0; + eoe->tx_queue_size = EC_EOE_TX_QUEUE_SIZE; + eoe->tx_queued_frames = 0; + + eoe->tx_frame_number = 0xFF; + memset(&eoe->stats, 0, sizeof(struct net_device_stats)); + + eoe->rx_counter = 0; + eoe->tx_counter = 0; + eoe->rx_rate = 0; + eoe->tx_rate = 0; + eoe->rate_jiffies = 0; + eoe->rx_idle = 1; + eoe->tx_idle = 1; + + /* device name eoe[as], because networking scripts don't + * like hyphens etc. in interface names. */ + if (slave->effective_alias) { + snprintf(name, EC_DATAGRAM_NAME_SIZE, + "eoe%ua%u", slave->master->index, slave->effective_alias); + } else { + snprintf(name, EC_DATAGRAM_NAME_SIZE, + "eoe%us%u", slave->master->index, slave->ring_position); + } + + snprintf(eoe->datagram.name, EC_DATAGRAM_NAME_SIZE, name); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) + eoe->dev = alloc_netdev(sizeof(ec_eoe_t *), name, NET_NAME_UNKNOWN, + ether_setup); +#else + eoe->dev = alloc_netdev(sizeof(ec_eoe_t *), name, ether_setup); +#endif + if (!eoe->dev) { + EC_SLAVE_ERR(slave, "Unable to allocate net_device %s" + " for EoE handler!\n", name); + ret = -ENODEV; + goto out_return; + } + + // initialize net_device + eoe->dev->netdev_ops = &ec_eoedev_ops; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) || (SUSE_VERSION == 15 && SUSE_PATCHLEVEL >= 5) + eth_hw_addr_set(eoe->dev, mac_addr); +#else + memcpy(eoe->dev->dev_addr, mac_addr, sizeof(mac_addr)); +#endif + + // initialize private data + priv = netdev_priv(eoe->dev); + *priv = eoe; + + // Usually setting the MTU appropriately makes the upper layers + // do the frame fragmenting. In some cases this doesn't work + // so the MTU is left on the Ethernet standard value and fragmenting + // is done "manually". +#if 0 + eoe->dev->mtu = slave->configured_rx_mailbox_size - ETH_HLEN - 10; +#endif + + // connect the net_device to the kernel + ret = register_netdev(eoe->dev); + if (ret) { + EC_SLAVE_ERR(slave, "Unable to register net_device:" + " error %i\n", ret); + goto out_free; + } + + // make the last address octet unique + mac_addr[ETH_ALEN - 1] = (uint8_t) eoe->dev->ifindex; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) || (SUSE_VERSION == 15 && SUSE_PATCHLEVEL >= 5) + eth_hw_addr_set(eoe->dev, mac_addr); +#else + memcpy(eoe->dev->dev_addr, mac_addr, sizeof(mac_addr)); +#endif + + return 0; + + out_free: + free_netdev(eoe->dev); + eoe->dev = NULL; + out_return: + return ret; +} + +/****************************************************************************/ + +/** EoE destructor. + * + * Unregisteres the net_device and frees allocated memory. + */ +void ec_eoe_clear(ec_eoe_t *eoe /**< EoE handler */) +{ + unregister_netdev(eoe->dev); // possibly calls close callback + + // empty transmit queue + ec_eoe_flush(eoe); + + if (eoe->tx_frame) { + dev_kfree_skb(eoe->tx_frame->skb); + kfree(eoe->tx_frame); + } + + if (eoe->rx_skb) + dev_kfree_skb(eoe->rx_skb); + + free_netdev(eoe->dev); + + ec_datagram_clear(&eoe->datagram); +} + +/****************************************************************************/ + +/** Empties the transmit queue. + */ +void ec_eoe_flush(ec_eoe_t *eoe /**< EoE handler */) +{ + ec_eoe_frame_t *frame, *next; + struct list_head tx_queue; + + netif_tx_lock_bh(eoe->dev); + + list_replace_init(&eoe->tx_queue, &tx_queue); + eoe->tx_queued_frames = 0; + + netif_tx_unlock_bh(eoe->dev); + + list_for_each_entry_safe(frame, next, &tx_queue, queue) { + list_del(&frame->queue); + dev_kfree_skb(frame->skb); + kfree(frame); + } +} + +/****************************************************************************/ + +/** Sends a frame or the next fragment. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_eoe_send(ec_eoe_t *eoe /**< EoE handler */) +{ + size_t remaining_size, current_size, complete_offset; + unsigned int last_fragment; + uint8_t *data; +#if EOE_DEBUG_LEVEL >= 3 + unsigned int i; +#endif + + remaining_size = eoe->tx_frame->skb->len - eoe->tx_offset; + + if (remaining_size <= eoe->slave->configured_tx_mailbox_size - 10) { + current_size = remaining_size; + last_fragment = 1; + } else { + current_size = ((eoe->slave->configured_tx_mailbox_size - 10) / 32) * 32; + last_fragment = 0; + } + + if (eoe->tx_fragment_number) { + complete_offset = eoe->tx_offset / 32; + } + else { + // complete size in 32 bit blocks, rounded up. + complete_offset = remaining_size / 32 + 1; + } + +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s TX sending fragment %u%s" + " with %zu octets (%zu). %u frames queued.\n", + eoe->dev->name, eoe->tx_fragment_number, + last_fragment ? "" : "+", current_size, complete_offset, + eoe->tx_queued_frames); +#endif + +#if EOE_DEBUG_LEVEL >= 3 + EC_SLAVE_DBG(eoe->slave, 0, ""); + for (i = 0; i < current_size; i++) { + printk(KERN_CONT "%02X ", + eoe->tx_frame->skb->data[eoe->tx_offset + i]); + if ((i + 1) % 16 == 0) { + printk(KERN_CONT "\n"); + EC_SLAVE_DBG(eoe->slave, 0, ""); + } + } + printk(KERN_CONT "\n"); +#endif + + data = ec_slave_mbox_prepare_send(eoe->slave, &eoe->datagram, + EC_MBOX_TYPE_EOE, current_size + 4); + if (IS_ERR(data)) + return PTR_ERR(data); + + EC_WRITE_U8 (data, EC_EOE_FRAMETYPE_INIT_REQ); // Initiate EoE Request + EC_WRITE_U8 (data + 1, last_fragment); + EC_WRITE_U16(data + 2, ((eoe->tx_fragment_number & 0x3F) | + (complete_offset & 0x3F) << 6 | + (eoe->tx_frame_number & 0x0F) << 12)); + + memcpy(data + 4, eoe->tx_frame->skb->data + eoe->tx_offset, current_size); + eoe->queue_datagram = 1; + + eoe->tx_offset += current_size; + eoe->tx_fragment_number++; + return 0; +} + +/****************************************************************************/ + +/** Runs the EoE state machine. + */ +void ec_eoe_run(ec_eoe_t *eoe /**< EoE handler */) +{ + if (!eoe->opened) + return; + + // if the datagram was not sent, or is not yet received, skip this cycle + if (eoe->queue_datagram || eoe->datagram.state == EC_DATAGRAM_SENT) + return; + + // call state function + eoe->state(eoe); + + // update statistics + if (jiffies - eoe->rate_jiffies > HZ) { + eoe->rx_rate = eoe->rx_counter; + eoe->tx_rate = eoe->tx_counter; + eoe->rx_counter = 0; + eoe->tx_counter = 0; + eoe->rate_jiffies = jiffies; + } + + ec_datagram_output_stats(&eoe->datagram); +} + +/****************************************************************************/ + +/** Queues the datagram, if necessary. + */ +void ec_eoe_queue(ec_eoe_t *eoe /**< EoE handler */) +{ + if (eoe->queue_datagram) { + ec_master_queue_datagram_ext(eoe->slave->master, &eoe->datagram); + eoe->queue_datagram = 0; + } +} + +/****************************************************************************/ + +/** Returns the state of the device. + * + * \return 1 if the device is "up", 0 if it is "down" + */ +int ec_eoe_is_open(const ec_eoe_t *eoe /**< EoE handler */) +{ + return eoe->opened; +} + +/****************************************************************************/ + +/** Returns the idle state. + * + * \retval 1 The device is idle. + * \retval 0 The device is busy. + */ +int ec_eoe_is_idle(const ec_eoe_t *eoe /**< EoE handler */) +{ + return eoe->rx_idle && eoe->tx_idle; +} + +/***************************************************************************** + * STATE PROCESSING FUNCTIONS + ****************************************************************************/ + +/** State: RX_START. + * + * Starts a new receiving sequence by queueing a datagram that checks the + * slave's mailbox for a new EoE datagram. + * + * \todo Use both devices. + */ +void ec_eoe_state_rx_start(ec_eoe_t *eoe /**< EoE handler */) +{ + if (eoe->slave->error_flag || + !eoe->slave->master->devices[EC_DEVICE_MAIN].link_state) { + eoe->rx_idle = 1; + eoe->tx_idle = 1; + return; + } + + ec_slave_mbox_prepare_check(eoe->slave, &eoe->datagram); + eoe->queue_datagram = 1; + eoe->state = ec_eoe_state_rx_check; +} + +/****************************************************************************/ + +/** State: RX_CHECK. + * + * Processes the checking datagram sent in RX_START and issues a receive + * datagram, if new data is available. + */ +void ec_eoe_state_rx_check(ec_eoe_t *eoe /**< EoE handler */) +{ + if (eoe->datagram.state != EC_DATAGRAM_RECEIVED) { + eoe->stats.rx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Failed to receive mbox" + " check datagram for %s.\n", eoe->dev->name); +#endif + eoe->state = ec_eoe_state_tx_start; + return; + } + + if (!ec_slave_mbox_check(&eoe->datagram)) { + eoe->rx_idle = 1; + eoe->state = ec_eoe_state_tx_start; + return; + } + + eoe->rx_idle = 0; + ec_slave_mbox_prepare_fetch(eoe->slave, &eoe->datagram); + eoe->queue_datagram = 1; + eoe->state = ec_eoe_state_rx_fetch; +} + +/****************************************************************************/ + +/** State: RX_FETCH. + * + * Checks if the requested data of RX_CHECK was received and processes the EoE + * datagram. + */ +void ec_eoe_state_rx_fetch(ec_eoe_t *eoe /**< EoE handler */) +{ + size_t rec_size, data_size; + uint8_t *data, frame_type, last_fragment, time_appended, mbox_prot; + uint8_t fragment_offset, fragment_number; +#if EOE_DEBUG_LEVEL >= 2 + uint8_t frame_number; +#endif + off_t offset; +#if EOE_DEBUG_LEVEL >= 3 + unsigned int i; +#endif + + if (eoe->datagram.state != EC_DATAGRAM_RECEIVED) { + eoe->stats.rx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Failed to receive mbox" + " fetch datagram for %s.\n", eoe->dev->name); +#endif + eoe->state = ec_eoe_state_tx_start; + return; + } + + data = ec_slave_mbox_fetch(eoe->slave, &eoe->datagram, + &mbox_prot, &rec_size); + if (IS_ERR(data)) { + eoe->stats.rx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Invalid mailbox response for %s.\n", + eoe->dev->name); +#endif + eoe->state = ec_eoe_state_tx_start; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_EOE) { // FIXME mailbox handler necessary + eoe->stats.rx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Other mailbox protocol response for %s.\n", + eoe->dev->name); +#endif + eoe->state = ec_eoe_state_tx_start; + return; + } + + frame_type = EC_READ_U16(data) & 0x000F; + + if (frame_type != EC_EOE_FRAMETYPE_INIT_REQ) { // EoE Fragment Data +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "%s: Other frame received." + " Dropping.\n", eoe->dev->name); +#endif + eoe->stats.rx_dropped++; + eoe->state = ec_eoe_state_tx_start; + return; + } + + // EoE Fragment Request received + + last_fragment = (EC_READ_U16(data) >> 8) & 0x0001; + time_appended = (EC_READ_U16(data) >> 9) & 0x0001; + fragment_number = EC_READ_U16(data + 2) & 0x003F; + fragment_offset = (EC_READ_U16(data + 2) >> 6) & 0x003F; +#if EOE_DEBUG_LEVEL >= 2 + frame_number = (EC_READ_U16(data + 2) >> 12) & 0x000F; +#endif + +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s RX fragment %u%s, offset %u," + " frame %u%s, %zu octets\n", eoe->dev->name, fragment_number, + last_fragment ? "" : "+", fragment_offset, frame_number, + time_appended ? ", + timestamp" : "", + time_appended ? rec_size - 8 : rec_size - 4); +#endif + +#if EOE_DEBUG_LEVEL >= 3 + EC_SLAVE_DBG(eoe->slave, 0, ""); + for (i = 0; i < rec_size - 4; i++) { + printk(KERN_CONT "%02X ", data[i + 4]); + if ((i + 1) % 16 == 0) { + printk(KERN_CONT "\n"); + EC_SLAVE_DBG(eoe->slave, 0, ""); + } + } + printk(KERN_CONT "\n"); +#endif + + data_size = time_appended ? rec_size - 8 : rec_size - 4; + + if (!fragment_number) { + if (eoe->rx_skb) { + EC_SLAVE_WARN(eoe->slave, "EoE RX freeing old socket buffer.\n"); + dev_kfree_skb(eoe->rx_skb); + } + + // new socket buffer + if (!(eoe->rx_skb = dev_alloc_skb(fragment_offset * 32))) { + if (printk_ratelimit()) + EC_SLAVE_WARN(eoe->slave, "EoE RX low on mem," + " frame dropped.\n"); + eoe->stats.rx_dropped++; + eoe->state = ec_eoe_state_tx_start; + return; + } + + eoe->rx_skb_offset = 0; + eoe->rx_skb_size = fragment_offset * 32; + eoe->rx_expected_fragment = 0; + } + else { + if (!eoe->rx_skb) { + eoe->stats.rx_dropped++; + eoe->state = ec_eoe_state_tx_start; + return; + } + + offset = fragment_offset * 32; + if (offset != eoe->rx_skb_offset || + offset + data_size > eoe->rx_skb_size || + fragment_number != eoe->rx_expected_fragment) { + dev_kfree_skb(eoe->rx_skb); + eoe->rx_skb = NULL; + eoe->stats.rx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Fragmenting error at %s.\n", + eoe->dev->name); +#endif + eoe->state = ec_eoe_state_tx_start; + return; + } + } + + // copy fragment into socket buffer + memcpy(skb_put(eoe->rx_skb, data_size), data + 4, data_size); + eoe->rx_skb_offset += data_size; + + if (last_fragment) { + // update statistics + eoe->stats.rx_packets++; + eoe->stats.rx_bytes += eoe->rx_skb->len; + eoe->rx_counter += eoe->rx_skb->len; + +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s RX frame completed" + " with %u octets.\n", eoe->dev->name, eoe->rx_skb->len); +#endif + + // pass socket buffer to network stack + eoe->rx_skb->dev = eoe->dev; + eoe->rx_skb->protocol = eth_type_trans(eoe->rx_skb, eoe->dev); + eoe->rx_skb->ip_summed = CHECKSUM_UNNECESSARY; + if (netif_rx(eoe->rx_skb)) { + EC_SLAVE_WARN(eoe->slave, "EoE RX netif_rx failed.\n"); + } + eoe->rx_skb = NULL; + + eoe->state = ec_eoe_state_tx_start; + } + else { + eoe->rx_expected_fragment++; +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s RX expecting fragment %u\n", + eoe->dev->name, eoe->rx_expected_fragment); +#endif + eoe->state = ec_eoe_state_rx_start; + } +} + +/****************************************************************************/ + +/** State: TX START. + * + * Starts a new transmit sequence. If no data is available, a new receive + * sequence is started instead. + * + * \todo Use both devices. + */ +void ec_eoe_state_tx_start(ec_eoe_t *eoe /**< EoE handler */) +{ +#if EOE_DEBUG_LEVEL >= 2 + unsigned int wakeup = 0; +#endif + + if (eoe->slave->error_flag || + !eoe->slave->master->devices[EC_DEVICE_MAIN].link_state) { + eoe->rx_idle = 1; + eoe->tx_idle = 1; + return; + } + + netif_tx_lock_bh(eoe->dev); + + if (!eoe->tx_queued_frames || list_empty(&eoe->tx_queue)) { + netif_tx_unlock_bh(eoe->dev); + eoe->tx_idle = 1; + // no data available. + // start a new receive immediately. + ec_eoe_state_rx_start(eoe); + return; + } + + // take the first frame out of the queue + eoe->tx_frame = list_entry(eoe->tx_queue.next, ec_eoe_frame_t, queue); + list_del(&eoe->tx_frame->queue); + if (!eoe->tx_queue_active && + eoe->tx_queued_frames == eoe->tx_queue_size / 2) { + netif_wake_queue(eoe->dev); + eoe->tx_queue_active = 1; +#if EOE_DEBUG_LEVEL >= 2 + wakeup = 1; +#endif + } + + eoe->tx_queued_frames--; + netif_tx_unlock_bh(eoe->dev); + + eoe->tx_idle = 0; + + eoe->tx_frame_number++; + eoe->tx_frame_number %= 16; + eoe->tx_fragment_number = 0; + eoe->tx_offset = 0; + + if (ec_eoe_send(eoe)) { + dev_kfree_skb(eoe->tx_frame->skb); + kfree(eoe->tx_frame); + eoe->tx_frame = NULL; + eoe->stats.tx_errors++; + eoe->state = ec_eoe_state_rx_start; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Send error at %s.\n", eoe->dev->name); +#endif + return; + } + +#if EOE_DEBUG_LEVEL >= 2 + if (wakeup) + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s waking up TX queue...\n", + eoe->dev->name); +#endif + + eoe->tries = EC_EOE_TRIES; + eoe->state = ec_eoe_state_tx_sent; +} + +/****************************************************************************/ + +/** State: TX SENT. + * + * Checks is the previous transmit datagram succeded and sends the next + * fragment, if necessary. + */ +void ec_eoe_state_tx_sent(ec_eoe_t *eoe /**< EoE handler */) +{ + if (eoe->datagram.state != EC_DATAGRAM_RECEIVED) { + if (eoe->tries) { + eoe->tries--; // try again + eoe->queue_datagram = 1; + } else { + eoe->stats.tx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Failed to receive send" + " datagram for %s after %u tries.\n", + eoe->dev->name, EC_EOE_TRIES); +#endif + eoe->state = ec_eoe_state_rx_start; + } + return; + } + + if (eoe->datagram.working_counter != 1) { + if (eoe->tries) { + eoe->tries--; // try again + eoe->queue_datagram = 1; + } else { + eoe->stats.tx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "No sending response" + " for %s after %u tries.\n", + eoe->dev->name, EC_EOE_TRIES); +#endif + eoe->state = ec_eoe_state_rx_start; + } + return; + } + + // frame completely sent + if (eoe->tx_offset >= eoe->tx_frame->skb->len) { + eoe->stats.tx_packets++; + eoe->stats.tx_bytes += eoe->tx_frame->skb->len; + eoe->tx_counter += eoe->tx_frame->skb->len; + dev_kfree_skb(eoe->tx_frame->skb); + kfree(eoe->tx_frame); + eoe->tx_frame = NULL; + eoe->state = ec_eoe_state_rx_start; + } + else { // send next fragment + if (ec_eoe_send(eoe)) { + dev_kfree_skb(eoe->tx_frame->skb); + kfree(eoe->tx_frame); + eoe->tx_frame = NULL; + eoe->stats.tx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Send error at %s.\n", eoe->dev->name); +#endif + eoe->state = ec_eoe_state_rx_start; + } + } +} + +/***************************************************************************** + * NET_DEVICE functions + ****************************************************************************/ + +/** Opens the virtual network device. + * + * \return Always zero (success). + */ +int ec_eoedev_open(struct net_device *dev /**< EoE net_device */) +{ + ec_eoe_t *eoe = *((ec_eoe_t **) netdev_priv(dev)); + ec_eoe_flush(eoe); + eoe->opened = 1; + eoe->rx_idle = 0; + eoe->tx_idle = 0; + netif_start_queue(dev); + eoe->tx_queue_active = 1; +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "%s opened.\n", dev->name); +#endif + return 0; +} + +/****************************************************************************/ + +/** Stops the virtual network device. + * + * \return Always zero (success). + */ +int ec_eoedev_stop(struct net_device *dev /**< EoE net_device */) +{ + ec_eoe_t *eoe = *((ec_eoe_t **) netdev_priv(dev)); + netif_stop_queue(dev); + eoe->rx_idle = 1; + eoe->tx_idle = 1; + eoe->tx_queue_active = 0; + eoe->opened = 0; + ec_eoe_flush(eoe); +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "%s stopped.\n", dev->name); +#endif + return 0; +} + +/****************************************************************************/ + +/** Transmits data via the virtual network device. + * + * \return Zero on success, non-zero on failure. + */ +int ec_eoedev_tx(struct sk_buff *skb, /**< transmit socket buffer */ + struct net_device *dev /**< EoE net_device */ + ) +{ + ec_eoe_t *eoe = *((ec_eoe_t **) netdev_priv(dev)); + ec_eoe_frame_t *frame; + +#if 0 + if (skb->len > eoe->slave->configured_tx_mailbox_size - 10) { + EC_SLAVE_WARN(eoe->slave, "EoE TX frame (%u octets)" + " exceeds MTU. dropping.\n", skb->len); + dev_kfree_skb(skb); + eoe->stats.tx_dropped++; + return 0; + } +#endif + + WARN_ON_ONCE(skb_get_queue_mapping(skb) != 0); + lockdep_assert_held(&netdev_get_tx_queue(dev, 0)->_xmit_lock); + + if (!(frame = + (ec_eoe_frame_t *) kmalloc(sizeof(ec_eoe_frame_t), GFP_ATOMIC))) { + if (printk_ratelimit()) + EC_SLAVE_WARN(eoe->slave, "EoE TX: low on mem. frame dropped.\n"); + return 1; + } + + frame->skb = skb; + + list_add_tail(&frame->queue, &eoe->tx_queue); + eoe->tx_queued_frames++; + if (eoe->tx_queued_frames == eoe->tx_queue_size) { + netif_stop_queue(dev); + eoe->tx_queue_active = 0; + } + +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s TX queued frame" + " with %u octets (%u frames queued).\n", + eoe->dev->name, skb->len, eoe->tx_queued_frames); + if (!eoe->tx_queue_active) + EC_SLAVE_WARN(eoe->slave, "EoE TX queue is now full.\n"); +#endif + + return 0; +} + +/****************************************************************************/ + +/** Gets statistics about the virtual network device. + * + * \return Statistics. + */ +struct net_device_stats *ec_eoedev_stats( + struct net_device *dev /**< EoE net_device */ + ) +{ + ec_eoe_t *eoe = *((ec_eoe_t **) netdev_priv(dev)); + return &eoe->stats; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/ethernet.h b/ubuntu/igh-ecat/master/ethernet.h new file mode 100644 index 00000000000000..ef0a8810621a2e --- /dev/null +++ b/ubuntu/igh-ecat/master/ethernet.h @@ -0,0 +1,122 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Ethernet over EtherCAT (EoE) +*/ + +/****************************************************************************/ + +#ifndef __EC_ETHERNET_H__ +#define __EC_ETHERNET_H__ + +#include +#include + +#include "globals.h" +#include "slave.h" +#include "datagram.h" + +/****************************************************************************/ + +/** EoE frame types. + */ +enum { + EC_EOE_FRAMETYPE_INIT_REQ = 0x00, /** Initiate EoE Request. */ + EC_EOE_FRAMETYPE_SET_IP_REQ = 0x02, /** Set IP Parameter Request. */ + EC_EOE_FRAMETYPE_SET_IP_RES = 0x03, /** Set IP Parameter Response. */ + EC_EOE_FRAMETYPE_FILT_REQ = 0x04, /** Set Address Filter Request. */ + EC_EOE_FRAMETYPE_FILT_RES = 0x05, /** Set Address Filter Response. */ +}; + +/*****************************************************************************/ + +/** + Queued frame structure. +*/ + +typedef struct +{ + struct list_head queue; /**< list item */ + struct sk_buff *skb; /**< socket buffer */ +} +ec_eoe_frame_t; + +/****************************************************************************/ + +typedef struct ec_eoe ec_eoe_t; /**< \see ec_eoe */ + +/** + Ethernet over EtherCAT (EoE) handler. + The master creates one of these objects for each slave that supports the + EoE protocol. +*/ + +struct ec_eoe +{ + struct list_head list; /**< list item */ + ec_slave_t *slave; /**< pointer to the corresponding slave */ + ec_datagram_t datagram; /**< datagram */ + unsigned int queue_datagram; /**< the datagram is ready for queuing */ + void (*state)(ec_eoe_t *); /**< state function for the state machine */ + struct net_device *dev; /**< net_device for virtual ethernet device */ + struct net_device_stats stats; /**< device statistics */ + unsigned int opened; /**< net_device is opened */ + unsigned long rate_jiffies; /**< time of last rate output */ + + struct sk_buff *rx_skb; /**< current rx socket buffer */ + off_t rx_skb_offset; /**< current write pointer in the socket buffer */ + size_t rx_skb_size; /**< size of the allocated socket buffer memory */ + uint8_t rx_expected_fragment; /**< next expected fragment number */ + uint32_t rx_counter; /**< octets received during last second */ + uint32_t rx_rate; /**< receive rate (bps) */ + unsigned int rx_idle; /**< Idle flag. */ + + struct list_head tx_queue; /**< queue for frames to send */ + unsigned int tx_queue_size; /**< Transmit queue size. */ + unsigned int tx_queue_active; /**< kernel netif queue started */ + unsigned int tx_queued_frames; /**< number of frames in the queue */ + ec_eoe_frame_t *tx_frame; /**< current TX frame */ + uint8_t tx_frame_number; /**< number of the transmitted frame */ + uint8_t tx_fragment_number; /**< number of the fragment */ + size_t tx_offset; /**< number of octets sent */ + uint32_t tx_counter; /**< octets transmitted during last second */ + uint32_t tx_rate; /**< transmit rate (bps) */ + unsigned int tx_idle; /**< Idle flag. */ + + unsigned int tries; /**< Tries. */ +}; + +/****************************************************************************/ + +int ec_eoe_init(ec_eoe_t *, ec_slave_t *); +void ec_eoe_clear(ec_eoe_t *); +void ec_eoe_run(ec_eoe_t *); +void ec_eoe_queue(ec_eoe_t *); +int ec_eoe_is_open(const ec_eoe_t *); +int ec_eoe_is_idle(const ec_eoe_t *); + +/****************************************************************************/ + +#endif + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/flag.c b/ubuntu/igh-ecat/master/flag.c new file mode 100644 index 00000000000000..652d35b1729259 --- /dev/null +++ b/ubuntu/igh-ecat/master/flag.c @@ -0,0 +1,69 @@ +/***************************************************************************** + * + * Copyright (C) 2021 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Slave Configuration Feature Flag. + */ + +/****************************************************************************/ + +#include + +#include "flag.h" + +/****************************************************************************/ + +/** SDO request constructor. + */ +int ec_flag_init( + ec_flag_t *flag, /**< Feature flag. */ + const char *key, /**< Feature key. */ + int32_t value /**< Feature value. */ + ) +{ + if (!key || strlen(key) == 0) { + return -EINVAL; + } + + if (!(flag->key = (uint8_t *) kmalloc(strlen(key) + 1, GFP_KERNEL))) { + return -ENOMEM; + } + + strcpy(flag->key, key); // no strncpy, buffer is alloc'ed with strlen + flag->value = value; + return 0; +} + +/****************************************************************************/ + +/** SDO request destructor. + */ +void ec_flag_clear( + ec_flag_t *flag /**< Feature flag. */ + ) +{ + if (flag->key) { + kfree(flag->key); + flag->key = NULL; + } +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/flag.h b/ubuntu/igh-ecat/master/flag.h new file mode 100644 index 00000000000000..e7679c2f2bef99 --- /dev/null +++ b/ubuntu/igh-ecat/master/flag.h @@ -0,0 +1,51 @@ +/***************************************************************************** + * + * Copyright (C) 2021 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT Slave Configuration Feature Flag. +*/ + +/****************************************************************************/ + +#ifndef __EC_FLAG_H__ +#define __EC_FLAG_H__ + +#include + +/****************************************************************************/ + +/** Slave configutation feature flag. + */ +typedef struct { + struct list_head list; /**< List item. */ + char *key; /**< Flag key (null-terminated ASCII string. */ + int32_t value; /**< Flag value (meaning depends on key). */ +} ec_flag_t; + +/****************************************************************************/ + +int ec_flag_init(ec_flag_t *, const char *, int32_t); +void ec_flag_clear(ec_flag_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fmmu_config.c b/ubuntu/igh-ecat/master/fmmu_config.c new file mode 100644 index 00000000000000..9e247a46ddbe0b --- /dev/null +++ b/ubuntu/igh-ecat/master/fmmu_config.c @@ -0,0 +1,91 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT FMMU configuration methods. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "slave_config.h" +#include "master.h" + +#include "fmmu_config.h" + +/****************************************************************************/ + +/** FMMU configuration constructor. + * + * Inits an FMMU configuration, sets the logical start address and adds the + * process data size for the mapped PDOs of the given direction to the domain + * data size. + */ +void ec_fmmu_config_init( + ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */ + ec_slave_config_t *sc, /**< EtherCAT slave configuration. */ + ec_domain_t *domain, /**< EtherCAT domain. */ + uint8_t sync_index, /**< Sync manager index to use. */ + ec_direction_t dir /**< PDO direction. */ + ) +{ + INIT_LIST_HEAD(&fmmu->list); + fmmu->sc = sc; + fmmu->sync_index = sync_index; + fmmu->dir = dir; + + fmmu->logical_start_address = domain->data_size; + fmmu->data_size = ec_pdo_list_total_size( + &sc->sync_configs[sync_index].pdos); + + ec_domain_add_fmmu_config(domain, fmmu); +} + +/****************************************************************************/ + +/** Initializes an FMMU configuration page. + * + * The referenced memory (\a data) must be at least EC_FMMU_PAGE_SIZE bytes. + */ +void ec_fmmu_config_page( + const ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */ + const ec_sync_t *sync, /**< Sync manager. */ + uint8_t *data /**> Configuration page memory. */ + ) +{ + EC_CONFIG_DBG(fmmu->sc, 1, "FMMU: LogAddr 0x%08X, Size %3u," + " PhysAddr 0x%04X, SM%u, Dir %s\n", + fmmu->logical_start_address, fmmu->data_size, + sync->physical_start_address, fmmu->sync_index, + fmmu->dir == EC_DIR_INPUT ? "in" : "out"); + + EC_WRITE_U32(data, fmmu->logical_start_address); + EC_WRITE_U16(data + 4, fmmu->data_size); // size of fmmu + EC_WRITE_U8 (data + 6, 0x00); // logical start bit + EC_WRITE_U8 (data + 7, 0x07); // logical end bit + EC_WRITE_U16(data + 8, sync->physical_start_address); + EC_WRITE_U8 (data + 10, 0x00); // physical start bit + EC_WRITE_U8 (data + 11, fmmu->dir == EC_DIR_INPUT ? 0x01 : 0x02); + EC_WRITE_U16(data + 12, 0x0001); // enable + EC_WRITE_U16(data + 14, 0x0000); // reserved +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fmmu_config.h b/ubuntu/igh-ecat/master/fmmu_config.h new file mode 100644 index 00000000000000..a4c8dc8ab640f6 --- /dev/null +++ b/ubuntu/igh-ecat/master/fmmu_config.h @@ -0,0 +1,58 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT FMMU configuration structure. + */ + +/****************************************************************************/ + +#ifndef __EC_FMMU_CONFIG_H__ +#define __EC_FMMU_CONFIG_H__ + +#include "globals.h" +#include "sync.h" + +/****************************************************************************/ + +/** FMMU configuration. + */ +typedef struct { + struct list_head list; /**< List node used by domain. */ + const ec_slave_config_t *sc; /**< EtherCAT slave config. */ + const ec_domain_t *domain; /**< Domain. */ + uint8_t sync_index; /**< Index of sync manager to use. */ + ec_direction_t dir; /**< FMMU direction. */ + uint32_t logical_start_address; /**< Logical start address. */ + unsigned int data_size; /**< Covered PDO size. */ +} ec_fmmu_config_t; + +/****************************************************************************/ + +void ec_fmmu_config_init(ec_fmmu_config_t *, ec_slave_config_t *, + ec_domain_t *, uint8_t, ec_direction_t); + +void ec_fmmu_config_page(const ec_fmmu_config_t *, const ec_sync_t *, + uint8_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/foe.h b/ubuntu/igh-ecat/master/foe.h new file mode 100644 index 00000000000000..ae4fc4b1f44ae8 --- /dev/null +++ b/ubuntu/igh-ecat/master/foe.h @@ -0,0 +1,54 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * FoE defines. + */ + +#ifndef __FOE_H__ +#define __FOE_H__ + +/****************************************************************************/ + +/** FoE error enumeration type. + */ +typedef enum { + FOE_BUSY = 0, /**< Busy. */ + FOE_READY = 1, /**< Ready. */ + FOE_IDLE = 2, /**< Idle. */ + FOE_WC_ERROR = 3, /**< Working counter error. */ + FOE_RECEIVE_ERROR = 4, /**< Receive error. */ + FOE_PROT_ERROR = 5, /**< Protocol error. */ + FOE_NODATA_ERROR = 6, /**< No data error. */ + FOE_PACKETNO_ERROR = 7, /**< Packet number error. */ + FOE_OPCODE_ERROR = 8, /**< OpCode error. */ + FOE_TIMEOUT_ERROR = 9, /**< Timeout error. */ + FOE_SEND_RX_DATA_ERROR = 10, /**< Error sending received data. */ + FOE_RX_DATA_ACK_ERROR = 11, /**< Error acknowledging received data. */ + FOE_ACK_ERROR = 12, /**< Acknowledge error. */ + FOE_MBOX_FETCH_ERROR = 13, /**< Error fetching data from mailbox. */ + FOE_READ_NODATA_ERROR = 14, /**< No data while reading. */ + FOE_MBOX_PROT_ERROR = 15, /**< Mailbox protocol error. */ +} ec_foe_error_t; + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/foe_request.c b/ubuntu/igh-ecat/master/foe_request.c new file mode 100644 index 00000000000000..3b68f734c57910 --- /dev/null +++ b/ubuntu/igh-ecat/master/foe_request.c @@ -0,0 +1,195 @@ +/***************************************************************************** + * + * Copyright (C) 2008 Olav Zarges, imc Messsysteme GmbH + * Copyright (C) 2020 Florian Pose, IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * File-over-EtherCAT request functions. + */ + +/****************************************************************************/ + +#include +#include +#include +#include + +#include "foe_request.h" +#include "foe.h" + +/****************************************************************************/ + +/** Default timeout in ms to wait for FoE transfer responses. + */ +#define EC_FOE_REQUEST_RESPONSE_TIMEOUT 3000 + +/****************************************************************************/ + +// prototypes for private methods +void ec_foe_request_clear_data(ec_foe_request_t *); + +/****************************************************************************/ + +/** FoE request constructor. + */ +void ec_foe_request_init( + ec_foe_request_t *req, /**< FoE request. */ + uint8_t* file_name /** filename */) +{ + INIT_LIST_HEAD(&req->list); + req->buffer = NULL; + req->file_name = file_name; + req->buffer_size = 0; + req->data_size = 0; + req->dir = EC_DIR_INVALID; + req->issue_timeout = 0; // no timeout + req->response_timeout = EC_FOE_REQUEST_RESPONSE_TIMEOUT; + req->state = EC_INT_REQUEST_INIT; + req->result = FOE_BUSY; + req->error_code = 0x00000000; +} + +/****************************************************************************/ + +/** FoE request destructor. + */ +void ec_foe_request_clear( + ec_foe_request_t *req /**< FoE request. */ + ) +{ + ec_foe_request_clear_data(req); +} + +/****************************************************************************/ + +/** FoE request destructor. + */ +void ec_foe_request_clear_data( + ec_foe_request_t *req /**< FoE request. */ + ) +{ + if (req->buffer) { + vfree(req->buffer); + req->buffer = NULL; + } + + req->buffer_size = 0; + req->data_size = 0; +} + +/****************************************************************************/ + +/** Pre-allocates the data memory. + * + * If the internal \a buffer_size is already bigger than \a size, nothing is + * done. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_request_alloc( + ec_foe_request_t *req, /**< FoE request. */ + size_t size /**< Data size to allocate. */ + ) +{ + if (size <= req->buffer_size) { + return 0; + } + + ec_foe_request_clear_data(req); + + if (!(req->buffer = (uint8_t *) vmalloc(size))) { + EC_ERR("Failed to allocate %zu bytes of FoE memory.\n", size); + return -ENOMEM; + } + + req->buffer_size = size; + req->data_size = 0; + return 0; +} + +/****************************************************************************/ + +/** Copies FoE data from an external source. + * + * If the \a buffer_size is to small, new memory is allocated. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_request_copy_data( + ec_foe_request_t *req, /**< FoE request. */ + const uint8_t *source, /**< Source data. */ + size_t size /**< Number of bytes in \a source. */ + ) +{ + int ret; + + ret = ec_foe_request_alloc(req, size); + if (ret) { + return ret; + } + + memcpy(req->buffer, source, size); + req->data_size = size; + return 0; +} + +/****************************************************************************/ + +/** Checks, if the timeout was exceeded. + * + * \return non-zero if the timeout was exceeded, else zero. + */ +int ec_foe_request_timed_out( + const ec_foe_request_t *req /**< FoE request. */ + ) +{ + return req->issue_timeout + && jiffies - req->jiffies_start > HZ * req->issue_timeout / 1000; +} + +/****************************************************************************/ + +/** Prepares a read request (slave to master). + */ +void ec_foe_request_read( + ec_foe_request_t *req /**< FoE request. */ + ) +{ + req->dir = EC_DIR_INPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->result = FOE_BUSY; + req->jiffies_start = jiffies; +} + +/****************************************************************************/ + +/** Prepares a write request (master to slave). + */ +void ec_foe_request_write( + ec_foe_request_t *req /**< FoE request. */ + ) +{ + req->dir = EC_DIR_OUTPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->result = FOE_BUSY; + req->jiffies_start = jiffies; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/foe_request.h b/ubuntu/igh-ecat/master/foe_request.h new file mode 100644 index 00000000000000..ba5ceb661e99d1 --- /dev/null +++ b/ubuntu/igh-ecat/master/foe_request.h @@ -0,0 +1,78 @@ +/***************************************************************************** + * + * Copyright (C) 2008 Olav Zarges, imc Messsysteme GmbH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT FoE request structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_FOE_REQUEST_H__ +#define __EC_FOE_REQUEST_H__ + +#include + +#include "../include/ecrt.h" + +#include "globals.h" + +/****************************************************************************/ + +/** FoE request. + */ +typedef struct { + struct list_head list; /**< List item. */ + uint8_t *buffer; /**< Pointer to FoE data. */ + size_t buffer_size; /**< Size of FoE data memory. */ + size_t data_size; /**< Size of FoE data. */ + + uint32_t issue_timeout; /**< Maximum time in ms, the processing of the + request may take. */ + uint32_t response_timeout; /**< Maximum time in ms, the transfer is + retried, if the slave does not respond. */ + ec_direction_t dir; /**< Direction. EC_DIR_OUTPUT means downloading to + the slave, EC_DIR_INPUT means uploading from the + slave. */ + ec_internal_request_state_t state; /**< FoE request state. */ + unsigned long jiffies_start; /**< Jiffies, when the request was issued. */ + unsigned long jiffies_sent; /**< Jiffies, when the upload/download + request was sent. */ + uint8_t *file_name; /**< Pointer to the filename. */ + uint32_t result; /**< FoE request abort code. Zero on success. */ + uint32_t error_code; /**< Error code from an FoE Error Request. */ +} ec_foe_request_t; + +/****************************************************************************/ + +void ec_foe_request_init(ec_foe_request_t *, uint8_t *file_name); +void ec_foe_request_clear(ec_foe_request_t *); + +int ec_foe_request_alloc(ec_foe_request_t *, size_t); +int ec_foe_request_copy_data(ec_foe_request_t *, const uint8_t *, size_t); +int ec_foe_request_timed_out(const ec_foe_request_t *); + +void ec_foe_request_write(ec_foe_request_t *); +void ec_foe_request_read(ec_foe_request_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_change.c b/ubuntu/igh-ecat/master/fsm_change.c new file mode 100644 index 00000000000000..98fae1847acf33 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_change.c @@ -0,0 +1,615 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT state change FSM. +*/ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "fsm_change.h" +#include "slave_config.h" + +/****************************************************************************/ + +unsigned int ec_fsm_change_timeout_ms(const ec_fsm_change_t *); + +void ec_fsm_change_state_start(ec_fsm_change_t *); +void ec_fsm_change_state_check(ec_fsm_change_t *); +void ec_fsm_change_state_status(ec_fsm_change_t *); +void ec_fsm_change_state_start_code(ec_fsm_change_t *); +void ec_fsm_change_state_code(ec_fsm_change_t *); +void ec_fsm_change_state_ack(ec_fsm_change_t *); +void ec_fsm_change_state_check_ack(ec_fsm_change_t *); +void ec_fsm_change_state_end(ec_fsm_change_t *); +void ec_fsm_change_state_error(ec_fsm_change_t *); + +/****************************************************************************/ + +/** + Constructor. +*/ + +void ec_fsm_change_init(ec_fsm_change_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< datagram */ + ) +{ + fsm->state = NULL; + fsm->datagram = datagram; + fsm->spontaneous_change = 0; +} + +/****************************************************************************/ + +/** + Destructor. +*/ + +void ec_fsm_change_clear(ec_fsm_change_t *fsm /**< finite state machine */) +{ +} + +/****************************************************************************/ + +/** Get timeout in ms. + * + * For defaults see ETG2000_S_R_V1i0i15 section 5.3.6.2. + */ +unsigned int ec_fsm_change_timeout_ms( + const ec_fsm_change_t *fsm /**< finite state machine */ + ) +{ + ec_slave_state_t from = fsm->old_state; + ec_slave_state_t to = fsm->requested_state; + + /* Search for specified timeout in slave configuration */ + if (fsm->slave->config) { + unsigned int timeout_ms = + ec_slave_config_al_timeout(fsm->slave->config, from, to); + if (timeout_ms) { + return timeout_ms; + } + } + + /* No specific timeout found. Use defaults from spec. */ + + if (from == EC_SLAVE_STATE_INIT && + (to == EC_SLAVE_STATE_PREOP || to == EC_SLAVE_STATE_BOOT)) { + return 3000; // PreopTimeout + } + if ((from == EC_SLAVE_STATE_PREOP && to == EC_SLAVE_STATE_SAFEOP) || + (from == EC_SLAVE_STATE_SAFEOP && to == EC_SLAVE_STATE_OP)) { + return 10000; // SafeopOpTimeout + } + if (to == EC_SLAVE_STATE_INIT || + ((from == EC_SLAVE_STATE_OP || from == EC_SLAVE_STATE_SAFEOP) + && to == EC_SLAVE_STATE_PREOP)) { + return 5000; // BackToInitTimeout + } + if (from == EC_SLAVE_STATE_OP && to == EC_SLAVE_STATE_SAFEOP) { + return 200; // BackToSafeopTimeout + } + + return 10000; // default [ms] +} + +/****************************************************************************/ + +/** + Starts the change state machine. +*/ + +void ec_fsm_change_start(ec_fsm_change_t *fsm, /**< finite state machine */ + ec_slave_t *slave, /**< EtherCAT slave */ + ec_slave_state_t state /**< requested state */ + ) +{ + fsm->mode = EC_FSM_CHANGE_MODE_FULL; + fsm->slave = slave; + fsm->requested_state = state; + fsm->state = ec_fsm_change_state_start; +} + +/****************************************************************************/ + +/** + Starts the change state machine to only acknowlegde a slave's state. +*/ + +void ec_fsm_change_ack(ec_fsm_change_t *fsm, /**< finite state machine */ + ec_slave_t *slave /**< EtherCAT slave */ + ) +{ + fsm->mode = EC_FSM_CHANGE_MODE_ACK_ONLY; + fsm->slave = slave; + fsm->requested_state = EC_SLAVE_STATE_UNKNOWN; + fsm->state = ec_fsm_change_state_start_code; +} + +/****************************************************************************/ + +/** + Executes the current state of the state machine. + \return false, if the state machine has terminated +*/ + +int ec_fsm_change_exec(ec_fsm_change_t *fsm /**< finite state machine */) +{ + fsm->state(fsm); + + return fsm->state != ec_fsm_change_state_end + && fsm->state != ec_fsm_change_state_error; +} + +/****************************************************************************/ + +/** + Returns, if the state machine terminated with success. + \return non-zero if successful. +*/ + +int ec_fsm_change_success(ec_fsm_change_t *fsm /**< Finite state machine */) +{ + return fsm->state == ec_fsm_change_state_end; +} + +/***************************************************************************** + * state change state machine + ****************************************************************************/ + +/** + Change state: START. +*/ + +void ec_fsm_change_state_start(ec_fsm_change_t *fsm + /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + fsm->take_time = 1; + fsm->old_state = fsm->slave->current_state; + + // write new state to slave + ec_datagram_fpwr(datagram, slave->station_address, 0x0120, 2); + EC_WRITE_U16(datagram->data, fsm->requested_state); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_change_state_check; +} + +/****************************************************************************/ + +/** + Change state: CHECK. +*/ + +void ec_fsm_change_state_check(ec_fsm_change_t *fsm + /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to receive state datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (fsm->take_time) { + fsm->take_time = 0; + fsm->jiffies_start = datagram->jiffies_sent; + } + + if (datagram->working_counter == 0) { + if (datagram->jiffies_received - fsm->jiffies_start >= 3 * HZ) { + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(fsm->requested_state, state_str, 0); + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to set state %s: ", state_str); + ec_datagram_print_wc_error(datagram); + return; + } + + // repeat writing new state to slave + ec_datagram_fpwr(datagram, slave->station_address, 0x0120, 2); + EC_WRITE_U16(datagram->data, fsm->requested_state); + fsm->retries = EC_FSM_RETRIES; + return; + } + + if (unlikely(datagram->working_counter > 1)) { + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(fsm->requested_state, state_str, 0); + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to set state %s: ", state_str); + ec_datagram_print_wc_error(datagram); + return; + } + + fsm->take_time = 1; + + // read AL status from slave + ec_datagram_fprd(datagram, slave->station_address, 0x0130, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->spontaneous_change = 0; + fsm->state = ec_fsm_change_state_status; +} + +/****************************************************************************/ + +/** + Change state: STATUS. +*/ + +void ec_fsm_change_state_status(ec_fsm_change_t *fsm + /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + unsigned int timeout_ms; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to receive state checking datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + char req_state[EC_STATE_STRING_SIZE]; + ec_state_string(fsm->requested_state, req_state, 0); + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to check state %s: ", req_state); + ec_datagram_print_wc_error(datagram); + return; + } + + if (fsm->take_time) { + fsm->take_time = 0; + fsm->jiffies_start = datagram->jiffies_sent; + } + + slave->current_state = EC_READ_U8(datagram->data); + + if (slave->current_state == fsm->requested_state) { + // state has been set successfully + fsm->state = ec_fsm_change_state_end; + return; + } + + if (slave->current_state != fsm->old_state) { // state changed + char req_state[EC_STATE_STRING_SIZE], cur_state[EC_STATE_STRING_SIZE]; + + ec_state_string(slave->current_state, cur_state, 0); + + if ((slave->current_state & 0x0F) != (fsm->old_state & 0x0F)) { + // Slave spontaneously changed its state just before the new state + // was written. Accept current state as old state and wait for + // state change + fsm->spontaneous_change = 1; + fsm->old_state = slave->current_state; + EC_SLAVE_WARN(slave, "Changed to %s in the meantime.\n", + cur_state); + goto check_again; + } + + // state change error + + slave->error_flag = 1; + ec_state_string(fsm->requested_state, req_state, 0); + + EC_SLAVE_ERR(slave, "Failed to set %s state, slave refused state" + " change (%s).\n", req_state, cur_state); + + ec_fsm_change_state_start_code(fsm); + return; + } + + // still old state + + timeout_ms = ec_fsm_change_timeout_ms(fsm); + if (datagram->jiffies_received - fsm->jiffies_start >= + timeout_ms * HZ / 1000) { + // timeout while checking + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(fsm->requested_state, state_str, 0); + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Timeout after %u ms while setting state %s.\n", + timeout_ms, state_str); + return; + } + + check_again: + // no timeout yet. check again + ec_datagram_fprd(datagram, slave->station_address, 0x0130, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; +} + +/****************************************************************************/ + +/** Enter reading AL status code. + */ +void ec_fsm_change_state_start_code( + ec_fsm_change_t *fsm /**< finite state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + + // fetch AL status error code + ec_datagram_fprd(datagram, slave->station_address, 0x0134, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_change_state_code; +} + +/****************************************************************************/ + +/** + Application layer status messages. +*/ + +const ec_code_msg_t al_status_messages[] = { + {0x0000, "No error"}, + {0x0001, "Unspecified error"}, + {0x0002, "No Memory"}, + {0x0011, "Invalid requested state change"}, + {0x0012, "Unknown requested state"}, + {0x0013, "Bootstrap not supported"}, + {0x0014, "No valid firmware"}, + {0x0015, "Invalid mailbox configuration"}, + {0x0016, "Invalid mailbox configuration"}, + {0x0017, "Invalid sync manager configuration"}, + {0x0018, "No valid inputs available"}, + {0x0019, "No valid outputs"}, + {0x001A, "Synchronization error"}, + {0x001B, "Sync manager watchdog"}, + {0x001C, "Invalid sync manager types"}, + {0x001D, "Invalid output configuration"}, + {0x001E, "Invalid input configuration"}, + {0x001F, "Invalid watchdog configuration"}, + {0x0020, "Slave needs cold start"}, + {0x0021, "Slave needs INIT"}, + {0x0022, "Slave needs PREOP"}, + {0x0023, "Slave needs SAFEOP"}, + {0x0024, "Invalid Input Mapping"}, + {0x0025, "Invalid Output Mapping"}, + {0x0026, "Inconsistent Settings"}, + {0x0027, "Freerun not supported"}, + {0x0028, "Synchronization not supported"}, + {0x0029, "Freerun needs 3 Buffer Mode"}, + {0x002A, "Background Watchdog"}, + {0x002B, "No Valid Inputs and Outputs"}, + {0x002C, "Fatal Sync Error"}, + {0x002D, "No Sync Error"}, + {0x0030, "Invalid DC SYNCH configuration"}, + {0x0031, "Invalid DC latch configuration"}, + {0x0032, "PLL error"}, + {0x0033, "DC Sync IO Error"}, + {0x0034, "DC Sync Timeout Error"}, + {0x0035, "DC Invalid Sync Cycle Time"}, + {0x0036, "DC Sync0 Cycle Time"}, + {0x0037, "DC Sync1 Cycle Time"}, + {0x0041, "MBX_AOE"}, + {0x0042, "MBX_EOE"}, + {0x0043, "MBX_COE"}, + {0x0044, "MBX_FOE"}, + {0x0045, "MBX_SOE"}, + {0x004F, "MBX_VOE"}, + {0x0050, "EEPROM No Access"}, + {0x0051, "EEPROM Error"}, + {0x0060, "Slave Restarted Locally"}, + {0xffff} +}; + + +/****************************************************************************/ + +/** + Change state: CODE. +*/ + +void ec_fsm_change_state_code(ec_fsm_change_t *fsm + /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + uint32_t code; + const ec_code_msg_t *al_msg; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed to receive" + " AL status code datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(fsm->slave, "Reception of AL status code" + " datagram failed: "); + ec_datagram_print_wc_error(datagram); + } else { + code = EC_READ_U16(datagram->data); + for (al_msg = al_status_messages; al_msg->code != 0xffff; al_msg++) { + if (al_msg->code != code) { + continue; + } + + EC_SLAVE_ERR(fsm->slave, "AL status message 0x%04X: \"%s\".\n", + al_msg->code, al_msg->message); + break; + } + if (al_msg->code == 0xffff) { /* not found in our list. */ + EC_SLAVE_ERR(fsm->slave, "Unknown AL status code 0x%04X.\n", + code); + } + } + + // acknowledge "old" slave state + ec_datagram_fpwr(datagram, fsm->slave->station_address, 0x0120, 2); + EC_WRITE_U16(datagram->data, fsm->slave->current_state); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_change_state_ack; +} + +/****************************************************************************/ + +/** + Change state: ACK. +*/ + +void ec_fsm_change_state_ack(ec_fsm_change_t *fsm /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to receive state ack datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Reception of state ack datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + fsm->take_time = 1; + + // read new AL status + ec_datagram_fprd(datagram, slave->station_address, 0x0130, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_change_state_check_ack; +} + +/****************************************************************************/ + +/** + Change state: CHECK ACK. +*/ + +void ec_fsm_change_state_check_ack(ec_fsm_change_t *fsm + /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + unsigned int timeout_ms; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to receive state ack check datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Reception of state ack check datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + if (fsm->take_time) { + fsm->take_time = 0; + fsm->jiffies_start = datagram->jiffies_sent; + } + + slave->current_state = EC_READ_U8(datagram->data); + + if (!(slave->current_state & EC_SLAVE_STATE_ACK_ERR)) { + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(slave->current_state, state_str, 0); + if (fsm->mode == EC_FSM_CHANGE_MODE_FULL) { + fsm->state = ec_fsm_change_state_error; + } + else { // EC_FSM_CHANGE_MODE_ACK_ONLY + fsm->state = ec_fsm_change_state_end; + } + EC_SLAVE_INFO(slave, "Acknowledged state %s.\n", state_str); + return; + } + + timeout_ms = ec_fsm_change_timeout_ms(fsm); + if (datagram->jiffies_received - fsm->jiffies_start >= + timeout_ms * HZ / 1000) { + // timeout while checking + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(slave->current_state, state_str, 0); + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Timeout after %u ms while acknowledging" + " state %s.\n", timeout_ms, state_str); + return; + } + + // reread new AL status + ec_datagram_fprd(datagram, slave->station_address, 0x0130, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; +} + +/****************************************************************************/ + +/** + State: ERROR. +*/ + +void ec_fsm_change_state_error(ec_fsm_change_t *fsm + /**< finite state machine */) +{ +} + +/****************************************************************************/ + +/** + State: END. +*/ + +void ec_fsm_change_state_end(ec_fsm_change_t *fsm + /**< finite state machine */) +{ +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_change.h b/ubuntu/igh-ecat/master/fsm_change.h new file mode 100644 index 00000000000000..c30ac257847912 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_change.h @@ -0,0 +1,84 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT state change FSM. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_CHANGE_H__ +#define __EC_FSM_CHANGE_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" + +/****************************************************************************/ + +/** + Mode of the change state machine. +*/ + +typedef enum { + EC_FSM_CHANGE_MODE_FULL, /**< full state change */ + EC_FSM_CHANGE_MODE_ACK_ONLY /**< only state acknowledgement */ +} +ec_fsm_change_mode_t; + +/****************************************************************************/ + +typedef struct ec_fsm_change ec_fsm_change_t; /**< \see ec_fsm_change */ + +/** + EtherCAT state change FSM. +*/ + +struct ec_fsm_change +{ + ec_slave_t *slave; /**< slave the FSM runs on */ + ec_datagram_t *datagram; /**< datagram used in the state machine */ + unsigned int retries; /**< retries upon datagram timeout */ + + void (*state)(ec_fsm_change_t *); /**< slave state change state function */ + ec_fsm_change_mode_t mode; /**< full state change, or ack only. */ + ec_slave_state_t requested_state; /**< input: state */ + ec_slave_state_t old_state; /**< prior slave state */ + unsigned long jiffies_start; /**< change timer */ + uint8_t take_time; /**< take sending timestamp */ + uint8_t spontaneous_change; /**< spontaneous state change detected */ +}; + +/****************************************************************************/ + +void ec_fsm_change_init(ec_fsm_change_t *, ec_datagram_t *); +void ec_fsm_change_clear(ec_fsm_change_t *); + +void ec_fsm_change_start(ec_fsm_change_t *, ec_slave_t *, ec_slave_state_t); +void ec_fsm_change_ack(ec_fsm_change_t *, ec_slave_t *); + +int ec_fsm_change_exec(ec_fsm_change_t *); +int ec_fsm_change_success(ec_fsm_change_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_coe.c b/ubuntu/igh-ecat/master/fsm_coe.c new file mode 100644 index 00000000000000..69765cd006ebac --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_coe.c @@ -0,0 +1,2537 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT CoE state machines. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "fsm_coe.h" +#include "slave_config.h" + +/****************************************************************************/ + +/** Maximum time in ms to wait for responses when reading out the dictionary. + */ +#define EC_FSM_COE_DICT_TIMEOUT 1000 + +/** CoE download request header size. + */ +#define EC_COE_DOWN_REQ_HEADER_SIZE 10 + +/** CoE download segment request header size. + */ +#define EC_COE_DOWN_SEG_REQ_HEADER_SIZE 3 + +/** Minimum size of download segment. + */ +#define EC_COE_DOWN_SEG_MIN_DATA_SIZE 7 + +/** Enable debug output for CoE retries. + */ +#define DEBUG_RETRIES 0 + +/** Enable warning output if transfers take too long. + */ +#define DEBUG_LONG 0 + +/****************************************************************************/ + +// prototypes for private methods +void ec_canopen_abort_msg(const ec_slave_t *, uint32_t); +int ec_fsm_coe_check_emergency(const ec_fsm_coe_t *, const uint8_t *, size_t); +int ec_fsm_coe_prepare_dict(ec_fsm_coe_t *, ec_datagram_t *); +int ec_fsm_coe_dict_prepare_desc(ec_fsm_coe_t *, ec_datagram_t *); +int ec_fsm_coe_dict_prepare_entry(ec_fsm_coe_t *, ec_datagram_t *); +int ec_fsm_coe_prepare_down_start(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_prepare_segment_request(ec_fsm_coe_t *, ec_datagram_t *); +int ec_fsm_coe_prepare_up(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_prepare_segment_request(ec_fsm_coe_t *, ec_datagram_t *); + +/****************************************************************************/ + +void ec_fsm_coe_dict_start(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_response(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_desc_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_desc_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_desc_response(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_entry_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_entry_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_entry_response(ec_fsm_coe_t *, ec_datagram_t *); + +void ec_fsm_coe_down_start(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_response(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_seg_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_seg_response(ec_fsm_coe_t *, ec_datagram_t *); + +void ec_fsm_coe_up_start(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_response(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_seg_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_seg_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_seg_response(ec_fsm_coe_t *, ec_datagram_t *); + +void ec_fsm_coe_end(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_error(ec_fsm_coe_t *, ec_datagram_t *); + +/****************************************************************************/ + +/** SDO abort messages. + * + * The "abort SDO transfer request" supplies an abort code, which can be + * translated to clear text. This table does the mapping of the codes and + * messages. + */ +const ec_code_msg_t sdo_abort_messages[] = { + {0x05030000, "Toggle bit not changed"}, + {0x05040000, "SDO protocol timeout"}, + {0x05040001, "Client/Server command specifier not valid or unknown"}, + {0x05040005, "Out of memory"}, + {0x06010000, "Unsupported access to an object"}, + {0x06010001, "Attempt to read a write-only object"}, + {0x06010002, "Attempt to write a read-only object"}, + {0x06020000, "This object does not exist in the object directory"}, + {0x06040041, "The object cannot be mapped into the PDO"}, + {0x06040042, "The number and length of the objects to be mapped would" + " exceed the PDO length"}, + {0x06040043, "General parameter incompatibility reason"}, + {0x06040047, "Gerneral internal incompatibility in device"}, + {0x06060000, "Access failure due to a hardware error"}, + {0x06070010, "Data type does not match, length of service parameter does" + " not match"}, + {0x06070012, "Data type does not match, length of service parameter too" + " high"}, + {0x06070013, "Data type does not match, length of service parameter too" + " low"}, + {0x06090011, "Subindex does not exist"}, + {0x06090030, "Value range of parameter exceeded"}, + {0x06090031, "Value of parameter written too high"}, + {0x06090032, "Value of parameter written too low"}, + {0x06090036, "Maximum value is less than minimum value"}, + {0x08000000, "General error"}, + {0x08000020, "Data cannot be transferred or stored to the application"}, + {0x08000021, "Data cannot be transferred or stored to the application" + " because of local control"}, + {0x08000022, "Data cannot be transferred or stored to the application" + " because of the present device state"}, + {0x08000023, "Object dictionary dynamic generation fails or no object" + " dictionary is present"}, + {} +}; + +/****************************************************************************/ + +/** Outputs an SDO abort message. + */ +void ec_canopen_abort_msg( + const ec_slave_t *slave, /**< Slave. */ + uint32_t abort_code /**< Abort code to search for. */ + ) +{ + const ec_code_msg_t *abort_msg; + + for (abort_msg = sdo_abort_messages; abort_msg->code; abort_msg++) { + if (abort_msg->code == abort_code) { + EC_SLAVE_ERR(slave, "SDO abort message 0x%08X: \"%s\".\n", + abort_msg->code, abort_msg->message); + return; + } + } + + EC_SLAVE_ERR(slave, "Unknown SDO abort code 0x%08X.\n", abort_code); +} + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_coe_init( + ec_fsm_coe_t *fsm /**< Finite state machine */ + ) +{ + fsm->state = NULL; + fsm->datagram = NULL; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_coe_clear( + ec_fsm_coe_t *fsm /**< Finite state machine */ + ) +{ +} + +/****************************************************************************/ + +/** Starts reading a slaves' SDO dictionary. + */ +void ec_fsm_coe_dictionary( + ec_fsm_coe_t *fsm, /**< Finite state machine */ + ec_slave_t *slave /**< EtherCAT slave */ + ) +{ + fsm->slave = slave; + fsm->state = ec_fsm_coe_dict_start; +} + +/****************************************************************************/ + +/** Starts to transfer an SDO to/from a slave. + */ +void ec_fsm_coe_transfer( + ec_fsm_coe_t *fsm, /**< State machine. */ + ec_slave_t *slave, /**< EtherCAT slave. */ + ec_sdo_request_t *request /**< SDO request. */ + ) +{ + fsm->slave = slave; + fsm->request = request; + + if (request->dir == EC_DIR_OUTPUT) { + fsm->state = ec_fsm_coe_down_start; + } + else { + fsm->state = ec_fsm_coe_up_start; + } +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * \return 1 if the datagram was used, else 0. + */ +int ec_fsm_coe_exec( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + int datagram_used = 0; + + if (fsm->datagram && + (fsm->datagram->state == EC_DATAGRAM_INIT || + fsm->datagram->state == EC_DATAGRAM_QUEUED || + fsm->datagram->state == EC_DATAGRAM_SENT)) { + // datagram not received yet + return datagram_used; + } + + fsm->state(fsm, datagram); + + datagram_used = + fsm->state != ec_fsm_coe_end && fsm->state != ec_fsm_coe_error; + + if (datagram_used) { + fsm->datagram = datagram; + } else { + fsm->datagram = NULL; + } + + return datagram_used; +} + +/****************************************************************************/ + +/** Returns, if the state machine terminated with success. + * \return non-zero if successful. + */ +int ec_fsm_coe_success( + const ec_fsm_coe_t *fsm /**< Finite state machine */ + ) +{ + return fsm->state == ec_fsm_coe_end; +} + +/****************************************************************************/ + +/** Check if the received data are a CoE emergency request. + * + * If the check is positive, the emergency request is output. + * + * \return The data were an emergency request. + */ +int ec_fsm_coe_check_emergency( + const ec_fsm_coe_t *fsm, /**< Finite state machine */ + const uint8_t *data, /**< CoE mailbox data. */ + size_t size /**< CoE mailbox data size. */ + ) +{ + if (size < 2 || ((EC_READ_U16(data) >> 12) & 0x0F) != 0x01) + return 0; + + if (size < 10) { + EC_SLAVE_WARN(fsm->slave, "Received incomplete CoE Emergency" + " request:\n"); + ec_print_data(data, size); + return 1; + } + + { + ec_slave_config_t *sc = fsm->slave->config; + if (sc) { + ec_coe_emerg_ring_push(&sc->emerg_ring, data + 2); + } + } + + EC_SLAVE_WARN(fsm->slave, "CoE Emergency Request received:\n" + "Error code 0x%04X, Error register 0x%02X, data:\n", + EC_READ_U16(data + 2), EC_READ_U8(data + 4)); + ec_print_data(data + 5, 5); + return 1; +} + +/***************************************************************************** + * CoE dictionary state machine + ****************************************************************************/ + +/** Prepare a dictionary request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_fsm_coe_prepare_dict( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t *data = ec_slave_mbox_prepare_send(slave, datagram, + EC_MBOX_TYPE_COE, 8); + if (IS_ERR(data)) { + return PTR_ERR(data); + } + + EC_WRITE_U16(data, 0x8 << 12); // SDO information + EC_WRITE_U8 (data + 2, 0x01); // Get OD List Request + EC_WRITE_U8 (data + 3, 0x00); + EC_WRITE_U16(data + 4, 0x0000); + EC_WRITE_U16(data + 6, 0x0001); // deliver all SDOs! + + fsm->state = ec_fsm_coe_dict_request; + return 0; +} + +/****************************************************************************/ + +/** CoE state: DICT START. + */ +void ec_fsm_coe_dict_start( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (!(slave->sii.mailbox_protocols & EC_MBOX_COE)) { + EC_SLAVE_ERR(slave, "Slave does not support CoE!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + if (slave->sii.has_general && !slave->sii.coe_details.enable_sdo_info) { + EC_SLAVE_ERR(slave, "Slave does not support" + " SDO information service!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_coe_prepare_dict(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } +} + +/****************************************************************************/ + +/** CoE state: DICT REQUEST. + * \todo Timeout behavior + */ +void ec_fsm_coe_dict_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_coe_prepare_dict(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE dictionary" + " request datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE dictionary request failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_check; +} + +/****************************************************************************/ + +/** CoE state: DICT CHECK. + */ +void ec_fsm_coe_dict_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave,"Reception of CoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= EC_FSM_COE_DICT_TIMEOUT) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout while waiting for" + " SDO dictionary list response.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_response; +} + +/****************************************************************************/ + +/** Prepare an object description request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_fsm_coe_dict_prepare_desc( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + u8 *data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + 8); + if (IS_ERR(data)) { + return PTR_ERR(data); + } + + EC_WRITE_U16(data, 0x8 << 12); // SDO information + EC_WRITE_U8 (data + 2, 0x03); // Get object description request + EC_WRITE_U8 (data + 3, 0x00); + EC_WRITE_U16(data + 4, 0x0000); + EC_WRITE_U16(data + 6, fsm->sdo->index); // SDO index + + fsm->state = ec_fsm_coe_dict_desc_request; + return 0; +} + +/****************************************************************************/ + +/** + CoE state: DICT RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_dict_response( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t *data, mbox_prot; + size_t rec_size; + unsigned int sdo_count, i; + uint16_t sdo_index, fragments_left; + ec_sdo_t *sdo; + bool first_segment; + size_t index_list_offset; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE dictionary" + " response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE dictionary response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_coe_error; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + fsm->state = ec_fsm_coe_error; + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_check; + return; + } + + if (rec_size < 3) { + EC_SLAVE_ERR(slave, "Received corrupted SDO dictionary response" + " (size %zu).\n", rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 == 0x8 && // SDO information + (EC_READ_U8(data + 2) & 0x7F) == 0x07) { // error response + EC_SLAVE_ERR(slave, "SDO information error response!\n"); + if (rec_size < 10) { + EC_SLAVE_ERR(slave, "Incomplete SDO information" + " error response:\n"); + ec_print_data(data, rec_size); + } else { + ec_canopen_abort_msg(slave, EC_READ_U32(data + 6)); + } + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 != 0x8 || // SDO information + (EC_READ_U8 (data + 2) & 0x7F) != 0x02) { // Get OD List response + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid SDO list response!" + " Retrying...\n"); + ec_print_data(data, rec_size); + } + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_check; + return; + } + + first_segment = list_empty(&slave->sdo_dictionary) ? true : false; + index_list_offset = first_segment ? 8 : 6; + + if (rec_size < index_list_offset || rec_size % 2) { + EC_SLAVE_ERR(slave, "Invalid data size %zu!\n", rec_size); + ec_print_data(data, rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + sdo_count = (rec_size - index_list_offset) / 2; + + for (i = 0; i < sdo_count; i++) { + sdo_index = EC_READ_U16(data + index_list_offset + i * 2); + if (!sdo_index) { + EC_SLAVE_DBG(slave, 1, "SDO dictionary contains index 0x0000.\n"); + continue; + } + + if (!(sdo = (ec_sdo_t *) kmalloc(sizeof(ec_sdo_t), GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate memory for SDO!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + ec_sdo_init(sdo, slave, sdo_index); + list_add_tail(&sdo->list, &slave->sdo_dictionary); + } + + fragments_left = EC_READ_U16(data + 4); + if (fragments_left) { + EC_SLAVE_DBG(slave, 1, "SDO list fragments left: %u\n", + fragments_left); + } + + if (EC_READ_U8(data + 2) & 0x80 || fragments_left) { + // more messages waiting. check again. + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_check; + return; + } + + if (list_empty(&slave->sdo_dictionary)) { + // no SDOs in dictionary. finished. + fsm->state = ec_fsm_coe_end; // success + return; + } + + // fetch SDO descriptions + fsm->sdo = list_entry(slave->sdo_dictionary.next, ec_sdo_t, list); + + fsm->retries = EC_FSM_RETRIES; + if (ec_fsm_coe_dict_prepare_desc(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } +} + +/****************************************************************************/ + +/** + CoE state: DICT DESC REQUEST. + \todo Timeout behavior +*/ + +void ec_fsm_coe_dict_desc_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_coe_dict_prepare_desc(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE SDO" + " description request datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE SDO description" + " request failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_desc_check; +} + +/****************************************************************************/ + +/** + CoE state: DICT DESC CHECK. +*/ + +void ec_fsm_coe_dict_desc_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= EC_FSM_COE_DICT_TIMEOUT) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout while waiting for" + " SDO 0x%04x object description response.\n", + fsm->sdo->index); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_desc_response; +} + +/****************************************************************************/ + +/** Prepare an entry description request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_fsm_coe_dict_prepare_entry( + ec_fsm_coe_t *fsm, /**< Finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + u8 *data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + 10); + if (IS_ERR(data)) { + return PTR_ERR(data); + } + + EC_WRITE_U16(data, 0x8 << 12); // SDO information + EC_WRITE_U8 (data + 2, 0x05); // Get entry description request + EC_WRITE_U8 (data + 3, 0x00); + EC_WRITE_U16(data + 4, 0x0000); + EC_WRITE_U16(data + 6, fsm->sdo->index); // SDO index + EC_WRITE_U8 (data + 8, fsm->subindex); // SDO subindex + EC_WRITE_U8 (data + 9, 0x01); // value info (access rights only) + + fsm->state = ec_fsm_coe_dict_entry_request; + return 0; +} + +/****************************************************************************/ + +/** + CoE state: DICT DESC RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_dict_desc_response( + ec_fsm_coe_t *fsm, /**< Finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_t *sdo = fsm->sdo; + uint8_t *data, mbox_prot; + size_t rec_size, name_size; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE SDO description" + " response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE SDO description" + " response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_coe_error; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + fsm->state = ec_fsm_coe_error; + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_desc_check; + return; + } + + if (rec_size < 3) { + EC_SLAVE_ERR(slave, "Received corrupted SDO description response" + " (size %zu).\n", rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 == 0x8 && // SDO information + (EC_READ_U8 (data + 2) & 0x7F) == 0x07) { // error response + EC_SLAVE_ERR(slave, "SDO information error response while" + " fetching SDO 0x%04X!\n", sdo->index); + ec_canopen_abort_msg(slave, EC_READ_U32(data + 6)); + fsm->state = ec_fsm_coe_error; + return; + } + + if (rec_size < 8) { + EC_SLAVE_ERR(slave, "Received corrupted SDO" + " description response (size %zu).\n", rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 != 0x8 || // SDO information + (EC_READ_U8 (data + 2) & 0x7F) != 0x04 || // Object desc. response + EC_READ_U16(data + 6) != sdo->index) { // SDO index + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid object description response while" + " fetching SDO 0x%04X!\n", sdo->index); + ec_print_data(data, rec_size); + } + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_desc_check; + return; + } + + if (rec_size < 12) { + EC_SLAVE_ERR(slave, "Invalid data size!\n"); + ec_print_data(data, rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + sdo->max_subindex = EC_READ_U8(data + 10); + sdo->object_code = EC_READ_U8(data + 11); + + name_size = rec_size - 12; + if (name_size) { + if (!(sdo->name = kmalloc(name_size + 1, GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate SDO name!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + memcpy(sdo->name, data + 12, name_size); + sdo->name[name_size] = 0; + } + + if (EC_READ_U8(data + 2) & 0x80) { + EC_SLAVE_ERR(slave, "Fragment follows (not implemented)!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + // start fetching entries + + fsm->subindex = 0; + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_coe_dict_prepare_entry(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } +} + +/****************************************************************************/ + +/** + CoE state: DICT ENTRY REQUEST. + \todo Timeout behavior +*/ + +void ec_fsm_coe_dict_entry_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_coe_dict_prepare_entry(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE SDO entry" + " request datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE SDO entry request failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_entry_check; +} + +/****************************************************************************/ + +/** + CoE state: DICT ENTRY CHECK. +*/ + +void ec_fsm_coe_dict_entry_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= EC_FSM_COE_DICT_TIMEOUT) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout while waiting for" + " SDO entry 0x%04x:%x description response.\n", + fsm->sdo->index, fsm->subindex); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_entry_response; +} + +/****************************************************************************/ + +/** + CoE state: DICT ENTRY RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_dict_entry_response( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_t *sdo = fsm->sdo; + uint8_t *data, mbox_prot; + size_t rec_size, data_size; + ec_sdo_entry_t *entry; + u16 word; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE SDO" + " description response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE SDO description" + " response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_coe_error; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + EC_SLAVE_ERR(slave, "Received mailbox protocol" + " 0x%02X as response.\n", mbox_prot); + fsm->state = ec_fsm_coe_error; + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_entry_check; + return; + } + + if (rec_size < 3) { + EC_SLAVE_ERR(slave, "Received corrupted SDO entry" + " description response (size %zu).\n", rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 == 0x8 && // SDO information + (EC_READ_U8 (data + 2) & 0x7F) == 0x07) { // error response + EC_SLAVE_WARN(slave, "SDO information error response while" + " fetching SDO entry 0x%04X:%02X!\n", + sdo->index, fsm->subindex); + ec_canopen_abort_msg(slave, EC_READ_U32(data + 6)); + + /* There may be gaps in the subindices, so try to continue with next + * subindex. */ + + } else { + + if (rec_size < 9) { + EC_SLAVE_ERR(slave, "Received corrupted SDO entry" + " description response (size %zu).\n", rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 != 0x8 || // SDO information + (EC_READ_U8(data + 2) & 0x7F) != 0x06 || // Entry desc. response + EC_READ_U16(data + 6) != sdo->index || // SDO index + EC_READ_U8(data + 8) != fsm->subindex) { // SDO subindex + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid entry description response" + " while fetching SDO entry 0x%04X:%02X!\n", + sdo->index, fsm->subindex); + ec_print_data(data, rec_size); + } + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_entry_check; + return; + } + + if (rec_size < 16) { + EC_SLAVE_ERR(slave, "Invalid data size %zu!\n", rec_size); + ec_print_data(data, rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + data_size = rec_size - 16; + + if (!(entry = (ec_sdo_entry_t *) + kmalloc(sizeof(ec_sdo_entry_t), GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate entry!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + ec_sdo_entry_init(entry, sdo, fsm->subindex); + entry->data_type = EC_READ_U16(data + 10); + entry->bit_length = EC_READ_U16(data + 12); + + // read access rights + word = EC_READ_U16(data + 14); + entry->read_access[EC_SDO_ENTRY_ACCESS_PREOP] = word & 0x0001; + entry->read_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = + (word >> 1) & 0x0001; + entry->read_access[EC_SDO_ENTRY_ACCESS_OP] = (word >> 2) & 0x0001; + entry->write_access[EC_SDO_ENTRY_ACCESS_PREOP] = (word >> 3) & 0x0001; + entry->write_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = + (word >> 4) & 0x0001; + entry->write_access[EC_SDO_ENTRY_ACCESS_OP] = (word >> 5) & 0x0001; + + if (data_size) { + uint8_t *desc; + if (!(desc = kmalloc(data_size + 1, GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate SDO entry name!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + memcpy(desc, data + 16, data_size); + desc[data_size] = 0; + entry->description = desc; + } + + list_add_tail(&entry->list, &sdo->entries); + } + + if (fsm->subindex < sdo->max_subindex) { + + fsm->subindex++; + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_coe_dict_prepare_entry(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + + return; + } + + // another SDO description to fetch? + if (fsm->sdo->list.next != &slave->sdo_dictionary) { + + fsm->sdo = list_entry(fsm->sdo->list.next, ec_sdo_t, list); + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_coe_dict_prepare_desc(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + + return; + } + + fsm->state = ec_fsm_coe_end; +} + +/***************************************************************************** + * CoE state machine + ****************************************************************************/ + +/** Prepare a donwnload request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_fsm_coe_prepare_down_start( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + u8 *data; + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->request; + uint8_t data_set_size; + + if (request->data_size > 0 && request->data_size <= 4) { + // use expedited transfer mode for lengths between 1 and 4 bytes + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + EC_COE_DOWN_REQ_HEADER_SIZE); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + return PTR_ERR(data); + } + + fsm->remaining = 0; + + data_set_size = 4 - request->data_size; + + EC_WRITE_U16(data, 0x2 << 12); // SDO request + EC_WRITE_U8 (data + 2, (0x3 // size specified, expedited + | data_set_size << 2 + | ((request->complete_access ? 1 : 0) << 4) + | 0x1 << 5)); // Download request + EC_WRITE_U16(data + 3, request->index); + EC_WRITE_U8 (data + 5, + request->complete_access ? 0x00 : request->subindex); + memcpy(data + 6, request->data, request->data_size); + memset(data + 6 + request->data_size, 0x00, 4 - request->data_size); + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Expedited download request:\n"); + ec_print_data(data, EC_COE_DOWN_REQ_HEADER_SIZE); + } + } + else { // data_size < 1 or data_size > 4, use normal transfer type + size_t data_size, + max_data_size = + slave->configured_rx_mailbox_size - EC_MBOX_HEADER_SIZE, + required_data_size = + EC_COE_DOWN_REQ_HEADER_SIZE + request->data_size; + + if (max_data_size < required_data_size) { + // segmenting needed + data_size = max_data_size; + } else { + data_size = required_data_size; + } + + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + data_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + return PTR_ERR(data); + } + + fsm->offset = 0; + fsm->remaining = request->data_size; + + EC_WRITE_U16(data, 0x2 << 12); // SDO request + EC_WRITE_U8(data + 2, + 0x1 // size indicator, normal + | ((request->complete_access ? 1 : 0) << 4) + | 0x1 << 5); // Download request + EC_WRITE_U16(data + 3, request->index); + EC_WRITE_U8 (data + 5, + request->complete_access ? 0x00 : request->subindex); + EC_WRITE_U32(data + 6, request->data_size); + + if (data_size > EC_COE_DOWN_REQ_HEADER_SIZE) { + size_t segment_size = data_size - EC_COE_DOWN_REQ_HEADER_SIZE; + memcpy(data + EC_COE_DOWN_REQ_HEADER_SIZE, + request->data, segment_size); + fsm->offset += segment_size; + fsm->remaining -= segment_size; + } + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Normal download request:\n"); + ec_print_data(data, data_size); + } + } + + fsm->state = ec_fsm_coe_down_request; + return 0; +} + +/****************************************************************************/ + +/** CoE state: DOWN START. + */ +void ec_fsm_coe_down_start( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->request; + + if (fsm->slave->master->debug_level) { + char subidxstr[10]; + if (request->complete_access) { + subidxstr[0] = 0x00; + } else { + sprintf(subidxstr, ":%02X", request->subindex); + } + EC_SLAVE_DBG(slave, 1, "Downloading SDO 0x%04X%s.\n", + request->index, subidxstr); + ec_print_data(request->data, request->data_size); + } + + if (!(slave->sii.mailbox_protocols & EC_MBOX_COE)) { + EC_SLAVE_ERR(slave, "Slave does not support CoE!\n"); + request->errno = EPROTONOSUPPORT; + fsm->state = ec_fsm_coe_error; + return; + } + + if (slave->configured_rx_mailbox_size < + EC_MBOX_HEADER_SIZE + EC_COE_DOWN_REQ_HEADER_SIZE) { + EC_SLAVE_ERR(slave, "Mailbox too small!\n"); + request->errno = ENOBUFS; + fsm->state = ec_fsm_coe_error; + return; + } + + + fsm->request->jiffies_sent = jiffies; + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_coe_prepare_down_start(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } +} + +/****************************************************************************/ + +/** + CoE state: DOWN REQUEST. + \todo Timeout behavior +*/ + +void ec_fsm_coe_down_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + unsigned long diff_ms; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_coe_prepare_down_start(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE download" + " request datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + diff_ms = (jiffies - fsm->request->jiffies_sent) * 1000 / HZ; + + if (fsm->datagram->working_counter != 1) { + if (!fsm->datagram->working_counter) { + if (diff_ms < fsm->request->response_timeout) { +#if DEBUG_RETRIES + EC_SLAVE_DBG(slave, 1, "Slave did not respond to SDO" + " download request. Retrying after %lu ms...\n", + diff_ms); +#endif + // no response; send request datagram again + if (ec_fsm_coe_prepare_down_start(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + } + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE download request" + " for SDO 0x%04x:%x failed with timeout after %lu ms: ", + fsm->request->index, fsm->request->subindex, diff_ms); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + +#if DEBUG_LONG + if (diff_ms > 200) { + EC_SLAVE_WARN(slave, "SDO 0x%04x:%x download took %lu ms.\n", + fsm->request->index, fsm->request->subindex, diff_ms); + } +#endif + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_check; +} + +/****************************************************************************/ + +/** CoE state: DOWN CHECK. + */ +void ec_fsm_coe_down_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check" + " datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= fsm->request->response_timeout) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout after %lu ms while waiting" + " for SDO 0x%04x:%x download response.\n", diff_ms, + fsm->request->index, fsm->request->subindex); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_response; +} + +/****************************************************************************/ + +/** Prepare a download segment request. + */ +void ec_fsm_coe_down_prepare_segment_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->request; + size_t max_segment_size = + slave->configured_rx_mailbox_size + - EC_MBOX_HEADER_SIZE + - EC_COE_DOWN_SEG_REQ_HEADER_SIZE; + size_t data_size; + uint8_t last_segment, seg_data_size, *data; + + if (fsm->remaining > max_segment_size) { + fsm->segment_size = max_segment_size; + last_segment = 0; + } else { + fsm->segment_size = fsm->remaining; + last_segment = 1; + } + + if (fsm->segment_size > EC_COE_DOWN_SEG_MIN_DATA_SIZE) { + seg_data_size = 0x00; + data_size = EC_COE_DOWN_SEG_REQ_HEADER_SIZE + fsm->segment_size; + } else { + seg_data_size = EC_COE_DOWN_SEG_MIN_DATA_SIZE - fsm->segment_size; + data_size = EC_COE_DOWN_SEG_REQ_HEADER_SIZE + + EC_COE_DOWN_SEG_MIN_DATA_SIZE; + } + + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + data_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + EC_WRITE_U16(data, 0x2 << 12); // SDO request + EC_WRITE_U8(data + 2, (last_segment ? 1 : 0) + | (seg_data_size << 1) + | (fsm->toggle << 4) + | (0x00 << 5)); // Download segment request + memcpy(data + EC_COE_DOWN_SEG_REQ_HEADER_SIZE, + request->data + fsm->offset, fsm->segment_size); + if (fsm->segment_size < EC_COE_DOWN_SEG_MIN_DATA_SIZE) { + memset(data + EC_COE_DOWN_SEG_REQ_HEADER_SIZE + fsm->segment_size, + 0x00, EC_COE_DOWN_SEG_MIN_DATA_SIZE - fsm->segment_size); + } + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Download segment request:\n"); + ec_print_data(data, data_size); + } + + fsm->state = ec_fsm_coe_down_seg_check; +} + +/****************************************************************************/ + +/** + CoE state: DOWN RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_down_response( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t *data, mbox_prot; + size_t rec_size; + ec_sdo_request_t *request = fsm->request; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE download" + " response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE download response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_check; + return; + } + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Download response:\n"); + ec_print_data(data, rec_size); + } + + if (rec_size < 6) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received data are too small (%zu bytes):\n", + rec_size); + ec_print_data(data, rec_size); + return; + } + + if (EC_READ_U16(data) >> 12 == 0x2 && // SDO request + EC_READ_U8 (data + 2) >> 5 == 0x4) { // abort SDO transfer request + char subidxstr[10]; + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + if (request->complete_access) { + subidxstr[0] = 0x00; + } else { + sprintf(subidxstr, ":%02X", request->subindex); + } + EC_SLAVE_ERR(slave, "SDO download 0x%04X%s (%zu bytes) aborted.\n", + request->index, subidxstr, request->data_size); + if (rec_size < 10) { + EC_SLAVE_ERR(slave, "Incomplete abort command:\n"); + ec_print_data(data, rec_size); + } else { + fsm->request->abort_code = EC_READ_U32(data + 6); + ec_canopen_abort_msg(slave, fsm->request->abort_code); + } + return; + } + + if (EC_READ_U16(data) >> 12 != 0x3 || // SDO response + EC_READ_U8 (data + 2) >> 5 != 0x3 || // Download response + EC_READ_U16(data + 3) != request->index || // index + EC_READ_U8 (data + 5) != request->subindex) { // subindex + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid SDO download response!" + " Retrying...\n"); + ec_print_data(data, rec_size); + } + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_check; + return; + } + + if (fsm->remaining) { // more segments to download + fsm->toggle = 0; + ec_fsm_coe_down_prepare_segment_request(fsm, datagram); + } else { + fsm->state = ec_fsm_coe_end; // success + } +} + +/****************************************************************************/ + +/** + CoE state: DOWN SEG CHECK. +*/ + +void ec_fsm_coe_down_seg_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox segment check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= fsm->request->response_timeout) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout while waiting for SDO download" + " segment response.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_seg_response; +} + +/****************************************************************************/ + +/** + CoE state: DOWN SEG RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_down_seg_response( + ec_fsm_coe_t *fsm, /**< Finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t *data, mbox_prot; + size_t rec_size; + ec_sdo_request_t *request = fsm->request; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE download response" + " datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE download response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_check; + return; + } + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Download response:\n"); + ec_print_data(data, rec_size); + } + + if (rec_size < 6) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received data are too small (%zu bytes):\n", + rec_size); + ec_print_data(data, rec_size); + return; + } + + if (EC_READ_U16(data) >> 12 == 0x2 && // SDO request + EC_READ_U8 (data + 2) >> 5 == 0x4) { // abort SDO transfer request + char subidxstr[10]; + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + if (request->complete_access) { + subidxstr[0] = 0x00; + } else { + sprintf(subidxstr, ":%02X", request->subindex); + } + EC_SLAVE_ERR(slave, "SDO download 0x%04X%s (%zu bytes) aborted.\n", + request->index, subidxstr, request->data_size); + if (rec_size < 10) { + EC_SLAVE_ERR(slave, "Incomplete abort command:\n"); + ec_print_data(data, rec_size); + } else { + fsm->request->abort_code = EC_READ_U32(data + 6); + ec_canopen_abort_msg(slave, fsm->request->abort_code); + } + return; + } + + if (EC_READ_U16(data) >> 12 != 0x3 || + ((EC_READ_U8(data + 2) >> 5) != 0x01)) { // segment response + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid SDO download response!" + " Retrying...\n"); + ec_print_data(data, rec_size); + } + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_seg_check; + return; + } + + if (((EC_READ_U8(data + 2) >> 4) & 0x01) != fsm->toggle) { + EC_SLAVE_ERR(slave, "Invalid toggle received during" + " segmented download:\n"); + ec_print_data(data, rec_size); + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + fsm->offset += fsm->segment_size; + fsm->remaining -= fsm->segment_size; + + if (fsm->remaining) { // more segments to download + fsm->toggle = !fsm->toggle; + ec_fsm_coe_down_prepare_segment_request(fsm, datagram); + } else { + fsm->state = ec_fsm_coe_end; // success + } +} + +/****************************************************************************/ + +/** Prepare an upload request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_fsm_coe_prepare_up( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->request; + ec_master_t *master = slave->master; + + u8 *data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + 10); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + return PTR_ERR(data); + } + + EC_WRITE_U16(data, 0x2 << 12); // SDO request + EC_WRITE_U8 (data + 2, 0x2 << 5); // initiate upload request + EC_WRITE_U16(data + 3, request->index); + EC_WRITE_U8 (data + 5, request->subindex); + memset(data + 6, 0x00, 4); + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Upload request:\n"); + ec_print_data(data, 10); + } + + fsm->state = ec_fsm_coe_up_request; + return 0; +} + +/****************************************************************************/ + +/** + CoE state: UP START. +*/ + +void ec_fsm_coe_up_start( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->request; + + EC_SLAVE_DBG(slave, 1, "Uploading SDO 0x%04X:%02X.\n", + request->index, request->subindex); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_COE)) { + EC_SLAVE_ERR(slave, "Slave does not support CoE!\n"); + request->errno = EPROTONOSUPPORT; + fsm->state = ec_fsm_coe_error; + return; + } + + fsm->retries = EC_FSM_RETRIES; + fsm->request->jiffies_sent = jiffies; + + if (ec_fsm_coe_prepare_up(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } +} + +/****************************************************************************/ +/** + CoE state: UP REQUEST. + \todo Timeout behavior +*/ + +void ec_fsm_coe_up_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + unsigned long diff_ms; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_coe_prepare_up(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE upload request: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + diff_ms = (jiffies - fsm->request->jiffies_sent) * 1000 / HZ; + + if (fsm->datagram->working_counter != 1) { + if (!fsm->datagram->working_counter) { + if (diff_ms < fsm->request->response_timeout) { +#if DEBUG_RETRIES + EC_SLAVE_DBG(slave, 1, "Slave did not respond to" + " SDO upload request. Retrying after %lu ms...\n", + diff_ms); +#endif + // no response; send request datagram again + if (ec_fsm_coe_prepare_up(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + } + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE upload request for" + " SDO 0x%04x:%x failed with timeout after %lu ms: ", + fsm->request->index, fsm->request->subindex, diff_ms); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + +#if DEBUG_LONG + if (diff_ms > 200) { + EC_SLAVE_WARN(slave, "SDO 0x%04x:%x upload took %lu ms.\n", + fsm->request->index, fsm->request->subindex, diff_ms); + } +#endif + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_check; +} + +/****************************************************************************/ + +/** + CoE state: UP CHECK. +*/ + +void ec_fsm_coe_up_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= fsm->request->response_timeout) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout after %lu ms while waiting for" + " SDO 0x%04x:%x upload response.\n", diff_ms, + fsm->request->index, fsm->request->subindex); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_response; +} + +/****************************************************************************/ + +/** Prepare an SDO upload segment request. + */ +void ec_fsm_coe_up_prepare_segment_request( + ec_fsm_coe_t *fsm, /**< Finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + uint8_t *data = + ec_slave_mbox_prepare_send(fsm->slave, datagram, EC_MBOX_TYPE_COE, + 10); + if (IS_ERR(data)) { + fsm->request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + EC_WRITE_U16(data, 0x2 << 12); // SDO request + EC_WRITE_U8 (data + 2, (fsm->toggle << 4 // toggle + | 0x3 << 5)); // upload segment request + memset(data + 3, 0x00, 7); + + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(fsm->slave, 1, "Upload segment request:\n"); + ec_print_data(data, 10); + } +} + +/****************************************************************************/ + +/** + CoE state: UP RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_up_response( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + uint16_t rec_index; + uint8_t *data, mbox_prot, rec_subindex; + size_t rec_size, data_size; + ec_sdo_request_t *request = fsm->request; + unsigned int expedited, size_specified; + int ret; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE upload response" + " datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE upload response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Upload response:\n"); + ec_print_data(data, rec_size); + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_WARN(slave, "Received mailbox protocol 0x%02X" + " as response.\n", mbox_prot); + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_check; + return; + } + + if (rec_size < 6) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received currupted SDO upload response" + " (%zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + return; + } + + if (EC_READ_U16(data) >> 12 == 0x2 && // SDO request + EC_READ_U8(data + 2) >> 5 == 0x4) { // abort SDO transfer request + EC_SLAVE_ERR(slave, "SDO upload 0x%04X:%02X aborted.\n", + request->index, request->subindex); + if (rec_size >= 10) { + request->abort_code = EC_READ_U32(data + 6); + ec_canopen_abort_msg(slave, request->abort_code); + } else { + EC_SLAVE_ERR(slave, "No abort message.\n"); + } + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 != 0x3 || // SDO response + EC_READ_U8(data + 2) >> 5 != 0x2) { // upload response + EC_SLAVE_ERR(slave, "Received unknown response while" + " uploading SDO 0x%04X:%02X.\n", + request->index, request->subindex); + ec_print_data(data, rec_size); + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + rec_index = EC_READ_U16(data + 3); + rec_subindex = EC_READ_U8(data + 5); + + if (rec_index != request->index || rec_subindex != request->subindex) { + EC_SLAVE_ERR(slave, "Received upload response for wrong SDO" + " (0x%04X:%02X, requested: 0x%04X:%02X).\n", + rec_index, rec_subindex, request->index, request->subindex); + ec_print_data(data, rec_size); + + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_check; + return; + } + + // normal or expedited? + expedited = EC_READ_U8(data + 2) & 0x02; + + if (expedited) { + size_specified = EC_READ_U8(data + 2) & 0x01; + if (size_specified) { + fsm->complete_size = 4 - ((EC_READ_U8(data + 2) & 0x0C) >> 2); + } else { + fsm->complete_size = 4; + } + + if (rec_size < 6 + fsm->complete_size) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received corrupted SDO expedited upload" + " response (only %zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + return; + } + + ret = ec_sdo_request_copy_data(request, data + 6, fsm->complete_size); + if (ret) { + request->errno = -ret; + fsm->state = ec_fsm_coe_error; + return; + } + } else { // normal + if (rec_size < 10) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received currupted SDO normal upload" + " response (only %zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + return; + } + + data_size = rec_size - 10; + fsm->complete_size = EC_READ_U32(data + 6); + + ret = ec_sdo_request_alloc(request, fsm->complete_size); + if (ret) { + request->errno = -ret; + fsm->state = ec_fsm_coe_error; + return; + } + + ret = ec_sdo_request_copy_data(request, data + 10, data_size); + if (ret) { + request->errno = -ret; + fsm->state = ec_fsm_coe_error; + return; + } + + fsm->toggle = 0; + + if (data_size < fsm->complete_size) { + EC_SLAVE_DBG(slave, 1, "SDO data incomplete (%zu / %u)." + " Segmenting...\n", data_size, fsm->complete_size); + ec_fsm_coe_up_prepare_segment_request(fsm, datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_request; + return; + } + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Uploaded data:\n"); + ec_print_data(request->data, request->data_size); + } + + fsm->state = ec_fsm_coe_end; // success +} + +/****************************************************************************/ + +/** + CoE state: UP REQUEST. + \todo Timeout behavior +*/ + +void ec_fsm_coe_up_seg_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_fsm_coe_up_prepare_segment_request(fsm, datagram); + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE upload segment" + " request datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE upload segment" + " request failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_check; +} + +/****************************************************************************/ + +/** + CoE state: UP CHECK. +*/ + +void ec_fsm_coe_up_seg_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check" + " datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox check datagram" + " failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= fsm->request->response_timeout) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout while waiting for SDO upload" + " segment response.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_response; +} + +/****************************************************************************/ + +/** + CoE state: UP RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_up_seg_response( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + uint8_t *data, mbox_prot; + size_t rec_size, data_size; + ec_sdo_request_t *request = fsm->request; + unsigned int last_segment; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE upload segment" + " response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE upload segment" + " response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Upload segment response:\n"); + ec_print_data(data, rec_size); + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_check; + return; + } + + if (rec_size < 10) { + EC_SLAVE_ERR(slave, "Received currupted SDO upload" + " segment response!\n"); + ec_print_data(data, rec_size); + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 == 0x2 && // SDO request + EC_READ_U8 (data + 2) >> 5 == 0x4) { // abort SDO transfer request + EC_SLAVE_ERR(slave, "SDO upload 0x%04X:%02X aborted.\n", + request->index, request->subindex); + request->abort_code = EC_READ_U32(data + 6); + ec_canopen_abort_msg(slave, request->abort_code); + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 != 0x3 || // SDO response + EC_READ_U8 (data + 2) >> 5 != 0x0) { // upload segment response + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid SDO upload segment response!\n"); + ec_print_data(data, rec_size); + } + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_check; + return; + } + + data_size = rec_size - 3; /* Header of segment upload is smaller than + normal upload */ + if (rec_size == 10) { + uint8_t seg_size = (EC_READ_U8(data + 2) & 0xE) >> 1; + data_size -= seg_size; + } + + if (request->data_size + data_size > fsm->complete_size) { + EC_SLAVE_ERR(slave, "SDO upload 0x%04X:%02X failed: Fragment" + " exceeding complete size!\n", + request->index, request->subindex); + request->errno = ENOBUFS; + fsm->state = ec_fsm_coe_error; + return; + } + + memcpy(request->data + request->data_size, data + 3, data_size); + request->data_size += data_size; + + last_segment = EC_READ_U8(data + 2) & 0x01; + if (!last_segment) { + fsm->toggle = !fsm->toggle; + ec_fsm_coe_up_prepare_segment_request(fsm, datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_request; + return; + } + + if (request->data_size != fsm->complete_size) { + EC_SLAVE_WARN(slave, "SDO upload 0x%04X:%02X: Assembled data" + " size (%zu) does not match complete size (%u)!\n", + request->index, request->subindex, + request->data_size, fsm->complete_size); + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Uploaded data:\n"); + ec_print_data(request->data, request->data_size); + } + + fsm->state = ec_fsm_coe_end; // success +} + +/****************************************************************************/ + +/** + State: ERROR. +*/ + +void ec_fsm_coe_error( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ + +/** + State: END. +*/ + +void ec_fsm_coe_end( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_coe.h b/ubuntu/igh-ecat/master/fsm_coe.h new file mode 100644 index 00000000000000..846e1447348973 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_coe.h @@ -0,0 +1,74 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CoE state machines. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_COE_H__ +#define __EC_FSM_COE_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" +#include "sdo.h" +#include "sdo_request.h" + +/****************************************************************************/ + +typedef struct ec_fsm_coe ec_fsm_coe_t; /**< \see ec_fsm_coe */ + +/** Finite state machines for the CANopen over EtherCAT protocol. + */ +struct ec_fsm_coe { + ec_slave_t *slave; /**< slave the FSM runs on */ + unsigned int retries; /**< retries upon datagram timeout */ + + void (*state)(ec_fsm_coe_t *, ec_datagram_t *); /**< CoE state function */ + ec_datagram_t *datagram; /**< Datagram used in last step. */ + unsigned long jiffies_start; /**< CoE timestamp. */ + ec_sdo_t *sdo; /**< current SDO */ + uint8_t subindex; /**< current subindex */ + ec_sdo_request_t *request; /**< SDO request */ + uint32_t complete_size; /**< Used when segmenting. */ + uint8_t toggle; /**< toggle bit for segment commands */ + uint32_t offset; /**< Data offset during segmented download. */ + uint32_t remaining; /**< Remaining bytes during segmented download. */ + size_t segment_size; /**< Current segment size. */ +}; + +/****************************************************************************/ + +void ec_fsm_coe_init(ec_fsm_coe_t *); +void ec_fsm_coe_clear(ec_fsm_coe_t *); + +void ec_fsm_coe_dictionary(ec_fsm_coe_t *, ec_slave_t *); +void ec_fsm_coe_transfer(ec_fsm_coe_t *, ec_slave_t *, ec_sdo_request_t *); + +int ec_fsm_coe_exec(ec_fsm_coe_t *, ec_datagram_t *); +int ec_fsm_coe_success(const ec_fsm_coe_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_eoe.c b/ubuntu/igh-ecat/master/fsm_eoe.c new file mode 100644 index 00000000000000..b3ef6898939f76 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_eoe.c @@ -0,0 +1,509 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2014 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT EoE state machines. +*/ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "fsm_eoe.h" + +/****************************************************************************/ + +/** Maximum time to wait for a set IP parameter response. + */ +#define EC_EOE_RESPONSE_TIMEOUT 3000 // [ms] + +/****************************************************************************/ + +// prototypes for private functions +void memcpy_swap32(void *, const void *); + +int ec_fsm_eoe_prepare_set(ec_fsm_eoe_t *, ec_datagram_t *); + +void ec_fsm_eoe_set_ip_start(ec_fsm_eoe_t *, ec_datagram_t *); +void ec_fsm_eoe_set_ip_request(ec_fsm_eoe_t *, ec_datagram_t *); +void ec_fsm_eoe_set_ip_check(ec_fsm_eoe_t *, ec_datagram_t *); +void ec_fsm_eoe_set_ip_response(ec_fsm_eoe_t *, ec_datagram_t *); + +void ec_fsm_eoe_end(ec_fsm_eoe_t *, ec_datagram_t *); +void ec_fsm_eoe_error(ec_fsm_eoe_t *, ec_datagram_t *); + +/****************************************************************************/ + +/** Host-architecture-independent 32-bit swap function. + * + * The internal storage of struct in_addr is always big-endian. + * The mailbox protocol format to supply IPv4 adresses is little-endian + * (Yuck!). So we need a swap function, that is independent of the CPU + * architecture. ntohl()/htonl() can not be used, because they evaluate to + * NOPs if the host architecture matches the target architecture! + */ +void memcpy_swap32(void *dst, const void *src) +{ + int i; + for (i = 0; i < 4; i++) { + ((u8 *) dst)[i] = ((const u8 *) src)[3 - i]; + } +} + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_eoe_init( + ec_fsm_eoe_t *fsm /**< finite state machine */ + ) +{ + fsm->slave = NULL; + fsm->retries = 0; + fsm->state = NULL; + fsm->datagram = NULL; + fsm->jiffies_start = 0; + fsm->request = NULL; + fsm->frame_type_retries = 0; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_eoe_clear( + ec_fsm_eoe_t *fsm /**< finite state machine */ + ) +{ +} + +/****************************************************************************/ + +/** Starts to set the EoE IP partameters of a slave. + */ +void ec_fsm_eoe_set_ip_param( + ec_fsm_eoe_t *fsm, /**< State machine. */ + ec_slave_t *slave, /**< EtherCAT slave. */ + ec_eoe_request_t *request /**< EoE request. */ + ) +{ + fsm->slave = slave; + fsm->request = request; + fsm->state = ec_fsm_eoe_set_ip_start; +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * \return 1 if the datagram was used, else 0. + */ +int ec_fsm_eoe_exec( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + int datagram_used = 0; + + if (fsm->datagram && + (fsm->datagram->state == EC_DATAGRAM_INIT || + fsm->datagram->state == EC_DATAGRAM_QUEUED || + fsm->datagram->state == EC_DATAGRAM_SENT)) { + // datagram not received yet + return datagram_used; + } + + fsm->state(fsm, datagram); + + datagram_used = + fsm->state != ec_fsm_eoe_end && fsm->state != ec_fsm_eoe_error; + + if (datagram_used) { + fsm->datagram = datagram; + } else { + fsm->datagram = NULL; + } + + return datagram_used; +} + +/****************************************************************************/ + +/** Returns, if the state machine terminated with success. + * + * \return non-zero if successful. + */ +int ec_fsm_eoe_success(const ec_fsm_eoe_t *fsm /**< Finite state machine */) +{ + return fsm->state == ec_fsm_eoe_end; +} + +/***************************************************************************** + * EoE set IP parameter state machine + ****************************************************************************/ + +/** Prepare a set IP parameters operation. + * + * \return 0 on success, otherwise a negative error code. + */ +int ec_fsm_eoe_prepare_set( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + uint8_t *data, *cur; + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + ec_eoe_request_t *req = fsm->request; + + // Note: based on wireshark packet filter it suggests that the EOE_INIT + // information is a fixed size with fixed information positions. + // see: packet-ecatmb.h and packet-ecatmb.c + // However, TwinCAT 2.1 testing also indicates that if a piece of + // information is missing then all subsequent items are ignored + // Also, if you want DHCP, then only set the mac address. + size_t size = 8 + // header + flags + ETH_ALEN + // mac address + 4 + // ip address + 4 + // subnet mask + 4 + // gateway + 4 + // dns server + EC_MAX_HOSTNAME_SIZE; // dns name + + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_EOE, + size); + if (IS_ERR(data)) { + return PTR_ERR(data); + } + + // zero data + memset(data, 0, size); + + // header + EC_WRITE_U8(data, EC_EOE_FRAMETYPE_SET_IP_REQ); // Set IP parameter req. + EC_WRITE_U8(data + 1, 0x00); // not used + EC_WRITE_U16(data + 2, 0x0000); // not used + + EC_WRITE_U32(data + 4, + ((req->mac_address_included != 0) << 0) | + ((req->ip_address_included != 0) << 1) | + ((req->subnet_mask_included != 0) << 2) | + ((req->gateway_included != 0) << 3) | + ((req->dns_included != 0) << 4) | + ((req->name_included != 0) << 5) + ); + + cur = data + 8; + + if (req->mac_address_included) { + memcpy(cur, req->mac_address, ETH_ALEN); + } + cur += ETH_ALEN; + + if (req->ip_address_included) { + memcpy_swap32(cur, &req->ip_address); + } + cur += 4; + + if (req->subnet_mask_included) { + memcpy_swap32(cur, &req->subnet_mask); + } + cur += 4; + + if (req->gateway_included) { + memcpy_swap32(cur, &req->gateway); + } + cur += 4; + + if (req->dns_included) { + memcpy_swap32(cur, &req->dns); + } + cur += 4; + + if (req->name_included) { + memcpy(cur, req->name, EC_MAX_HOSTNAME_SIZE); + } + cur += EC_MAX_HOSTNAME_SIZE; + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "Set IP parameter request:\n"); + ec_print_data(data, cur - data); + } + + fsm->request->jiffies_sent = jiffies; + + return 0; +} + +/****************************************************************************/ + +/** EoE state: SET IP START. + */ +void ec_fsm_eoe_set_ip_start( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + EC_SLAVE_DBG(slave, 1, "Setting IP parameters.\n"); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_EOE)) { + EC_SLAVE_ERR(slave, "Slave does not support EoE!\n"); + fsm->state = ec_fsm_eoe_error; + return; + } + + if (ec_fsm_eoe_prepare_set(fsm, datagram)) { + fsm->state = ec_fsm_eoe_error; + return; + } + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_eoe_set_ip_request; +} + +/****************************************************************************/ + +/** EoE state: SET IP REQUEST. + */ +void ec_fsm_eoe_set_ip_request( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_eoe_prepare_set(fsm, datagram)) { + fsm->state = ec_fsm_eoe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Failed to receive EoE set IP parameter" + " request: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + unsigned long diff_ms = + (jiffies - fsm->request->jiffies_sent) * 1000 / HZ; + + if (!fsm->datagram->working_counter) { + if (diff_ms < EC_EOE_RESPONSE_TIMEOUT) { + // no response; send request datagram again + if (ec_fsm_eoe_prepare_set(fsm, datagram)) { + fsm->state = ec_fsm_eoe_error; + } + return; + } + } + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Reception of EoE set IP parameter request" + " failed after %lu ms: ", diff_ms); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_eoe_set_ip_check; + fsm->frame_type_retries = 10; +} + +/****************************************************************************/ + +/** EoE state: SET IP CHECK. + */ +void ec_fsm_eoe_set_ip_check( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Failed to receive EoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Reception of EoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= EC_EOE_RESPONSE_TIMEOUT) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Timeout after %lu ms while waiting for" + " set IP parameter response.\n", diff_ms); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_eoe_set_ip_response; +} + +/****************************************************************************/ + +/** EoE state: SET IP RESPONSE. + */ +void ec_fsm_eoe_set_ip_response( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + uint8_t *data, mbox_prot, frame_type; + size_t rec_size; + ec_eoe_request_t *req = fsm->request; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Failed to receive EoE read response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Reception of EoE read response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_eoe_error; + return; + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "Set IP parameter response:\n"); + ec_print_data(data, rec_size); + } + + if (mbox_prot != EC_MBOX_TYPE_EOE) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + return; + } + + if (rec_size < 4) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Received currupted EoE set IP parameter response" + " (%zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + return; + } + + frame_type = EC_READ_U8(data) & 0x0f; + + if (frame_type != EC_EOE_FRAMETYPE_SET_IP_RES) { + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "Received no set IP parameter response" + " (frame type %x).\n", frame_type); + ec_print_data(data, rec_size); + } + if (fsm->frame_type_retries--) { + // there may be an EoE segment left in the mailbox. + // discard it and receive again. + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_eoe_set_ip_check; + return; + } + else { + EC_SLAVE_ERR(slave, "Received no set IP parameter response.\n"); + fsm->state = ec_fsm_eoe_error; + return; + } + } + + req->result = EC_READ_U16(data + 2); // result code 0x0000 means success + + if (req->result) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_DBG(slave, 1, "EoE set IP parameters failed with result code" + " 0x%04X.\n", req->result); + } else { + fsm->state = ec_fsm_eoe_end; // success + } +} + +/****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_eoe_error( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_eoe_end( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_eoe.h b/ubuntu/igh-ecat/master/fsm_eoe.h new file mode 100644 index 00000000000000..7f901bdd5e3ba0 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_eoe.h @@ -0,0 +1,67 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2014 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT EoE set IP parameter state machines. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_EOE_H__ +#define __EC_FSM_EOE_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" +#include "eoe_request.h" + +/****************************************************************************/ + +typedef struct ec_fsm_eoe ec_fsm_eoe_t; /**< \see ec_fsm_eoe */ + +/** Finite state machines for the Ethernet over EtherCAT protocol. + */ +struct ec_fsm_eoe { + ec_slave_t *slave; /**< slave the FSM runs on */ + unsigned int retries; /**< retries upon datagram timeout */ + + void (*state)(ec_fsm_eoe_t *, ec_datagram_t *); /**< EoE state function */ + ec_datagram_t *datagram; /**< Datagram used in the previous step. */ + unsigned long jiffies_start; /**< Timestamp. */ + ec_eoe_request_t *request; /**< EoE request */ + unsigned int frame_type_retries; /**< retries upon wrong frame type. */ +}; + +/****************************************************************************/ + +void ec_fsm_eoe_init(ec_fsm_eoe_t *); +void ec_fsm_eoe_clear(ec_fsm_eoe_t *); + +void ec_fsm_eoe_set_ip_param(ec_fsm_eoe_t *, ec_slave_t *, + ec_eoe_request_t *); + +int ec_fsm_eoe_exec(ec_fsm_eoe_t *, ec_datagram_t *); +int ec_fsm_eoe_success(const ec_fsm_eoe_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_foe.c b/ubuntu/igh-ecat/master/fsm_foe.c new file mode 100644 index 00000000000000..126c306e341c53 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_foe.c @@ -0,0 +1,915 @@ +/***************************************************************************** + * + * Copyright (C) 2008 Olav Zarges, imc Messsysteme GmbH + * 2013 Florian Pose + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT FoE state machines. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "fsm_foe.h" +#include "foe.h" + +/****************************************************************************/ + +/** Maximum time in ms to wait for responses when reading out the dictionary. + */ +#define EC_FSM_FOE_TIMEOUT 3000 + +/** Size of the FoE header. + */ +#define EC_FOE_HEADER_SIZE 6 +// uint8_t OpCode +// uint8_t reserved +// uint32_t PacketNo, Password, ErrorCode + +//#define DEBUG_FOE + +/****************************************************************************/ + +/** FoE OpCodes. + */ +enum { + EC_FOE_OPCODE_RRQ = 1, /**< Read request. */ + EC_FOE_OPCODE_WRQ = 2, /**< Write request. */ + EC_FOE_OPCODE_DATA = 3, /**< Data. */ + EC_FOE_OPCODE_ACK = 4, /**< Acknowledge. */ + EC_FOE_OPCODE_ERR = 5, /**< Error. */ + EC_FOE_OPCODE_BUSY = 6 /**< Busy. */ +}; + +/****************************************************************************/ + +int ec_foe_prepare_data_send(ec_fsm_foe_t *, ec_datagram_t *); +int ec_foe_prepare_wrq_send(ec_fsm_foe_t *, ec_datagram_t *); +int ec_foe_prepare_rrq_send(ec_fsm_foe_t *, ec_datagram_t *); +int ec_foe_prepare_send_ack(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_foe_set_tx_error(ec_fsm_foe_t *, uint32_t); +void ec_foe_set_rx_error(ec_fsm_foe_t *, uint32_t); + +void ec_fsm_foe_end(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_error(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_fsm_foe_state_wrq_sent(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_state_rrq_sent(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_fsm_foe_state_ack_check(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_state_ack_read(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_fsm_foe_state_data_sent(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_fsm_foe_state_data_check(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_state_data_read(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_state_sent_ack(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_fsm_foe_write_start(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_read_start(ec_fsm_foe_t *, ec_datagram_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_foe_init( + ec_fsm_foe_t *fsm /**< finite state machine */ + ) +{ + fsm->state = NULL; + fsm->datagram = NULL; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_foe_clear(ec_fsm_foe_t *fsm /**< finite state machine */) +{ +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * \return 1, if the datagram was used, else 0. + */ +int ec_fsm_foe_exec( + ec_fsm_foe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + int datagram_used = 0; + + if (fsm->datagram && + (fsm->datagram->state == EC_DATAGRAM_INIT || + fsm->datagram->state == EC_DATAGRAM_QUEUED || + fsm->datagram->state == EC_DATAGRAM_SENT)) { + // datagram not received yet + return datagram_used; + } + + fsm->state(fsm, datagram); + + datagram_used = + fsm->state != ec_fsm_foe_end && fsm->state != ec_fsm_foe_error; + + if (datagram_used) { + fsm->datagram = datagram; + } else { + fsm->datagram = NULL; + } + + return datagram_used; +} + +/****************************************************************************/ + +/** Returns, if the state machine terminated with success. + * \return non-zero if successful. + */ +int ec_fsm_foe_success(const ec_fsm_foe_t *fsm /**< Finite state machine */) +{ + return fsm->state == ec_fsm_foe_end; +} + +/****************************************************************************/ + +/** Prepares an FoE transfer. + */ +void ec_fsm_foe_transfer( + ec_fsm_foe_t *fsm, /**< State machine. */ + ec_slave_t *slave, /**< EtherCAT slave. */ + ec_foe_request_t *request /**< Sdo request. */ + ) +{ + fsm->slave = slave; + fsm->request = request; + + if (request->dir == EC_DIR_OUTPUT) { + fsm->tx_buffer = fsm->request->buffer; + fsm->tx_buffer_size = fsm->request->data_size; + fsm->tx_buffer_offset = 0; + + fsm->tx_filename = fsm->request->file_name; + fsm->tx_filename_len = strlen(fsm->tx_filename); + + fsm->state = ec_fsm_foe_write_start; + } + else { + fsm->rx_buffer = fsm->request->buffer; + fsm->rx_buffer_size = fsm->request->buffer_size; + + fsm->rx_filename = fsm->request->file_name; + fsm->rx_filename_len = strlen(fsm->rx_filename); + + fsm->state = ec_fsm_foe_read_start; + } +} + +/****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_foe_error( + ec_fsm_foe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_foe_end( + ec_fsm_foe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif +} + +/****************************************************************************/ + +/** Sends a file or the next fragment. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_prepare_data_send( + ec_fsm_foe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + size_t remaining_size, current_size; + uint8_t *data; + + remaining_size = fsm->tx_buffer_size - fsm->tx_buffer_offset; + + if (remaining_size < fsm->slave->configured_tx_mailbox_size + - EC_MBOX_HEADER_SIZE - EC_FOE_HEADER_SIZE) { + current_size = remaining_size; + fsm->tx_last_packet = 1; + } else { + current_size = fsm->slave->configured_tx_mailbox_size + - EC_MBOX_HEADER_SIZE - EC_FOE_HEADER_SIZE; + } + + data = ec_slave_mbox_prepare_send(fsm->slave, + datagram, EC_MBOX_TYPE_FOE, current_size + EC_FOE_HEADER_SIZE); + if (IS_ERR(data)) { + return -1; + } + + EC_WRITE_U16(data, EC_FOE_OPCODE_DATA); // OpCode = DataBlock req. + EC_WRITE_U32(data + 2, fsm->tx_packet_no); // PacketNo, Password + + memcpy(data + EC_FOE_HEADER_SIZE, + fsm->tx_buffer + fsm->tx_buffer_offset, current_size); + fsm->tx_current_size = current_size; + + return 0; +} + +/****************************************************************************/ + +/** Prepare a write request (WRQ) with filename + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_prepare_wrq_send( + ec_fsm_foe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + size_t current_size; + uint8_t *data; + + fsm->tx_buffer_offset = 0; + fsm->tx_current_size = 0; + fsm->tx_packet_no = 0; + fsm->tx_last_packet = 0; + + current_size = fsm->tx_filename_len; + + data = ec_slave_mbox_prepare_send(fsm->slave, datagram, + EC_MBOX_TYPE_FOE, current_size + EC_FOE_HEADER_SIZE); + if (IS_ERR(data)) { + return -1; + } + + EC_WRITE_U16( data, EC_FOE_OPCODE_WRQ); // fsm write request + EC_WRITE_U32( data + 2, fsm->tx_packet_no ); + + memcpy(data + EC_FOE_HEADER_SIZE, fsm->tx_filename, current_size); + + return 0; +} + +/****************************************************************************/ + +/** Initializes the FoE write state machine. + */ +void ec_fsm_foe_write_start( + ec_fsm_foe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + fsm->tx_buffer_offset = 0; + fsm->tx_current_size = 0; + fsm->tx_packet_no = 0; + fsm->tx_last_packet = 0; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (!(slave->sii.mailbox_protocols & EC_MBOX_FOE)) { + ec_foe_set_tx_error(fsm, FOE_MBOX_PROT_ERROR); + EC_SLAVE_ERR(slave, "Slave does not support FoE!\n"); + return; + } + + if (ec_foe_prepare_wrq_send(fsm, datagram)) { + ec_foe_set_tx_error(fsm, FOE_PROT_ERROR); + return; + } + + fsm->state = ec_fsm_foe_state_wrq_sent; +} + +/****************************************************************************/ + +/** Check for acknowledge. + */ +void ec_fsm_foe_state_ack_check( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to receive FoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE mailbox check datagram" + " failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + // slave did not put anything in the mailbox yet + unsigned long diff_ms = (fsm->datagram->jiffies_received - + fsm->jiffies_start) * 1000 / HZ; + if (diff_ms >= EC_FSM_FOE_TIMEOUT) { + ec_foe_set_tx_error(fsm, FOE_TIMEOUT_ERROR); + EC_SLAVE_ERR(slave, "Timeout while waiting for ack response.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_ack_read; +} + +/****************************************************************************/ + +/** Acknowledge a read operation. + */ +void ec_fsm_foe_state_ack_read( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t *data, mbox_prot; + uint8_t opCode; + size_t rec_size; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to receive FoE ack response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE ack response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + ec_foe_set_tx_error(fsm, FOE_PROT_ERROR); + return; + } + + if (mbox_prot != EC_MBOX_TYPE_FOE) { + ec_foe_set_tx_error(fsm, FOE_MBOX_PROT_ERROR); + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + return; + } + + opCode = EC_READ_U8(data); + + if (opCode == EC_FOE_OPCODE_BUSY) { + // slave not ready + if (ec_foe_prepare_data_send(fsm, datagram)) { + ec_foe_set_tx_error(fsm, FOE_PROT_ERROR); + EC_SLAVE_ERR(slave, "Slave is busy.\n"); + return; + } + fsm->state = ec_fsm_foe_state_data_sent; + return; + } + + if (opCode == EC_FOE_OPCODE_ACK) { + fsm->tx_packet_no++; + fsm->tx_buffer_offset += fsm->tx_current_size; + + if (fsm->tx_last_packet) { + fsm->state = ec_fsm_foe_end; + return; + } + + if (ec_foe_prepare_data_send(fsm, datagram)) { + ec_foe_set_tx_error(fsm, FOE_PROT_ERROR); + return; + } + fsm->state = ec_fsm_foe_state_data_sent; + return; + } + ec_foe_set_tx_error(fsm, FOE_ACK_ERROR); +} + +/****************************************************************************/ + +/** State: WRQ SENT. + * + * Checks is the previous transmit datagram succeded and sends the next + * fragment, if necessary. + */ +void ec_fsm_foe_state_wrq_sent( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to send FoE WRQ: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + // slave did not put anything in the mailbox yet + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE WRQ failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_ack_check; +} + +/****************************************************************************/ + +/** State: WRQ SENT. + * + * Checks is the previous transmit datagram succeded and sends the next + * fragment, if necessary. + */ +void ec_fsm_foe_state_data_sent( + ec_fsm_foe_t *fsm, /**< Foe statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_tx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to receive FoE ack response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + ec_foe_set_tx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE data send failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); + fsm->jiffies_start = jiffies; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_ack_check; +} + +/****************************************************************************/ + +/** Prepare a read request (RRQ) with filename + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_prepare_rrq_send( + ec_fsm_foe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + size_t current_size; + uint8_t *data; + + current_size = fsm->rx_filename_len; + + data = ec_slave_mbox_prepare_send(fsm->slave, datagram, + EC_MBOX_TYPE_FOE, current_size + EC_FOE_HEADER_SIZE); + if (IS_ERR(data)) { + return -1; + } + + EC_WRITE_U16(data, EC_FOE_OPCODE_RRQ); // fsm read request + EC_WRITE_U32(data + 2, 0x00000000); // no passwd + memcpy(data + EC_FOE_HEADER_SIZE, fsm->rx_filename, current_size); + + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(fsm->slave, 1, "FoE Read Request:\n"); + ec_print_data(data, current_size + EC_FOE_HEADER_SIZE); + } + + return 0; +} + +/****************************************************************************/ + +/** Prepare to send an acknowledge. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_prepare_send_ack( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + uint8_t *data; + + data = ec_slave_mbox_prepare_send(fsm->slave, datagram, + EC_MBOX_TYPE_FOE, EC_FOE_HEADER_SIZE); + if (IS_ERR(data)) { + return -1; + } + + EC_WRITE_U16(data, EC_FOE_OPCODE_ACK); + EC_WRITE_U32(data + 2, fsm->rx_expected_packet_no); + + return 0; +} + +/****************************************************************************/ + +/** State: RRQ SENT. + * + * Checks is the previous transmit datagram succeeded and sends the next + * fragment, if necessary. + */ +void ec_fsm_foe_state_rrq_sent( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to send FoE RRQ: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + // slave did not put anything in the mailbox yet + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE RRQ failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_data_check; +} + +/****************************************************************************/ + +/** Starting state for read operations. + */ +void ec_fsm_foe_read_start( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + fsm->rx_buffer_offset = 0; + fsm->rx_expected_packet_no = 1; + fsm->rx_last_packet = 0; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (!(slave->sii.mailbox_protocols & EC_MBOX_FOE)) { + ec_foe_set_tx_error(fsm, FOE_MBOX_PROT_ERROR); + EC_SLAVE_ERR(slave, "Slave does not support FoE!\n"); + return; + } + + if (ec_foe_prepare_rrq_send(fsm, datagram)) { + ec_foe_set_rx_error(fsm, FOE_PROT_ERROR); + return; + } + + fsm->state = ec_fsm_foe_state_rrq_sent; +} + +/****************************************************************************/ + +/** Check for data. + */ +void ec_fsm_foe_state_data_check( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to send FoE DATA READ: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE DATA READ: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = (fsm->datagram->jiffies_received - + fsm->jiffies_start) * 1000 / HZ; + if (diff_ms >= EC_FSM_FOE_TIMEOUT) { + ec_foe_set_tx_error(fsm, FOE_TIMEOUT_ERROR); + EC_SLAVE_ERR(slave, "Timeout while waiting for ack response.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_data_read; +} + +/****************************************************************************/ + +/** Start reading data. + */ +void ec_fsm_foe_state_data_read( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + size_t rec_size; + uint8_t *data, opCode, packet_no, mbox_prot; + + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to receive FoE DATA READ datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE DATA READ failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + ec_foe_set_rx_error(fsm, FOE_MBOX_FETCH_ERROR); + return; + } + + if (mbox_prot != EC_MBOX_TYPE_FOE) { + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + ec_foe_set_rx_error(fsm, FOE_PROT_ERROR); + return; + } + + opCode = EC_READ_U8(data); + + if (opCode == EC_FOE_OPCODE_BUSY) { + if (ec_foe_prepare_send_ack(fsm, datagram)) { + ec_foe_set_rx_error(fsm, FOE_PROT_ERROR); + } + return; + } + + if (opCode == EC_FOE_OPCODE_ERR) { + fsm->request->error_code = EC_READ_U32(data + 2); + EC_SLAVE_ERR(slave, "Received FoE Error Request (code 0x%08x).\n", + fsm->request->error_code); + if (rec_size > 6) { + uint8_t text[256]; + strscpy(text, data + 6, min(rec_size - 6, sizeof(text))); + EC_SLAVE_ERR(slave, "FoE Error Text: %s\n", text); + } + ec_foe_set_rx_error(fsm, FOE_OPCODE_ERROR); + return; + } + + if (opCode != EC_FOE_OPCODE_DATA) { + EC_SLAVE_ERR(slave, "Received OPCODE %x, expected %x.\n", + opCode, EC_FOE_OPCODE_DATA); + fsm->request->error_code = 0x00000000; + ec_foe_set_rx_error(fsm, FOE_OPCODE_ERROR); + return; + } + + packet_no = EC_READ_U16(data + 2); + if (packet_no != fsm->rx_expected_packet_no) { + EC_SLAVE_ERR(slave, "Received unexpected packet number.\n"); + ec_foe_set_rx_error(fsm, FOE_PACKETNO_ERROR); + return; + } + + rec_size -= EC_FOE_HEADER_SIZE; + + if (fsm->rx_buffer_size >= fsm->rx_buffer_offset + rec_size) { + memcpy(fsm->rx_buffer + fsm->rx_buffer_offset, + data + EC_FOE_HEADER_SIZE, rec_size); + fsm->rx_buffer_offset += rec_size; + } + + fsm->rx_last_packet = + (rec_size + EC_MBOX_HEADER_SIZE + EC_FOE_HEADER_SIZE + != slave->configured_rx_mailbox_size); + + if (fsm->rx_last_packet || + (slave->configured_rx_mailbox_size - EC_MBOX_HEADER_SIZE + - EC_FOE_HEADER_SIZE + fsm->rx_buffer_offset) + <= fsm->rx_buffer_size) { + // either it was the last packet or a new packet will fit into the + // delivered buffer +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "last_packet=true\n"); +#endif + if (ec_foe_prepare_send_ack(fsm, datagram)) { + ec_foe_set_rx_error(fsm, FOE_RX_DATA_ACK_ERROR); + return; + } + + fsm->state = ec_fsm_foe_state_sent_ack; + } + else { + // no more data fits into the delivered buffer + // ... wait for new read request + EC_SLAVE_ERR(slave, "Data do not fit in receive buffer!\n"); + printk(KERN_CONT " rx_buffer_size = %d\n", fsm->rx_buffer_size); + printk(KERN_CONT "rx_buffer_offset = %d\n", fsm->rx_buffer_offset); + printk(KERN_CONT " rec_size = %zd\n", rec_size); + printk(KERN_CONT " rx_mailbox_size = %d\n", + slave->configured_rx_mailbox_size); + printk(KERN_CONT " rx_last_packet = %d\n", fsm->rx_last_packet); + fsm->request->result = FOE_READY; + } +} + +/****************************************************************************/ + +/** Sent an acknowledge. + */ +void ec_fsm_foe_state_sent_ack( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to send FoE ACK: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + // slave did not put anything into the mailbox yet + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE ACK failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + + if (fsm->rx_last_packet) { + fsm->rx_expected_packet_no = 0; + fsm->request->data_size = fsm->rx_buffer_offset; + fsm->state = ec_fsm_foe_end; + } + else { + fsm->rx_expected_packet_no++; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_data_check; + } +} + +/****************************************************************************/ + +/** Set an error code and go to the send error state. + */ +void ec_foe_set_tx_error( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + uint32_t errorcode /**< FoE error code. */ + ) +{ + fsm->request->result = errorcode; + fsm->state = ec_fsm_foe_error; +} + +/****************************************************************************/ + +/** Set an error code and go to the receive error state. + */ +void ec_foe_set_rx_error( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + uint32_t errorcode /**< FoE error code. */ + ) +{ + fsm->request->result = errorcode; + fsm->state = ec_fsm_foe_error; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_foe.h b/ubuntu/igh-ecat/master/fsm_foe.h new file mode 100644 index 00000000000000..55711dccee0692 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_foe.h @@ -0,0 +1,87 @@ +/***************************************************************************** + * + * Copyright (C) 2008 Olav Zarges, imc Messsysteme GmbH + * 2009-2012 Florian Pose + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT FoE state machines. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_FOE_H__ +#define __EC_FSM_FOE_H__ + +#include "globals.h" +#include "../include/ecrt.h" +#include "datagram.h" +#include "slave.h" +#include "foe_request.h" + +/****************************************************************************/ + +typedef struct ec_fsm_foe ec_fsm_foe_t; /**< \see ec_fsm_foe */ + +/** Finite state machines for the CANopen-over-EtherCAT protocol. + */ +struct ec_fsm_foe { + ec_slave_t *slave; /**< Slave the FSM runs on. */ + unsigned int retries; /**< Retries upon datagram timeout */ + + void (*state)(ec_fsm_foe_t *, ec_datagram_t *); /**< FoE state function. + */ + ec_datagram_t *datagram; /**< Datagram used in previous step. */ + unsigned long jiffies_start; /**< FoE timestamp. */ + uint8_t subindex; /**< Current subindex. */ + ec_foe_request_t *request; /**< FoE request. */ + uint8_t toggle; /**< Toggle bit for segment commands. */ + + uint8_t *tx_buffer; /**< Buffer with data to transmit. */ + uint32_t tx_buffer_size; /**< Size of data to transmit. */ + uint32_t tx_buffer_offset; /**< Offset of data to tranmit next. */ + uint32_t tx_last_packet; /**< Current packet is last one to send. */ + uint32_t tx_packet_no; /**< FoE packet number. */ + uint32_t tx_current_size; /**< Size of current packet to send. */ + uint8_t *tx_filename; /**< Name of file to transmit. */ + uint32_t tx_filename_len; /**< Lenth of transmit file name. */ + + uint8_t *rx_buffer; /**< Buffer for received data. */ + uint32_t rx_buffer_size; /**< Size of receive buffer. */ + uint32_t rx_buffer_offset; /**< Offset in receive buffer. */ + uint32_t rx_expected_packet_no; /**< Expected receive packet number. */ + uint32_t rx_last_packet; /**< Current packet is the last to receive. */ + uint8_t *rx_filename; /**< Name of the file to receive. */ + uint32_t rx_filename_len; /**< Length of the receive file name. */ +}; + +/****************************************************************************/ + +void ec_fsm_foe_init(ec_fsm_foe_t *); +void ec_fsm_foe_clear(ec_fsm_foe_t *); + +int ec_fsm_foe_exec(ec_fsm_foe_t *, ec_datagram_t *); +int ec_fsm_foe_success(const ec_fsm_foe_t *); + +void ec_fsm_foe_transfer(ec_fsm_foe_t *, ec_slave_t *, ec_foe_request_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_master.c b/ubuntu/igh-ecat/master/fsm_master.c new file mode 100644 index 00000000000000..909c0115f4838b --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_master.c @@ -0,0 +1,1472 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT master state machine. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" +#ifdef EC_EOE +#include "ethernet.h" +#endif + +#include "fsm_master.h" +#include "fsm_foe.h" + +/****************************************************************************/ + +/** Time difference [ns] to tolerate without setting a new system time offset. + */ +#define EC_SYSTEM_TIME_TOLERANCE_NS 1000000 + +/****************************************************************************/ + +// prototypes for private methods +void ec_fsm_master_restart(ec_fsm_master_t *); +int ec_fsm_master_action_process_sii(ec_fsm_master_t *); +int ec_fsm_master_action_process_int_request(ec_fsm_master_t *); +void ec_fsm_master_action_idle(ec_fsm_master_t *); +void ec_fsm_master_action_next_slave_state(ec_fsm_master_t *); +void ec_fsm_master_action_configure(ec_fsm_master_t *); +u64 ec_fsm_master_dc_offset32(ec_fsm_master_t *, u64, u64, unsigned long); +u64 ec_fsm_master_dc_offset64(ec_fsm_master_t *, u64, u64, unsigned long); + +/****************************************************************************/ + +void ec_fsm_master_state_start(ec_fsm_master_t *); +void ec_fsm_master_state_broadcast(ec_fsm_master_t *); +void ec_fsm_master_state_read_state(ec_fsm_master_t *); +void ec_fsm_master_state_acknowledge(ec_fsm_master_t *); +void ec_fsm_master_state_configure_slave(ec_fsm_master_t *); +void ec_fsm_master_state_clear_addresses(ec_fsm_master_t *); +void ec_fsm_master_state_dc_measure_delays(ec_fsm_master_t *); +void ec_fsm_master_state_scan_slave(ec_fsm_master_t *); +void ec_fsm_master_state_dc_read_offset(ec_fsm_master_t *); +void ec_fsm_master_state_dc_write_offset(ec_fsm_master_t *); +void ec_fsm_master_state_assign_sii(ec_fsm_master_t *); +void ec_fsm_master_state_write_sii(ec_fsm_master_t *); +void ec_fsm_master_state_sdo_dictionary(ec_fsm_master_t *); +void ec_fsm_master_state_sdo_request(ec_fsm_master_t *); +void ec_fsm_master_state_soe_request(ec_fsm_master_t *); + +void ec_fsm_master_enter_clear_addresses(ec_fsm_master_t *); +void ec_fsm_master_enter_write_system_times(ec_fsm_master_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_master_init( + ec_fsm_master_t *fsm, /**< Master state machine. */ + ec_master_t *master, /**< EtherCAT master. */ + ec_datagram_t *datagram /**< Datagram object to use. */ + ) +{ + fsm->master = master; + fsm->datagram = datagram; + + // inits the member variables state, idle, dev_idx, link_state, + // slaves_responding, slave_states and rescan_required + ec_fsm_master_reset(fsm); + + fsm->retries = 0; + fsm->scan_jiffies = 0; + fsm->slave = NULL; + fsm->sii_request = NULL; + fsm->sii_index = 0; + fsm->sdo_request = NULL; + fsm->soe_request = NULL; + + // init sub-state-machines + ec_fsm_coe_init(&fsm->fsm_coe); + ec_fsm_soe_init(&fsm->fsm_soe); + ec_fsm_pdo_init(&fsm->fsm_pdo, &fsm->fsm_coe); +#ifdef EC_EOE + ec_fsm_eoe_init(&fsm->fsm_eoe); +#endif + ec_fsm_change_init(&fsm->fsm_change, fsm->datagram); + ec_fsm_slave_config_init(&fsm->fsm_slave_config, fsm->datagram, + &fsm->fsm_change, &fsm->fsm_coe, &fsm->fsm_soe, &fsm->fsm_pdo, + &fsm->fsm_eoe); + ec_fsm_slave_scan_init(&fsm->fsm_slave_scan, fsm->datagram, + &fsm->fsm_slave_config, &fsm->fsm_pdo); + ec_fsm_sii_init(&fsm->fsm_sii, fsm->datagram); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_master_clear( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + // clear sub-state machines + ec_fsm_coe_clear(&fsm->fsm_coe); + ec_fsm_soe_clear(&fsm->fsm_soe); + ec_fsm_pdo_clear(&fsm->fsm_pdo); +#ifdef EC_EOE + ec_fsm_eoe_clear(&fsm->fsm_eoe); +#endif + ec_fsm_change_clear(&fsm->fsm_change); + ec_fsm_slave_config_clear(&fsm->fsm_slave_config); + ec_fsm_slave_scan_clear(&fsm->fsm_slave_scan); + ec_fsm_sii_clear(&fsm->fsm_sii); +} + +/****************************************************************************/ + +/** Reset state machine. + */ +void ec_fsm_master_reset( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_device_index_t dev_idx; + + fsm->state = ec_fsm_master_state_start; + fsm->idle = 0; + fsm->dev_idx = EC_DEVICE_MAIN; + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(fsm->master); dev_idx++) { + fsm->link_state[dev_idx] = 0; + fsm->slaves_responding[dev_idx] = 0; + fsm->slave_states[dev_idx] = EC_SLAVE_STATE_UNKNOWN; + } + + fsm->rescan_required = 0; +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * If the state machine's datagram is not sent or received yet, the execution + * of the state machine is delayed to the next cycle. + * + * \return true, if the state machine was executed + */ +int ec_fsm_master_exec( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + if (fsm->datagram->state == EC_DATAGRAM_SENT + || fsm->datagram->state == EC_DATAGRAM_QUEUED) { + // datagram was not sent or received yet. + return 0; + } + + fsm->state(fsm); + return 1; +} + +/****************************************************************************/ + +/** + * \return true, if the state machine is in an idle phase + */ +int ec_fsm_master_idle( + const ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + return fsm->idle; +} + +/****************************************************************************/ + +/** Restarts the master state machine. + */ +void ec_fsm_master_restart( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + fsm->dev_idx = EC_DEVICE_MAIN; + fsm->state = ec_fsm_master_state_start; + fsm->state(fsm); // execute immediately +} + +/***************************************************************************** + * Master state machine + ****************************************************************************/ + +/** Master state: START. + * + * Starts with getting slave count and slave states. + */ +void ec_fsm_master_state_start( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + + fsm->idle = 1; + + // check for emergency requests + if (!list_empty(&master->emerg_reg_requests)) { + ec_reg_request_t *request; + + // get first request + request = list_entry(master->emerg_reg_requests.next, + ec_reg_request_t, list); + list_del_init(&request->list); // dequeue + request->state = EC_INT_REQUEST_BUSY; + + if (request->transfer_size > fsm->datagram->mem_size) { + EC_MASTER_ERR(master, "Emergency request data too large!\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&master->request_queue); + fsm->state(fsm); // continue + return; + } + + if (request->dir != EC_DIR_OUTPUT) { + EC_MASTER_ERR(master, "Emergency requests must be" + " write requests!\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&master->request_queue); + fsm->state(fsm); // continue + return; + } + + EC_MASTER_DBG(master, 1, "Writing emergency register request...\n"); + ec_datagram_apwr(fsm->datagram, request->ring_position, + request->address, request->transfer_size); + memcpy(fsm->datagram->data, request->data, request->transfer_size); + fsm->datagram->device_index = EC_DEVICE_MAIN; + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&master->request_queue); + return; + } + + ec_datagram_brd(fsm->datagram, 0x0130, 2); + ec_datagram_zero(fsm->datagram); + fsm->datagram->device_index = fsm->dev_idx; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_broadcast; +} + +/****************************************************************************/ + +/** Master state: BROADCAST. + * + * Processes the broadcast read slave count and slaves states. + */ +void ec_fsm_master_state_broadcast( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + unsigned int i, size; + ec_slave_t *slave; + ec_master_t *master = fsm->master; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + // bus topology change? + if (datagram->working_counter != fsm->slaves_responding[fsm->dev_idx]) { + fsm->rescan_required = 1; + fsm->slaves_responding[fsm->dev_idx] = datagram->working_counter; + EC_MASTER_INFO(master, "%u slave(s) responding on %s device. " + "Re-scanning on next possibility.\n", + fsm->slaves_responding[fsm->dev_idx], + ec_device_names[fsm->dev_idx != 0]); + } + + if (fsm->link_state[fsm->dev_idx] && + !master->devices[fsm->dev_idx].link_state) { + ec_device_index_t dev_idx; + + EC_MASTER_DBG(master, 1, "Master state machine detected " + "link down on %s device. Clearing slave list.\n", + ec_device_names[fsm->dev_idx != 0]); + +#ifdef EC_EOE + ec_master_eoe_stop(master); + ec_master_clear_eoe_handlers(master); +#endif + ec_master_clear_slaves(master); + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(master); dev_idx++) { + fsm->slave_states[dev_idx] = 0x00; + fsm->slaves_responding[dev_idx] = 0; /* Reset to trigger rescan on + next link up. */ + } + } + fsm->link_state[fsm->dev_idx] = master->devices[fsm->dev_idx].link_state; + + if (datagram->state == EC_DATAGRAM_RECEIVED && + fsm->slaves_responding[fsm->dev_idx]) { + uint8_t states = EC_READ_U8(datagram->data); + if (states != fsm->slave_states[fsm->dev_idx]) { + // slave states changed + char state_str[EC_STATE_STRING_SIZE]; + fsm->slave_states[fsm->dev_idx] = states; + ec_state_string(states, state_str, 1); + EC_MASTER_INFO(master, "Slave states on %s device: %s.\n", + ec_device_names[fsm->dev_idx != 0], state_str); + } + } else { + fsm->slave_states[fsm->dev_idx] = 0x00; + } + + fsm->dev_idx++; + if (fsm->dev_idx < ec_master_num_devices(master)) { + // check number of responding slaves on next device + fsm->state = ec_fsm_master_state_start; + fsm->state(fsm); // execute immediately + return; + } + + if (fsm->rescan_required) { + down(&master->scan_sem); + if (!master->allow_scan) { + up(&master->scan_sem); + } else { + unsigned int count = 0, next_dev_slave, ring_position; + ec_device_index_t dev_idx; + + master->scan_busy = 1; + master->scan_index = 0; + up(&master->scan_sem); + + EC_MASTER_INFO(master, "Re-scanning now.\n"); + + // clear all slaves and scan the bus + fsm->rescan_required = 0; + fsm->idle = 0; + fsm->scan_jiffies = jiffies; + +#ifdef EC_EOE + ec_master_eoe_stop(master); + ec_master_clear_eoe_handlers(master); +#endif + ec_master_clear_slaves(master); + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(master); dev_idx++) { + count += fsm->slaves_responding[dev_idx]; + } + + if (!count) { + // no slaves present -> finish state machine. + master->scan_busy = 0; + wake_up_interruptible(&master->scan_queue); + ec_fsm_master_restart(fsm); + return; + } + + size = sizeof(ec_slave_t) * count; + if (!(master->slaves = + (ec_slave_t *) kmalloc(size, GFP_KERNEL))) { + EC_MASTER_ERR(master, "Failed to allocate %u bytes" + " of slave memory!\n", size); + master->scan_busy = 0; + wake_up_interruptible(&master->scan_queue); + ec_fsm_master_restart(fsm); + return; + } + + // init slaves + dev_idx = EC_DEVICE_MAIN; + next_dev_slave = fsm->slaves_responding[dev_idx]; + ring_position = 0; + for (i = 0; i < count; i++, ring_position++) { + slave = master->slaves + i; + while (i >= next_dev_slave) { + dev_idx++; + next_dev_slave += fsm->slaves_responding[dev_idx]; + ring_position = 0; + } + + ec_slave_init(slave, master, dev_idx, ring_position, i + 1); + + // do not force reconfiguration in operation phase to avoid + // unnecesssary process data interruptions + if (master->phase != EC_OPERATION) { + slave->force_config = 1; + } + } + master->slave_count = count; + master->fsm_slave = master->slaves; + + /* start with first device with slaves responding; at least one + * has responding slaves, otherwise count would be zero. */ + fsm->dev_idx = EC_DEVICE_MAIN; + while (!fsm->slaves_responding[fsm->dev_idx]) { + fsm->dev_idx++; + } + + ec_fsm_master_enter_clear_addresses(fsm); + return; + } + } + + if (master->slave_count) { + + // application applied configurations + if (master->config_changed) { + master->config_changed = 0; + + EC_MASTER_DBG(master, 1, "Configuration changed.\n"); + + fsm->slave = master->slaves; // begin with first slave + ec_fsm_master_enter_write_system_times(fsm); + + } else { + // fetch state from first slave + fsm->slave = master->slaves; + ec_datagram_fprd(fsm->datagram, fsm->slave->station_address, + 0x0130, 2); + ec_datagram_zero(datagram); + fsm->datagram->device_index = fsm->slave->device_index; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_read_state; + } + } else { + ec_fsm_master_restart(fsm); + } +} + +/****************************************************************************/ + +/** Check for pending SII write requests and process one. + * + * \return non-zero, if an SII write request is processed. + */ +int ec_fsm_master_action_process_sii( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_sii_write_request_t *request; + ec_slave_config_t *config; + ec_flag_t *flag; + int assign_to_pdi; + + // search the first request to be processed + while (1) { + if (list_empty(&master->sii_requests)) + break; + + // get first request + request = list_entry(master->sii_requests.next, + ec_sii_write_request_t, list); + list_del_init(&request->list); // dequeue + request->state = EC_INT_REQUEST_BUSY; + + assign_to_pdi = 0; + config = request->slave->config; + if (config) { + flag = ec_slave_config_find_flag(config, "AssignToPdi"); + if (flag) { + assign_to_pdi = flag->value; + } + } + + if (assign_to_pdi) { + fsm->sii_request = request; + EC_SLAVE_DBG(request->slave, 1, + "Assigning SII back to EtherCAT.\n"); + ec_datagram_fpwr(fsm->datagram, request->slave->station_address, + 0x0500, 0x01); + EC_WRITE_U8(fsm->datagram->data, 0x00); // EtherCAT + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_assign_sii; + return 1; + } + + // found pending SII write operation. execute it! + EC_SLAVE_DBG(request->slave, 1, "Writing SII data...\n"); + fsm->sii_request = request; + fsm->sii_index = 0; + ec_fsm_sii_write(&fsm->fsm_sii, request->slave, request->offset, + request->words, EC_FSM_SII_USE_CONFIGURED_ADDRESS); + fsm->state = ec_fsm_master_state_write_sii; + fsm->state(fsm); // execute immediately + return 1; + } + + return 0; +} + +/****************************************************************************/ + +/** Check for pending internal SDO/SoE requests and process one. + * + * \return non-zero, if an SDO request is processed. + */ +int ec_fsm_master_action_process_int_request( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_slave_t *slave; + ec_sdo_request_t *sdo_req; + ec_soe_request_t *soe_req; + + // search for internal requests to be processed + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + + if (!slave->config) { + continue; + } + + list_for_each_entry(sdo_req, &slave->config->sdo_requests, list) { + if (sdo_req->state == EC_INT_REQUEST_QUEUED) { + + if (ec_sdo_request_timed_out(sdo_req)) { + sdo_req->state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_DBG(slave, 1, "Internal SDO request" + " timed out.\n"); + continue; + } + + if (slave->current_state == EC_SLAVE_STATE_INIT) { + sdo_req->state = EC_INT_REQUEST_FAILURE; + continue; + } + + sdo_req->state = EC_INT_REQUEST_BUSY; + EC_SLAVE_DBG(slave, 1, "Processing internal" + " SDO request...\n"); + fsm->idle = 0; + fsm->sdo_request = sdo_req; + fsm->slave = slave; + fsm->state = ec_fsm_master_state_sdo_request; + ec_fsm_coe_transfer(&fsm->fsm_coe, slave, sdo_req); + ec_fsm_coe_exec(&fsm->fsm_coe, fsm->datagram); + return 1; + } + } + + list_for_each_entry(soe_req, &slave->config->soe_requests, list) { + if (soe_req->state == EC_INT_REQUEST_QUEUED) { + + if (ec_soe_request_timed_out(soe_req)) { + soe_req->state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_DBG(slave, 1, "Internal SoE request" + " timed out.\n"); + continue; + } + + if (slave->current_state == EC_SLAVE_STATE_INIT) { + soe_req->state = EC_INT_REQUEST_FAILURE; + continue; + } + + soe_req->state = EC_INT_REQUEST_BUSY; + EC_SLAVE_DBG(slave, 1, "Processing internal" + " SoE request...\n"); + fsm->idle = 0; + fsm->soe_request = soe_req; + fsm->slave = slave; + fsm->state = ec_fsm_master_state_soe_request; + ec_fsm_soe_transfer(&fsm->fsm_soe, slave, soe_req); + ec_fsm_soe_exec(&fsm->fsm_soe, fsm->datagram); + return 1; + } + } + } + return 0; +} + +/****************************************************************************/ + +/** Master action: IDLE. + * + * Does secondary work. + */ +void ec_fsm_master_action_idle( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_slave_t *slave; + + // Check for pending internal SDO or SoE requests + if (ec_fsm_master_action_process_int_request(fsm)) { + return; + } + + // enable processing of requests + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + ec_fsm_slave_set_ready(&slave->fsm); + } + + // check, if slaves have an SDO dictionary to read out. + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + if (!(slave->sii.mailbox_protocols & EC_MBOX_COE) + || (slave->sii.has_general + && !slave->sii.coe_details.enable_sdo_info) + || slave->sdo_dictionary_fetched + || slave->current_state == EC_SLAVE_STATE_INIT + || slave->current_state == EC_SLAVE_STATE_UNKNOWN + || jiffies - slave->jiffies_preop < EC_WAIT_SDO_DICT * HZ + ) continue; + + EC_SLAVE_DBG(slave, 1, "Fetching SDO dictionary.\n"); + + slave->sdo_dictionary_fetched = 1; + + // start fetching SDO dictionary + fsm->idle = 0; + fsm->slave = slave; + fsm->state = ec_fsm_master_state_sdo_dictionary; + ec_fsm_coe_dictionary(&fsm->fsm_coe, slave); + ec_fsm_coe_exec(&fsm->fsm_coe, fsm->datagram); // execute immediately + fsm->datagram->device_index = fsm->slave->device_index; + return; + } + + // check for pending SII write operations. + if (ec_fsm_master_action_process_sii(fsm)) { + return; // SII write request found + } + + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ + +/** Master action: Get state of next slave. + */ +void ec_fsm_master_action_next_slave_state( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + + // is there another slave to query? + fsm->slave++; + if (fsm->slave < master->slaves + master->slave_count) { + // fetch state from next slave + fsm->idle = 1; + ec_datagram_fprd(fsm->datagram, + fsm->slave->station_address, 0x0130, 2); + ec_datagram_zero(fsm->datagram); + fsm->datagram->device_index = fsm->slave->device_index; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_read_state; + return; + } + + // all slaves processed + ec_fsm_master_action_idle(fsm); +} + +/****************************************************************************/ + +/** Master action: Configure. + */ +void ec_fsm_master_action_configure( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_slave_t *slave = fsm->slave; + + if (master->config_changed) { + master->config_changed = 0; + + // abort iterating through slaves, + // first compensate DC system time offsets, + // then begin configuring at slave 0 + EC_MASTER_DBG(master, 1, "Configuration changed" + " (aborting state check).\n"); + + fsm->slave = master->slaves; // begin with first slave + ec_fsm_master_enter_write_system_times(fsm); + return; + } + + // Does the slave have to be configured? + if ((slave->current_state != slave->requested_state + || slave->force_config) && !slave->error_flag) { + + // Start slave configuration + down(&master->config_sem); + master->config_busy = 1; + up(&master->config_sem); + + if (master->debug_level) { + char old_state[EC_STATE_STRING_SIZE], + new_state[EC_STATE_STRING_SIZE]; + ec_state_string(slave->current_state, old_state, 0); + ec_state_string(slave->requested_state, new_state, 0); + EC_SLAVE_DBG(slave, 1, "Changing state from %s to %s%s.\n", + old_state, new_state, + slave->force_config ? " (forced)" : ""); + } + + fsm->idle = 0; + fsm->state = ec_fsm_master_state_configure_slave; + ec_fsm_slave_config_start(&fsm->fsm_slave_config, slave); + fsm->state(fsm); // execute immediately + fsm->datagram->device_index = fsm->slave->device_index; + return; + } + + // process next slave + ec_fsm_master_action_next_slave_state(fsm); +} + +/****************************************************************************/ + +/** Master state: READ STATE. + * + * Fetches the AL state of a slave. + */ +void ec_fsm_master_state_read_state( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_ERR(slave, "Failed to receive AL state datagram: "); + ec_datagram_print_state(datagram); + ec_fsm_master_restart(fsm); + return; + } + + // did the slave not respond to its station address? + if (datagram->working_counter != 1) { + if (!slave->error_flag) { + slave->error_flag = 1; + EC_SLAVE_DBG(slave, 1, "Slave did not respond to state query.\n"); + } + ec_fsm_master_restart(fsm); + return; + } + + // A single slave responded + ec_slave_set_state(slave, EC_READ_U8(datagram->data)); + + if (!slave->error_flag) { + // Check, if new slave state has to be acknowledged + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + fsm->idle = 0; + fsm->state = ec_fsm_master_state_acknowledge; + ec_fsm_change_ack(&fsm->fsm_change, slave); + fsm->state(fsm); // execute immediately + return; + } + + // No acknowlegde necessary; check for configuration + ec_fsm_master_action_configure(fsm); + return; + } + + // slave has error flag set; process next one + ec_fsm_master_action_next_slave_state(fsm); +} + +/****************************************************************************/ + +/** Master state: ACKNOWLEDGE. + */ +void ec_fsm_master_state_acknowledge( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_change_exec(&fsm->fsm_change)) { + return; + } + + if (!ec_fsm_change_success(&fsm->fsm_change)) { + fsm->slave->error_flag = 1; + EC_SLAVE_ERR(slave, "Failed to acknowledge state change.\n"); + } + + ec_fsm_master_action_configure(fsm); +} + +/****************************************************************************/ + +/** Start clearing slave addresses. + */ +void ec_fsm_master_enter_clear_addresses( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + // broadcast clear all station addresses + ec_datagram_bwr(fsm->datagram, 0x0010, 2); + EC_WRITE_U16(fsm->datagram->data, 0x0000); + fsm->datagram->device_index = fsm->dev_idx; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_clear_addresses; +} + +/****************************************************************************/ + +/** Master state: CLEAR ADDRESSES. + */ +void ec_fsm_master_state_clear_addresses( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_MASTER_ERR(master, "Failed to receive address" + " clearing datagram on %s link: ", + ec_device_names[fsm->dev_idx != 0]); + ec_datagram_print_state(datagram); + master->scan_busy = 0; + master->scan_index = master->slave_count; + wake_up_interruptible(&master->scan_queue); + ec_fsm_master_restart(fsm); + return; + } + + if (datagram->working_counter != fsm->slaves_responding[fsm->dev_idx]) { + EC_MASTER_WARN(master, "Failed to clear station addresses on %s link:" + " Cleared %u of %u", + ec_device_names[fsm->dev_idx != 0], datagram->working_counter, + fsm->slaves_responding[fsm->dev_idx]); + } + + EC_MASTER_DBG(master, 1, "Sending broadcast-write" + " to measure transmission delays on %s link.\n", + ec_device_names[fsm->dev_idx != 0]); + + ec_datagram_bwr(datagram, 0x0900, 1); + ec_datagram_zero(datagram); + fsm->datagram->device_index = fsm->dev_idx; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_dc_measure_delays; +} + +/****************************************************************************/ + +/** Master state: DC MEASURE DELAYS. + */ +void ec_fsm_master_state_dc_measure_delays( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_MASTER_ERR(master, "Failed to receive delay measuring datagram" + " on %s link: ", ec_device_names[fsm->dev_idx != 0]); + ec_datagram_print_state(datagram); + master->scan_busy = 0; + master->scan_index = master->slave_count; + wake_up_interruptible(&master->scan_queue); + ec_fsm_master_restart(fsm); + return; + } + + EC_MASTER_DBG(master, 1, "%u slaves responded to delay measuring" + " on %s link.\n", + datagram->working_counter, ec_device_names[fsm->dev_idx != 0]); + + do { + fsm->dev_idx++; + } while (fsm->dev_idx < ec_master_num_devices(master) && + !fsm->slaves_responding[fsm->dev_idx]); + if (fsm->dev_idx < ec_master_num_devices(master)) { + ec_fsm_master_enter_clear_addresses(fsm); + return; + } + + EC_MASTER_INFO(master, "Scanning bus.\n"); + + // begin scanning of slaves + fsm->slave = master->slaves; + master->scan_index = 0; + EC_MASTER_DBG(master, 1, "Scanning slave %u on %s link.\n", + fsm->slave->ring_position, + ec_device_names[fsm->slave->device_index != 0]); + fsm->state = ec_fsm_master_state_scan_slave; + ec_fsm_slave_scan_start(&fsm->fsm_slave_scan, fsm->slave); + ec_fsm_slave_scan_exec(&fsm->fsm_slave_scan); // execute immediately + fsm->datagram->device_index = fsm->slave->device_index; +} + +/****************************************************************************/ + +/** Master state: SCAN SLAVE. + * + * Executes the sub-statemachine for the scanning of a slave. + */ +void ec_fsm_master_state_scan_slave( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; +#ifdef EC_EOE + ec_slave_t *slave = fsm->slave; +#endif + + if (ec_fsm_slave_scan_exec(&fsm->fsm_slave_scan)) { + return; + } + +#ifdef EC_EOE + if (slave->sii.mailbox_protocols & EC_MBOX_EOE) { + // create EoE handler for this slave + ec_eoe_t *eoe; + if (!(eoe = kmalloc(sizeof(ec_eoe_t), GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate EoE handler memory!\n"); + } else if (ec_eoe_init(eoe, slave)) { + EC_SLAVE_ERR(slave, "Failed to init EoE handler!\n"); + kfree(eoe); + } else { + list_add_tail(&eoe->list, &master->eoe_handlers); + } + } +#endif + + // another slave to fetch? + fsm->slave++; + master->scan_index++; + if (fsm->slave < master->slaves + master->slave_count) { + EC_MASTER_DBG(master, 1, "Scanning slave %u on %s link.\n", + fsm->slave->ring_position, + ec_device_names[fsm->slave->device_index != 0]); + ec_fsm_slave_scan_start(&fsm->fsm_slave_scan, fsm->slave); + ec_fsm_slave_scan_exec(&fsm->fsm_slave_scan); // execute immediately + fsm->datagram->device_index = fsm->slave->device_index; + return; + } + + EC_MASTER_INFO(master, "Bus scanning completed in %lu ms.\n", + (jiffies - fsm->scan_jiffies) * 1000 / HZ); + + master->scan_busy = 0; + master->scan_index = master->slave_count; + wake_up_interruptible(&master->scan_queue); + + ec_master_calc_dc(master); + + // Attach slave configurations + ec_master_attach_slave_configs(master); + +#ifdef EC_EOE + // check if EoE processing has to be started + ec_master_eoe_start(master); +#endif + + if (master->slave_count) { + master->config_changed = 0; + + fsm->slave = master->slaves; // begin with first slave + ec_fsm_master_enter_write_system_times(fsm); + } else { + ec_fsm_master_restart(fsm); + } +} + +/****************************************************************************/ + +/** Master state: CONFIGURE SLAVE. + * + * Starts configuring a slave. + */ +void ec_fsm_master_state_configure_slave( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + + if (ec_fsm_slave_config_exec(&fsm->fsm_slave_config)) { + return; + } + + fsm->slave->force_config = 0; + + // configuration finished + master->config_busy = 0; + wake_up_interruptible(&master->config_queue); + + if (!ec_fsm_slave_config_success(&fsm->fsm_slave_config)) { + // TODO: mark slave_config as failed. + } + + fsm->idle = 1; + ec_fsm_master_action_next_slave_state(fsm); +} + +/****************************************************************************/ + +/** Start writing DC system times. + */ +void ec_fsm_master_enter_write_system_times( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + + if (master->dc_ref_time) { + + while (fsm->slave < master->slaves + master->slave_count) { + if (!fsm->slave->base_dc_supported + || !fsm->slave->has_dc_system_time) { + fsm->slave++; + continue; + } + + EC_SLAVE_DBG(fsm->slave, 1, "Checking system time offset.\n"); + + // read DC system time (0x0910, 64 bit) + // gap (64 bit) + // and time offset (0x0920, 64 bit) + ec_datagram_fprd(fsm->datagram, fsm->slave->station_address, + 0x0910, 24); + fsm->datagram->device_index = fsm->slave->device_index; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_dc_read_offset; + return; + } + + } else { + if (master->active) { + EC_MASTER_WARN(master, "No application time received up to now," + " but master already active.\n"); + } else { + EC_MASTER_DBG(master, 1, "No app_time received up to now.\n"); + } + } + + // scanning and setting system times complete + ec_master_request_op(master); + EC_MASTER_DBG(master, 1, "After requesting OP, rescan_required is %u.\n", + fsm->rescan_required); + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ + +/** Configure 32 bit time offset. + * + * \return New offset. + */ +u64 ec_fsm_master_dc_offset32( + ec_fsm_master_t *fsm, /**< Master state machine. */ + u64 system_time, /**< System time register. */ + u64 old_offset, /**< Time offset register. */ + unsigned long jiffies_since_read /**< Jiffies for correction. */ + ) +{ + ec_slave_t *slave = fsm->slave; + u32 correction, system_time32, old_offset32, new_offset; + s32 time_diff; + + system_time32 = (u32) system_time; + old_offset32 = (u32) old_offset; + + // correct read system time by elapsed time since read operation + correction = jiffies_since_read * 1000 / HZ * 1000000; + system_time32 += correction; + time_diff = (u32) slave->master->app_time - system_time32; + + EC_SLAVE_DBG(slave, 1, "DC 32 bit system time offset calculation:" + " system_time=%u (corrected with %u)," + " app_time=%llu, diff=%i\n", + system_time32, correction, + slave->master->app_time, time_diff); + + if (EC_ABS(time_diff) > EC_SYSTEM_TIME_TOLERANCE_NS) { + new_offset = time_diff + old_offset32; + EC_SLAVE_DBG(slave, 1, "Setting time offset to %u (was %u)\n", + new_offset, old_offset32); + return (u64) new_offset; + } else { + EC_SLAVE_DBG(slave, 1, "Not touching time offset.\n"); + return old_offset; + } +} + +/****************************************************************************/ + +/** Configure 64 bit time offset. + * + * \return New offset. + */ +u64 ec_fsm_master_dc_offset64( + ec_fsm_master_t *fsm, /**< Master state machine. */ + u64 system_time, /**< System time register. */ + u64 old_offset, /**< Time offset register. */ + unsigned long jiffies_since_read /**< Jiffies for correction. */ + ) +{ + ec_slave_t *slave = fsm->slave; + u64 new_offset, correction; + s64 time_diff; + + // correct read system time by elapsed time since read operation + correction = (u64) (jiffies_since_read * 1000 / HZ) * 1000000; + system_time += correction; + time_diff = fsm->slave->master->app_time - system_time; + + EC_SLAVE_DBG(slave, 1, "DC 64 bit system time offset calculation:" + " system_time=%llu (corrected with %llu)," + " app_time=%llu, diff=%lli\n", + system_time, correction, + slave->master->app_time, time_diff); + + if (EC_ABS(time_diff) > EC_SYSTEM_TIME_TOLERANCE_NS) { + new_offset = time_diff + old_offset; + EC_SLAVE_DBG(slave, 1, "Setting time offset to %llu (was %llu)\n", + new_offset, old_offset); + } else { + new_offset = old_offset; + EC_SLAVE_DBG(slave, 1, "Not touching time offset.\n"); + } + + return new_offset; +} + +/****************************************************************************/ + +/** Master state: DC READ OFFSET. + */ +void ec_fsm_master_state_dc_read_offset( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + u64 system_time, old_offset, new_offset; + unsigned long jiffies_since_read; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_ERR(slave, "Failed to receive DC times datagram: "); + ec_datagram_print_state(datagram); + fsm->slave++; + ec_fsm_master_enter_write_system_times(fsm); + return; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(slave, "Failed to get DC times: "); + ec_datagram_print_wc_error(datagram); + fsm->slave++; + ec_fsm_master_enter_write_system_times(fsm); + return; + } + + system_time = EC_READ_U64(datagram->data); // 0x0910 + old_offset = EC_READ_U64(datagram->data + 16); // 0x0920 + jiffies_since_read = jiffies - datagram->jiffies_sent; + + if (slave->base_dc_range == EC_DC_32) { + new_offset = ec_fsm_master_dc_offset32(fsm, + system_time, old_offset, jiffies_since_read); + } else { + new_offset = ec_fsm_master_dc_offset64(fsm, + system_time, old_offset, jiffies_since_read); + } + + // set DC system time offset and transmission delay + ec_datagram_fpwr(datagram, slave->station_address, 0x0920, 12); + EC_WRITE_U64(datagram->data, new_offset); + EC_WRITE_U32(datagram->data + 8, slave->transmission_delay); + fsm->datagram->device_index = slave->device_index; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_dc_write_offset; +} + +/****************************************************************************/ + +/** Master state: DC WRITE OFFSET. + */ +void ec_fsm_master_state_dc_write_offset( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_ERR(slave, + "Failed to receive DC system time offset datagram: "); + ec_datagram_print_state(datagram); + fsm->slave++; + ec_fsm_master_enter_write_system_times(fsm); + return; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_ERR(slave, "Failed to set DC system time offset: "); + ec_datagram_print_wc_error(datagram); + fsm->slave++; + ec_fsm_master_enter_write_system_times(fsm); + return; + } + + fsm->slave++; + ec_fsm_master_enter_write_system_times(fsm); +} + +/****************************************************************************/ + +/** Master state: ASSIGN SII. + */ +void ec_fsm_master_state_assign_sii( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_sii_write_request_t *request = fsm->sii_request; + ec_slave_t *slave = request->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_ERR(slave, "Failed to receive SII assignment datagram: "); + ec_datagram_print_state(datagram); + goto cont; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_ERR(slave, "Failed to assign SII back to EtherCAT: "); + ec_datagram_print_wc_error(datagram); + goto cont; + } + +cont: + // found pending SII write operation. execute it! + EC_SLAVE_DBG(slave, 1, "Writing SII data (after assignment)...\n"); + fsm->sii_index = 0; + ec_fsm_sii_write(&fsm->fsm_sii, slave, request->offset, + request->words, EC_FSM_SII_USE_CONFIGURED_ADDRESS); + fsm->state = ec_fsm_master_state_write_sii; + fsm->state(fsm); // execute immediately +} + +/****************************************************************************/ + +/** Master state: WRITE SII. + */ +void ec_fsm_master_state_write_sii( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_sii_write_request_t *request = fsm->sii_request; + ec_slave_t *slave = request->slave; + + if (ec_fsm_sii_exec(&fsm->fsm_sii)) return; + + if (!ec_fsm_sii_success(&fsm->fsm_sii)) { + EC_SLAVE_ERR(slave, "Failed to write SII data.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&master->request_queue); + ec_fsm_master_restart(fsm); + return; + } + + fsm->sii_index++; + if (fsm->sii_index < request->nwords) { + ec_fsm_sii_write(&fsm->fsm_sii, slave, + request->offset + fsm->sii_index, + request->words + fsm->sii_index, + EC_FSM_SII_USE_CONFIGURED_ADDRESS); + ec_fsm_sii_exec(&fsm->fsm_sii); // execute immediately + return; + } + + // finished writing SII + EC_SLAVE_DBG(slave, 1, "Finished writing %zu words of SII data.\n", + request->nwords); + + if (request->offset <= 4 && request->offset + request->nwords > 4) { + // alias was written + slave->sii.alias = EC_READ_U16(request->words + 4); + // TODO: read alias from register 0x0012 + slave->effective_alias = slave->sii.alias; + } + // TODO: Evaluate other SII contents! + + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&master->request_queue); + + // check for another SII write request + if (ec_fsm_master_action_process_sii(fsm)) + return; // processing another request + + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ + +/** Master state: SDO DICTIONARY. + */ +void ec_fsm_master_state_sdo_dictionary( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = fsm->master; + + if (ec_fsm_coe_exec(&fsm->fsm_coe, fsm->datagram)) { + return; + } + + if (!ec_fsm_coe_success(&fsm->fsm_coe)) { + ec_fsm_master_restart(fsm); + return; + } + + // SDO dictionary fetching finished + + if (master->debug_level) { + unsigned int sdo_count, entry_count; + ec_slave_sdo_dict_info(slave, &sdo_count, &entry_count); + EC_SLAVE_DBG(slave, 1, "Fetched %u SDOs and %u entries.\n", + sdo_count, entry_count); + } + + // attach pdo names from dictionary + ec_slave_attach_pdo_names(slave); + + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ + +/** Master state: SDO REQUEST. + */ +void ec_fsm_master_state_sdo_request( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_sdo_request_t *request = fsm->sdo_request; + + if (!request) { + // configuration was cleared in the meantime + ec_fsm_master_restart(fsm); + return; + } + + if (ec_fsm_coe_exec(&fsm->fsm_coe, fsm->datagram)) { + return; + } + + if (!ec_fsm_coe_success(&fsm->fsm_coe)) { + EC_SLAVE_DBG(fsm->slave, 1, + "Failed to process internal SDO request.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->master->request_queue); + ec_fsm_master_restart(fsm); + return; + } + + // SDO request finished + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&fsm->master->request_queue); + + EC_SLAVE_DBG(fsm->slave, 1, "Finished internal SDO request.\n"); + + // check for another SDO/SoE request + if (ec_fsm_master_action_process_int_request(fsm)) { + return; // processing another request + } + + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ + +/** Master state: SoE REQUEST. + */ +void ec_fsm_master_state_soe_request( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_soe_request_t *request = fsm->soe_request; + + if (!request) { + // configuration was cleared in the meantime + ec_fsm_master_restart(fsm); + return; + } + + if (ec_fsm_soe_exec(&fsm->fsm_soe, fsm->datagram)) { + return; + } + + if (!ec_fsm_soe_success(&fsm->fsm_soe)) { + EC_SLAVE_DBG(fsm->slave, 1, + "Failed to process internal SoE request.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->master->request_queue); + ec_fsm_master_restart(fsm); + return; + } + + // SoE request finished + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&fsm->master->request_queue); + + EC_SLAVE_DBG(fsm->slave, 1, "Finished internal SoE request.\n"); + + // check for another CoE/SoE request + if (ec_fsm_master_action_process_int_request(fsm)) { + return; // processing another request + } + + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_master.h b/ubuntu/igh-ecat/master/fsm_master.h new file mode 100644 index 00000000000000..d645786651ee33 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_master.h @@ -0,0 +1,107 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT master state machine. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_MASTER_H__ +#define __EC_FSM_MASTER_H__ + +#include "globals.h" +#include "datagram.h" +#include "foe_request.h" +#include "sdo_request.h" +#include "soe_request.h" +#include "fsm_slave_config.h" +#include "fsm_slave_scan.h" +#include "fsm_pdo.h" + +/****************************************************************************/ + +/** SII write request. + */ +typedef struct { + struct list_head list; /**< List head. */ + ec_slave_t *slave; /**< EtherCAT slave. */ + uint16_t offset; /**< SII word offset. */ + size_t nwords; /**< Number of words. */ + const uint16_t *words; /**< Pointer to the data words. */ + ec_internal_request_state_t state; /**< State of the request. */ +} ec_sii_write_request_t; + +/****************************************************************************/ + +typedef struct ec_fsm_master ec_fsm_master_t; /**< \see ec_fsm_master */ + +/** Finite state machine of an EtherCAT master. + */ +struct ec_fsm_master { + ec_master_t *master; /**< master the FSM runs on */ + ec_datagram_t *datagram; /**< datagram used in the state machine */ + unsigned int retries; /**< retries on datagram timeout. */ + + void (*state)(ec_fsm_master_t *); /**< master state function */ + ec_device_index_t dev_idx; /**< Current device index (for scanning etc.). + */ + int idle; /**< state machine is in idle phase */ + unsigned long scan_jiffies; /**< beginning of slave scanning */ + uint8_t link_state[EC_MAX_NUM_DEVICES]; /**< Last link state for every + device. */ + unsigned int slaves_responding[EC_MAX_NUM_DEVICES]; /**< Number of + responding slaves + for every device. */ + unsigned int rescan_required; /**< A bus rescan is required. */ + ec_slave_state_t slave_states[EC_MAX_NUM_DEVICES]; /**< AL states of + responding slaves for + every device. */ + ec_slave_t *slave; /**< current slave */ + ec_sii_write_request_t *sii_request; /**< SII write request */ + off_t sii_index; /**< index to SII write request data */ + ec_sdo_request_t *sdo_request; /**< SDO request to process. */ + ec_soe_request_t *soe_request; /**< SoE request to process. */ + + ec_fsm_coe_t fsm_coe; /**< CoE state machine */ + ec_fsm_soe_t fsm_soe; /**< SoE state machine */ + ec_fsm_pdo_t fsm_pdo; /**< PDO configuration state machine. */ + ec_fsm_eoe_t fsm_eoe; /**< EoE state machine */ + ec_fsm_change_t fsm_change; /**< State change state machine */ + ec_fsm_slave_config_t fsm_slave_config; /**< slave state machine */ + ec_fsm_slave_scan_t fsm_slave_scan; /**< slave state machine */ + ec_fsm_sii_t fsm_sii; /**< SII state machine */ +}; + +/****************************************************************************/ + +void ec_fsm_master_init(ec_fsm_master_t *, ec_master_t *, ec_datagram_t *); +void ec_fsm_master_clear(ec_fsm_master_t *); + +void ec_fsm_master_reset(ec_fsm_master_t *); + +int ec_fsm_master_exec(ec_fsm_master_t *); +int ec_fsm_master_idle(const ec_fsm_master_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_pdo.c b/ubuntu/igh-ecat/master/fsm_pdo.c new file mode 100644 index 00000000000000..0d5f87e16e78c8 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_pdo.c @@ -0,0 +1,806 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT PDO configuration state machine. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" + +#include "fsm_pdo.h" + +/****************************************************************************/ + +// prototypes for private methods +void ec_fsm_pdo_print(const ec_fsm_pdo_t *); +int ec_fsm_pdo_running(const ec_fsm_pdo_t *); +ec_pdo_t *ec_fsm_pdo_conf_action_next_pdo(const ec_fsm_pdo_t *, + const struct list_head *); + +/****************************************************************************/ + +void ec_fsm_pdo_read_state_start(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_read_state_pdo_count(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_read_state_pdo(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_read_state_pdo_entries(ec_fsm_pdo_t *, ec_datagram_t *); + +void ec_fsm_pdo_read_action_next_sync(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_read_action_next_pdo(ec_fsm_pdo_t *, ec_datagram_t *); + +void ec_fsm_pdo_conf_state_start(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_state_read_mapping(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_state_mapping(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_state_zero_pdo_count(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_state_assign_pdo(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_state_set_pdo_count(ec_fsm_pdo_t *, ec_datagram_t *); + +void ec_fsm_pdo_conf_action_next_sync(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_action_pdo_mapping(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_action_check_mapping(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_action_next_pdo_mapping(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_action_check_assignment(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_action_assign_pdo(ec_fsm_pdo_t *, ec_datagram_t *); + +void ec_fsm_pdo_state_end(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_state_error(ec_fsm_pdo_t *, ec_datagram_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_pdo_init( + ec_fsm_pdo_t *fsm, /**< PDO configuration state machine. */ + ec_fsm_coe_t *fsm_coe /**< CoE state machine to use */ + ) +{ + fsm->fsm_coe = fsm_coe; + ec_fsm_pdo_entry_init(&fsm->fsm_pdo_entry, fsm_coe); + ec_pdo_list_init(&fsm->pdos); + ec_sdo_request_init(&fsm->request); + ec_pdo_init(&fsm->slave_pdo); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_pdo_clear( + ec_fsm_pdo_t *fsm /**< PDO configuration state machine. */ + ) +{ + ec_fsm_pdo_entry_clear(&fsm->fsm_pdo_entry); + ec_pdo_list_clear(&fsm->pdos); + ec_sdo_request_clear(&fsm->request); + ec_pdo_clear(&fsm->slave_pdo); +} + +/****************************************************************************/ + +/** Print the current and desired PDO assignment. + */ +void ec_fsm_pdo_print( + const ec_fsm_pdo_t *fsm /**< PDO configuration state machine. */ + ) +{ + printk(KERN_CONT "Currently assigned PDOs: "); + ec_pdo_list_print(&fsm->sync->pdos); + printk(KERN_CONT ". PDOs to assign: "); + ec_pdo_list_print(&fsm->pdos); + printk(KERN_CONT "\n"); +} + +/****************************************************************************/ + +/** Start reading the PDO configuration. + */ +void ec_fsm_pdo_start_reading( + ec_fsm_pdo_t *fsm, /**< PDO configuration state machine. */ + ec_slave_t *slave /**< slave to configure */ + ) +{ + fsm->slave = slave; + fsm->state = ec_fsm_pdo_read_state_start; +} + +/****************************************************************************/ + +/** Start writing the PDO configuration. + */ +void ec_fsm_pdo_start_configuration( + ec_fsm_pdo_t *fsm, /**< PDO configuration state machine. */ + ec_slave_t *slave /**< slave to configure */ + ) +{ + fsm->slave = slave; + fsm->state = ec_fsm_pdo_conf_state_start; +} + +/****************************************************************************/ + +/** Get running state. + * + * \return false, if state machine has terminated + */ +int ec_fsm_pdo_running( + const ec_fsm_pdo_t *fsm /**< PDO configuration state machine. */ + ) +{ + return fsm->state != ec_fsm_pdo_state_end + && fsm->state != ec_fsm_pdo_state_error; +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * If the state machine's datagram is not sent or received yet, the execution + * of the state machine is delayed to the next cycle. + * + * \return false, if state machine has terminated + */ +int ec_fsm_pdo_exec( + ec_fsm_pdo_t *fsm, /**< PDO configuration state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + fsm->state(fsm, datagram); + + return ec_fsm_pdo_running(fsm); +} + +/****************************************************************************/ + +/** Get execution result. + * + * \return true, if the state machine terminated gracefully + */ +int ec_fsm_pdo_success( + const ec_fsm_pdo_t *fsm /**< PDO configuration state machine. */ + ) +{ + return fsm->state == ec_fsm_pdo_state_end; +} + +/***************************************************************************** + * Reading state funtions. + ****************************************************************************/ + +/** Start reading PDO assignment. + */ +void ec_fsm_pdo_read_state_start( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + // read PDO assignment for first sync manager not reserved for mailbox + fsm->sync_index = 1; // next is 2 + ec_fsm_pdo_read_action_next_sync(fsm, datagram); +} + +/****************************************************************************/ + +/** Read PDO assignment of next sync manager. + */ +void ec_fsm_pdo_read_action_next_sync( + ec_fsm_pdo_t *fsm, /**< finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + fsm->sync_index++; + + for (; fsm->sync_index < EC_MAX_SYNC_MANAGERS; fsm->sync_index++) { + if (!(fsm->sync = ec_slave_get_sync(slave, fsm->sync_index))) + continue; + + EC_SLAVE_DBG(slave, 1, "Reading PDO assignment of SM%u.\n", + fsm->sync_index); + + ec_pdo_list_clear_pdos(&fsm->pdos); + + ecrt_sdo_request_index(&fsm->request, 0x1C10 + fsm->sync_index, 0); + ecrt_sdo_request_read(&fsm->request); + fsm->state = ec_fsm_pdo_read_state_pdo_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + + EC_SLAVE_DBG(slave, 1, "Reading of PDO configuration finished.\n"); + + ec_pdo_list_clear_pdos(&fsm->pdos); + fsm->state = ec_fsm_pdo_state_end; +} + +/****************************************************************************/ + +/** Count assigned PDOs. + */ +void ec_fsm_pdo_read_state_pdo_count( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_ERR(fsm->slave, "Failed to read number of assigned PDOs" + " for SM%u.\n", fsm->sync_index); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + + if (fsm->request.data_size != sizeof(uint8_t)) { + EC_SLAVE_ERR(fsm->slave, "Invalid data size %zu returned" + " when uploading SDO 0x%04X:%02X.\n", fsm->request.data_size, + fsm->request.index, fsm->request.subindex); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + fsm->pdo_count = EC_READ_U8(fsm->request.data); + + EC_SLAVE_DBG(fsm->slave, 1, "%u PDOs assigned.\n", fsm->pdo_count); + + // read first PDO + fsm->pdo_pos = 1; + ec_fsm_pdo_read_action_next_pdo(fsm, datagram); +} + +/****************************************************************************/ + +/** Read next PDO. + */ +void ec_fsm_pdo_read_action_next_pdo( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (fsm->pdo_pos <= fsm->pdo_count) { + ecrt_sdo_request_index(&fsm->request, 0x1C10 + fsm->sync_index, + fsm->pdo_pos); + ecrt_sdo_request_read(&fsm->request); + fsm->state = ec_fsm_pdo_read_state_pdo; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + + // finished reading PDO configuration + + ec_pdo_list_copy(&fsm->sync->pdos, &fsm->pdos); + ec_pdo_list_clear_pdos(&fsm->pdos); + + // next sync manager + ec_fsm_pdo_read_action_next_sync(fsm, datagram); +} + +/****************************************************************************/ + +/** Fetch PDO information. + */ +void ec_fsm_pdo_read_state_pdo( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_ERR(fsm->slave, "Failed to read index of" + " assigned PDO %u from SM%u.\n", + fsm->pdo_pos, fsm->sync_index); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + + if (fsm->request.data_size != sizeof(uint16_t)) { + EC_SLAVE_ERR(fsm->slave, "Invalid data size %zu returned" + " when uploading SDO 0x%04X:%02X.\n", fsm->request.data_size, + fsm->request.index, fsm->request.subindex); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + + if (!(fsm->pdo = (ec_pdo_t *) + kmalloc(sizeof(ec_pdo_t), GFP_KERNEL))) { + EC_SLAVE_ERR(fsm->slave, "Failed to allocate PDO.\n"); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + + ec_pdo_init(fsm->pdo); + fsm->pdo->index = EC_READ_U16(fsm->request.data); + fsm->pdo->sync_index = fsm->sync_index; + + EC_SLAVE_DBG(fsm->slave, 1, "PDO 0x%04X.\n", fsm->pdo->index); + + list_add_tail(&fsm->pdo->list, &fsm->pdos.list); + + fsm->state = ec_fsm_pdo_read_state_pdo_entries; + ec_fsm_pdo_entry_start_reading(&fsm->fsm_pdo_entry, fsm->slave, fsm->pdo); + fsm->state(fsm, datagram); // execute immediately +} + +/****************************************************************************/ + +/** Fetch PDO information. + */ +void ec_fsm_pdo_read_state_pdo_entries( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_pdo_entry_exec(&fsm->fsm_pdo_entry, datagram)) { + return; + } + + if (!ec_fsm_pdo_entry_success(&fsm->fsm_pdo_entry)) { + EC_SLAVE_ERR(fsm->slave, "Failed to read mapped PDO entries" + " for PDO 0x%04X.\n", fsm->pdo->index); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + + // next PDO + fsm->pdo_pos++; + ec_fsm_pdo_read_action_next_pdo(fsm, datagram); +} + +/***************************************************************************** + * Writing state functions. + ****************************************************************************/ + +/** Start PDO configuration. + */ +void ec_fsm_pdo_conf_state_start( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (!fsm->slave->config) { + fsm->state = ec_fsm_pdo_state_end; + return; + } + + fsm->sync_index = 1; // next is 2 + ec_fsm_pdo_conf_action_next_sync(fsm, datagram); +} + +/****************************************************************************/ + +/** Assign next PDO. + * + * \return Next PDO, or NULL. + */ +ec_pdo_t *ec_fsm_pdo_conf_action_next_pdo( + const ec_fsm_pdo_t *fsm, /**< PDO configuration state machine. */ + const struct list_head *list /**< current PDO list item */ + ) +{ + list = list->next; + if (list == &fsm->pdos.list) + return NULL; // no next PDO + return list_entry(list, ec_pdo_t, list); +} + +/****************************************************************************/ + +/** Get the next sync manager for a pdo configuration. + */ +void ec_fsm_pdo_conf_action_next_sync( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + fsm->sync_index++; + + for (; fsm->sync_index < EC_MAX_SYNC_MANAGERS; fsm->sync_index++) { + if (!fsm->slave->config) { + // slave configuration removed in the meantime + fsm->state = ec_fsm_pdo_state_error; + return; + } + + if (ec_pdo_list_copy(&fsm->pdos, + &fsm->slave->config->sync_configs[fsm->sync_index].pdos)) + { + fsm->state = ec_fsm_pdo_state_error; + return; + } + + if (!(fsm->sync = ec_slave_get_sync(fsm->slave, fsm->sync_index))) { + if (!list_empty(&fsm->pdos.list)) + EC_SLAVE_WARN(fsm->slave, "PDOs configured for SM%u," + " but slave does not provide the" + " sync manager information!\n", + fsm->sync_index); + continue; + } + + // get first configured PDO + if (!(fsm->pdo = + ec_fsm_pdo_conf_action_next_pdo(fsm, &fsm->pdos.list))) { + // no pdos configured + ec_fsm_pdo_conf_action_check_assignment(fsm, datagram); + return; + } + + ec_fsm_pdo_conf_action_pdo_mapping(fsm, datagram); + return; + } + + fsm->state = ec_fsm_pdo_state_end; +} + +/****************************************************************************/ + +/** Check if the mapping has to be read, otherwise start to configure it. + */ +void ec_fsm_pdo_conf_action_pdo_mapping( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + const ec_pdo_t *assigned_pdo; + + fsm->slave_pdo.index = fsm->pdo->index; + + if ((assigned_pdo = ec_slave_find_pdo(fsm->slave, fsm->pdo->index))) { + ec_pdo_copy_entries(&fsm->slave_pdo, assigned_pdo); + } else { // configured PDO is not assigned and thus unknown + ec_pdo_clear_entries(&fsm->slave_pdo); + } + + if (list_empty(&fsm->slave_pdo.entries)) { + EC_SLAVE_DBG(fsm->slave, 1, "Reading mapping of PDO 0x%04X.\n", + fsm->pdo->index); + + // pdo mapping is unknown; start loading it + ec_fsm_pdo_entry_start_reading(&fsm->fsm_pdo_entry, fsm->slave, + &fsm->slave_pdo); + fsm->state = ec_fsm_pdo_conf_state_read_mapping; + fsm->state(fsm, datagram); // execute immediately + return; + } + + // pdo mapping is known, check if it most be re-configured + ec_fsm_pdo_conf_action_check_mapping(fsm, datagram); +} + +/****************************************************************************/ + +/** Execute the PDO entry state machine to read the current PDO's mapping. + */ +void ec_fsm_pdo_conf_state_read_mapping( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_pdo_entry_exec(&fsm->fsm_pdo_entry, datagram)) { + return; + } + + if (!ec_fsm_pdo_entry_success(&fsm->fsm_pdo_entry)) + EC_SLAVE_WARN(fsm->slave, + "Failed to read PDO entries for PDO 0x%04X.\n", + fsm->pdo->index); + + // check if the mapping must be re-configured + ec_fsm_pdo_conf_action_check_mapping(fsm, datagram); +} + +/****************************************************************************/ + +/** Check if the mapping has to be re-configured. + * + * \todo Display mapping differences. + */ +void ec_fsm_pdo_conf_action_check_mapping( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + // check, if slave supports PDO configuration + if ((fsm->slave->sii.mailbox_protocols & EC_MBOX_COE) + && fsm->slave->sii.has_general + && fsm->slave->sii.coe_details.enable_pdo_configuration) { + + // always write PDO mapping + ec_fsm_pdo_entry_start_configuration(&fsm->fsm_pdo_entry, fsm->slave, + fsm->pdo, &fsm->slave_pdo); + fsm->state = ec_fsm_pdo_conf_state_mapping; + fsm->state(fsm, datagram); // execure immediately + return; + } + else if (!ec_pdo_equal_entries(fsm->pdo, &fsm->slave_pdo)) { + EC_SLAVE_WARN(fsm->slave, "Slave does not support" + " changing the PDO mapping!\n"); + EC_SLAVE_WARN(fsm->slave, ""); + printk(KERN_CONT "Currently mapped PDO entries: "); + ec_pdo_print_entries(&fsm->slave_pdo); + printk(KERN_CONT ". Entries to map: "); + ec_pdo_print_entries(fsm->pdo); + printk(KERN_CONT "\n"); + } + + ec_fsm_pdo_conf_action_next_pdo_mapping(fsm, datagram); +} + +/****************************************************************************/ + +/** Let the PDO entry state machine configure the current PDO's mapping. + */ +void ec_fsm_pdo_conf_state_mapping( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_pdo_entry_exec(&fsm->fsm_pdo_entry, datagram)) { + return; + } + + if (!ec_fsm_pdo_entry_success(&fsm->fsm_pdo_entry)) + EC_SLAVE_WARN(fsm->slave, + "Failed to configure mapping of PDO 0x%04X.\n", + fsm->pdo->index); + + ec_fsm_pdo_conf_action_next_pdo_mapping(fsm, datagram); +} + +/****************************************************************************/ + +/** Check mapping of next PDO, otherwise configure assignment. + */ +void ec_fsm_pdo_conf_action_next_pdo_mapping( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + // get next configured PDO + if (!(fsm->pdo = ec_fsm_pdo_conf_action_next_pdo(fsm, &fsm->pdo->list))) { + // no more configured pdos + ec_fsm_pdo_conf_action_check_assignment(fsm, datagram); + return; + } + + ec_fsm_pdo_conf_action_pdo_mapping(fsm, datagram); +} + +/****************************************************************************/ + +/** Check if the PDO assignment of the current SM has to be re-configured. + */ +void ec_fsm_pdo_conf_action_check_assignment( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if ((fsm->slave->sii.mailbox_protocols & EC_MBOX_COE) + && fsm->slave->sii.has_general + && fsm->slave->sii.coe_details.enable_pdo_assign) { + + // always write PDO assignment + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(fsm->slave, 1, "Setting PDO assignment of SM%u:\n", + fsm->sync_index); + EC_SLAVE_DBG(fsm->slave, 1, ""); ec_fsm_pdo_print(fsm); + } + + if (ec_sdo_request_alloc(&fsm->request, 2)) { + fsm->state = ec_fsm_pdo_state_error; + return; + } + + // set mapped PDO count to zero + EC_WRITE_U8(fsm->request.data, 0); // zero PDOs mapped + fsm->request.data_size = 1; + ecrt_sdo_request_index(&fsm->request, 0x1C10 + fsm->sync_index, 0); + ecrt_sdo_request_write(&fsm->request); + + EC_SLAVE_DBG(fsm->slave, 1, "Setting number of assigned" + " PDOs to zero.\n"); + + fsm->state = ec_fsm_pdo_conf_state_zero_pdo_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + else if (!ec_pdo_list_equal(&fsm->sync->pdos, &fsm->pdos)) { + EC_SLAVE_WARN(fsm->slave, "Slave does not support assigning PDOs!\n"); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_print(fsm); + } + + ec_fsm_pdo_conf_action_next_sync(fsm, datagram); +} + +/****************************************************************************/ + +/** Set the number of assigned PDOs to zero. + */ +void ec_fsm_pdo_conf_state_zero_pdo_count( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to clear PDO assignment of SM%u.\n", + fsm->sync_index); + EC_SLAVE_WARN(fsm->slave, ""); + ec_fsm_pdo_print(fsm); + ec_fsm_pdo_conf_action_next_sync(fsm, datagram); + return; + } + + // the sync manager's assigned PDOs have been cleared + ec_pdo_list_clear_pdos(&fsm->sync->pdos); + + // assign all PDOs belonging to the current sync manager + + // find first PDO + if (!(fsm->pdo = ec_fsm_pdo_conf_action_next_pdo(fsm, &fsm->pdos.list))) { + // check for mapping to be altered + ec_fsm_pdo_conf_action_next_sync(fsm, datagram); + return; + } + + // assign first PDO + fsm->pdo_pos = 1; + ec_fsm_pdo_conf_action_assign_pdo(fsm, datagram); +} + +/****************************************************************************/ + +/** Assign a PDO. + */ +void ec_fsm_pdo_conf_action_assign_pdo( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + EC_WRITE_U16(fsm->request.data, fsm->pdo->index); + fsm->request.data_size = 2; + ecrt_sdo_request_index(&fsm->request, + 0x1C10 + fsm->sync_index, fsm->pdo_pos); + ecrt_sdo_request_write(&fsm->request); + + EC_SLAVE_DBG(fsm->slave, 1, "Assigning PDO 0x%04X at position %u.\n", + fsm->pdo->index, fsm->pdo_pos); + + fsm->state = ec_fsm_pdo_conf_state_assign_pdo; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately +} + +/****************************************************************************/ + +/** Add a PDO to the sync managers PDO assignment. + */ +void ec_fsm_pdo_conf_state_assign_pdo( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to assign PDO 0x%04X at position %u" + " of SM%u.\n", + fsm->pdo->index, fsm->pdo_pos, fsm->sync_index); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_print(fsm); + fsm->state = ec_fsm_pdo_state_error; + return; + } + + // find next PDO + if (!(fsm->pdo = ec_fsm_pdo_conf_action_next_pdo(fsm, &fsm->pdo->list))) { + // no more PDOs to assign, set PDO count + EC_WRITE_U8(fsm->request.data, fsm->pdo_pos); + fsm->request.data_size = 1; + ecrt_sdo_request_index(&fsm->request, 0x1C10 + fsm->sync_index, 0); + ecrt_sdo_request_write(&fsm->request); + + EC_SLAVE_DBG(fsm->slave, 1, + "Setting number of assigned PDOs to %u.\n", + fsm->pdo_pos); + + fsm->state = ec_fsm_pdo_conf_state_set_pdo_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + + // add next PDO to assignment + fsm->pdo_pos++; + ec_fsm_pdo_conf_action_assign_pdo(fsm, datagram); +} + +/****************************************************************************/ + +/** Set the number of assigned PDOs. + */ +void ec_fsm_pdo_conf_state_set_pdo_count( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to set number of" + " assigned PDOs of SM%u.\n", fsm->sync_index); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_print(fsm); + fsm->state = ec_fsm_pdo_state_error; + return; + } + + // PDOs have been configured + ec_pdo_list_copy(&fsm->sync->pdos, &fsm->pdos); + + EC_SLAVE_DBG(fsm->slave, 1, "Successfully configured" + " PDO assignment of SM%u.\n", fsm->sync_index); + + // check if PDO mapping has to be altered + ec_fsm_pdo_conf_action_next_sync(fsm, datagram); +} + +/***************************************************************************** + * Common state functions + ****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_pdo_state_error( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_pdo_state_end( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_pdo.h b/ubuntu/igh-ecat/master/fsm_pdo.h new file mode 100644 index 00000000000000..41fc876a23ba75 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_pdo.h @@ -0,0 +1,76 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT PDO configuration state machine structures. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_PDO_H__ +#define __EC_FSM_PDO_H__ + +#include "globals.h" +#include "datagram.h" +#include "fsm_coe.h" +#include "fsm_pdo_entry.h" + +/****************************************************************************/ + +/** + * \see ec_fsm_pdo + */ +typedef struct ec_fsm_pdo ec_fsm_pdo_t; + +/** PDO configuration state machine. + */ +struct ec_fsm_pdo +{ + void (*state)(ec_fsm_pdo_t *, ec_datagram_t *); /**< State function. */ + ec_fsm_coe_t *fsm_coe; /**< CoE state machine to use. */ + ec_fsm_pdo_entry_t fsm_pdo_entry; /**< PDO entry state machine. */ + ec_pdo_list_t pdos; /**< PDO configuration. */ + ec_sdo_request_t request; /**< SDO request. */ + ec_pdo_t slave_pdo; /**< PDO actually appearing in a slave. */ + + ec_slave_t *slave; /**< Slave the FSM runs on. */ + uint8_t sync_index; /**< Current sync manager index. */ + ec_sync_t *sync; /**< Current sync manager. */ + ec_pdo_t *pdo; /**< Current PDO. */ + unsigned int pdo_pos; /**< Assignment position of current PDOs. */ + unsigned int pdo_count; /**< Number of assigned PDOs. */ +}; + +/****************************************************************************/ + +void ec_fsm_pdo_init(ec_fsm_pdo_t *, ec_fsm_coe_t *); +void ec_fsm_pdo_clear(ec_fsm_pdo_t *); + +void ec_fsm_pdo_start_reading(ec_fsm_pdo_t *, ec_slave_t *); +void ec_fsm_pdo_start_configuration(ec_fsm_pdo_t *, ec_slave_t *); + +int ec_fsm_pdo_exec(ec_fsm_pdo_t *, ec_datagram_t *); +int ec_fsm_pdo_success(const ec_fsm_pdo_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_pdo_entry.c b/ubuntu/igh-ecat/master/fsm_pdo_entry.c new file mode 100644 index 00000000000000..3c7be428925207 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_pdo_entry.c @@ -0,0 +1,541 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT PDO mapping state machine. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" + +#include "fsm_pdo_entry.h" + +/****************************************************************************/ + +// prototypes for private methods +void ec_fsm_pdo_entry_print(const ec_fsm_pdo_entry_t *); +int ec_fsm_pdo_entry_running(const ec_fsm_pdo_entry_t *); +ec_pdo_entry_t *ec_fsm_pdo_entry_conf_next_entry(const ec_fsm_pdo_entry_t *, + const struct list_head *); + +/****************************************************************************/ + +void ec_fsm_pdo_entry_read_state_start(ec_fsm_pdo_entry_t *, ec_datagram_t *); +void ec_fsm_pdo_entry_read_state_count(ec_fsm_pdo_entry_t *, ec_datagram_t *); +void ec_fsm_pdo_entry_read_state_entry(ec_fsm_pdo_entry_t *, ec_datagram_t *); + +void ec_fsm_pdo_entry_read_action_next(ec_fsm_pdo_entry_t *, ec_datagram_t *); + +void ec_fsm_pdo_entry_conf_state_start(ec_fsm_pdo_entry_t *, ec_datagram_t *); +void ec_fsm_pdo_entry_conf_state_zero_entry_count(ec_fsm_pdo_entry_t *, + ec_datagram_t *); +void ec_fsm_pdo_entry_conf_state_map_entry(ec_fsm_pdo_entry_t *, + ec_datagram_t *); +void ec_fsm_pdo_entry_conf_state_set_entry_count(ec_fsm_pdo_entry_t *, + ec_datagram_t *); + +void ec_fsm_pdo_entry_conf_action_map(ec_fsm_pdo_entry_t *, ec_datagram_t *); + +void ec_fsm_pdo_entry_state_end(ec_fsm_pdo_entry_t *, ec_datagram_t *); +void ec_fsm_pdo_entry_state_error(ec_fsm_pdo_entry_t *, ec_datagram_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_pdo_entry_init( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_fsm_coe_t *fsm_coe /**< CoE state machine to use. */ + ) +{ + fsm->fsm_coe = fsm_coe; + ec_sdo_request_init(&fsm->request); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_pdo_entry_clear( + ec_fsm_pdo_entry_t *fsm /**< PDO mapping state machine. */ + ) +{ + ec_sdo_request_clear(&fsm->request); +} + +/****************************************************************************/ + +/** Print the current and desired PDO mapping. + */ +void ec_fsm_pdo_entry_print( + const ec_fsm_pdo_entry_t *fsm /**< PDO mapping state machine. */ + ) +{ + printk(KERN_CONT "Currently mapped PDO entries: "); + ec_pdo_print_entries(fsm->cur_pdo); + printk(KERN_CONT ". Entries to map: "); + ec_pdo_print_entries(fsm->source_pdo); + printk(KERN_CONT "\n"); +} + +/****************************************************************************/ + +/** Start reading a PDO's entries. + */ +void ec_fsm_pdo_entry_start_reading( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_slave_t *slave, /**< Slave to configure. */ + ec_pdo_t *pdo /**< PDO to read entries for. */ + ) +{ + fsm->slave = slave; + fsm->target_pdo = pdo; + + ec_pdo_clear_entries(fsm->target_pdo); + + fsm->state = ec_fsm_pdo_entry_read_state_start; +} + +/****************************************************************************/ + +/** Start PDO mapping state machine. + */ +void ec_fsm_pdo_entry_start_configuration( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_slave_t *slave, /**< Slave to configure. */ + const ec_pdo_t *pdo, /**< PDO with the desired entries. */ + const ec_pdo_t *cur_pdo /**< Current PDO mapping. */ + ) +{ + fsm->slave = slave; + fsm->source_pdo = pdo; + fsm->cur_pdo = cur_pdo; + + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Changing mapping of PDO 0x%04X.\n", + pdo->index); + EC_SLAVE_DBG(slave, 1, ""); ec_fsm_pdo_entry_print(fsm); + } + + fsm->state = ec_fsm_pdo_entry_conf_state_start; +} + +/****************************************************************************/ + +/** Get running state. + * + * \return false, if state machine has terminated + */ +int ec_fsm_pdo_entry_running( + const ec_fsm_pdo_entry_t *fsm /**< PDO mapping state machine. */ + ) +{ + return fsm->state != ec_fsm_pdo_entry_state_end + && fsm->state != ec_fsm_pdo_entry_state_error; +} + +/****************************************************************************/ + +/** Executes the current state. + * + * \return false, if state machine has terminated + */ +int ec_fsm_pdo_entry_exec( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + fsm->state(fsm, datagram); + + return ec_fsm_pdo_entry_running(fsm); +} + +/****************************************************************************/ + +/** Get execution result. + * + * \return true, if the state machine terminated gracefully + */ +int ec_fsm_pdo_entry_success( + const ec_fsm_pdo_entry_t *fsm /**< PDO mapping state machine. */ + ) +{ + return fsm->state == ec_fsm_pdo_entry_state_end; +} + +/***************************************************************************** + * Reading state functions. + ****************************************************************************/ + +/** Request reading the number of mapped PDO entries. + */ +void ec_fsm_pdo_entry_read_state_start( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ecrt_sdo_request_index(&fsm->request, fsm->target_pdo->index, 0); + ecrt_sdo_request_read(&fsm->request); + + fsm->state = ec_fsm_pdo_entry_read_state_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately +} + +/****************************************************************************/ + +/** Read number of mapped PDO entries. + */ +void ec_fsm_pdo_entry_read_state_count( + ec_fsm_pdo_entry_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_ERR(fsm->slave, + "Failed to read number of mapped PDO entries.\n"); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + if (fsm->request.data_size != sizeof(uint8_t)) { + EC_SLAVE_ERR(fsm->slave, "Invalid data size %zu at uploading" + " SDO 0x%04X:%02X.\n", + fsm->request.data_size, fsm->request.index, + fsm->request.subindex); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + fsm->entry_count = EC_READ_U8(fsm->request.data); + + EC_SLAVE_DBG(fsm->slave, 1, "%u PDO entries mapped.\n", fsm->entry_count); + + // read first PDO entry + fsm->entry_pos = 1; + ec_fsm_pdo_entry_read_action_next(fsm, datagram); +} + +/****************************************************************************/ + +/** Read next PDO entry. + */ +void ec_fsm_pdo_entry_read_action_next( + ec_fsm_pdo_entry_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (fsm->entry_pos <= fsm->entry_count) { + ecrt_sdo_request_index(&fsm->request, fsm->target_pdo->index, + fsm->entry_pos); + ecrt_sdo_request_read(&fsm->request); + fsm->state = ec_fsm_pdo_entry_read_state_entry; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + + // finished reading entries. + fsm->state = ec_fsm_pdo_entry_state_end; +} + +/****************************************************************************/ + +/** Read PDO entry information. + */ +void ec_fsm_pdo_entry_read_state_entry( + ec_fsm_pdo_entry_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_ERR(fsm->slave, "Failed to read mapped PDO entry.\n"); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + if (fsm->request.data_size != sizeof(uint32_t)) { + EC_SLAVE_ERR(fsm->slave, "Invalid data size %zu at" + " uploading SDO 0x%04X:%02X.\n", + fsm->request.data_size, fsm->request.index, + fsm->request.subindex); + fsm->state = ec_fsm_pdo_entry_state_error; + } else { + uint32_t pdo_entry_info; + ec_pdo_entry_t *pdo_entry; + + pdo_entry_info = EC_READ_U32(fsm->request.data); + + if (!(pdo_entry = (ec_pdo_entry_t *) + kmalloc(sizeof(ec_pdo_entry_t), GFP_KERNEL))) { + EC_SLAVE_ERR(fsm->slave, "Failed to allocate PDO entry.\n"); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + ec_pdo_entry_init(pdo_entry); + pdo_entry->index = pdo_entry_info >> 16; + pdo_entry->subindex = (pdo_entry_info >> 8) & 0xFF; + pdo_entry->bit_length = pdo_entry_info & 0xFF; + + if (!pdo_entry->index && !pdo_entry->subindex) { + if (ec_pdo_entry_set_name(pdo_entry, "Gap")) { + ec_pdo_entry_clear(pdo_entry); + kfree(pdo_entry); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + } + + EC_SLAVE_DBG(fsm->slave, 1, + "PDO entry 0x%04X:%02X, %u bit, \"%s\".\n", + pdo_entry->index, pdo_entry->subindex, + pdo_entry->bit_length, + pdo_entry->name ? pdo_entry->name : "???"); + + list_add_tail(&pdo_entry->list, &fsm->target_pdo->entries); + + // next PDO entry + fsm->entry_pos++; + ec_fsm_pdo_entry_read_action_next(fsm, datagram); + } +} + +/***************************************************************************** + * Configuration state functions. + ****************************************************************************/ + +/** Start PDO mapping. + */ +void ec_fsm_pdo_entry_conf_state_start( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_sdo_request_alloc(&fsm->request, 4)) { + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + // set mapped PDO entry count to zero + EC_WRITE_U8(fsm->request.data, 0); + fsm->request.data_size = 1; + ecrt_sdo_request_index(&fsm->request, fsm->source_pdo->index, 0); + ecrt_sdo_request_write(&fsm->request); + + EC_SLAVE_DBG(fsm->slave, 1, "Setting entry count to zero.\n"); + + fsm->state = ec_fsm_pdo_entry_conf_state_zero_entry_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately +} + +/****************************************************************************/ + +/** Process next PDO entry. + * + * \return Next PDO entry, or NULL. + */ +ec_pdo_entry_t *ec_fsm_pdo_entry_conf_next_entry( + const ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + const struct list_head *list /**< current entry list item */ + ) +{ + list = list->next; + if (list == &fsm->source_pdo->entries) + return NULL; // no next entry + return list_entry(list, ec_pdo_entry_t, list); +} + +/****************************************************************************/ + +/** Set the number of mapped entries to zero. + */ +void ec_fsm_pdo_entry_conf_state_zero_entry_count( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to clear PDO mapping.\n"); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_entry_print(fsm); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + // find first entry + if (!(fsm->entry = ec_fsm_pdo_entry_conf_next_entry( + fsm, &fsm->source_pdo->entries))) { + + EC_SLAVE_DBG(fsm->slave, 1, "No entries to map.\n"); + + fsm->state = ec_fsm_pdo_entry_state_end; // finished + return; + } + + // add first entry + fsm->entry_pos = 1; + ec_fsm_pdo_entry_conf_action_map(fsm, datagram); +} + +/****************************************************************************/ + +/** Starts to add a PDO entry. + */ +void ec_fsm_pdo_entry_conf_action_map( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + uint32_t value; + + EC_SLAVE_DBG(fsm->slave, 1, "Mapping PDO entry 0x%04X:%02X (%u bit)" + " at position %u.\n", + fsm->entry->index, fsm->entry->subindex, + fsm->entry->bit_length, fsm->entry_pos); + + value = fsm->entry->index << 16 + | fsm->entry->subindex << 8 | fsm->entry->bit_length; + EC_WRITE_U32(fsm->request.data, value); + fsm->request.data_size = 4; + ecrt_sdo_request_index(&fsm->request, fsm->source_pdo->index, + fsm->entry_pos); + ecrt_sdo_request_write(&fsm->request); + + fsm->state = ec_fsm_pdo_entry_conf_state_map_entry; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately +} + +/****************************************************************************/ + +/** Add a PDO entry. + */ +void ec_fsm_pdo_entry_conf_state_map_entry( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to map PDO entry" + " 0x%04X:%02X (%u bit) to position %u.\n", + fsm->entry->index, fsm->entry->subindex, + fsm->entry->bit_length, fsm->entry_pos); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_entry_print(fsm); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + // find next entry + if (!(fsm->entry = ec_fsm_pdo_entry_conf_next_entry( + fsm, &fsm->entry->list))) { + + // No more entries to add. Write entry count. + EC_WRITE_U8(fsm->request.data, fsm->entry_pos); + fsm->request.data_size = 1; + ecrt_sdo_request_index(&fsm->request, fsm->source_pdo->index, 0); + ecrt_sdo_request_write(&fsm->request); + + EC_SLAVE_DBG(fsm->slave, 1, "Setting number of PDO entries to %u.\n", + fsm->entry_pos); + + fsm->state = ec_fsm_pdo_entry_conf_state_set_entry_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + + // add next entry + fsm->entry_pos++; + ec_fsm_pdo_entry_conf_action_map(fsm, datagram); +} + +/****************************************************************************/ + +/** Set the number of entries. + */ +void ec_fsm_pdo_entry_conf_state_set_entry_count( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to set number of entries.\n"); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_entry_print(fsm); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + EC_SLAVE_DBG(fsm->slave, 1, "Successfully configured" + " mapping for PDO 0x%04X.\n", fsm->source_pdo->index); + + fsm->state = ec_fsm_pdo_entry_state_end; // finished +} + +/***************************************************************************** + * Common state functions + ****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_pdo_entry_state_error( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_pdo_entry_state_end( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_pdo_entry.h b/ubuntu/igh-ecat/master/fsm_pdo_entry.h new file mode 100644 index 00000000000000..d6638af65c7005 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_pdo_entry.h @@ -0,0 +1,75 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT PDO entry configuration state machine structures. + */ + +/****************************************************************************/ + +#ifndef __EC_FSM_PDO_ENTRY_H__ +#define __EC_FSM_PDO_ENTRY_H__ + +#include "globals.h" +#include "datagram.h" +#include "fsm_coe.h" + +/****************************************************************************/ + +/** + * \see ec_fsm_pdo_entry + */ +typedef struct ec_fsm_pdo_entry ec_fsm_pdo_entry_t; + +/** PDO configuration state machine. + */ +struct ec_fsm_pdo_entry +{ + void (*state)(ec_fsm_pdo_entry_t *, ec_datagram_t *); /**< state function + */ + ec_fsm_coe_t *fsm_coe; /**< CoE state machine to use */ + ec_sdo_request_t request; /**< SDO request. */ + + ec_slave_t *slave; /**< Slave the FSM runs on. */ + ec_pdo_t *target_pdo; /**< PDO to read the mapping for. */ + const ec_pdo_t *source_pdo; /**< PDO with desired mapping. */ + const ec_pdo_t *cur_pdo; /**< PDO with current mapping (display only). */ + const ec_pdo_entry_t *entry; /**< Current entry. */ + unsigned int entry_count; /**< Number of entries. */ + unsigned int entry_pos; /**< Position in PDO mapping. */ +}; + +/****************************************************************************/ + +void ec_fsm_pdo_entry_init(ec_fsm_pdo_entry_t *, ec_fsm_coe_t *); +void ec_fsm_pdo_entry_clear(ec_fsm_pdo_entry_t *); + +void ec_fsm_pdo_entry_start_reading(ec_fsm_pdo_entry_t *, ec_slave_t *, + ec_pdo_t *); +void ec_fsm_pdo_entry_start_configuration(ec_fsm_pdo_entry_t *, ec_slave_t *, + const ec_pdo_t *, const ec_pdo_t *); + +int ec_fsm_pdo_entry_exec(ec_fsm_pdo_entry_t *, ec_datagram_t *); +int ec_fsm_pdo_entry_success(const ec_fsm_pdo_entry_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_sii.c b/ubuntu/igh-ecat/master/fsm_sii.c new file mode 100644 index 00000000000000..7e5954915499cc --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_sii.c @@ -0,0 +1,482 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave information interface FSM. +*/ + +/****************************************************************************/ + +#include "globals.h" +#include "mailbox.h" +#include "master.h" +#include "fsm_sii.h" + +/** Read/write timeout [ms]. + * + * Used to calculate timeouts bsed on the jiffies counter. + * + * \attention Must be more than 10 to avoid problems on kernels that run with + * a timer interupt frequency of 100 Hz. + */ +#define SII_TIMEOUT 20 + +/** Time before evaluating answer at writing [ms]. + */ +#define SII_INHIBIT 5 + +//#define SII_DEBUG + +/****************************************************************************/ + +void ec_fsm_sii_state_start_reading(ec_fsm_sii_t *); +void ec_fsm_sii_state_read_check(ec_fsm_sii_t *); +void ec_fsm_sii_state_read_fetch(ec_fsm_sii_t *); +void ec_fsm_sii_state_start_writing(ec_fsm_sii_t *); +void ec_fsm_sii_state_write_check(ec_fsm_sii_t *); +void ec_fsm_sii_state_write_check2(ec_fsm_sii_t *); +void ec_fsm_sii_state_end(ec_fsm_sii_t *); +void ec_fsm_sii_state_error(ec_fsm_sii_t *); + +/****************************************************************************/ + +/** + Constructor. +*/ + +void ec_fsm_sii_init(ec_fsm_sii_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< datagram structure to use */ + ) +{ + fsm->state = NULL; + fsm->datagram = datagram; +} + +/****************************************************************************/ + +/** + Destructor. +*/ + +void ec_fsm_sii_clear(ec_fsm_sii_t *fsm /**< finite state machine */) +{ +} + +/****************************************************************************/ + +/** + Initializes the SII read state machine. +*/ + +void ec_fsm_sii_read(ec_fsm_sii_t *fsm, /**< finite state machine */ + ec_slave_t *slave, /**< slave to read from */ + uint16_t word_offset, /**< offset to read from */ + ec_fsm_sii_addressing_t mode /**< addressing scheme */ + ) +{ + fsm->state = ec_fsm_sii_state_start_reading; + fsm->slave = slave; + fsm->word_offset = word_offset; + fsm->mode = mode; +} + +/****************************************************************************/ + +/** + Initializes the SII write state machine. +*/ + +void ec_fsm_sii_write(ec_fsm_sii_t *fsm, /**< finite state machine */ + ec_slave_t *slave, /**< slave to read from */ + uint16_t word_offset, /**< offset to read from */ + const uint16_t *value, /**< pointer to 2 bytes of data */ + ec_fsm_sii_addressing_t mode /**< addressing scheme */ + ) +{ + fsm->state = ec_fsm_sii_state_start_writing; + fsm->slave = slave; + fsm->word_offset = word_offset; + fsm->mode = mode; + memcpy(fsm->value, value, 2); +} + +/****************************************************************************/ + +/** + Executes the SII state machine. + \return false, if the state machine has terminated +*/ + +int ec_fsm_sii_exec(ec_fsm_sii_t *fsm /**< finite state machine */) +{ + fsm->state(fsm); + + return fsm->state != ec_fsm_sii_state_end + && fsm->state != ec_fsm_sii_state_error; +} + +/****************************************************************************/ + +/** + Returns, if the master startup state machine terminated with success. + \return non-zero if successful. +*/ + +int ec_fsm_sii_success(ec_fsm_sii_t *fsm /**< Finite state machine */) +{ + return fsm->state == ec_fsm_sii_state_end; +} + +/***************************************************************************** + * state functions + ****************************************************************************/ + +/** + SII state: START READING. + Starts reading the slave information interface. +*/ + +void ec_fsm_sii_state_start_reading( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + // initiate read operation + switch (fsm->mode) { + case EC_FSM_SII_USE_INCREMENT_ADDRESS: + ec_datagram_apwr(datagram, fsm->slave->ring_position, 0x502, 4); + break; + case EC_FSM_SII_USE_CONFIGURED_ADDRESS: + ec_datagram_fpwr(datagram, fsm->slave->station_address, 0x502, 4); + break; + } + + EC_WRITE_U8 (datagram->data, 0x80); // two address octets + EC_WRITE_U8 (datagram->data + 1, 0x01); // request read operation + EC_WRITE_U16(datagram->data + 2, fsm->word_offset); + +#ifdef SII_DEBUG + EC_SLAVE_DBG(fsm->slave, 0, "reading SII data, word %u:\n", + fsm->word_offset); + ec_print_data(datagram->data, 4); +#endif + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_sii_state_read_check; +} + +/****************************************************************************/ + +/** + SII state: READ CHECK. + Checks, if the SII-read-datagram has been sent and issues a fetch datagram. +*/ + +void ec_fsm_sii_state_read_check( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed to receive SII read datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, "Reception of SII read datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + fsm->jiffies_start = datagram->jiffies_sent; + fsm->check_once_more = 1; + + // issue check/fetch datagram + switch (fsm->mode) { + case EC_FSM_SII_USE_INCREMENT_ADDRESS: + ec_datagram_aprd(datagram, fsm->slave->ring_position, 0x502, 10); + break; + case EC_FSM_SII_USE_CONFIGURED_ADDRESS: + ec_datagram_fprd(datagram, fsm->slave->station_address, 0x502, 10); + break; + } + + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_sii_state_read_fetch; +} + +/****************************************************************************/ + +/** + SII state: READ FETCH. + Fetches the result of an SII-read datagram. +*/ +void ec_fsm_sii_state_read_fetch( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, + "Failed to receive SII check/fetch datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, + "Reception of SII check/fetch datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + +#ifdef SII_DEBUG + EC_SLAVE_DBG(fsm->slave, 0, "checking SII read state:\n"); + ec_print_data(datagram->data, 10); +#endif + + if (EC_READ_U8(datagram->data + 1) & 0x20) { + EC_SLAVE_ERR(fsm->slave, "Error on last command while" + " reading from SII word 0x%04x.\n", fsm->word_offset); + fsm->state = ec_fsm_sii_state_error; + return; + } + + // check "busy bit" + if (EC_READ_U8(datagram->data + 1) & 0x81) { /* busy bit or + read operation busy */ + // still busy... timeout? + unsigned long diff_ms = + (datagram->jiffies_received - fsm->jiffies_start) * 1000 / HZ; + if (diff_ms >= SII_TIMEOUT) { + if (fsm->check_once_more) { + fsm->check_once_more = 0; + } else { + EC_SLAVE_ERR(fsm->slave, "SII: Read timeout.\n"); + fsm->state = ec_fsm_sii_state_error; + return; + } + } + + // issue check/fetch datagram again + fsm->retries = EC_FSM_RETRIES; + return; + } + + // SII value received. + memcpy(fsm->value, datagram->data + 6, 4); + fsm->state = ec_fsm_sii_state_end; +} + +/****************************************************************************/ + +/** + SII state: START WRITING. + Starts writing a word through the slave information interface. +*/ + +void ec_fsm_sii_state_start_writing( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + // initiate write operation + ec_datagram_fpwr(datagram, fsm->slave->station_address, 0x502, 8); + EC_WRITE_U8 (datagram->data, 0x81); /* two address octets + + enable write access */ + EC_WRITE_U8 (datagram->data + 1, 0x02); // request write operation + EC_WRITE_U16(datagram->data + 2, fsm->word_offset); + memset(datagram->data + 4, 0x00, 2); + memcpy(datagram->data + 6, fsm->value, 2); + +#ifdef SII_DEBUG + EC_SLAVE_DBG(fsm->slave, 0, "writing SII data:\n"); + ec_print_data(datagram->data, 8); +#endif + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_sii_state_write_check; +} + +/****************************************************************************/ + +/** + SII state: WRITE CHECK. +*/ + +void ec_fsm_sii_state_write_check( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed to receive SII write datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, "Reception of SII write datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + fsm->jiffies_start = datagram->jiffies_sent; + fsm->check_once_more = 1; + + // issue check datagram + ec_datagram_fprd(datagram, fsm->slave->station_address, 0x502, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_sii_state_write_check2; +} + +/****************************************************************************/ + +/** + SII state: WRITE CHECK 2. +*/ + +void ec_fsm_sii_state_write_check2( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + unsigned long diff_ms; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, + "Failed to receive SII write check datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, + "Reception of SII write check datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + +#ifdef SII_DEBUG + EC_SLAVE_DBG(fsm->slave, 0, "checking SII write state:\n"); + ec_print_data(datagram->data, 2); +#endif + + if (EC_READ_U8(datagram->data + 1) & 0x20) { + EC_SLAVE_ERR(fsm->slave, "SII: Error on last SII command!\n"); + fsm->state = ec_fsm_sii_state_error; + return; + } + + /* FIXME: some slaves never answer with the busy flag set... + * wait a few ms for the write operation to complete. */ + diff_ms = (datagram->jiffies_received - fsm->jiffies_start) * 1000 / HZ; + if (diff_ms < SII_INHIBIT) { +#ifdef SII_DEBUG + EC_SLAVE_DBG(fsm->slave, 0, "too early.\n"); +#endif + // issue check datagram again + fsm->retries = EC_FSM_RETRIES; + return; + } + + if (EC_READ_U8(datagram->data + 1) & 0x82) { /* busy bit or + write operation busy bit */ + // still busy... timeout? + if (diff_ms >= SII_TIMEOUT) { + if (fsm->check_once_more) { + fsm->check_once_more = 0; + } else { + EC_SLAVE_ERR(fsm->slave, "SII: Write timeout.\n"); + fsm->state = ec_fsm_sii_state_error; + return; + } + } + + // issue check datagram again + fsm->retries = EC_FSM_RETRIES; + return; + } + + if (EC_READ_U8(datagram->data + 1) & 0x40) { + EC_SLAVE_ERR(fsm->slave, "SII: Write operation failed!\n"); + fsm->state = ec_fsm_sii_state_error; + return; + } + + // success + fsm->state = ec_fsm_sii_state_end; +} + +/****************************************************************************/ + +/** + State: ERROR. +*/ + +void ec_fsm_sii_state_error( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ +} + +/****************************************************************************/ + +/** + State: END. +*/ + +void ec_fsm_sii_state_end( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_sii.h b/ubuntu/igh-ecat/master/fsm_sii.h new file mode 100644 index 00000000000000..405e2850249247 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_sii.h @@ -0,0 +1,82 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave information interface FSM structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_SII_H__ +#define __EC_FSM_SII_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" + +/****************************************************************************/ + +/** SII access addressing mode. + */ +typedef enum { + EC_FSM_SII_USE_INCREMENT_ADDRESS, /**< Use auto-increment addressing. */ + EC_FSM_SII_USE_CONFIGURED_ADDRESS /**< Use configured addresses. */ +} ec_fsm_sii_addressing_t; + +/****************************************************************************/ + +typedef struct ec_fsm_sii ec_fsm_sii_t; /**< \see ec_fsm_sii */ + +/** + Slave information interface FSM. +*/ + +struct ec_fsm_sii +{ + ec_slave_t *slave; /**< slave the FSM runs on */ + ec_datagram_t *datagram; /**< datagram used in the state machine */ + unsigned int retries; /**< retries upon datagram timeout */ + + void (*state)(ec_fsm_sii_t *); /**< SII state function */ + uint16_t word_offset; /**< input: word offset in SII */ + ec_fsm_sii_addressing_t mode; /**< reading via APRD or NPRD */ + uint8_t value[4]; /**< raw SII value (32bit) */ + unsigned long jiffies_start; /**< Start timestamp. */ + uint8_t check_once_more; /**< one more try after timeout */ +}; + +/****************************************************************************/ + +void ec_fsm_sii_init(ec_fsm_sii_t *, ec_datagram_t *); +void ec_fsm_sii_clear(ec_fsm_sii_t *); + +void ec_fsm_sii_read(ec_fsm_sii_t *, ec_slave_t *, + uint16_t, ec_fsm_sii_addressing_t); +void ec_fsm_sii_write(ec_fsm_sii_t *, ec_slave_t *, uint16_t, + const uint16_t *, ec_fsm_sii_addressing_t); + +int ec_fsm_sii_exec(ec_fsm_sii_t *); +int ec_fsm_sii_success(ec_fsm_sii_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_slave.c b/ubuntu/igh-ecat/master/fsm_slave.c new file mode 100644 index 00000000000000..6e1f9c36996594 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_slave.c @@ -0,0 +1,685 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT slave (SDO) state machine. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" + +#include "fsm_slave.h" + +/****************************************************************************/ + +void ec_fsm_slave_state_idle(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_ready(ec_fsm_slave_t *, ec_datagram_t *); +int ec_fsm_slave_action_process_sdo(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_sdo_request(ec_fsm_slave_t *, ec_datagram_t *); +int ec_fsm_slave_action_process_reg(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_reg_request(ec_fsm_slave_t *, ec_datagram_t *); +int ec_fsm_slave_action_process_foe(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_foe_request(ec_fsm_slave_t *, ec_datagram_t *); +int ec_fsm_slave_action_process_soe(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_soe_request(ec_fsm_slave_t *, ec_datagram_t *); +#ifdef EC_EOE +int ec_fsm_slave_action_process_eoe(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_eoe_request(ec_fsm_slave_t *, ec_datagram_t *); +#endif + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_slave_init( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + fsm->slave = slave; + INIT_LIST_HEAD(&fsm->list); // mark as unlisted + + fsm->state = ec_fsm_slave_state_idle; + fsm->datagram = NULL; + fsm->sdo_request = NULL; + fsm->reg_request = NULL; + fsm->foe_request = NULL; + fsm->soe_request = NULL; +#ifdef EC_EOE + fsm->eoe_request = NULL; +#endif + + // Init sub-state-machines + ec_fsm_coe_init(&fsm->fsm_coe); + ec_fsm_foe_init(&fsm->fsm_foe); + ec_fsm_soe_init(&fsm->fsm_soe); +#ifdef EC_EOE + ec_fsm_eoe_init(&fsm->fsm_eoe); +#endif +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_slave_clear( + ec_fsm_slave_t *fsm /**< Master state machine. */ + ) +{ + // signal requests that are currently in operation + + if (fsm->sdo_request) { + fsm->sdo_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->slave->master->request_queue); + } + + if (fsm->reg_request) { + fsm->reg_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->slave->master->request_queue); + } + + if (fsm->foe_request) { + fsm->foe_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->slave->master->request_queue); + } + + if (fsm->soe_request) { + fsm->soe_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->slave->master->request_queue); + } + +#ifdef EC_EOE + if (fsm->eoe_request) { + fsm->soe_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->slave->master->request_queue); + } +#endif + + // clear sub-state machines + ec_fsm_coe_clear(&fsm->fsm_coe); + ec_fsm_foe_clear(&fsm->fsm_foe); + ec_fsm_soe_clear(&fsm->fsm_soe); +#ifdef EC_EOE + ec_fsm_eoe_clear(&fsm->fsm_eoe); +#endif +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * \return 1 if \a datagram was used, else 0. + */ +int ec_fsm_slave_exec( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< New datagram to use. */ + ) +{ + int datagram_used; + + fsm->state(fsm, datagram); + + datagram_used = fsm->state != ec_fsm_slave_state_idle && + fsm->state != ec_fsm_slave_state_ready; + + if (datagram_used) { + fsm->datagram = datagram; + } else { + fsm->datagram = NULL; + } + + return datagram_used; +} + +/****************************************************************************/ + +/** Sets the current state of the state machine to READY + */ +void ec_fsm_slave_set_ready( + ec_fsm_slave_t *fsm /**< Slave state machine. */ + ) +{ + if (fsm->state == ec_fsm_slave_state_idle) { + EC_SLAVE_DBG(fsm->slave, 1, "Ready for requests.\n"); + fsm->state = ec_fsm_slave_state_ready; + } +} + +/****************************************************************************/ + +/** Returns, if the FSM is currently not busy and ready to execute. + * + * \return Non-zero if ready. + */ +int ec_fsm_slave_is_ready( + const ec_fsm_slave_t *fsm /**< Slave state machine. */ + ) +{ + return fsm->state == ec_fsm_slave_state_ready; +} + +/***************************************************************************** + * Slave state machine + ****************************************************************************/ + +/** Slave state: IDLE. + */ +void ec_fsm_slave_state_idle( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + // do nothing +} + +/****************************************************************************/ + +/** Slave state: READY. + */ +void ec_fsm_slave_state_ready( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + // Check for pending external SDO requests + if (ec_fsm_slave_action_process_sdo(fsm, datagram)) { + return; + } + + // Check for pending external register requests + if (ec_fsm_slave_action_process_reg(fsm, datagram)) { + return; + } + + // Check for pending FoE requests + if (ec_fsm_slave_action_process_foe(fsm, datagram)) { + return; + } + + // Check for pending SoE requests + if (ec_fsm_slave_action_process_soe(fsm, datagram)) { + return; + } + +#ifdef EC_EOE + // Check for pending EoE IP parameter requests + if (ec_fsm_slave_action_process_eoe(fsm, datagram)) { + return; + } +#endif +} + +/****************************************************************************/ + +/** Check for pending SDO requests and process one. + * + * \return non-zero, if an SDO request is processed. + */ +int ec_fsm_slave_action_process_sdo( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request; + + if (list_empty(&slave->sdo_requests)) { + return 0; + } + + // take the first request to be processed + request = list_entry(slave->sdo_requests.next, ec_sdo_request_t, list); + list_del_init(&request->list); // dequeue + + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + EC_SLAVE_WARN(slave, "Aborting SDO request," + " slave has error flag set.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + if (slave->current_state == EC_SLAVE_STATE_INIT) { + EC_SLAVE_WARN(slave, "Aborting SDO request, slave is in INIT.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + fsm->sdo_request = request; + request->state = EC_INT_REQUEST_BUSY; + + // Found pending SDO request. Execute it! + EC_SLAVE_DBG(slave, 1, "Processing SDO request...\n"); + + // Start SDO transfer + fsm->state = ec_fsm_slave_state_sdo_request; + ec_fsm_coe_transfer(&fsm->fsm_coe, slave, request); + ec_fsm_coe_exec(&fsm->fsm_coe, datagram); // execute immediately + return 1; +} + +/****************************************************************************/ + +/** Slave state: SDO_REQUEST. + */ +void ec_fsm_slave_state_sdo_request( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->sdo_request; + + if (ec_fsm_coe_exec(&fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(&fsm->fsm_coe)) { + EC_SLAVE_ERR(slave, "Failed to process SDO request.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->sdo_request = NULL; + fsm->state = ec_fsm_slave_state_ready; + return; + } + + EC_SLAVE_DBG(slave, 1, "Finished SDO request.\n"); + + // SDO request finished + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&slave->master->request_queue); + fsm->sdo_request = NULL; + fsm->state = ec_fsm_slave_state_ready; +} + +/****************************************************************************/ + +/** Check for pending register requests and process one. + * + * \return non-zero, if a register request is processed. + */ +int ec_fsm_slave_action_process_reg( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_reg_request_t *reg; + + fsm->reg_request = NULL; + + if (slave->config) { + // search the first internal register request to be processed + list_for_each_entry(reg, &slave->config->reg_requests, list) { + if (reg->state == EC_INT_REQUEST_QUEUED) { + fsm->reg_request = reg; + break; + } + } + } + + if (!fsm->reg_request && !list_empty(&slave->reg_requests)) { + // take the first external request to be processed + fsm->reg_request = + list_entry(slave->reg_requests.next, ec_reg_request_t, list); + list_del_init(&fsm->reg_request->list); // dequeue + } + + if (!fsm->reg_request) { // no register request to process + return 0; + } + + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + EC_SLAVE_WARN(slave, "Aborting register request," + " slave has error flag set.\n"); + fsm->reg_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->reg_request = NULL; + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + // Found pending register request. Execute it! + EC_SLAVE_DBG(slave, 1, "Processing register request...\n"); + + fsm->reg_request->state = EC_INT_REQUEST_BUSY; + + // Start register access + if (fsm->reg_request->dir == EC_DIR_INPUT) { + ec_datagram_fprd(datagram, slave->station_address, + fsm->reg_request->address, fsm->reg_request->transfer_size); + ec_datagram_zero(datagram); + } else { + ec_datagram_fpwr(datagram, slave->station_address, + fsm->reg_request->address, fsm->reg_request->transfer_size); + memcpy(datagram->data, fsm->reg_request->data, + fsm->reg_request->transfer_size); + } + datagram->device_index = slave->device_index; + fsm->state = ec_fsm_slave_state_reg_request; + return 1; +} + +/****************************************************************************/ + +/** Slave state: Register request. + */ +void ec_fsm_slave_state_reg_request( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_reg_request_t *reg = fsm->reg_request; + + if (!reg) { + // configuration was cleared in the meantime + fsm->state = ec_fsm_slave_state_ready; + fsm->reg_request = NULL; + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_ERR(slave, "Failed to receive register" + " request datagram: "); + ec_datagram_print_state(fsm->datagram); + reg->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->reg_request = NULL; + fsm->state = ec_fsm_slave_state_ready; + return; + } + + if (fsm->datagram->working_counter == 1) { + if (reg->dir == EC_DIR_INPUT) { // read request + memcpy(reg->data, fsm->datagram->data, reg->transfer_size); + } + + reg->state = EC_INT_REQUEST_SUCCESS; + EC_SLAVE_DBG(slave, 1, "Register request successful.\n"); + } else { + reg->state = EC_INT_REQUEST_FAILURE; + ec_datagram_print_state(fsm->datagram); + EC_SLAVE_ERR(slave, "Register request failed" + " (working counter is %u).\n", + fsm->datagram->working_counter); + } + + wake_up_all(&slave->master->request_queue); + fsm->reg_request = NULL; + fsm->state = ec_fsm_slave_state_ready; +} + +/****************************************************************************/ + +/** Check for pending FoE requests and process one. + * + * \return non-zero, if an FoE request is processed. + */ +int ec_fsm_slave_action_process_foe( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_foe_request_t *request; + + if (list_empty(&slave->foe_requests)) { + return 0; + } + + // take the first request to be processed + request = list_entry(slave->foe_requests.next, ec_foe_request_t, list); + list_del_init(&request->list); // dequeue + + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + EC_SLAVE_WARN(slave, "Aborting FoE request," + " slave has error flag set.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + request->state = EC_INT_REQUEST_BUSY; + fsm->foe_request = request; + + EC_SLAVE_DBG(slave, 1, "Processing FoE request.\n"); + + fsm->state = ec_fsm_slave_state_foe_request; + ec_fsm_foe_transfer(&fsm->fsm_foe, slave, request); + ec_fsm_foe_exec(&fsm->fsm_foe, datagram); + return 1; +} + +/****************************************************************************/ + +/** Slave state: FOE REQUEST. + */ +void ec_fsm_slave_state_foe_request( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_foe_request_t *request = fsm->foe_request; + + if (ec_fsm_foe_exec(&fsm->fsm_foe, datagram)) { + return; + } + + if (!ec_fsm_foe_success(&fsm->fsm_foe)) { + EC_SLAVE_ERR(slave, "Failed to handle FoE request.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->foe_request = NULL; + fsm->state = ec_fsm_slave_state_ready; + return; + } + + // finished transferring FoE + EC_SLAVE_DBG(slave, 1, "Successfully transferred %zu bytes of FoE" + " data.\n", request->data_size); + + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&slave->master->request_queue); + fsm->foe_request = NULL; + fsm->state = ec_fsm_slave_state_ready; +} + +/****************************************************************************/ + +/** Check for pending SoE requests and process one. + * + * \return non-zero, if a request is processed. + */ +int ec_fsm_slave_action_process_soe( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *req; + + if (list_empty(&slave->soe_requests)) { + return 0; + } + + // take the first request to be processed + req = list_entry(slave->soe_requests.next, ec_soe_request_t, list); + list_del_init(&req->list); // dequeue + + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + EC_SLAVE_WARN(slave, "Aborting SoE request," + " slave has error flag set.\n"); + req->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + if (slave->current_state == EC_SLAVE_STATE_INIT) { + EC_SLAVE_WARN(slave, "Aborting SoE request, slave is in INIT.\n"); + req->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + fsm->soe_request = req; + req->state = EC_INT_REQUEST_BUSY; + + // Found pending request. Execute it! + EC_SLAVE_DBG(slave, 1, "Processing SoE request...\n"); + + // Start SoE transfer + fsm->state = ec_fsm_slave_state_soe_request; + ec_fsm_soe_transfer(&fsm->fsm_soe, slave, req); + ec_fsm_soe_exec(&fsm->fsm_soe, datagram); // execute immediately + return 1; +} + +/****************************************************************************/ + +/** Slave state: SOE_REQUEST. + */ +void ec_fsm_slave_state_soe_request( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *request = fsm->soe_request; + + if (ec_fsm_soe_exec(&fsm->fsm_soe, datagram)) { + return; + } + + if (!ec_fsm_soe_success(&fsm->fsm_soe)) { + EC_SLAVE_ERR(slave, "Failed to process SoE request.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->soe_request = NULL; + fsm->state = ec_fsm_slave_state_ready; + return; + } + + EC_SLAVE_DBG(slave, 1, "Finished SoE request.\n"); + + // SoE request finished + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&slave->master->request_queue); + fsm->soe_request = NULL; + fsm->state = ec_fsm_slave_state_ready; +} + +/****************************************************************************/ + +#ifdef EC_EOE +/** Check for pending EoE IP parameter requests and process one. + * + * \return non-zero, if a request is processed. + */ +int ec_fsm_slave_action_process_eoe( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_eoe_request_t *request; + + if (list_empty(&slave->eoe_requests)) { + return 0; + } + + // take the first request to be processed + request = list_entry(slave->eoe_requests.next, ec_eoe_request_t, list); + list_del_init(&request->list); // dequeue + + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + EC_SLAVE_WARN(slave, "Aborting EoE request," + " slave has error flag set.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + if (slave->current_state == EC_SLAVE_STATE_INIT) { + EC_SLAVE_WARN(slave, "Aborting EoE request, slave is in INIT.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + fsm->eoe_request = request; + request->state = EC_INT_REQUEST_BUSY; + + // Found pending request. Execute it! + EC_SLAVE_DBG(slave, 1, "Processing EoE request...\n"); + + // Start EoE command + fsm->state = ec_fsm_slave_state_eoe_request; + ec_fsm_eoe_set_ip_param(&fsm->fsm_eoe, slave, request); + ec_fsm_eoe_exec(&fsm->fsm_eoe, datagram); // execute immediately + return 1; +} + +/****************************************************************************/ + +/** Slave state: EOE_REQUEST. + */ +void ec_fsm_slave_state_eoe_request( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_eoe_request_t *req = fsm->eoe_request; + + if (ec_fsm_eoe_exec(&fsm->fsm_eoe, datagram)) { + return; + } + + if (ec_fsm_eoe_success(&fsm->fsm_eoe)) { + req->state = EC_INT_REQUEST_SUCCESS; + EC_SLAVE_DBG(slave, 1, "Finished EoE request.\n"); + } + else { + req->state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Failed to process EoE request.\n"); + } + + wake_up_all(&slave->master->request_queue); + fsm->eoe_request = NULL; + fsm->state = ec_fsm_slave_state_ready; +} + +/****************************************************************************/ +#endif diff --git a/ubuntu/igh-ecat/master/fsm_slave.h b/ubuntu/igh-ecat/master/fsm_slave.h new file mode 100644 index 00000000000000..079bd5f8b473a6 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_slave.h @@ -0,0 +1,87 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave request state machine. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_SLAVE_H__ +#define __EC_FSM_SLAVE_H__ + +#include "globals.h" +#include "datagram.h" +#include "sdo_request.h" +#include "reg_request.h" +#ifdef EC_EOE +#include "eoe_request.h" +#endif +#include "fsm_coe.h" +#include "fsm_foe.h" +#include "fsm_soe.h" +#ifdef EC_EOE +#include "fsm_eoe.h" +#endif + +/****************************************************************************/ + +typedef struct ec_fsm_slave ec_fsm_slave_t; /**< \see ec_fsm_slave */ + +/** Finite state machine of an EtherCAT slave. + */ +struct ec_fsm_slave { + ec_slave_t *slave; /**< slave the FSM runs on */ + struct list_head list; /**< Used for execution list. */ + + void (*state)(ec_fsm_slave_t *, ec_datagram_t *); /**< State function. */ + ec_datagram_t *datagram; /**< Previous state datagram. */ + ec_sdo_request_t *sdo_request; /**< SDO request to process. */ + ec_reg_request_t *reg_request; /**< Register request to process. */ + ec_foe_request_t *foe_request; /**< FoE request to process. */ + off_t foe_index; /**< Index to FoE write request data. */ + ec_soe_request_t *soe_request; /**< SoE request to process. */ +#ifdef EC_EOE + ec_eoe_request_t *eoe_request; /**< SoE request to process. */ +#endif + + ec_fsm_coe_t fsm_coe; /**< CoE state machine. */ + ec_fsm_foe_t fsm_foe; /**< FoE state machine. */ + ec_fsm_soe_t fsm_soe; /**< SoE state machine. */ +#ifdef EC_EOE + ec_fsm_eoe_t fsm_eoe; /**< EoE state machine. */ +#endif +}; + +/****************************************************************************/ + +void ec_fsm_slave_init(ec_fsm_slave_t *, ec_slave_t *); +void ec_fsm_slave_clear(ec_fsm_slave_t *); + +int ec_fsm_slave_exec(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_set_ready(ec_fsm_slave_t *); +int ec_fsm_slave_is_ready(const ec_fsm_slave_t *); + +/****************************************************************************/ + + +#endif // __EC_FSM_SLAVE_H__ diff --git a/ubuntu/igh-ecat/master/fsm_slave_config.c b/ubuntu/igh-ecat/master/fsm_slave_config.c new file mode 100644 index 00000000000000..47e750f46b243a --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_slave_config.c @@ -0,0 +1,1864 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** \file + * + * EtherCAT slave configuration state machine. + */ + +/****************************************************************************/ + +#include + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" +#include "fsm_slave_config.h" + +/****************************************************************************/ + +/** Maximum clock difference (in ns) before going to SAFEOP. + * + * Wait for DC time difference to drop under this absolute value before + * requesting SAFEOP. + */ +#define EC_DC_MAX_SYNC_DIFF_NS 10000 + +/** Maximum time (in ms) to wait for clock discipline. + */ +#define EC_DC_SYNC_WAIT_MS 5000 + +/** Time offset (in ns), that is added to cyclic start time. + */ +#define EC_DC_START_OFFSET 100000000ULL + +/****************************************************************************/ + +// prototypes for private methods +int ec_fsm_slave_config_running(const ec_fsm_slave_config_t *); + +/****************************************************************************/ + +void ec_fsm_slave_config_state_start(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_init(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_clear_fmmus(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_clear_sync(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_dc_clear_assign(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_mbox_sync(ec_fsm_slave_config_t *); +#ifdef EC_SII_ASSIGN +void ec_fsm_slave_config_state_assign_pdi(ec_fsm_slave_config_t *); +#endif +void ec_fsm_slave_config_state_boot_preop(ec_fsm_slave_config_t *); +#ifdef EC_SII_ASSIGN +void ec_fsm_slave_config_state_assign_ethercat(ec_fsm_slave_config_t *); +#endif +void ec_fsm_slave_config_state_sdo_conf(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_soe_conf_preop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_eoe_ip_param(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_watchdog_divider(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_watchdog(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_pdo_sync(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_pdo_conf(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_fmmu(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_dc_cycle(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_dc_sync_check(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_dc_start(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_dc_assign(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_wait_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_soe_conf_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_op(ec_fsm_slave_config_t *); + +void ec_fsm_slave_config_enter_init(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_clear_sync(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_dc_clear_assign(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_mbox_sync(ec_fsm_slave_config_t *); +#ifdef EC_SII_ASSIGN +void ec_fsm_slave_config_enter_assign_pdi(ec_fsm_slave_config_t *); +#endif +void ec_fsm_slave_config_enter_boot_preop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_sdo_conf(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_soe_conf_preop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_eoe_ip_param(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_pdo_conf(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_watchdog_divider(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_watchdog(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_pdo_sync(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_fmmu(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_dc_cycle(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_wait_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_soe_conf_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_op(ec_fsm_slave_config_t *); + +void ec_fsm_slave_config_state_end(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_error(ec_fsm_slave_config_t *); + +void ec_fsm_slave_config_reconfigure(ec_fsm_slave_config_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_slave_config_init( + ec_fsm_slave_config_t *fsm, /**< slave state machine */ + ec_datagram_t *datagram, /**< datagram structure to use */ + ec_fsm_change_t *fsm_change, /**< State change state machine to use. */ + ec_fsm_coe_t *fsm_coe, /**< CoE state machine to use. */ + ec_fsm_soe_t *fsm_soe, /**< SoE state machine to use. */ + ec_fsm_pdo_t *fsm_pdo, /**< PDO configuration state machine to use. */ + ec_fsm_eoe_t *fsm_eoe /**< EoE state machine to use. */ + ) +{ + ec_sdo_request_init(&fsm->request_copy); + ec_soe_request_init(&fsm->soe_request_copy); + + fsm->datagram = datagram; + fsm->fsm_change = fsm_change; + fsm->fsm_coe = fsm_coe; + fsm->fsm_soe = fsm_soe; + fsm->fsm_pdo = fsm_pdo; + fsm->fsm_eoe = fsm_eoe; + + fsm->wait_ms = 0; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_slave_config_clear( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_sdo_request_clear(&fsm->request_copy); + ec_soe_request_clear(&fsm->soe_request_copy); +} + +/****************************************************************************/ + +/** Start slave configuration state machine. + */ +void ec_fsm_slave_config_start( + ec_fsm_slave_config_t *fsm, /**< slave state machine */ + ec_slave_t *slave /**< slave to configure */ + ) +{ + fsm->slave = slave; + fsm->state = ec_fsm_slave_config_state_start; +} + +/****************************************************************************/ + +/** + * \return false, if state machine has terminated + */ +int ec_fsm_slave_config_running( + const ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + return fsm->state != ec_fsm_slave_config_state_end + && fsm->state != ec_fsm_slave_config_state_error; +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * If the state machine's datagram is not sent or received yet, the execution + * of the state machine is delayed to the next cycle. + * + * \return false, if state machine has terminated + */ +int ec_fsm_slave_config_exec( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + if (fsm->datagram->state == EC_DATAGRAM_SENT + || fsm->datagram->state == EC_DATAGRAM_QUEUED) { + // datagram was not sent or received yet. + return ec_fsm_slave_config_running(fsm); + } + + fsm->state(fsm); + return ec_fsm_slave_config_running(fsm); +} + +/****************************************************************************/ + +/** + * \return true, if the state machine terminated gracefully + */ +int ec_fsm_slave_config_success( + const ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + return fsm->state == ec_fsm_slave_config_state_end; +} + +/***************************************************************************** + * Slave configuration state machine + ****************************************************************************/ + +/** Slave configuration state: START. + */ +void ec_fsm_slave_config_state_start( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + EC_SLAVE_DBG(fsm->slave, 1, "Configuring...\n"); + ec_fsm_slave_config_enter_init(fsm); +} + +/****************************************************************************/ + +/** Start state change to INIT. + */ +void ec_fsm_slave_config_enter_init( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_fsm_change_start(fsm->fsm_change, fsm->slave, EC_SLAVE_STATE_INIT); + ec_fsm_change_exec(fsm->fsm_change); + fsm->state = ec_fsm_slave_config_state_init; +} + +/****************************************************************************/ + +/** Slave configuration state: INIT. + */ +void ec_fsm_slave_config_state_init( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + + if (ec_fsm_change_exec(fsm->fsm_change)) return; + + if (!ec_fsm_change_success(fsm->fsm_change)) { + if (!fsm->fsm_change->spontaneous_change) + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + EC_SLAVE_DBG(slave, 1, "Now in INIT.\n"); + + if (!slave->base_fmmu_count) { // skip FMMU configuration + ec_fsm_slave_config_enter_clear_sync(fsm); + return; + } + + EC_SLAVE_DBG(slave, 1, "Clearing FMMU configurations...\n"); + + // clear FMMU configurations + ec_datagram_fpwr(datagram, slave->station_address, + 0x0600, EC_FMMU_PAGE_SIZE * slave->base_fmmu_count); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_clear_fmmus; +} + +/****************************************************************************/ + +/** Slave configuration state: CLEAR FMMU. + */ +void ec_fsm_slave_config_state_clear_fmmus( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed receive FMMU clearing datagram.\n"); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed to clear FMMUs: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_clear_sync(fsm); +} + +/****************************************************************************/ + +/** Clear the sync manager configurations. + */ +void ec_fsm_slave_config_enter_clear_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + size_t sync_size; + + if (!slave->base_sync_count) { + // no sync managers + ec_fsm_slave_config_enter_dc_clear_assign(fsm); + return; + } + + EC_SLAVE_DBG(slave, 1, "Clearing sync manager configurations...\n"); + + sync_size = EC_SYNC_PAGE_SIZE * slave->base_sync_count; + + // clear sync manager configurations + ec_datagram_fpwr(datagram, slave->station_address, 0x0800, sync_size); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_clear_sync; +} + +/****************************************************************************/ + +/** Slave configuration state: CLEAR SYNC. + */ +void ec_fsm_slave_config_state_clear_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed receive sync manager" + " clearing datagram.\n"); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(fsm->slave, + "Failed to clear sync manager configurations: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_dc_clear_assign(fsm); +} + +/****************************************************************************/ + +/** Clear the DC assignment. + */ +void ec_fsm_slave_config_enter_dc_clear_assign( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + + if (!slave->base_dc_supported || !slave->has_dc_system_time) { + ec_fsm_slave_config_enter_mbox_sync(fsm); + return; + } + + EC_SLAVE_DBG(slave, 1, "Clearing DC assignment...\n"); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0980, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_dc_clear_assign; +} + +/****************************************************************************/ + +/** Slave configuration state: CLEAR DC ASSIGN. + */ +void ec_fsm_slave_config_state_dc_clear_assign( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed receive DC assignment" + " clearing datagram.\n"); + return; + } + + if (datagram->working_counter != 1) { + // clearing the DC assignment does not succeed on simple slaves + EC_SLAVE_DBG(fsm->slave, 1, "Failed to clear DC assignment: "); + ec_datagram_print_wc_error(datagram); + } + + ec_fsm_slave_config_enter_mbox_sync(fsm); +} + +/****************************************************************************/ + +/** Check for mailbox sync managers to be configured. + */ +void ec_fsm_slave_config_enter_mbox_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + unsigned int i; + + // slave is now in INIT + if (slave->current_state == slave->requested_state) { + fsm->state = ec_fsm_slave_config_state_end; // successful + EC_SLAVE_DBG(slave, 1, "Finished configuration.\n"); + return; + } + + if (!slave->sii.mailbox_protocols) { + // no mailbox protocols supported + EC_SLAVE_DBG(slave, 1, "Slave does not support" + " mailbox communication.\n"); +#ifdef EC_SII_ASSIGN + ec_fsm_slave_config_enter_assign_pdi(fsm); +#else + ec_fsm_slave_config_enter_boot_preop(fsm); +#endif + return; + } + + EC_SLAVE_DBG(slave, 1, "Configuring mailbox sync managers...\n"); + + if (slave->requested_state == EC_SLAVE_STATE_BOOT) { + ec_sync_t sync; + + ec_datagram_fpwr(datagram, slave->station_address, 0x0800, + EC_SYNC_PAGE_SIZE * 2); + ec_datagram_zero(datagram); + + ec_sync_init(&sync, slave); + sync.physical_start_address = slave->sii.boot_rx_mailbox_offset; + sync.control_register = 0x26; + sync.enable = 1; + ec_sync_page(&sync, 0, slave->sii.boot_rx_mailbox_size, + EC_DIR_INVALID, // use default direction + 0, // no PDO xfer + datagram->data); + slave->configured_rx_mailbox_offset = + slave->sii.boot_rx_mailbox_offset; + slave->configured_rx_mailbox_size = + slave->sii.boot_rx_mailbox_size; + + ec_sync_init(&sync, slave); + sync.physical_start_address = slave->sii.boot_tx_mailbox_offset; + sync.control_register = 0x22; + sync.enable = 1; + ec_sync_page(&sync, 1, slave->sii.boot_tx_mailbox_size, + EC_DIR_INVALID, // use default direction + 0, // no PDO xfer + datagram->data + EC_SYNC_PAGE_SIZE); + slave->configured_tx_mailbox_offset = + slave->sii.boot_tx_mailbox_offset; + slave->configured_tx_mailbox_size = + slave->sii.boot_tx_mailbox_size; + + } else if (slave->sii.sync_count >= 2) { // mailbox configuration provided + ec_datagram_fpwr(datagram, slave->station_address, 0x0800, + EC_SYNC_PAGE_SIZE * slave->sii.sync_count); + ec_datagram_zero(datagram); + + for (i = 0; i < 2; i++) { + ec_sync_page(&slave->sii.syncs[i], i, + slave->sii.syncs[i].default_length, + NULL, // use default sync manager configuration + 0, // no PDO xfer + datagram->data + EC_SYNC_PAGE_SIZE * i); + } + + slave->configured_rx_mailbox_offset = + slave->sii.syncs[0].physical_start_address; + slave->configured_rx_mailbox_size = + slave->sii.syncs[0].default_length; + slave->configured_tx_mailbox_offset = + slave->sii.syncs[1].physical_start_address; + slave->configured_tx_mailbox_size = + slave->sii.syncs[1].default_length; + } else { // no mailbox sync manager configurations provided + ec_sync_t sync; + + EC_SLAVE_DBG(slave, 1, "Slave does not provide" + " mailbox sync manager configurations.\n"); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0800, + EC_SYNC_PAGE_SIZE * 2); + ec_datagram_zero(datagram); + + ec_sync_init(&sync, slave); + sync.physical_start_address = slave->sii.std_rx_mailbox_offset; + sync.control_register = 0x26; + sync.enable = 1; + ec_sync_page(&sync, 0, slave->sii.std_rx_mailbox_size, + NULL, // use default sync manager configuration + 0, // no PDO xfer + datagram->data); + slave->configured_rx_mailbox_offset = + slave->sii.std_rx_mailbox_offset; + slave->configured_rx_mailbox_size = + slave->sii.std_rx_mailbox_size; + + ec_sync_init(&sync, slave); + sync.physical_start_address = slave->sii.std_tx_mailbox_offset; + sync.control_register = 0x22; + sync.enable = 1; + ec_sync_page(&sync, 1, slave->sii.std_tx_mailbox_size, + NULL, // use default sync manager configuration + 0, // no PDO xfer + datagram->data + EC_SYNC_PAGE_SIZE); + slave->configured_tx_mailbox_offset = + slave->sii.std_tx_mailbox_offset; + slave->configured_tx_mailbox_size = + slave->sii.std_tx_mailbox_size; + } + + fsm->take_time = 1; + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_mbox_sync; +} + +/****************************************************************************/ + +/** Slave configuration state: SYNC. + * + * \todo Timeout for response. + */ +void ec_fsm_slave_config_state_mbox_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive sync manager" + " configuration datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (fsm->take_time) { + fsm->take_time = 0; + fsm->jiffies_start = datagram->jiffies_sent; + } + + /* Because the sync manager configurations are cleared during the last + * cycle, some slaves do not immediately respond to the mailbox sync + * manager configuration datagram. Therefore, resend the datagram for + * a certain time, if the slave does not respond. + */ + if (datagram->working_counter == 0) { + unsigned long diff = datagram->jiffies_received - fsm->jiffies_start; + + if (diff >= HZ) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Timeout while configuring" + " mailbox sync managers.\n"); + return; + } else { + EC_SLAVE_DBG(slave, 1, "Resending after %u ms...\n", + (unsigned int) diff * 1000 / HZ); + } + + // send configuration datagram again + fsm->retries = EC_FSM_RETRIES; + return; + } + else if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to set sync managers: "); + ec_datagram_print_wc_error(datagram); + return; + } + +#ifdef EC_SII_ASSIGN + ec_fsm_slave_config_enter_assign_pdi(fsm); +#else + ec_fsm_slave_config_enter_boot_preop(fsm); +#endif +} + +/****************************************************************************/ + +#ifdef EC_SII_ASSIGN + +/** Assign SII to PDI. + */ +void ec_fsm_slave_config_enter_assign_pdi( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (fsm->slave->requested_state != EC_SLAVE_STATE_BOOT) { + EC_SLAVE_DBG(slave, 1, "Assigning SII access to PDI.\n"); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0500, 0x01); + EC_WRITE_U8(datagram->data, 0x01); // PDI + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_assign_pdi; + } + else { + ec_fsm_slave_config_enter_boot_preop(fsm); + } +} + +/****************************************************************************/ + +/** Slave configuration state: ASSIGN_PDI. + */ +void ec_fsm_slave_config_state_assign_pdi( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_WARN(slave, "Failed receive SII assignment datagram: "); + ec_datagram_print_state(datagram); + goto cont_preop; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(slave, "Failed to assign SII to PDI: "); + ec_datagram_print_wc_error(datagram); + } + +cont_preop: + ec_fsm_slave_config_enter_boot_preop(fsm); +} + +#endif + +/****************************************************************************/ + +/** Request PREOP state. + */ +void ec_fsm_slave_config_enter_boot_preop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + fsm->state = ec_fsm_slave_config_state_boot_preop; + + if (fsm->slave->requested_state != EC_SLAVE_STATE_BOOT) { + ec_fsm_change_start(fsm->fsm_change, + fsm->slave, EC_SLAVE_STATE_PREOP); + } else { // BOOT + ec_fsm_change_start(fsm->fsm_change, + fsm->slave, EC_SLAVE_STATE_BOOT); + } + + ec_fsm_change_exec(fsm->fsm_change); // execute immediately +} + +/****************************************************************************/ + +/** Slave configuration state: BOOT/PREOP. + */ +void ec_fsm_slave_config_state_boot_preop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; +#ifdef EC_SII_ASSIGN + int assign_to_pdi; + ec_slave_config_t *config; + ec_flag_t *flag; +#endif + + if (ec_fsm_change_exec(fsm->fsm_change)) { + return; + } + + if (!ec_fsm_change_success(fsm->fsm_change)) { + if (!fsm->fsm_change->spontaneous_change) + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + // slave is now in BOOT or PREOP + slave->jiffies_preop = fsm->datagram->jiffies_received; + + EC_SLAVE_DBG(slave, 1, "Now in %s.\n", + slave->requested_state != EC_SLAVE_STATE_BOOT ? "PREOP" : "BOOT"); + +#ifdef EC_SII_ASSIGN + assign_to_pdi = 0; + config = fsm->slave->config; + if (config) { + flag = ec_slave_config_find_flag(config, "AssignToPdi"); + if (flag) { + assign_to_pdi = flag->value; + } + } + + if (assign_to_pdi) { + EC_SLAVE_DBG(slave, 1, "Skipping SII assignment back to EtherCAT.\n"); + if (slave->current_state == slave->requested_state) { + fsm->state = ec_fsm_slave_config_state_end; // successful + EC_SLAVE_DBG(slave, 1, "Finished configuration.\n"); + return; + } + + ec_fsm_slave_config_enter_sdo_conf(fsm); + } + else { + EC_SLAVE_DBG(slave, 1, "Assigning SII access back to EtherCAT.\n"); + + ec_datagram_fpwr(fsm->datagram, slave->station_address, 0x0500, 0x01); + EC_WRITE_U8(fsm->datagram->data, 0x00); // EtherCAT + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_assign_ethercat; + } +#else + if (slave->current_state == slave->requested_state) { + fsm->state = ec_fsm_slave_config_state_end; // successful + EC_SLAVE_DBG(slave, 1, "Finished configuration.\n"); + return; + } + + ec_fsm_slave_config_enter_sdo_conf(fsm); +#endif +} + +/****************************************************************************/ + +#ifdef EC_SII_ASSIGN + +/** Slave configuration state: ASSIGN_ETHERCAT. + */ +void ec_fsm_slave_config_state_assign_ethercat( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_WARN(slave, "Failed receive SII assignment datagram: "); + ec_datagram_print_state(datagram); + goto cont_sdo_conf; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(slave, "Failed to assign SII back to EtherCAT: "); + ec_datagram_print_wc_error(datagram); + } + +cont_sdo_conf: + if (slave->current_state == slave->requested_state) { + fsm->state = ec_fsm_slave_config_state_end; // successful + EC_SLAVE_DBG(slave, 1, "Finished configuration.\n"); + return; + } + + ec_fsm_slave_config_enter_sdo_conf(fsm); +} + +#endif + +/****************************************************************************/ + +/** Check for SDO configurations to be applied. + */ +void ec_fsm_slave_config_enter_sdo_conf( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (!slave->config) { + ec_fsm_slave_config_enter_pdo_sync(fsm); + return; + } + + // No CoE configuration to be applied? + if (list_empty(&slave->config->sdo_configs)) { // skip SDO configuration + ec_fsm_slave_config_enter_soe_conf_preop(fsm); + return; + } + + // start SDO configuration + fsm->state = ec_fsm_slave_config_state_sdo_conf; + fsm->request = list_entry(fsm->slave->config->sdo_configs.next, + ec_sdo_request_t, list); + ec_sdo_request_copy(&fsm->request_copy, fsm->request); + ecrt_sdo_request_write(&fsm->request_copy); + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request_copy); + ec_fsm_coe_exec(fsm->fsm_coe, fsm->datagram); // execute immediately +} + +/****************************************************************************/ + +/** Slave configuration state: SDO_CONF. + */ +void ec_fsm_slave_config_state_sdo_conf( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, fsm->datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_ERR(fsm->slave, "SDO configuration failed.\n"); + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + if (!fsm->slave->config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + // Another SDO to configure? + if (fsm->request->list.next != &fsm->slave->config->sdo_configs) { + fsm->request = list_entry(fsm->request->list.next, + ec_sdo_request_t, list); + ec_sdo_request_copy(&fsm->request_copy, fsm->request); + ecrt_sdo_request_write(&fsm->request_copy); + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request_copy); + ec_fsm_coe_exec(fsm->fsm_coe, fsm->datagram); // execute immediately + return; + } + + // All SDOs are now configured. + ec_fsm_slave_config_enter_soe_conf_preop(fsm); +} + +/****************************************************************************/ + +/** Check for SoE configurations to be applied. + */ +void ec_fsm_slave_config_enter_soe_conf_preop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *req; + + if (!slave->config) { + ec_fsm_slave_config_enter_pdo_sync(fsm); + return; + } + + list_for_each_entry(req, &slave->config->soe_configs, list) { + if (req->al_state == EC_AL_STATE_PREOP) { + // start SoE configuration + fsm->state = ec_fsm_slave_config_state_soe_conf_preop; + fsm->soe_request = req; + ec_soe_request_copy(&fsm->soe_request_copy, fsm->soe_request); + ec_soe_request_write(&fsm->soe_request_copy); + ec_fsm_soe_transfer(fsm->fsm_soe, fsm->slave, + &fsm->soe_request_copy); + ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram); + return; + } + } + + // No SoE configuration to be applied in PREOP + ec_fsm_slave_config_enter_eoe_ip_param(fsm); +} + +/****************************************************************************/ + +/** Slave configuration state: SOE_CONF. + */ +void ec_fsm_slave_config_state_soe_conf_preop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram)) { + return; + } + + if (!ec_fsm_soe_success(fsm->fsm_soe)) { + EC_SLAVE_ERR(slave, "SoE configuration failed.\n"); + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + if (!fsm->slave->config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + // Another IDN to configure in PREOP? + while (fsm->soe_request->list.next != &fsm->slave->config->soe_configs) { + fsm->soe_request = list_entry(fsm->soe_request->list.next, + ec_soe_request_t, list); + if (fsm->soe_request->al_state == EC_AL_STATE_PREOP) { + ec_soe_request_copy(&fsm->soe_request_copy, fsm->soe_request); + ec_soe_request_write(&fsm->soe_request_copy); + ec_fsm_soe_transfer(fsm->fsm_soe, fsm->slave, + &fsm->soe_request_copy); + ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram); + return; + } + } + + // All PREOP IDNs are now configured. + ec_fsm_slave_config_enter_eoe_ip_param(fsm); +} + +/****************************************************************************/ + +/** EOE_IP_PARAM entry function. + */ +void ec_fsm_slave_config_enter_eoe_ip_param( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ +#ifdef EC_EOE + ec_slave_t *slave = fsm->slave; + ec_eoe_request_t *request = &slave->config->eoe_ip_param_request; + + if (ec_eoe_request_valid(request)) { + EC_SLAVE_DBG(slave, 1, "Setting EoE IP parameters...\n"); + + // Start EoE command + fsm->state = ec_fsm_slave_config_state_eoe_ip_param; + ec_fsm_eoe_set_ip_param(fsm->fsm_eoe, slave, request); + ec_fsm_eoe_exec(fsm->fsm_eoe, fsm->datagram); // execute immediately + return; + } +#endif + + ec_fsm_slave_config_enter_pdo_conf(fsm); +} + +/****************************************************************************/ + +/** Slave configuration state: EOE_IP_PARAM. + */ +void ec_fsm_slave_config_state_eoe_ip_param( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ +#ifdef EC_EOE + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_eoe_exec(fsm->fsm_eoe, fsm->datagram)) { + return; + } + + if (ec_fsm_eoe_success(fsm->fsm_eoe)) { + EC_SLAVE_DBG(slave, 1, "Finished setting EoE IP parameters.\n"); + } + else { + EC_SLAVE_ERR(slave, "Failed to set EoE IP parameters.\n"); + } +#endif + ec_fsm_slave_config_enter_pdo_conf(fsm); +} + +/****************************************************************************/ + +/** PDO_CONF entry function. + */ +void ec_fsm_slave_config_enter_pdo_conf( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + // Start configuring PDOs + ec_fsm_pdo_start_configuration(fsm->fsm_pdo, fsm->slave); + fsm->state = ec_fsm_slave_config_state_pdo_conf; + fsm->state(fsm); // execute immediately +} + +/****************************************************************************/ + +/** Slave configuration state: PDO_CONF. + */ +void ec_fsm_slave_config_state_pdo_conf( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + // TODO check for config here + + if (ec_fsm_pdo_exec(fsm->fsm_pdo, fsm->datagram)) { + return; + } + + if (!fsm->slave->config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + if (!ec_fsm_pdo_success(fsm->fsm_pdo)) { + EC_SLAVE_WARN(fsm->slave, "PDO configuration failed.\n"); + } + + ec_fsm_slave_config_enter_watchdog_divider(fsm); +} + +/****************************************************************************/ + +/** WATCHDOG_DIVIDER entry function. + */ +void ec_fsm_slave_config_enter_watchdog_divider( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + ec_slave_config_t *config = slave->config; + + if (config && config->watchdog_divider) { + EC_SLAVE_DBG(slave, 1, "Setting watchdog divider to %u.\n", + config->watchdog_divider); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0400, 2); + EC_WRITE_U16(datagram->data, config->watchdog_divider); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_watchdog_divider; + } else { + ec_fsm_slave_config_enter_watchdog(fsm); + } +} + +/****************************************************************************/ + +/** Slave configuration state: WATCHDOG_DIVIDER. + */ +void ec_fsm_slave_config_state_watchdog_divider( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive watchdog divider" + " configuration datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + EC_SLAVE_WARN(slave, "Failed to set watchdog divider: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_watchdog(fsm); +} + +/****************************************************************************/ + +/** WATCHDOG entry function + */ +void ec_fsm_slave_config_enter_watchdog( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + ec_slave_config_t *config = slave->config; + + if (config && config->watchdog_intervals) { + EC_SLAVE_DBG(slave, 1, "Setting process data" + " watchdog intervals to %u.\n", config->watchdog_intervals); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0420, 2); + EC_WRITE_U16(datagram->data, config->watchdog_intervals); + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_watchdog; + } else { + ec_fsm_slave_config_enter_pdo_sync(fsm); + } +} + +/****************************************************************************/ + +/** Slave configuration state: WATCHDOG. + */ + +void ec_fsm_slave_config_state_watchdog( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive sync manager" + " watchdog configuration datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(slave, "Failed to set process data" + " watchdog intervals: "); + ec_datagram_print_wc_error(datagram); + } + + ec_fsm_slave_config_enter_pdo_sync(fsm); +} + +/****************************************************************************/ + +/** Check for PDO sync managers to be configured. + */ +void ec_fsm_slave_config_enter_pdo_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + unsigned int i, j, offset, num_pdo_syncs; + uint8_t sync_index; + const ec_sync_t *sync; + uint16_t size; + + if (slave->sii.mailbox_protocols) { + offset = 2; // slave has mailboxes + } else { + offset = 0; + } + + if (slave->sii.sync_count <= offset) { + // no PDO sync managers to configure + ec_fsm_slave_config_enter_fmmu(fsm); + return; + } + + num_pdo_syncs = slave->sii.sync_count - offset; + + // configure sync managers for process data + ec_datagram_fpwr(datagram, slave->station_address, + 0x0800 + EC_SYNC_PAGE_SIZE * offset, + EC_SYNC_PAGE_SIZE * num_pdo_syncs); + ec_datagram_zero(datagram); + + for (i = 0; i < num_pdo_syncs; i++) { + const ec_sync_config_t *sync_config; + uint8_t pdo_xfer = 0; + sync_index = i + offset; + sync = &slave->sii.syncs[sync_index]; + + if (slave->config) { + const ec_slave_config_t *sc = slave->config; + sync_config = &sc->sync_configs[sync_index]; + size = ec_pdo_list_total_size(&sync_config->pdos); + + // determine, if PDOs shall be transferred via this SM + // inthat case, enable sync manager in every case + for (j = 0; j < sc->used_fmmus; j++) { + if (sc->fmmu_configs[j].sync_index == sync_index) { + pdo_xfer = 1; + break; + } + } + + } else { + sync_config = NULL; + size = sync->default_length; + } + + ec_sync_page(sync, sync_index, size, sync_config, pdo_xfer, + datagram->data + EC_SYNC_PAGE_SIZE * i); + } + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_pdo_sync; +} + +/****************************************************************************/ + +/** Configure PDO sync managers. + */ +void ec_fsm_slave_config_state_pdo_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive process data sync" + " manager configuration datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to set process data sync managers: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_fmmu(fsm); +} + +/****************************************************************************/ + +/** Check for FMMUs to be configured. + */ +void ec_fsm_slave_config_enter_fmmu( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + unsigned int i; + const ec_fmmu_config_t *fmmu; + const ec_sync_t *sync; + + if (!slave->config) { + ec_fsm_slave_config_enter_wait_safeop(fsm); + return; + } + + if (slave->base_fmmu_count < slave->config->used_fmmus) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Slave has less FMMUs (%u)" + " than requested (%u).\n", slave->base_fmmu_count, + slave->config->used_fmmus); + return; + } + + if (!slave->base_fmmu_count) { // skip FMMU configuration + ec_fsm_slave_config_enter_dc_cycle(fsm); + return; + } + + // configure FMMUs + ec_datagram_fpwr(datagram, slave->station_address, + 0x0600, EC_FMMU_PAGE_SIZE * slave->base_fmmu_count); + ec_datagram_zero(datagram); + for (i = 0; i < slave->config->used_fmmus; i++) { + fmmu = &slave->config->fmmu_configs[i]; + if (!(sync = ec_slave_get_sync(slave, fmmu->sync_index))) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to determine PDO sync manager" + " for FMMU!\n"); + return; + } + ec_fmmu_config_page(fmmu, sync, + datagram->data + EC_FMMU_PAGE_SIZE * i); + } + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_fmmu; +} + +/****************************************************************************/ + +/** Slave configuration state: FMMU. + */ +void ec_fsm_slave_config_state_fmmu( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive FMMUs datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to set FMMUs: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_dc_cycle(fsm); +} + +/****************************************************************************/ + +/** Check for DC to be configured. + */ +void ec_fsm_slave_config_enter_dc_cycle( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + ec_slave_config_t *config = slave->config; + + if (!config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + if (config->dc_assign_activate) { + if (!slave->base_dc_supported || !slave->has_dc_system_time) { + EC_SLAVE_WARN(slave, "Slave seems not to support" + " distributed clocks!\n"); + } + + EC_SLAVE_DBG(slave, 1, "Setting DC cycle times to %u / %u.\n", + config->dc_sync[0].cycle_time, config->dc_sync[1].cycle_time); + + // set DC cycle times + ec_datagram_fpwr(datagram, slave->station_address, 0x09A0, 8); + EC_WRITE_U32(datagram->data, config->dc_sync[0].cycle_time); + EC_WRITE_U32(datagram->data + 4, config->dc_sync[1].cycle_time); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_dc_cycle; + } else { + // DC are unused + ec_fsm_slave_config_enter_wait_safeop(fsm); + } +} + +/****************************************************************************/ + +/** Slave configuration state: DC CYCLE. + */ +void ec_fsm_slave_config_state_dc_cycle( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + ec_slave_config_t *config = slave->config; + + if (!config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive DC cycle times datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to set DC cycle times: "); + ec_datagram_print_wc_error(datagram); + return; + } + + EC_SLAVE_DBG(slave, 1, "Checking for synchrony.\n"); + + fsm->jiffies_start = jiffies; + ec_datagram_fprd(datagram, slave->station_address, 0x092c, 4); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_dc_sync_check; +} + +/****************************************************************************/ + +/** Slave configuration state: DC SYNC CHECK. + */ +void ec_fsm_slave_config_state_dc_sync_check( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + ec_slave_config_t *config = slave->config; + uint32_t abs_sync_diff; + unsigned long diff_ms; + ec_sync_signal_t *sync0 = &config->dc_sync[0]; + ec_sync_signal_t *sync1 = &config->dc_sync[1]; + u64 start_time; + + if (!config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive DC sync check datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to check DC synchrony: "); + ec_datagram_print_wc_error(datagram); + return; + } + + abs_sync_diff = EC_READ_U32(datagram->data) & 0x7fffffff; + diff_ms = (datagram->jiffies_received - fsm->jiffies_start) * 1000 / HZ; + + if (abs_sync_diff > EC_DC_MAX_SYNC_DIFF_NS) { + + if (diff_ms >= EC_DC_SYNC_WAIT_MS) { + EC_SLAVE_WARN(slave, "Slave did not sync after %lu ms.\n", + diff_ms); + } else { + EC_SLAVE_DBG(slave, 1, "Sync after %4lu ms: %10u ns\n", + diff_ms, abs_sync_diff); + + // check synchrony again + ec_datagram_fprd(datagram, slave->station_address, 0x092c, 4); + fsm->retries = EC_FSM_RETRIES; + return; + } + } else { + EC_SLAVE_DBG(slave, 1, "%u ns difference after %lu ms.\n", + abs_sync_diff, diff_ms); + } + + // set DC start time (roughly in the future, not in-phase) + start_time = master->app_time + EC_DC_START_OFFSET; // now + X ns + + if (sync0->cycle_time) { + // find correct phase + if (master->dc_ref_time) { + u64 diff, start; + u32 remainder, cycle; + + diff = start_time - master->dc_ref_time; + cycle = sync0->cycle_time + sync1->cycle_time; + remainder = do_div(diff, cycle); + + start = start_time + cycle - remainder + sync0->shift_time; + + EC_SLAVE_DBG(slave, 1, " ref_time=%llu\n", master->dc_ref_time); + EC_SLAVE_DBG(slave, 1, " app_time=%llu\n", master->app_time); + EC_SLAVE_DBG(slave, 1, " start_time=%llu\n", start_time); + EC_SLAVE_DBG(slave, 1, " cycle=%u\n", cycle); + EC_SLAVE_DBG(slave, 1, " shift_time=%i\n", sync0->shift_time); + EC_SLAVE_DBG(slave, 1, " remainder=%u\n", remainder); + EC_SLAVE_DBG(slave, 1, " start=%llu\n", start); + start_time = start; + } else { + EC_SLAVE_WARN(slave, "No application time supplied." + " Cyclic start time will not be in phase.\n"); + } + } + + EC_SLAVE_DBG(slave, 1, "Setting DC cyclic operation" + " start time to %llu.\n", start_time); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0990, 8); + EC_WRITE_U64(datagram->data, start_time); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_dc_start; +} + +/****************************************************************************/ + +/** Slave configuration state: DC START. + */ +void ec_fsm_slave_config_state_dc_start( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + ec_slave_config_t *config = slave->config; + + if (!config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive DC start time datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to set DC start time: "); + ec_datagram_print_wc_error(datagram); + return; + } + + EC_SLAVE_DBG(slave, 1, "Setting DC AssignActivate to 0x%04x.\n", + config->dc_assign_activate); + + // assign sync unit to EtherCAT or PDI + ec_datagram_fpwr(datagram, slave->station_address, 0x0980, 2); + EC_WRITE_U16(datagram->data, config->dc_assign_activate); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_dc_assign; +} + +/****************************************************************************/ + +/** Slave configuration state: DC ASSIGN. + */ +void ec_fsm_slave_config_state_dc_assign( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive DC activation datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to activate DC: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_wait_safeop(fsm); +} + +/****************************************************************************/ + +/** Wait before SAFEOP transition. + * + * The feature flag WaitBeforeSAFEOPms can be used to add a wait time before + * going to SAFEOP. This can be used as a workaround for slaves that need some + * extra time for initialisation. + */ +void ec_fsm_slave_config_enter_wait_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_config_t *config = fsm->slave->config; + fsm->wait_ms = 0UL; + if (config) { + ec_flag_t *flag = ec_slave_config_find_flag(config, + "WaitBeforeSAFEOPms"); + if (flag && flag->value > 0) { + fsm->wait_ms = (unsigned long) flag->value; + } + } + + if (fsm->wait_ms > 0) { + fsm->state = ec_fsm_slave_config_state_wait_safeop; + + /* dummy read */ + ec_datagram_fprd(fsm->datagram, fsm->slave->station_address, + 0x0600, 1); + + fsm->jiffies_start = jiffies; + } + else { + ec_fsm_slave_config_enter_safeop(fsm); + } +} + +/****************************************************************************/ + +/** Slave configuration state: WAIT SAFEOP. + */ +void ec_fsm_slave_config_state_wait_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + unsigned long diff = jiffies - fsm->jiffies_start; + + if (diff * 1000 / HZ < fsm->wait_ms) { + return; + } + + ec_fsm_slave_config_enter_safeop(fsm); +} + +/****************************************************************************/ + +/** Request SAFEOP state. + */ +void ec_fsm_slave_config_enter_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + fsm->state = ec_fsm_slave_config_state_safeop; + ec_fsm_change_start(fsm->fsm_change, fsm->slave, EC_SLAVE_STATE_SAFEOP); + ec_fsm_change_exec(fsm->fsm_change); // execute immediately +} + +/****************************************************************************/ + +/** Slave configuration state: SAFEOP. + */ +void ec_fsm_slave_config_state_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_change_exec(fsm->fsm_change)) return; + + if (!ec_fsm_change_success(fsm->fsm_change)) { + if (!fsm->fsm_change->spontaneous_change) + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + // slave is now in SAFEOP + + EC_SLAVE_DBG(slave, 1, "Now in SAFEOP.\n"); + + if (fsm->slave->current_state == fsm->slave->requested_state) { + fsm->state = ec_fsm_slave_config_state_end; // successful + EC_SLAVE_DBG(slave, 1, "Finished configuration.\n"); + return; + } + + ec_fsm_slave_config_enter_soe_conf_safeop(fsm); +} + +/****************************************************************************/ + +/** Check for SoE configurations to be applied in SAFEOP. + */ +void ec_fsm_slave_config_enter_soe_conf_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *req; + + if (!slave->config) { + ec_fsm_slave_config_enter_op(fsm); + return; + } + + list_for_each_entry(req, &slave->config->soe_configs, list) { + if (req->al_state == EC_AL_STATE_SAFEOP) { + // start SoE configuration + fsm->state = ec_fsm_slave_config_state_soe_conf_safeop; + fsm->soe_request = req; + ec_soe_request_copy(&fsm->soe_request_copy, fsm->soe_request); + ec_soe_request_write(&fsm->soe_request_copy); + ec_fsm_soe_transfer(fsm->fsm_soe, fsm->slave, + &fsm->soe_request_copy); + ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram); + return; + } + } + + // No SoE configuration to be applied in SAFEOP + ec_fsm_slave_config_enter_op(fsm); +} + +/****************************************************************************/ + +/** Slave configuration state: SOE_CONF. + */ +void ec_fsm_slave_config_state_soe_conf_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram)) { + return; + } + + if (!ec_fsm_soe_success(fsm->fsm_soe)) { + EC_SLAVE_ERR(slave, "SoE configuration failed.\n"); + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + if (!fsm->slave->config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + // Another IDN to configure in SAFEOP? + while (fsm->soe_request->list.next != &fsm->slave->config->soe_configs) { + fsm->soe_request = list_entry(fsm->soe_request->list.next, + ec_soe_request_t, list); + if (fsm->soe_request->al_state == EC_AL_STATE_SAFEOP) { + ec_soe_request_copy(&fsm->soe_request_copy, fsm->soe_request); + ec_soe_request_write(&fsm->soe_request_copy); + ec_fsm_soe_transfer(fsm->fsm_soe, fsm->slave, + &fsm->soe_request_copy); + ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram); + return; + } + } + + // All SAFEOP IDNs are now configured. + ec_fsm_slave_config_enter_op(fsm); +} + +/****************************************************************************/ + +/** Bring slave to OP. + */ +void ec_fsm_slave_config_enter_op( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + // set state to OP + fsm->state = ec_fsm_slave_config_state_op; + ec_fsm_change_start(fsm->fsm_change, fsm->slave, EC_SLAVE_STATE_OP); + ec_fsm_change_exec(fsm->fsm_change); // execute immediately +} + +/****************************************************************************/ + +/** Slave configuration state: OP + */ +void ec_fsm_slave_config_state_op( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_change_exec(fsm->fsm_change)) return; + + if (!ec_fsm_change_success(fsm->fsm_change)) { + if (!fsm->fsm_change->spontaneous_change) + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + // slave is now in OP + + EC_SLAVE_DBG(slave, 1, "Now in OP. Finished configuration.\n"); + + fsm->state = ec_fsm_slave_config_state_end; // successful +} + +/****************************************************************************/ + +/** Reconfigure the slave starting at INIT. + */ +void ec_fsm_slave_config_reconfigure( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + EC_SLAVE_DBG(fsm->slave, 1, "Slave configuration detached during " + "configuration. Reconfiguring."); + + ec_fsm_slave_config_enter_init(fsm); // reconfigure +} + +/***************************************************************************** + * Common state functions + ****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_slave_config_state_error( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_slave_config_state_end( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_slave_config.h b/ubuntu/igh-ecat/master/fsm_slave_config.h new file mode 100644 index 00000000000000..fa33c83b76de97 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_slave_config.h @@ -0,0 +1,81 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + \file + EtherCAT slave configuration state machine. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_SLAVE_CONFIG_H__ +#define __EC_FSM_SLAVE_CONFIG_H__ + +#include "globals.h" +#include "slave.h" +#include "datagram.h" +#include "fsm_change.h" +#include "fsm_coe.h" +#include "fsm_pdo.h" +#include "fsm_eoe.h" + +/****************************************************************************/ + +/** \see ec_fsm_slave_config */ +typedef struct ec_fsm_slave_config ec_fsm_slave_config_t; + +/** Finite state machine to configure an EtherCAT slave. + */ +struct ec_fsm_slave_config +{ + ec_datagram_t *datagram; /**< Datagram used in the state machine. */ + ec_fsm_change_t *fsm_change; /**< State change state machine. */ + ec_fsm_coe_t *fsm_coe; /**< CoE state machine. */ + ec_fsm_soe_t *fsm_soe; /**< SoE state machine. */ + ec_fsm_pdo_t *fsm_pdo; /**< PDO configuration state machine. */ + ec_fsm_eoe_t *fsm_eoe; /**< EoE state machine. */ + + ec_slave_t *slave; /**< Slave the FSM runs on. */ + void (*state)(ec_fsm_slave_config_t *); /**< State function. */ + unsigned int retries; /**< Retries on datagram timeout. */ + ec_sdo_request_t *request; /**< SDO request for SDO configuration. */ + ec_sdo_request_t request_copy; /**< Copied SDO request. */ + ec_soe_request_t *soe_request; /**< SDO request for SDO configuration. */ + ec_soe_request_t soe_request_copy; /**< Copied SDO request. */ + unsigned long jiffies_start; /**< For timeout calculations. */ + unsigned int take_time; /**< Store jiffies after datagram reception. */ + unsigned long wait_ms; /**< Wait time (used to wait before SAFEOP). */ +}; + +/****************************************************************************/ + +void ec_fsm_slave_config_init(ec_fsm_slave_config_t *, ec_datagram_t *, + ec_fsm_change_t *, ec_fsm_coe_t *, ec_fsm_soe_t *, ec_fsm_pdo_t *, + ec_fsm_eoe_t *); +void ec_fsm_slave_config_clear(ec_fsm_slave_config_t *); + +void ec_fsm_slave_config_start(ec_fsm_slave_config_t *, ec_slave_t *); + +int ec_fsm_slave_config_exec(ec_fsm_slave_config_t *); +int ec_fsm_slave_config_success(const ec_fsm_slave_config_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_slave_scan.c b/ubuntu/igh-ecat/master/fsm_slave_scan.c new file mode 100644 index 00000000000000..e4b563583e0cea --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_slave_scan.c @@ -0,0 +1,1121 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave state machines. +*/ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" + +#include "fsm_slave_scan.h" + +/****************************************************************************/ + +// prototypes for private methods +int ec_fsm_slave_scan_running(const ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_enter_sii_size(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_enter_assign_sii(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_enter_datalink(ec_fsm_slave_scan_t *); +#ifdef EC_REGALIAS +void ec_fsm_slave_scan_enter_regalias(ec_fsm_slave_scan_t *); +#endif +void ec_fsm_slave_scan_enter_preop(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_enter_pdos(ec_fsm_slave_scan_t *); + +/****************************************************************************/ + +void ec_fsm_slave_scan_state_start(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_address(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_state(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_base(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_dc_cap(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_dc_times(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_datalink(ec_fsm_slave_scan_t *); +#ifdef EC_SII_ASSIGN +void ec_fsm_slave_scan_state_assign_sii(ec_fsm_slave_scan_t *); +#endif +void ec_fsm_slave_scan_state_sii_size(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_sii_data(ec_fsm_slave_scan_t *); +#ifdef EC_REGALIAS +void ec_fsm_slave_scan_state_regalias(ec_fsm_slave_scan_t *); +#endif +void ec_fsm_slave_scan_state_preop(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_sync(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_pdos(ec_fsm_slave_scan_t *); + +void ec_fsm_slave_scan_state_end(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_error(ec_fsm_slave_scan_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_slave_scan_init( + ec_fsm_slave_scan_t *fsm, /**< Slave scanning state machine. */ + ec_datagram_t *datagram, /**< Datagram to use. */ + ec_fsm_slave_config_t *fsm_slave_config, /**< Slave configuration + state machine to use. */ + ec_fsm_pdo_t *fsm_pdo /**< PDO configuration machine to use. */ + ) +{ + fsm->datagram = datagram; + fsm->fsm_slave_config = fsm_slave_config; + fsm->fsm_pdo = fsm_pdo; + + // init sub state machines + ec_fsm_sii_init(&fsm->fsm_sii, fsm->datagram); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_slave_scan_clear(ec_fsm_slave_scan_t *fsm /**< slave state machine */) +{ + // clear sub state machines + ec_fsm_sii_clear(&fsm->fsm_sii); +} + +/****************************************************************************/ + +/** + * Start slave scan state machine. + */ + +void ec_fsm_slave_scan_start( + ec_fsm_slave_scan_t *fsm, /**< slave state machine */ + ec_slave_t *slave /**< slave to configure */ + ) +{ + fsm->slave = slave; + fsm->state = ec_fsm_slave_scan_state_start; +} + +/****************************************************************************/ + +/** + \return false, if state machine has terminated +*/ + +int ec_fsm_slave_scan_running( + const ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + return fsm->state != ec_fsm_slave_scan_state_end + && fsm->state != ec_fsm_slave_scan_state_error; +} + +/****************************************************************************/ + +/** + Executes the current state of the state machine. + If the state machine's datagram is not sent or received yet, the execution + of the state machine is delayed to the next cycle. + \return false, if state machine has terminated +*/ + +int ec_fsm_slave_scan_exec(ec_fsm_slave_scan_t *fsm /**< slave state machine */) +{ + if (fsm->datagram->state == EC_DATAGRAM_SENT + || fsm->datagram->state == EC_DATAGRAM_QUEUED) { + // datagram was not sent or received yet. + return ec_fsm_slave_scan_running(fsm); + } + + fsm->state(fsm); + return ec_fsm_slave_scan_running(fsm); +} + +/****************************************************************************/ + +/** + \return true, if the state machine terminated gracefully +*/ + +int ec_fsm_slave_scan_success(const ec_fsm_slave_scan_t *fsm /**< slave state machine */) +{ + return fsm->state == ec_fsm_slave_scan_state_end; +} + +/***************************************************************************** + * slave scan state machine + ****************************************************************************/ + +/** + Slave scan state: START. + First state of the slave state machine. Writes the station address to the + slave, according to its ring position. +*/ + +void ec_fsm_slave_scan_state_start(ec_fsm_slave_scan_t *fsm /**< slave state machine */) +{ + // write station address + ec_datagram_apwr(fsm->datagram, fsm->slave->ring_position, 0x0010, 2); + EC_WRITE_U16(fsm->datagram->data, fsm->slave->station_address); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_address; +} + +/****************************************************************************/ + +/** + Slave scan state: ADDRESS. +*/ + +void ec_fsm_slave_scan_state_address( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(fsm->slave, + "Failed to receive station address datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed to write station address: "); + ec_datagram_print_wc_error(datagram); + return; + } + + // Read AL state + ec_datagram_fprd(datagram, fsm->slave->station_address, 0x0130, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_state; +} + +/****************************************************************************/ + +/** + Slave scan state: STATE. +*/ + +void ec_fsm_slave_scan_state_state( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive AL state datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to read AL state: "); + ec_datagram_print_wc_error(datagram); + return; + } + + slave->current_state = EC_READ_U8(datagram->data); + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(slave->current_state, state_str, 0); + EC_SLAVE_WARN(slave, "Slave has state error bit set (%s)!\n", + state_str); + } + + // read base data + ec_datagram_fprd(datagram, fsm->slave->station_address, 0x0000, 12); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_base; +} + +/****************************************************************************/ + +/** Slave scan state: BASE. + */ +void ec_fsm_slave_scan_state_base( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + u8 octet; + int i; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive base data datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to read base data: "); + ec_datagram_print_wc_error(datagram); + return; + } + + slave->base_type = EC_READ_U8 (datagram->data); + slave->base_revision = EC_READ_U8 (datagram->data + 1); + slave->base_build = EC_READ_U16(datagram->data + 2); + + slave->base_fmmu_count = EC_READ_U8 (datagram->data + 4); + if (slave->base_fmmu_count > EC_MAX_FMMUS) { + EC_SLAVE_WARN(slave, "Slave has more FMMUs (%u) than the master can" + " handle (%u).\n", slave->base_fmmu_count, EC_MAX_FMMUS); + slave->base_fmmu_count = EC_MAX_FMMUS; + } + + slave->base_sync_count = EC_READ_U8(datagram->data + 5); + if (slave->base_sync_count > EC_MAX_SYNC_MANAGERS) { + EC_SLAVE_WARN(slave, "Slave provides more sync managers (%u)" + " than the master can handle (%u).\n", + slave->base_sync_count, EC_MAX_SYNC_MANAGERS); + slave->base_sync_count = EC_MAX_SYNC_MANAGERS; + } + + octet = EC_READ_U8(datagram->data + 7); + for (i = 0; i < EC_MAX_PORTS; i++) { + slave->ports[i].desc = (octet >> (2 * i)) & 0x03; + } + + octet = EC_READ_U8(datagram->data + 8); + slave->base_fmmu_bit_operation = octet & 0x01; + slave->base_dc_supported = (octet >> 2) & 0x01; + slave->base_dc_range = ((octet >> 3) & 0x01) ? EC_DC_64 : EC_DC_32; + + if (slave->base_dc_supported) { + // read DC capabilities + ec_datagram_fprd(datagram, slave->station_address, 0x0910, + slave->base_dc_range == EC_DC_64 ? 8 : 4); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_dc_cap; + } else { + ec_fsm_slave_scan_enter_datalink(fsm); + } +} + +/****************************************************************************/ + +/** + Slave scan state: DC CAPABILITIES. +*/ + +void ec_fsm_slave_scan_state_dc_cap( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive system time datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter == 1) { + slave->has_dc_system_time = 1; + EC_SLAVE_DBG(slave, 1, "Slave has the System Time register.\n"); + } else if (datagram->working_counter == 0) { + EC_SLAVE_DBG(slave, 1, "Slave has no System Time register; delay " + "measurement only.\n"); + } else { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to determine, if system time register is " + "supported: "); + ec_datagram_print_wc_error(datagram); + return; + } + + // read DC port receive times + ec_datagram_fprd(datagram, slave->station_address, 0x0900, 16); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_dc_times; +} + +/****************************************************************************/ + +/** + Slave scan state: DC TIMES. +*/ + +void ec_fsm_slave_scan_state_dc_times( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + int i; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive system time datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to get DC receive times: "); + ec_datagram_print_wc_error(datagram); + return; + } + + for (i = 0; i < EC_MAX_PORTS; i++) { + slave->ports[i].receive_time = EC_READ_U32(datagram->data + 4 * i); + } + + ec_fsm_slave_scan_enter_datalink(fsm); +} + +/****************************************************************************/ + +/** + Slave scan entry function: DATALINK. +*/ + +void ec_fsm_slave_scan_enter_datalink( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + // read data link status + ec_datagram_fprd(datagram, slave->station_address, 0x0110, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_datalink; +} + +/****************************************************************************/ + +/** Enter slave scan state SII_SIZE. + */ +void ec_fsm_slave_scan_enter_sii_size( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + // Start fetching SII size + + EC_SLAVE_DBG(fsm->slave, 1, "Determining SII size.\n"); + + fsm->sii_offset = EC_FIRST_SII_CATEGORY_OFFSET; // first category header + ec_fsm_sii_read(&fsm->fsm_sii, fsm->slave, fsm->sii_offset, + EC_FSM_SII_USE_CONFIGURED_ADDRESS); + fsm->state = ec_fsm_slave_scan_state_sii_size; + fsm->state(fsm); // execute state immediately +} + +/****************************************************************************/ + +#ifdef EC_SII_ASSIGN + +/** Enter slave scan state ASSIGN_SII. + */ +void ec_fsm_slave_scan_enter_assign_sii( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + EC_SLAVE_DBG(slave, 1, "Assigning SII access to EtherCAT.\n"); + + // assign SII to ECAT + ec_datagram_fpwr(datagram, slave->station_address, 0x0500, 1); + EC_WRITE_U8(datagram->data, 0x00); // EtherCAT + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_assign_sii; +} + +#endif + +/****************************************************************************/ + +/** + Slave scan state: DATALINK. +*/ + +void ec_fsm_slave_scan_state_datalink( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + uint16_t dl_status; + unsigned int i; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive DL status datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to read DL status: "); + ec_datagram_print_wc_error(datagram); + return; + } + + dl_status = EC_READ_U16(datagram->data); + for (i = 0; i < EC_MAX_PORTS; i++) { + slave->ports[i].link.link_up = + dl_status & (1 << (4 + i)) ? 1 : 0; + slave->ports[i].link.loop_closed = + dl_status & (1 << (8 + i * 2)) ? 1 : 0; + slave->ports[i].link.signal_detected = + dl_status & (1 << (9 + i * 2)) ? 1 : 0; + } + +#ifdef EC_SII_ASSIGN + ec_fsm_slave_scan_enter_assign_sii(fsm); +#else + ec_fsm_slave_scan_enter_sii_size(fsm); +#endif +} + +/****************************************************************************/ + +#ifdef EC_SII_ASSIGN + +/** + Slave scan state: ASSIGN_SII. +*/ + +void ec_fsm_slave_scan_state_assign_sii( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_WARN(slave, "Failed to receive SII assignment datagram: "); + ec_datagram_print_state(datagram); + // Try to go on, probably assignment is correct + goto continue_with_sii_size; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(slave, "Failed to assign SII to EtherCAT: "); + ec_datagram_print_wc_error(datagram); + // Try to go on, probably assignment is correct + } + +continue_with_sii_size: + ec_fsm_slave_scan_enter_sii_size(fsm); +} + +#endif + +/****************************************************************************/ + +/** + Slave scan state: SII SIZE. +*/ + +void ec_fsm_slave_scan_state_sii_size( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint16_t cat_type, cat_size; + + if (ec_fsm_sii_exec(&fsm->fsm_sii)) + return; + + if (!ec_fsm_sii_success(&fsm->fsm_sii)) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to determine SII content size:" + " Reading word offset 0x%04x failed. Assuming %u words.\n", + fsm->sii_offset, EC_FIRST_SII_CATEGORY_OFFSET); + slave->sii_nwords = EC_FIRST_SII_CATEGORY_OFFSET; + goto alloc_sii; + } + + cat_type = EC_READ_U16(fsm->fsm_sii.value); + cat_size = EC_READ_U16(fsm->fsm_sii.value + 2); + + if (cat_type != 0xFFFF) { // not the last category + off_t next_offset = 2UL + fsm->sii_offset + cat_size; + + EC_SLAVE_DBG(slave, 1, "Found category type %u with size %u." + " Proceeding to offset %zd.\n", + cat_type, cat_size, (ssize_t)next_offset); + + if (next_offset >= EC_MAX_SII_SIZE) { + EC_SLAVE_WARN(slave, "SII size exceeds %u words" + " (0xffff limiter missing?).\n", EC_MAX_SII_SIZE); + // cut off category data... + slave->sii_nwords = EC_FIRST_SII_CATEGORY_OFFSET; + goto alloc_sii; + } + fsm->sii_offset = next_offset; + ec_fsm_sii_read(&fsm->fsm_sii, slave, fsm->sii_offset, + EC_FSM_SII_USE_CONFIGURED_ADDRESS); + ec_fsm_sii_exec(&fsm->fsm_sii); // execute state immediately + return; + } + + slave->sii_nwords = fsm->sii_offset + 1; + +alloc_sii: + if (slave->sii_words) { + EC_SLAVE_WARN(slave, "Freeing old SII data...\n"); + kfree(slave->sii_words); + } + + if (!(slave->sii_words = + (uint16_t *) kmalloc(slave->sii_nwords * 2, GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate %zu words of SII data.\n", + slave->sii_nwords); + slave->sii_nwords = 0; + slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + return; + } + + // Start fetching SII contents + + fsm->state = ec_fsm_slave_scan_state_sii_data; + fsm->sii_offset = 0x0000; + ec_fsm_sii_read(&fsm->fsm_sii, slave, fsm->sii_offset, + EC_FSM_SII_USE_CONFIGURED_ADDRESS); + ec_fsm_sii_exec(&fsm->fsm_sii); // execute state immediately +} + +/****************************************************************************/ + +/** + Slave scan state: SII DATA. +*/ + +void ec_fsm_slave_scan_state_sii_data(ec_fsm_slave_scan_t *fsm + /**< slave state machine */) +{ + ec_slave_t *slave = fsm->slave; + uint16_t *cat_word, cat_type, cat_size; + + if (ec_fsm_sii_exec(&fsm->fsm_sii)) return; + + if (!ec_fsm_sii_success(&fsm->fsm_sii)) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to fetch SII contents.\n"); + return; + } + + // 2 words fetched + + if (fsm->sii_offset + 2 <= slave->sii_nwords) { // 2 words fit + memcpy(slave->sii_words + fsm->sii_offset, fsm->fsm_sii.value, 4); + } else { // copy the last word + memcpy(slave->sii_words + fsm->sii_offset, fsm->fsm_sii.value, 2); + } + + if (fsm->sii_offset + 2 < slave->sii_nwords) { + // fetch the next 2 words + fsm->sii_offset += 2; + ec_fsm_sii_read(&fsm->fsm_sii, slave, fsm->sii_offset, + EC_FSM_SII_USE_CONFIGURED_ADDRESS); + ec_fsm_sii_exec(&fsm->fsm_sii); // execute state immediately + return; + } + + // Evaluate SII contents + + ec_slave_clear_sync_managers(slave); + + slave->sii.alias = + EC_READ_U16(slave->sii_words + 0x0004); + slave->effective_alias = slave->sii.alias; + slave->sii.vendor_id = + EC_READ_U32(slave->sii_words + 0x0008); + slave->sii.product_code = + EC_READ_U32(slave->sii_words + 0x000A); + slave->sii.revision_number = + EC_READ_U32(slave->sii_words + 0x000C); + slave->sii.serial_number = + EC_READ_U32(slave->sii_words + 0x000E); + slave->sii.boot_rx_mailbox_offset = + EC_READ_U16(slave->sii_words + 0x0014); + slave->sii.boot_rx_mailbox_size = + EC_READ_U16(slave->sii_words + 0x0015); + slave->sii.boot_tx_mailbox_offset = + EC_READ_U16(slave->sii_words + 0x0016); + slave->sii.boot_tx_mailbox_size = + EC_READ_U16(slave->sii_words + 0x0017); + slave->sii.std_rx_mailbox_offset = + EC_READ_U16(slave->sii_words + 0x0018); + slave->sii.std_rx_mailbox_size = + EC_READ_U16(slave->sii_words + 0x0019); + slave->sii.std_tx_mailbox_offset = + EC_READ_U16(slave->sii_words + 0x001A); + slave->sii.std_tx_mailbox_size = + EC_READ_U16(slave->sii_words + 0x001B); + slave->sii.mailbox_protocols = + EC_READ_U16(slave->sii_words + 0x001C); + if (slave->sii.mailbox_protocols) { + int need_delim = 0; + uint16_t all = EC_MBOX_AOE | EC_MBOX_COE | EC_MBOX_FOE | + EC_MBOX_SOE | EC_MBOX_VOE; + if ((slave->sii.mailbox_protocols & all) && + slave->master->debug_level >= 1) { + EC_SLAVE_DBG(slave, 1, "Slave announces to support "); + if (slave->sii.mailbox_protocols & EC_MBOX_AOE) { + printk(KERN_CONT "AoE"); + need_delim = 1; + } + if (slave->sii.mailbox_protocols & EC_MBOX_COE) { + if (need_delim) { + printk(KERN_CONT ", "); + } + printk(KERN_CONT "CoE"); + need_delim = 1; + } + if (slave->sii.mailbox_protocols & EC_MBOX_FOE) { + if (need_delim) { + printk(KERN_CONT ", "); + } + printk(KERN_CONT "FoE"); + need_delim = 1; + } + if (slave->sii.mailbox_protocols & EC_MBOX_SOE) { + if (need_delim) { + printk(KERN_CONT ", "); + } + printk(KERN_CONT "SoE"); + need_delim = 1; + } + if (slave->sii.mailbox_protocols & EC_MBOX_VOE) { + if (need_delim) { + printk(KERN_CONT ", "); + } + printk(KERN_CONT "VoE"); + need_delim = 1; + } + printk(KERN_CONT ".\n"); + } + if (slave->sii.mailbox_protocols & ~all) { + EC_SLAVE_DBG(slave, 1, "Slave announces to support unknown" + " mailbox protocols 0x%04X.", + slave->sii.mailbox_protocols & ~all); + } + } + else { + EC_SLAVE_DBG(slave, 1, "Slave announces to support no mailbox" + " protocols."); + } + + if (slave->sii.boot_rx_mailbox_offset == 0xffff || + slave->sii.boot_rx_mailbox_size == 0xffff || + slave->sii.boot_tx_mailbox_offset == 0xffff || + slave->sii.boot_tx_mailbox_size == 0xffff || + slave->sii.std_rx_mailbox_offset == 0xffff || + slave->sii.std_rx_mailbox_size == 0xffff || + slave->sii.std_tx_mailbox_offset == 0xffff || + slave->sii.std_tx_mailbox_size == 0xffff) { + slave->sii.mailbox_protocols = 0x0000; + EC_SLAVE_ERR(slave, "Invalid mailbox settings in SII." + " Disabling mailbox communication."); + } + + if (slave->sii_nwords == EC_FIRST_SII_CATEGORY_OFFSET) { + // sii does not contain category data + fsm->state = ec_fsm_slave_scan_state_end; + return; + } + + if (slave->sii_nwords < EC_FIRST_SII_CATEGORY_OFFSET + 1) { + EC_SLAVE_ERR(slave, "Unexpected end of SII data:" + " First category header missing.\n"); + goto end; + } + + // evaluate category data + cat_word = slave->sii_words + EC_FIRST_SII_CATEGORY_OFFSET; + while (EC_READ_U16(cat_word) != 0xFFFF) { + + // type and size words must fit + if (cat_word + 2 - slave->sii_words > slave->sii_nwords) { + EC_SLAVE_ERR(slave, "Unexpected end of SII data:" + " Category header incomplete.\n"); + goto end; + } + + cat_type = EC_READ_U16(cat_word) & 0x7FFF; + cat_size = EC_READ_U16(cat_word + 1); + cat_word += 2; + + if (cat_word + cat_size - slave->sii_words > slave->sii_nwords) { + EC_SLAVE_WARN(slave, "Unexpected end of SII data:" + " Category data incomplete.\n"); + goto end; + } + + switch (cat_type) { + case 0x000A: + if (ec_slave_fetch_sii_strings(slave, (uint8_t *) cat_word, + cat_size * 2)) + goto end; + break; + case 0x001E: + if (ec_slave_fetch_sii_general(slave, (uint8_t *) cat_word, + cat_size * 2)) + goto end; + break; + case 0x0028: + break; + case 0x0029: + if (ec_slave_fetch_sii_syncs(slave, (uint8_t *) cat_word, + cat_size * 2)) + goto end; + break; + case 0x0032: + if (ec_slave_fetch_sii_pdos( slave, (uint8_t *) cat_word, + cat_size * 2, EC_DIR_INPUT)) // TxPDO + goto end; + break; + case 0x0033: + if (ec_slave_fetch_sii_pdos( slave, (uint8_t *) cat_word, + cat_size * 2, EC_DIR_OUTPUT)) // RxPDO + goto end; + break; + default: + EC_SLAVE_DBG(slave, 1, "Unknown category type 0x%04X.\n", + cat_type); + } + + cat_word += cat_size; + if (cat_word - slave->sii_words >= slave->sii_nwords) { + EC_SLAVE_WARN(slave, "Unexpected end of SII data:" + " Next category header missing.\n"); + goto end; + } + } + +#ifdef EC_REGALIAS + ec_fsm_slave_scan_enter_regalias(fsm); +#else + if (slave->sii.mailbox_protocols & EC_MBOX_COE) { + ec_fsm_slave_scan_enter_preop(fsm); + } else { + fsm->state = ec_fsm_slave_scan_state_end; + } +#endif + return; + +end: + EC_SLAVE_ERR(slave, "Failed to analyze category data.\n"); + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; +} + +/****************************************************************************/ + +#ifdef EC_REGALIAS + +/** Slave scan entry function: REGALIAS. + */ +void ec_fsm_slave_scan_enter_regalias( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + // read alias from register + EC_SLAVE_DBG(slave, 1, "Reading alias from register.\n"); + ec_datagram_fprd(datagram, slave->station_address, 0x0012, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_regalias; +} + +/****************************************************************************/ + +/** Slave scan state: REGALIAS. + */ +void ec_fsm_slave_scan_state_regalias( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive register alias datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_DBG(slave, 1, "Failed to read register alias.\n"); + } else { + slave->effective_alias = EC_READ_U16(datagram->data); + EC_SLAVE_DBG(slave, 1, "Read alias %u from register.\n", + slave->effective_alias); + } + + if (slave->sii.mailbox_protocols & EC_MBOX_COE) { + ec_fsm_slave_scan_enter_preop(fsm); + } else { + fsm->state = ec_fsm_slave_scan_state_end; + } +} + +#endif // defined EC_REGALIAS + +/****************************************************************************/ + +/** Enter slave scan state PREOP. + */ +void ec_fsm_slave_scan_enter_preop( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t current_state = slave->current_state & EC_SLAVE_STATE_MASK; + + if (current_state != EC_SLAVE_STATE_PREOP + && current_state != EC_SLAVE_STATE_SAFEOP + && current_state != EC_SLAVE_STATE_OP) { + if (slave->master->debug_level) { + char str[EC_STATE_STRING_SIZE]; + ec_state_string(current_state, str, 0); + EC_SLAVE_DBG(slave, 0, "Slave is not in the state" + " to do mailbox com (%s), setting to PREOP.\n", str); + } + + fsm->state = ec_fsm_slave_scan_state_preop; + ec_slave_request_state(slave, EC_SLAVE_STATE_PREOP); + ec_fsm_slave_config_start(fsm->fsm_slave_config, slave); + ec_fsm_slave_config_exec(fsm->fsm_slave_config); + } else { + EC_SLAVE_DBG(slave, 1, "Reading mailbox" + " sync manager configuration.\n"); + + /* Scan current sync manager configuration to get configured mailbox + * sizes. */ + ec_datagram_fprd(fsm->datagram, slave->station_address, 0x0800, + EC_SYNC_PAGE_SIZE * 2); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_sync; + } +} + +/****************************************************************************/ + +/** Slave scan state: PREOP. + */ +void ec_fsm_slave_scan_state_preop( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + if (ec_fsm_slave_config_exec(fsm->fsm_slave_config)) + return; + + if (!ec_fsm_slave_config_success(fsm->fsm_slave_config)) { + fsm->state = ec_fsm_slave_scan_state_error; + return; + } + + ec_fsm_slave_scan_enter_pdos(fsm); +} + +/****************************************************************************/ + +/** Slave scan state: SYNC. + */ +void ec_fsm_slave_scan_state_sync( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + uint16_t tx_offset, tx_size, rx_offset, rx_size; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive sync manager" + " configuration datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to read DL status: "); + ec_datagram_print_wc_error(datagram); + return; + } + + rx_offset = EC_READ_U16(datagram->data); + rx_size = EC_READ_U16(datagram->data + 2); + tx_offset = EC_READ_U16(datagram->data + 8); + tx_size = EC_READ_U16(datagram->data + 10); + + if (rx_size == 0xffff) { + fsm->state = ec_fsm_slave_scan_state_error; + slave->sii.mailbox_protocols = 0x0000; + EC_SLAVE_ERR(slave, "Invalid RX mailbox size (%u) configured." + " Disabling mailbox communication.", rx_size); + return; + } + + if (tx_size == 0xffff) { + fsm->state = ec_fsm_slave_scan_state_error; + slave->sii.mailbox_protocols = 0x0000; + EC_SLAVE_ERR(slave, "Invalid TX mailbox size (%u) configured." + " Disabling mailbox communication.", tx_size); + return; + } + + slave->configured_rx_mailbox_offset = rx_offset; + slave->configured_rx_mailbox_size = rx_size; + slave->configured_tx_mailbox_offset = tx_offset; + slave->configured_tx_mailbox_size = tx_size; + + EC_SLAVE_DBG(slave, 1, "Mailbox configuration:\n"); + EC_SLAVE_DBG(slave, 1, " RX offset=0x%04x size=%u\n", + slave->configured_rx_mailbox_offset, + slave->configured_rx_mailbox_size); + EC_SLAVE_DBG(slave, 1, " TX offset=0x%04x size=%u\n", + slave->configured_tx_mailbox_offset, + slave->configured_tx_mailbox_size); + + ec_fsm_slave_scan_enter_pdos(fsm); +} + +/****************************************************************************/ + +/** Enter slave scan state PDOS. + */ +void ec_fsm_slave_scan_enter_pdos( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + EC_SLAVE_DBG(slave, 1, "Scanning PDO assignment and mapping.\n"); + fsm->state = ec_fsm_slave_scan_state_pdos; + ec_fsm_pdo_start_reading(fsm->fsm_pdo, slave); + ec_fsm_pdo_exec(fsm->fsm_pdo, fsm->datagram); // execute immediately +} + +/****************************************************************************/ + +/** Slave scan state: PDOS. + */ +void ec_fsm_slave_scan_state_pdos( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + if (ec_fsm_pdo_exec(fsm->fsm_pdo, fsm->datagram)) { + return; + } + + if (!ec_fsm_pdo_success(fsm->fsm_pdo)) { + fsm->state = ec_fsm_slave_scan_state_error; + return; + } + + // reading PDO configuration finished + fsm->state = ec_fsm_slave_scan_state_end; +} + +/***************************************************************************** + * Common state functions + ****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_slave_scan_state_error( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_slave_scan_state_end( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_slave_scan.h b/ubuntu/igh-ecat/master/fsm_slave_scan.h new file mode 100644 index 00000000000000..72c8a39ace1490 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_slave_scan.h @@ -0,0 +1,75 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave scanning state machine. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_SLAVE_SCAN_H__ +#define __EC_FSM_SLAVE_SCAN_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" +#include "fsm_sii.h" +#include "fsm_change.h" +#include "fsm_coe.h" +#include "fsm_pdo.h" + +/****************************************************************************/ + +/** \see ec_fsm_slave_scan */ +typedef struct ec_fsm_slave_scan ec_fsm_slave_scan_t; + +/** Finite state machine for scanning an EtherCAT slave. + */ +struct ec_fsm_slave_scan +{ + ec_slave_t *slave; /**< Slave the FSM runs on. */ + ec_datagram_t *datagram; /**< Datagram used in the state machine. */ + ec_fsm_slave_config_t *fsm_slave_config; /**< Slave configuration state + machine to use. */ + ec_fsm_pdo_t *fsm_pdo; /**< PDO configuration state machine to use. */ + unsigned int retries; /**< Retries on datagram timeout. */ + + void (*state)(ec_fsm_slave_scan_t *); /**< State function. */ + uint16_t sii_offset; /**< SII offset in words. */ + + ec_fsm_sii_t fsm_sii; /**< SII state machine. */ +}; + +/****************************************************************************/ + +void ec_fsm_slave_scan_init(ec_fsm_slave_scan_t *, ec_datagram_t *, + ec_fsm_slave_config_t *, ec_fsm_pdo_t *); +void ec_fsm_slave_scan_clear(ec_fsm_slave_scan_t *); + +void ec_fsm_slave_scan_start(ec_fsm_slave_scan_t *, ec_slave_t *); + +int ec_fsm_slave_scan_exec(ec_fsm_slave_scan_t *); +int ec_fsm_slave_scan_success(const ec_fsm_slave_scan_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/fsm_soe.c b/ubuntu/igh-ecat/master/fsm_soe.c new file mode 100644 index 00000000000000..b24f03a9417b88 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_soe.c @@ -0,0 +1,844 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2020 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT SoE state machines. +*/ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "fsm_soe.h" + +/****************************************************************************/ + +/** SoE operations + */ +enum { + OPCODE_READ_REQUEST = 0x01, /**< Read request. */ + OPCODE_READ_RESPONSE = 0x02, /**< Read response. */ + OPCODE_WRITE_REQUEST = 0x03, /**< Write request. */ + OPCODE_WRITE_RESPONSE = 0x04 /**< Write response. */ +}; + +/** Size of all SoE headers. + */ +#define EC_SOE_SIZE 0x04 + +/** SoE header size. + */ +#define EC_SOE_HEADER_SIZE (EC_MBOX_HEADER_SIZE + EC_SOE_SIZE) + +/** SoE response timeout [ms]. + */ +#define EC_SOE_RESPONSE_TIMEOUT 1000 + +/****************************************************************************/ + +// prototypes for private methods +void ec_print_soe_error(const ec_slave_t *, uint16_t); +void ec_fsm_soe_print_error(ec_fsm_soe_t *); +int ec_fsm_soe_prepare_read(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_write_next_fragment(ec_fsm_soe_t *, ec_datagram_t *); + +/****************************************************************************/ + +void ec_fsm_soe_read_start(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_read_request(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_read_check(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_read_response(ec_fsm_soe_t *, ec_datagram_t *); + +void ec_fsm_soe_write_start(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_write_request(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_write_check(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_write_response(ec_fsm_soe_t *, ec_datagram_t *); + +void ec_fsm_soe_end(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_error(ec_fsm_soe_t *, ec_datagram_t *); + +/****************************************************************************/ + +extern const ec_code_msg_t soe_error_codes[]; + +/****************************************************************************/ + +/** Outputs an SoE error code. +*/ +void ec_print_soe_error(const ec_slave_t *slave, uint16_t error_code) +{ + const ec_code_msg_t *error_msg; + + for (error_msg = soe_error_codes; error_msg->code; error_msg++) { + if (error_msg->code == error_code) { + EC_SLAVE_ERR(slave, "SoE error 0x%04X: \"%s\".\n", + error_msg->code, error_msg->message); + return; + } + } + + EC_SLAVE_ERR(slave, "Unknown SoE error 0x%04X.\n", error_code); +} + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_soe_init( + ec_fsm_soe_t *fsm /**< finite state machine */ + ) +{ + fsm->state = NULL; + fsm->datagram = NULL; + fsm->fragment_size = 0; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_soe_clear( + ec_fsm_soe_t *fsm /**< finite state machine */ + ) +{ +} + +/****************************************************************************/ + +/** Starts to transfer an IDN to/from a slave. + */ +void ec_fsm_soe_transfer( + ec_fsm_soe_t *fsm, /**< State machine. */ + ec_slave_t *slave, /**< EtherCAT slave. */ + ec_soe_request_t *request /**< SoE request. */ + ) +{ + fsm->slave = slave; + fsm->request = request; + + if (request->dir == EC_DIR_OUTPUT) { + fsm->state = ec_fsm_soe_write_start; + } else { + fsm->state = ec_fsm_soe_read_start; + } +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * \return 1 if the datagram was used, else 0. + */ +int ec_fsm_soe_exec( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + int datagram_used = 0; + + if (fsm->datagram && + (fsm->datagram->state == EC_DATAGRAM_INIT || + fsm->datagram->state == EC_DATAGRAM_QUEUED || + fsm->datagram->state == EC_DATAGRAM_SENT)) { + // datagram not received yet + return datagram_used; + } + + fsm->state(fsm, datagram); + + datagram_used = + fsm->state != ec_fsm_soe_end && fsm->state != ec_fsm_soe_error; + + if (datagram_used) { + fsm->datagram = datagram; + } else { + fsm->datagram = NULL; + } + + return datagram_used; +} + +/****************************************************************************/ + +/** Returns, if the state machine terminated with success. + * + * \return non-zero if successful. + */ +int ec_fsm_soe_success(const ec_fsm_soe_t *fsm /**< Finite state machine */) +{ + return fsm->state == ec_fsm_soe_end; +} + +/****************************************************************************/ + +/** Output information about a failed SoE transfer. + */ +void ec_fsm_soe_print_error(ec_fsm_soe_t *fsm /**< Finite state machine */) +{ + ec_soe_request_t *request = fsm->request; + + EC_SLAVE_ERR(fsm->slave, ""); + + if (request->dir == EC_DIR_OUTPUT) { + printk(KERN_CONT "Writing"); + } else { + printk(KERN_CONT "Reading"); + } + + printk(KERN_CONT " IDN 0x%04X failed.\n", request->idn); +} + +/***************************************************************************** + * SoE read state machine + ****************************************************************************/ + +/** Prepare a read operation. + * + * \return 0 on success, otherwise a negative error code. + */ +int ec_fsm_soe_prepare_read( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + uint8_t *data; + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + ec_soe_request_t *request = fsm->request; + + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_SOE, + EC_SOE_SIZE); + if (IS_ERR(data)) { + return PTR_ERR(data); + } + + EC_WRITE_U8(data, OPCODE_READ_REQUEST | (request->drive_no & 0x07) << 5); + EC_WRITE_U8(data + 1, 1 << 6); // request value + EC_WRITE_U16(data + 2, request->idn); + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "SSC read request:\n"); + ec_print_data(data, EC_SOE_SIZE); + } + + fsm->request->jiffies_sent = jiffies; + fsm->state = ec_fsm_soe_read_request; + + return 0; +} + +/****************************************************************************/ + +/** SoE state: READ START. + */ +void ec_fsm_soe_read_start( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *request = fsm->request; + + EC_SLAVE_DBG(slave, 1, "Reading IDN 0x%04X of drive %u.\n", request->idn, + request->drive_no); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_SOE)) { + EC_SLAVE_ERR(slave, "Slave does not support SoE!\n"); + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + request->data_size = 0; + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_soe_prepare_read(fsm, datagram)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + } +} + +/****************************************************************************/ + +/** SoE state: READ REQUEST. + */ +void ec_fsm_soe_read_request( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + unsigned long diff_ms; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_soe_prepare_read(fsm, datagram)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE read request: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + diff_ms = (jiffies - fsm->request->jiffies_sent) * 1000 / HZ; + + if (fsm->datagram->working_counter != 1) { + if (!fsm->datagram->working_counter) { + if (diff_ms < EC_SOE_RESPONSE_TIMEOUT) { + // no response; send request datagram again + if (ec_fsm_soe_prepare_read(fsm, datagram)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + } + return; + } + } + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE read request" + " failed after %lu ms: ", diff_ms); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_soe_read_check; +} + +/****************************************************************************/ + +/** CoE state: READ CHECK. + */ +void ec_fsm_soe_read_check( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= EC_SOE_RESPONSE_TIMEOUT) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Timeout after %lu ms while waiting for" + " read response.\n", diff_ms); + ec_fsm_soe_print_error(fsm); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_soe_read_response; +} + +/****************************************************************************/ + +/** SoE state: READ RESPONSE. + */ +void ec_fsm_soe_read_response( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + uint8_t *data, mbox_prot, header, opcode, incomplete, error_flag, + value_included; + size_t rec_size, data_size; + ec_soe_request_t *req = fsm->request; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE read response datagram: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE read response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "SSC read response:\n"); + ec_print_data(data, rec_size); + } + + if (mbox_prot != EC_MBOX_TYPE_SOE) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + ec_fsm_soe_print_error(fsm); + return; + } + + if (rec_size < EC_SOE_SIZE) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Received currupted SoE read response" + " (%zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + return; + } + + header = EC_READ_U8(data); + opcode = header & 0x7; + incomplete = (header >> 3) & 1; + error_flag = (header >> 4) & 1; + + if (opcode != OPCODE_READ_RESPONSE) { + EC_SLAVE_ERR(slave, "Received no read response (opcode %x).\n", + opcode); + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + return; + } + + if (error_flag) { + req->error_code = EC_READ_U16(data + rec_size - 2); + EC_SLAVE_ERR(slave, "Received error response:\n"); + ec_print_soe_error(slave, req->error_code); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + return; + } else { + req->error_code = 0x0000; + } + + value_included = (EC_READ_U8(data + 1) >> 6) & 1; + if (!value_included) { + EC_SLAVE_ERR(slave, "No value included!\n"); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + return; + } + + data_size = rec_size - EC_SOE_SIZE; + if (ec_soe_request_append_data(req, + data + EC_SOE_SIZE, data_size)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + if (incomplete) { + EC_SLAVE_DBG(slave, 1, "SoE data incomplete. Waiting for fragment" + " at offset %zu.\n", req->data_size); + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_soe_read_check; + } else { + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "IDN data:\n"); + ec_print_data(req->data, req->data_size); + } + + fsm->state = ec_fsm_soe_end; // success + } +} + +/***************************************************************************** + * SoE write state machine + ****************************************************************************/ + +/** Write next fragment. + */ +void ec_fsm_soe_write_next_fragment( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + ec_soe_request_t *req = fsm->request; + uint8_t incomplete, *data; + size_t max_fragment_size, remaining_size; + uint16_t fragments_left; + + remaining_size = req->data_size - fsm->offset; + max_fragment_size = slave->configured_rx_mailbox_size - EC_SOE_HEADER_SIZE; + incomplete = remaining_size > max_fragment_size; + fsm->fragment_size = incomplete ? max_fragment_size : remaining_size; + fragments_left = remaining_size / fsm->fragment_size - 1; + if (remaining_size % fsm->fragment_size) { + fragments_left++; + } + + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_SOE, + EC_SOE_SIZE + fsm->fragment_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + EC_WRITE_U8(data, OPCODE_WRITE_REQUEST | incomplete << 3 | + (req->drive_no & 0x07) << 5); + EC_WRITE_U8(data + 1, 1 << 6); // only value included + EC_WRITE_U16(data + 2, incomplete ? fragments_left : req->idn); + memcpy(data + EC_SOE_SIZE, req->data + fsm->offset, fsm->fragment_size); + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "SSC write request:\n"); + ec_print_data(data, EC_SOE_SIZE + fsm->fragment_size); + } + + fsm->state = ec_fsm_soe_write_request; +} + +/****************************************************************************/ + +/** SoE state: WRITE START. + */ +void ec_fsm_soe_write_start( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *req = fsm->request; + + EC_SLAVE_DBG(slave, 1, "Writing IDN 0x%04X of drive %u (%zu byte).\n", + req->idn, req->drive_no, req->data_size); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_SOE)) { + EC_SLAVE_ERR(slave, "Slave does not support SoE!\n"); + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + if (slave->configured_rx_mailbox_size <= EC_SOE_HEADER_SIZE) { + EC_SLAVE_ERR(slave, "Mailbox size (%u) too small for SoE write.\n", + slave->configured_rx_mailbox_size); + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + fsm->offset = 0; + fsm->retries = EC_FSM_RETRIES; + ec_fsm_soe_write_next_fragment(fsm, datagram); + req->jiffies_sent = jiffies; +} + +/****************************************************************************/ + +/** SoE state: WRITE REQUEST. + */ +void ec_fsm_soe_write_request( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + unsigned long diff_ms; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_fsm_soe_write_next_fragment(fsm, datagram); + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE write request: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + diff_ms = (jiffies - fsm->request->jiffies_sent) * 1000 / HZ; + + if (fsm->datagram->working_counter != 1) { + if (!fsm->datagram->working_counter) { + if (diff_ms < EC_SOE_RESPONSE_TIMEOUT) { + // no response; send request datagram again + ec_fsm_soe_write_next_fragment(fsm, datagram); + return; + } + } + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE write request" + " failed after %lu ms: ", diff_ms); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + // fragment successfully sent + fsm->offset += fsm->fragment_size; + + if (fsm->offset < fsm->request->data_size) { + // next fragment + fsm->retries = EC_FSM_RETRIES; + ec_fsm_soe_write_next_fragment(fsm, datagram); + fsm->request->jiffies_sent = jiffies; + } else { + // all fragments sent; query response + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_soe_write_check; + } +} + +/****************************************************************************/ + +/** CoE state: WRITE CHECK. + */ +void ec_fsm_soe_write_check( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE write request datagram: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE write request datagram: "); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (datagram->jiffies_received - fsm->jiffies_start) * 1000 / HZ; + if (diff_ms >= EC_SOE_RESPONSE_TIMEOUT) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Timeout after %lu ms while waiting" + " for write response.\n", diff_ms); + ec_fsm_soe_print_error(fsm); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_soe_write_response; +} + +/****************************************************************************/ + +/** SoE state: WRITE RESPONSE. + */ +void ec_fsm_soe_write_response( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + ec_soe_request_t *req = fsm->request; + uint8_t *data, mbox_prot, opcode, error_flag; + uint16_t idn; + size_t rec_size; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; // FIXME: request again? + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE write" + " response datagram: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE write response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "SSC write response:\n"); + ec_print_data(data, rec_size); + } + + if (mbox_prot != EC_MBOX_TYPE_SOE) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + ec_fsm_soe_print_error(fsm); + return; + } + + if (rec_size < EC_SOE_SIZE) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Received corrupted SoE write response" + " (%zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + return; + } + + opcode = EC_READ_U8(data) & 0x7; + if (opcode != OPCODE_WRITE_RESPONSE) { + EC_SLAVE_ERR(slave, "Received no write response" + " (opcode %x).\n", opcode); + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + return; + } + + idn = EC_READ_U16(data + 2); + if (idn != req->idn) { + EC_SLAVE_ERR(slave, "Received response for" + " wrong IDN 0x%04x.\n", idn); + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + return; + } + + error_flag = (EC_READ_U8(data) >> 4) & 1; + if (error_flag) { + if (rec_size < EC_SOE_SIZE + 2) { + EC_SLAVE_ERR(slave, "Received corrupted error response" + " - error flag set, but received size is %zu.\n", + rec_size); + } else { + req->error_code = EC_READ_U16(data + EC_SOE_SIZE); + EC_SLAVE_ERR(slave, "Received error response:\n"); + ec_print_soe_error(slave, req->error_code); + } + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + } else { + req->error_code = 0x0000; + fsm->state = ec_fsm_soe_end; // success + } +} + +/****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_soe_error( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_soe_end( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/fsm_soe.h b/ubuntu/igh-ecat/master/fsm_soe.h new file mode 100644 index 00000000000000..b99253d8d16c64 --- /dev/null +++ b/ubuntu/igh-ecat/master/fsm_soe.h @@ -0,0 +1,67 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CoE state machines. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_SOE_H__ +#define __EC_FSM_SOE_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" +#include "soe_request.h" + +/****************************************************************************/ + +typedef struct ec_fsm_soe ec_fsm_soe_t; /**< \see ec_fsm_soe */ + +/** Finite state machines for the Sercos over EtherCAT protocol. + */ +struct ec_fsm_soe { + ec_slave_t *slave; /**< slave the FSM runs on */ + unsigned int retries; /**< retries upon datagram timeout */ + + void (*state)(ec_fsm_soe_t *, ec_datagram_t *); /**< CoE state function */ + ec_datagram_t *datagram; /**< Datagram used in the previous step. */ + unsigned long jiffies_start; /**< Timestamp. */ + ec_soe_request_t *request; /**< SoE request */ + off_t offset; /**< IDN data offset during fragmented write. */ + size_t fragment_size; /**< Size of the current fragment. */ +}; + +/****************************************************************************/ + +void ec_fsm_soe_init(ec_fsm_soe_t *); +void ec_fsm_soe_clear(ec_fsm_soe_t *); + +void ec_fsm_soe_transfer(ec_fsm_soe_t *, ec_slave_t *, ec_soe_request_t *); + +int ec_fsm_soe_exec(ec_fsm_soe_t *, ec_datagram_t *); +int ec_fsm_soe_success(const ec_fsm_soe_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/globals.h b/ubuntu/igh-ecat/master/globals.h new file mode 100644 index 00000000000000..da738e8b77e04f --- /dev/null +++ b/ubuntu/igh-ecat/master/globals.h @@ -0,0 +1,314 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2021 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT master. + * + * The file is free software; you can redistribute it and/or modify it under + * the terms of the GNU Lesser General Public License as published by the + * Free Software Foundation; version 2.1 of the License. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + * License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this file. If not, see . + * + ****************************************************************************/ + +/** \file + * Global definitions and macros. + */ + +/****************************************************************************/ + +#ifndef __EC_MASTER_GLOBALS_H__ +#define __EC_MASTER_GLOBALS_H__ + +#include "../globals.h" +#include "../include/ecrt.h" + +/***************************************************************************** + * EtherCAT master + ****************************************************************************/ + +/** Datagram timeout in microseconds. */ +#define EC_IO_TIMEOUT 500 + +/** Time to send a byte in nanoseconds. + * + * t_ns = 1 / (100 MBit/s / 8 bit/byte) = 80 ns/byte + */ +#define EC_BYTE_TRANSMISSION_TIME_NS 80 + +/** Number of state machine retries on datagram timeout. */ +#define EC_FSM_RETRIES 3 + +/** Seconds to wait before fetching SDO dictionary + after slave entered PREOP state. */ +#define EC_WAIT_SDO_DICT 3 + +/** Minimum size of a buffer used with ec_state_string(). */ +#define EC_STATE_STRING_SIZE 32 + +/** Maximum SII size in words, to avoid infinite reading. */ +#define EC_MAX_SII_SIZE 4096 + +/** Number of statistic rate intervals to maintain. */ +#define EC_RATE_COUNT 3 + +/***************************************************************************** + * EtherCAT protocol + ****************************************************************************/ + +/** Size of an EtherCAT frame header. */ +#define EC_FRAME_HEADER_SIZE 2 + +/** Size of an EtherCAT datagram header. */ +#define EC_DATAGRAM_HEADER_SIZE 10 + +/** Size of an EtherCAT datagram footer. */ +#define EC_DATAGRAM_FOOTER_SIZE 2 + +/** Size of the EtherCAT address field. */ +#define EC_ADDR_LEN 4 + +/** Resulting maximum data size of a single datagram in a frame. */ +#define EC_MAX_DATA_SIZE (ETH_DATA_LEN - EC_FRAME_HEADER_SIZE \ + - EC_DATAGRAM_HEADER_SIZE - EC_DATAGRAM_FOOTER_SIZE) + +/** Mailbox header size. */ +#define EC_MBOX_HEADER_SIZE 6 + +/** Word offset of first SII category. */ +#define EC_FIRST_SII_CATEGORY_OFFSET 0x40 + +/** Size of a sync manager configuration page. */ +#define EC_SYNC_PAGE_SIZE 8 + +/** Maximum number of FMMUs per slave. */ +#define EC_MAX_FMMUS 16 + +/** Size of an FMMU configuration page. */ +#define EC_FMMU_PAGE_SIZE 16 + +/** Number of DC sync signals. */ +#define EC_SYNC_SIGNAL_COUNT 2 + +/** Size of the datagram description string. + * + * This is also used as the maximum lenth of EoE device names. + **/ +#define EC_DATAGRAM_NAME_SIZE 20 + +/** Maximum hostname size. + * + * Used inside the EoE set IP parameter request. + */ +#define EC_MAX_HOSTNAME_SIZE 32 + +/** Slave state mask. + * + * Apply this mask to a slave state byte to get the slave state without + * the error flag. + */ +#define EC_SLAVE_STATE_MASK 0x0F + +/** State of an EtherCAT slave. + */ +typedef enum { + EC_SLAVE_STATE_UNKNOWN = 0x00, + /**< unknown state */ + EC_SLAVE_STATE_INIT = 0x01, + /**< INIT state (no mailbox communication, no IO) */ + EC_SLAVE_STATE_PREOP = 0x02, + /**< PREOP state (mailbox communication, no IO) */ + EC_SLAVE_STATE_BOOT = 0x03, + /**< Bootstrap state (mailbox communication, firmware update) */ + EC_SLAVE_STATE_SAFEOP = 0x04, + /**< SAFEOP (mailbox communication and input update) */ + EC_SLAVE_STATE_OP = 0x08, + /**< OP (mailbox communication and input/output update) */ + EC_SLAVE_STATE_ACK_ERR = 0x10 + /**< Acknowledge/Error bit (no actual state) */ +} ec_slave_state_t; + +/** Supported mailbox protocols. + * + * Not to mix up with the mailbox type field in the mailbox header defined in + * master/mailbox.h. + */ +enum { + EC_MBOX_AOE = 0x01, /**< ADS over EtherCAT */ + EC_MBOX_EOE = 0x02, /**< Ethernet over EtherCAT */ + EC_MBOX_COE = 0x04, /**< CANopen over EtherCAT */ + EC_MBOX_FOE = 0x08, /**< File-Access over EtherCAT */ + EC_MBOX_SOE = 0x10, /**< Servo-Profile over EtherCAT */ + EC_MBOX_VOE = 0x20 /**< Vendor specific */ +}; + +/** Slave information interface CANopen over EtherCAT details flags. + */ +typedef struct { + uint8_t enable_sdo : 1; /**< Enable SDO access. */ + uint8_t enable_sdo_info : 1; /**< SDO information service available. */ + uint8_t enable_pdo_assign : 1; /**< PDO mapping configurable. */ + uint8_t enable_pdo_configuration : 1; /**< PDO configuration possible. */ + uint8_t enable_upload_at_startup : 1; /**< ?. */ + uint8_t enable_sdo_complete_access : 1; /**< Complete access possible. */ +} ec_sii_coe_details_t; + +/** Slave information interface general flags. + */ +typedef struct { + uint8_t enable_safeop : 1; /**< ?. */ + uint8_t enable_not_lrw : 1; /**< Slave does not support LRW. */ +} ec_sii_general_flags_t; + +/** EtherCAT slave distributed clocks range. + */ +typedef enum { + EC_DC_32, /**< 32 bit. */ + EC_DC_64 /*< 64 bit for system time, system time offset and + port 0 receive time. */ +} ec_slave_dc_range_t; + +/** EtherCAT slave sync signal configuration. + */ +typedef struct { + uint32_t cycle_time; /**< Cycle time [ns]. */ + int32_t shift_time; /**< Shift time [ns]. */ +} ec_sync_signal_t; + +/** Access states for SDO entries. + * + * The access rights are managed per AL state. + */ +enum { + EC_SDO_ENTRY_ACCESS_PREOP, /**< Access rights in PREOP. */ + EC_SDO_ENTRY_ACCESS_SAFEOP, /**< Access rights in SAFEOP. */ + EC_SDO_ENTRY_ACCESS_OP, /**< Access rights in OP. */ + EC_SDO_ENTRY_ACCESS_COUNT /**< Number of states. */ +}; + +/** Master devices. + */ +typedef enum { + EC_DEVICE_MAIN, /**< Main device. */ + EC_DEVICE_BACKUP /**< Backup device */ +} ec_device_index_t; + +extern const char *ec_device_names[2]; // only main and backup! + +/****************************************************************************/ + +/** Convenience macro for printing EtherCAT-specific information to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT: ". + * + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_INFO(fmt, args...) \ + printk(KERN_INFO "EtherCAT: " fmt, ##args) + +/** Convenience macro for printing EtherCAT-specific errors to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT ERROR: ". + * + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_ERR(fmt, args...) \ + printk(KERN_ERR "EtherCAT ERROR: " fmt, ##args) + +/** Convenience macro for printing EtherCAT-specific warnings to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT WARNING: ". + * + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_WARN(fmt, args...) \ + printk(KERN_WARNING "EtherCAT WARNING: " fmt, ##args) + +/** Convenience macro for printing EtherCAT debug messages to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT DEBUG: ". + * + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_DBG(fmt, args...) \ + printk(KERN_DEBUG "EtherCAT DEBUG: " fmt, ##args) + +/****************************************************************************/ + +/** Absolute value. + */ +#define EC_ABS(X) ((X) >= 0 ? (X) : -(X)) + +/****************************************************************************/ + +extern char *ec_master_version_str; + +/****************************************************************************/ + +unsigned int ec_master_count(void); +void ec_print_data(const uint8_t *, size_t); +void ec_print_data_diff(const uint8_t *, const uint8_t *, size_t); +size_t ec_state_string(uint8_t, char *, uint8_t); +ssize_t ec_mac_print(const uint8_t *, char *); +int ec_mac_is_zero(const uint8_t *); + +ec_master_t *ecrt_request_master_err(unsigned int); + +/****************************************************************************/ + +/** Code/Message pair. + * + * Some EtherCAT datagrams support reading a status code to display a certain + * message. This type allows to map a code to a message string. + */ +typedef struct { + uint32_t code; /**< Code. */ + const char *message; /**< Message belonging to \a code. */ +} ec_code_msg_t; + +/****************************************************************************/ + +/** Generic request state. + * + * \attention If ever changing this, please be sure to adjust the \a + * state_table in master/sdo_request.c. + */ +typedef enum { + EC_INT_REQUEST_INIT, + EC_INT_REQUEST_QUEUED, + EC_INT_REQUEST_BUSY, + EC_INT_REQUEST_SUCCESS, + EC_INT_REQUEST_FAILURE +} ec_internal_request_state_t; + +/****************************************************************************/ + +extern const ec_request_state_t ec_request_state_translation_table[]; + +/****************************************************************************/ + +/** Origin type. + */ +typedef enum { + EC_ORIG_INTERNAL, /**< Internal. */ + EC_ORIG_EXTERNAL /**< External. */ +} ec_origin_t; + +/****************************************************************************/ + +typedef struct ec_slave ec_slave_t; /**< \see ec_slave. */ + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/ioctl.c b/ubuntu/igh-ecat/master/ioctl.c new file mode 100644 index 00000000000000..051e520f9e0eeb --- /dev/null +++ b/ubuntu/igh-ecat/master/ioctl.c @@ -0,0 +1,5591 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + \file + EtherCAT master character device. +*/ + +/****************************************************************************/ + +#include +#include + +#include "master.h" +#include "slave_config.h" +#include "voe_handler.h" +#include "ethernet.h" +#include "ioctl.h" + +/** Set to 1 to enable ioctl() latency tracing. + * + * Requires CPU timestamp counter! + */ +#define DEBUG_LATENCY 0 + +/** Optional compiler attributes fo ioctl() functions. + */ +#if 0 +#define ATTRIBUTES __attribute__ ((__noinline__)) +#else +#define ATTRIBUTES +#endif + +#ifdef EC_IOCTL_RTDM +# include "rtdm_details.h" +/* RTDM does not support locking yet, + * therefore no send/receive callbacks are set too. */ +# define ec_ioctl_lock(lock) do {} while(0) +# define ec_ioctl_unlock(lock) do {} while(0) +# define ec_ioctl_lock_interruptible(lock) (0) +# define ec_copy_to_user(to, from, n, ctx) \ + rtdm_safe_copy_to_user(ec_ioctl_to_rtdm(ctx), to, from, n) +# define ec_copy_from_user(to, from, n, ctx) \ + rtdm_safe_copy_from_user(ec_ioctl_to_rtdm(ctx), to, from, n) +#else +# define ec_ioctl_lock(lock) rt_mutex_lock(lock) +# define ec_ioctl_unlock(lock) rt_mutex_unlock(lock) +# if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) || \ + (defined(CONFIG_PREEMPT_RT_FULL) && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) +# define ec_ioctl_lock_interruptible(lock) \ + rt_mutex_lock_interruptible(lock) +# else +# define ec_ioctl_lock_interruptible(lock) \ + rt_mutex_lock_interruptible(lock, 0) +# endif +# define ec_copy_to_user(to, from, n, ctx) copy_to_user(to, from, n) +# define ec_copy_from_user(to, from, n, ctx) copy_from_user(to, from, n) +#endif // EC_IOCTL_RTDM + +/****************************************************************************/ + +/** Copies a string to an ioctl structure. + */ +static void ec_ioctl_strcpy( + char *target, /**< Target. */ + const char *source /**< Source. */ + ) +{ + if (source) { + strscpy(target, source, EC_IOCTL_STRING_SIZE); + target[EC_IOCTL_STRING_SIZE - 1] = 0; + } else { + target[0] = 0; + } +} + +/****************************************************************************/ + +/** Get module information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_module( + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_module_t data; + + data.ioctl_version_magic = EC_IOCTL_VERSION_MAGIC; + data.master_count = ec_master_count(); + + if (ec_copy_to_user((void __user *) arg, &data, sizeof(data), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get master information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_master( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_master_t io; + unsigned int dev_idx, j; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + io.slave_count = master->slave_count; + io.scan_index = master->scan_index; + io.config_count = ec_master_config_count(master); + io.domain_count = ec_master_domain_count(master); +#ifdef EC_EOE + io.eoe_handler_count = ec_master_eoe_handler_count(master); +#else + io.eoe_handler_count = 0; +#endif + io.phase = (uint8_t) master->phase; + io.active = (uint8_t) master->active; + io.scan_busy = master->scan_busy; + + up(&master->master_sem); + + if (down_interruptible(&master->device_sem)) { + return -EINTR; + } + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(master); dev_idx++) { + ec_device_t *device = &master->devices[dev_idx]; + + if (device->dev) { + memcpy(io.devices[dev_idx].address, device->dev->dev_addr, + ETH_ALEN); + } else { + memcpy(io.devices[dev_idx].address, master->macs[dev_idx], + ETH_ALEN); + } + io.devices[dev_idx].attached = device->dev ? 1 : 0; + io.devices[dev_idx].link_state = device->link_state ? 1 : 0; + io.devices[dev_idx].tx_count = device->tx_count; + io.devices[dev_idx].rx_count = device->rx_count; + io.devices[dev_idx].tx_bytes = device->tx_bytes; + io.devices[dev_idx].rx_bytes = device->rx_bytes; + io.devices[dev_idx].tx_errors = device->tx_errors; + for (j = 0; j < EC_RATE_COUNT; j++) { + io.devices[dev_idx].tx_frame_rates[j] = + device->tx_frame_rates[j]; + io.devices[dev_idx].rx_frame_rates[j] = + device->rx_frame_rates[j]; + io.devices[dev_idx].tx_byte_rates[j] = + device->tx_byte_rates[j]; + io.devices[dev_idx].rx_byte_rates[j] = + device->rx_byte_rates[j]; + } + } + io.num_devices = ec_master_num_devices(master); + + io.tx_count = master->device_stats.tx_count; + io.rx_count = master->device_stats.rx_count; + io.tx_bytes = master->device_stats.tx_bytes; + io.rx_bytes = master->device_stats.rx_bytes; + for (j = 0; j < EC_RATE_COUNT; j++) { + io.tx_frame_rates[j] = + master->device_stats.tx_frame_rates[j]; + io.rx_frame_rates[j] = + master->device_stats.rx_frame_rates[j]; + io.tx_byte_rates[j] = + master->device_stats.tx_byte_rates[j]; + io.rx_byte_rates[j] = + master->device_stats.rx_byte_rates[j]; + io.loss_rates[j] = + master->device_stats.loss_rates[j]; + } + + up(&master->device_sem); + + io.app_time = master->app_time; + io.dc_ref_time = master->dc_ref_time; + io.ref_clock = + master->dc_ref_clock ? master->dc_ref_clock->ring_position : 0xffff; + + if (copy_to_user((void __user *) arg, &io, sizeof(io))) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Get slave information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_slave_t data; + const ec_slave_t *slave; + int i; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", data.position); + return -EINVAL; + } + + data.device_index = slave->device_index; + data.vendor_id = slave->sii.vendor_id; + data.product_code = slave->sii.product_code; + data.revision_number = slave->sii.revision_number; + data.serial_number = slave->sii.serial_number; + data.alias = slave->effective_alias; + data.boot_rx_mailbox_offset = slave->sii.boot_rx_mailbox_offset; + data.boot_rx_mailbox_size = slave->sii.boot_rx_mailbox_size; + data.boot_tx_mailbox_offset = slave->sii.boot_tx_mailbox_offset; + data.boot_tx_mailbox_size = slave->sii.boot_tx_mailbox_size; + data.std_rx_mailbox_offset = slave->sii.std_rx_mailbox_offset; + data.std_rx_mailbox_size = slave->sii.std_rx_mailbox_size; + data.std_tx_mailbox_offset = slave->sii.std_tx_mailbox_offset; + data.std_tx_mailbox_size = slave->sii.std_tx_mailbox_size; + data.mailbox_protocols = slave->sii.mailbox_protocols; + data.has_general_category = slave->sii.has_general; + data.coe_details = slave->sii.coe_details; + data.general_flags = slave->sii.general_flags; + data.current_on_ebus = slave->sii.current_on_ebus; + for (i = 0; i < EC_MAX_PORTS; i++) { + data.ports[i].desc = slave->ports[i].desc; + data.ports[i].link.link_up = slave->ports[i].link.link_up; + data.ports[i].link.loop_closed = slave->ports[i].link.loop_closed; + data.ports[i].link.signal_detected = + slave->ports[i].link.signal_detected; + data.ports[i].receive_time = slave->ports[i].receive_time; + if (slave->ports[i].next_slave) { + data.ports[i].next_slave = + slave->ports[i].next_slave->ring_position; + } else { + data.ports[i].next_slave = 0xffff; + } + data.ports[i].delay_to_next_dc = slave->ports[i].delay_to_next_dc; + } + data.fmmu_bit = slave->base_fmmu_bit_operation; + data.dc_supported = slave->base_dc_supported; + data.dc_range = slave->base_dc_range; + data.has_dc_system_time = slave->has_dc_system_time; + data.transmission_delay = slave->transmission_delay; + data.al_state = slave->current_state; + data.error_flag = slave->error_flag; + + data.sync_count = slave->sii.sync_count; + data.sdo_count = ec_slave_sdo_count(slave); + data.sii_nwords = slave->sii_nwords; + ec_ioctl_strcpy(data.group, slave->sii.group); + ec_ioctl_strcpy(data.image, slave->sii.image); + ec_ioctl_strcpy(data.order, slave->sii.order); + ec_ioctl_strcpy(data.name, slave->sii.name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave sync manager information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sync( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_slave_sync_t data; + const ec_slave_t *slave; + const ec_sync_t *sync; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (data.sync_index >= slave->sii.sync_count) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Sync manager %u does not exist!\n", + data.sync_index); + return -EINVAL; + } + + sync = &slave->sii.syncs[data.sync_index]; + + data.physical_start_address = sync->physical_start_address; + data.default_size = sync->default_length; + data.control_register = sync->control_register; + data.enable = sync->enable; + data.pdo_count = ec_pdo_list_count(&sync->pdos); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave sync manager PDO information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sync_pdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_slave_sync_pdo_t data; + const ec_slave_t *slave; + const ec_sync_t *sync; + const ec_pdo_t *pdo; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (data.sync_index >= slave->sii.sync_count) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Sync manager %u does not exist!\n", + data.sync_index); + return -EINVAL; + } + + sync = &slave->sii.syncs[data.sync_index]; + if (!(pdo = ec_pdo_list_find_pdo_by_pos_const( + &sync->pdos, data.pdo_pos))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Sync manager %u does not contain a PDO with " + "position %u!\n", data.sync_index, data.pdo_pos); + return -EINVAL; + } + + data.index = pdo->index; + data.entry_count = ec_pdo_entry_count(pdo); + ec_ioctl_strcpy(data.name, pdo->name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave sync manager PDO entry information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sync_pdo_entry( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_slave_sync_pdo_entry_t data; + const ec_slave_t *slave; + const ec_sync_t *sync; + const ec_pdo_t *pdo; + const ec_pdo_entry_t *entry; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (data.sync_index >= slave->sii.sync_count) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Sync manager %u does not exist!\n", + data.sync_index); + return -EINVAL; + } + + sync = &slave->sii.syncs[data.sync_index]; + if (!(pdo = ec_pdo_list_find_pdo_by_pos_const( + &sync->pdos, data.pdo_pos))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Sync manager %u does not contain a PDO with " + "position %u!\n", data.sync_index, data.pdo_pos); + return -EINVAL; + } + + if (!(entry = ec_pdo_find_entry_by_pos_const( + pdo, data.entry_pos))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "PDO 0x%04X does not contain an entry with " + "position %u!\n", data.pdo_pos, data.entry_pos); + return -EINVAL; + } + + data.index = entry->index; + data.subindex = entry->subindex; + data.bit_length = entry->bit_length; + ec_ioctl_strcpy(data.name, entry->name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get domain information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_domain_t data; + const ec_domain_t *domain; + unsigned int dev_idx; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(domain = ec_master_find_domain_const(master, data.index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Domain %u does not exist!\n", data.index); + return -EINVAL; + } + + data.data_size = domain->data_size; + data.logical_base_address = domain->logical_base_address; + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + data.working_counter[dev_idx] = domain->working_counter[dev_idx]; + } + data.expected_working_counter = domain->expected_working_counter; + data.fmmu_count = ec_domain_fmmu_count(domain); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get domain FMMU information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_fmmu( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_domain_fmmu_t data; + const ec_domain_t *domain; + const ec_fmmu_config_t *fmmu; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(domain = ec_master_find_domain_const(master, data.domain_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Domain %u does not exist!\n", + data.domain_index); + return -EINVAL; + } + + if (!(fmmu = ec_domain_find_fmmu(domain, data.fmmu_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Domain %u has less than %u" + " fmmu configurations.\n", + data.domain_index, data.fmmu_index + 1); + return -EINVAL; + } + + data.slave_config_alias = fmmu->sc->alias; + data.slave_config_position = fmmu->sc->position; + data.sync_index = fmmu->sync_index; + data.dir = fmmu->dir; + data.logical_address = fmmu->logical_start_address; + data.data_size = fmmu->data_size; + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get domain data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_data( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_domain_data_t data; + const ec_domain_t *domain; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(domain = ec_master_find_domain_const(master, data.domain_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Domain %u does not exist!\n", + data.domain_index); + return -EINVAL; + } + + if (domain->data_size != data.data_size) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Data size mismatch %u/%zu!\n", + data.data_size, domain->data_size); + return -EFAULT; + } + + if (copy_to_user((void __user *) data.target, domain->data, + domain->data_size)) { + up(&master->master_sem); + return -EFAULT; + } + + up(&master->master_sem); + return 0; +} + +/****************************************************************************/ + +/** Set master debug level. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_master_debug( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + return ec_master_debug_level(master, (unsigned long) arg); +} + +/****************************************************************************/ + +/** Issue a bus scan. + * + * \return Always zero (success). + */ +static ATTRIBUTES int ec_ioctl_master_rescan( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + EC_MASTER_DBG(master, 1, "Got rescan command via ioctl()." + " Re-scanning on next possibility.\n"); + master->fsm.rescan_required = 1; + return 0; +} + +/****************************************************************************/ + +/** Set slave state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_state_t data; + ec_slave_t *slave; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + ec_slave_request_state(slave, data.al_state); + + up(&master->master_sem); + return 0; +} + +/****************************************************************************/ + +/** Get slave SDO information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sdo_t data; + const ec_slave_t *slave; + const ec_sdo_t *sdo; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (!(sdo = ec_slave_get_sdo_by_pos_const( + slave, data.sdo_position))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "SDO %u does not exist!\n", data.sdo_position); + return -EINVAL; + } + + data.sdo_index = sdo->index; + data.max_subindex = sdo->max_subindex; + ec_ioctl_strcpy(data.name, sdo->name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave SDO entry information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sdo_entry( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sdo_entry_t data; + const ec_slave_t *slave; + const ec_sdo_t *sdo; + const ec_sdo_entry_t *entry; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (data.sdo_spec <= 0) { + if (!(sdo = ec_slave_get_sdo_by_pos_const( + slave, -data.sdo_spec))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "SDO %u does not exist!\n", -data.sdo_spec); + return -EINVAL; + } + } else { + if (!(sdo = ec_slave_get_sdo_const( + slave, data.sdo_spec))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "SDO 0x%04X does not exist!\n", + data.sdo_spec); + return -EINVAL; + } + } + + if (!(entry = ec_sdo_get_entry_const( + sdo, data.sdo_entry_subindex))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "SDO entry 0x%04X:%02X does not exist!\n", + sdo->index, data.sdo_entry_subindex); + return -EINVAL; + } + + data.data_type = entry->data_type; + data.bit_length = entry->bit_length; + data.read_access[EC_SDO_ENTRY_ACCESS_PREOP] = + entry->read_access[EC_SDO_ENTRY_ACCESS_PREOP]; + data.read_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = + entry->read_access[EC_SDO_ENTRY_ACCESS_SAFEOP]; + data.read_access[EC_SDO_ENTRY_ACCESS_OP] = + entry->read_access[EC_SDO_ENTRY_ACCESS_OP]; + data.write_access[EC_SDO_ENTRY_ACCESS_PREOP] = + entry->write_access[EC_SDO_ENTRY_ACCESS_PREOP]; + data.write_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = + entry->write_access[EC_SDO_ENTRY_ACCESS_SAFEOP]; + data.write_access[EC_SDO_ENTRY_ACCESS_OP] = + entry->write_access[EC_SDO_ENTRY_ACCESS_OP]; + ec_ioctl_strcpy(data.description, entry->description); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Upload SDO. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sdo_upload( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sdo_upload_t data; + uint8_t *target; + int ret; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (!(target = kmalloc(data.target_size, GFP_KERNEL))) { + EC_MASTER_ERR(master, "Failed to allocate %zu bytes" + " for SDO upload.\n", data.target_size); + return -ENOMEM; + } + + ret = ecrt_master_sdo_upload(master, data.slave_position, + data.sdo_index, data.sdo_entry_subindex, target, + data.target_size, &data.data_size, &data.abort_code); + + if (!ret) { + if (copy_to_user((void __user *) data.target, + target, data.data_size)) { + kfree(target); + return -EFAULT; + } + } + + kfree(target); + + if (__copy_to_user((void __user *) arg, &data, sizeof(data))) { + return -EFAULT; + } + + return ret; +} + +/****************************************************************************/ + +/** Download SDO. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sdo_download( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sdo_download_t data; + uint8_t *sdo_data; + int retval; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (!(sdo_data = kmalloc(data.data_size, GFP_KERNEL))) { + EC_MASTER_ERR(master, "Failed to allocate %zu bytes" + " for SDO download.\n", data.data_size); + return -ENOMEM; + } + + if (copy_from_user(sdo_data, (void __user *) data.data, data.data_size)) { + kfree(sdo_data); + return -EFAULT; + } + + if (data.complete_access) { + retval = ecrt_master_sdo_download_complete(master, data.slave_position, + data.sdo_index, sdo_data, data.data_size, &data.abort_code); + } else { + retval = ecrt_master_sdo_download(master, data.slave_position, + data.sdo_index, data.sdo_entry_subindex, sdo_data, + data.data_size, &data.abort_code); + } + + kfree(sdo_data); + + if (__copy_to_user((void __user *) arg, &data, sizeof(data))) { + retval = -EFAULT; + } + + return retval; +} + +/****************************************************************************/ + +/** Read a slave's SII. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sii_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sii_t data; + const ec_slave_t *slave; + int retval; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (!data.nwords + || data.offset + data.nwords > slave->sii_nwords) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Invalid SII read offset/size %u/%u for slave SII" + " size %zu!\n", data.offset, data.nwords, slave->sii_nwords); + return -EINVAL; + } + + if (copy_to_user((void __user *) data.words, + slave->sii_words + data.offset, data.nwords * 2)) + retval = -EFAULT; + else + retval = 0; + + up(&master->master_sem); + return retval; +} + +/****************************************************************************/ + +/** Write a slave's SII. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sii_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sii_t data; + ec_slave_t *slave; + unsigned int byte_size; + uint16_t *words; + ec_sii_write_request_t request; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (!data.nwords) { + return 0; + } + + byte_size = sizeof(uint16_t) * data.nwords; + if (!(words = kmalloc(byte_size, GFP_KERNEL))) { + EC_MASTER_ERR(master, "Failed to allocate %u bytes" + " for SII contents.\n", byte_size); + return -ENOMEM; + } + + if (copy_from_user(words, + (void __user *) data.words, byte_size)) { + kfree(words); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(words); + return -EINTR; + } + + if (!(slave = ec_master_find_slave( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + kfree(words); + return -EINVAL; + } + + // init SII write request + INIT_LIST_HEAD(&request.list); + request.slave = slave; + request.words = words; + request.offset = data.offset; + request.nwords = data.nwords; + request.state = EC_INT_REQUEST_QUEUED; + + // schedule SII write request. + list_add_tail(&request.list, &master->sii_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&request.list); + up(&master->master_sem); + kfree(words); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + kfree(words); + + return request.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; +} + +/****************************************************************************/ + +/** Read a slave's registers. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_reg_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_reg_t io; + ec_slave_t *slave; + ec_reg_request_t request; + int ret; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + if (!io.size) { + return 0; + } + + // init register request + ret = ec_reg_request_init(&request, io.size); + if (ret) { + return ret; + } + + ret = ecrt_reg_request_read(&request, io.address, io.size); + if (ret) { + return ret; + } + + if (down_interruptible(&master->master_sem)) { + ec_reg_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave( + master, 0, io.slave_position))) { + up(&master->master_sem); + ec_reg_request_clear(&request); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + io.slave_position); + return -EINVAL; + } + + // schedule request. + list_add_tail(&request.list, &slave->reg_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&request.list); + up(&master->master_sem); + ec_reg_request_clear(&request); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + if (request.state == EC_INT_REQUEST_SUCCESS) { + if (copy_to_user((void __user *) io.data, request.data, io.size)) { + return -EFAULT; + } + } + ec_reg_request_clear(&request); + + return request.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; +} + +/****************************************************************************/ + +/** Write a slave's registers. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_reg_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_reg_t io; + ec_slave_t *slave; + ec_reg_request_t request; + int ret; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + if (!io.size) { + return 0; + } + + // init register request + ret = ec_reg_request_init(&request, io.size); + if (ret) { + return ret; + } + + if (copy_from_user(request.data, (void __user *) io.data, io.size)) { + ec_reg_request_clear(&request); + return -EFAULT; + } + + ret = ecrt_reg_request_write(&request, io.address, io.size); + if (ret) { + return ret; + } + + if (down_interruptible(&master->master_sem)) { + ec_reg_request_clear(&request); + return -EINTR; + } + + if (io.emergency) { + request.ring_position = io.slave_position; + // schedule request. + list_add_tail(&request.list, &master->emerg_reg_requests); + } + else { + if (!(slave = ec_master_find_slave(master, 0, io.slave_position))) { + up(&master->master_sem); + ec_reg_request_clear(&request); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + io.slave_position); + return -EINVAL; + } + + // schedule request. + list_add_tail(&request.list, &slave->reg_requests); + } + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&request.list); + up(&master->master_sem); + ec_reg_request_clear(&request); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + ec_reg_request_clear(&request); + + return request.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; +} + +/****************************************************************************/ + +/** Get slave configuration information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_t data; + const ec_slave_config_t *sc; + uint8_t i; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config_const( + master, data.config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + data.config_index); + return -EINVAL; + } + + data.alias = sc->alias; + data.position = sc->position; + data.vendor_id = sc->vendor_id; + data.product_code = sc->product_code; + for (i = 0; i < EC_MAX_SYNC_MANAGERS; i++) { + data.syncs[i].dir = sc->sync_configs[i].dir; + data.syncs[i].watchdog_mode = sc->sync_configs[i].watchdog_mode; + data.syncs[i].pdo_count = + ec_pdo_list_count(&sc->sync_configs[i].pdos); + } + data.watchdog_divider = sc->watchdog_divider; + data.watchdog_intervals = sc->watchdog_intervals; + data.sdo_count = ec_slave_config_sdo_count(sc); + data.idn_count = ec_slave_config_idn_count(sc); + data.flag_count = ec_slave_config_flag_count(sc); + data.slave_position = sc->slave ? sc->slave->ring_position : -1; + data.dc_assign_activate = sc->dc_assign_activate; + for (i = 0; i < EC_SYNC_SIGNAL_COUNT; i++) { + data.dc_sync[i] = sc->dc_sync[i]; + } + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave configuration PDO information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_pdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_pdo_t data; + const ec_slave_config_t *sc; + const ec_pdo_t *pdo; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (data.sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_MASTER_ERR(master, "Invalid sync manager index %u!\n", + data.sync_index); + return -EINVAL; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config_const( + master, data.config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + data.config_index); + return -EINVAL; + } + + if (!(pdo = ec_pdo_list_find_pdo_by_pos_const( + &sc->sync_configs[data.sync_index].pdos, + data.pdo_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Invalid PDO position!\n"); + return -EINVAL; + } + + data.index = pdo->index; + data.entry_count = ec_pdo_entry_count(pdo); + ec_ioctl_strcpy(data.name, pdo->name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave configuration PDO entry information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_pdo_entry( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_pdo_entry_t data; + const ec_slave_config_t *sc; + const ec_pdo_t *pdo; + const ec_pdo_entry_t *entry; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (data.sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_MASTER_ERR(master, "Invalid sync manager index %u!\n", + data.sync_index); + return -EINVAL; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config_const( + master, data.config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + data.config_index); + return -EINVAL; + } + + if (!(pdo = ec_pdo_list_find_pdo_by_pos_const( + &sc->sync_configs[data.sync_index].pdos, + data.pdo_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Invalid PDO position!\n"); + return -EINVAL; + } + + if (!(entry = ec_pdo_find_entry_by_pos_const( + pdo, data.entry_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Entry not found!\n"); + return -EINVAL; + } + + data.index = entry->index; + data.subindex = entry->subindex; + data.bit_length = entry->bit_length; + ec_ioctl_strcpy(data.name, entry->name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave configuration SDO information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_sdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_sdo_t *ioctl; + const ec_slave_config_t *sc; + const ec_sdo_request_t *req; + + if (!(ioctl = kmalloc(sizeof(*ioctl), GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(ioctl, (void __user *) arg, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(ioctl); + return -EINTR; + } + + if (!(sc = ec_master_get_config_const( + master, ioctl->config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + ioctl->config_index); + kfree(ioctl); + return -EINVAL; + } + + if (!(req = ec_slave_config_get_sdo_by_pos_const( + sc, ioctl->sdo_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Invalid SDO position!\n"); + kfree(ioctl); + return -EINVAL; + } + + ioctl->index = req->index; + ioctl->subindex = req->subindex; + ioctl->size = req->data_size; + memcpy(ioctl->data, req->data, + min((u32) ioctl->size, (u32) EC_MAX_SDO_DATA_SIZE)); + ioctl->complete_access = req->complete_access; + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, ioctl, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + kfree(ioctl); + return 0; +} + +/****************************************************************************/ + +/** Get slave configuration IDN information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_idn( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_idn_t *ioctl; + const ec_slave_config_t *sc; + const ec_soe_request_t *req; + + if (!(ioctl = kmalloc(sizeof(*ioctl), GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(ioctl, (void __user *) arg, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(ioctl); + return -EINTR; + } + + if (!(sc = ec_master_get_config_const( + master, ioctl->config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + ioctl->config_index); + kfree(ioctl); + return -EINVAL; + } + + if (!(req = ec_slave_config_get_idn_by_pos_const( + sc, ioctl->idn_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Invalid IDN position!\n"); + kfree(ioctl); + return -EINVAL; + } + + ioctl->drive_no = req->drive_no; + ioctl->idn = req->idn; + ioctl->state = req->al_state; + ioctl->size = req->data_size; + memcpy(ioctl->data, req->data, + min((u32) ioctl->size, (u32) EC_MAX_IDN_DATA_SIZE)); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, ioctl, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + kfree(ioctl); + return 0; +} + +/****************************************************************************/ + +/** Get slave configuration feature flag information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_flag( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_flag_t *ioctl; + const ec_slave_config_t *sc; + const ec_flag_t *flag; + size_t size; + + if (!(ioctl = kmalloc(sizeof(*ioctl), GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(ioctl, (void __user *) arg, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(ioctl); + return -EINTR; + } + + if (!(sc = ec_master_get_config_const( + master, ioctl->config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + ioctl->config_index); + kfree(ioctl); + return -EINVAL; + } + + if (!(flag = ec_slave_config_get_flag_by_pos_const( + sc, ioctl->flag_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Invalid flag position!\n"); + kfree(ioctl); + return -EINVAL; + } + + size = min((u32) strlen(flag->key), (u32) EC_MAX_FLAG_KEY_SIZE - 1); + memcpy(ioctl->key, flag->key, size); + ioctl->key[size] = 0x00; + ioctl->value = flag->value; + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, ioctl, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + kfree(ioctl); + return 0; +} + +/****************************************************************************/ + +#ifdef EC_EOE + +/** Get configured EoE IP parameters for a given slave configuration. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_ip( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_eoe_ip_t *ioctl; + const ec_slave_config_t *sc; + const ec_eoe_request_t *req; + + if (!(ioctl = kmalloc(sizeof(*ioctl), GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(ioctl, (void __user *) arg, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(ioctl); + return -EINTR; + } + + if (!(sc = ec_master_get_config_const(master, ioctl->config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + ioctl->config_index); + kfree(ioctl); + return -EINVAL; + } + + req = &sc->eoe_ip_param_request; + + ioctl->mac_address_included = req->mac_address_included; + ioctl->ip_address_included = req->ip_address_included; + ioctl->subnet_mask_included = req->subnet_mask_included; + ioctl->gateway_included = req->gateway_included; + ioctl->dns_included = req->dns_included; + ioctl->name_included = req->name_included; + + memcpy(ioctl->mac_address, req->mac_address, EC_ETH_ALEN); + ioctl->ip_address = req->ip_address; + ioctl->subnet_mask = req->subnet_mask; + ioctl->gateway = req->gateway; + ioctl->dns = req->dns; + strscpy(ioctl->name, req->name, EC_MAX_HOSTNAME_SIZE); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, ioctl, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + kfree(ioctl); + return 0; +} + +#endif + +/****************************************************************************/ + +#ifdef EC_EOE + +/** Get EoE handler information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_eoe_handler( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_eoe_handler_t data; + const ec_eoe_t *eoe; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(eoe = ec_master_get_eoe_handler_const(master, data.eoe_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "EoE handler %u does not exist!\n", + data.eoe_index); + return -EINVAL; + } + + if (eoe->slave) { + data.slave_position = eoe->slave->ring_position; + } else { + data.slave_position = 0xffff; + } + snprintf(data.name, EC_DATAGRAM_NAME_SIZE, eoe->dev->name); + data.open = eoe->opened; + data.rx_bytes = eoe->stats.tx_bytes; + data.rx_rate = eoe->tx_rate; + data.tx_bytes = eoe->stats.rx_bytes; + data.tx_rate = eoe->tx_rate; + data.tx_queued_frames = eoe->tx_queued_frames; + data.tx_queue_size = eoe->tx_queue_size; + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +#endif + +/****************************************************************************/ + +#ifdef EC_EOE +/** Request EoE IP parameter setting. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_eoe_ip_param( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_eoe_ip_t io; + ec_eoe_request_t req; + ec_slave_t *slave; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + // init EoE request + ec_eoe_request_init(&req); + + req.mac_address_included = io.mac_address_included; + req.ip_address_included = io.ip_address_included; + req.subnet_mask_included = io.subnet_mask_included; + req.gateway_included = io.gateway_included; + req.dns_included = io.dns_included; + req.name_included = io.name_included; + + memcpy(req.mac_address, io.mac_address, EC_ETH_ALEN); + req.ip_address = io.ip_address; + req.subnet_mask = io.subnet_mask; + req.gateway = io.gateway; + req.dns = io.dns; + memcpy(req.name, io.name, EC_MAX_HOSTNAME_SIZE); + + req.state = EC_INT_REQUEST_QUEUED; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + if (!(slave = ec_master_find_slave( + master, 0, io.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + io.slave_position); + return -EINVAL; + } + + EC_MASTER_DBG(master, 1, "Scheduling EoE request.\n"); + + // schedule request. + list_add_tail(&req.list, &slave->eoe_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + req.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (req.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&req.list); + up(&master->master_sem); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, req.state != EC_INT_REQUEST_BUSY); + + io.result = req.result; + + if (copy_to_user((void __user *) arg, &io, sizeof(io))) { + return -EFAULT; + } + + return req.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; +} +#endif + +/*****************************************************************************/ + +/** Request the master from userspace. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_request( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_master_t *m; + int ret = 0; + + m = ecrt_request_master_err(master->index); + if (IS_ERR(m)) { + ret = PTR_ERR(m); + } else { + ctx->requested = 1; + } + + return ret; +} + +/****************************************************************************/ + +/** Create a domain. + * + * \return Domain index on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_create_domain( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_domain_t *domain; + + if (unlikely(!ctx->requested)) + return -EPERM; + + domain = ecrt_master_create_domain_err(master); + if (IS_ERR(domain)) + return PTR_ERR(domain); + + return domain->index; +} + +/****************************************************************************/ + +/** Create a slave configuration. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_create_slave_config( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_t data; + ec_slave_config_t *sc, *entry; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + sc = ecrt_master_slave_config_err(master, data.alias, data.position, + data.vendor_id, data.product_code); + if (IS_ERR(sc)) + return PTR_ERR(sc); + + data.config_index = 0; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + list_for_each_entry(entry, &master->configs, list) { + if (entry == sc) + break; + data.config_index++; + } + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Select the DC reference clock. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_select_ref_clock( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + unsigned long config_index = (unsigned long) arg; + ec_slave_config_t *sc = NULL; + int ret = 0; + + if (unlikely(!ctx->requested)) { + ret = -EPERM; + goto out_return; + } + + if (down_interruptible(&master->master_sem)) { + ret = -EINTR; + goto out_return; + } + + if (config_index != 0xFFFFFFFF) { + if (!(sc = ec_master_get_config(master, config_index))) { + ret = -ENOENT; + goto out_up; + } + } + + ecrt_master_select_reference_clock(master, sc); + +out_up: + up(&master->master_sem); +out_return: + return ret; +} + +/****************************************************************************/ + +/** Activates the master. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_activate( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_master_activate_t io; + ec_domain_t *domain; + off_t offset; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + io.process_data = NULL; + + /* Get the sum of the domains' process data sizes. */ + + ctx->process_data_size = 0; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + list_for_each_entry(domain, &master->domains, list) { + ctx->process_data_size += ecrt_domain_size(domain); + } + + up(&master->master_sem); + + if (ctx->process_data_size) { + ctx->process_data = vmalloc(ctx->process_data_size); + if (!ctx->process_data) { + ctx->process_data_size = 0; + return -ENOMEM; + } + + /* Set the memory as external process data memory for the + * domains. + */ + offset = 0; + list_for_each_entry(domain, &master->domains, list) { + ecrt_domain_external_memory(domain, + ctx->process_data + offset); + offset += ecrt_domain_size(domain); + } + +#if defined(EC_IOCTL_RTDM) && !defined(EC_RTDM_XENOMAI_V3) + /* RTDM uses a different approach for memory-mapping, which has to be + * initiated by the kernel. + */ + ret = ec_rtdm_mmap(ctx, &io.process_data); + if (ret < 0) { + EC_MASTER_ERR(master, "Failed to map process data" + " memory to user space (code %i).\n", ret); + return ret; + } +#endif + } + + io.process_data_size = ctx->process_data_size; + +#ifndef EC_IOCTL_RTDM + /* RTDM does not support locking yet. */ + ecrt_master_callbacks(master, ec_master_internal_send_cb, + ec_master_internal_receive_cb, master); +#endif + + ret = ecrt_master_activate(master); + if (ret < 0) + return ret; + + if (copy_to_user((void __user *) arg, &io, + sizeof(ec_ioctl_master_activate_t))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Deactivates the master. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_deactivate( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + if (unlikely(!ctx->requested)) + return -EPERM; + + return ecrt_master_deactivate(master); +} + +/****************************************************************************/ + +/** Set max. number of databytes in a cycle + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_set_send_interval( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + size_t send_interval; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&send_interval, (void __user *) arg, + sizeof(send_interval))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + ec_master_set_send_interval(master, send_interval); + + up(&master->master_sem); + return 0; +} + +/****************************************************************************/ + +/** Send frames. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_send( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_send(master); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Receive frames. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_receive( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_receive(master); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Get the master state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_master_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_master_state_t data; + int ret; + + ret = ecrt_master_state(master, &data); + if (ret) + return ret; + + if (ec_copy_to_user((void __user *) arg, &data, sizeof(data), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get the link state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_master_link_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_link_state_t ioctl; + ec_master_link_state_t state; + int ret; + + if (ec_copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl), ctx)) { + return -EFAULT; + } + + ret = ecrt_master_link_state(master, ioctl.dev_idx, &state); + if (ret < 0) { + return ret; + } + + if (ec_copy_to_user((void __user *) ioctl.state, + &state, sizeof(state), ctx)) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Set the master DC application time. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_app_time( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + uint64_t time; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&time, (void __user *) arg, sizeof(time), ctx)) { + return -EFAULT; + } + + return ecrt_master_application_time(master, time); +} + +/****************************************************************************/ + +/** Sync the reference clock. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sync_ref( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_sync_reference_clock(master); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Sync the reference clock. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sync_ref_to( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + uint64_t time; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&time, (void __user *) arg, sizeof(time), ctx)) { + return -EFAULT; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_sync_reference_clock_to(master, time); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Sync the slave clocks. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sync_slaves( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_sync_slave_clocks(master); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Get the system time of the reference clock. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_ref_clock_time( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + uint32_t time; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + ret = ecrt_master_reference_clock_time(master, &time); + if (ret) { + return ret; + } + + if (ec_copy_to_user((void __user *) arg, &time, sizeof(time), ctx)) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Queue the sync monitoring datagram. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sync_mon_queue( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_sync_monitor_queue(master); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Processes the sync monitoring datagram. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sync_mon_process( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + uint32_t time_diff; + + if (unlikely(!ctx->requested)) + return -EPERM; + + time_diff = ecrt_master_sync_monitor_process(master); + + if (ec_copy_to_user((void __user *) arg, &time_diff, + sizeof(time_diff), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Reset configuration. + * + * \return Always zero (success). + */ +static ATTRIBUTES int ec_ioctl_reset( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ +#ifdef EC_IOCTL_RTDM + /* Xenomai/LXRT is like NMI context, so we do a two-stage schedule. */ + irq_work_queue(&master->sc_reset_work_kicker); +#else + schedule_work(&master->sc_reset_work); +#endif + return 0; +} + +/****************************************************************************/ + +/** Configure a sync manager. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_sync( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_t data; + ec_slave_config_t *sc; + unsigned int i; + int ret = 0; + + if (unlikely(!ctx->requested)) { + ret = -EPERM; + goto out_return; + } + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + ret = -EFAULT; + goto out_return; + } + + if (down_interruptible(&master->master_sem)) { + ret = -EINTR; + goto out_return; + } + + if (!(sc = ec_master_get_config(master, data.config_index))) { + ret = -ENOENT; + goto out_up; + } + + for (i = 0; i < EC_MAX_SYNC_MANAGERS; i++) { + if (data.syncs[i].config_this) { + ret = ecrt_slave_config_sync_manager(sc, i, data.syncs[i].dir, + data.syncs[i].watchdog_mode); + if (ret) { + goto out_up; + } + } + } + +out_up: + up(&master->master_sem); +out_return: + return ret; +} + +/****************************************************************************/ + +/** Configure a slave's watchdogs. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_watchdog( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_t data; + ec_slave_config_t *sc; + int ret = 0; + + if (unlikely(!ctx->requested)) { + ret = -EPERM; + goto out_return; + } + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + ret = -EFAULT; + goto out_return; + } + + if (down_interruptible(&master->master_sem)) { + ret = -EINTR; + goto out_return; + } + + if (!(sc = ec_master_get_config(master, data.config_index))) { + ret = -ENOENT; + goto out_up; + } + + ret = ecrt_slave_config_watchdog(sc, + data.watchdog_divider, data.watchdog_intervals); + +out_up: + up(&master->master_sem); +out_return: + return ret; +} + +/****************************************************************************/ + +/** Add a PDO to the assignment. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_add_pdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_pdo_t data; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + return ecrt_slave_config_pdo_assign_add(sc, data.sync_index, data.index); +} + +/****************************************************************************/ + +/** Clears the PDO assignment. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_clear_pdos( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_pdo_t data; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + return ecrt_slave_config_pdo_assign_clear(sc, data.sync_index); +} + +/****************************************************************************/ + +/** Add an entry to a PDO's mapping. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_add_entry( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_add_pdo_entry_t data; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + return ecrt_slave_config_pdo_mapping_add(sc, data.pdo_index, + data.entry_index, data.entry_subindex, data.entry_bit_length); +} + +/****************************************************************************/ + +/** Clears the mapping of a PDO. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_clear_entries( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_pdo_t data; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + return ecrt_slave_config_pdo_mapping_clear(sc, data.index); +} + +/****************************************************************************/ + +/** Registers a PDO entry. + * + * \return Process data offset on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_reg_pdo_entry( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_pdo_entry_t data; + ec_slave_config_t *sc; + ec_domain_t *domain; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + if (!(domain = ec_master_find_domain(master, data.domain_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc or domain could be invalidated */ + + ret = ecrt_slave_config_reg_pdo_entry(sc, data.entry_index, + data.entry_subindex, domain, &data.bit_position); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return ret; +} + +/****************************************************************************/ + +/** Registers a PDO entry by its position. + * + * \return Process data offset on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_reg_pdo_pos( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_pdo_pos_t io; + ec_slave_config_t *sc; + ec_domain_t *domain; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, io.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + if (!(domain = ec_master_find_domain(master, io.domain_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc or domain could be invalidated */ + + ret = ecrt_slave_config_reg_pdo_entry_pos(sc, io.sync_index, + io.pdo_pos, io.entry_pos, domain, &io.bit_position); + + if (copy_to_user((void __user *) arg, &io, sizeof(io))) + return -EFAULT; + + return ret; +} + +/****************************************************************************/ + +/** Sets the DC AssignActivate word and the sync signal times. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_dc( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_t data; + ec_slave_config_t *sc; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + ret = ecrt_slave_config_dc(sc, data.dc_assign_activate, + data.dc_sync[0].cycle_time, + data.dc_sync[0].shift_time, + data.dc_sync[1].cycle_time, + data.dc_sync[1].shift_time); + + up(&master->master_sem); + + return ret; +} + +/****************************************************************************/ + +/** Configures an SDO. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_sdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_sdo_t data; + ec_slave_config_t *sc; + uint8_t *sdo_data = NULL; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (!data.size) + return -EINVAL; + + if (!(sdo_data = kmalloc(data.size, GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(sdo_data, (void __user *) data.data, data.size)) { + kfree(sdo_data); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(sdo_data); + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + kfree(sdo_data); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + if (data.complete_access) { + ret = ecrt_slave_config_complete_sdo(sc, + data.index, sdo_data, data.size); + } else { + ret = ecrt_slave_config_sdo(sc, data.index, data.subindex, sdo_data, + data.size); + } + kfree(sdo_data); + return ret; +} + +/****************************************************************************/ + +/** Set the emergency ring buffer size. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_emerg_size( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_emerg_t io; + ec_slave_config_t *sc; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, io.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + ret = ecrt_slave_config_emerg_size(sc, io.size); + + up(&master->master_sem); + + return ret; +} + +/****************************************************************************/ + +/** Get an emergency message from the ring. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_emerg_pop( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_emerg_t io; + ec_slave_config_t *sc; + u8 msg[EC_COE_EMERGENCY_MSG_SIZE]; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because configuration will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + ret = ecrt_slave_config_emerg_pop(sc, msg); + if (ret < 0) { + return ret; + } + + if (ec_copy_to_user((void __user *) io.target, msg, sizeof(msg), ctx)) { + return -EFAULT; + } + + return ret; +} + +/****************************************************************************/ + +/** Clear the emergency ring. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_emerg_clear( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_emerg_t io; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because configuration will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + return ecrt_slave_config_emerg_clear(sc); +} + +/****************************************************************************/ + +/** Get the number of emergency overruns. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_emerg_overruns( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_emerg_t io; + ec_slave_config_t *sc; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because configuration will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + ret = ecrt_slave_config_emerg_overruns(sc); + if (ret < 0) { + return ret; + } + + io.overruns = ret; + + if (ec_copy_to_user((void __user *) arg, &io, sizeof(io), ctx)) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Create an SDO request. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_create_sdo_request( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + data.request_index = 0; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + sc = ec_master_get_config(master, data.config_index); + if (!sc) { + up(&master->master_sem); + return -ENOENT; + } + + list_for_each_entry(req, &sc->sdo_requests, list) { + data.request_index++; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + req = ecrt_slave_config_create_sdo_request_err(sc, data.sdo_index, + data.sdo_subindex, data.size); + if (IS_ERR(req)) + return PTR_ERR(req); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Create an SoE request. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_create_soe_request( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + data.request_index = 0; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + sc = ec_master_get_config(master, data.config_index); + if (!sc) { + up(&master->master_sem); + return -ENOENT; + } + + list_for_each_entry(req, &sc->soe_requests, list) { + data.request_index++; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + req = ecrt_slave_config_create_soe_request_err(sc, data.drive_no, + data.idn, data.size); + if (IS_ERR(req)) { + return PTR_ERR(req); + } + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Create a register request. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_create_reg_request( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_request_t io; + ec_slave_config_t *sc; + ec_reg_request_t *reg; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + io.request_index = 0; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + sc = ec_master_get_config(master, io.config_index); + if (!sc) { + up(&master->master_sem); + return -ENOENT; + } + + list_for_each_entry(reg, &sc->reg_requests, list) { + io.request_index++; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + reg = ecrt_slave_config_create_reg_request_err(sc, io.mem_size); + if (IS_ERR(reg)) { + return PTR_ERR(reg); + } + + if (copy_to_user((void __user *) arg, &io, sizeof(io))) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Create a VoE handler. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_create_voe_handler( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + data.voe_index = 0; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + sc = ec_master_get_config(master, data.config_index); + if (!sc) { + up(&master->master_sem); + return -ENOENT; + } + + list_for_each_entry(voe, &sc->voe_handlers, list) { + data.voe_index++; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + voe = ecrt_slave_config_create_voe_handler_err(sc, data.size); + if (IS_ERR(voe)) + return PTR_ERR(voe); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get the slave configuration's state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_state_t data; + const ec_slave_config_t *sc; + ec_slave_config_state_t state; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because sc will not be deleted in the + * meantime. */ + + if (!(sc = ec_master_get_config_const(master, data.config_index))) { + return -ENOENT; + } + + ret = ecrt_slave_config_state(sc, &state); + if (ret) + return ret; + + if (ec_copy_to_user((void __user *) data.state, + &state, sizeof(state), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Configures an IDN. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_idn( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_idn_t ioctl; + ec_slave_config_t *sc; + uint8_t *data = NULL; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl))) + return -EFAULT; + + if (!ioctl.size) + return -EINVAL; + + if (!(data = kmalloc(ioctl.size, GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(data, (void __user *) ioctl.data, ioctl.size)) { + kfree(data); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(data); + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, ioctl.config_index))) { + up(&master->master_sem); + kfree(data); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + ret = ecrt_slave_config_idn( + sc, ioctl.drive_no, ioctl.idn, ioctl.al_state, data, ioctl.size); + kfree(data); + return ret; +} + +/****************************************************************************/ + +/** Configures a feature flag. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_flag( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_flag_t ioctl; + ec_slave_config_t *sc; + uint8_t *key; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl))) { + return -EFAULT; + } + + if (!ioctl.key_size) { + return -EINVAL; + } + + if (!(key = kmalloc(ioctl.key_size + 1, GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(key, (void __user *) ioctl.key, ioctl.key_size)) { + kfree(key); + return -EFAULT; + } + key[ioctl.key_size] = '\0'; + + if (down_interruptible(&master->master_sem)) { + kfree(key); + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, ioctl.config_index))) { + up(&master->master_sem); + kfree(key); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + ret = ecrt_slave_config_flag(sc, key, ioctl.value); + kfree(key); + return ret; +} + +/****************************************************************************/ + +/** Sets an AL state transition timeout. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_state_timeout( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_state_timeout_t ioctl; + ec_slave_config_t *sc; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, ioctl.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + ret = ecrt_slave_config_state_timeout(sc, ioctl.from_state, + ioctl.to_state, ioctl.timeout_ms); + return ret; +} + +/****************************************************************************/ + +#ifdef EC_EOE + +/** Configures EoE IP parameters. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_ip( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_eoe_ip_t io; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, io.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + /* the kernel versions of the EoE set IP methods never fail. */ + if (io.mac_address_included) { + ecrt_slave_config_eoe_mac_address(sc, io.mac_address); + } + if (io.ip_address_included) { + ecrt_slave_config_eoe_ip_address(sc, io.ip_address); + } + if (io.subnet_mask_included) { + ecrt_slave_config_eoe_subnet_mask(sc, io.subnet_mask); + } + if (io.gateway_included) { + ecrt_slave_config_eoe_default_gateway(sc, io.gateway); + } + if (io.dns_included) { + ecrt_slave_config_eoe_dns_address(sc, io.dns); + } + if (io.name_included) { + ecrt_slave_config_eoe_hostname(sc, io.name); + } + + return 0; +} + +#endif + +/****************************************************************************/ + +/** Gets the domain's data size. + * + * \return Domain size, or a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_size( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + const ec_domain_t *domain; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + list_for_each_entry(domain, &master->domains, list) { + if (domain->index == (unsigned long) arg) { + size_t size = ecrt_domain_size(domain); + up(&master->master_sem); + return size; + } + } + + up(&master->master_sem); + return -ENOENT; +} + +/****************************************************************************/ + +/** Gets the domain's offset in the total process data. + * + * \return Domain offset, or a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_offset( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int offset = 0; + const ec_domain_t *domain; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + list_for_each_entry(domain, &master->domains, list) { + if (domain->index == (unsigned long) arg) { + up(&master->master_sem); + return offset; + } + offset += ecrt_domain_size(domain); + } + + up(&master->master_sem); + return -ENOENT; +} + +/****************************************************************************/ + +/** Process the domain. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_process( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_domain_t *domain; + + if (unlikely(!ctx->requested)) + return -EPERM; + + /* no locking of master_sem needed, because domain will not be deleted in + * the meantime. */ + + if (!(domain = ec_master_find_domain(master, (unsigned long) arg))) { + return -ENOENT; + } + + return ecrt_domain_process(domain); +} + +/****************************************************************************/ + +/** Queue the domain. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_queue( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_domain_t *domain; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + /* no locking of master_sem needed, because domain will not be deleted in + * the meantime. */ + + if (!(domain = ec_master_find_domain(master, (unsigned long) arg))) { + return -ENOENT; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_domain_queue(domain); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Get the domain state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_domain_state_t data; + const ec_domain_t *domain; + ec_domain_state_t state; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because domain will not be deleted in + * the meantime. */ + + if (!(domain = ec_master_find_domain_const(master, data.domain_index))) { + return -ENOENT; + } + + ret = ecrt_domain_state(domain, &state); + if (ret) + return ret; + + if (ec_copy_to_user((void __user *) data.state, &state, sizeof(state), + ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Sets an SDO request's SDO index and subindex. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_index( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_sdo_request_index(req, data.sdo_index, data.sdo_subindex); +} + +/****************************************************************************/ + +/** Sets an SDO request's timeout. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_timeout( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_sdo_request_timeout(req, data.timeout); +} + +/****************************************************************************/ + +/** Gets an SDO request's state. + * + * Also pre-fetches the size of incoming data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + data.state = ecrt_sdo_request_state(req); + if (data.state == EC_REQUEST_SUCCESS && req->dir == EC_DIR_INPUT) + data.size = ecrt_sdo_request_data_size(req); + else + data.size = 0; + + if (ec_copy_to_user((void __user *) arg, &data, sizeof(data), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Starts an SDO read operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_sdo_request_read(req); +} + +/****************************************************************************/ + +/** Starts an SDO write operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + if (!data.size) { + EC_MASTER_ERR(master, "SDO download: Data size may not be zero!\n"); + return -EINVAL; + } + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + if (data.size > req->mem_size) + return -ENOBUFS; + + if (ec_copy_from_user(req->data, (void __user *) data.data, + data.size, ctx)) + return -EFAULT; + + req->data_size = data.size; + return ecrt_sdo_request_write(req); +} + +/****************************************************************************/ + +/** Read SDO data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_data( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + if (ec_copy_to_user((void __user *) data.data, ecrt_sdo_request_data(req), + ecrt_sdo_request_data_size(req), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Sets an SoE request's drive number and IDN. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_index( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_soe_request_idn(req, data.drive_no, data.idn); +} + +/****************************************************************************/ + +/** Sets an CoE request's timeout. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_timeout( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_soe_request_timeout(req, data.timeout); +} + +/****************************************************************************/ + +/** Gets an SoE request's state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + data.state = ecrt_soe_request_state(req); + if (data.state == EC_REQUEST_SUCCESS && req->dir == EC_DIR_INPUT) { + data.size = ecrt_soe_request_data_size(req); + } + else { + data.size = 0; + } + + if (ec_copy_to_user((void __user *) arg, &data, sizeof(data), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Starts an SoE IDN read operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_soe_request_read(req); +} + +/****************************************************************************/ + +/** Starts an SoE IDN write operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + if (!data.size) { + EC_MASTER_ERR(master, "IDN write: Data size may not be zero!\n"); + return -EINVAL; + } + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + if (data.size > req->mem_size) + return -ENOBUFS; + + if (ec_copy_from_user(req->data, (void __user *) data.data, + data.size, ctx)) + return -EFAULT; + + req->data_size = data.size; + return ecrt_soe_request_write(req); +} + +/****************************************************************************/ + +/** Read SoE IDN data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_data( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + if (ec_copy_to_user((void __user *) data.data, ecrt_soe_request_data(req), + ecrt_soe_request_data_size(req), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Read register data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_reg_request_data( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_request_t io; + ec_slave_config_t *sc; + ec_reg_request_t *reg; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + if (io.mem_size <= 0) { + return 0; + } + + /* no locking of master_sem needed, because neither sc nor reg will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + if (!(reg = ec_slave_config_find_reg_request(sc, io.request_index))) { + return -ENOENT; + } + + if (ec_copy_to_user((void __user *) io.data, ecrt_reg_request_data(reg), + min(reg->mem_size, io.mem_size), ctx)) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Gets an register request's state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_reg_request_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_request_t io; + ec_slave_config_t *sc; + ec_reg_request_t *reg; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because neither sc nor reg will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + if (!(reg = ec_slave_config_find_reg_request(sc, io.request_index))) { + return -ENOENT; + } + + io.state = ecrt_reg_request_state(reg); + io.new_data = io.state == EC_REQUEST_SUCCESS && reg->dir == EC_DIR_INPUT; + + if (ec_copy_to_user((void __user *) arg, &io, sizeof(io), ctx)) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Starts an register write operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_reg_request_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_request_t io; + ec_slave_config_t *sc; + ec_reg_request_t *reg; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because neither sc nor reg will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + if (!(reg = ec_slave_config_find_reg_request(sc, io.request_index))) { + return -ENOENT; + } + + if (io.transfer_size > reg->mem_size) { + return -ENOBUFS; + } + + if (ec_copy_from_user(reg->data, (void __user *) io.data, + io.transfer_size, ctx)) { + return -EFAULT; + } + + return ecrt_reg_request_write(reg, io.address, io.transfer_size); +} + +/****************************************************************************/ + +/** Starts an register read operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_reg_request_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_request_t io; + ec_slave_config_t *sc; + ec_reg_request_t *reg; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because neither sc nor reg will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + if (!(reg = ec_slave_config_find_reg_request(sc, io.request_index))) { + return -ENOENT; + } + + if (io.transfer_size > reg->mem_size) { + return -ENOBUFS; + } + + return ecrt_reg_request_read(reg, io.address, io.transfer_size); +} + +/****************************************************************************/ + +/** Sets the VoE send header. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_send_header( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + uint32_t vendor_id; + uint16_t vendor_type; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + if (ec_copy_from_user(&vendor_id, data.vendor_id, sizeof(vendor_id), ctx)) + return -EFAULT; + + if (ec_copy_from_user(&vendor_type, data.vendor_type, + sizeof(vendor_type), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + return ecrt_voe_handler_send_header(voe, vendor_id, vendor_type); +} + +/****************************************************************************/ + +/** Gets the received VoE header. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_rec_header( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + uint32_t vendor_id; + uint16_t vendor_type; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + ret = ecrt_voe_handler_received_header(voe, &vendor_id, &vendor_type); + if (ret) + return ret; + + if (likely(data.vendor_id)) + if (ec_copy_to_user(data.vendor_id, &vendor_id, + sizeof(vendor_id), ctx)) + return -EFAULT; + + if (likely(data.vendor_type)) + if (ec_copy_to_user(data.vendor_type, &vendor_type, + sizeof(vendor_type), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Starts a VoE read operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + return ecrt_voe_handler_read(voe); +} + +/****************************************************************************/ + +/** Starts a VoE read operation without sending a sync message first. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_read_nosync( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + return ecrt_voe_handler_read_nosync(voe); +} + +/****************************************************************************/ + +/** Starts a VoE write operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + if (data.size) { + if (data.size > ec_voe_handler_mem_size(voe)) + return -ENOBUFS; + + if (ec_copy_from_user(ecrt_voe_handler_data(voe), + (void __user *) data.data, data.size, ctx)) + return -EFAULT; + } + + return ecrt_voe_handler_write(voe, data.size); +} + +/****************************************************************************/ + +/** Executes the VoE state machine. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_exec( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + data.state = ecrt_voe_handler_execute(voe); + ec_ioctl_unlock(&master->io_mutex); + if (data.state == EC_REQUEST_SUCCESS && voe->dir == EC_DIR_INPUT) + data.size = ecrt_voe_handler_data_size(voe); + else + data.size = 0; + + if (ec_copy_to_user((void __user *) arg, &data, sizeof(data), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Reads the received VoE data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_data( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + if (ec_copy_to_user((void __user *) data.data, ecrt_voe_handler_data(voe), + ecrt_voe_handler_data_size(voe), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Read a file from a slave via FoE. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_foe_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_foe_t io; + ec_foe_request_t request; + ec_slave_t *slave; + int ret; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + ec_foe_request_init(&request, io.file_name); + ret = ec_foe_request_alloc(&request, 10000); // FIXME + if (ret) { + ec_foe_request_clear(&request); + return ret; + } + + ec_foe_request_read(&request); + + if (down_interruptible(&master->master_sem)) { + ec_foe_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, io.slave_position))) { + up(&master->master_sem); + ec_foe_request_clear(&request); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + io.slave_position); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling FoE read request.\n"); + + // schedule request. + list_add_tail(&request.list, &slave->foe_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + list_del(&request.list); + up(&master->master_sem); + ec_foe_request_clear(&request); + return -EINTR; + } + // request already processing: interrupt not possible. + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + io.result = request.result; + io.error_code = request.error_code; + + if (request.state != EC_INT_REQUEST_SUCCESS) { + io.data_size = 0; + ret = -EIO; + } else { + if (request.data_size > io.buffer_size) { + EC_SLAVE_ERR(slave, "%s(): Buffer too small.\n", __func__); + ec_foe_request_clear(&request); + return -ENOBUFS; + } + io.data_size = request.data_size; + if (copy_to_user((void __user *) io.buffer, + request.buffer, io.data_size)) { + ec_foe_request_clear(&request); + return -EFAULT; + } + ret = 0; + } + + if (__copy_to_user((void __user *) arg, &io, sizeof(io))) { + ret = -EFAULT; + } + + ec_foe_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +/** Write a file to a slave via FoE + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_foe_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_foe_t io; + ec_foe_request_t request; + ec_slave_t *slave; + int ret; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + ec_foe_request_init(&request, io.file_name); + + ret = ec_foe_request_alloc(&request, io.buffer_size); + if (ret) { + ec_foe_request_clear(&request); + return ret; + } + + if (copy_from_user(request.buffer, + (void __user *) io.buffer, io.buffer_size)) { + ec_foe_request_clear(&request); + return -EFAULT; + } + + request.data_size = io.buffer_size; + ec_foe_request_write(&request); + + if (down_interruptible(&master->master_sem)) { + ec_foe_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, io.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + io.slave_position); + ec_foe_request_clear(&request); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling FoE write request.\n"); + + // schedule FoE write request. + list_add_tail(&request.list, &slave->foe_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&request.list); + up(&master->master_sem); + ec_foe_request_clear(&request); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + io.result = request.result; + io.error_code = request.error_code; + + ret = request.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; + + if (__copy_to_user((void __user *) arg, &io, sizeof(io))) { + ret = -EFAULT; + } + + ec_foe_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +/** Read an SoE IDN. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_soe_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_soe_read_t ioctl; + u8 *data; + int retval; + + if (copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl))) { + return -EFAULT; + } + + data = kmalloc(ioctl.mem_size, GFP_KERNEL); + if (!data) { + EC_MASTER_ERR(master, "Failed to allocate %zu bytes of IDN data.\n", + ioctl.mem_size); + return -ENOMEM; + } + + retval = ecrt_master_read_idn(master, ioctl.slave_position, + ioctl.drive_no, ioctl.idn, data, ioctl.mem_size, &ioctl.data_size, + &ioctl.error_code); + if (retval) { + kfree(data); + return retval; + } + + if (copy_to_user((void __user *) ioctl.data, + data, ioctl.data_size)) { + kfree(data); + return -EFAULT; + } + kfree(data); + + if (__copy_to_user((void __user *) arg, &ioctl, sizeof(ioctl))) { + retval = -EFAULT; + } + + EC_MASTER_DBG(master, 1, "Finished SoE read request.\n"); + return retval; +} + +/****************************************************************************/ + +/** Write an IDN to a slave via SoE. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_soe_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_soe_write_t ioctl; + u8 *data; + int retval; + + if (copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl))) { + return -EFAULT; + } + + data = kmalloc(ioctl.data_size, GFP_KERNEL); + if (!data) { + EC_MASTER_ERR(master, "Failed to allocate %zu bytes of IDN data.\n", + ioctl.data_size); + return -ENOMEM; + } + if (copy_from_user(data, (void __user *) ioctl.data, ioctl.data_size)) { + kfree(data); + return -EFAULT; + } + + retval = ecrt_master_write_idn(master, ioctl.slave_position, + ioctl.drive_no, ioctl.idn, data, ioctl.data_size, + &ioctl.error_code); + kfree(data); + if (retval) { + return retval; + } + + if (__copy_to_user((void __user *) arg, &ioctl, sizeof(ioctl))) { + retval = -EFAULT; + } + + EC_MASTER_DBG(master, 1, "Finished SoE write request.\n"); + return retval; +} + +/***************************************************************************** + * ioctl() file operation functions + ****************************************************************************/ + +/** ioctl() function to use. + * + * For RTDM, there will be ec_ioctl_rtdm_rt and ec_ioctl_rtdm_nrt. + * For "normal" cdev, there will be ec_ioctl_rt only. + */ +#ifndef EC_IOCTL_RTDM +static long ec_ioctl_nrt( + ec_master_t *master, /**< EtherCAT master. */ + ec_ioctl_context_t *ctx, /**< Device context. */ + unsigned int cmd, /**< ioctl() command identifier. */ + void *arg /**< ioctl() argument. */); +#endif + +/****************************************************************************/ + +/** Called when an ioctl() command is issued. + * Both RT and nRT context. + * + * \return ioctl() return code. + */ +static long ec_ioctl_both( + ec_master_t *master, /**< EtherCAT master. */ + ec_ioctl_context_t *ctx, /**< Device context. */ + unsigned int cmd, /**< ioctl() command identifier. */ + void *arg /**< ioctl() argument. */ + ) +{ + int ret; + + switch (cmd) { + case EC_IOCTL_MODULE: + ret = ec_ioctl_module(arg, ctx); + break; + case EC_IOCTL_MASTER_RESCAN: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_master_rescan(master, arg); + break; + case EC_IOCTL_MASTER_STATE: + ret = ec_ioctl_master_state(master, arg, ctx); + break; + case EC_IOCTL_MASTER_LINK_STATE: + ret = ec_ioctl_master_link_state(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_TIMEOUT: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sdo_request_timeout(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_DATA: + ret = ec_ioctl_sdo_request_data(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_TIMEOUT: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_soe_request_timeout(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_DATA: + ret = ec_ioctl_soe_request_data(master, arg, ctx); + break; + case EC_IOCTL_REG_REQUEST_DATA: + ret = ec_ioctl_reg_request_data(master, arg, ctx); + break; + case EC_IOCTL_VOE_SEND_HEADER: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_voe_send_header(master, arg, ctx); + break; + case EC_IOCTL_VOE_DATA: + ret = ec_ioctl_voe_data(master, arg, ctx); + break; + default: +#ifdef EC_IOCTL_RTDM + ret = -ENOTTY; +#else + /* chain non-rt commands for normal cdev */ + ret = ec_ioctl_nrt(master, ctx, cmd, arg); +#endif + break; + } + + return ret; +} + +/****************************************************************************/ + +/** Called when an ioctl() command is issued. + * RTDM: RT only. + * + * \return ioctl() return code. + */ +#ifdef EC_IOCTL_RTDM +long ec_ioctl_rtdm_rt +#else +long ec_ioctl +#endif + ( + ec_master_t *master, /**< EtherCAT master. */ + ec_ioctl_context_t *ctx, /**< Device context. */ + unsigned int cmd, /**< ioctl() command identifier. */ + void *arg /**< ioctl() argument. */ + ) +{ +#if DEBUG_LATENCY + cycles_t a = get_cycles(), b; + unsigned int t; +#endif + long ret; + + switch (cmd) { + case EC_IOCTL_SEND: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_send(master, arg, ctx); + break; + case EC_IOCTL_RECEIVE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_receive(master, arg, ctx); + break; + case EC_IOCTL_APP_TIME: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_app_time(master, arg, ctx); + break; + case EC_IOCTL_SYNC_REF: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sync_ref(master, arg, ctx); + break; + case EC_IOCTL_SYNC_REF_TO: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sync_ref_to(master, arg, ctx); + break; + case EC_IOCTL_SYNC_SLAVES: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sync_slaves(master, arg, ctx); + break; + case EC_IOCTL_REF_CLOCK_TIME: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_ref_clock_time(master, arg, ctx); + break; + case EC_IOCTL_SYNC_MON_QUEUE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sync_mon_queue(master, arg, ctx); + break; + case EC_IOCTL_SYNC_MON_PROCESS: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sync_mon_process(master, arg, ctx); + break; + case EC_IOCTL_RESET: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_reset(master, arg, ctx); + break; + case EC_IOCTL_SC_EMERG_POP: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_emerg_pop(master, arg, ctx); + break; + case EC_IOCTL_SC_EMERG_CLEAR: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_emerg_clear(master, arg, ctx); + break; + case EC_IOCTL_SC_EMERG_OVERRUNS: + ret = ec_ioctl_sc_emerg_overruns(master, arg, ctx); + break; + case EC_IOCTL_SC_STATE: + ret = ec_ioctl_sc_state(master, arg, ctx); + break; + case EC_IOCTL_DOMAIN_PROCESS: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_domain_process(master, arg, ctx); + break; + case EC_IOCTL_DOMAIN_QUEUE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_domain_queue(master, arg, ctx); + break; + case EC_IOCTL_DOMAIN_STATE: + ret = ec_ioctl_domain_state(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_INDEX: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sdo_request_index(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_STATE: + ret = ec_ioctl_sdo_request_state(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sdo_request_read(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sdo_request_write(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_IDN: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_soe_request_index(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_STATE: + ret = ec_ioctl_soe_request_state(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_soe_request_read(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_soe_request_write(master, arg, ctx); + break; + case EC_IOCTL_REG_REQUEST_STATE: + ret = ec_ioctl_reg_request_state(master, arg, ctx); + break; + case EC_IOCTL_REG_REQUEST_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_reg_request_write(master, arg, ctx); + break; + case EC_IOCTL_REG_REQUEST_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_reg_request_read(master, arg, ctx); + break; + case EC_IOCTL_VOE_REC_HEADER: + ret = ec_ioctl_voe_rec_header(master, arg, ctx); + break; + case EC_IOCTL_VOE_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_voe_read(master, arg, ctx); + break; + case EC_IOCTL_VOE_READ_NOSYNC: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_voe_read_nosync(master, arg, ctx); + break; + case EC_IOCTL_VOE_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_voe_write(master, arg, ctx); + break; + case EC_IOCTL_VOE_EXEC: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_voe_exec(master, arg, ctx); + break; + default: + ret = ec_ioctl_both(master, ctx, cmd, arg); + break; + } + +#if DEBUG_LATENCY + b = get_cycles(); + t = (unsigned int) ((b - a) * 1000LL) / cpu_khz; + if (t > 50) { + EC_MASTER_WARN(master, "ioctl(0x%02x) took %u us.\n", + _IOC_NR(cmd), t); + } +#endif + + return ret; +} + +/****************************************************************************/ + +/** Called when an ioctl() command is issued. + * nRT context only. + * + * \return ioctl() return code. + */ +#ifdef EC_IOCTL_RTDM +long ec_ioctl_rtdm_nrt +#else +static long ec_ioctl_nrt +#endif + ( + ec_master_t *master, /**< EtherCAT master. */ + ec_ioctl_context_t *ctx, /**< Device context. */ + unsigned int cmd, /**< ioctl() command identifier. */ + void *arg /**< ioctl() argument. */ + ) +{ +#if DEBUG_LATENCY && !defined(EC_IOCTL_RTDM) + cycles_t a = get_cycles(), b; + unsigned int t; +#endif + int ret; + + switch (cmd) { + case EC_IOCTL_MASTER: + ret = ec_ioctl_master(master, arg); + break; + case EC_IOCTL_SLAVE: + ret = ec_ioctl_slave(master, arg); + break; + case EC_IOCTL_SLAVE_SYNC: + ret = ec_ioctl_slave_sync(master, arg); + break; + case EC_IOCTL_SLAVE_SYNC_PDO: + ret = ec_ioctl_slave_sync_pdo(master, arg); + break; + case EC_IOCTL_SLAVE_SYNC_PDO_ENTRY: + ret = ec_ioctl_slave_sync_pdo_entry(master, arg); + break; + case EC_IOCTL_DOMAIN: + ret = ec_ioctl_domain(master, arg); + break; + case EC_IOCTL_DOMAIN_FMMU: + ret = ec_ioctl_domain_fmmu(master, arg); + break; + case EC_IOCTL_DOMAIN_DATA: + ret = ec_ioctl_domain_data(master, arg); + break; + case EC_IOCTL_MASTER_DEBUG: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_master_debug(master, arg); + break; + case EC_IOCTL_SLAVE_STATE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_state(master, arg); + break; + case EC_IOCTL_SLAVE_SDO: + ret = ec_ioctl_slave_sdo(master, arg); + break; + case EC_IOCTL_SLAVE_SDO_ENTRY: + ret = ec_ioctl_slave_sdo_entry(master, arg); + break; + case EC_IOCTL_SLAVE_SDO_UPLOAD: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_sdo_upload(master, arg); + break; + case EC_IOCTL_SLAVE_SDO_DOWNLOAD: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_sdo_download(master, arg); + break; + case EC_IOCTL_SLAVE_SII_READ: + ret = ec_ioctl_slave_sii_read(master, arg); + break; + case EC_IOCTL_SLAVE_SII_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_sii_write(master, arg); + break; + case EC_IOCTL_SLAVE_REG_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_reg_read(master, arg); + break; + case EC_IOCTL_SLAVE_REG_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_reg_write(master, arg); + break; + case EC_IOCTL_SLAVE_FOE_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_foe_read(master, arg); + break; + case EC_IOCTL_SLAVE_FOE_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_foe_write(master, arg); + break; + case EC_IOCTL_SLAVE_SOE_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_soe_read(master, arg); + break; + case EC_IOCTL_SLAVE_SOE_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_soe_write(master, arg); + break; +#ifdef EC_EOE + case EC_IOCTL_SLAVE_EOE_IP_PARAM: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_eoe_ip_param(master, arg); + break; +#endif + case EC_IOCTL_CONFIG: + ret = ec_ioctl_config(master, arg); + break; + case EC_IOCTL_CONFIG_PDO: + ret = ec_ioctl_config_pdo(master, arg); + break; + case EC_IOCTL_CONFIG_PDO_ENTRY: + ret = ec_ioctl_config_pdo_entry(master, arg); + break; + case EC_IOCTL_CONFIG_SDO: + ret = ec_ioctl_config_sdo(master, arg); + break; + case EC_IOCTL_CONFIG_IDN: + ret = ec_ioctl_config_idn(master, arg); + break; + case EC_IOCTL_CONFIG_FLAG: + ret = ec_ioctl_config_flag(master, arg); + break; +#ifdef EC_EOE + case EC_IOCTL_CONFIG_EOE_IP_PARAM: + ret = ec_ioctl_config_ip(master, arg); + break; + case EC_IOCTL_EOE_HANDLER: + ret = ec_ioctl_eoe_handler(master, arg); + break; +#endif + + /* Application interface */ + + case EC_IOCTL_REQUEST: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_request(master, arg, ctx); + break; + case EC_IOCTL_CREATE_DOMAIN: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_create_domain(master, arg, ctx); + break; + case EC_IOCTL_CREATE_SLAVE_CONFIG: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_create_slave_config(master, arg, ctx); + break; + case EC_IOCTL_SELECT_REF_CLOCK: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_select_ref_clock(master, arg, ctx); + break; + case EC_IOCTL_ACTIVATE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_activate(master, arg, ctx); + break; + case EC_IOCTL_DEACTIVATE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_deactivate(master, arg, ctx); + break; + case EC_IOCTL_SC_SYNC: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_sync(master, arg, ctx); + break; + case EC_IOCTL_SC_WATCHDOG: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_watchdog(master, arg, ctx); + break; + case EC_IOCTL_SC_ADD_PDO: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_add_pdo(master, arg, ctx); + break; + case EC_IOCTL_SC_CLEAR_PDOS: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_clear_pdos(master, arg, ctx); + break; + case EC_IOCTL_SC_ADD_ENTRY: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_add_entry(master, arg, ctx); + break; + case EC_IOCTL_SC_CLEAR_ENTRIES: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_clear_entries(master, arg, ctx); + break; + case EC_IOCTL_SC_REG_PDO_ENTRY: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_reg_pdo_entry(master, arg, ctx); + break; + case EC_IOCTL_SC_REG_PDO_POS: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_reg_pdo_pos(master, arg, ctx); + break; + case EC_IOCTL_SC_DC: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_dc(master, arg, ctx); + break; + case EC_IOCTL_SC_SDO: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_sdo(master, arg, ctx); + break; + case EC_IOCTL_SC_EMERG_SIZE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_emerg_size(master, arg, ctx); + break; + case EC_IOCTL_SC_SDO_REQUEST: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_create_sdo_request(master, arg, ctx); + break; + case EC_IOCTL_SC_SOE_REQUEST: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_create_soe_request(master, arg, ctx); + break; + case EC_IOCTL_SC_REG_REQUEST: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_create_reg_request(master, arg, ctx); + break; + case EC_IOCTL_SC_VOE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_create_voe_handler(master, arg, ctx); + break; + case EC_IOCTL_SC_IDN: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_idn(master, arg, ctx); + break; + case EC_IOCTL_SC_FLAG: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_flag(master, arg, ctx); + break; + case EC_IOCTL_SC_STATE_TIMEOUT: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_state_timeout(master, arg, ctx); + break; +#ifdef EC_EOE + case EC_IOCTL_SC_EOE_IP_PARAM: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_ip(master, arg, ctx); + break; +#endif + case EC_IOCTL_DOMAIN_SIZE: + ret = ec_ioctl_domain_size(master, arg, ctx); + break; + case EC_IOCTL_DOMAIN_OFFSET: + ret = ec_ioctl_domain_offset(master, arg, ctx); + break; + case EC_IOCTL_SET_SEND_INTERVAL: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_set_send_interval(master, arg, ctx); + break; + default: +#ifdef EC_IOCTL_RTDM + ret = ec_ioctl_both(master, ctx, cmd, arg); +#else + ret = -ENOTTY; +#endif + break; + } + +#if DEBUG_LATENCY && !defined(EC_IOCTL_RTDM) + b = get_cycles(); + t = (unsigned int) ((b - a) * 1000LL) / cpu_khz; + if (t > 50) { + EC_MASTER_WARN(master, "ioctl(0x%02x) took %u us.\n", + _IOC_NR(cmd), t); + } +#endif + + return ret; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/ioctl.h b/ubuntu/igh-ecat/master/ioctl.h new file mode 100644 index 00000000000000..0c51e6380f4365 --- /dev/null +++ b/ubuntu/igh-ecat/master/ioctl.h @@ -0,0 +1,879 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT master. + * + * The file is free software; you can redistribute it and/or modify it under + * the terms of the GNU Lesser General Public License as published by the + * Free Software Foundation; version 2.1 of the License. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + * License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this file. If not, see . + * + ****************************************************************************/ + +/** + \file + EtherCAT master character device IOCTL commands. +*/ + +/****************************************************************************/ + +#ifndef __EC_IOCTL_H__ +#define __EC_IOCTL_H__ + +#include + +#include "globals.h" + +/****************************************************************************/ + +/** \cond */ + +#define EC_IOCTL_TYPE 0xa4 + +#define EC_IO(nr) _IO(EC_IOCTL_TYPE, nr) +#define EC_IOR(nr, type) _IOR(EC_IOCTL_TYPE, nr, type) +#define EC_IOW(nr, type) _IOW(EC_IOCTL_TYPE, nr, type) +#define EC_IOWR(nr, type) _IOWR(EC_IOCTL_TYPE, nr, type) + +/** EtherCAT master ioctl() version magic. + * + * Increment this when changing the ioctl interface! + */ +#define EC_IOCTL_VERSION_MAGIC 37 + +// Command-line tool +#define EC_IOCTL_MODULE EC_IOR(0x00, ec_ioctl_module_t) +#define EC_IOCTL_MASTER EC_IOR(0x01, ec_ioctl_master_t) +#define EC_IOCTL_SLAVE EC_IOWR(0x02, ec_ioctl_slave_t) +#define EC_IOCTL_SLAVE_SYNC EC_IOWR(0x03, ec_ioctl_slave_sync_t) +#define EC_IOCTL_SLAVE_SYNC_PDO EC_IOWR(0x04, ec_ioctl_slave_sync_pdo_t) +#define EC_IOCTL_SLAVE_SYNC_PDO_ENTRY EC_IOWR(0x05, ec_ioctl_slave_sync_pdo_entry_t) +#define EC_IOCTL_DOMAIN EC_IOWR(0x06, ec_ioctl_domain_t) +#define EC_IOCTL_DOMAIN_FMMU EC_IOWR(0x07, ec_ioctl_domain_fmmu_t) +#define EC_IOCTL_DOMAIN_DATA EC_IOWR(0x08, ec_ioctl_domain_data_t) +#define EC_IOCTL_MASTER_DEBUG EC_IO(0x09) +#define EC_IOCTL_MASTER_RESCAN EC_IO(0x0a) +#define EC_IOCTL_SLAVE_STATE EC_IOW(0x0b, ec_ioctl_slave_state_t) +#define EC_IOCTL_SLAVE_SDO EC_IOWR(0x0c, ec_ioctl_slave_sdo_t) +#define EC_IOCTL_SLAVE_SDO_ENTRY EC_IOWR(0x0d, ec_ioctl_slave_sdo_entry_t) +#define EC_IOCTL_SLAVE_SDO_UPLOAD EC_IOWR(0x0e, ec_ioctl_slave_sdo_upload_t) +#define EC_IOCTL_SLAVE_SDO_DOWNLOAD EC_IOWR(0x0f, ec_ioctl_slave_sdo_download_t) +#define EC_IOCTL_SLAVE_SII_READ EC_IOWR(0x10, ec_ioctl_slave_sii_t) +#define EC_IOCTL_SLAVE_SII_WRITE EC_IOW(0x11, ec_ioctl_slave_sii_t) +#define EC_IOCTL_SLAVE_REG_READ EC_IOWR(0x12, ec_ioctl_slave_reg_t) +#define EC_IOCTL_SLAVE_REG_WRITE EC_IOW(0x13, ec_ioctl_slave_reg_t) +#define EC_IOCTL_SLAVE_FOE_READ EC_IOWR(0x14, ec_ioctl_slave_foe_t) +#define EC_IOCTL_SLAVE_FOE_WRITE EC_IOW(0x15, ec_ioctl_slave_foe_t) +#define EC_IOCTL_SLAVE_SOE_READ EC_IOWR(0x16, ec_ioctl_slave_soe_read_t) +#define EC_IOCTL_SLAVE_SOE_WRITE EC_IOWR(0x17, ec_ioctl_slave_soe_write_t) +#ifdef EC_EOE +#define EC_IOCTL_SLAVE_EOE_IP_PARAM EC_IOW(0x18, ec_ioctl_eoe_ip_t) +#endif +#define EC_IOCTL_CONFIG EC_IOWR(0x19, ec_ioctl_config_t) +#define EC_IOCTL_CONFIG_PDO EC_IOWR(0x1a, ec_ioctl_config_pdo_t) +#define EC_IOCTL_CONFIG_PDO_ENTRY EC_IOWR(0x1b, ec_ioctl_config_pdo_entry_t) +#define EC_IOCTL_CONFIG_SDO EC_IOWR(0x1c, ec_ioctl_config_sdo_t) +#define EC_IOCTL_CONFIG_IDN EC_IOWR(0x1d, ec_ioctl_config_idn_t) +#define EC_IOCTL_CONFIG_FLAG EC_IOWR(0x1e, ec_ioctl_config_flag_t) +#ifdef EC_EOE +#define EC_IOCTL_CONFIG_EOE_IP_PARAM EC_IOWR(0x1f, ec_ioctl_eoe_ip_t) +#define EC_IOCTL_EOE_HANDLER EC_IOWR(0x20, ec_ioctl_eoe_handler_t) +#endif + +// Application interface +#define EC_IOCTL_REQUEST EC_IO(0x21) +#define EC_IOCTL_CREATE_DOMAIN EC_IO(0x22) +#define EC_IOCTL_CREATE_SLAVE_CONFIG EC_IOWR(0x23, ec_ioctl_config_t) +#define EC_IOCTL_SELECT_REF_CLOCK EC_IOW(0x24, uint32_t) +#define EC_IOCTL_ACTIVATE EC_IOR(0x25, ec_ioctl_master_activate_t) +#define EC_IOCTL_DEACTIVATE EC_IO(0x26) +#define EC_IOCTL_SEND EC_IO(0x27) +#define EC_IOCTL_RECEIVE EC_IO(0x28) +#define EC_IOCTL_MASTER_STATE EC_IOR(0x29, ec_master_state_t) +#define EC_IOCTL_MASTER_LINK_STATE EC_IOWR(0x2a, ec_ioctl_link_state_t) +#define EC_IOCTL_APP_TIME EC_IOW(0x2b, uint64_t) +#define EC_IOCTL_SYNC_REF EC_IO(0x2c) +#define EC_IOCTL_SYNC_REF_TO EC_IOW(0x2d, uint64_t) +#define EC_IOCTL_SYNC_SLAVES EC_IO(0x2e) +#define EC_IOCTL_REF_CLOCK_TIME EC_IOR(0x2f, uint32_t) +#define EC_IOCTL_SYNC_MON_QUEUE EC_IO(0x30) +#define EC_IOCTL_SYNC_MON_PROCESS EC_IOR(0x31, uint32_t) +#define EC_IOCTL_RESET EC_IO(0x32) +#define EC_IOCTL_SC_SYNC EC_IOW(0x33, ec_ioctl_config_t) +#define EC_IOCTL_SC_WATCHDOG EC_IOW(0x34, ec_ioctl_config_t) +#define EC_IOCTL_SC_ADD_PDO EC_IOW(0x35, ec_ioctl_config_pdo_t) +#define EC_IOCTL_SC_CLEAR_PDOS EC_IOW(0x36, ec_ioctl_config_pdo_t) +#define EC_IOCTL_SC_ADD_ENTRY EC_IOW(0x37, ec_ioctl_add_pdo_entry_t) +#define EC_IOCTL_SC_CLEAR_ENTRIES EC_IOW(0x38, ec_ioctl_config_pdo_t) +#define EC_IOCTL_SC_REG_PDO_ENTRY EC_IOWR(0x39, ec_ioctl_reg_pdo_entry_t) +#define EC_IOCTL_SC_REG_PDO_POS EC_IOWR(0x3a, ec_ioctl_reg_pdo_pos_t) +#define EC_IOCTL_SC_DC EC_IOW(0x3b, ec_ioctl_config_t) +#define EC_IOCTL_SC_SDO EC_IOW(0x3c, ec_ioctl_sc_sdo_t) +#define EC_IOCTL_SC_EMERG_SIZE EC_IOW(0x3d, ec_ioctl_sc_emerg_t) +#define EC_IOCTL_SC_EMERG_POP EC_IOWR(0x3e, ec_ioctl_sc_emerg_t) +#define EC_IOCTL_SC_EMERG_CLEAR EC_IOW(0x3f, ec_ioctl_sc_emerg_t) +#define EC_IOCTL_SC_EMERG_OVERRUNS EC_IOWR(0x40, ec_ioctl_sc_emerg_t) +#define EC_IOCTL_SC_SDO_REQUEST EC_IOWR(0x41, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SC_SOE_REQUEST EC_IOWR(0x42, ec_ioctl_soe_request_t) +#define EC_IOCTL_SC_REG_REQUEST EC_IOWR(0x43, ec_ioctl_reg_request_t) +#define EC_IOCTL_SC_VOE EC_IOWR(0x44, ec_ioctl_voe_t) +#define EC_IOCTL_SC_STATE EC_IOWR(0x45, ec_ioctl_sc_state_t) +#define EC_IOCTL_SC_IDN EC_IOW(0x46, ec_ioctl_sc_idn_t) +#define EC_IOCTL_SC_FLAG EC_IOW(0x47, ec_ioctl_sc_flag_t) +#ifdef EC_EOE +#define EC_IOCTL_SC_EOE_IP_PARAM EC_IOW(0x48, ec_ioctl_eoe_ip_t) +#endif +#define EC_IOCTL_SC_STATE_TIMEOUT EC_IOW(0x49, ec_ioctl_sc_state_timeout_t) +#define EC_IOCTL_DOMAIN_SIZE EC_IO(0x4a) +#define EC_IOCTL_DOMAIN_OFFSET EC_IO(0x4b) +#define EC_IOCTL_DOMAIN_PROCESS EC_IO(0x4c) +#define EC_IOCTL_DOMAIN_QUEUE EC_IO(0x4d) +#define EC_IOCTL_DOMAIN_STATE EC_IOWR(0x4e, ec_ioctl_domain_state_t) +#define EC_IOCTL_SDO_REQUEST_INDEX EC_IOWR(0x4f, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SDO_REQUEST_TIMEOUT EC_IOWR(0x50, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SDO_REQUEST_STATE EC_IOWR(0x51, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SDO_REQUEST_READ EC_IOWR(0x52, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SDO_REQUEST_WRITE EC_IOWR(0x53, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SDO_REQUEST_DATA EC_IOWR(0x54, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SOE_REQUEST_IDN EC_IOWR(0x55, ec_ioctl_soe_request_t) +#define EC_IOCTL_SOE_REQUEST_TIMEOUT EC_IOWR(0x56, ec_ioctl_soe_request_t) +#define EC_IOCTL_SOE_REQUEST_STATE EC_IOWR(0x57, ec_ioctl_soe_request_t) +#define EC_IOCTL_SOE_REQUEST_READ EC_IOWR(0x58, ec_ioctl_soe_request_t) +#define EC_IOCTL_SOE_REQUEST_WRITE EC_IOWR(0x59, ec_ioctl_soe_request_t) +#define EC_IOCTL_SOE_REQUEST_DATA EC_IOWR(0x5a, ec_ioctl_soe_request_t) +#define EC_IOCTL_REG_REQUEST_DATA EC_IOWR(0x5b, ec_ioctl_reg_request_t) +#define EC_IOCTL_REG_REQUEST_STATE EC_IOWR(0x5c, ec_ioctl_reg_request_t) +#define EC_IOCTL_REG_REQUEST_WRITE EC_IOWR(0x5d, ec_ioctl_reg_request_t) +#define EC_IOCTL_REG_REQUEST_READ EC_IOWR(0x5e, ec_ioctl_reg_request_t) +#define EC_IOCTL_VOE_SEND_HEADER EC_IOW(0x5f, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_REC_HEADER EC_IOWR(0x60, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_READ EC_IOW(0x61, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_READ_NOSYNC EC_IOW(0x62, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_WRITE EC_IOWR(0x63, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_EXEC EC_IOWR(0x64, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_DATA EC_IOWR(0x65, ec_ioctl_voe_t) +#define EC_IOCTL_SET_SEND_INTERVAL EC_IOW(0x66, size_t) + +/****************************************************************************/ + +#define EC_IOCTL_STRING_SIZE 64 + +/****************************************************************************/ + +typedef struct { + uint32_t ioctl_version_magic; + uint32_t master_count; +} ec_ioctl_module_t; + +/****************************************************************************/ + +typedef struct { + uint32_t slave_count; + uint32_t scan_index; + uint32_t config_count; + uint32_t domain_count; + uint32_t eoe_handler_count; + uint8_t phase; + uint8_t active; + uint8_t scan_busy; + struct ec_ioctl_device { + uint8_t address[6]; + uint8_t attached; + uint8_t link_state; + uint64_t tx_count; + uint64_t rx_count; + uint64_t tx_bytes; + uint64_t rx_bytes; + uint64_t tx_errors; + int32_t tx_frame_rates[EC_RATE_COUNT]; + int32_t rx_frame_rates[EC_RATE_COUNT]; + int32_t tx_byte_rates[EC_RATE_COUNT]; + int32_t rx_byte_rates[EC_RATE_COUNT]; + } devices[EC_MAX_NUM_DEVICES]; + uint32_t num_devices; + uint64_t tx_count; + uint64_t rx_count; + uint64_t tx_bytes; + uint64_t rx_bytes; + int32_t tx_frame_rates[EC_RATE_COUNT]; + int32_t rx_frame_rates[EC_RATE_COUNT]; + int32_t tx_byte_rates[EC_RATE_COUNT]; + int32_t rx_byte_rates[EC_RATE_COUNT]; + int32_t loss_rates[EC_RATE_COUNT]; + uint64_t app_time; + uint64_t dc_ref_time; + uint16_t ref_clock; +} ec_ioctl_master_t; + +/****************************************************************************/ + +typedef struct { + // input + uint16_t position; + + // outputs + unsigned int device_index; + uint32_t vendor_id; + uint32_t product_code; + uint32_t revision_number; + uint32_t serial_number; + uint16_t alias; + uint16_t boot_rx_mailbox_offset; + uint16_t boot_rx_mailbox_size; + uint16_t boot_tx_mailbox_offset; + uint16_t boot_tx_mailbox_size; + uint16_t std_rx_mailbox_offset; + uint16_t std_rx_mailbox_size; + uint16_t std_tx_mailbox_offset; + uint16_t std_tx_mailbox_size; + uint16_t mailbox_protocols; + uint8_t has_general_category; + ec_sii_coe_details_t coe_details; + ec_sii_general_flags_t general_flags; + int16_t current_on_ebus; + struct { + ec_slave_port_desc_t desc; + ec_slave_port_link_t link; + uint32_t receive_time; + uint16_t next_slave; + uint32_t delay_to_next_dc; + } ports[EC_MAX_PORTS]; + uint8_t fmmu_bit; + uint8_t dc_supported; + ec_slave_dc_range_t dc_range; + uint8_t has_dc_system_time; + uint32_t transmission_delay; + uint8_t al_state; + uint8_t error_flag; + uint8_t sync_count; + uint16_t sdo_count; + uint32_t sii_nwords; + char group[EC_IOCTL_STRING_SIZE]; + char image[EC_IOCTL_STRING_SIZE]; + char order[EC_IOCTL_STRING_SIZE]; + char name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_slave_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint32_t sync_index; + + // outputs + uint16_t physical_start_address; + uint16_t default_size; + uint8_t control_register; + uint8_t enable; + uint8_t pdo_count; +} ec_ioctl_slave_sync_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint32_t sync_index; + uint32_t pdo_pos; + + // outputs + uint16_t index; + uint8_t entry_count; + int8_t name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_slave_sync_pdo_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint32_t sync_index; + uint32_t pdo_pos; + uint32_t entry_pos; + + // outputs + uint16_t index; + uint8_t subindex; + uint8_t bit_length; + int8_t name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_slave_sync_pdo_entry_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t index; + + // outputs + uint32_t data_size; + uint32_t logical_base_address; + uint16_t working_counter[EC_MAX_NUM_DEVICES]; + uint16_t expected_working_counter; + uint32_t fmmu_count; +} ec_ioctl_domain_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t domain_index; + uint32_t fmmu_index; + + // outputs + uint16_t slave_config_alias; + uint16_t slave_config_position; + uint8_t sync_index; + ec_direction_t dir; + uint32_t logical_address; + uint32_t data_size; +} ec_ioctl_domain_fmmu_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t domain_index; + uint32_t data_size; + uint8_t *target; +} ec_ioctl_domain_data_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint8_t al_state; +} ec_ioctl_slave_state_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint16_t sdo_position; + + // outputs + uint16_t sdo_index; + uint8_t max_subindex; + int8_t name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_slave_sdo_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + int sdo_spec; // positive: index, negative: list position + uint8_t sdo_entry_subindex; + + // outputs + uint16_t data_type; + uint16_t bit_length; + uint8_t read_access[EC_SDO_ENTRY_ACCESS_COUNT]; + uint8_t write_access[EC_SDO_ENTRY_ACCESS_COUNT]; + int8_t description[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_slave_sdo_entry_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint16_t sdo_index; + uint8_t sdo_entry_subindex; + size_t target_size; + uint8_t *target; + + // outputs + size_t data_size; + uint32_t abort_code; +} ec_ioctl_slave_sdo_upload_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint16_t sdo_index; + uint8_t sdo_entry_subindex; + uint8_t complete_access; + size_t data_size; + uint8_t *data; + + // outputs + uint32_t abort_code; +} ec_ioctl_slave_sdo_download_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint16_t offset; + uint32_t nwords; + uint16_t *words; +} ec_ioctl_slave_sii_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint8_t emergency; + uint16_t address; + size_t size; + uint8_t *data; +} ec_ioctl_slave_reg_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint16_t offset; + size_t buffer_size; + uint8_t *buffer; + + // outputs + size_t data_size; + uint32_t result; + uint32_t error_code; + char file_name[32]; +} ec_ioctl_slave_foe_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint8_t drive_no; + uint16_t idn; + size_t mem_size; + uint8_t *data; + + // outputs + size_t data_size; + uint16_t error_code; +} ec_ioctl_slave_soe_read_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint8_t drive_no; + uint16_t idn; + size_t data_size; + uint8_t *data; + + // outputs + uint16_t error_code; +} ec_ioctl_slave_soe_write_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + + // outputs + uint16_t alias; + uint16_t position; + uint32_t vendor_id; + uint32_t product_code; + struct { + ec_direction_t dir; + ec_watchdog_mode_t watchdog_mode; + uint32_t pdo_count; + uint8_t config_this; + } syncs[EC_MAX_SYNC_MANAGERS]; + uint16_t watchdog_divider; + uint16_t watchdog_intervals; + uint32_t sdo_count; + uint32_t idn_count; + uint32_t flag_count; + int32_t slave_position; + uint16_t dc_assign_activate; + ec_sync_signal_t dc_sync[EC_SYNC_SIGNAL_COUNT]; +} ec_ioctl_config_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint8_t sync_index; + uint16_t pdo_pos; + + // outputs + uint16_t index; + uint8_t entry_count; + int8_t name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_config_pdo_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint8_t sync_index; + uint16_t pdo_pos; + uint8_t entry_pos; + + // outputs + uint16_t index; + uint8_t subindex; + uint8_t bit_length; + int8_t name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_config_pdo_entry_t; + +/****************************************************************************/ + +/** Maximum size for displayed SDO data. + * \todo Make this dynamic. + */ +#define EC_MAX_SDO_DATA_SIZE 1024 + +typedef struct { + // inputs + uint32_t config_index; + uint32_t sdo_pos; + + // outputs + uint16_t index; + uint8_t subindex; + size_t size; + uint8_t data[EC_MAX_SDO_DATA_SIZE]; + uint8_t complete_access; +} ec_ioctl_config_sdo_t; + +/****************************************************************************/ + +/** Maximum size for displayed IDN data. + * \todo Make this dynamic. + */ +#define EC_MAX_IDN_DATA_SIZE 1024 + +typedef struct { + // inputs + uint32_t config_index; + uint32_t idn_pos; + + // outputs + uint8_t drive_no; + uint16_t idn; + ec_al_state_t state; + size_t size; + uint8_t data[EC_MAX_IDN_DATA_SIZE]; +} ec_ioctl_config_idn_t; + +/****************************************************************************/ + +/** Maximum size for key. + */ +#define EC_MAX_FLAG_KEY_SIZE 128 + +typedef struct { + // inputs + uint32_t config_index; + uint32_t flag_pos; + + // outputs + char key[EC_MAX_FLAG_KEY_SIZE]; + int32_t value; +} ec_ioctl_config_flag_t; + +/****************************************************************************/ + +#ifdef EC_EOE + +typedef struct { + // input + uint16_t eoe_index; + + // outputs + char name[EC_DATAGRAM_NAME_SIZE]; + uint16_t slave_position; + uint8_t open; + uint32_t rx_bytes; + uint32_t rx_rate; + uint32_t tx_bytes; + uint32_t tx_rate; + uint32_t tx_queued_frames; + uint32_t tx_queue_size; +} ec_ioctl_eoe_handler_t; + +#endif + +/****************************************************************************/ + +#define EC_ETH_ALEN 6 +#ifdef ETH_ALEN +#if ETH_ALEN != EC_ETH_ALEN +#error Ethernet address length mismatch +#endif +#endif + +typedef struct { + // input + uint16_t slave_position; + uint16_t config_index; // alternatively + + uint8_t mac_address_included; + uint8_t ip_address_included; + uint8_t subnet_mask_included; + uint8_t gateway_included; + uint8_t dns_included; + uint8_t name_included; + + unsigned char mac_address[EC_ETH_ALEN]; + struct in_addr ip_address; + struct in_addr subnet_mask; + struct in_addr gateway; + struct in_addr dns; + char name[EC_MAX_HOSTNAME_SIZE]; + + // output + uint16_t result; +} ec_ioctl_eoe_ip_t; + +/*****************************************************************************/ + +typedef struct { + // outputs + void *process_data; + size_t process_data_size; +} ec_ioctl_master_activate_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint16_t pdo_index; + uint16_t entry_index; + uint8_t entry_subindex; + uint8_t entry_bit_length; +} ec_ioctl_add_pdo_entry_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint16_t entry_index; + uint8_t entry_subindex; + uint32_t domain_index; + + // outputs + unsigned int bit_position; +} ec_ioctl_reg_pdo_entry_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint32_t sync_index; + uint32_t pdo_pos; + uint32_t entry_pos; + uint32_t domain_index; + + // outputs + unsigned int bit_position; +} ec_ioctl_reg_pdo_pos_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint16_t index; + uint8_t subindex; + const uint8_t *data; + size_t size; + uint8_t complete_access; +} ec_ioctl_sc_sdo_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + size_t size; + uint8_t *target; + + // outputs + int32_t overruns; +} ec_ioctl_sc_emerg_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + + // outputs + ec_slave_config_state_t *state; +} ec_ioctl_sc_state_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint8_t drive_no; + uint16_t idn; + ec_al_state_t al_state; + const uint8_t *data; + size_t size; +} ec_ioctl_sc_idn_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + size_t key_size; + char *key; + int32_t value; +} ec_ioctl_sc_flag_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + ec_al_state_t from_state; + ec_al_state_t to_state; + uint32_t timeout_ms; +} ec_ioctl_sc_state_timeout_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t domain_index; + + // outputs + ec_domain_state_t *state; +} ec_ioctl_domain_state_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + + // inputs/outputs + uint32_t request_index; + uint16_t sdo_index; + uint8_t sdo_subindex; + size_t size; + uint8_t *data; + uint32_t timeout; + ec_request_state_t state; +} ec_ioctl_sdo_request_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + + // inputs/outputs + uint32_t request_index; + uint8_t drive_no; + uint16_t idn; + size_t size; + uint8_t *data; + uint32_t timeout; + ec_request_state_t state; +} ec_ioctl_soe_request_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + size_t mem_size; + + // inputs/outputs + uint32_t request_index; + uint8_t *data; + ec_request_state_t state; + uint8_t new_data; + uint16_t address; + size_t transfer_size; +} ec_ioctl_reg_request_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + + // inputs/outputs + uint32_t voe_index; + uint32_t *vendor_id; + uint16_t *vendor_type; + size_t size; + uint8_t *data; + ec_request_state_t state; +} ec_ioctl_voe_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t dev_idx; + + // outputs + ec_master_link_state_t *state; +} ec_ioctl_link_state_t; + +/****************************************************************************/ + +#ifdef __KERNEL__ + +/** Context data structure for file handles. + */ +typedef struct { + unsigned int writable; /**< Device was opened with write permission. */ + unsigned int requested; /**< Master was requested via this file handle. */ + uint8_t *process_data; /**< Total process data area. */ + size_t process_data_size; /**< Size of the \a process_data. */ +} ec_ioctl_context_t; + +long ec_ioctl(ec_master_t *, ec_ioctl_context_t *, unsigned int, + void __user *); + +#ifdef EC_RTDM + +long ec_ioctl_rtdm_rt(ec_master_t *, ec_ioctl_context_t *, unsigned int, + void __user *); +long ec_ioctl_rtdm_nrt(ec_master_t *, ec_ioctl_context_t *, unsigned int, + void __user *); + +#ifndef EC_RTDM_XENOMAI_V3 +int ec_rtdm_mmap(ec_ioctl_context_t *, void **); +#endif + +#endif + +#endif + +/****************************************************************************/ + +/** \endcond */ + +#endif diff --git a/ubuntu/igh-ecat/master/mailbox.c b/ubuntu/igh-ecat/master/mailbox.c new file mode 100644 index 00000000000000..05a10fd1c3b12c --- /dev/null +++ b/ubuntu/igh-ecat/master/mailbox.c @@ -0,0 +1,203 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Mailbox functionality. +*/ + +/****************************************************************************/ + +#include +#include + +#include "mailbox.h" +#include "datagram.h" +#include "master.h" + +/****************************************************************************/ + +/** + Prepares a mailbox-send datagram. + \return Pointer to mailbox datagram data, or ERR_PTR() code. +*/ + +uint8_t *ec_slave_mbox_prepare_send(const ec_slave_t *slave, /**< slave */ + ec_datagram_t *datagram, /**< datagram */ + uint8_t type, /**< mailbox protocol */ + size_t size /**< size of the data */ + ) +{ + size_t total_size; + int ret; + + if (unlikely(!slave->sii.mailbox_protocols)) { + EC_SLAVE_ERR(slave, "Slave does not support mailbox" + " communication!\n"); + return ERR_PTR(-EPROTONOSUPPORT); + } + + total_size = EC_MBOX_HEADER_SIZE + size; + + if (unlikely(total_size > slave->configured_rx_mailbox_size)) { + EC_SLAVE_ERR(slave, "Data size (%zu) does not fit in mailbox (%u)!\n", + total_size, slave->configured_rx_mailbox_size); + return ERR_PTR(-ENOBUFS); + } + + ret = ec_datagram_fpwr(datagram, slave->station_address, + slave->configured_rx_mailbox_offset, + slave->configured_rx_mailbox_size); + if (ret) + return ERR_PTR(ret); + + EC_WRITE_U16(datagram->data, size); // mailbox service data length + EC_WRITE_U16(datagram->data + 2, slave->station_address); // station addr. + EC_WRITE_U8 (datagram->data + 4, 0x00); // channel & priority + EC_WRITE_U8 (datagram->data + 5, type); // underlying protocol type + + return datagram->data + EC_MBOX_HEADER_SIZE; +} + +/****************************************************************************/ + +/** + Prepares a datagram for checking the mailbox state. + \todo Determine sync manager used for receive mailbox + \return 0 in case of success, else < 0 +*/ + +int ec_slave_mbox_prepare_check(const ec_slave_t *slave, /**< slave */ + ec_datagram_t *datagram /**< datagram */ + ) +{ + int ret = ec_datagram_fprd(datagram, slave->station_address, 0x808, 8); + if (ret) + return ret; + + ec_datagram_zero(datagram); + return 0; +} + +/****************************************************************************/ + +/** + Processes a mailbox state checking datagram. + \return 0 in case of success, else < 0 +*/ + +int ec_slave_mbox_check(const ec_datagram_t *datagram /**< datagram */) +{ + return EC_READ_U8(datagram->data + 5) & 8 ? 1 : 0; +} + +/****************************************************************************/ + +/** + Prepares a datagram to fetch mailbox data. + \return 0 in case of success, else < 0 +*/ + +int ec_slave_mbox_prepare_fetch(const ec_slave_t *slave, /**< slave */ + ec_datagram_t *datagram /**< datagram */ + ) +{ + int ret = ec_datagram_fprd(datagram, slave->station_address, + slave->configured_tx_mailbox_offset, + slave->configured_tx_mailbox_size); + if (ret) + return ret; + + ec_datagram_zero(datagram); + return 0; +} + +/****************************************************************************/ + +/** + Mailbox error codes. +*/ + +const ec_code_msg_t mbox_error_messages[] = { + {0x00000001, "MBXERR_SYNTAX"}, + {0x00000002, "MBXERR_UNSUPPORTEDPROTOCOL"}, + {0x00000003, "MBXERR_INVAILDCHANNEL"}, + {0x00000004, "MBXERR_SERVICENOTSUPPORTED"}, + {0x00000005, "MBXERR_INVALIDHEADER"}, + {0x00000006, "MBXERR_SIZETOOSHORT"}, + {0x00000007, "MBXERR_NOMOREMEMORY"}, + {0x00000008, "MBXERR_INVALIDSIZE"}, + {} +}; + +/****************************************************************************/ + +/** Processes received mailbox data. + * + * \return Pointer to the received data, or ERR_PTR() code. + */ +uint8_t *ec_slave_mbox_fetch(const ec_slave_t *slave, /**< slave */ + const ec_datagram_t *datagram, /**< datagram */ + uint8_t *type, /**< expected mailbox protocol */ + size_t *size /**< size of the received data */ + ) +{ + size_t data_size; + + data_size = EC_READ_U16(datagram->data); + + if (data_size + EC_MBOX_HEADER_SIZE > slave->configured_tx_mailbox_size) { + EC_SLAVE_ERR(slave, "Corrupt mailbox response received!\n"); + ec_print_data(datagram->data, slave->configured_tx_mailbox_size); + return ERR_PTR(-EPROTO); + } + + *type = EC_READ_U8(datagram->data + 5) & 0x0F; + *size = data_size; + + if (*type == 0x00) { + const ec_code_msg_t *mbox_msg; + uint16_t code = EC_READ_U16(datagram->data + 8); + + EC_SLAVE_ERR(slave, "Mailbox error response received - "); + + for (mbox_msg = mbox_error_messages; mbox_msg->code; mbox_msg++) { + if (mbox_msg->code != code) + continue; + printk(KERN_CONT "Code 0x%04X: \"%s\".\n", + mbox_msg->code, mbox_msg->message); + break; + } + + if (!mbox_msg->code) { + printk(KERN_CONT "Unknown error reply code 0x%04X.\n", code); + } + + if (slave->master->debug_level) + ec_print_data(datagram->data + EC_MBOX_HEADER_SIZE, data_size); + + return ERR_PTR(-EPROTO); + } + + return datagram->data + EC_MBOX_HEADER_SIZE; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/mailbox.h b/ubuntu/igh-ecat/master/mailbox.h new file mode 100644 index 00000000000000..e9de78cf0ab89d --- /dev/null +++ b/ubuntu/igh-ecat/master/mailbox.h @@ -0,0 +1,64 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Mailbox functionality. +*/ + +/****************************************************************************/ + +#ifndef __EC_MAILBOX_H__ +#define __EC_MAILBOX_H__ + +#include "slave.h" + +/****************************************************************************/ + +/** Size of the mailbox header. + */ +#define EC_MBOX_HEADER_SIZE 6 + +/** Mailbox types. + * + * These are used in the 'Type' field of the mailbox header. + */ +enum { + EC_MBOX_TYPE_EOE = 0x02, + EC_MBOX_TYPE_COE = 0x03, + EC_MBOX_TYPE_FOE = 0x04, + EC_MBOX_TYPE_SOE = 0x05, + EC_MBOX_TYPE_VOE = 0x0f, +}; + +/****************************************************************************/ + +uint8_t *ec_slave_mbox_prepare_send(const ec_slave_t *, ec_datagram_t *, + uint8_t, size_t); +int ec_slave_mbox_prepare_check(const ec_slave_t *, ec_datagram_t *); +int ec_slave_mbox_check(const ec_datagram_t *); +int ec_slave_mbox_prepare_fetch(const ec_slave_t *, ec_datagram_t *); +uint8_t *ec_slave_mbox_fetch(const ec_slave_t *, const ec_datagram_t *, + uint8_t *, size_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/master.c b/ubuntu/igh-ecat/master/master.c new file mode 100644 index 00000000000000..04f0cfc08c63b5 --- /dev/null +++ b/ubuntu/igh-ecat/master/master.c @@ -0,0 +1,3350 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2020 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * vim: expandtab + * + ****************************************************************************/ + +/** + \file + EtherCAT master methods. +*/ + +/****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "globals.h" +#include "slave.h" +#include "slave_config.h" +#include "device.h" +#include "datagram.h" + +#ifdef EC_EOE +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) +#include // struct sched_param +#include // sched_setscheduler +#endif +#include "ethernet.h" +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) || \ + (defined(CONFIG_PREEMPT_RT_FULL) && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) +# define ec_rt_lock_interruptible(lock) \ + rt_mutex_lock_interruptible(lock) +#else +# define ec_rt_lock_interruptible(lock) \ + rt_mutex_lock_interruptible(lock, 0) +#endif + +#include "master.h" + +/****************************************************************************/ + +/** Set to 1 to enable external datagram injection debugging. + */ +#define DEBUG_INJECT 0 + +/** Always output corrupted frames. + */ +#define FORCE_OUTPUT_CORRUPTED 0 + +/** SDO injection timeout in microseconds. */ +#define EC_SDO_INJECTION_TIMEOUT 10000 + +#ifdef EC_HAVE_CYCLES + +/** Frame timeout in cycles. + */ +static cycles_t timeout_cycles; + +/** Timeout for external datagram injection [cycles]. + */ +static cycles_t ext_injection_timeout_cycles; + +#else + +/** Frame timeout in jiffies. + */ +static unsigned long timeout_jiffies; + +/** Timeout for external datagram injection [jiffies]. + */ +static unsigned long ext_injection_timeout_jiffies; + +#endif + +/** List of intervals for statistics [s]. + */ +const unsigned int rate_intervals[] = { + 1, 10, 60 +}; + +/****************************************************************************/ + +void ec_master_clear_config(ec_master_t *); +void ec_master_clear_slave_configs(ec_master_t *); +void ec_master_clear_domains(ec_master_t *); +int ec_master_thread_start(ec_master_t *, int (*)(void *), const char *); +void ec_master_thread_stop(ec_master_t *); +void ec_master_inject_external_datagrams(ec_master_t *); +ec_datagram_t *ec_master_get_external_datagram(ec_master_t *); +void ec_master_exec_slave_fsms(ec_master_t *); +void ec_master_send_datagrams(ec_master_t *, ec_device_index_t); +int ec_master_calc_topology_rec(ec_master_t *, ec_slave_t *, unsigned int *); +void ec_master_calc_topology(ec_master_t *); +void ec_master_calc_transmission_delays(ec_master_t *); +static int ec_master_idle_thread(void *); +static int ec_master_operation_thread(void *); +#ifdef EC_EOE +static int ec_master_eoe_thread(void *); +#endif +void ec_master_find_dc_ref_clock(ec_master_t *); +void ec_master_clear_device_stats(ec_master_t *); +void ec_master_update_device_stats(ec_master_t *); +void ec_master_nanosleep(const unsigned long); +static void sc_reset_task_kicker(struct irq_work *work); +static void sc_reset_task(struct work_struct *work); + +/****************************************************************************/ + +/** Static variables initializer. +*/ +void ec_master_init_static(void) +{ +#ifdef EC_HAVE_CYCLES + timeout_cycles = (cycles_t) EC_IO_TIMEOUT /* us */ * (cpu_khz / 1000); + ext_injection_timeout_cycles = + (cycles_t) EC_SDO_INJECTION_TIMEOUT /* us */ * (cpu_khz / 1000); +#else + // one jiffy may always elapse between time measurement + timeout_jiffies = max(EC_IO_TIMEOUT * HZ / 1000000, 1); + ext_injection_timeout_jiffies = + max(EC_SDO_INJECTION_TIMEOUT * HZ / 1000000, 1); +#endif +} + +/****************************************************************************/ + +/** + Master constructor. + \return 0 in case of success, else < 0 +*/ + +int ec_master_init(ec_master_t *master, /**< EtherCAT master */ + unsigned int index, /**< master index */ + const uint8_t *main_mac, /**< MAC address of main device */ + const uint8_t *backup_mac, /**< MAC address of backup device */ + dev_t device_number, /**< Character device number. */ + struct class *class, /**< Device class. */ + unsigned int debug_level, /**< Debug level (module parameter). */ + unsigned int run_on_cpu /**< bind created kernel threads to a cpu */ + ) +{ + int ret; + unsigned int dev_idx, i; + + master->index = index; + master->reserved = 0; + + sema_init(&master->master_sem, 1); + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < EC_MAX_NUM_DEVICES; dev_idx++) { + master->macs[dev_idx] = NULL; + } + + master->macs[EC_DEVICE_MAIN] = main_mac; + +#if EC_MAX_NUM_DEVICES > 1 + master->macs[EC_DEVICE_BACKUP] = backup_mac; + master->num_devices = 1 + !ec_mac_is_zero(backup_mac); +#else + if (!ec_mac_is_zero(backup_mac)) { + EC_MASTER_WARN(master, "Ignoring backup MAC address!"); + } +#endif + + ec_master_clear_device_stats(master); + + sema_init(&master->device_sem, 1); + + master->phase = EC_ORPHANED; + master->active = 0; + master->config_changed = 0; + master->injection_seq_fsm = 0; + master->injection_seq_rt = 0; + + master->slaves = NULL; + master->slave_count = 0; + + INIT_LIST_HEAD(&master->configs); + INIT_LIST_HEAD(&master->domains); + + master->app_time = 0ULL; + master->dc_ref_time = 0ULL; + + master->scan_busy = 0; + master->scan_index = 0; + master->allow_scan = 1; + sema_init(&master->scan_sem, 1); + init_waitqueue_head(&master->scan_queue); + + master->config_busy = 0; + sema_init(&master->config_sem, 1); + init_waitqueue_head(&master->config_queue); + + INIT_LIST_HEAD(&master->datagram_queue); + master->datagram_index = 0; + + INIT_LIST_HEAD(&master->ext_datagram_queue); + sema_init(&master->ext_queue_sem, 1); + + master->ext_ring_idx_rt = 0; + master->ext_ring_idx_fsm = 0; + + // init external datagram ring + for (i = 0; i < EC_EXT_RING_SIZE; i++) { + ec_datagram_t *datagram = &master->ext_datagram_ring[i]; + ec_datagram_init(datagram); + snprintf(datagram->name, EC_DATAGRAM_NAME_SIZE, "ext-%u", i); + } + + // send interval in IDLE phase + ec_master_set_send_interval(master, 1000000 / HZ); + + master->fsm_slave = NULL; + INIT_LIST_HEAD(&master->fsm_exec_list); + master->fsm_exec_count = 0U; + + master->debug_level = debug_level; + master->run_on_cpu = run_on_cpu; + master->stats.timeouts = 0; + master->stats.corrupted = 0; + master->stats.unmatched = 0; + master->stats.output_jiffies = 0; + + master->thread = NULL; + +#ifdef EC_EOE + master->eoe_thread = NULL; + INIT_LIST_HEAD(&master->eoe_handlers); +#endif + + rt_mutex_init(&master->io_mutex); + master->send_cb = NULL; + master->receive_cb = NULL; + master->cb_data = NULL; + master->app_send_cb = NULL; + master->app_receive_cb = NULL; + master->app_cb_data = NULL; + + INIT_LIST_HEAD(&master->sii_requests); + INIT_LIST_HEAD(&master->emerg_reg_requests); + + init_waitqueue_head(&master->request_queue); + + // init devices + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + ret = ec_device_init(&master->devices[dev_idx], master); + if (ret < 0) { + goto out_clear_devices; + } + } + + // init state machine datagram + ec_datagram_init(&master->fsm_datagram); + snprintf(master->fsm_datagram.name, EC_DATAGRAM_NAME_SIZE, "master-fsm"); + ret = ec_datagram_prealloc(&master->fsm_datagram, EC_MAX_DATA_SIZE); + if (ret < 0) { + ec_datagram_clear(&master->fsm_datagram); + EC_MASTER_ERR(master, "Failed to allocate FSM datagram.\n"); + goto out_clear_devices; + } + + // create state machine object + ec_fsm_master_init(&master->fsm, master, &master->fsm_datagram); + + // alloc external datagram ring + for (i = 0; i < EC_EXT_RING_SIZE; i++) { + ec_datagram_t *datagram = &master->ext_datagram_ring[i]; + ret = ec_datagram_prealloc(datagram, EC_MAX_DATA_SIZE); + if (ret) { + EC_MASTER_ERR(master, "Failed to allocate external" + " datagram %u.\n", i); + goto out_clear_ext_datagrams; + } + } + + // init reference sync datagram + ec_datagram_init(&master->ref_sync_datagram); + snprintf(master->ref_sync_datagram.name, EC_DATAGRAM_NAME_SIZE, + "refsync"); + ret = ec_datagram_prealloc(&master->ref_sync_datagram, 4); + if (ret < 0) { + ec_datagram_clear(&master->ref_sync_datagram); + EC_MASTER_ERR(master, "Failed to allocate reference" + " synchronisation datagram.\n"); + goto out_clear_ext_datagrams; + } + + // init sync datagram + ec_datagram_init(&master->sync_datagram); + snprintf(master->sync_datagram.name, EC_DATAGRAM_NAME_SIZE, "sync"); + ret = ec_datagram_prealloc(&master->sync_datagram, 4); + if (ret < 0) { + ec_datagram_clear(&master->sync_datagram); + EC_MASTER_ERR(master, "Failed to allocate" + " synchronisation datagram.\n"); + goto out_clear_ref_sync; + } + + // init sync monitor datagram + ec_datagram_init(&master->sync_mon_datagram); + snprintf(master->sync_mon_datagram.name, EC_DATAGRAM_NAME_SIZE, + "syncmon"); + ret = ec_datagram_brd(&master->sync_mon_datagram, 0x092c, 4); + if (ret < 0) { + ec_datagram_clear(&master->sync_mon_datagram); + EC_MASTER_ERR(master, "Failed to allocate sync" + " monitoring datagram.\n"); + goto out_clear_sync; + } + + master->dc_ref_config = NULL; + master->dc_ref_clock = NULL; + + INIT_WORK(&master->sc_reset_work, sc_reset_task); + init_irq_work(&master->sc_reset_work_kicker, sc_reset_task_kicker); + + // init character device + ret = ec_cdev_init(&master->cdev, master, device_number); + if (ret) + goto out_clear_sync_mon; + + master->class_device = device_create(class, NULL, + MKDEV(MAJOR(device_number), master->index), NULL, + "EtherCAT%u", master->index); + if (IS_ERR(master->class_device)) { + EC_MASTER_ERR(master, "Failed to create class device!\n"); + ret = PTR_ERR(master->class_device); + goto out_clear_cdev; + } + +#ifdef EC_RTDM + // init RTDM device + ret = ec_rtdm_dev_init(&master->rtdm_dev, master); + if (ret) { + goto out_unregister_class_device; + } +#endif + + return 0; + +#ifdef EC_RTDM +out_unregister_class_device: + device_unregister(master->class_device); +#endif +out_clear_cdev: + ec_cdev_clear(&master->cdev); +out_clear_sync_mon: + ec_datagram_clear(&master->sync_mon_datagram); +out_clear_sync: + ec_datagram_clear(&master->sync_datagram); +out_clear_ref_sync: + ec_datagram_clear(&master->ref_sync_datagram); +out_clear_ext_datagrams: + for (i = 0; i < EC_EXT_RING_SIZE; i++) { + ec_datagram_clear(&master->ext_datagram_ring[i]); + } + ec_fsm_master_clear(&master->fsm); + ec_datagram_clear(&master->fsm_datagram); +out_clear_devices: + for (; dev_idx > 0; dev_idx--) { + ec_device_clear(&master->devices[dev_idx - 1]); + } + return ret; +} + +/****************************************************************************/ + +/** Destructor. +*/ +void ec_master_clear( + ec_master_t *master /**< EtherCAT master */ + ) +{ + unsigned int dev_idx, i; + +#ifdef EC_RTDM + ec_rtdm_dev_clear(&master->rtdm_dev); +#endif + + device_unregister(master->class_device); + + ec_cdev_clear(&master->cdev); + + irq_work_sync(&master->sc_reset_work_kicker); + cancel_work_sync(&master->sc_reset_work); + +#ifdef EC_EOE + ec_master_clear_eoe_handlers(master); +#endif + ec_master_clear_domains(master); + ec_master_clear_slave_configs(master); + ec_master_clear_slaves(master); + + ec_datagram_clear(&master->sync_mon_datagram); + ec_datagram_clear(&master->sync_datagram); + ec_datagram_clear(&master->ref_sync_datagram); + + for (i = 0; i < EC_EXT_RING_SIZE; i++) { + ec_datagram_clear(&master->ext_datagram_ring[i]); + } + + ec_fsm_master_clear(&master->fsm); + ec_datagram_clear(&master->fsm_datagram); + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + ec_device_clear(&master->devices[dev_idx]); + } +} + +/****************************************************************************/ + +#ifdef EC_EOE +/** Clear and free all EoE handlers. + */ +void ec_master_clear_eoe_handlers( + ec_master_t *master /**< EtherCAT master */ + ) +{ + ec_eoe_t *eoe, *next; + + list_for_each_entry_safe(eoe, next, &master->eoe_handlers, list) { + list_del(&eoe->list); + ec_eoe_clear(eoe); + kfree(eoe); + } +} +#endif + +/****************************************************************************/ + +/** Clear all slave configurations. + */ +void ec_master_clear_slave_configs(ec_master_t *master) +{ + ec_slave_config_t *sc, *next; + + master->dc_ref_config = NULL; + master->fsm.sdo_request = NULL; // mark sdo_request as invalid + + list_for_each_entry_safe(sc, next, &master->configs, list) { + list_del(&sc->list); + ec_slave_config_clear(sc); + kfree(sc); + } +} + +/****************************************************************************/ + +/** Clear all slaves. + */ +void ec_master_clear_slaves(ec_master_t *master) +{ + ec_slave_t *slave; + + master->dc_ref_clock = NULL; + + // External requests are obsolete, so we wake pending waiters and remove + // them from the list. + + while (!list_empty(&master->sii_requests)) { + ec_sii_write_request_t *request = + list_entry(master->sii_requests.next, + ec_sii_write_request_t, list); + list_del_init(&request->list); // dequeue + EC_MASTER_WARN(master, "Discarding SII request, slave %u about" + " to be deleted.\n", request->slave->ring_position); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&master->request_queue); + } + + master->fsm_slave = NULL; + INIT_LIST_HEAD(&master->fsm_exec_list); + master->fsm_exec_count = 0; + + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + ec_slave_clear(slave); + } + + if (master->slaves) { + kfree(master->slaves); + master->slaves = NULL; + } + + master->slave_count = 0; +} + +/****************************************************************************/ + +/** Clear all domains. + */ +void ec_master_clear_domains(ec_master_t *master) +{ + ec_domain_t *domain, *next; + + list_for_each_entry_safe(domain, next, &master->domains, list) { + list_del(&domain->list); + ec_domain_clear(domain); + kfree(domain); + } +} + +/****************************************************************************/ + +/** Clear the configuration applied by the application. + */ +void ec_master_clear_config( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + down(&master->master_sem); + ec_master_clear_domains(master); + ec_master_clear_slave_configs(master); + up(&master->master_sem); +} + +/****************************************************************************/ + +/** Internal sending callback. + */ +void ec_master_internal_send_cb( + void *cb_data /**< Callback data. */ + ) +{ + ec_master_t *master = (ec_master_t *) cb_data; + if (ec_rt_lock_interruptible(&master->io_mutex)) + return; + ecrt_master_send_ext(master); + rt_mutex_unlock(&master->io_mutex); +} + +/****************************************************************************/ + +/** Internal receiving callback. + */ +void ec_master_internal_receive_cb( + void *cb_data /**< Callback data. */ + ) +{ + ec_master_t *master = (ec_master_t *) cb_data; + if (ec_rt_lock_interruptible(&master->io_mutex)) + return; + ecrt_master_receive(master); + rt_mutex_unlock(&master->io_mutex); +} + +/****************************************************************************/ + +/** Starts the master thread. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_master_thread_start( + ec_master_t *master, /**< EtherCAT master */ + int (*thread_func)(void *), /**< thread function to start */ + const char *name /**< Thread name. */ + ) +{ + EC_MASTER_INFO(master, "Starting %s thread.\n", name); + master->thread = kthread_create(thread_func, master, name); + if (IS_ERR(master->thread)) { + int err = (int) PTR_ERR(master->thread); + EC_MASTER_ERR(master, "Failed to start master thread (error %i)!\n", + err); + master->thread = NULL; + return err; + } + if (0xffffffff != master->run_on_cpu) { + EC_MASTER_INFO(master, " binding thread to cpu %u\n",master->run_on_cpu); + kthread_bind(master->thread,master->run_on_cpu); + } + /* Ignoring return value of wake_up_process */ + (void) wake_up_process(master->thread); + + return 0; +} + +/****************************************************************************/ + +/** Stops the master thread. + */ +void ec_master_thread_stop( + ec_master_t *master /**< EtherCAT master */ + ) +{ + unsigned long sleep_jiffies; + + if (!master->thread) { + EC_MASTER_WARN(master, "%s(): Already finished!\n", __func__); + return; + } + + EC_MASTER_DBG(master, 1, "Stopping master thread.\n"); + + kthread_stop(master->thread); + master->thread = NULL; + EC_MASTER_INFO(master, "Master thread exited.\n"); + + if (master->fsm_datagram.state != EC_DATAGRAM_SENT) { + return; + } + + // wait for FSM datagram + sleep_jiffies = max(HZ / 100, 1); // 10 ms, at least 1 jiffy + schedule_timeout(sleep_jiffies); +} + +/****************************************************************************/ + +/** Transition function from ORPHANED to IDLE phase. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_master_enter_idle_phase( + ec_master_t *master /**< EtherCAT master */ + ) +{ + int ret; + ec_device_index_t dev_idx; + + EC_MASTER_DBG(master, 1, "ORPHANED -> IDLE.\n"); + + master->send_cb = ec_master_internal_send_cb; + master->receive_cb = ec_master_internal_receive_cb; + master->cb_data = master; + + master->phase = EC_IDLE; + + // reset number of responding slaves to trigger scanning + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + master->fsm.slaves_responding[dev_idx] = 0; + } + + ret = ec_master_thread_start(master, ec_master_idle_thread, + "EtherCAT-IDLE"); + if (ret) + master->phase = EC_ORPHANED; + + return ret; +} + +/****************************************************************************/ + +/** Transition function from IDLE to ORPHANED phase. + */ +void ec_master_leave_idle_phase(ec_master_t *master /**< EtherCAT master */) +{ + EC_MASTER_DBG(master, 1, "IDLE -> ORPHANED.\n"); + + master->phase = EC_ORPHANED; + +#ifdef EC_EOE + ec_master_eoe_stop(master); +#endif + ec_master_thread_stop(master); + + down(&master->master_sem); + ec_master_clear_slaves(master); + up(&master->master_sem); + + ec_fsm_master_reset(&master->fsm); +} + +/****************************************************************************/ + +/** Transition function from IDLE to OPERATION phase. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_master_enter_operation_phase( + ec_master_t *master /**< EtherCAT master */ + ) +{ + int ret = 0; + ec_slave_t *slave; + + EC_MASTER_DBG(master, 1, "IDLE -> OPERATION.\n"); + + down(&master->config_sem); + if (master->config_busy) { + up(&master->config_sem); + + // wait for slave configuration to complete + ret = wait_event_interruptible(master->config_queue, + !master->config_busy); + if (ret) { + EC_MASTER_INFO(master, "Finishing slave configuration" + " interrupted by signal.\n"); + goto out_return; + } + + EC_MASTER_DBG(master, 1, "Waiting for pending slave" + " configuration returned.\n"); + } else { + up(&master->config_sem); + } + + down(&master->scan_sem); + master->allow_scan = 0; // 'lock' the slave list + if (!master->scan_busy) { + up(&master->scan_sem); + } else { + up(&master->scan_sem); + + // wait for slave scan to complete + ret = wait_event_interruptible(master->scan_queue, + !master->scan_busy); + if (ret) { + EC_MASTER_INFO(master, "Waiting for slave scan" + " interrupted by signal.\n"); + goto out_allow; + } + + EC_MASTER_DBG(master, 1, "Waiting for pending" + " slave scan returned.\n"); + } + + // set states for all slaves + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + ec_slave_request_state(slave, EC_SLAVE_STATE_PREOP); + } + + master->phase = EC_OPERATION; + master->app_send_cb = NULL; + master->app_receive_cb = NULL; + master->app_cb_data = NULL; + return ret; + +out_allow: + master->allow_scan = 1; +out_return: + return ret; +} + +/****************************************************************************/ + +/** Transition function from OPERATION to IDLE phase. + */ +void ec_master_leave_operation_phase( + ec_master_t *master /**< EtherCAT master */ + ) +{ + if (master->active) { + ecrt_master_deactivate(master); // also clears config + } else { + ec_master_clear_config(master); + } + + /* Re-allow scanning for IDLE phase. */ + master->allow_scan = 1; + + EC_MASTER_DBG(master, 1, "OPERATION -> IDLE.\n"); + + master->phase = EC_IDLE; +} + +/****************************************************************************/ + +/** Injects external datagrams that fit into the datagram queue. + */ +void ec_master_inject_external_datagrams( + ec_master_t *master /**< EtherCAT master */ + ) +{ + ec_datagram_t *datagram; + size_t queue_size = 0, new_queue_size = 0; +#if DEBUG_INJECT + unsigned int datagram_count = 0; +#endif + + if (master->ext_ring_idx_rt == master->ext_ring_idx_fsm) { + // nothing to inject + return; + } + + list_for_each_entry(datagram, &master->datagram_queue, queue) { + if (datagram->state == EC_DATAGRAM_QUEUED) { + queue_size += datagram->data_size; + } + } + +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "Injecting datagrams, queue_size=%zu\n", + queue_size); +#endif + + while (master->ext_ring_idx_rt != master->ext_ring_idx_fsm) { + datagram = &master->ext_datagram_ring[master->ext_ring_idx_rt]; + + if (datagram->state != EC_DATAGRAM_INIT) { + // skip datagram + master->ext_ring_idx_rt = + (master->ext_ring_idx_rt + 1) % EC_EXT_RING_SIZE; + continue; + } + + new_queue_size = queue_size + datagram->data_size; + if (new_queue_size <= master->max_queue_size) { +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "Injecting datagram %s" + " size=%zu, queue_size=%zu\n", datagram->name, + datagram->data_size, new_queue_size); + datagram_count++; +#endif +#ifdef EC_HAVE_CYCLES + datagram->cycles_sent = 0; +#endif + datagram->jiffies_sent = 0; + ec_master_queue_datagram(master, datagram); + queue_size = new_queue_size; + } + else if (datagram->data_size > master->max_queue_size) { + datagram->state = EC_DATAGRAM_ERROR; + EC_MASTER_ERR(master, "External datagram %s is too large," + " size=%zu, max_queue_size=%zu\n", + datagram->name, datagram->data_size, + master->max_queue_size); + } + else { // datagram does not fit in the current cycle +#ifdef EC_HAVE_CYCLES + cycles_t cycles_now = get_cycles(); + + if (cycles_now - datagram->cycles_sent + > ext_injection_timeout_cycles) +#else + if (jiffies - datagram->jiffies_sent + > ext_injection_timeout_jiffies) +#endif + { +#if defined EC_RT_SYSLOG || DEBUG_INJECT + unsigned int time_us; +#endif + + datagram->state = EC_DATAGRAM_ERROR; + +#if defined EC_RT_SYSLOG || DEBUG_INJECT +#ifdef EC_HAVE_CYCLES + time_us = (unsigned int) + ((cycles_now - datagram->cycles_sent) * 1000LL) + / cpu_khz; +#else + time_us = (unsigned int) + ((jiffies - datagram->jiffies_sent) * 1000000 / HZ); +#endif + EC_MASTER_ERR(master, "Timeout %u us: Injecting" + " external datagram %s size=%zu," + " max_queue_size=%zu\n", time_us, datagram->name, + datagram->data_size, master->max_queue_size); +#endif + } + else { +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "Deferred injecting" + " external datagram %s size=%u, queue_size=%u\n", + datagram->name, datagram->data_size, queue_size); +#endif + break; + } + } + + master->ext_ring_idx_rt = + (master->ext_ring_idx_rt + 1) % EC_EXT_RING_SIZE; + } + +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "Injected %u datagrams.\n", datagram_count); +#endif +} + +/****************************************************************************/ + +/** Sets the expected interval between calls to ecrt_master_send + * and calculates the maximum amount of data to queue. + */ +void ec_master_set_send_interval( + ec_master_t *master, /**< EtherCAT master */ + unsigned int send_interval /**< Send interval */ + ) +{ + master->send_interval = send_interval; + master->max_queue_size = + (send_interval * 1000) / EC_BYTE_TRANSMISSION_TIME_NS; + master->max_queue_size -= master->max_queue_size / 10; +} + +/****************************************************************************/ + +/** Searches for a free datagram in the external datagram ring. + * + * \return Next free datagram, or NULL. + */ +ec_datagram_t *ec_master_get_external_datagram( + ec_master_t *master /**< EtherCAT master */ + ) +{ + if ((master->ext_ring_idx_fsm + 1) % EC_EXT_RING_SIZE != + master->ext_ring_idx_rt) { + ec_datagram_t *datagram = + &master->ext_datagram_ring[master->ext_ring_idx_fsm]; + return datagram; + } + else { + return NULL; + } +} + +/****************************************************************************/ + +/** Places a datagram in the datagram queue. + */ +void ec_master_queue_datagram( + ec_master_t *master, /**< EtherCAT master */ + ec_datagram_t *datagram /**< datagram */ + ) +{ + ec_datagram_t *queued_datagram; + + /* It is possible, that a datagram in the queue is re-initialized with the + * ec_datagram_() methods and then shall be queued with this method. + * In that case, the state is already reset to EC_DATAGRAM_INIT. Check if + * the datagram is queued to avoid duplicate queuing (which results in an + * infinite loop!). Set the state to EC_DATAGRAM_QUEUED again, probably + * causing an unmatched datagram. */ + list_for_each_entry(queued_datagram, &master->datagram_queue, queue) { + if (queued_datagram == datagram) { + datagram->skip_count++; +#ifdef EC_RT_SYSLOG + EC_MASTER_DBG(master, 1, + "Datagram %p already queued (skipping).\n", datagram); +#endif + datagram->state = EC_DATAGRAM_QUEUED; + return; + } + } + + list_add_tail(&datagram->queue, &master->datagram_queue); + datagram->state = EC_DATAGRAM_QUEUED; +} + +/****************************************************************************/ + +/** Places a datagram in the non-application datagram queue. + */ +void ec_master_queue_datagram_ext( + ec_master_t *master, /**< EtherCAT master */ + ec_datagram_t *datagram /**< datagram */ + ) +{ + down(&master->ext_queue_sem); + list_add_tail(&datagram->ext_queue, &master->ext_datagram_queue); + up(&master->ext_queue_sem); +} + +/****************************************************************************/ + +/** Sends the datagrams in the queue for a certain device. + * + */ +void ec_master_send_datagrams( + ec_master_t *master, /**< EtherCAT master */ + ec_device_index_t device_index /**< Device index. */ + ) +{ + ec_datagram_t *datagram, *next; + size_t datagram_size; + uint8_t *frame_data, *cur_data = NULL; + void *follows_word; +#ifdef EC_HAVE_CYCLES + cycles_t cycles_start, cycles_sent, cycles_end; +#endif + unsigned long jiffies_sent; + unsigned int frame_count, more_datagrams_waiting; + struct list_head sent_datagrams; + +#ifdef EC_HAVE_CYCLES + cycles_start = get_cycles(); +#endif + frame_count = 0; + INIT_LIST_HEAD(&sent_datagrams); + + EC_MASTER_DBG(master, 2, "%s(device_index = %u)\n", + __func__, device_index); + + do { + frame_data = NULL; + follows_word = NULL; + more_datagrams_waiting = 0; + + // fill current frame with datagrams + list_for_each_entry(datagram, &master->datagram_queue, queue) { + if (datagram->state != EC_DATAGRAM_QUEUED || + datagram->device_index != device_index) { + continue; + } + + if (!frame_data) { + // fetch pointer to transmit socket buffer + frame_data = + ec_device_tx_data(&master->devices[device_index]); + cur_data = frame_data + EC_FRAME_HEADER_SIZE; + } + + // does the current datagram fit in the frame? + datagram_size = EC_DATAGRAM_HEADER_SIZE + datagram->data_size + + EC_DATAGRAM_FOOTER_SIZE; + if (cur_data - frame_data + datagram_size > ETH_DATA_LEN) { + more_datagrams_waiting = 1; + break; + } + + list_add_tail(&datagram->sent, &sent_datagrams); + datagram->index = master->datagram_index++; + + EC_MASTER_DBG(master, 2, "Adding datagram 0x%02X\n", + datagram->index); + + // set "datagram following" flag in previous datagram + if (follows_word) { + EC_WRITE_U16(follows_word, + EC_READ_U16(follows_word) | 0x8000); + } + + // EtherCAT datagram header + EC_WRITE_U8 (cur_data, datagram->type); + EC_WRITE_U8 (cur_data + 1, datagram->index); + memcpy(cur_data + 2, datagram->address, EC_ADDR_LEN); + EC_WRITE_U16(cur_data + 6, datagram->data_size & 0x7FF); + EC_WRITE_U16(cur_data + 8, 0x0000); + follows_word = cur_data + 6; + cur_data += EC_DATAGRAM_HEADER_SIZE; + + // EtherCAT datagram data + memcpy(cur_data, datagram->data, datagram->data_size); + cur_data += datagram->data_size; + + // EtherCAT datagram footer + EC_WRITE_U16(cur_data, 0x0000); // reset working counter + cur_data += EC_DATAGRAM_FOOTER_SIZE; + } + + if (list_empty(&sent_datagrams)) { + EC_MASTER_DBG(master, 2, "nothing to send.\n"); + break; + } + + // EtherCAT frame header + EC_WRITE_U16(frame_data, ((cur_data - frame_data + - EC_FRAME_HEADER_SIZE) & 0x7FF) | 0x1000); + + // pad frame + while (cur_data - frame_data < ETH_ZLEN - ETH_HLEN) + EC_WRITE_U8(cur_data++, 0x00); + + EC_MASTER_DBG(master, 2, "frame size: %zu\n", cur_data - frame_data); + + // send frame + ec_device_send(&master->devices[device_index], + cur_data - frame_data); +#ifdef EC_HAVE_CYCLES + cycles_sent = get_cycles(); +#endif + jiffies_sent = jiffies; + + // set datagram states and sending timestamps + list_for_each_entry_safe(datagram, next, &sent_datagrams, sent) { + datagram->state = EC_DATAGRAM_SENT; +#ifdef EC_HAVE_CYCLES + datagram->cycles_sent = cycles_sent; +#endif + datagram->jiffies_sent = jiffies_sent; + list_del_init(&datagram->sent); // empty list of sent datagrams + } + + frame_count++; + } + while (more_datagrams_waiting); + +#ifdef EC_HAVE_CYCLES + if (unlikely(master->debug_level > 1)) { + cycles_end = get_cycles(); + EC_MASTER_DBG(master, 0, "%s()" + " sent %u frames in %uus.\n", __func__, frame_count, + (unsigned int) (cycles_end - cycles_start) * 1000 / cpu_khz); + } +#endif +} + +/****************************************************************************/ + +/** Processes a received frame. + * + * This function is called by the network driver for every received frame. + * + * \return 0 in case of success, else < 0 + */ +void ec_master_receive_datagrams( + ec_master_t *master, /**< EtherCAT master */ + ec_device_t *device, /**< EtherCAT device */ + const uint8_t *frame_data, /**< frame data */ + size_t size /**< size of the received data */ + ) +{ + size_t frame_size, data_size; + uint8_t datagram_type, datagram_index; + unsigned int cmd_follows, matched; + const uint8_t *cur_data; + ec_datagram_t *datagram; + + if (unlikely(size < EC_FRAME_HEADER_SIZE)) { + if (master->debug_level || FORCE_OUTPUT_CORRUPTED) { + EC_MASTER_DBG(master, 0, "Corrupted frame received" + " on %s (size %zu < %u byte):\n", + device->dev->name, size, EC_FRAME_HEADER_SIZE); + ec_print_data(frame_data, size); + } + master->stats.corrupted++; +#ifdef EC_RT_SYSLOG + ec_master_output_stats(master); +#endif + return; + } + + cur_data = frame_data; + + // check length of entire frame + frame_size = EC_READ_U16(cur_data) & 0x07FF; + cur_data += EC_FRAME_HEADER_SIZE; + + if (unlikely(frame_size > size)) { + if (master->debug_level || FORCE_OUTPUT_CORRUPTED) { + EC_MASTER_DBG(master, 0, "Corrupted frame received" + " on %s (invalid frame size %zu for " + "received size %zu):\n", device->dev->name, + frame_size, size); + ec_print_data(frame_data, size); + } + master->stats.corrupted++; +#ifdef EC_RT_SYSLOG + ec_master_output_stats(master); +#endif + return; + } + + cmd_follows = 1; + while (cmd_follows) { + // process datagram header + datagram_type = EC_READ_U8 (cur_data); + datagram_index = EC_READ_U8 (cur_data + 1); + data_size = EC_READ_U16(cur_data + 6) & 0x07FF; + cmd_follows = EC_READ_U16(cur_data + 6) & 0x8000; + cur_data += EC_DATAGRAM_HEADER_SIZE; + + if (unlikely(cur_data - frame_data + + data_size + EC_DATAGRAM_FOOTER_SIZE > size)) { + if (master->debug_level || FORCE_OUTPUT_CORRUPTED) { + EC_MASTER_DBG(master, 0, "Corrupted frame received" + " on %s (invalid data size %zu):\n", + device->dev->name, data_size); + ec_print_data(frame_data, size); + } + master->stats.corrupted++; +#ifdef EC_RT_SYSLOG + ec_master_output_stats(master); +#endif + return; + } + + // search for matching datagram in the queue + matched = 0; + list_for_each_entry(datagram, &master->datagram_queue, queue) { + if (datagram->index == datagram_index + && datagram->state == EC_DATAGRAM_SENT + && datagram->type == datagram_type + && datagram->data_size == data_size) { + matched = 1; + break; + } + } + + // no matching datagram was found + if (!matched) { + master->stats.unmatched++; +#ifdef EC_RT_SYSLOG + ec_master_output_stats(master); +#endif + + if (unlikely(master->debug_level > 0)) { + EC_MASTER_DBG(master, 0, "UNMATCHED datagram:\n"); + ec_print_data(cur_data - EC_DATAGRAM_HEADER_SIZE, + EC_DATAGRAM_HEADER_SIZE + data_size + + EC_DATAGRAM_FOOTER_SIZE); +#ifdef EC_DEBUG_RING + ec_device_debug_ring_print(&master->devices[EC_DEVICE_MAIN]); +#endif + } + + cur_data += data_size + EC_DATAGRAM_FOOTER_SIZE; + continue; + } + + if (datagram->type != EC_DATAGRAM_APWR && + datagram->type != EC_DATAGRAM_FPWR && + datagram->type != EC_DATAGRAM_BWR && + datagram->type != EC_DATAGRAM_LWR) { + // copy received data into the datagram memory, + // if something has been read + memcpy(datagram->data, cur_data, data_size); + } + cur_data += data_size; + + // set the datagram's working counter + datagram->working_counter = EC_READ_U16(cur_data); + cur_data += EC_DATAGRAM_FOOTER_SIZE; + + // dequeue the received datagram + datagram->state = EC_DATAGRAM_RECEIVED; +#ifdef EC_HAVE_CYCLES + datagram->cycles_received = + master->devices[EC_DEVICE_MAIN].cycles_poll; +#endif + datagram->jiffies_received = + master->devices[EC_DEVICE_MAIN].jiffies_poll; + list_del_init(&datagram->queue); + } +} + +/****************************************************************************/ + +/** Output master statistics. + * + * This function outputs statistical data on demand, but not more often than + * necessary. The output happens at most once a second. + */ +void ec_master_output_stats(ec_master_t *master /**< EtherCAT master */) +{ + if (unlikely(jiffies - master->stats.output_jiffies >= HZ)) { + master->stats.output_jiffies = jiffies; + + if (master->stats.timeouts) { + EC_MASTER_WARN(master, "%u datagram%s TIMED OUT!\n", + master->stats.timeouts, + master->stats.timeouts == 1 ? "" : "s"); + master->stats.timeouts = 0; + } + if (master->stats.corrupted) { + EC_MASTER_WARN(master, "%u frame%s CORRUPTED!\n", + master->stats.corrupted, + master->stats.corrupted == 1 ? "" : "s"); + master->stats.corrupted = 0; + } + if (master->stats.unmatched) { + EC_MASTER_WARN(master, "%u datagram%s UNMATCHED!\n", + master->stats.unmatched, + master->stats.unmatched == 1 ? "" : "s"); + master->stats.unmatched = 0; + } + } +} + +/****************************************************************************/ + +/** Clears the common device statistics. + */ +void ec_master_clear_device_stats( + ec_master_t *master /**< EtherCAT master */ + ) +{ + unsigned int i; + + // zero frame statistics + master->device_stats.tx_count = 0; + master->device_stats.last_tx_count = 0; + master->device_stats.rx_count = 0; + master->device_stats.last_rx_count = 0; + master->device_stats.tx_bytes = 0; + master->device_stats.last_tx_bytes = 0; + master->device_stats.rx_bytes = 0; + master->device_stats.last_rx_bytes = 0; + master->device_stats.last_loss = 0; + + for (i = 0; i < EC_RATE_COUNT; i++) { + master->device_stats.tx_frame_rates[i] = 0; + master->device_stats.rx_frame_rates[i] = 0; + master->device_stats.tx_byte_rates[i] = 0; + master->device_stats.rx_byte_rates[i] = 0; + master->device_stats.loss_rates[i] = 0; + } + + master->device_stats.jiffies = 0; +} + +/****************************************************************************/ + +/** Updates the common device statistics. + */ +void ec_master_update_device_stats( + ec_master_t *master /**< EtherCAT master */ + ) +{ + ec_device_stats_t *s = &master->device_stats; + s32 tx_frame_rate, rx_frame_rate, tx_byte_rate, rx_byte_rate, loss_rate; + u64 loss; + unsigned int i, dev_idx; + + // frame statistics + if (likely(jiffies - s->jiffies < HZ)) { + return; + } + + tx_frame_rate = (s->tx_count - s->last_tx_count) * 1000; + rx_frame_rate = (s->rx_count - s->last_rx_count) * 1000; + tx_byte_rate = s->tx_bytes - s->last_tx_bytes; + rx_byte_rate = s->rx_bytes - s->last_rx_bytes; + loss = s->tx_count - s->rx_count; + loss_rate = (loss - s->last_loss) * 1000; + + /* Low-pass filter: + * Y_n = y_(n - 1) + T / tau * (x - y_(n - 1)) | T = 1 + * -> Y_n += (x - y_(n - 1)) / tau + */ + for (i = 0; i < EC_RATE_COUNT; i++) { + s32 n = rate_intervals[i]; + s->tx_frame_rates[i] += (tx_frame_rate - s->tx_frame_rates[i]) / n; + s->rx_frame_rates[i] += (rx_frame_rate - s->rx_frame_rates[i]) / n; + s->tx_byte_rates[i] += (tx_byte_rate - s->tx_byte_rates[i]) / n; + s->rx_byte_rates[i] += (rx_byte_rate - s->rx_byte_rates[i]) / n; + s->loss_rates[i] += (loss_rate - s->loss_rates[i]) / n; + } + + s->last_tx_count = s->tx_count; + s->last_rx_count = s->rx_count; + s->last_tx_bytes = s->tx_bytes; + s->last_rx_bytes = s->rx_bytes; + s->last_loss = loss; + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + ec_device_update_stats(&master->devices[dev_idx]); + } + + s->jiffies = jiffies; +} + +/****************************************************************************/ + +#ifdef EC_USE_HRTIMER + +/* + * Sleep related functions: + */ +static enum hrtimer_restart ec_master_nanosleep_wakeup(struct hrtimer *timer) +{ + struct hrtimer_sleeper *t = + container_of(timer, struct hrtimer_sleeper, timer); + struct task_struct *task = t->task; + + t->task = NULL; + if (task) + wake_up_process(task); + + return HRTIMER_NORESTART; +} + +/****************************************************************************/ + +void ec_master_nanosleep(const unsigned long nsecs) +{ + struct hrtimer_sleeper t; + enum hrtimer_mode mode = HRTIMER_MODE_REL; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 15, 0) + hrtimer_setup(&t.timer, ec_master_nanosleep_wakeup, + CLOCK_MONOTONIC, mode); +#else + hrtimer_init(&t.timer, CLOCK_MONOTONIC, mode); + t.timer.function = ec_master_nanosleep_wakeup; +#endif + t.task = current; + hrtimer_set_expires(&t.timer, ktime_set(0, nsecs)); + + do { + set_current_state(TASK_INTERRUPTIBLE); + hrtimer_start(&t.timer, hrtimer_get_expires(&t.timer), mode); + + if (likely(t.task)) + schedule(); + + hrtimer_cancel(&t.timer); + mode = HRTIMER_MODE_ABS; + + } while (t.task && !signal_pending(current)); +} + +#endif // EC_USE_HRTIMER + +/****************************************************************************/ + +/** Execute slave FSMs. + */ +void ec_master_exec_slave_fsms( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + ec_datagram_t *datagram; + ec_fsm_slave_t *fsm, *next; + unsigned int count = 0; + + list_for_each_entry_safe(fsm, next, &master->fsm_exec_list, list) { + if (!fsm->datagram) { + EC_MASTER_WARN(master, "Slave %u FSM has zero datagram." + "This is a bug!\n", fsm->slave->ring_position); + list_del_init(&fsm->list); + master->fsm_exec_count--; + return; + } + + if (fsm->datagram->state == EC_DATAGRAM_INIT || + fsm->datagram->state == EC_DATAGRAM_QUEUED || + fsm->datagram->state == EC_DATAGRAM_SENT) { + // previous datagram was not sent or received yet. + // wait until next thread execution + return; + } + + datagram = ec_master_get_external_datagram(master); + if (!datagram) { + // no free datagrams at the moment + EC_MASTER_WARN(master, "No free datagram during" + " slave FSM execution. This is a bug!\n"); + continue; + } + +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "Executing slave %u FSM.\n", + fsm->slave->ring_position); +#endif + if (ec_fsm_slave_exec(fsm, datagram)) { + // FSM consumed datagram +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "FSM consumed datagram %s\n", + datagram->name); +#endif + master->ext_ring_idx_fsm = + (master->ext_ring_idx_fsm + 1) % EC_EXT_RING_SIZE; + } + else { + // FSM finished + list_del_init(&fsm->list); + master->fsm_exec_count--; +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "FSM finished. %u remaining.\n", + master->fsm_exec_count); +#endif + } + } + + while (master->fsm_exec_count < EC_EXT_RING_SIZE / 2 + && count < master->slave_count) { + + if (ec_fsm_slave_is_ready(&master->fsm_slave->fsm)) { + datagram = ec_master_get_external_datagram(master); + + if (ec_fsm_slave_exec(&master->fsm_slave->fsm, datagram)) { + master->ext_ring_idx_fsm = + (master->ext_ring_idx_fsm + 1) % EC_EXT_RING_SIZE; + list_add_tail(&master->fsm_slave->fsm.list, + &master->fsm_exec_list); + master->fsm_exec_count++; +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "New slave %u FSM" + " consumed datagram %s, now %u FSMs in list.\n", + master->fsm_slave->ring_position, datagram->name, + master->fsm_exec_count); +#endif + } + } + + master->fsm_slave++; + if (master->fsm_slave >= master->slaves + master->slave_count) { + master->fsm_slave = master->slaves; + } + count++; + } +} + +/****************************************************************************/ + +/** Master kernel thread function for IDLE phase. + */ +static int ec_master_idle_thread(void *priv_data) +{ + ec_master_t *master = (ec_master_t *) priv_data; + int fsm_exec; +#ifdef EC_USE_HRTIMER + size_t sent_bytes; +#endif + + // send interval in IDLE phase + ec_master_set_send_interval(master, 1000000 / HZ); + + EC_MASTER_DBG(master, 1, "Idle thread running with send interval = %u us," + " max data size=%zu\n", master->send_interval, + master->max_queue_size); + + while (!kthread_should_stop()) { + ec_datagram_output_stats(&master->fsm_datagram); + + // receive + if (ec_rt_lock_interruptible(&master->io_mutex)) + break; + ecrt_master_receive(master); + rt_mutex_unlock(&master->io_mutex); + + // execute master & slave state machines + if (down_interruptible(&master->master_sem)) { + break; + } + + fsm_exec = ec_fsm_master_exec(&master->fsm); + + ec_master_exec_slave_fsms(master); + + up(&master->master_sem); + + // queue and send + if (ec_rt_lock_interruptible(&master->io_mutex)) + break; + if (fsm_exec) { + ec_master_queue_datagram(master, &master->fsm_datagram); + } + ecrt_master_send(master); +#ifdef EC_USE_HRTIMER + sent_bytes = master->devices[EC_DEVICE_MAIN].tx_skb[ + master->devices[EC_DEVICE_MAIN].tx_ring_index]->len; +#endif + rt_mutex_unlock(&master->io_mutex); + + if (ec_fsm_master_idle(&master->fsm)) { +#ifdef EC_USE_HRTIMER + ec_master_nanosleep(master->send_interval * 1000); +#else + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); +#endif + } else { +#ifdef EC_USE_HRTIMER + ec_master_nanosleep(sent_bytes * EC_BYTE_TRANSMISSION_TIME_NS); +#else + schedule(); +#endif + } + } + + EC_MASTER_DBG(master, 1, "Master IDLE thread exiting...\n"); + + return 0; +} + +/****************************************************************************/ + +/** Master kernel thread function for OPERATION phase. + */ +static int ec_master_operation_thread(void *priv_data) +{ + ec_master_t *master = (ec_master_t *) priv_data; + + EC_MASTER_DBG(master, 1, "Operation thread running" + " with fsm interval = %u us, max data size=%zu\n", + master->send_interval, master->max_queue_size); + + while (!kthread_should_stop()) { + ec_datagram_output_stats(&master->fsm_datagram); + + if (master->injection_seq_rt == master->injection_seq_fsm) { + // output statistics + ec_master_output_stats(master); + + // execute master & slave state machines + if (down_interruptible(&master->master_sem)) { + break; + } + + if (ec_fsm_master_exec(&master->fsm)) { + // Inject datagrams (let the RT thread queue them, see + // ecrt_master_send()) + master->injection_seq_fsm++; + } + + ec_master_exec_slave_fsms(master); + + up(&master->master_sem); + } + +#ifdef EC_USE_HRTIMER + // the op thread should not work faster than the sending RT thread + ec_master_nanosleep(master->send_interval * 1000); +#else + if (ec_fsm_master_idle(&master->fsm)) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + } + else { + schedule(); + } +#endif + } + + EC_MASTER_DBG(master, 1, "Master OP thread exiting...\n"); + return 0; +} + +/****************************************************************************/ + +#ifdef EC_EOE + +/* compatibility for priority changes */ +static inline void set_normal_priority(struct task_struct *p, int nice) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) + sched_set_normal(p, nice); +#else + struct sched_param param = { .sched_priority = 0 }; + sched_setscheduler(p, SCHED_NORMAL, ¶m); + set_user_nice(p, nice); +#endif +} + +/****************************************************************************/ + +/** Starts Ethernet over EtherCAT processing on demand. + */ +void ec_master_eoe_start(ec_master_t *master /**< EtherCAT master */) +{ + if (master->eoe_thread) { + EC_MASTER_WARN(master, "EoE already running!\n"); + return; + } + + if (list_empty(&master->eoe_handlers)) + return; + + if (!master->send_cb || !master->receive_cb) { + EC_MASTER_WARN(master, "No EoE processing" + " because of missing callbacks!\n"); + return; + } + + EC_MASTER_INFO(master, "Starting EoE thread.\n"); + master->eoe_thread = kthread_run(ec_master_eoe_thread, master, + "EtherCAT-EoE"); + if (IS_ERR(master->eoe_thread)) { + int err = (int) PTR_ERR(master->eoe_thread); + EC_MASTER_ERR(master, "Failed to start EoE thread (error %i)!\n", + err); + master->eoe_thread = NULL; + return; + } + + set_normal_priority(master->eoe_thread, 0); +} + +/****************************************************************************/ + +/** Stops the Ethernet over EtherCAT processing. + */ +void ec_master_eoe_stop(ec_master_t *master /**< EtherCAT master */) +{ + if (master->eoe_thread) { + EC_MASTER_INFO(master, "Stopping EoE thread.\n"); + + kthread_stop(master->eoe_thread); + master->eoe_thread = NULL; + EC_MASTER_INFO(master, "EoE thread exited.\n"); + } +} + +/****************************************************************************/ + +/** Does the Ethernet over EtherCAT processing. + */ +static int ec_master_eoe_thread(void *priv_data) +{ + ec_master_t *master = (ec_master_t *) priv_data; + ec_eoe_t *eoe; + unsigned int none_open, sth_to_send, all_idle; + + EC_MASTER_DBG(master, 1, "EoE thread running.\n"); + + while (!kthread_should_stop()) { + none_open = 1; + all_idle = 1; + + list_for_each_entry(eoe, &master->eoe_handlers, list) { + if (ec_eoe_is_open(eoe)) { + none_open = 0; + break; + } + } + if (none_open) + goto schedule; + + // receive datagrams + master->receive_cb(master->cb_data); + + // actual EoE processing + sth_to_send = 0; + list_for_each_entry(eoe, &master->eoe_handlers, list) { + ec_eoe_run(eoe); + if (eoe->queue_datagram) { + sth_to_send = 1; + } + if (!ec_eoe_is_idle(eoe)) { + all_idle = 0; + } + } + + if (sth_to_send) { + list_for_each_entry(eoe, &master->eoe_handlers, list) { + ec_eoe_queue(eoe); + } + // (try to) send datagrams + master->send_cb(master->cb_data); + } + +schedule: + if (all_idle) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + } else { + schedule(); + } + } + + EC_MASTER_DBG(master, 1, "EoE thread exiting...\n"); + return 0; +} + +#endif + +/****************************************************************************/ + +/** Attaches the slave configurations to the slaves. + */ +void ec_master_attach_slave_configs( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + ec_slave_config_t *sc; + + list_for_each_entry(sc, &master->configs, list) { + ec_slave_config_attach(sc); + } +} + +/****************************************************************************/ + +/** Common implementation for ec_master_find_slave() + * and ec_master_find_slave_const(). + */ +#define EC_FIND_SLAVE \ + do { \ + if (alias) { \ + for (; slave < master->slaves + master->slave_count; \ + slave++) { \ + if (slave->effective_alias == alias) \ + break; \ + } \ + if (slave == master->slaves + master->slave_count) \ + return NULL; \ + } \ + \ + slave += position; \ + if (slave < master->slaves + master->slave_count) { \ + return slave; \ + } else { \ + return NULL; \ + } \ + } while (0) + +/** Finds a slave in the bus, given the alias and position. + * + * \return Search result, or NULL. + */ +ec_slave_t *ec_master_find_slave( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t alias, /**< Slave alias. */ + uint16_t position /**< Slave position. */ + ) +{ + ec_slave_t *slave = master->slaves; + EC_FIND_SLAVE; +} + +/** Finds a slave in the bus, given the alias and position. + * + * Const version. + * + * \return Search result, or NULL. + */ +const ec_slave_t *ec_master_find_slave_const( + const ec_master_t *master, /**< EtherCAT master. */ + uint16_t alias, /**< Slave alias. */ + uint16_t position /**< Slave position. */ + ) +{ + const ec_slave_t *slave = master->slaves; + EC_FIND_SLAVE; +} + +/****************************************************************************/ + +/** Get the number of slave configurations provided by the application. + * + * \return Number of configurations. + */ +unsigned int ec_master_config_count( + const ec_master_t *master /**< EtherCAT master. */ + ) +{ + const ec_slave_config_t *sc; + unsigned int count = 0; + + list_for_each_entry(sc, &master->configs, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Common implementation for ec_master_get_config() + * and ec_master_get_config_const(). + */ +#define EC_FIND_CONFIG \ + do { \ + list_for_each_entry(sc, &master->configs, list) { \ + if (pos--) \ + continue; \ + return sc; \ + } \ + return NULL; \ + } while (0) + +/** Get a slave configuration via its position in the list. + * + * \return Slave configuration or \a NULL. + */ +ec_slave_config_t *ec_master_get_config( + const ec_master_t *master, /**< EtherCAT master. */ + unsigned int pos /**< List position. */ + ) +{ + ec_slave_config_t *sc; + EC_FIND_CONFIG; +} + +/** Get a slave configuration via its position in the list. + * + * Const version. + * + * \return Slave configuration or \a NULL. + */ +const ec_slave_config_t *ec_master_get_config_const( + const ec_master_t *master, /**< EtherCAT master. */ + unsigned int pos /**< List position. */ + ) +{ + const ec_slave_config_t *sc; + EC_FIND_CONFIG; +} + +/****************************************************************************/ + +/** Get the number of domains. + * + * \return Number of domains. + */ +unsigned int ec_master_domain_count( + const ec_master_t *master /**< EtherCAT master. */ + ) +{ + const ec_domain_t *domain; + unsigned int count = 0; + + list_for_each_entry(domain, &master->domains, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Common implementation for ec_master_find_domain() and + * ec_master_find_domain_const(). + */ +#define EC_FIND_DOMAIN \ + do { \ + list_for_each_entry(domain, &master->domains, list) { \ + if (index--) \ + continue; \ + return domain; \ + } \ + \ + return NULL; \ + } while (0) + +/** Get a domain via its position in the list. + * + * \return Domain pointer, or \a NULL if not found. + */ +ec_domain_t *ec_master_find_domain( + ec_master_t *master, /**< EtherCAT master. */ + unsigned int index /**< Domain index. */ + ) +{ + ec_domain_t *domain; + EC_FIND_DOMAIN; +} + +/** Get a domain via its position in the list. + * + * Const version. + * + * \return Domain pointer, or \a NULL if not found. + */ +const ec_domain_t *ec_master_find_domain_const( + const ec_master_t *master, /**< EtherCAT master. */ + unsigned int index /**< Domain index. */ + ) +{ + const ec_domain_t *domain; + EC_FIND_DOMAIN; +} + +/****************************************************************************/ + +#ifdef EC_EOE + +/** Get the number of EoE handlers. + * + * \return Number of EoE handlers. + */ +uint16_t ec_master_eoe_handler_count( + const ec_master_t *master /**< EtherCAT master. */ + ) +{ + const ec_eoe_t *eoe; + unsigned int count = 0; + + list_for_each_entry(eoe, &master->eoe_handlers, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Get an EoE handler via its position in the list. + * + * Const version. + * + * \return EoE handler pointer, or \a NULL if not found. + */ +const ec_eoe_t *ec_master_get_eoe_handler_const( + const ec_master_t *master, /**< EtherCAT master. */ + uint16_t index /**< EoE handler index. */ + ) +{ + const ec_eoe_t *eoe; + + list_for_each_entry(eoe, &master->eoe_handlers, list) { + if (index--) + continue; + return eoe; + } + + return NULL; +} + +#endif + +/****************************************************************************/ + +/** Set the debug level. + * + * \retval 0 Success. + * \retval -EINVAL Invalid debug level. + */ +int ec_master_debug_level( + ec_master_t *master, /**< EtherCAT master. */ + unsigned int level /**< Debug level. May be 0, 1 or 2. */ + ) +{ + if (level > 2) { + EC_MASTER_ERR(master, "Invalid debug level %u!\n", level); + return -EINVAL; + } + + if (level != master->debug_level) { + master->debug_level = level; + EC_MASTER_INFO(master, "Master debug level set to %u.\n", + master->debug_level); + } + + return 0; +} + +/****************************************************************************/ + +/** Finds the DC reference clock. + */ +void ec_master_find_dc_ref_clock( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + ec_slave_t *slave, *ref = NULL; + + if (master->dc_ref_config) { + // Use application-selected reference clock + slave = master->dc_ref_config->slave; + + if (slave) { + if (slave->base_dc_supported && slave->has_dc_system_time) { + ref = slave; + } + else { + EC_MASTER_WARN(master, "Slave %u can not act as a" + " DC reference clock!", slave->ring_position); + } + } + else { + EC_MASTER_WARN(master, "DC reference clock config (%u-%u)" + " has no slave attached!\n", master->dc_ref_config->alias, + master->dc_ref_config->position); + } + } + else { + // Use first slave with DC support as reference clock + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + if (slave->base_dc_supported && slave->has_dc_system_time) { + ref = slave; + break; + } + } + + } + + master->dc_ref_clock = ref; + + if (ref) { + EC_MASTER_INFO(master, "Using slave %u as DC reference clock.\n", + ref->ring_position); + } + else { + EC_MASTER_INFO(master, "No DC reference clock found.\n"); + } + + // These calls always succeed, because the + // datagrams have been pre-allocated. + ec_datagram_fpwr(&master->ref_sync_datagram, + ref ? ref->station_address : 0xffff, 0x0910, 4); + ec_datagram_frmw(&master->sync_datagram, + ref ? ref->station_address : 0xffff, 0x0910, 4); +} + +/****************************************************************************/ + +/** Calculates the bus topology; recursion function. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_master_calc_topology_rec( + ec_master_t *master, /**< EtherCAT master. */ + ec_slave_t *port0_slave, /**< Slave at port 0. */ + unsigned int *slave_position /**< Slave position. */ + ) +{ + ec_slave_t *slave = master->slaves + *slave_position; + unsigned int port_index; + int ret; + + static const unsigned int next_table[EC_MAX_PORTS] = { + 3, 2, 0, 1 + }; + + slave->ports[0].next_slave = port0_slave; + + port_index = 3; + while (port_index != 0) { + if (!slave->ports[port_index].link.loop_closed) { + *slave_position = *slave_position + 1; + if (*slave_position < master->slave_count) { + slave->ports[port_index].next_slave = + master->slaves + *slave_position; + ret = ec_master_calc_topology_rec(master, + slave, slave_position); + if (ret) { + return ret; + } + } else { + return -1; + } + } + + port_index = next_table[port_index]; + } + + return 0; +} + +/****************************************************************************/ + +/** Calculates the bus topology. + */ +void ec_master_calc_topology( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + unsigned int slave_position = 0; + + if (master->slave_count == 0) + return; + + if (ec_master_calc_topology_rec(master, NULL, &slave_position)) + EC_MASTER_ERR(master, "Failed to calculate bus topology.\n"); +} + +/****************************************************************************/ + +/** Calculates the bus transmission delays. + */ +void ec_master_calc_transmission_delays( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + ec_slave_t *slave; + + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + ec_slave_calc_port_delays(slave); + } + + if (master->dc_ref_clock) { + uint32_t delay = 0; + ec_slave_calc_transmission_delays_rec(master->dc_ref_clock, &delay); + } +} + +/****************************************************************************/ + +/** Distributed-clocks calculations. + */ +void ec_master_calc_dc( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + // find DC reference clock + ec_master_find_dc_ref_clock(master); + + // calculate bus topology + ec_master_calc_topology(master); + + ec_master_calc_transmission_delays(master); +} + +/****************************************************************************/ + +/** Request OP state for configured slaves. + */ +void ec_master_request_op( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + unsigned int i; + ec_slave_t *slave; + + if (!master->active) + return; + + EC_MASTER_DBG(master, 1, "Requesting OP...\n"); + + // request OP for all configured slaves + for (i = 0; i < master->slave_count; i++) { + slave = master->slaves + i; + if (slave->config) { + ec_slave_request_state(slave, EC_SLAVE_STATE_OP); + } + } + + // always set DC reference clock to OP + if (master->dc_ref_clock) { + ec_slave_request_state(master->dc_ref_clock, EC_SLAVE_STATE_OP); + } +} + +/***************************************************************************** + * Application interface + ****************************************************************************/ + +/** Same as ecrt_master_create_domain(), but with ERR_PTR() return value. + * + * \return New domain, or ERR_PTR() return value. + */ +ec_domain_t *ecrt_master_create_domain_err( + ec_master_t *master /**< master */ + ) +{ + ec_domain_t *domain, *last_domain; + unsigned int index; + + EC_MASTER_DBG(master, 1, "ecrt_master_create_domain(master = 0x%p)\n", + master); + + if (!(domain = + (ec_domain_t *) kmalloc(sizeof(ec_domain_t), GFP_KERNEL))) { + EC_MASTER_ERR(master, "Error allocating domain memory!\n"); + return ERR_PTR(-ENOMEM); + } + + down(&master->master_sem); + + if (list_empty(&master->domains)) { + index = 0; + } else { + last_domain = list_entry(master->domains.prev, ec_domain_t, list); + index = last_domain->index + 1; + } + + ec_domain_init(domain, master, index); + list_add_tail(&domain->list, &master->domains); + + up(&master->master_sem); + + EC_MASTER_DBG(master, 1, "Created domain %u.\n", domain->index); + + return domain; +} + +/****************************************************************************/ + +ec_domain_t *ecrt_master_create_domain( + ec_master_t *master /**< master */ + ) +{ + ec_domain_t *d = ecrt_master_create_domain_err(master); + return IS_ERR(d) ? NULL : d; +} + +/****************************************************************************/ + +int ecrt_master_activate(ec_master_t *master) +{ + uint32_t domain_offset; + ec_domain_t *domain; + int ret; +#ifdef EC_EOE + int eoe_was_running; +#endif + + EC_MASTER_DBG(master, 1, "ecrt_master_activate(master = 0x%p)\n", master); + + if (master->active) { + EC_MASTER_WARN(master, "%s: Master already active!\n", __func__); + return 0; + } + + down(&master->master_sem); + + // finish all domains + domain_offset = 0; + list_for_each_entry(domain, &master->domains, list) { + ret = ec_domain_finish(domain, domain_offset); + if (ret < 0) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Failed to finish domain 0x%p!\n", domain); + return ret; + } + domain_offset += domain->data_size; + } + + up(&master->master_sem); + + // restart EoE process and master thread with new locking + + ec_master_thread_stop(master); +#ifdef EC_EOE + eoe_was_running = master->eoe_thread != NULL; + ec_master_eoe_stop(master); +#endif + + EC_MASTER_DBG(master, 1, "FSM datagram is %p.\n", &master->fsm_datagram); + + master->injection_seq_fsm = 0; + master->injection_seq_rt = 0; + + master->send_cb = master->app_send_cb; + master->receive_cb = master->app_receive_cb; + master->cb_data = master->app_cb_data; + +#ifdef EC_EOE + if (eoe_was_running) { + ec_master_eoe_start(master); + } +#endif + ret = ec_master_thread_start(master, ec_master_operation_thread, + "EtherCAT-OP"); + if (ret < 0) { + EC_MASTER_ERR(master, "Failed to start master thread!\n"); + return ret; + } + + /* Allow scanning after a topology change. */ + master->allow_scan = 1; + + master->active = 1; + + // notify state machine, that the configuration shall now be applied + master->config_changed = 1; + + return 0; +} + +/****************************************************************************/ + +int ecrt_master_deactivate(ec_master_t *master) +{ + ec_slave_t *slave; +#ifdef EC_EOE + ec_eoe_t *eoe; + int eoe_was_running; +#endif + + EC_MASTER_DBG(master, 1, "%s(master = 0x%p)\n", __func__, master); + + if (!master->active) { + EC_MASTER_WARN(master, "%s: Master not active.\n", __func__); + return -EINVAL; + } + + ec_master_thread_stop(master); +#ifdef EC_EOE + eoe_was_running = master->eoe_thread != NULL; + ec_master_eoe_stop(master); +#endif + + master->send_cb = ec_master_internal_send_cb; + master->receive_cb = ec_master_internal_receive_cb; + master->cb_data = master; + + ec_master_clear_config(master); + + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + + // set states for all slaves + ec_slave_request_state(slave, EC_SLAVE_STATE_PREOP); + + // mark for reconfiguration, because the master could have no + // possibility for a reconfiguration between two sequential operation + // phases. + slave->force_config = 1; + } + +#ifdef EC_EOE + // ... but leave EoE slaves in OP + list_for_each_entry(eoe, &master->eoe_handlers, list) { + if (ec_eoe_is_open(eoe)) + ec_slave_request_state(eoe->slave, EC_SLAVE_STATE_OP); + } +#endif + + master->app_time = 0ULL; + master->dc_ref_time = 0ULL; + +#ifdef EC_EOE + if (eoe_was_running) { + ec_master_eoe_start(master); + } +#endif + if (ec_master_thread_start(master, ec_master_idle_thread, + "EtherCAT-IDLE")) { + EC_MASTER_WARN(master, "Failed to restart master thread!\n"); + } + + /* Disallow scanning to get into the same state like after a master + * request (after ec_master_enter_operation_phase() is called). */ + master->allow_scan = 0; + + master->active = 0; + return 0; +} + +/****************************************************************************/ + +int ecrt_master_send(ec_master_t *master) +{ + ec_datagram_t *datagram, *n; + ec_device_index_t dev_idx; + + if (master->injection_seq_rt != master->injection_seq_fsm) { + // inject datagram produced by master FSM + ec_master_queue_datagram(master, &master->fsm_datagram); + master->injection_seq_rt = master->injection_seq_fsm; + } + + ec_master_inject_external_datagrams(master); + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + if (unlikely(!master->devices[dev_idx].link_state)) { + // link is down, no datagram can be sent + list_for_each_entry_safe(datagram, n, + &master->datagram_queue, queue) { + if (datagram->device_index == dev_idx) { + datagram->state = EC_DATAGRAM_ERROR; + list_del_init(&datagram->queue); + } + } + + if (!master->devices[dev_idx].dev) { + continue; + } + + // query link state + ec_device_poll(&master->devices[dev_idx]); + + // clear frame statistics + ec_device_clear_stats(&master->devices[dev_idx]); + continue; + } + + // send frames + ec_master_send_datagrams(master, dev_idx); + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_receive(ec_master_t *master) +{ + unsigned int dev_idx; + ec_datagram_t *datagram, *next; + + // receive datagrams + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + ec_device_poll(&master->devices[dev_idx]); + } + ec_master_update_device_stats(master); + + // dequeue all datagrams that timed out + list_for_each_entry_safe(datagram, next, &master->datagram_queue, queue) { + if (datagram->state != EC_DATAGRAM_SENT) continue; + +#ifdef EC_HAVE_CYCLES + if (master->devices[EC_DEVICE_MAIN].cycles_poll - + datagram->cycles_sent > timeout_cycles) { +#else + if (master->devices[EC_DEVICE_MAIN].jiffies_poll - + datagram->jiffies_sent > timeout_jiffies) { +#endif + list_del_init(&datagram->queue); + datagram->state = EC_DATAGRAM_TIMED_OUT; + master->stats.timeouts++; + +#ifdef EC_RT_SYSLOG + ec_master_output_stats(master); + + if (unlikely(master->debug_level > 0)) { + unsigned int time_us; +#ifdef EC_HAVE_CYCLES + time_us = (unsigned int) + (master->devices[EC_DEVICE_MAIN].cycles_poll - + datagram->cycles_sent) * 1000 / cpu_khz; +#else + time_us = (unsigned int) + ((master->devices[EC_DEVICE_MAIN].jiffies_poll - + datagram->jiffies_sent) * 1000000 / HZ); +#endif + EC_MASTER_DBG(master, 0, "TIMED OUT datagram %p," + " index %02X waited %u us.\n", + datagram, datagram->index, time_us); + } +#endif /* RT_SYSLOG */ + } + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_send_ext(ec_master_t *master) +{ + ec_datagram_t *datagram, *next; + + if (down_trylock(&master->ext_queue_sem)) + return -EAGAIN; + + list_for_each_entry_safe(datagram, next, &master->ext_datagram_queue, + ext_queue) { + list_del_init(&datagram->ext_queue); + ec_master_queue_datagram(master, datagram); + } + up(&master->ext_queue_sem); + + return ecrt_master_send(master); +} + +/****************************************************************************/ + +/** Same as ecrt_master_slave_config(), but with ERR_PTR() return value. + */ +ec_slave_config_t *ecrt_master_slave_config_err(ec_master_t *master, + uint16_t alias, uint16_t position, uint32_t vendor_id, + uint32_t product_code) +{ + ec_slave_config_t *sc; + unsigned int found = 0; + + + EC_MASTER_DBG(master, 1, "ecrt_master_slave_config(master = 0x%p," + " alias = %u, position = %u, vendor_id = 0x%08x," + " product_code = 0x%08x)\n", + master, alias, position, vendor_id, product_code); + + list_for_each_entry(sc, &master->configs, list) { + if (sc->alias == alias && sc->position == position) { + found = 1; + break; + } + } + + if (found) { // config with same alias/position already existing + if (sc->vendor_id != vendor_id || sc->product_code != product_code) { + EC_MASTER_ERR(master, "Slave type mismatch. Slave was" + " configured as 0x%08X/0x%08X before. Now configuring" + " with 0x%08X/0x%08X.\n", sc->vendor_id, sc->product_code, + vendor_id, product_code); + return ERR_PTR(-ENOENT); + } + } else { + EC_MASTER_DBG(master, 1, "Creating slave configuration for %u:%u," + " 0x%08X/0x%08X.\n", + alias, position, vendor_id, product_code); + + if (!(sc = (ec_slave_config_t *) kmalloc(sizeof(ec_slave_config_t), + GFP_KERNEL))) { + EC_MASTER_ERR(master, "Failed to allocate memory" + " for slave configuration.\n"); + return ERR_PTR(-ENOMEM); + } + + ec_slave_config_init(sc, master, + alias, position, vendor_id, product_code); + + down(&master->master_sem); + + // try to find the addressed slave + ec_slave_config_attach(sc); + ec_slave_config_load_default_sync_config(sc); + list_add_tail(&sc->list, &master->configs); + + up(&master->master_sem); + } + + return sc; +} + +/****************************************************************************/ + +ec_slave_config_t *ecrt_master_slave_config(ec_master_t *master, + uint16_t alias, uint16_t position, uint32_t vendor_id, + uint32_t product_code) +{ + ec_slave_config_t *sc = ecrt_master_slave_config_err(master, alias, + position, vendor_id, product_code); + return IS_ERR(sc) ? NULL : sc; +} + +/****************************************************************************/ + +int ecrt_master_select_reference_clock(ec_master_t *master, + ec_slave_config_t *sc) +{ + if (sc) { + ec_slave_t *slave = sc->slave; + + // output an early warning + if (slave && + (!slave->base_dc_supported || !slave->has_dc_system_time)) { + EC_MASTER_WARN(master, "Slave %u can not act as" + " a reference clock!", slave->ring_position); + } + } + + master->dc_ref_config = sc; + return 0; +} + +/****************************************************************************/ + +int ecrt_master(ec_master_t *master, ec_master_info_t *master_info) +{ + EC_MASTER_DBG(master, 1, "ecrt_master(master = 0x%p," + " master_info = 0x%p)\n", master, master_info); + + master_info->slave_count = master->slave_count; + master_info->link_up = master->devices[EC_DEVICE_MAIN].link_state; + master_info->scan_busy = master->scan_busy; + master_info->app_time = master->app_time; + return 0; +} + +/****************************************************************************/ + +int ecrt_master_scan_progress(ec_master_t *master, + ec_master_scan_progress_t *progress) +{ + EC_MASTER_DBG(master, 1, "ecrt_master_scan_progress(master = 0x%p," + " progress = 0x%p)\n", master, progress); + + progress->slave_count = master->slave_count; + progress->scan_index = master->scan_index; + return 0; +} + +/****************************************************************************/ + +int ecrt_master_get_slave(ec_master_t *master, uint16_t slave_position, + ec_slave_info_t *slave_info) +{ + const ec_slave_t *slave; + unsigned int i; + int ret = 0; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + slave = ec_master_find_slave_const(master, 0, slave_position); + + if (slave == NULL) { + ret = -ENOENT; + goto out_get_slave; + } + + slave_info->position = slave->ring_position; + slave_info->vendor_id = slave->sii.vendor_id; + slave_info->product_code = slave->sii.product_code; + slave_info->revision_number = slave->sii.revision_number; + slave_info->serial_number = slave->sii.serial_number; + slave_info->alias = slave->effective_alias; + slave_info->current_on_ebus = slave->sii.current_on_ebus; + + for (i = 0; i < EC_MAX_PORTS; i++) { + slave_info->ports[i].desc = slave->ports[i].desc; + slave_info->ports[i].link.link_up = slave->ports[i].link.link_up; + slave_info->ports[i].link.loop_closed = + slave->ports[i].link.loop_closed; + slave_info->ports[i].link.signal_detected = + slave->ports[i].link.signal_detected; + slave_info->ports[i].receive_time = slave->ports[i].receive_time; + if (slave->ports[i].next_slave) { + slave_info->ports[i].next_slave = + slave->ports[i].next_slave->ring_position; + } else { + slave_info->ports[i].next_slave = 0xffff; + } + slave_info->ports[i].delay_to_next_dc = + slave->ports[i].delay_to_next_dc; + } + + slave_info->al_state = slave->current_state; + slave_info->error_flag = slave->error_flag; + slave_info->sync_count = slave->sii.sync_count; + slave_info->sdo_count = ec_slave_sdo_count(slave); + if (slave->sii.name) { + strscpy(slave_info->name, slave->sii.name, EC_MAX_STRING_LENGTH); + } else { + slave_info->name[0] = 0; + } + +out_get_slave: + up(&master->master_sem); + + return ret; +} + +/****************************************************************************/ + +void ecrt_master_callbacks(ec_master_t *master, + void (*send_cb)(void *), void (*receive_cb)(void *), void *cb_data) +{ + EC_MASTER_DBG(master, 1, "ecrt_master_callbacks(master = 0x%p," + " send_cb = 0x%p, receive_cb = 0x%p, cb_data = 0x%p)\n", + master, send_cb, receive_cb, cb_data); + + master->app_send_cb = send_cb; + master->app_receive_cb = receive_cb; + master->app_cb_data = cb_data; +} + +/****************************************************************************/ + +int ecrt_master_state(const ec_master_t *master, ec_master_state_t *state) +{ + ec_device_index_t dev_idx; + + state->slaves_responding = 0U; + state->al_states = 0; + state->link_up = 0U; + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + /* Announce sum of responding slaves on all links. */ + state->slaves_responding += master->fsm.slaves_responding[dev_idx]; + + /* Binary-or slave states of all links. */ + state->al_states |= master->fsm.slave_states[dev_idx]; + + /* Signal link up if at least one device has link. */ + state->link_up |= master->devices[dev_idx].link_state; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_link_state(const ec_master_t *master, unsigned int dev_idx, + ec_master_link_state_t *state) +{ + if (dev_idx >= ec_master_num_devices(master)) { + return -EINVAL; + } + + state->slaves_responding = master->fsm.slaves_responding[dev_idx]; + state->al_states = master->fsm.slave_states[dev_idx]; + state->link_up = master->devices[dev_idx].link_state; + + return 0; +} + +/****************************************************************************/ + +int ecrt_master_application_time(ec_master_t *master, uint64_t app_time) +{ + master->app_time = app_time; + + if (unlikely(!master->dc_ref_time)) { + master->dc_ref_time = app_time; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_reference_clock_time(const ec_master_t *master, + uint32_t *time) +{ + if (!master->dc_ref_clock) { + return -ENXIO; + } + + if (master->sync_datagram.state != EC_DATAGRAM_RECEIVED) { + return -EIO; + } + + // Get returned datagram time, transmission delay removed. + *time = EC_READ_U32(master->sync_datagram.data) - + master->dc_ref_clock->transmission_delay; + + return 0; +} + +/****************************************************************************/ + +int ecrt_master_sync_reference_clock(ec_master_t *master) +{ + if (master->dc_ref_clock) { + EC_WRITE_U32(master->ref_sync_datagram.data, master->app_time); + ec_master_queue_datagram(master, &master->ref_sync_datagram); + } else { + return -ENXIO; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_sync_reference_clock_to( + ec_master_t *master, + uint64_t sync_time + ) +{ + if (master->dc_ref_clock) { + EC_WRITE_U32(master->ref_sync_datagram.data, sync_time); + ec_master_queue_datagram(master, &master->ref_sync_datagram); + } else { + return -ENXIO; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_sync_slave_clocks(ec_master_t *master) +{ + if (master->dc_ref_clock) { + ec_datagram_zero(&master->sync_datagram); + ec_master_queue_datagram(master, &master->sync_datagram); + } else { + return -ENXIO; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_sync_monitor_queue(ec_master_t *master) +{ + ec_datagram_zero(&master->sync_mon_datagram); + ec_master_queue_datagram(master, &master->sync_mon_datagram); + return 0; +} + +/****************************************************************************/ + +uint32_t ecrt_master_sync_monitor_process(const ec_master_t *master) +{ + if (master->sync_mon_datagram.state == EC_DATAGRAM_RECEIVED) { + return EC_READ_U32(master->sync_mon_datagram.data) & 0x7fffffff; + } else { + return 0xffffffff; + } +} + +/****************************************************************************/ + +int ecrt_master_sdo_download(ec_master_t *master, uint16_t slave_position, + uint16_t index, uint8_t subindex, const uint8_t *data, + size_t data_size, uint32_t *abort_code) +{ + ec_sdo_request_t request; + ec_slave_t *slave; + int ret; + + EC_MASTER_DBG(master, 1, "%s(master = 0x%p," + " slave_position = %u, index = 0x%04X, subindex = 0x%02X," + " data = 0x%p, data_size = %zu, abort_code = 0x%p)\n", + __func__, master, slave_position, index, subindex, + data, data_size, abort_code); + + ec_sdo_request_init(&request); + ecrt_sdo_request_index(&request, index, subindex); + ret = ec_sdo_request_alloc(&request, data_size); + if (ret) { + ec_sdo_request_clear(&request); + return ret; + } + + memcpy(request.data, data, data_size); + request.data_size = data_size; + ecrt_sdo_request_write(&request); + + if (down_interruptible(&master->master_sem)) { + ec_sdo_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", slave_position); + ec_sdo_request_clear(&request); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling SDO download request.\n"); + + // schedule request. + list_add_tail(&request.list, &slave->sdo_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + list_del(&request.list); + up(&master->master_sem); + ec_sdo_request_clear(&request); + return -EINTR; + } + // request already processing: interrupt not possible. + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + *abort_code = request.abort_code; + + if (request.state == EC_INT_REQUEST_SUCCESS) { + ret = 0; + } else if (request.errno) { + ret = -request.errno; + } else { + ret = -EIO; + } + + ec_sdo_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +int ecrt_master_sdo_download_complete(ec_master_t *master, + uint16_t slave_position, uint16_t index, const uint8_t *data, + size_t data_size, uint32_t *abort_code) +{ + ec_sdo_request_t request; + ec_slave_t *slave; + int ret; + + EC_MASTER_DBG(master, 1, "%s(master = 0x%p," + " slave_position = %u, index = 0x%04X," + " data = 0x%p, data_size = %zu, abort_code = 0x%p)\n", + __func__, master, slave_position, index, data, data_size, + abort_code); + + ec_sdo_request_init(&request); + ecrt_sdo_request_index(&request, index, 0); + ret = ec_sdo_request_alloc(&request, data_size); + if (ret) { + ec_sdo_request_clear(&request); + return ret; + } + + request.complete_access = 1; + memcpy(request.data, data, data_size); + request.data_size = data_size; + ecrt_sdo_request_write(&request); + + if (down_interruptible(&master->master_sem)) { + ec_sdo_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", slave_position); + ec_sdo_request_clear(&request); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling SDO download request" + " (complete access).\n"); + + // schedule request. + list_add_tail(&request.list, &slave->sdo_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + list_del(&request.list); + up(&master->master_sem); + ec_sdo_request_clear(&request); + return -EINTR; + } + // request already processing: interrupt not possible. + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + *abort_code = request.abort_code; + + if (request.state == EC_INT_REQUEST_SUCCESS) { + ret = 0; + } else if (request.errno) { + ret = -request.errno; + } else { + ret = -EIO; + } + + ec_sdo_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +int ecrt_master_sdo_upload(ec_master_t *master, uint16_t slave_position, + uint16_t index, uint8_t subindex, uint8_t *target, + size_t target_size, size_t *result_size, uint32_t *abort_code) +{ + ec_sdo_request_t request; + ec_slave_t *slave; + int ret = 0; + + EC_MASTER_DBG(master, 1, "%s(master = 0x%p," + " slave_position = %u, index = 0x%04X, subindex = 0x%02X," + " target = 0x%p, target_size = %zu, result_size = 0x%p," + " abort_code = 0x%p)\n", + __func__, master, slave_position, index, subindex, + target, target_size, result_size, abort_code); + + ec_sdo_request_init(&request); + ecrt_sdo_request_index(&request, index, subindex); + ecrt_sdo_request_read(&request); + + if (down_interruptible(&master->master_sem)) { + ec_sdo_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, slave_position))) { + up(&master->master_sem); + ec_sdo_request_clear(&request); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", slave_position); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling SDO upload request.\n"); + + // schedule request. + list_add_tail(&request.list, &slave->sdo_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + list_del(&request.list); + up(&master->master_sem); + ec_sdo_request_clear(&request); + return -EINTR; + } + // request already processing: interrupt not possible. + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + *abort_code = request.abort_code; + + if (request.state != EC_INT_REQUEST_SUCCESS) { + *result_size = 0; + if (request.errno) { + ret = -request.errno; + } else { + ret = -EIO; + } + } else { + if (request.data_size > target_size) { + EC_SLAVE_ERR(slave, "%s(): Buffer too small.\n", __func__); + ret = -ENOBUFS; + } + else { + memcpy(target, request.data, request.data_size); + *result_size = request.data_size; + ret = 0; + } + } + + ec_sdo_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +int ecrt_master_write_idn(ec_master_t *master, uint16_t slave_position, + uint8_t drive_no, uint16_t idn, const uint8_t *data, size_t data_size, + uint16_t *error_code) +{ + ec_soe_request_t request; + ec_slave_t *slave; + int ret; + + if (drive_no > 7) { + EC_MASTER_ERR(master, "Invalid drive number!\n"); + return -EINVAL; + } + + ec_soe_request_init(&request); + ec_soe_request_set_drive_no(&request, drive_no); + ec_soe_request_set_idn(&request, idn); + + ret = ec_soe_request_alloc(&request, data_size); + if (ret) { + ec_soe_request_clear(&request); + return ret; + } + + memcpy(request.data, data, data_size); + request.data_size = data_size; + ec_soe_request_write(&request); + + if (down_interruptible(&master->master_sem)) { + ec_soe_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + slave_position); + ec_soe_request_clear(&request); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling SoE write request.\n"); + + // schedule SoE write request. + list_add_tail(&request.list, &slave->soe_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&request.list); + up(&master->master_sem); + ec_soe_request_clear(&request); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + if (error_code) { + *error_code = request.error_code; + } + ret = request.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; + ec_soe_request_clear(&request); + + return ret; +} + +/****************************************************************************/ + +int ecrt_master_read_idn(ec_master_t *master, uint16_t slave_position, + uint8_t drive_no, uint16_t idn, uint8_t *target, size_t target_size, + size_t *result_size, uint16_t *error_code) +{ + ec_soe_request_t request; + ec_slave_t *slave; + int ret; + + if (drive_no > 7) { + EC_MASTER_ERR(master, "Invalid drive number!\n"); + return -EINVAL; + } + + ec_soe_request_init(&request); + ec_soe_request_set_drive_no(&request, drive_no); + ec_soe_request_set_idn(&request, idn); + ec_soe_request_read(&request); + + if (down_interruptible(&master->master_sem)) { + ec_soe_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, slave_position))) { + up(&master->master_sem); + ec_soe_request_clear(&request); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", slave_position); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling SoE read request.\n"); + + // schedule request. + list_add_tail(&request.list, &slave->soe_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + list_del(&request.list); + up(&master->master_sem); + ec_soe_request_clear(&request); + return -EINTR; + } + // request already processing: interrupt not possible. + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + if (error_code) { + *error_code = request.error_code; + } + + if (request.state != EC_INT_REQUEST_SUCCESS) { + if (result_size) { + *result_size = 0; + } + ret = -EIO; + } else { // success + if (request.data_size > target_size) { + EC_SLAVE_ERR(slave, "%s(): Buffer too small.\n", __func__); + ret = -ENOBUFS; + } + else { // data fits in buffer + if (result_size) { + *result_size = request.data_size; + } + memcpy(target, request.data, request.data_size); + ret = 0; + } + } + + ec_soe_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +int ecrt_master_reset(ec_master_t *master) +{ + ec_slave_config_t *sc; + + list_for_each_entry(sc, &master->configs, list) { + if (sc->slave) { + ec_slave_request_state(sc->slave, EC_SLAVE_STATE_OP); + } + } + return 0; +} + +/****************************************************************************/ + +static void sc_reset_task_kicker(struct irq_work *work) +{ + struct ec_master *master = + container_of(work, struct ec_master, sc_reset_work_kicker); + schedule_work(&master->sc_reset_work); +} + +/****************************************************************************/ + +static void sc_reset_task(struct work_struct *work) +{ + struct ec_master *master = + container_of(work, struct ec_master, sc_reset_work); + + down(&master->master_sem); + ecrt_master_reset(master); + up(&master->master_sem); +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_master_create_domain); +EXPORT_SYMBOL(ecrt_master_activate); +EXPORT_SYMBOL(ecrt_master_deactivate); +EXPORT_SYMBOL(ecrt_master_send); +EXPORT_SYMBOL(ecrt_master_send_ext); +EXPORT_SYMBOL(ecrt_master_receive); +EXPORT_SYMBOL(ecrt_master_callbacks); +EXPORT_SYMBOL(ecrt_master); +EXPORT_SYMBOL(ecrt_master_scan_progress); +EXPORT_SYMBOL(ecrt_master_get_slave); +EXPORT_SYMBOL(ecrt_master_slave_config); +EXPORT_SYMBOL(ecrt_master_select_reference_clock); +EXPORT_SYMBOL(ecrt_master_state); +EXPORT_SYMBOL(ecrt_master_link_state); +EXPORT_SYMBOL(ecrt_master_application_time); +EXPORT_SYMBOL(ecrt_master_sync_reference_clock); +EXPORT_SYMBOL(ecrt_master_sync_reference_clock_to); +EXPORT_SYMBOL(ecrt_master_sync_slave_clocks); +EXPORT_SYMBOL(ecrt_master_reference_clock_time); +EXPORT_SYMBOL(ecrt_master_sync_monitor_queue); +EXPORT_SYMBOL(ecrt_master_sync_monitor_process); +EXPORT_SYMBOL(ecrt_master_sdo_download); +EXPORT_SYMBOL(ecrt_master_sdo_download_complete); +EXPORT_SYMBOL(ecrt_master_sdo_upload); +EXPORT_SYMBOL(ecrt_master_write_idn); +EXPORT_SYMBOL(ecrt_master_read_idn); +EXPORT_SYMBOL(ecrt_master_reset); + +/** \endcond */ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/master.h b/ubuntu/igh-ecat/master/master.h new file mode 100644 index 00000000000000..a1125e85a360e6 --- /dev/null +++ b/ubuntu/igh-ecat/master/master.h @@ -0,0 +1,386 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT master structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_MASTER_H__ +#define __EC_MASTER_H__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "device.h" +#include "domain.h" +#include "ethernet.h" +#include "fsm_master.h" +#include "cdev.h" + +#ifdef EC_RTDM +#include "rtdm.h" +#endif + +/****************************************************************************/ + +/** Convenience macro for printing master-specific information to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT : ", + * where INDEX is the master index. + * + * \param master EtherCAT master + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_MASTER_INFO(master, fmt, args...) \ + printk(KERN_INFO "EtherCAT %u: " fmt, master->index, ##args) + +/** Convenience macro for printing master-specific errors to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT : ", + * where INDEX is the master index. + * + * \param master EtherCAT master + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_MASTER_ERR(master, fmt, args...) \ + printk(KERN_ERR "EtherCAT ERROR %u: " fmt, master->index, ##args) + +/** Convenience macro for printing master-specific warnings to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT : ", + * where INDEX is the master index. + * + * \param master EtherCAT master + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_MASTER_WARN(master, fmt, args...) \ + printk(KERN_WARNING "EtherCAT WARNING %u: " fmt, master->index, ##args) + +/** Convenience macro for printing master-specific debug messages to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT : ", + * where INDEX is the master index. + * + * \param master EtherCAT master + * \param level Debug level. Master's debug level must be >= \a level for + * output. + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_MASTER_DBG(master, level, fmt, args...) \ + do { \ + if (master->debug_level >= level) { \ + printk(KERN_DEBUG "EtherCAT DEBUG %u: " fmt, \ + master->index, ##args); \ + } \ + } while (0) + + +/** Size of the external datagram ring. + * + * The external datagram ring is used for slave FSMs. + */ +#define EC_EXT_RING_SIZE 32 + +/** Maximum number of masters. + */ +#define EC_MAX_MASTERS 32 + +/****************************************************************************/ + +/** EtherCAT master phase. + */ +typedef enum { + EC_ORPHANED, /**< Orphaned phase. The master has no Ethernet device + attached. */ + EC_IDLE, /**< Idle phase. An Ethernet device is attached, but the master + is not in use, yet. */ + EC_OPERATION /**< Operation phase. The master was requested by a realtime + application. */ +} ec_master_phase_t; + +/****************************************************************************/ + +/** Cyclic statistics. + */ +typedef struct { + unsigned int timeouts; /**< datagram timeouts */ + unsigned int corrupted; /**< corrupted frames */ + unsigned int unmatched; /**< unmatched datagrams (received, but not + queued any longer) */ + unsigned long output_jiffies; /**< time of last output */ +} ec_stats_t; + +/****************************************************************************/ + +/** Device statistics. + */ +typedef struct { + u64 tx_count; /**< Number of frames sent. */ + u64 last_tx_count; /**< Number of frames sent of last statistics cycle. */ + u64 rx_count; /**< Number of frames received. */ + u64 last_rx_count; /**< Number of frames received of last statistics + cycle. */ + u64 tx_bytes; /**< Number of bytes sent. */ + u64 last_tx_bytes; /**< Number of bytes sent of last statistics cycle. */ + u64 rx_bytes; /**< Number of bytes received. */ + u64 last_rx_bytes; /**< Number of bytes received of last statistics cycle. + */ + u64 last_loss; /**< Tx/Rx difference of last statistics cycle. */ + s32 tx_frame_rates[EC_RATE_COUNT]; /**< Transmit rates in frames/s for + different statistics cycle periods. + */ + s32 rx_frame_rates[EC_RATE_COUNT]; /**< Receive rates in frames/s for + different statistics cycle periods. + */ + s32 tx_byte_rates[EC_RATE_COUNT]; /**< Transmit rates in byte/s for + different statistics cycle periods. */ + s32 rx_byte_rates[EC_RATE_COUNT]; /**< Receive rates in byte/s for + different statistics cycle periods. */ + s32 loss_rates[EC_RATE_COUNT]; /**< Frame loss rates for different + statistics cycle periods. */ + unsigned long jiffies; /**< Jiffies of last statistic cycle. */ +} ec_device_stats_t; + +/****************************************************************************/ + +#if EC_MAX_NUM_DEVICES < 1 +#error Invalid number of devices +#endif + +/****************************************************************************/ + +/** EtherCAT master. + * + * Manages slaves, domains and IO. + */ +struct ec_master { + unsigned int index; /**< Index. */ + unsigned int reserved; /**< \a True, if the master is in use. */ + + ec_cdev_t cdev; /**< Master character device. */ + struct device *class_device; /**< Master class device. */ + +#ifdef EC_RTDM + ec_rtdm_dev_t rtdm_dev; /**< RTDM device. */ +#endif + + struct semaphore master_sem; /**< Master semaphore. */ + + ec_device_t devices[EC_MAX_NUM_DEVICES]; /**< EtherCAT devices. */ + const uint8_t *macs[EC_MAX_NUM_DEVICES]; /**< Device MAC addresses. */ +#if EC_MAX_NUM_DEVICES > 1 + unsigned int num_devices; /**< Number of devices. Access this always via + ec_master_num_devices(), because it may be + optimized! */ +#endif + struct semaphore device_sem; /**< Device semaphore. */ + ec_device_stats_t device_stats; /**< Device statistics. */ + + ec_fsm_master_t fsm; /**< Master state machine. */ + ec_datagram_t fsm_datagram; /**< Datagram used for state machines. */ + ec_master_phase_t phase; /**< Master phase. */ + unsigned int active; /**< Master has been activated. */ + unsigned int config_changed; /**< The configuration changed. */ + unsigned int injection_seq_fsm; /**< Datagram injection sequence number + for the FSM side. */ + unsigned int injection_seq_rt; /**< Datagram injection sequence number + for the realtime side. */ + + ec_slave_t *slaves; /**< Array of slaves on the bus. */ + unsigned int slave_count; /**< Number of slaves on the bus. */ + + /* Configuration applied by the application. */ + struct list_head configs; /**< List of slave configurations. */ + struct list_head domains; /**< List of domains. */ + + u64 app_time; /**< Time of the last ecrt_master_sync() call. */ + u64 dc_ref_time; /**< Common reference timestamp for DC start times. */ + ec_datagram_t ref_sync_datagram; /**< Datagram used for synchronizing the + reference clock to the master clock. */ + ec_datagram_t sync_datagram; /**< Datagram used for DC drift + compensation. */ + ec_datagram_t sync_mon_datagram; /**< Datagram used for DC synchronisation + monitoring. */ + ec_slave_config_t *dc_ref_config; /**< Application-selected DC reference + clock slave config. */ + ec_slave_t *dc_ref_clock; /**< DC reference clock slave. */ + + unsigned int scan_busy; /**< Current scan state. */ + unsigned int scan_index; /**< Index of slave currently scanned. */ + unsigned int allow_scan; /**< \a True, if slave scanning is allowed. */ + struct semaphore scan_sem; /**< Semaphore protecting the \a scan_busy + variable and the \a allow_scan flag. */ + wait_queue_head_t scan_queue; /**< Queue for processes that wait for + slave scanning. */ + + unsigned int config_busy; /**< State of slave configuration. */ + struct semaphore config_sem; /**< Semaphore protecting the \a config_busy + variable and the allow_config flag. */ + wait_queue_head_t config_queue; /**< Queue for processes that wait for + slave configuration. */ + + struct list_head datagram_queue; /**< Datagram queue. */ + uint8_t datagram_index; /**< Current datagram index. */ + + struct list_head ext_datagram_queue; /**< Queue for non-application + datagrams. */ + struct semaphore ext_queue_sem; /**< Semaphore protecting the \a + ext_datagram_queue. */ + + ec_datagram_t ext_datagram_ring[EC_EXT_RING_SIZE]; /**< External datagram + ring. */ + unsigned int ext_ring_idx_rt; /**< Index in external datagram ring for RT + side. */ + unsigned int ext_ring_idx_fsm; /**< Index in external datagram ring for + FSM side. */ + unsigned int send_interval; /**< Interval between two calls to + ecrt_master_send(). */ + size_t max_queue_size; /**< Maximum size of datagram queue */ + + ec_slave_t *fsm_slave; /**< Slave that is queried next for FSM exec. */ + struct list_head fsm_exec_list; /**< Slave FSM execution list. */ + unsigned int fsm_exec_count; /**< Number of entries in execution list. */ + + unsigned int debug_level; /**< Master debug level. */ + unsigned int run_on_cpu; /**< bind kernel threads to this cpu */ + ec_stats_t stats; /**< Cyclic statistics. */ + + struct task_struct *thread; /**< Master thread. */ + +#ifdef EC_EOE + struct task_struct *eoe_thread; /**< EoE thread. */ + struct list_head eoe_handlers; /**< Ethernet over EtherCAT handlers. */ +#endif + + struct rt_mutex io_mutex; /**< Mutex used in \a IDLE and \a OP phase. */ + + void (*send_cb)(void *); /**< Current send datagrams callback. */ + void (*receive_cb)(void *); /**< Current receive datagrams callback. */ + void *cb_data; /**< Current callback data. */ + void (*app_send_cb)(void *); /**< Application's send datagrams + callback. */ + void (*app_receive_cb)(void *); /**< Application's receive datagrams + callback. */ + void *app_cb_data; /**< Application callback data. */ + + struct list_head sii_requests; /**< SII write requests. */ + struct list_head emerg_reg_requests; /**< Emergency register access + requests. */ + + wait_queue_head_t request_queue; /**< Wait queue for external requests + from user space. */ + struct work_struct sc_reset_work; /**< Task to reset slave configuration. */ + struct irq_work sc_reset_work_kicker; /**< NMI-Safe kicker to trigger + reset task above. */ +}; + +/****************************************************************************/ + +// static funtions +void ec_master_init_static(void); + +// master creation/deletion +int ec_master_init(ec_master_t *, unsigned int, const uint8_t *, + const uint8_t *, dev_t, struct class *, unsigned int, unsigned int); +void ec_master_clear(ec_master_t *); + +/** Number of Ethernet devices. + */ +#if EC_MAX_NUM_DEVICES > 1 +#define ec_master_num_devices(MASTER) ((MASTER)->num_devices) +#else +#define ec_master_num_devices(MASTER) 1 +#endif + +// phase transitions +int ec_master_enter_idle_phase(ec_master_t *); +void ec_master_leave_idle_phase(ec_master_t *); +int ec_master_enter_operation_phase(ec_master_t *); +void ec_master_leave_operation_phase(ec_master_t *); + +#ifdef EC_EOE +// EoE +void ec_master_eoe_start(ec_master_t *); +void ec_master_eoe_stop(ec_master_t *); +#endif + +// datagram IO +void ec_master_receive_datagrams(ec_master_t *, ec_device_t *, + const uint8_t *, size_t); +void ec_master_queue_datagram(ec_master_t *, ec_datagram_t *); +void ec_master_queue_datagram_ext(ec_master_t *, ec_datagram_t *); + +// misc. +void ec_master_set_send_interval(ec_master_t *, unsigned int); +void ec_master_attach_slave_configs(ec_master_t *); +ec_slave_t *ec_master_find_slave(ec_master_t *, uint16_t, uint16_t); +const ec_slave_t *ec_master_find_slave_const(const ec_master_t *, uint16_t, + uint16_t); +void ec_master_output_stats(ec_master_t *); +#ifdef EC_EOE +void ec_master_clear_eoe_handlers(ec_master_t *); +#endif +void ec_master_clear_slaves(ec_master_t *); + +unsigned int ec_master_config_count(const ec_master_t *); +ec_slave_config_t *ec_master_get_config( + const ec_master_t *, unsigned int); +const ec_slave_config_t *ec_master_get_config_const( + const ec_master_t *, unsigned int); +unsigned int ec_master_domain_count(const ec_master_t *); +ec_domain_t *ec_master_find_domain(ec_master_t *, unsigned int); +const ec_domain_t *ec_master_find_domain_const(const ec_master_t *, + unsigned int); +#ifdef EC_EOE +uint16_t ec_master_eoe_handler_count(const ec_master_t *); +const ec_eoe_t *ec_master_get_eoe_handler_const(const ec_master_t *, uint16_t); +#endif + +int ec_master_debug_level(ec_master_t *, unsigned int); + +ec_domain_t *ecrt_master_create_domain_err(ec_master_t *); +ec_slave_config_t *ecrt_master_slave_config_err(ec_master_t *, uint16_t, + uint16_t, uint32_t, uint32_t); + +void ec_master_calc_dc(ec_master_t *); +void ec_master_request_op(ec_master_t *); + +void ec_master_internal_send_cb(void *); +void ec_master_internal_receive_cb(void *); + +extern const unsigned int rate_intervals[EC_RATE_COUNT]; // see master.c + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/module.c b/ubuntu/igh-ecat/master/module.c new file mode 100644 index 00000000000000..b8156a1d3d5261 --- /dev/null +++ b/ubuntu/igh-ecat/master/module.c @@ -0,0 +1,681 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT master driver module. + */ + +/****************************************************************************/ + +#include +#include +#include + +#include "globals.h" +#include "master.h" +#include "device.h" + +/****************************************************************************/ + +/****************************************************************************/ + +int __init ec_init_module(void); +void __exit ec_cleanup_module(void); + +static int ec_mac_parse(uint8_t *, const char *, int); + +// prototypes for private functions +int ec_mac_equal(const uint8_t *, const uint8_t *); +int ec_mac_is_broadcast(const uint8_t *); + +/****************************************************************************/ + +static char *main_devices[EC_MAX_MASTERS]; /**< Main devices parameter. */ +static unsigned int master_count; /**< Number of masters. */ +static char *backup_devices[EC_MAX_MASTERS]; /**< Backup devices parameter. */ +static unsigned int backup_count; /**< Number of backup devices. */ +static unsigned int debug_level; /**< Debug level parameter. */ +static unsigned int run_on_cpu = 0xffffffff; /**< Bind created kernel threads + to a cpu. Default do not bind. + */ + +static ec_master_t *masters; /**< Array of masters. */ +static struct semaphore master_sem; /**< Master semaphore. */ + +dev_t device_number; /**< Device number for master cdevs. */ +struct class *class; /**< Device class. */ + +static uint8_t macs[EC_MAX_MASTERS][2][ETH_ALEN]; /**< MAC addresses. */ + +char *ec_master_version_str = EC_MASTER_VERSION; /**< Version string. */ + +/****************************************************************************/ + +/** \cond */ + +MODULE_AUTHOR("Florian Pose "); +MODULE_DESCRIPTION("EtherCAT master driver module"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(EC_MASTER_VERSION); + +module_param_array(main_devices, charp, &master_count, S_IRUGO); +MODULE_PARM_DESC(main_devices, "MAC addresses of main devices"); +module_param_array(backup_devices, charp, &backup_count, S_IRUGO); +MODULE_PARM_DESC(backup_devices, "MAC addresses of backup devices"); +module_param_named(debug_level, debug_level, uint, S_IRUGO); +MODULE_PARM_DESC(debug_level, "Debug level"); +module_param_named(run_on_cpu, run_on_cpu, uint, S_IRUGO); +MODULE_PARM_DESC(run_on_cpu, "Bind kthreads to a specific cpu"); + +/** \endcond */ + +/****************************************************************************/ + +/** Module initialization. + * + * Initializes \a master_count masters. + * \return 0 on success, else < 0 + */ +int __init ec_init_module(void) +{ + int i, ret = 0; + + EC_INFO("Master driver %s\n", EC_MASTER_VERSION); + + sema_init(&master_sem, 1); + + if (master_count) { + if (alloc_chrdev_region(&device_number, + 0, master_count, "EtherCAT")) { + EC_ERR("Failed to obtain device number(s)!\n"); + ret = -EBUSY; + goto out_return; + } + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0) + class = class_create(THIS_MODULE, "EtherCAT"); +#else + class = class_create("EtherCAT"); +#endif + if (IS_ERR(class)) { + EC_ERR("Failed to create device class.\n"); + ret = PTR_ERR(class); + goto out_cdev; + } + + // zero MAC addresses + memset(macs, 0x00, sizeof(uint8_t) * EC_MAX_MASTERS * 2 * ETH_ALEN); + + // process MAC parameters + for (i = 0; i < master_count; i++) { + ret = ec_mac_parse(macs[i][0], main_devices[i], 0); + if (ret) + goto out_class; + + if (i < backup_count) { + ret = ec_mac_parse(macs[i][1], backup_devices[i], 1); + if (ret) + goto out_class; + } + } + + // initialize static master variables + ec_master_init_static(); + + if (master_count) { + if (!(masters = kmalloc(sizeof(ec_master_t) * master_count, + GFP_KERNEL))) { + EC_ERR("Failed to allocate memory" + " for EtherCAT masters.\n"); + ret = -ENOMEM; + goto out_class; + } + } + + for (i = 0; i < master_count; i++) { + ret = ec_master_init(&masters[i], i, macs[i][0], macs[i][1], + device_number, class, debug_level, run_on_cpu); + if (ret) + goto out_free_masters; + } + + EC_INFO("%u master%s waiting for devices.\n", + master_count, (master_count == 1 ? "" : "s")); + return ret; + +out_free_masters: + for (i--; i >= 0; i--) + ec_master_clear(&masters[i]); + kfree(masters); +out_class: + class_destroy(class); +out_cdev: + if (master_count) + unregister_chrdev_region(device_number, master_count); +out_return: + return ret; +} + +/****************************************************************************/ + +/** Module cleanup. + * + * Clears all master instances. + */ +void __exit ec_cleanup_module(void) +{ + unsigned int i; + + for (i = 0; i < master_count; i++) { + ec_master_clear(&masters[i]); + } + + if (master_count) + kfree(masters); + + class_destroy(class); + + if (master_count) + unregister_chrdev_region(device_number, master_count); + + EC_INFO("Master module cleaned up.\n"); +} + +/****************************************************************************/ + +/** Get the number of masters. + */ +unsigned int ec_master_count(void) +{ + return master_count; +} + +/***************************************************************************** + * MAC address functions + ****************************************************************************/ + +/** + * \return true, if two MAC addresses are equal. + */ +int ec_mac_equal( + const uint8_t *mac1, /**< First MAC address. */ + const uint8_t *mac2 /**< Second MAC address. */ + ) +{ + unsigned int i; + + for (i = 0; i < ETH_ALEN; i++) + if (mac1[i] != mac2[i]) + return 0; + + return 1; +} + +/****************************************************************************/ + +/** Maximum MAC string size. + */ +#define EC_MAX_MAC_STRING_SIZE (3 * ETH_ALEN) + +/** Print a MAC address to a buffer. + * + * The buffer size must be at least EC_MAX_MAC_STRING_SIZE. + * + * \return number of bytes written. + */ +ssize_t ec_mac_print( + const uint8_t *mac, /**< MAC address */ + char *buffer /**< Target buffer. */ + ) +{ + off_t off = 0; + unsigned int i; + + for (i = 0; i < ETH_ALEN; i++) { + off += sprintf(buffer + off, "%02X", mac[i]); + if (i < ETH_ALEN - 1) off += sprintf(buffer + off, ":"); + } + + return off; +} + +/****************************************************************************/ + +/** + * \return true, if the MAC address is all-zero. + */ +int ec_mac_is_zero( + const uint8_t *mac /**< MAC address. */ + ) +{ + unsigned int i; + + for (i = 0; i < ETH_ALEN; i++) + if (mac[i]) + return 0; + + return 1; +} + +/****************************************************************************/ + +/** + * \return true, if the given MAC address is the broadcast address. + */ +int ec_mac_is_broadcast( + const uint8_t *mac /**< MAC address. */ + ) +{ + unsigned int i; + + for (i = 0; i < ETH_ALEN; i++) + if (mac[i] != 0xff) + return 0; + + return 1; +} + +/****************************************************************************/ + +/** Parse a MAC address from a string. + * + * The MAC address must match the regular expression + * "([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2}". + * + * \return 0 on success, else < 0 + */ +static int ec_mac_parse(uint8_t *mac, const char *src, int allow_empty) +{ + unsigned int i, value; + const char *orig = src; + char *rem; + + if (!strlen(src)) { + if (allow_empty){ + return 0; + } else { + EC_ERR("MAC address may not be empty.\n"); + return -EINVAL; + } + } + + for (i = 0; i < ETH_ALEN; i++) { + value = simple_strtoul(src, &rem, 16); + if (rem != src + 2 + || value > 0xFF + || (i < ETH_ALEN - 1 && *rem != ':')) { + EC_ERR("Invalid MAC address \"%s\".\n", orig); + return -EINVAL; + } + mac[i] = value; + if (i < ETH_ALEN - 1) { + src = rem + 1; // skip colon + } + } + + return 0; +} + +/****************************************************************************/ + +/** Outputs frame contents for debugging purposes. + * If the data block is larger than 256 bytes, only the first 128 + * and the last 128 bytes will be shown + */ +void ec_print_data(const uint8_t *data, /**< pointer to data */ + size_t size /**< number of bytes to output */ + ) +{ + unsigned int i; + + EC_DBG(""); + for (i = 0; i < size; i++) { + printk(KERN_CONT "%02X ", data[i]); + + if ((i + 1) % 16 == 0 && i < size - 1) { + printk(KERN_CONT "\n"); + EC_DBG(""); + } + + if (i + 1 == 128 && size > 256) { + printk(KERN_CONT "dropped %zu bytes\n", size - 128 - i); + i = size - 128; + EC_DBG(""); + } + } + printk(KERN_CONT "\n"); +} + +/****************************************************************************/ + +/** Outputs frame contents and differences for debugging purposes. + */ +void ec_print_data_diff(const uint8_t *d1, /**< first data */ + const uint8_t *d2, /**< second data */ + size_t size /** number of bytes to output */ + ) +{ + unsigned int i; + + EC_DBG(""); + for (i = 0; i < size; i++) { + if (d1[i] == d2[i]) { + printk(KERN_CONT ".. "); + } + else { + printk(KERN_CONT "%02X ", d2[i]); + } + if ((i + 1) % 16 == 0) { + printk(KERN_CONT "\n"); + EC_DBG(""); + } + } + printk(KERN_CONT "\n"); +} + +/****************************************************************************/ + +/** Prints slave states in clear text. + * + * \return Size of the created string. + */ +size_t ec_state_string(uint8_t states, /**< slave states */ + char *buffer, /**< target buffer + (min. EC_STATE_STRING_SIZE bytes) */ + uint8_t multi /**< Show multi-state mask. */ + ) +{ + off_t off = 0; + unsigned int first = 1; + + if (!states) { + off += sprintf(buffer + off, "(unknown)"); + return off; + } + + if (multi) { // multiple slaves + if (states & EC_SLAVE_STATE_INIT) { + off += sprintf(buffer + off, "INIT"); + first = 0; + } + if (states & EC_SLAVE_STATE_PREOP) { + if (!first) off += sprintf(buffer + off, ", "); + off += sprintf(buffer + off, "PREOP"); + first = 0; + } + if (states & EC_SLAVE_STATE_SAFEOP) { + if (!first) off += sprintf(buffer + off, ", "); + off += sprintf(buffer + off, "SAFEOP"); + first = 0; + } + if (states & EC_SLAVE_STATE_OP) { + if (!first) off += sprintf(buffer + off, ", "); + off += sprintf(buffer + off, "OP"); + } + } else { // single slave + if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_INIT) { + off += sprintf(buffer + off, "INIT"); + } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_PREOP) { + off += sprintf(buffer + off, "PREOP"); + } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_BOOT) { + off += sprintf(buffer + off, "BOOT"); + } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_SAFEOP) { + off += sprintf(buffer + off, "SAFEOP"); + } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_OP) { + off += sprintf(buffer + off, "OP"); + } else { + off += sprintf(buffer + off, "(invalid)"); + } + first = 0; + } + + if (states & EC_SLAVE_STATE_ACK_ERR) { + if (!first) off += sprintf(buffer + off, " + "); + off += sprintf(buffer + off, "ERROR"); + } + + return off; +} + +/***************************************************************************** + * Device interface + ****************************************************************************/ + +/** Device names. + */ +const char *ec_device_names[2] = { + "main", + "backup" +}; + +/** Offers an EtherCAT device to a certain master. + * + * The master decides, if it wants to use the device for EtherCAT operation, + * or not. It is important, that the offered net_device is not used by the + * kernel IP stack. If the master, accepted the offer, the address of the + * newly created EtherCAT device is returned, else \a NULL is returned. + * + * \return Pointer to device, if accepted, or NULL if declined. + * \ingroup DeviceInterface + */ +ec_device_t *ecdev_offer( + struct net_device *net_dev, /**< net_device to offer */ + ec_pollfunc_t poll, /**< device poll function */ + struct module *module /**< pointer to the module */ + ) +{ + ec_master_t *master; + char str[EC_MAX_MAC_STRING_SIZE]; + unsigned int i, dev_idx; + + for (i = 0; i < master_count; i++) { + master = &masters[i]; + ec_mac_print(net_dev->dev_addr, str); + + if (down_interruptible(&master->device_sem)) { + EC_MASTER_WARN(master, "%s() interrupted!\n", __func__); + return NULL; + } + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(master); dev_idx++) { + if (!master->devices[dev_idx].dev + && (ec_mac_equal(master->macs[dev_idx], net_dev->dev_addr) + || ec_mac_is_broadcast(master->macs[dev_idx]))) { + + EC_INFO("Accepting %s as %s device for master %u.\n", + str, ec_device_names[dev_idx != 0], master->index); + + ec_device_attach(&master->devices[dev_idx], + net_dev, poll, module); + up(&master->device_sem); + + snprintf(net_dev->name, IFNAMSIZ, "ec%c%u", + ec_device_names[dev_idx != 0][0], master->index); + + return &master->devices[dev_idx]; // offer accepted + } + } + + up(&master->device_sem); + + EC_MASTER_DBG(master, 1, "Master declined device %s.\n", str); + } + + return NULL; // offer declined +} + +/***************************************************************************** + * Application interface + ****************************************************************************/ + +/** Request a master. + * + * Same as ecrt_request_master(), but with ERR_PTR() return value. + * + * \return Requested master. + */ +ec_master_t *ecrt_request_master_err( + unsigned int master_index /**< Master index. */ + ) +{ + ec_master_t *master, *errptr = NULL; + unsigned int dev_idx = EC_DEVICE_MAIN; + + EC_INFO("Requesting master %u...\n", master_index); + + if (master_index >= master_count) { + EC_ERR("Invalid master index %u.\n", master_index); + errptr = ERR_PTR(-EINVAL); + goto out_return; + } + master = &masters[master_index]; + + if (down_interruptible(&master_sem)) { + errptr = ERR_PTR(-EINTR); + goto out_return; + } + + if (master->reserved) { + up(&master_sem); + EC_MASTER_ERR(master, "Master already in use!\n"); + errptr = ERR_PTR(-EBUSY); + goto out_return; + } + master->reserved = 1; + up(&master_sem); + + if (down_interruptible(&master->device_sem)) { + errptr = ERR_PTR(-EINTR); + goto out_release; + } + + if (master->phase != EC_IDLE) { + up(&master->device_sem); + EC_MASTER_ERR(master, "Master still waiting for devices!\n"); + errptr = ERR_PTR(-ENODEV); + goto out_release; + } + + for (; dev_idx < ec_master_num_devices(master); dev_idx++) { + ec_device_t *device = &master->devices[dev_idx]; + if (!try_module_get(device->module)) { + up(&master->device_sem); + EC_MASTER_ERR(master, "Device module is unloading!\n"); + errptr = ERR_PTR(-ENODEV); + goto out_module_put; + } + } + + up(&master->device_sem); + + if (ec_master_enter_operation_phase(master)) { + EC_MASTER_ERR(master, "Failed to enter OPERATION phase!\n"); + errptr = ERR_PTR(-EIO); + goto out_module_put; + } + + EC_INFO("Successfully requested master %u.\n", master_index); + return master; + + out_module_put: + for (; dev_idx > 0; dev_idx--) { + ec_device_t *device = &master->devices[dev_idx - 1]; + module_put(device->module); + } + out_release: + master->reserved = 0; + out_return: + return errptr; +} + +/****************************************************************************/ + +ec_master_t *ecrt_request_master(unsigned int master_index) +{ + ec_master_t *master = ecrt_request_master_err(master_index); + return IS_ERR(master) ? NULL : master; +} + +/****************************************************************************/ + +void ecrt_release_master(ec_master_t *master) +{ + unsigned int dev_idx; + + EC_MASTER_INFO(master, "Releasing master...\n"); + + if (!master->reserved) { + EC_MASTER_WARN(master, "%s(): Master was was not requested!\n", + __func__); + return; + } + + ec_master_leave_operation_phase(master); + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + module_put(master->devices[dev_idx].module); + } + + master->reserved = 0; + + EC_MASTER_INFO(master, "Released.\n"); +} + +/****************************************************************************/ + +unsigned int ecrt_version_magic(void) +{ + return ECRT_VERSION_MAGIC; +} + +/****************************************************************************/ + +/** Global request state type translation table. + * + * Translates an internal request state to an external one. + */ +const ec_request_state_t ec_request_state_translation_table[] = { + EC_REQUEST_UNUSED, // EC_INT_REQUEST_INIT, + EC_REQUEST_BUSY, // EC_INT_REQUEST_QUEUED, + EC_REQUEST_BUSY, // EC_INT_REQUEST_BUSY, + EC_REQUEST_SUCCESS, // EC_INT_REQUEST_SUCCESS, + EC_REQUEST_ERROR // EC_INT_REQUEST_FAILURE +}; + +/****************************************************************************/ + +/** \cond */ + +module_init(ec_init_module); +module_exit(ec_cleanup_module); + +EXPORT_SYMBOL(ecdev_offer); + +EXPORT_SYMBOL(ecrt_request_master); +EXPORT_SYMBOL(ecrt_release_master); +EXPORT_SYMBOL(ecrt_version_magic); + +/** \endcond */ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/pdo.c b/ubuntu/igh-ecat/master/pdo.c new file mode 100644 index 00000000000000..9c145939574567 --- /dev/null +++ b/ubuntu/igh-ecat/master/pdo.c @@ -0,0 +1,309 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT process data object methods. +*/ + +/****************************************************************************/ + +#include +#include + +#include "pdo.h" + +/****************************************************************************/ + +/** PDO constructor. + */ +void ec_pdo_init( + ec_pdo_t *pdo /**< EtherCAT PDO */ + ) +{ + pdo->sync_index = -1; // not assigned + pdo->name = NULL; + INIT_LIST_HEAD(&pdo->entries); +} + +/****************************************************************************/ + +/** PDO copy constructor. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_pdo_init_copy( + ec_pdo_t *pdo, /**< PDO to create. */ + const ec_pdo_t *other_pdo /**< PDO to copy from. */ + ) +{ + int ret = 0; + + pdo->index = other_pdo->index; + pdo->sync_index = other_pdo->sync_index; + pdo->name = NULL; + INIT_LIST_HEAD(&pdo->entries); + + ret = ec_pdo_set_name(pdo, other_pdo->name); + if (ret < 0) + goto out_return; + + ret = ec_pdo_copy_entries(pdo, other_pdo); + if (ret < 0) + goto out_clear; + + return 0; + +out_clear: + ec_pdo_clear(pdo); +out_return: + return ret; +} + +/****************************************************************************/ + +/** PDO destructor. + */ +void ec_pdo_clear(ec_pdo_t *pdo /**< EtherCAT PDO. */) +{ + if (pdo->name) + kfree(pdo->name); + + ec_pdo_clear_entries(pdo); +} + +/****************************************************************************/ + +/** Clear PDO entry list. + */ +void ec_pdo_clear_entries(ec_pdo_t *pdo /**< EtherCAT PDO. */) +{ + ec_pdo_entry_t *entry, *next; + + // free all PDO entries + list_for_each_entry_safe(entry, next, &pdo->entries, list) { + list_del(&entry->list); + ec_pdo_entry_clear(entry); + kfree(entry); + } +} + +/****************************************************************************/ + +/** Set PDO name. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_pdo_set_name( + ec_pdo_t *pdo, /**< PDO. */ + const char *name /**< New name. */ + ) +{ + unsigned int len; + + if (pdo->name && name && !strcmp(pdo->name, name)) + return 0; + + if (pdo->name) + kfree(pdo->name); + + if (name && (len = strlen(name))) { + if (!(pdo->name = (char *) kmalloc(len + 1, GFP_KERNEL))) { + EC_ERR("Failed to allocate PDO name.\n"); + return -ENOMEM; + } + memcpy(pdo->name, name, len + 1); + } else { + pdo->name = NULL; + } + + return 0; +} + +/****************************************************************************/ + +/** Add a new PDO entry to the configuration. + * + * \retval Pointer to the added entry, otherwise a ERR_PTR() code. + */ +ec_pdo_entry_t *ec_pdo_add_entry( + ec_pdo_t *pdo, /**< PDO. */ + uint16_t index, /**< New entry's index. */ + uint8_t subindex, /**< New entry's subindex. */ + uint8_t bit_length /**< New entry's bit length. */ + ) +{ + ec_pdo_entry_t *entry; + + if (!(entry = kmalloc(sizeof(ec_pdo_entry_t), GFP_KERNEL))) { + EC_ERR("Failed to allocate memory for PDO entry.\n"); + return ERR_PTR(-ENOMEM); + } + + ec_pdo_entry_init(entry); + entry->index = index; + entry->subindex = subindex; + entry->bit_length = bit_length; + list_add_tail(&entry->list, &pdo->entries); + return entry; +} + +/****************************************************************************/ + +/** Copy PDO entries from another PDO. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_pdo_copy_entries( + ec_pdo_t *pdo, /**< PDO whos entries shall be replaced. */ + const ec_pdo_t *other /**< Pdo with entries to copy. */ + ) +{ + ec_pdo_entry_t *entry, *other_entry; + int ret; + + ec_pdo_clear_entries(pdo); + + list_for_each_entry(other_entry, &other->entries, list) { + if (!(entry = (ec_pdo_entry_t *) + kmalloc(sizeof(ec_pdo_entry_t), GFP_KERNEL))) { + EC_ERR("Failed to allocate memory for PDO entry copy.\n"); + return -ENOMEM; + } + + ret = ec_pdo_entry_init_copy(entry, other_entry); + if (ret < 0) { + kfree(entry); + return ret; + } + + list_add_tail(&entry->list, &pdo->entries); + } + + return 0; +} + +/****************************************************************************/ + +/** Compares the entries of two PDOs. + * + * \retval 1 The entries of the given PDOs are equal. + * \retval 0 The entries of the given PDOs differ. + */ +int ec_pdo_equal_entries( + const ec_pdo_t *pdo1, /**< First PDO. */ + const ec_pdo_t *pdo2 /**< Second PDO. */ + ) +{ + const struct list_head *head1, *head2, *item1, *item2; + const ec_pdo_entry_t *entry1, *entry2; + + head1 = item1 = &pdo1->entries; + head2 = item2 = &pdo2->entries; + + while (1) { + item1 = item1->next; + item2 = item2->next; + + if ((item1 == head1) ^ (item2 == head2)) // unequal lengths + return 0; + if (item1 == head1) // both finished + break; + + entry1 = list_entry(item1, ec_pdo_entry_t, list); + entry2 = list_entry(item2, ec_pdo_entry_t, list); + if (!ec_pdo_entry_equal(entry1, entry2)) + return 0; + } + + return 1; +} + +/****************************************************************************/ + +/** Get the number of PDO entries. + * + * \return Number of PDO entries. + */ +unsigned int ec_pdo_entry_count( + const ec_pdo_t *pdo /**< PDO. */ + ) +{ + const ec_pdo_entry_t *entry; + unsigned int num = 0; + + list_for_each_entry(entry, &pdo->entries, list) { + num++; + } + + return num; +} + +/****************************************************************************/ + +/** Finds a PDO entry via its position in the list. + * + * Const version. + * + * \return Search result, or NULL. + */ +const ec_pdo_entry_t *ec_pdo_find_entry_by_pos_const( + const ec_pdo_t *pdo, /**< PDO. */ + unsigned int pos /**< Position in the list. */ + ) +{ + const ec_pdo_entry_t *entry; + + list_for_each_entry(entry, &pdo->entries, list) { + if (pos--) + continue; + return entry; + } + + return NULL; +} + +/****************************************************************************/ + +/** Outputs the PDOs in the list. + */ +void ec_pdo_print_entries( + const ec_pdo_t *pdo /**< PDO. */ + ) +{ + const ec_pdo_entry_t *entry; + + if (list_empty(&pdo->entries)) { + printk(KERN_CONT "(none)"); + } else { + list_for_each_entry(entry, &pdo->entries, list) { + printk(KERN_CONT "0x%04X:%02X/%u", + entry->index, entry->subindex, entry->bit_length); + if (entry->list.next != &pdo->entries) + printk(KERN_CONT " "); + } + } +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/pdo.h b/ubuntu/igh-ecat/master/pdo.h new file mode 100644 index 00000000000000..1819c836578f23 --- /dev/null +++ b/ubuntu/igh-ecat/master/pdo.h @@ -0,0 +1,67 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT Process data object structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_PDO_H__ +#define __EC_PDO_H__ + +#include + +#include "globals.h" +#include "pdo_entry.h" + +/****************************************************************************/ + +/** PDO description. + */ +typedef struct { + struct list_head list; /**< List item. */ + uint16_t index; /**< PDO index. */ + int8_t sync_index; /**< Assigned sync manager. \todo remove? */ + char *name; /**< PDO name. */ + struct list_head entries; /**< List of PDO entries. */ +} ec_pdo_t; + +/****************************************************************************/ + +void ec_pdo_init(ec_pdo_t *); +int ec_pdo_init_copy(ec_pdo_t *, const ec_pdo_t *); +void ec_pdo_clear(ec_pdo_t *); +void ec_pdo_clear_entries(ec_pdo_t *); +int ec_pdo_set_name(ec_pdo_t *, const char *); +ec_pdo_entry_t *ec_pdo_add_entry(ec_pdo_t *, uint16_t, uint8_t, uint8_t); +int ec_pdo_copy_entries(ec_pdo_t *, const ec_pdo_t *); +int ec_pdo_equal_entries(const ec_pdo_t *, const ec_pdo_t *); +unsigned int ec_pdo_entry_count(const ec_pdo_t *); +const ec_pdo_entry_t *ec_pdo_find_entry_by_pos_const( + const ec_pdo_t *, unsigned int); + +void ec_pdo_print_entries(const ec_pdo_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/pdo_entry.c b/ubuntu/igh-ecat/master/pdo_entry.c new file mode 100644 index 00000000000000..836cb3df45979a --- /dev/null +++ b/ubuntu/igh-ecat/master/pdo_entry.c @@ -0,0 +1,124 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT process data object entry methods. +*/ + +/****************************************************************************/ + +#include + +#include "pdo_entry.h" + +/****************************************************************************/ + +/** PDO entry constructor. + */ +void ec_pdo_entry_init( + ec_pdo_entry_t *entry /**< PDO entry. */ + ) +{ + entry->name = NULL; +} + +/****************************************************************************/ + +/** PDO entry copy constructor. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_pdo_entry_init_copy( + ec_pdo_entry_t *entry, /**< PDO entry. */ + const ec_pdo_entry_t *other /**< PDO entry to copy from. */ + ) +{ + entry->index = other->index; + entry->subindex = other->subindex; + entry->name = NULL; + entry->bit_length = other->bit_length; + + return ec_pdo_entry_set_name(entry, other->name); +} + +/****************************************************************************/ + +/** PDO entry destructor. + */ +void ec_pdo_entry_clear(ec_pdo_entry_t *entry /**< PDO entry. */) +{ + if (entry->name) + kfree(entry->name); +} + +/****************************************************************************/ + +/** Set PDO entry name. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_pdo_entry_set_name( + ec_pdo_entry_t *entry, /**< PDO entry. */ + const char *name /**< New name. */ + ) +{ + unsigned int len; + + if (entry->name && name && !strcmp(entry->name, name)) + return 0; + + if (entry->name) + kfree(entry->name); + + if (name && (len = strlen(name))) { + if (!(entry->name = (char *) kmalloc(len + 1, GFP_KERNEL))) { + EC_ERR("Failed to allocate PDO entry name.\n"); + return -ENOMEM; + } + memcpy(entry->name, name, len + 1); + } else { + entry->name = NULL; + } + + return 0; +} + +/****************************************************************************/ + +/** Compares two PDO entries. + * + * \retval 1 The entries are equal. + * \retval 0 The entries differ. + */ +int ec_pdo_entry_equal( + const ec_pdo_entry_t *entry1, /**< First PDO entry. */ + const ec_pdo_entry_t *entry2 /**< Second PDO entry. */ + ) +{ + return entry1->index == entry2->index + && entry1->subindex == entry2->subindex + && entry1->bit_length == entry2->bit_length; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/pdo_entry.h b/ubuntu/igh-ecat/master/pdo_entry.h new file mode 100644 index 00000000000000..96dc41ebfd57be --- /dev/null +++ b/ubuntu/igh-ecat/master/pdo_entry.h @@ -0,0 +1,58 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT Process data object structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_PDO_ENTRY_H__ +#define __EC_PDO_ENTRY_H__ + +#include + +#include "globals.h" + +/****************************************************************************/ + +/** PDO entry description. + */ +typedef struct { + struct list_head list; /**< list item */ + uint16_t index; /**< PDO entry index */ + uint8_t subindex; /**< PDO entry subindex */ + char *name; /**< entry name */ + uint8_t bit_length; /**< entry length in bit */ +} ec_pdo_entry_t; + +/****************************************************************************/ + +void ec_pdo_entry_init(ec_pdo_entry_t *); +int ec_pdo_entry_init_copy(ec_pdo_entry_t *, const ec_pdo_entry_t *); +void ec_pdo_entry_clear(ec_pdo_entry_t *); +int ec_pdo_entry_set_name(ec_pdo_entry_t *, const char *); +int ec_pdo_entry_equal(const ec_pdo_entry_t *, const ec_pdo_entry_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/pdo_list.c b/ubuntu/igh-ecat/master/pdo_list.c new file mode 100644 index 00000000000000..f26b1c880c28e1 --- /dev/null +++ b/ubuntu/igh-ecat/master/pdo_list.c @@ -0,0 +1,338 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT PDO list methods. +*/ + +/****************************************************************************/ + +#include + +#include "globals.h" +#include "pdo.h" +#include "slave_config.h" +#include "master.h" + +#include "pdo_list.h" + +/****************************************************************************/ + +/** PDO list constructor. + */ +void ec_pdo_list_init( + ec_pdo_list_t *pl /**< PDO list. */ + ) +{ + INIT_LIST_HEAD(&pl->list); +} + +/****************************************************************************/ + +/** PDO list destructor. + */ +void ec_pdo_list_clear(ec_pdo_list_t *pl /**< PDO list. */) +{ + ec_pdo_list_clear_pdos(pl); +} + +/****************************************************************************/ + +/** Clears the list of mapped PDOs. + */ +void ec_pdo_list_clear_pdos(ec_pdo_list_t *pl /**< PDO list. */) +{ + ec_pdo_t *pdo, *next; + + list_for_each_entry_safe(pdo, next, &pl->list, list) { + list_del_init(&pdo->list); + ec_pdo_clear(pdo); + kfree(pdo); + } +} + +/****************************************************************************/ + +/** Calculates the total size of the mapped PDO entries. + * + * \retval Data size in byte. + */ +uint16_t ec_pdo_list_total_size( + const ec_pdo_list_t *pl /**< PDO list. */ + ) +{ + unsigned int bit_size; + const ec_pdo_t *pdo; + const ec_pdo_entry_t *pdo_entry; + uint16_t byte_size; + + bit_size = 0; + list_for_each_entry(pdo, &pl->list, list) { + list_for_each_entry(pdo_entry, &pdo->entries, list) { + bit_size += pdo_entry->bit_length; + } + } + + if (bit_size % 8) // round up to full bytes + byte_size = bit_size / 8 + 1; + else + byte_size = bit_size / 8; + + return byte_size; +} + +/****************************************************************************/ + +/** Add a new PDO to the list. + * + * \return Pointer to new PDO, otherwise an ERR_PTR() code. + */ +ec_pdo_t *ec_pdo_list_add_pdo( + ec_pdo_list_t *pl, /**< PDO list. */ + uint16_t index /**< PDO index. */ + ) +{ + ec_pdo_t *pdo; + + if (!(pdo = (ec_pdo_t *) kmalloc(sizeof(ec_pdo_t), GFP_KERNEL))) { + EC_ERR("Failed to allocate memory for PDO.\n"); + return ERR_PTR(-ENOMEM); + } + + ec_pdo_init(pdo); + pdo->index = index; + list_add_tail(&pdo->list, &pl->list); + return pdo; +} + +/****************************************************************************/ + +/** Add the copy of an existing PDO to the list. + * + * \return 0 on success, else < 0 + */ +int ec_pdo_list_add_pdo_copy( + ec_pdo_list_t *pl, /**< PDO list. */ + const ec_pdo_t *pdo /**< PDO to add. */ + ) +{ + ec_pdo_t *mapped_pdo; + int ret; + + // PDO already mapped? + list_for_each_entry(mapped_pdo, &pl->list, list) { + if (mapped_pdo->index != pdo->index) continue; + EC_ERR("PDO 0x%04X is already mapped!\n", pdo->index); + return -EEXIST; + } + + if (!(mapped_pdo = kmalloc(sizeof(ec_pdo_t), GFP_KERNEL))) { + EC_ERR("Failed to allocate PDO memory.\n"); + return -ENOMEM; + } + + ret = ec_pdo_init_copy(mapped_pdo, pdo); + if (ret < 0) { + kfree(mapped_pdo); + return ret; + } + + list_add_tail(&mapped_pdo->list, &pl->list); + return 0; +} + +/****************************************************************************/ + +/** Makes a deep copy of another PDO list. + * + * \return 0 on success, else < 0 + */ +int ec_pdo_list_copy( + ec_pdo_list_t *pl, /**< PDO list. */ + const ec_pdo_list_t *other /**< PDO list to copy from. */ + ) +{ + ec_pdo_t *other_pdo; + int ret; + + ec_pdo_list_clear_pdos(pl); + + // PDO already mapped? + list_for_each_entry(other_pdo, &other->list, list) { + ret = ec_pdo_list_add_pdo_copy(pl, other_pdo); + if (ret) + return ret; + } + + return 0; +} + +/****************************************************************************/ + +/** Compares two PDO lists. + * + * Only the list is compared, not the PDO entries (i. e. the PDO + * mapping). + * + * \retval 1 The given PDO lists are equal. + * \retval 0 The given PDO lists differ. + */ +int ec_pdo_list_equal( + const ec_pdo_list_t *pl1, /**< First list. */ + const ec_pdo_list_t *pl2 /**< Second list. */ + ) +{ + const struct list_head *h1, *h2, *l1, *l2; + const ec_pdo_t *p1, *p2; + + h1 = l1 = &pl1->list; + h2 = l2 = &pl2->list; + + while (1) { + l1 = l1->next; + l2 = l2->next; + + if ((l1 == h1) ^ (l2 == h2)) // unequal lengths + return 0; + if (l1 == h1) // both finished + break; + + p1 = list_entry(l1, ec_pdo_t, list); + p2 = list_entry(l2, ec_pdo_t, list); + + if (p1->index != p2->index) + return 0; + } + + return 1; +} + +/****************************************************************************/ + +/** Finds a PDO with the given index. + * + * \return Search result, or NULL. + */ +ec_pdo_t *ec_pdo_list_find_pdo( + const ec_pdo_list_t *pl, /**< PDO list. */ + uint16_t index /**< PDO index. */ + ) +{ + ec_pdo_t *pdo; + + list_for_each_entry(pdo, &pl->list, list) { + if (pdo->index != index) + continue; + return pdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a PDO with the given index and returns a const pointer. + * + * \return Search result, or NULL. + */ +const ec_pdo_t *ec_pdo_list_find_pdo_const( + const ec_pdo_list_t *pl, /**< PDO list. */ + uint16_t index /**< PDO index. */ + ) +{ + const ec_pdo_t *pdo; + + list_for_each_entry(pdo, &pl->list, list) { + if (pdo->index != index) + continue; + return pdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a PDO via its position in the list. + * + * Const version. + * + * \return Zero on success, otherwise a negative error code. + */ +const ec_pdo_t *ec_pdo_list_find_pdo_by_pos_const( + const ec_pdo_list_t *pl, /**< PDO list. */ + unsigned int pos /**< Position in the list. */ + ) +{ + const ec_pdo_t *pdo; + + list_for_each_entry(pdo, &pl->list, list) { + if (pos--) + continue; + return pdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get the number of PDOs in the list. + * + * \return Number of PDOs. + */ +unsigned int ec_pdo_list_count( + const ec_pdo_list_t *pl /**< PDO list. */ + ) +{ + const ec_pdo_t *pdo; + unsigned int num = 0; + + list_for_each_entry(pdo, &pl->list, list) { + num++; + } + + return num; +} + +/****************************************************************************/ + +/** Outputs the PDOs in the list. + */ +void ec_pdo_list_print( + const ec_pdo_list_t *pl /**< PDO list. */ + ) +{ + const ec_pdo_t *pdo; + + if (list_empty(&pl->list)) { + printk(KERN_CONT "(none)"); + } else { + list_for_each_entry(pdo, &pl->list, list) { + printk(KERN_CONT "0x%04X", pdo->index); + if (pdo->list.next != &pl->list) + printk(KERN_CONT " "); + } + } +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/pdo_list.h b/ubuntu/igh-ecat/master/pdo_list.h new file mode 100644 index 00000000000000..5bd9be7f9a9035 --- /dev/null +++ b/ubuntu/igh-ecat/master/pdo_list.h @@ -0,0 +1,71 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT PDO list structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_PDO_LIST_H__ +#define __EC_PDO_LIST_H__ + +#include + +#include "globals.h" +#include "pdo.h" + +/****************************************************************************/ + +/** EtherCAT PDO list. + */ +typedef struct { + struct list_head list; /**< List of PDOs. */ +} ec_pdo_list_t; + +/****************************************************************************/ + +void ec_pdo_list_init(ec_pdo_list_t *); +void ec_pdo_list_clear(ec_pdo_list_t *); + +void ec_pdo_list_clear_pdos(ec_pdo_list_t *); + +ec_pdo_t *ec_pdo_list_add_pdo(ec_pdo_list_t *, uint16_t); +int ec_pdo_list_add_pdo_copy(ec_pdo_list_t *, const ec_pdo_t *); + +int ec_pdo_list_copy(ec_pdo_list_t *, const ec_pdo_list_t *); + +uint16_t ec_pdo_list_total_size(const ec_pdo_list_t *); +int ec_pdo_list_equal(const ec_pdo_list_t *, const ec_pdo_list_t *); + +ec_pdo_t *ec_pdo_list_find_pdo(const ec_pdo_list_t *, uint16_t); +const ec_pdo_t *ec_pdo_list_find_pdo_const(const ec_pdo_list_t *, + uint16_t); +const ec_pdo_t *ec_pdo_list_find_pdo_by_pos_const( + const ec_pdo_list_t *, unsigned int); +unsigned int ec_pdo_list_count(const ec_pdo_list_t *); + +void ec_pdo_list_print(const ec_pdo_list_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/reg_request.c b/ubuntu/igh-ecat/master/reg_request.c new file mode 100644 index 00000000000000..eab70b1d140b0c --- /dev/null +++ b/ubuntu/igh-ecat/master/reg_request.c @@ -0,0 +1,125 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Register request functions. + */ + +/****************************************************************************/ + +#include +#include +#include + +#include "reg_request.h" + +/****************************************************************************/ + +/** Register request constructor. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_reg_request_init( + ec_reg_request_t *reg, /**< Register request. */ + size_t size /**< Memory size. */ + ) +{ + if (!(reg->data = (uint8_t *) kmalloc(size, GFP_KERNEL))) { + EC_ERR("Failed to allocate %zu bytes of register memory.\n", size); + return -ENOMEM; + } + + INIT_LIST_HEAD(®->list); + reg->mem_size = size; + memset(reg->data, 0x00, size); + reg->dir = EC_DIR_INVALID; + reg->address = 0; + reg->transfer_size = 0; + reg->state = EC_INT_REQUEST_INIT; + reg->ring_position = 0; + return 0; +} + +/****************************************************************************/ + +/** Register request destructor. + */ +void ec_reg_request_clear( + ec_reg_request_t *reg /**< Register request. */ + ) +{ + if (reg->data) { + kfree(reg->data); + } +} + +/***************************************************************************** + * Application interface. + ****************************************************************************/ + +uint8_t *ecrt_reg_request_data(const ec_reg_request_t *reg) +{ + return reg->data; +} + +/****************************************************************************/ + +ec_request_state_t ecrt_reg_request_state(const ec_reg_request_t *reg) +{ + return ec_request_state_translation_table[reg->state]; +} + +/****************************************************************************/ + +int ecrt_reg_request_write(ec_reg_request_t *reg, uint16_t address, + size_t size) +{ + reg->dir = EC_DIR_OUTPUT; + reg->address = address; + reg->transfer_size = min(size, reg->mem_size); + reg->state = EC_INT_REQUEST_QUEUED; + return 0; +} + +/****************************************************************************/ + +int ecrt_reg_request_read(ec_reg_request_t *reg, uint16_t address, + size_t size) +{ + reg->dir = EC_DIR_INPUT; + reg->address = address; + reg->transfer_size = min(size, reg->mem_size); + reg->state = EC_INT_REQUEST_QUEUED; + return 0; +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_reg_request_data); +EXPORT_SYMBOL(ecrt_reg_request_state); +EXPORT_SYMBOL(ecrt_reg_request_write); +EXPORT_SYMBOL(ecrt_reg_request_read); + +/** \endcond */ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/reg_request.h b/ubuntu/igh-ecat/master/reg_request.h new file mode 100644 index 00000000000000..86876b6479169c --- /dev/null +++ b/ubuntu/igh-ecat/master/reg_request.h @@ -0,0 +1,59 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT register request structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_REG_REQUEST_H__ +#define __EC_REG_REQUEST_H__ + +#include + +#include "globals.h" + +/****************************************************************************/ + +/** Register request. + */ +struct ec_reg_request { + struct list_head list; /**< List item. */ + size_t mem_size; /**< Size of data memory. */ + uint8_t *data; /**< Pointer to data memory. */ + ec_direction_t dir; /**< Direction. EC_DIR_OUTPUT means writing to the + slave, EC_DIR_INPUT means reading from the slave. */ + uint16_t address; /**< Register address. */ + size_t transfer_size; /**< Size of the data to transfer. */ + ec_internal_request_state_t state; /**< Request state. */ + uint16_t ring_position; /**< Ring position for emergency requests. */ +}; + +/****************************************************************************/ + +int ec_reg_request_init(ec_reg_request_t *, size_t); +void ec_reg_request_clear(ec_reg_request_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/rt_locks.h b/ubuntu/igh-ecat/master/rt_locks.h new file mode 100644 index 00000000000000..bfe592171f29c2 --- /dev/null +++ b/ubuntu/igh-ecat/master/rt_locks.h @@ -0,0 +1,75 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Abstract locks for realtime part of interface. +*/ + +/****************************************************************************/ + +#ifndef __EC_LOCKS_H__ +#define __EC_LOCKS_H__ + +#include "globals.h" +#include + +#include + +/****************************************************************************/ + +#ifdef EC_USE_RTMUTEX + +#include + +typedef struct rt_mutex ec_lock_t; + +static inline void ec_lock_init(ec_lock_t *sem) { rt_mutex_init(sem); } +static inline void ec_lock_down(ec_lock_t *sem) { rt_mutex_lock(sem); } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 34) +static inline int ec_lock_down_interruptible(ec_lock_t *sem) { + return rt_mutex_lock_interruptible(sem); +} +#else +static inline int ec_lock_down_interruptible(ec_lock_t *sem) { + return rt_mutex_lock_interruptible(sem, 1); +} +#endif +static inline void ec_lock_up(ec_lock_t *sem) { rt_mutex_unlock(sem); } + +#else + +typedef struct semaphore ec_lock_t; + +static inline void ec_lock_init(ec_lock_t *sem) { sema_init(sem, 1); } +static inline void ec_lock_down(ec_lock_t *sem) { down(sem); } +static inline int ec_lock_down_interruptible(ec_lock_t *sem) { + return down_interruptible(sem); +} +static inline void ec_lock_up(ec_lock_t *sem) { up(sem); } + +#endif + +/****************************************************************************/ + +#endif + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/rtdm-ioctl.c b/ubuntu/igh-ecat/master/rtdm-ioctl.c new file mode 120000 index 00000000000000..738e33d1a82792 --- /dev/null +++ b/ubuntu/igh-ecat/master/rtdm-ioctl.c @@ -0,0 +1 @@ +ioctl.c \ No newline at end of file diff --git a/ubuntu/igh-ecat/master/rtdm.c b/ubuntu/igh-ecat/master/rtdm.c new file mode 100644 index 00000000000000..0112e1a7ba166e --- /dev/null +++ b/ubuntu/igh-ecat/master/rtdm.c @@ -0,0 +1,259 @@ +/***************************************************************************** + * + * Copyright (C) 2009-2010 Moehwald GmbH B. Benner + * 2011 IgH Andreas Stewering-Bone + * 2012 Florian Pose + * + * This file is part of the IgH EtherCAT master. + * + * The IgH EtherCAT master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as published + * by the Free Software Foundation; version 2 of the License. + * + * The IgH EtherCAT master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT master. If not, see . + * + ****************************************************************************/ + +/** \file + * RTDM interface. + */ + +#include +#include +#include + + +#include "master.h" +#include "ioctl.h" +#include "rtdm.h" +#include "rtdm_details.h" + +/* include last because it does some redefinitions */ +#include + +/** Set to 1 to enable device operations debugging. + */ +#define DEBUG 0 + +/****************************************************************************/ + +static int ec_rtdm_open(struct rtdm_dev_context *, rtdm_user_info_t *, int); +static int ec_rtdm_close(struct rtdm_dev_context *, rtdm_user_info_t *); +static int ec_rtdm_ioctl_nrt_handler(struct rtdm_dev_context *, + rtdm_user_info_t *, unsigned int, void __user *); +static int ec_rtdm_ioctl_rt_handler(struct rtdm_dev_context *, + rtdm_user_info_t *, unsigned int, void __user *); + +/****************************************************************************/ + +/** Initialize an RTDM device. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_rtdm_dev_init( + ec_rtdm_dev_t *rtdm_dev, /**< EtherCAT RTDM device. */ + ec_master_t *master /**< EtherCAT master. */ + ) +{ + int ret; + + rtdm_dev->master = master; + + rtdm_dev->dev = kzalloc(sizeof(struct rtdm_device), GFP_KERNEL); + if (!rtdm_dev->dev) { + EC_MASTER_ERR(master, "Failed to reserve memory for RTDM device.\n"); + return -ENOMEM; + } + + rtdm_dev->dev->struct_version = RTDM_DEVICE_STRUCT_VER; + rtdm_dev->dev->device_flags = RTDM_NAMED_DEVICE; + rtdm_dev->dev->context_size = sizeof(ec_rtdm_context_t); + snprintf(rtdm_dev->dev->device_name, RTDM_MAX_DEVNAME_LEN, + "EtherCAT%u", master->index); + rtdm_dev->dev->open_nrt = ec_rtdm_open; + rtdm_dev->dev->ops.close_nrt = ec_rtdm_close; + rtdm_dev->dev->ops.ioctl_rt = ec_rtdm_ioctl_rt_handler; + rtdm_dev->dev->ops.ioctl_nrt = ec_rtdm_ioctl_nrt_handler; + rtdm_dev->dev->device_class = RTDM_CLASS_EXPERIMENTAL; + rtdm_dev->dev->device_sub_class = 222; + rtdm_dev->dev->driver_name = "EtherCAT"; + rtdm_dev->dev->driver_version = RTDM_DRIVER_VER(1, 0, 2); + rtdm_dev->dev->peripheral_name = rtdm_dev->dev->device_name; + rtdm_dev->dev->provider_name = "EtherLab Community"; + rtdm_dev->dev->proc_name = rtdm_dev->dev->device_name; + rtdm_dev->dev->device_data = rtdm_dev; /* pointer to parent */ + + EC_MASTER_INFO(master, "Registering RTDM device %s.\n", + rtdm_dev->dev->driver_name); + ret = rtdm_dev_register(rtdm_dev->dev); + if (ret) { + EC_MASTER_ERR(master, "Initialization of RTDM interface failed" + " (return value %i).\n", ret); + kfree(rtdm_dev->dev); + } + + return ret; +} + +/****************************************************************************/ + +/** Clear an RTDM device. + */ +void ec_rtdm_dev_clear( + ec_rtdm_dev_t *rtdm_dev /**< EtherCAT RTDM device. */ + ) +{ + int ret; + + EC_MASTER_INFO(rtdm_dev->master, "Unregistering RTDM device %s.\n", + rtdm_dev->dev->driver_name); + ret = rtdm_dev_unregister(rtdm_dev->dev, 1000 /* poll delay [ms] */); + if (ret < 0) { + EC_MASTER_WARN(rtdm_dev->master, + "Failed to unregister RTDM device (code %i).\n", ret); + } + + kfree(rtdm_dev->dev); +} + +/****************************************************************************/ + +/** Driver open. + * + * \return Always zero (success). + */ +static int ec_rtdm_open( + struct rtdm_dev_context *context, /**< Context. */ + rtdm_user_info_t *user_info, /**< User data. */ + int oflags /**< Open flags. */ + ) +{ + ec_rtdm_context_t *ctx = (ec_rtdm_context_t *) context->dev_private; +#if DEBUG + ec_rtdm_dev_t *rtdm_dev = (ec_rtdm_dev_t *) context->device->device_data; +#endif + + ctx->user_fd = user_info; + ctx->ioctl_ctx.writable = oflags & O_WRONLY || oflags & O_RDWR; + ctx->ioctl_ctx.requested = 0; + ctx->ioctl_ctx.process_data = NULL; + ctx->ioctl_ctx.process_data_size = 0; + +#if DEBUG + EC_MASTER_INFO(rtdm_dev->master, "RTDM device %s opened.\n", + context->device->device_name); +#endif + return 0; +} + +/****************************************************************************/ + +/** Driver close. + * + * \return Always zero (success). + */ +static int ec_rtdm_close( + struct rtdm_dev_context *context, /**< Context. */ + rtdm_user_info_t *user_info /**< User data. */ + ) +{ + ec_rtdm_context_t *ctx = (ec_rtdm_context_t *) context->dev_private; + ec_rtdm_dev_t *rtdm_dev = (ec_rtdm_dev_t *) context->device->device_data; + + if (ctx->ioctl_ctx.requested) { + ecrt_release_master(rtdm_dev->master); + } + +#if DEBUG + EC_MASTER_INFO(rtdm_dev->master, "RTDM device %s closed.\n", + context->device->device_name); +#endif + return 0; +} + +/****************************************************************************/ + +/** Driver ioctl. + * + * \return ioctl() return code. + */ +static int ec_rtdm_ioctl_nrt_handler( + struct rtdm_dev_context *context, /**< Context. */ + rtdm_user_info_t *user_info, /**< User data. */ + unsigned int request, /**< Request. */ + void __user *arg /**< Argument. */ + ) +{ + ec_rtdm_context_t *ctx = (ec_rtdm_context_t *) context->dev_private; + ec_rtdm_dev_t *rtdm_dev = (ec_rtdm_dev_t *) context->device->device_data; + +#if DEBUG + EC_MASTER_INFO(rtdm_dev->master, "ioctl(request = %u, ctl = %02x)" + " on RTDM device %s.\n", request, _IOC_NR(request), + context->device->device_name); +#endif + return ec_ioctl_rtdm_nrt(rtdm_dev->master, &ctx->ioctl_ctx, request, arg); +} + +/****************************************************************************/ + +static int ec_rtdm_ioctl_rt_handler( + struct rtdm_dev_context *context, /**< Context. */ + rtdm_user_info_t *user_info, /**< User data. */ + unsigned int request, /**< Request. */ + void __user *arg /**< Argument. */ + ) +{ + int result; + ec_rtdm_context_t *ctx = (ec_rtdm_context_t *) context->dev_private; + ec_rtdm_dev_t *rtdm_dev = (ec_rtdm_dev_t *) context->device->device_data; + +#if DEBUG + EC_MASTER_INFO(rtdm_dev->master, "ioctl(request = %u, ctl = %02x)" + " on RTDM device %s.\n", request, _IOC_NR(request), + context->device->device_name); +#endif + result = + ec_ioctl_rtdm_rt(rtdm_dev->master, &ctx->ioctl_ctx, request, arg); + + if (result == -ENOTTY) { + /* Try again with nrt ioctl handler above in secondary mode. */ + return -ENOSYS; + } + return result; +} + +/****************************************************************************/ + +/** Memory-map process data to user space. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_rtdm_mmap( + ec_ioctl_context_t *ioctl_ctx, /**< Context. */ + void **user_address /**< Userspace address. */ + ) +{ + ec_rtdm_context_t *ctx = + container_of(ioctl_ctx, ec_rtdm_context_t, ioctl_ctx); + int ret; + + ret = rtdm_mmap_to_user(ctx->user_fd, + ioctl_ctx->process_data, ioctl_ctx->process_data_size, + PROT_READ | PROT_WRITE, + user_address, + NULL, NULL); + if (ret < 0) { + return ret; + } + + return 0; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/rtdm.h b/ubuntu/igh-ecat/master/rtdm.h new file mode 100644 index 00000000000000..3c2fa1380a0b3f --- /dev/null +++ b/ubuntu/igh-ecat/master/rtdm.h @@ -0,0 +1,50 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Florian Pose + * + * This file is part of the IgH EtherCAT master. + * + * The IgH EtherCAT master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as published + * by the Free Software Foundation; version 2 of the License. + * + * The IgH EtherCAT master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT master. If not, see . + * + ****************************************************************************/ + +/** \file + * RTDM interface. + */ + +#ifndef __EC_RTDM_H__ +#define __EC_RTDM_H__ + +#include "../include/ecrt.h" /* ec_master_t */ + +/****************************************************************************/ + +struct rtdm_device; + +/****************************************************************************/ + +/** EtherCAT RTDM device. + */ +typedef struct ec_rtdm_dev { + ec_master_t *master; /**< Master pointer. */ + struct rtdm_device *dev; /**< RTDM device. */ +} ec_rtdm_dev_t; + +/****************************************************************************/ + +int ec_rtdm_dev_init(ec_rtdm_dev_t *, ec_master_t *); +void ec_rtdm_dev_clear(ec_rtdm_dev_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/rtdm_details.h b/ubuntu/igh-ecat/master/rtdm_details.h new file mode 100644 index 00000000000000..d57ce01e5febc3 --- /dev/null +++ b/ubuntu/igh-ecat/master/rtdm_details.h @@ -0,0 +1,60 @@ +/***************************************************************************** + * + * Copyright (C) 2024 Bjarne von Horn + * + * This file is part of the IgH EtherCAT master. + * + * The IgH EtherCAT master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as published + * by the Free Software Foundation; version 2 of the License. + * + * The IgH EtherCAT master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT master. If not, see . + * + ****************************************************************************/ + +#ifndef __EC_RTDM_DETAILS_H__ +#define __EC_RTDM_DETAILS_H__ + +#include "../config.h" +#include "ioctl.h" + +#include + +#ifdef EC_RTDM_XENOMAI_V3 + +#include +#define EC_RTDM_USERFD_T struct rtdm_fd + +#else // EC_RTDM_XENOMAI_V3 + +#include + +#define EC_RTDM_USERFD_T rtdm_user_info_t + +#endif // EC_RTDM_XENOMAI_V3 + +/****************************************************************************/ + +/** Context structure for an open RTDM file handle. + */ +typedef struct ec_rtdm_context { + EC_RTDM_USERFD_T *user_fd; /**< RTDM user data. */ + ec_ioctl_context_t ioctl_ctx; /**< Context structure. */ +} ec_rtdm_context_t; + +/****************************************************************************/ + +static inline EC_RTDM_USERFD_T *ec_ioctl_to_rtdm(ec_ioctl_context_t *ctx) +{ + return container_of(ctx, ec_rtdm_context_t, ioctl_ctx)->user_fd; +} + +/****************************************************************************/ + +#endif // __EC_RTDM_DETAILS_H__ diff --git a/ubuntu/igh-ecat/master/rtdm_xenomai_v3.c b/ubuntu/igh-ecat/master/rtdm_xenomai_v3.c new file mode 100644 index 00000000000000..230e4172f9c778 --- /dev/null +++ b/ubuntu/igh-ecat/master/rtdm_xenomai_v3.c @@ -0,0 +1,193 @@ +/***************************************************************************** + * + * Copyright (C) 2009-2010 Moehwald GmbH B. Benner + * 2011 IgH Andreas Stewering-Bone + * 2012 Florian Pose + * + * This file is part of the IgH EtherCAT master. + * + * The IgH EtherCAT master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as published + * by the Free Software Foundation; version 2 of the License. + * + * The IgH EtherCAT master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT master. If not, see . + * + ****************************************************************************/ + +/** \file + * RTDM interface. + */ + +#include +#include +#include + +#include "master.h" +#include "ioctl.h" +#include "rtdm.h" +#include "rtdm_details.h" + +/** Set to 1 to enable device operations debugging. + */ +#define DEBUG_RTDM 0 + +/****************************************************************************/ + +static int ec_rtdm_open(struct rtdm_fd *fd, int oflags) +{ + struct ec_rtdm_context *ctx = rtdm_fd_to_private(fd); +#if DEBUG_RTDM + struct rtdm_device *dev = rtdm_fd_device(fd); + ec_rtdm_dev_t *rtdm_dev = dev->device_data; +#endif + + ctx->user_fd = fd; + + ctx->ioctl_ctx.writable = oflags & O_WRONLY || oflags & O_RDWR; + ctx->ioctl_ctx.requested = 0; + ctx->ioctl_ctx.process_data = NULL; + ctx->ioctl_ctx.process_data_size = 0; + +#if DEBUG_RTDM + EC_MASTER_INFO(rtdm_dev->master, "RTDM device %s opened.\n", + dev->name); +#endif + + return 0; +} + +/****************************************************************************/ + +static void ec_rtdm_close(struct rtdm_fd *fd) +{ + struct ec_rtdm_context *ctx = rtdm_fd_to_private(fd); + struct rtdm_device *dev = rtdm_fd_device(fd); + ec_rtdm_dev_t *rtdm_dev = dev->device_data; + + if (ctx->ioctl_ctx.requested) + ecrt_release_master(rtdm_dev->master); + + if (ctx->ioctl_ctx.process_data) + vfree(ctx->ioctl_ctx.process_data); + +#if DEBUG_RTDM + EC_MASTER_INFO(rtdm_dev->master, "RTDM device %s closed.\n", + dev->name); +#endif +} + +/****************************************************************************/ + +static int ec_rtdm_ioctl_rt_handler(struct rtdm_fd *fd, unsigned int request, + void __user *arg) +{ + int result; + struct ec_rtdm_context *ctx = rtdm_fd_to_private(fd); + struct rtdm_device *dev = rtdm_fd_device(fd); + ec_rtdm_dev_t *rtdm_dev = dev->device_data; + + result = + ec_ioctl_rtdm_rt(rtdm_dev->master, &ctx->ioctl_ctx, request, arg); + + if (result == -ENOTTY) + /* Try again with nrt ioctl handler below in secondary mode. */ + return -ENOSYS; + + return result; +} + +/****************************************************************************/ + +static int ec_rtdm_ioctl_nrt_handler(struct rtdm_fd *fd, unsigned int request, + void __user *arg) +{ + struct ec_rtdm_context *ctx = rtdm_fd_to_private(fd); + struct rtdm_device *dev = rtdm_fd_device(fd); + ec_rtdm_dev_t *rtdm_dev = dev->device_data; + + return ec_ioctl_rtdm_nrt(rtdm_dev->master, &ctx->ioctl_ctx, request, arg); +} + +/****************************************************************************/ + +static int ec_rtdm_mmap(struct rtdm_fd *fd, struct vm_area_struct *vma) +{ + struct ec_rtdm_context *ctx = + (struct ec_rtdm_context *) rtdm_fd_to_private(fd); + return rtdm_mmap_kmem(vma, (void *)ctx->ioctl_ctx.process_data); +} + +/****************************************************************************/ + +static struct rtdm_driver ec_rtdm_driver = { + .profile_info = RTDM_PROFILE_INFO(ec_rtdm, + RTDM_CLASS_EXPERIMENTAL, + 222, + 0), + .device_flags = RTDM_NAMED_DEVICE, + .device_count = EC_MAX_MASTERS, + .context_size = sizeof(struct ec_rtdm_context), + .ops = { + .open = ec_rtdm_open, + .close = ec_rtdm_close, + .ioctl_rt = ec_rtdm_ioctl_rt_handler, + .ioctl_nrt = ec_rtdm_ioctl_nrt_handler, + .mmap = ec_rtdm_mmap, + }, +}; + +/****************************************************************************/ + +int ec_rtdm_dev_init(ec_rtdm_dev_t *rtdm_dev, ec_master_t *master) +{ + struct rtdm_device *dev; + int ret; + + rtdm_dev->master = master; + + rtdm_dev->dev = kzalloc(sizeof(struct rtdm_device), GFP_KERNEL); + if (!rtdm_dev->dev) { + EC_MASTER_ERR(master, + "Failed to reserve memory for RTDM device.\n"); + return -ENOMEM; + } + + dev = rtdm_dev->dev; + + dev->driver = &ec_rtdm_driver; + dev->device_data = rtdm_dev; + dev->label = "EtherCAT%u"; + dev->minor = master->index; + + ret = rtdm_dev_register(dev); + if (ret) { + EC_MASTER_ERR(master, "Initialization of RTDM interface failed" + " (return value %i).\n", ret); + kfree(dev); + return ret; + } + + EC_MASTER_INFO(master, "Registered RTDM device %s.\n", dev->name); + + return 0; +} + +/****************************************************************************/ + +void ec_rtdm_dev_clear(ec_rtdm_dev_t *rtdm_dev) +{ + rtdm_dev_unregister(rtdm_dev->dev); + + EC_MASTER_INFO(rtdm_dev->master, "Unregistered RTDM device %s.\n", + rtdm_dev->dev->name); + + kfree(rtdm_dev->dev); +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/sdo.c b/ubuntu/igh-ecat/master/sdo.c new file mode 100644 index 00000000000000..3b8d3ac6ce7a1b --- /dev/null +++ b/ubuntu/igh-ecat/master/sdo.c @@ -0,0 +1,124 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + CANopen SDO functions. +*/ + +/****************************************************************************/ + +#include + +#include "master.h" + +#include "sdo.h" + +/****************************************************************************/ + +/** Constructor. + */ +void ec_sdo_init( + ec_sdo_t *sdo, /**< SDO. */ + ec_slave_t *slave, /**< Parent slave. */ + uint16_t index /**< SDO index. */ + ) +{ + sdo->slave = slave; + sdo->index = index; + sdo->object_code = 0x00; + sdo->name = NULL; + sdo->max_subindex = 0; + INIT_LIST_HEAD(&sdo->entries); +} + +/****************************************************************************/ + +/** SDO destructor. + * + * Clears and frees an SDO object. + */ +void ec_sdo_clear( + ec_sdo_t *sdo /**< SDO. */ + ) +{ + ec_sdo_entry_t *entry, *next; + + // free all entries + list_for_each_entry_safe(entry, next, &sdo->entries, list) { + list_del(&entry->list); + ec_sdo_entry_clear(entry); + kfree(entry); + } + + if (sdo->name) + kfree(sdo->name); +} + +/****************************************************************************/ + +/** Get an SDO entry from an SDO via its subindex. + * + * \retval >0 Pointer to the requested SDO entry. + * \retval NULL SDO entry not found. + */ +ec_sdo_entry_t *ec_sdo_get_entry( + ec_sdo_t *sdo, /**< SDO. */ + uint8_t subindex /**< Entry subindex. */ + ) +{ + ec_sdo_entry_t *entry; + + list_for_each_entry(entry, &sdo->entries, list) { + if (entry->subindex != subindex) + continue; + return entry; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get an SDO entry from an SDO via its subindex. + * + * const version. + * + * \retval >0 Pointer to the requested SDO entry. + * \retval NULL SDO entry not found. + */ +const ec_sdo_entry_t *ec_sdo_get_entry_const( + const ec_sdo_t *sdo, /**< SDO. */ + uint8_t subindex /**< Entry subindex. */ + ) +{ + const ec_sdo_entry_t *entry; + + list_for_each_entry(entry, &sdo->entries, list) { + if (entry->subindex != subindex) + continue; + return entry; + } + + return NULL; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/sdo.h b/ubuntu/igh-ecat/master/sdo.h new file mode 100644 index 00000000000000..5426bcaa2ec7f3 --- /dev/null +++ b/ubuntu/igh-ecat/master/sdo.h @@ -0,0 +1,61 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CANopen SDO structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SDO_H__ +#define __EC_SDO_H__ + +#include + +#include "globals.h" +#include "sdo_entry.h" + +/****************************************************************************/ + +/** CANopen SDO. + */ +struct ec_sdo { + struct list_head list; /**< List item. */ + ec_slave_t *slave; /**< Parent slave. */ + uint16_t index; /**< SDO index. */ + uint8_t object_code; /**< Object code. */ + char *name; /**< SDO name. */ + uint8_t max_subindex; /**< Maximum subindex. */ + struct list_head entries; /**< List of entries. */ +}; + +/****************************************************************************/ + +void ec_sdo_init(ec_sdo_t *, ec_slave_t *, uint16_t); +void ec_sdo_clear(ec_sdo_t *); + +ec_sdo_entry_t *ec_sdo_get_entry(ec_sdo_t *, uint8_t); +const ec_sdo_entry_t *ec_sdo_get_entry_const(const ec_sdo_t *, uint8_t); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/sdo_entry.c b/ubuntu/igh-ecat/master/sdo_entry.c new file mode 100644 index 00000000000000..ae4b36619828bb --- /dev/null +++ b/ubuntu/igh-ecat/master/sdo_entry.c @@ -0,0 +1,69 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + CANopen over EtherCAT SDO entry functions. +*/ + +/****************************************************************************/ + +#include + +#include "sdo_entry.h" + +/****************************************************************************/ + +/** Constructor. + */ +void ec_sdo_entry_init( + ec_sdo_entry_t *entry, /**< SDO entry. */ + ec_sdo_t *sdo, /**< Parent SDO. */ + uint8_t subindex /**< Subindex. */ + ) +{ + entry->sdo = sdo; + entry->subindex = subindex; + entry->data_type = 0x0000; + entry->bit_length = 0; + entry->read_access[EC_SDO_ENTRY_ACCESS_PREOP] = 0; + entry->read_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = 0; + entry->read_access[EC_SDO_ENTRY_ACCESS_OP] = 0; + entry->write_access[EC_SDO_ENTRY_ACCESS_PREOP] = 0; + entry->write_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = 0; + entry->write_access[EC_SDO_ENTRY_ACCESS_OP] = 0; + entry->description = NULL; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_sdo_entry_clear( + ec_sdo_entry_t *entry /**< SDO entry. */ + ) +{ + + if (entry->description) + kfree(entry->description); +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/sdo_entry.h b/ubuntu/igh-ecat/master/sdo_entry.h new file mode 100644 index 00000000000000..87c92bbd803cae --- /dev/null +++ b/ubuntu/igh-ecat/master/sdo_entry.h @@ -0,0 +1,64 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CANopen SDO entry structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SDO_ENTRY_H__ +#define __EC_SDO_ENTRY_H__ + +#include +#include + +#include "globals.h" + +/****************************************************************************/ + +struct ec_sdo; +typedef struct ec_sdo ec_sdo_t; /**< \see ec_sdo. */ + +/****************************************************************************/ + +/** CANopen SDO entry. + */ +typedef struct { + struct list_head list; /**< List item. */ + ec_sdo_t *sdo; /**< Parent SDO. */ + uint8_t subindex; /**< Subindex. */ + uint16_t data_type; /**< Data type. */ + uint16_t bit_length; /**< Data size in bit. */ + uint8_t read_access[EC_SDO_ENTRY_ACCESS_COUNT]; /**< Read access. */ + uint8_t write_access[EC_SDO_ENTRY_ACCESS_COUNT]; /**< Write access. */ + char *description; /**< Description. */ +} ec_sdo_entry_t; + +/****************************************************************************/ + +void ec_sdo_entry_init(ec_sdo_entry_t *, ec_sdo_t *, uint8_t); +void ec_sdo_entry_clear(ec_sdo_entry_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/sdo_request.c b/ubuntu/igh-ecat/master/sdo_request.c new file mode 100644 index 00000000000000..040c6b5d5a8a0c --- /dev/null +++ b/ubuntu/igh-ecat/master/sdo_request.c @@ -0,0 +1,256 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Canopen over EtherCAT SDO request functions. + */ + +/****************************************************************************/ + +#include +#include +#include + +#include "sdo_request.h" + +/****************************************************************************/ + +/** Default timeout in ms to wait for SDO transfer responses. + */ +#define EC_SDO_REQUEST_RESPONSE_TIMEOUT 1000 + +/****************************************************************************/ + +void ec_sdo_request_clear_data(ec_sdo_request_t *); + +/****************************************************************************/ + +/** SDO request constructor. + */ +void ec_sdo_request_init( + ec_sdo_request_t *req /**< SDO request. */ + ) +{ + req->complete_access = 0; + req->data = NULL; + req->mem_size = 0; + req->data_size = 0; + req->issue_timeout = 0; // no timeout + req->response_timeout = EC_SDO_REQUEST_RESPONSE_TIMEOUT; + req->dir = EC_DIR_INVALID; + req->state = EC_INT_REQUEST_INIT; + req->jiffies_start = 0U; + req->jiffies_sent = 0U; + req->errno = 0; + req->abort_code = 0x00000000; +} + +/****************************************************************************/ + +/** SDO request destructor. + */ +void ec_sdo_request_clear( + ec_sdo_request_t *req /**< SDO request. */ + ) +{ + ec_sdo_request_clear_data(req); +} + +/****************************************************************************/ + +/** Copy another SDO request. + * + * \attention Only the index subindex and data are copied. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_sdo_request_copy( + ec_sdo_request_t *req, /**< SDO request. */ + const ec_sdo_request_t *other /**< Other SDO request to copy from. */ + ) +{ + req->complete_access = other->complete_access; + req->index = other->index; + req->subindex = other->subindex; + return ec_sdo_request_copy_data(req, other->data, other->data_size); +} + +/****************************************************************************/ + +/** SDO request destructor. + */ +void ec_sdo_request_clear_data( + ec_sdo_request_t *req /**< SDO request. */ + ) +{ + if (req->data) { + kfree(req->data); + req->data = NULL; + } + + req->mem_size = 0; + req->data_size = 0; +} + +/****************************************************************************/ + +/** Pre-allocates the data memory. + * + * If the \a mem_size is already bigger than \a size, nothing is done. + * + * \return 0 on success, otherwise -ENOMEM. + */ +int ec_sdo_request_alloc( + ec_sdo_request_t *req, /**< SDO request. */ + size_t size /**< Data size to allocate. */ + ) +{ + if (size <= req->mem_size) + return 0; + + ec_sdo_request_clear_data(req); + + if (!(req->data = (uint8_t *) kmalloc(size, GFP_KERNEL))) { + EC_ERR("Failed to allocate %zu bytes of SDO memory.\n", size); + return -ENOMEM; + } + + req->mem_size = size; + req->data_size = 0; + return 0; +} + +/****************************************************************************/ + +/** Copies SDO data from an external source. + * + * If the \a mem_size is to small, new memory is allocated. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_sdo_request_copy_data( + ec_sdo_request_t *req, /**< SDO request. */ + const uint8_t *source, /**< Source data. */ + size_t size /**< Number of bytes in \a source. */ + ) +{ + int ret = ec_sdo_request_alloc(req, size); + if (ret < 0) + return ret; + + memcpy(req->data, source, size); + req->data_size = size; + return 0; +} + +/****************************************************************************/ + +/** Checks, if the timeout was exceeded. + * + * \return non-zero if the timeout was exceeded, else zero. + */ +int ec_sdo_request_timed_out(const ec_sdo_request_t *req /**< SDO request. */) +{ + return req->issue_timeout + && jiffies - req->jiffies_start > HZ * req->issue_timeout / 1000; +} + +/***************************************************************************** + * Application interface. + ****************************************************************************/ + +int ecrt_sdo_request_index(ec_sdo_request_t *req, uint16_t index, + uint8_t subindex) +{ + req->index = index; + req->subindex = subindex; + return 0; +} + +/****************************************************************************/ + +int ecrt_sdo_request_timeout(ec_sdo_request_t *req, uint32_t timeout) +{ + req->issue_timeout = timeout; + return 0; +} + +/****************************************************************************/ + +uint8_t *ecrt_sdo_request_data(const ec_sdo_request_t *req) +{ + return req->data; +} + +/****************************************************************************/ + +size_t ecrt_sdo_request_data_size(const ec_sdo_request_t *req) +{ + return req->data_size; +} + +/****************************************************************************/ + +ec_request_state_t ecrt_sdo_request_state(const ec_sdo_request_t *req) +{ + return ec_request_state_translation_table[req->state]; +} + +/****************************************************************************/ + +int ecrt_sdo_request_read(ec_sdo_request_t *req) +{ + req->dir = EC_DIR_INPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->errno = 0; + req->abort_code = 0x00000000; + req->jiffies_start = jiffies; + return 0; +} + +/****************************************************************************/ + +int ecrt_sdo_request_write(ec_sdo_request_t *req) +{ + req->dir = EC_DIR_OUTPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->errno = 0; + req->abort_code = 0x00000000; + req->jiffies_start = jiffies; + return 0; +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_sdo_request_index); +EXPORT_SYMBOL(ecrt_sdo_request_timeout); +EXPORT_SYMBOL(ecrt_sdo_request_data); +EXPORT_SYMBOL(ecrt_sdo_request_data_size); +EXPORT_SYMBOL(ecrt_sdo_request_state); +EXPORT_SYMBOL(ecrt_sdo_request_read); +EXPORT_SYMBOL(ecrt_sdo_request_write); + +/** \endcond */ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/sdo_request.h b/ubuntu/igh-ecat/master/sdo_request.h new file mode 100644 index 00000000000000..aa2d1849cec329 --- /dev/null +++ b/ubuntu/igh-ecat/master/sdo_request.h @@ -0,0 +1,75 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CANopen SDO request structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SDO_REQUEST_H__ +#define __EC_SDO_REQUEST_H__ + +#include + +#include "globals.h" + +/****************************************************************************/ + +/** CANopen SDO request. + */ +struct ec_sdo_request { + struct list_head list; /**< List item. */ + uint16_t index; /**< SDO index. */ + uint8_t subindex; /**< SDO subindex. */ + uint8_t *data; /**< Pointer to SDO data. */ + size_t mem_size; /**< Size of SDO data memory. */ + size_t data_size; /**< Size of SDO data. */ + uint8_t complete_access; /**< SDO shall be transferred completely. */ + uint32_t issue_timeout; /**< Maximum time in ms, the processing of the + request may take. */ + uint32_t response_timeout; /**< Maximum time in ms, the transfer is + retried, if the slave does not respond. */ + ec_direction_t dir; /**< Direction. EC_DIR_OUTPUT means downloading to + the slave, EC_DIR_INPUT means uploading from the + slave. */ + ec_internal_request_state_t state; /**< SDO request state. */ + unsigned long jiffies_start; /**< Jiffies, when the request was issued. */ + unsigned long jiffies_sent; /**< Jiffies, when the upload/download + request was sent. */ + int errno; /**< Error number. */ + uint32_t abort_code; /**< SDO request abort code. Zero on success. */ +}; + +/****************************************************************************/ + +void ec_sdo_request_init(ec_sdo_request_t *); +void ec_sdo_request_clear(ec_sdo_request_t *); + +int ec_sdo_request_copy(ec_sdo_request_t *, const ec_sdo_request_t *); +int ec_sdo_request_alloc(ec_sdo_request_t *, size_t); +int ec_sdo_request_copy_data(ec_sdo_request_t *, const uint8_t *, size_t); +int ec_sdo_request_timed_out(const ec_sdo_request_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/slave.c b/ubuntu/igh-ecat/master/slave.c new file mode 100644 index 00000000000000..04cf2151daff7e --- /dev/null +++ b/ubuntu/igh-ecat/master/slave.c @@ -0,0 +1,1010 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave methods. +*/ + +/****************************************************************************/ + +#include +#include + +#include "globals.h" +#include "datagram.h" +#include "master.h" +#include "slave_config.h" + +#include "slave.h" + +/****************************************************************************/ + +extern const ec_code_msg_t al_status_messages[]; + +/****************************************************************************/ + +// prototypes for private methods +char *ec_slave_sii_string(const ec_slave_t *, unsigned int); +void ec_slave_find_names_for_pdo(ec_slave_t *, ec_pdo_t *); +unsigned int ec_slave_get_previous_port(const ec_slave_t *, unsigned int); +unsigned int ec_slave_get_next_port(const ec_slave_t *, unsigned int); +uint32_t ec_slave_calc_rtt_sum(const ec_slave_t *); +ec_slave_t *ec_slave_find_next_dc_slave(ec_slave_t *); + +/****************************************************************************/ + +/** + Slave constructor. + \return 0 in case of success, else < 0 +*/ + +void ec_slave_init( + ec_slave_t *slave, /**< EtherCAT slave */ + ec_master_t *master, /**< EtherCAT master */ + ec_device_index_t dev_idx, /**< Device index. */ + uint16_t ring_position, /**< ring position */ + uint16_t station_address /**< station address to configure */ + ) +{ + unsigned int i; + + slave->master = master; + slave->device_index = dev_idx; + slave->ring_position = ring_position; + slave->station_address = station_address; + slave->effective_alias = 0x0000; + + slave->config = NULL; + slave->requested_state = EC_SLAVE_STATE_PREOP; + slave->current_state = EC_SLAVE_STATE_UNKNOWN; + slave->error_flag = 0; + slave->force_config = 0; + slave->configured_rx_mailbox_offset = 0x0000; + slave->configured_rx_mailbox_size = 0x0000; + slave->configured_tx_mailbox_offset = 0x0000; + slave->configured_tx_mailbox_size = 0x0000; + + slave->base_type = 0; + slave->base_revision = 0; + slave->base_build = 0; + slave->base_fmmu_count = 0; + slave->base_sync_count = 0; + + for (i = 0; i < EC_MAX_PORTS; i++) { + slave->ports[i].desc = EC_PORT_NOT_IMPLEMENTED; + + slave->ports[i].link.link_up = 0; + slave->ports[i].link.loop_closed = 0; + slave->ports[i].link.signal_detected = 0; + slave->sii.physical_layer[i] = 0xFF; + + slave->ports[i].receive_time = 0U; + + slave->ports[i].next_slave = NULL; + slave->ports[i].delay_to_next_dc = 0U; + } + + slave->base_fmmu_bit_operation = 0; + slave->base_dc_supported = 0; + slave->base_dc_range = EC_DC_32; + slave->has_dc_system_time = 0; + slave->transmission_delay = 0U; + + slave->sii_words = NULL; + slave->sii_nwords = 0; + + slave->sii.alias = 0x0000; + slave->sii.vendor_id = 0x00000000; + slave->sii.product_code = 0x00000000; + slave->sii.revision_number = 0x00000000; + slave->sii.serial_number = 0x00000000; + slave->sii.boot_rx_mailbox_offset = 0x0000; + slave->sii.boot_rx_mailbox_size = 0x0000; + slave->sii.boot_tx_mailbox_offset = 0x0000; + slave->sii.boot_tx_mailbox_size = 0x0000; + slave->sii.std_rx_mailbox_offset = 0x0000; + slave->sii.std_rx_mailbox_size = 0x0000; + slave->sii.std_tx_mailbox_offset = 0x0000; + slave->sii.std_tx_mailbox_size = 0x0000; + slave->sii.mailbox_protocols = 0; + + slave->sii.strings = NULL; + slave->sii.string_count = 0; + + slave->sii.has_general = 0; + slave->sii.group = NULL; + slave->sii.image = NULL; + slave->sii.order = NULL; + slave->sii.name = NULL; + memset(&slave->sii.coe_details, 0x00, sizeof(ec_sii_coe_details_t)); + memset(&slave->sii.general_flags, 0x00, sizeof(ec_sii_general_flags_t)); + slave->sii.current_on_ebus = 0; + + slave->sii.syncs = NULL; + slave->sii.sync_count = 0; + + INIT_LIST_HEAD(&slave->sii.pdos); + + INIT_LIST_HEAD(&slave->sdo_dictionary); + + slave->sdo_dictionary_fetched = 0; + slave->jiffies_preop = 0; + + INIT_LIST_HEAD(&slave->sdo_requests); + INIT_LIST_HEAD(&slave->reg_requests); + INIT_LIST_HEAD(&slave->foe_requests); + INIT_LIST_HEAD(&slave->soe_requests); + INIT_LIST_HEAD(&slave->eoe_requests); + + // create state machine object + ec_fsm_slave_init(&slave->fsm, slave); +} + +/****************************************************************************/ + +/** + Slave destructor. + Clears and frees a slave object. +*/ + +void ec_slave_clear(ec_slave_t *slave /**< EtherCAT slave */) +{ + ec_sdo_t *sdo, *next_sdo; + unsigned int i; + ec_pdo_t *pdo, *next_pdo; + + // abort all pending requests + + while (!list_empty(&slave->sdo_requests)) { + ec_sdo_request_t *request = + list_entry(slave->sdo_requests.next, ec_sdo_request_t, list); + list_del_init(&request->list); // dequeue + EC_SLAVE_WARN(slave, "Discarding SDO request," + " slave about to be deleted.\n"); + request->state = EC_INT_REQUEST_FAILURE; + } + + while (!list_empty(&slave->reg_requests)) { + ec_reg_request_t *reg = + list_entry(slave->reg_requests.next, ec_reg_request_t, list); + list_del_init(®->list); // dequeue + EC_SLAVE_WARN(slave, "Discarding register request," + " slave about to be deleted.\n"); + reg->state = EC_INT_REQUEST_FAILURE; + } + + while (!list_empty(&slave->foe_requests)) { + ec_foe_request_t *request = + list_entry(slave->foe_requests.next, ec_foe_request_t, list); + list_del_init(&request->list); // dequeue + EC_SLAVE_WARN(slave, "Discarding FoE request," + " slave about to be deleted.\n"); + request->state = EC_INT_REQUEST_FAILURE; + } + + while (!list_empty(&slave->soe_requests)) { + ec_soe_request_t *request = + list_entry(slave->soe_requests.next, ec_soe_request_t, list); + list_del_init(&request->list); // dequeue + EC_SLAVE_WARN(slave, "Discarding SoE request," + " slave about to be deleted.\n"); + request->state = EC_INT_REQUEST_FAILURE; + } + +#ifdef EC_EOE + while (!list_empty(&slave->eoe_requests)) { + ec_eoe_request_t *request = + list_entry(slave->eoe_requests.next, ec_eoe_request_t, list); + list_del_init(&request->list); // dequeue + EC_SLAVE_WARN(slave, "Discarding EoE request," + " slave about to be deleted.\n"); + request->state = EC_INT_REQUEST_FAILURE; + } +#endif + + wake_up_all(&slave->master->request_queue); + + if (slave->config) { + ec_slave_config_detach(slave->config); + } + + // free all SDOs + list_for_each_entry_safe(sdo, next_sdo, &slave->sdo_dictionary, list) { + list_del(&sdo->list); + ec_sdo_clear(sdo); + kfree(sdo); + } + + // free all strings + if (slave->sii.strings) { + for (i = 0; i < slave->sii.string_count; i++) + kfree(slave->sii.strings[i]); + kfree(slave->sii.strings); + } + + // free all sync managers + ec_slave_clear_sync_managers(slave); + + // free all SII PDOs + list_for_each_entry_safe(pdo, next_pdo, &slave->sii.pdos, list) { + list_del(&pdo->list); + ec_pdo_clear(pdo); + kfree(pdo); + } + + if (slave->sii_words) { + kfree(slave->sii_words); + } + + ec_fsm_slave_clear(&slave->fsm); +} + +/****************************************************************************/ + +/** Clear the sync manager array. + */ +void ec_slave_clear_sync_managers(ec_slave_t *slave /**< EtherCAT slave. */) +{ + unsigned int i; + + if (slave->sii.syncs) { + for (i = 0; i < slave->sii.sync_count; i++) { + ec_sync_clear(&slave->sii.syncs[i]); + } + kfree(slave->sii.syncs); + slave->sii.syncs = NULL; + } +} + +/****************************************************************************/ + +/** + * Sets the application state of a slave. + */ + +void ec_slave_set_state(ec_slave_t *slave, /**< EtherCAT slave */ + ec_slave_state_t new_state /**< new application state */ + ) +{ + if (new_state != slave->current_state) { + if (slave->master->debug_level) { + char old_state[EC_STATE_STRING_SIZE], + cur_state[EC_STATE_STRING_SIZE]; + ec_state_string(slave->current_state, old_state, 0); + ec_state_string(new_state, cur_state, 0); + EC_SLAVE_DBG(slave, 0, "%s -> %s.\n", old_state, cur_state); + } + slave->current_state = new_state; + } +} + +/****************************************************************************/ + +/** + * Request a slave state and resets the error flag. + */ + +void ec_slave_request_state(ec_slave_t *slave, /**< EtherCAT slave */ + ec_slave_state_t state /**< new state */ + ) +{ + slave->requested_state = state; + slave->error_flag = 0; +} + +/****************************************************************************/ + +/** + Fetches data from a STRING category. + \todo range checking + \return 0 in case of success, else < 0 +*/ + +int ec_slave_fetch_sii_strings( + ec_slave_t *slave, /**< EtherCAT slave */ + const uint8_t *data, /**< category data */ + size_t data_size /**< number of bytes */ + ) +{ + int i, err; + size_t size; + off_t offset; + + slave->sii.string_count = data[0]; + + if (slave->sii.string_count) { + if (!(slave->sii.strings = + kmalloc(sizeof(char *) * slave->sii.string_count, + GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate string array memory.\n"); + err = -ENOMEM; + goto out_zero; + } + + offset = 1; + for (i = 0; i < slave->sii.string_count; i++) { + size = data[offset]; + // allocate memory for string structure and data at a single blow + if (!(slave->sii.strings[i] = + kmalloc(sizeof(char) * size + 1, GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate string memory.\n"); + err = -ENOMEM; + goto out_free; + } + memcpy(slave->sii.strings[i], data + offset + 1, size); + slave->sii.strings[i][size] = 0x00; // append binary zero + offset += 1 + size; + } + } + + return 0; + +out_free: + for (i--; i >= 0; i--) + kfree(slave->sii.strings[i]); + kfree(slave->sii.strings); + slave->sii.strings = NULL; +out_zero: + slave->sii.string_count = 0; + return err; +} + +/****************************************************************************/ + +/** + Fetches data from a GENERAL category. + \return 0 in case of success, else < 0 +*/ + +int ec_slave_fetch_sii_general( + ec_slave_t *slave, /**< EtherCAT slave */ + const uint8_t *data, /**< category data */ + size_t data_size /**< size in bytes */ + ) +{ + unsigned int i; + uint8_t flags; + + if (data_size != 32) { + EC_SLAVE_ERR(slave, "Wrong size of general category (%zu/32).\n", + data_size); + return -EINVAL; + } + + slave->sii.group = ec_slave_sii_string(slave, data[0]); + slave->sii.image = ec_slave_sii_string(slave, data[1]); + slave->sii.order = ec_slave_sii_string(slave, data[2]); + slave->sii.name = ec_slave_sii_string(slave, data[3]); + + for (i = 0; i < 4; i++) + slave->sii.physical_layer[i] = + (data[4] & (0x03 << (i * 2))) >> (i * 2); + + // read CoE details + flags = EC_READ_U8(data + 5); + slave->sii.coe_details.enable_sdo = (flags >> 0) & 0x01; + slave->sii.coe_details.enable_sdo_info = (flags >> 1) & 0x01; + slave->sii.coe_details.enable_pdo_assign = (flags >> 2) & 0x01; + slave->sii.coe_details.enable_pdo_configuration = (flags >> 3) & 0x01; + slave->sii.coe_details.enable_upload_at_startup = (flags >> 4) & 0x01; + slave->sii.coe_details.enable_sdo_complete_access = (flags >> 5) & 0x01; + + // read general flags + flags = EC_READ_U8(data + 0x000B); + slave->sii.general_flags.enable_safeop = (flags >> 0) & 0x01; + slave->sii.general_flags.enable_not_lrw = (flags >> 1) & 0x01; + + slave->sii.current_on_ebus = EC_READ_S16(data + 0x0C); + slave->sii.has_general = 1; + return 0; +} + +/****************************************************************************/ + +/** Fetches data from a SYNC MANAGER category. + * + * Appends the sync managers described in the category to the existing ones. + * + * \return 0 in case of success, else < 0 + */ +int ec_slave_fetch_sii_syncs( + ec_slave_t *slave, /**< EtherCAT slave. */ + const uint8_t *data, /**< Category data. */ + size_t data_size /**< Number of bytes. */ + ) +{ + unsigned int i, count, total_count; + ec_sync_t *sync; + size_t memsize; + ec_sync_t *syncs; + uint8_t index; + + // one sync manager struct is 4 words long + if (data_size % 8) { + EC_SLAVE_ERR(slave, "Invalid SII sync manager category size %zu.\n", + data_size); + return -EINVAL; + } + + count = data_size / 8; + + if (count) { + total_count = count + slave->sii.sync_count; + if (total_count > EC_MAX_SYNC_MANAGERS) { + EC_SLAVE_ERR(slave, "Exceeded maximum number of" + " sync managers!\n"); + return -EOVERFLOW; + } + memsize = sizeof(ec_sync_t) * total_count; + if (!(syncs = kmalloc(memsize, GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate %zu bytes" + " for sync managers.\n", memsize); + return -ENOMEM; + } + + for (i = 0; i < slave->sii.sync_count; i++) + ec_sync_init_copy(syncs + i, slave->sii.syncs + i); + + // initialize new sync managers + for (i = 0; i < count; i++, data += 8) { + index = i + slave->sii.sync_count; + sync = &syncs[index]; + + ec_sync_init(sync, slave); + sync->physical_start_address = EC_READ_U16(data); + sync->default_length = EC_READ_U16(data + 2); + sync->control_register = EC_READ_U8(data + 4); + sync->enable = EC_READ_U8(data + 6); + } + + if (slave->sii.syncs) + kfree(slave->sii.syncs); + slave->sii.syncs = syncs; + slave->sii.sync_count = total_count; + } + + return 0; +} + +/****************************************************************************/ + +/** + Fetches data from a [RT]xPDO category. + \return 0 in case of success, else < 0 +*/ + +int ec_slave_fetch_sii_pdos( + ec_slave_t *slave, /**< EtherCAT slave */ + const uint8_t *data, /**< category data */ + size_t data_size, /**< number of bytes */ + ec_direction_t dir /**< PDO direction. */ + ) +{ + int ret; + ec_pdo_t *pdo; + ec_pdo_entry_t *entry; + unsigned int entry_count, i; + + while (data_size >= 8) { + if (!(pdo = kmalloc(sizeof(ec_pdo_t), GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate PDO memory.\n"); + return -ENOMEM; + } + + ec_pdo_init(pdo); + pdo->index = EC_READ_U16(data); + entry_count = EC_READ_U8(data + 2); + pdo->sync_index = EC_READ_U8(data + 3); + ret = ec_pdo_set_name(pdo, + ec_slave_sii_string(slave, EC_READ_U8(data + 5))); + if (ret) { + ec_pdo_clear(pdo); + kfree(pdo); + return ret; + } + list_add_tail(&pdo->list, &slave->sii.pdos); + + data_size -= 8; + data += 8; + + for (i = 0; i < entry_count; i++) { + if (!(entry = kmalloc(sizeof(ec_pdo_entry_t), GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate PDO entry memory.\n"); + return -ENOMEM; + } + + ec_pdo_entry_init(entry); + entry->index = EC_READ_U16(data); + entry->subindex = EC_READ_U8(data + 2); + ret = ec_pdo_entry_set_name(entry, + ec_slave_sii_string(slave, EC_READ_U8(data + 3))); + if (ret) { + ec_pdo_entry_clear(entry); + kfree(entry); + return ret; + } + entry->bit_length = EC_READ_U8(data + 5); + list_add_tail(&entry->list, &pdo->entries); + + data_size -= 8; + data += 8; + } + + // if sync manager index is positive, the PDO is mapped by default + if (pdo->sync_index >= 0) { + ec_sync_t *sync; + + if (!(sync = ec_slave_get_sync(slave, pdo->sync_index))) { + EC_SLAVE_ERR(slave, "Invalid SM index %i for PDO 0x%04X.", + pdo->sync_index, pdo->index); + return -ENOENT; + } + + ret = ec_pdo_list_add_pdo_copy(&sync->pdos, pdo); + if (ret) + return ret; + } + } + + return 0; +} + +/****************************************************************************/ + +/** + Searches the string list for an index. + \return 0 in case of success, else < 0 +*/ + +char *ec_slave_sii_string( + const ec_slave_t *slave, /**< EtherCAT slave */ + unsigned int index /**< string index */ + ) +{ + if (!index--) + return NULL; + + if (index >= slave->sii.string_count) { + EC_SLAVE_DBG(slave, 1, "String %u not found.\n", index); + return NULL; + } + + return slave->sii.strings[index]; +} + +/****************************************************************************/ + +/** Get the sync manager given an index. + * + * \return pointer to sync manager, or NULL. + */ +ec_sync_t *ec_slave_get_sync( + ec_slave_t *slave, /**< EtherCAT slave. */ + uint8_t sync_index /**< Sync manager index. */ + ) +{ + if (sync_index < slave->sii.sync_count) { + return &slave->sii.syncs[sync_index]; + } else { + return NULL; + } +} + +/****************************************************************************/ + +/** + Counts the total number of SDOs and entries in the dictionary. +*/ + +void ec_slave_sdo_dict_info(const ec_slave_t *slave, /**< EtherCAT slave */ + unsigned int *sdo_count, /**< number of SDOs */ + unsigned int *entry_count /**< total number of + entries */ + ) +{ + unsigned int sdos = 0, entries = 0; + ec_sdo_t *sdo; + ec_sdo_entry_t *entry; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + sdos++; + list_for_each_entry(entry, &sdo->entries, list) { + entries++; + } + } + + *sdo_count = sdos; + *entry_count = entries; +} + +/****************************************************************************/ + +/** + * Get an SDO from the dictionary. + * \returns The desired SDO, or NULL. + */ + +ec_sdo_t *ec_slave_get_sdo( + ec_slave_t *slave, /**< EtherCAT slave */ + uint16_t index /**< SDO index */ + ) +{ + ec_sdo_t *sdo; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + if (sdo->index != index) + continue; + return sdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** + * Get an SDO from the dictionary. + * + * const version. + * + * \returns The desired SDO, or NULL. + */ + +const ec_sdo_t *ec_slave_get_sdo_const( + const ec_slave_t *slave, /**< EtherCAT slave */ + uint16_t index /**< SDO index */ + ) +{ + const ec_sdo_t *sdo; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + if (sdo->index != index) + continue; + return sdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get an SDO from the dictionary, given its position in the list. + * \returns The desired SDO, or NULL. + */ + +const ec_sdo_t *ec_slave_get_sdo_by_pos_const( + const ec_slave_t *slave, /**< EtherCAT slave. */ + uint16_t sdo_position /**< SDO list position. */ + ) +{ + const ec_sdo_t *sdo; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + if (sdo_position--) + continue; + return sdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get the number of SDOs in the dictionary. + * \returns SDO count. + */ + +uint16_t ec_slave_sdo_count( + const ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + const ec_sdo_t *sdo; + uint16_t count = 0; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Finds a mapped PDO. + * \returns The desired PDO object, or NULL. + */ +const ec_pdo_t *ec_slave_find_pdo( + const ec_slave_t *slave, /**< Slave. */ + uint16_t index /**< PDO index to find. */ + ) +{ + unsigned int i; + const ec_sync_t *sync; + const ec_pdo_t *pdo; + + for (i = 0; i < slave->sii.sync_count; i++) { + sync = &slave->sii.syncs[i]; + + if (!(pdo = ec_pdo_list_find_pdo_const(&sync->pdos, index))) + continue; + + return pdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Find name for a PDO and its entries. + */ +void ec_slave_find_names_for_pdo( + ec_slave_t *slave, + ec_pdo_t *pdo + ) +{ + const ec_sdo_t *sdo; + ec_pdo_entry_t *pdo_entry; + const ec_sdo_entry_t *sdo_entry; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + if (sdo->index == pdo->index) { + ec_pdo_set_name(pdo, sdo->name); + } else { + list_for_each_entry(pdo_entry, &pdo->entries, list) { + if (sdo->index == pdo_entry->index) { + sdo_entry = ec_sdo_get_entry_const( + sdo, pdo_entry->subindex); + if (sdo_entry) { + ec_pdo_entry_set_name(pdo_entry, + sdo_entry->description); + } + } + } + } + } +} + +/****************************************************************************/ + +/** Attach PDO names. + */ +void ec_slave_attach_pdo_names( + ec_slave_t *slave + ) +{ + unsigned int i; + ec_sync_t *sync; + ec_pdo_t *pdo; + + for (i = 0; i < slave->sii.sync_count; i++) { + sync = slave->sii.syncs + i; + list_for_each_entry(pdo, &sync->pdos.list, list) { + ec_slave_find_names_for_pdo(slave, pdo); + } + } +} + +/****************************************************************************/ + +/** Returns the previous connected port of a given port. + * + * \return Port index. + */ +unsigned int ec_slave_get_previous_port( + const ec_slave_t *slave, /**< EtherCAT slave. */ + unsigned int port_index /**< Port index. */ + ) +{ + static const unsigned int prev_table[EC_MAX_PORTS] = { + 2, 3, 1, 0 + }; + + if (port_index >= EC_MAX_PORTS) { + EC_SLAVE_WARN(slave, "%s(port_index=%u): Invalid port index!\n", + __func__, port_index); + } + + do { + port_index = prev_table[port_index]; + if (slave->ports[port_index].next_slave) { + return port_index; + } + } while (port_index); + + return 0; +} + +/****************************************************************************/ + +/** Returns the next connected port of a given port. + * + * \return Port index. + */ +unsigned int ec_slave_get_next_port( + const ec_slave_t *slave, /**< EtherCAT slave. */ + unsigned int port_index /**< Port index. */ + ) +{ + static const unsigned int next_table[EC_MAX_PORTS] = { + 3, 2, 0, 1 + }; + + if (port_index >= EC_MAX_PORTS) { + EC_SLAVE_WARN(slave, "%s(port_index=%u): Invalid port index!\n", + __func__, port_index); + } + + do { + port_index = next_table[port_index]; + if (slave->ports[port_index].next_slave) { + return port_index; + } + } while (port_index); + + return 0; +} + +/****************************************************************************/ + +/** Calculates the sum of round-trip-times of connected ports 1-3. + * + * \return Round-trip-time in ns. + */ +uint32_t ec_slave_calc_rtt_sum( + const ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + uint32_t rtt_sum = 0, rtt; + unsigned int port_index = ec_slave_get_next_port(slave, 0); + + while (port_index != 0) { + unsigned int prev_index = + ec_slave_get_previous_port(slave, port_index); + + rtt = slave->ports[port_index].receive_time - + slave->ports[prev_index].receive_time; + rtt_sum += rtt; + port_index = ec_slave_get_next_port(slave, port_index); + } + + return rtt_sum; +} + +/****************************************************************************/ + +/** Finds the next slave supporting DC delay measurement. + * + * \return Next DC slave, or NULL. + */ +ec_slave_t *ec_slave_find_next_dc_slave( + ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + unsigned int port_index; + ec_slave_t *dc_slave = NULL; + + if (slave->base_dc_supported) { + dc_slave = slave; + } else { + port_index = ec_slave_get_next_port(slave, 0); + + while (port_index != 0) { + ec_slave_t *next = slave->ports[port_index].next_slave; + + if (next) { + dc_slave = ec_slave_find_next_dc_slave(next); + + if (dc_slave) { + break; + } + } + port_index = ec_slave_get_next_port(slave, port_index); + } + } + + return dc_slave; +} + +/****************************************************************************/ + +/** Calculates the port transmission delays. + */ +void ec_slave_calc_port_delays( + ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + unsigned int port_index; + ec_slave_t *next_slave, *next_dc; + uint32_t rtt, next_rtt_sum; + + if (!slave->base_dc_supported) + return; + + port_index = ec_slave_get_next_port(slave, 0); + + while (port_index != 0) { + next_slave = slave->ports[port_index].next_slave; + next_dc = ec_slave_find_next_dc_slave(next_slave); + + if (next_dc) { + unsigned int prev_port = + ec_slave_get_previous_port(slave, port_index); + + rtt = slave->ports[port_index].receive_time - + slave->ports[prev_port].receive_time; + next_rtt_sum = ec_slave_calc_rtt_sum(next_dc); + + slave->ports[port_index].delay_to_next_dc = + (rtt - next_rtt_sum) / 2; // FIXME + next_dc->ports[0].delay_to_next_dc = + (rtt - next_rtt_sum) / 2; + +#if 0 + EC_SLAVE_DBG(slave, 1, "delay %u:%u rtt=%u" + " next_rtt_sum=%u delay=%u\n", + slave->ring_position, port_index, rtt, next_rtt_sum, + slave->ports[port_index].delay_to_next_dc); +#endif + } + + port_index = ec_slave_get_next_port(slave, port_index); + } +} + +/****************************************************************************/ + +/** Recursively calculates transmission delays. + */ +void ec_slave_calc_transmission_delays_rec( + ec_slave_t *slave, /**< Current slave. */ + uint32_t *delay /**< Sum of delays. */ + ) +{ + unsigned int i; + ec_slave_t *next_dc; + + EC_SLAVE_DBG(slave, 1, "%s(delay = %u ns)\n", __func__, *delay); + + slave->transmission_delay = *delay; + + i = ec_slave_get_next_port(slave, 0); + + while (i != 0) { + ec_slave_port_t *port = &slave->ports[i]; + next_dc = ec_slave_find_next_dc_slave(port->next_slave); + if (next_dc) { + *delay = *delay + port->delay_to_next_dc; +#if 0 + EC_SLAVE_DBG(slave, 1, "%u:%u %u\n", + slave->ring_position, i, *delay); +#endif + ec_slave_calc_transmission_delays_rec(next_dc, delay); + } + + i = ec_slave_get_next_port(slave, i); + } + + *delay = *delay + slave->ports[0].delay_to_next_dc; +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/slave.h b/ubuntu/igh-ecat/master/slave.h new file mode 100644 index 00000000000000..4e113e288e1a68 --- /dev/null +++ b/ubuntu/igh-ecat/master/slave.h @@ -0,0 +1,266 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SLAVE_H__ +#define __EC_SLAVE_H__ + +#include +#include + +#include "globals.h" +#include "datagram.h" +#include "pdo.h" +#include "sync.h" +#include "sdo.h" +#include "fsm_slave.h" + +/****************************************************************************/ + +/** Convenience macro for printing slave-specific information to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT -: ", where INDEX is the master index and + * POSITION is the slave's ring position. + * + * \param slave EtherCAT slave + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_SLAVE_INFO(slave, fmt, args...) \ + printk(KERN_INFO "EtherCAT %u-%u: " fmt, slave->master->index, \ + slave->ring_position, ##args) + +/** Convenience macro for printing slave-specific errors to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT -: ", where INDEX is the master index and + * POSITION is the slave's ring position. + * + * \param slave EtherCAT slave + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_SLAVE_ERR(slave, fmt, args...) \ + printk(KERN_ERR "EtherCAT ERROR %u-%u: " fmt, slave->master->index, \ + slave->ring_position, ##args) + +/** Convenience macro for printing slave-specific warnings to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT -: ", where INDEX is the master index and + * POSITION is the slave's ring position. + * + * \param slave EtherCAT slave + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_SLAVE_WARN(slave, fmt, args...) \ + printk(KERN_WARNING "EtherCAT WARNING %u-%u: " fmt, \ + slave->master->index, slave->ring_position, ##args) + +/** Convenience macro for printing slave-specific debug messages to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT -: ", where INDEX is the master index and + * POSITION is the slave's ring position. + * + * \param slave EtherCAT slave + * \param level Debug level. Master's debug level must be >= \a level for + * output. + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_SLAVE_DBG(slave, level, fmt, args...) \ + do { \ + if (slave->master->debug_level >= level) { \ + printk(KERN_DEBUG "EtherCAT DEBUG %u-%u: " fmt, \ + slave->master->index, slave->ring_position, ##args); \ + } \ + } while (0) + +/****************************************************************************/ + +/** Slave port. + */ +typedef struct { + ec_slave_port_desc_t desc; /**< Port descriptors. */ + ec_slave_port_link_t link; /**< Port link status. */ + ec_slave_t *next_slave; /**< Connected slaves. */ + uint32_t receive_time; /**< Port receive times for delay + measurement. */ + uint32_t delay_to_next_dc; /**< Delay to next slave with DC support behind + this port [ns]. */ +} ec_slave_port_t; + +/****************************************************************************/ + +/** Slave information interface data. + */ +typedef struct { + // Non-category data + uint16_t alias; /**< Configured station alias. */ + uint32_t vendor_id; /**< Vendor ID. */ + uint32_t product_code; /**< Vendor-specific product code. */ + uint32_t revision_number; /**< Revision number. */ + uint32_t serial_number; /**< Serial number. */ + uint16_t boot_rx_mailbox_offset; /**< Bootstrap receive mailbox address. */ + uint16_t boot_rx_mailbox_size; /**< Bootstrap receive mailbox size. */ + uint16_t boot_tx_mailbox_offset; /**< Bootstrap transmit mailbox address. */ + uint16_t boot_tx_mailbox_size; /**< Bootstrap transmit mailbox size. */ + uint16_t std_rx_mailbox_offset; /**< Standard receive mailbox address. */ + uint16_t std_rx_mailbox_size; /**< Standard receive mailbox size. */ + uint16_t std_tx_mailbox_offset; /**< Standard transmit mailbox address. */ + uint16_t std_tx_mailbox_size; /**< Standard transmit mailbox size. */ + uint16_t mailbox_protocols; /**< Supported mailbox protocols. */ + + // Strings + char **strings; /**< Strings in SII categories. */ + unsigned int string_count; /**< Number of SII strings. */ + + // General + unsigned int has_general; /**< General category present. */ + char *group; /**< Group name. */ + char *image; /**< Image name. */ + char *order; /**< Order number. */ + char *name; /**< Slave name. */ + uint8_t physical_layer[EC_MAX_PORTS]; /**< Port media. */ + ec_sii_coe_details_t coe_details; /**< CoE detail flags. */ + ec_sii_general_flags_t general_flags; /**< General flags. */ + int16_t current_on_ebus; /**< Power consumption in mA. */ + + // SyncM + ec_sync_t *syncs; /**< SYNC MANAGER categories. */ + unsigned int sync_count; /**< Number of sync managers. */ + + // [RT]XPDO + struct list_head pdos; /**< SII [RT]XPDO categories. */ +} ec_sii_t; + +/****************************************************************************/ + +/** EtherCAT slave. + */ +struct ec_slave +{ + ec_master_t *master; /**< Master owning the slave. */ + ec_device_index_t device_index; /**< Index of device the slave responds + on. */ + + // addresses + uint16_t ring_position; /**< Ring position. */ + uint16_t station_address; /**< Configured station address. */ + uint16_t effective_alias; /**< Effective alias address. */ + + ec_slave_port_t ports[EC_MAX_PORTS]; /**< Ports. */ + + // configuration + ec_slave_config_t *config; /**< Current configuration. */ + ec_slave_state_t requested_state; /**< Requested application state. */ + ec_slave_state_t current_state; /**< Current application state. */ + unsigned int error_flag; /**< Stop processing after an error. */ + unsigned int force_config; /**< Force (re-)configuration. */ + uint16_t configured_rx_mailbox_offset; /**< Configured receive mailbox + offset. */ + uint16_t configured_rx_mailbox_size; /**< Configured receive mailbox size. + */ + uint16_t configured_tx_mailbox_offset; /**< Configured send mailbox + offset. */ + uint16_t configured_tx_mailbox_size; /**< Configured send mailbox size. */ + + // base data + uint8_t base_type; /**< Slave type. */ + uint8_t base_revision; /**< Revision. */ + uint16_t base_build; /**< Build number. */ + uint8_t base_fmmu_count; /**< Number of supported FMMUs. */ + uint8_t base_sync_count; /**< Number of supported sync managers. */ + uint8_t base_fmmu_bit_operation; /**< FMMU bit operation is supported. */ + uint8_t base_dc_supported; /**< Distributed clocks are supported. */ + ec_slave_dc_range_t base_dc_range; /**< DC range. */ + uint8_t has_dc_system_time; /**< The slave supports the DC system time + register. Otherwise it can only be used for + delay measurement. */ + uint32_t transmission_delay; /**< DC system time transmission delay + (offset from reference clock). */ + + // SII + uint16_t *sii_words; /**< Complete SII image. */ + size_t sii_nwords; /**< Size of the SII contents in words. */ + + // Slave information interface + ec_sii_t sii; /**< Extracted SII data. */ + + struct list_head sdo_dictionary; /**< SDO dictionary list */ + uint8_t sdo_dictionary_fetched; /**< Dictionary has been fetched. */ + unsigned long jiffies_preop; /**< Time, the slave went to PREOP. */ + + struct list_head sdo_requests; /**< SDO access requests. */ + struct list_head reg_requests; /**< Register access requests. */ + struct list_head foe_requests; /**< FoE requests. */ + struct list_head soe_requests; /**< SoE requests. */ + struct list_head eoe_requests; /**< EoE set IP parameter requests. */ + + ec_fsm_slave_t fsm; /**< Slave state machine. */ +}; + +/****************************************************************************/ + +// slave construction/destruction +void ec_slave_init(ec_slave_t *, ec_master_t *, ec_device_index_t, + uint16_t, uint16_t); +void ec_slave_clear(ec_slave_t *); + +void ec_slave_clear_sync_managers(ec_slave_t *); + +void ec_slave_request_state(ec_slave_t *, ec_slave_state_t); +void ec_slave_set_state(ec_slave_t *, ec_slave_state_t); + +// SII categories +int ec_slave_fetch_sii_strings(ec_slave_t *, const uint8_t *, size_t); +int ec_slave_fetch_sii_general(ec_slave_t *, const uint8_t *, size_t); +int ec_slave_fetch_sii_syncs(ec_slave_t *, const uint8_t *, size_t); +int ec_slave_fetch_sii_pdos(ec_slave_t *, const uint8_t *, size_t, + ec_direction_t); + +// misc. +ec_sync_t *ec_slave_get_sync(ec_slave_t *, uint8_t); + +void ec_slave_sdo_dict_info(const ec_slave_t *, + unsigned int *, unsigned int *); +ec_sdo_t *ec_slave_get_sdo(ec_slave_t *, uint16_t); +const ec_sdo_t *ec_slave_get_sdo_const(const ec_slave_t *, uint16_t); +const ec_sdo_t *ec_slave_get_sdo_by_pos_const(const ec_slave_t *, uint16_t); +uint16_t ec_slave_sdo_count(const ec_slave_t *); +const ec_pdo_t *ec_slave_find_pdo(const ec_slave_t *, uint16_t); +void ec_slave_attach_pdo_names(ec_slave_t *); + +void ec_slave_calc_port_delays(ec_slave_t *); +void ec_slave_calc_transmission_delays_rec(ec_slave_t *, uint32_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/slave_config.c b/ubuntu/igh-ecat/master/slave_config.c new file mode 100644 index 00000000000000..073bb7f03d679c --- /dev/null +++ b/ubuntu/igh-ecat/master/slave_config.c @@ -0,0 +1,1652 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * vim: expandtab + * + ****************************************************************************/ + +/** + \file + EtherCAT slave configuration methods. +*/ + +/****************************************************************************/ + +#include "slave_config.h" + +#include "globals.h" +#include "master.h" +#include "voe_handler.h" +#include "flag.h" +#include "ioctl.h" + +#ifdef EC_EOE +#include "eoe_request.h" +#endif + +#include +#include + +/****************************************************************************/ + +// prototypes for private methods +int ec_slave_config_prepare_fmmu(ec_slave_config_t *, ec_domain_t *, uint8_t, + ec_direction_t); +void ec_slave_config_load_default_mapping(const ec_slave_config_t *, + ec_pdo_t *); + +/****************************************************************************/ + +/** EtherCAT application-layer transition timeout. + */ +typedef struct { + struct list_head list; + ec_slave_state_t from; + ec_slave_state_t to; + unsigned int timeout_ms; +} ec_al_timeout_t; + +/****************************************************************************/ + +/** Slave configuration constructor. + * + * See ecrt_master_slave_config() for the usage of the \a alias and \a + * position parameters. + */ +void ec_slave_config_init( + ec_slave_config_t *sc, /**< Slave configuration. */ + ec_master_t *master, /**< EtherCAT master. */ + uint16_t alias, /**< Slave alias. */ + uint16_t position, /**< Slave position. */ + uint32_t vendor_id, /**< Expected vendor ID. */ + uint32_t product_code /**< Expected product code. */ + ) +{ + unsigned int i; + + sc->master = master; + + sc->alias = alias; + sc->position = position; + sc->vendor_id = vendor_id; + sc->product_code = product_code; + sc->watchdog_divider = 0; // use default + sc->watchdog_intervals = 0; // use default + + sc->slave = NULL; + + for (i = 0; i < EC_MAX_SYNC_MANAGERS; i++) + ec_sync_config_init(&sc->sync_configs[i]); + + sc->used_fmmus = 0; + sc->dc_assign_activate = 0x0000; + sc->dc_sync[0].cycle_time = 0U; + sc->dc_sync[1].cycle_time = 0; + sc->dc_sync[0].shift_time = 0U; + sc->dc_sync[1].shift_time = 0; + + INIT_LIST_HEAD(&sc->sdo_configs); + INIT_LIST_HEAD(&sc->sdo_requests); + INIT_LIST_HEAD(&sc->soe_requests); + INIT_LIST_HEAD(&sc->reg_requests); + INIT_LIST_HEAD(&sc->voe_handlers); + INIT_LIST_HEAD(&sc->soe_configs); + INIT_LIST_HEAD(&sc->flags); + INIT_LIST_HEAD(&sc->al_timeouts); + +#ifdef EC_EOE + ec_eoe_request_init(&sc->eoe_ip_param_request); +#endif + + ec_coe_emerg_ring_init(&sc->emerg_ring, sc); +} + +/****************************************************************************/ + +/** Slave configuration destructor. + * + * Clears and frees a slave configuration object. + */ +void ec_slave_config_clear( + ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + unsigned int i; + ec_sdo_request_t *req, *next_req; + ec_voe_handler_t *voe, *next_voe; + ec_reg_request_t *reg, *next_reg; + ec_soe_request_t *soe, *next_soe; + ec_flag_t *flag, *next_flag; + ec_al_timeout_t *timeout, *next_timeout; + + ec_slave_config_detach(sc); + + // Free sync managers + for (i = 0; i < EC_MAX_SYNC_MANAGERS; i++) + ec_sync_config_clear(&sc->sync_configs[i]); + + // free all SDO configurations + list_for_each_entry_safe(req, next_req, &sc->sdo_configs, list) { + list_del(&req->list); + ec_sdo_request_clear(req); + kfree(req); + } + + // free all SDO requests + list_for_each_entry_safe(req, next_req, &sc->sdo_requests, list) { + list_del(&req->list); + ec_sdo_request_clear(req); + kfree(req); + } + + // free all SoE requests + list_for_each_entry_safe(soe, next_soe, &sc->soe_requests, list) { + list_del(&soe->list); + ec_soe_request_clear(soe); + kfree(soe); + } + + // free all register requests + list_for_each_entry_safe(reg, next_reg, &sc->reg_requests, list) { + list_del(®->list); + ec_reg_request_clear(reg); + kfree(reg); + } + + // free all VoE handlers + list_for_each_entry_safe(voe, next_voe, &sc->voe_handlers, list) { + list_del(&voe->list); + ec_voe_handler_clear(voe); + kfree(voe); + } + + // free all SoE configurations + list_for_each_entry_safe(soe, next_soe, &sc->soe_configs, list) { + list_del(&soe->list); + ec_soe_request_clear(soe); + kfree(soe); + } + + // free all flags + list_for_each_entry_safe(flag, next_flag, &sc->flags, list) { + list_del(&flag->list); + ec_flag_clear(flag); + kfree(flag); + } + + // free all AL timeouts + list_for_each_entry_safe(timeout, next_timeout, &sc->al_timeouts, list) { + list_del(&timeout->list); + kfree(timeout); + } + + ec_coe_emerg_ring_clear(&sc->emerg_ring); +} + +/****************************************************************************/ + +/** Prepares an FMMU configuration. + * + * Configuration data for the FMMU is saved in the slave config structure and + * is written to the slave during the configuration. The FMMU configuration + * is done in a way, that the complete data range of the corresponding sync + * manager is covered. Seperate FMMUs are configured for each domain. If the + * FMMU configuration is already prepared, the function does nothing and + * returns with success. + * + * \retval >=0 Success, logical offset byte address. + * \retval <0 Error code. + */ +int ec_slave_config_prepare_fmmu( + ec_slave_config_t *sc, /**< Slave configuration. */ + ec_domain_t *domain, /**< Domain. */ + uint8_t sync_index, /**< Sync manager index. */ + ec_direction_t dir /**< PDO direction. */ + ) +{ + unsigned int i; + ec_fmmu_config_t *fmmu; + + // FMMU configuration already prepared? + for (i = 0; i < sc->used_fmmus; i++) { + fmmu = &sc->fmmu_configs[i]; + if (fmmu->domain == domain && fmmu->sync_index == sync_index) + return fmmu->logical_start_address; + } + + if (sc->used_fmmus == EC_MAX_FMMUS) { + EC_CONFIG_ERR(sc, "FMMU limit reached!\n"); + return -EOVERFLOW; + } + + fmmu = &sc->fmmu_configs[sc->used_fmmus++]; + + down(&sc->master->master_sem); + ec_fmmu_config_init(fmmu, sc, domain, sync_index, dir); + up(&sc->master->master_sem); + + return fmmu->logical_start_address; +} + +/****************************************************************************/ + +/** Attaches the configuration to the addressed slave object. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_slave_config_attach( + ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + ec_slave_t *slave; + + if (sc->slave) + return 0; // already attached + + if (!(slave = ec_master_find_slave( + sc->master, sc->alias, sc->position))) { + EC_CONFIG_DBG(sc, 1, "Failed to find slave for configuration.\n"); + return -ENOENT; + } + + if (slave->config) { + EC_CONFIG_DBG(sc, 1, "Failed to attach configuration. Slave %u" + " already has a configuration!\n", slave->ring_position); + return -EEXIST; + } + + if ( +#ifdef EC_IDENT_WILDCARDS + sc->vendor_id != 0xffffffff && +#endif + slave->sii.vendor_id != sc->vendor_id + ) { + EC_CONFIG_DBG(sc, 1, "Slave %u has no matching vendor ID (0x%08X)" + " for configuration (0x%08X).\n", + slave->ring_position, slave->sii.vendor_id, sc->vendor_id); + return -EINVAL; + } + + if ( +#ifdef EC_IDENT_WILDCARDS + sc->product_code != 0xffffffff && +#endif + slave->sii.product_code != sc->product_code + ) { + EC_CONFIG_DBG(sc, 1, "Slave %u has no matching product code (0x%08X)" + " for configuration (0x%08X).\n", + slave->ring_position, slave->sii.product_code, + sc->product_code); + return -EINVAL; + } + + // attach slave + slave->config = sc; + sc->slave = slave; + + EC_CONFIG_DBG(sc, 1, "Attached slave %u.\n", slave->ring_position); + return 0; +} + +/****************************************************************************/ + +/** Detaches the configuration from a slave object. + */ +void ec_slave_config_detach( + ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + if (sc->slave) { + ec_reg_request_t *reg; + + sc->slave->config = NULL; + + // invalidate processing register request + list_for_each_entry(reg, &sc->reg_requests, list) { + if (sc->slave->fsm.reg_request == reg) { + sc->slave->fsm.reg_request = NULL; + break; + } + } + + sc->slave = NULL; + } +} + +/****************************************************************************/ + +/** Loads the default PDO assignment from the slave object. + */ +void ec_slave_config_load_default_sync_config(ec_slave_config_t *sc) +{ + uint8_t sync_index; + ec_sync_config_t *sync_config; + const ec_sync_t *sync; + + if (!sc->slave) + return; + + for (sync_index = 0; sync_index < EC_MAX_SYNC_MANAGERS; sync_index++) { + sync_config = &sc->sync_configs[sync_index]; + if ((sync = ec_slave_get_sync(sc->slave, sync_index))) { + sync_config->dir = ec_sync_default_direction(sync); + if (sync_config->dir == EC_DIR_INVALID) + EC_SLAVE_WARN(sc->slave, + "SM%u has an invalid direction field!\n", sync_index); + ec_pdo_list_copy(&sync_config->pdos, &sync->pdos); + } + } +} + +/****************************************************************************/ + +/** Loads the default mapping for a PDO from the slave object. + */ +void ec_slave_config_load_default_mapping( + const ec_slave_config_t *sc, + ec_pdo_t *pdo + ) +{ + unsigned int i; + const ec_sync_t *sync; + const ec_pdo_t *default_pdo; + + if (!sc->slave) + return; + + EC_CONFIG_DBG(sc, 1, "Loading default mapping for PDO 0x%04X.\n", + pdo->index); + + // find PDO in any sync manager (it could be reassigned later) + for (i = 0; i < sc->slave->sii.sync_count; i++) { + sync = &sc->slave->sii.syncs[i]; + + list_for_each_entry(default_pdo, &sync->pdos.list, list) { + if (default_pdo->index != pdo->index) + continue; + + if (default_pdo->name) { + EC_CONFIG_DBG(sc, 1, "Found PDO name \"%s\".\n", + default_pdo->name); + + // take PDO name from assigned one + ec_pdo_set_name(pdo, default_pdo->name); + } + + // copy entries (= default PDO mapping) + if (ec_pdo_copy_entries(pdo, default_pdo)) + return; + + if (sc->master->debug_level) { + const ec_pdo_entry_t *entry; + list_for_each_entry(entry, &pdo->entries, list) { + EC_CONFIG_DBG(sc, 1, "Entry 0x%04X:%02X.\n", + entry->index, entry->subindex); + } + } + + return; + } + } + + EC_CONFIG_DBG(sc, 1, "No default mapping found.\n"); +} + +/****************************************************************************/ + +/** Get the number of SDO configurations. + * + * \return Number of SDO configurations. + */ +unsigned int ec_slave_config_sdo_count( + const ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + const ec_sdo_request_t *req; + unsigned int count = 0; + + list_for_each_entry(req, &sc->sdo_configs, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Finds an SDO configuration via its position in the list. + * + * Const version. + * + * \return Search result, or NULL. + */ +const ec_sdo_request_t *ec_slave_config_get_sdo_by_pos_const( + const ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + const ec_sdo_request_t *req; + + list_for_each_entry(req, &sc->sdo_configs, list) { + if (pos--) + continue; + return req; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get the number of IDN configurations. + * + * \return Number of SDO configurations. + */ +unsigned int ec_slave_config_idn_count( + const ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + const ec_soe_request_t *req; + unsigned int count = 0; + + list_for_each_entry(req, &sc->soe_configs, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Finds an IDN configuration via its position in the list. + * + * Const version. + * + * \return Search result, or NULL. + */ +const ec_soe_request_t *ec_slave_config_get_idn_by_pos_const( + const ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + const ec_soe_request_t *req; + + list_for_each_entry(req, &sc->soe_configs, list) { + if (pos--) + continue; + return req; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get the number of feature flags. + * + * \return Number of feature flags. + */ +unsigned int ec_slave_config_flag_count( + const ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + const ec_flag_t *flag; + unsigned int count = 0; + + list_for_each_entry(flag, &sc->flags, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Finds a flag via its position in the list. + * + * Const version. + * + * \return Search result, or NULL. + */ +const ec_flag_t *ec_slave_config_get_flag_by_pos_const( + const ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + const ec_flag_t *flag; + + list_for_each_entry(flag, &sc->flags, list) { + if (pos--) + continue; + return flag; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a CoE SDO request via its position in the list. + * + * \return Search result, or NULL. + */ +ec_sdo_request_t *ec_slave_config_find_sdo_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + ec_sdo_request_t *req; + + list_for_each_entry(req, &sc->sdo_requests, list) { + if (pos--) + continue; + return req; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a SoE request via its position in the list. + * + * \return Search result, or NULL. + */ +ec_soe_request_t *ec_slave_config_find_soe_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + ec_soe_request_t *req; + + list_for_each_entry(req, &sc->soe_requests, list) { + if (pos--) + continue; + return req; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a register handler via its position in the list. + * + * \return Search result, or NULL. + */ +ec_reg_request_t *ec_slave_config_find_reg_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + ec_reg_request_t *reg; + + list_for_each_entry(reg, &sc->reg_requests, list) { + if (pos--) + continue; + return reg; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a VoE handler via its position in the list. + * + * \return Search result, or NULL. + */ +ec_voe_handler_t *ec_slave_config_find_voe_handler( + ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + ec_voe_handler_t *voe; + + list_for_each_entry(voe, &sc->voe_handlers, list) { + if (pos--) + continue; + return voe; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a flag. + * + * \return Search result, or NULL. + */ +ec_flag_t *ec_slave_config_find_flag( + ec_slave_config_t *sc, /**< Slave configuration. */ + const char *key /**< Flag key. */ + ) +{ + if (sc) { + ec_flag_t *flag; + list_for_each_entry(flag, &sc->flags, list) { + if (!strcmp(flag->key, key)) { + return flag; + } + } + } + + return NULL; +} + +/****************************************************************************/ + +/** Return an AL state timeout. + * + * \return Search result, or 0. + */ +unsigned int ec_slave_config_al_timeout(const ec_slave_config_t *sc, + ec_slave_state_t from, ec_slave_state_t to) +{ + ec_al_timeout_t *timeout; + + list_for_each_entry(timeout, &sc->al_timeouts, list) { + if (timeout->from == from && timeout->to == to) { + return timeout->timeout_ms; + } + } + + return 0; +} + +/***************************************************************************** + * Application interface + ****************************************************************************/ + +int ecrt_slave_config_sync_manager(ec_slave_config_t *sc, uint8_t sync_index, + ec_direction_t dir, ec_watchdog_mode_t watchdog_mode) +{ + ec_sync_config_t *sync_config; + + EC_CONFIG_DBG(sc, 1, "ecrt_slave_config_sync_manager(sc = 0x%p," + " sync_index = %u, dir = %i, watchdog_mode = %i)\n", + sc, sync_index, dir, watchdog_mode); + + if (sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_CONFIG_ERR(sc, "Invalid sync manager index %u!\n", sync_index); + return -ENOENT; + } + + if (dir != EC_DIR_OUTPUT && dir != EC_DIR_INPUT) { + EC_CONFIG_ERR(sc, "Invalid direction %u!\n", (unsigned int) dir); + return -EINVAL; + } + + sync_config = &sc->sync_configs[sync_index]; + sync_config->dir = dir; + sync_config->watchdog_mode = watchdog_mode; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_watchdog(ec_slave_config_t *sc, + uint16_t divider, uint16_t intervals) +{ + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, divider = %u, intervals = %u)\n", + __func__, sc, divider, intervals); + + sc->watchdog_divider = divider; + sc->watchdog_intervals = intervals; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_pdo_assign_add(ec_slave_config_t *sc, + uint8_t sync_index, uint16_t pdo_index) +{ + ec_pdo_t *pdo; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, sync_index = %u, " + "pdo_index = 0x%04X)\n", __func__, sc, sync_index, pdo_index); + + if (sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_CONFIG_ERR(sc, "Invalid sync manager index %u!\n", sync_index); + return -EINVAL; + } + + down(&sc->master->master_sem); + + pdo = ec_pdo_list_add_pdo(&sc->sync_configs[sync_index].pdos, pdo_index); + if (IS_ERR(pdo)) { + up(&sc->master->master_sem); + return PTR_ERR(pdo); + } + pdo->sync_index = sync_index; + + ec_slave_config_load_default_mapping(sc, pdo); + + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_pdo_assign_clear(ec_slave_config_t *sc, + uint8_t sync_index) +{ + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, sync_index = %u)\n", + __func__, sc, sync_index); + + if (sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_CONFIG_ERR(sc, "Invalid sync manager index %u!\n", sync_index); + return -EINVAL; + } + + down(&sc->master->master_sem); + ec_pdo_list_clear_pdos(&sc->sync_configs[sync_index].pdos); + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_pdo_mapping_add(ec_slave_config_t *sc, + uint16_t pdo_index, uint16_t entry_index, uint8_t entry_subindex, + uint8_t entry_bit_length) +{ + uint8_t sync_index; + ec_pdo_t *pdo = NULL; + ec_pdo_entry_t *entry; + int retval = 0; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, " + "pdo_index = 0x%04X, entry_index = 0x%04X, " + "entry_subindex = 0x%02X, entry_bit_length = %u)\n", + __func__, sc, pdo_index, entry_index, entry_subindex, + entry_bit_length); + + for (sync_index = 0; sync_index < EC_MAX_SYNC_MANAGERS; sync_index++) + if ((pdo = ec_pdo_list_find_pdo( + &sc->sync_configs[sync_index].pdos, pdo_index))) + break; + + if (pdo) { + down(&sc->master->master_sem); + entry = ec_pdo_add_entry(pdo, entry_index, entry_subindex, + entry_bit_length); + up(&sc->master->master_sem); + if (IS_ERR(entry)) + retval = PTR_ERR(entry); + } else { + EC_CONFIG_ERR(sc, "PDO 0x%04X is not assigned.\n", pdo_index); + retval = -ENOENT; + } + + return retval; +} + +/****************************************************************************/ + +int ecrt_slave_config_pdo_mapping_clear(ec_slave_config_t *sc, + uint16_t pdo_index) +{ + uint8_t sync_index; + ec_pdo_t *pdo = NULL; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, pdo_index = 0x%04X)\n", + __func__, sc, pdo_index); + + for (sync_index = 0; sync_index < EC_MAX_SYNC_MANAGERS; sync_index++) + if ((pdo = ec_pdo_list_find_pdo( + &sc->sync_configs[sync_index].pdos, pdo_index))) + break; + + if (pdo) { + down(&sc->master->master_sem); + ec_pdo_clear_entries(pdo); + up(&sc->master->master_sem); + } else { + EC_CONFIG_WARN(sc, "PDO 0x%04X is not assigned.\n", pdo_index); + } + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_pdos(ec_slave_config_t *sc, + unsigned int n_syncs, const ec_sync_info_t syncs[]) +{ + int ret; + unsigned int i, j, k; + const ec_sync_info_t *sync_info; + const ec_pdo_info_t *pdo_info; + const ec_pdo_entry_info_t *entry_info; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, n_syncs = %u, syncs = 0x%p)\n", + __func__, sc, n_syncs, syncs); + + if (!syncs) + return 0; + + for (i = 0; i < n_syncs; i++) { + sync_info = &syncs[i]; + + if (sync_info->index == (uint8_t) EC_END) + break; + + if (sync_info->index >= EC_MAX_SYNC_MANAGERS) { + EC_CONFIG_ERR(sc, "Invalid sync manager index %u!\n", + sync_info->index); + return -ENOENT; + } + + ret = ecrt_slave_config_sync_manager(sc, sync_info->index, + sync_info->dir, sync_info->watchdog_mode); + if (ret) + return ret; + + ecrt_slave_config_pdo_assign_clear(sc, sync_info->index); + + if (sync_info->n_pdos && sync_info->pdos) { + + for (j = 0; j < sync_info->n_pdos; j++) { + pdo_info = &sync_info->pdos[j]; + + ret = ecrt_slave_config_pdo_assign_add( + sc, sync_info->index, pdo_info->index); + if (ret) + return ret; + + ecrt_slave_config_pdo_mapping_clear(sc, pdo_info->index); + + if (pdo_info->n_entries && pdo_info->entries) { + for (k = 0; k < pdo_info->n_entries; k++) { + entry_info = &pdo_info->entries[k]; + + ret = ecrt_slave_config_pdo_mapping_add(sc, + pdo_info->index, entry_info->index, + entry_info->subindex, + entry_info->bit_length); + if (ret) + return ret; + } + } + } + } + } + + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_reg_pdo_entry( + ec_slave_config_t *sc, + uint16_t index, + uint8_t subindex, + ec_domain_t *domain, + unsigned int *bit_position + ) +{ + uint8_t sync_index; + const ec_sync_config_t *sync_config; + unsigned int bit_offset, bit_pos; + ec_pdo_t *pdo; + ec_pdo_entry_t *entry; + int sync_offset; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "subindex = 0x%02X, domain = 0x%p, bit_position = 0x%p)\n", + __func__, sc, index, subindex, domain, bit_position); + + for (sync_index = 0; sync_index < EC_MAX_SYNC_MANAGERS; sync_index++) { + sync_config = &sc->sync_configs[sync_index]; + bit_offset = 0; + + list_for_each_entry(pdo, &sync_config->pdos.list, list) { + list_for_each_entry(entry, &pdo->entries, list) { + if (entry->index != index || entry->subindex != subindex) { + bit_offset += entry->bit_length; + } else { + bit_pos = bit_offset % 8; + if (bit_position) { + *bit_position = bit_pos; + } else if (bit_pos) { + EC_CONFIG_ERR(sc, "PDO entry 0x%04X:%02X does" + " not byte-align.\n", index, subindex); + return -EFAULT; + } + + sync_offset = ec_slave_config_prepare_fmmu( + sc, domain, sync_index, sync_config->dir); + if (sync_offset < 0) + return sync_offset; + + return sync_offset + bit_offset / 8; + } + } + } + } + + EC_CONFIG_ERR(sc, "PDO entry 0x%04X:%02X is not mapped.\n", + index, subindex); + return -ENOENT; +} + +/****************************************************************************/ + +int ecrt_slave_config_reg_pdo_entry_pos( + ec_slave_config_t *sc, + uint8_t sync_index, + unsigned int pdo_pos, + unsigned int entry_pos, + ec_domain_t *domain, + unsigned int *bit_position + ) +{ + const ec_sync_config_t *sync_config; + unsigned int bit_offset, pp, ep; + ec_pdo_t *pdo; + ec_pdo_entry_t *entry; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, sync_index = %u, pdo_pos = %u," + " entry_pos = %u, domain = 0x%p, bit_position = 0x%p)\n", + __func__, sc, sync_index, pdo_pos, entry_pos, + domain, bit_position); + + if (sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_CONFIG_ERR(sc, "Invalid syncmanager position %u.\n", sync_index); + return -EINVAL; + } + + sync_config = &sc->sync_configs[sync_index]; + bit_offset = 0; + pp = 0; + + list_for_each_entry(pdo, &sync_config->pdos.list, list) { + ep = 0; + list_for_each_entry(entry, &pdo->entries, list) { + if (pp != pdo_pos || ep != entry_pos) { + bit_offset += entry->bit_length; + } else { + unsigned int bit_pos = bit_offset % 8; + int sync_offset; + + if (bit_position) { + *bit_position = bit_pos; + } else if (bit_pos) { + EC_CONFIG_ERR(sc, "PDO entry 0x%04X:%02X does" + " not byte-align.\n", + pdo->index, entry->subindex); + return -EFAULT; + } + + sync_offset = ec_slave_config_prepare_fmmu( + sc, domain, sync_index, sync_config->dir); + if (sync_offset < 0) + return sync_offset; + + return sync_offset + bit_offset / 8; + } + ep++; + } + pp++; + } + + EC_CONFIG_ERR(sc, "PDO entry specification %u/%u/%u out of range.\n", + sync_index, pdo_pos, entry_pos); + return -ENOENT; +} + +/****************************************************************************/ + +int ecrt_slave_config_dc(ec_slave_config_t *sc, uint16_t assign_activate, + uint32_t sync0_cycle_time, int32_t sync0_shift_time, + uint32_t sync1_cycle_time, int32_t sync1_shift_time) +{ + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, assign_activate = 0x%04X," + " sync0_cycle = %u, sync0_shift = %i," + " sync1_cycle = %u, sync1_shift = %i\n", + __func__, sc, assign_activate, sync0_cycle_time, sync0_shift_time, + sync1_cycle_time, sync1_shift_time); + + sc->dc_assign_activate = assign_activate; + sc->dc_sync[0].cycle_time = sync0_cycle_time; + sc->dc_sync[0].shift_time = sync0_shift_time; + sc->dc_sync[1].cycle_time = sync1_cycle_time; + sc->dc_sync[1].shift_time = sync1_shift_time; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_sdo(ec_slave_config_t *sc, uint16_t index, + uint8_t subindex, const uint8_t *data, size_t size) +{ + ec_slave_t *slave = sc->slave; + ec_sdo_request_t *req; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "subindex = 0x%02X, data = 0x%p, size = %zu)\n", + __func__, sc, index, subindex, data, size); + + if (slave && !(slave->sii.mailbox_protocols & EC_MBOX_COE)) { + EC_CONFIG_WARN(sc, "Attached slave does not support CoE!\n"); + } + + if (!(req = (ec_sdo_request_t *) + kmalloc(sizeof(ec_sdo_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate memory for" + " SDO configuration!\n"); + return -ENOMEM; + } + + ec_sdo_request_init(req); + ecrt_sdo_request_index(req, index, subindex); + + ret = ec_sdo_request_copy_data(req, data, size); + if (ret < 0) { + ec_sdo_request_clear(req); + kfree(req); + return ret; + } + + down(&sc->master->master_sem); + list_add_tail(&req->list, &sc->sdo_configs); + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_sdo8(ec_slave_config_t *sc, uint16_t index, + uint8_t subindex, uint8_t value) +{ + uint8_t data[1]; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "subindex = 0x%02X, value = %u)\n", + __func__, sc, index, subindex, (unsigned int) value); + + EC_WRITE_U8(data, value); + return ecrt_slave_config_sdo(sc, index, subindex, data, 1); +} + +/****************************************************************************/ + +int ecrt_slave_config_sdo16(ec_slave_config_t *sc, uint16_t index, + uint8_t subindex, uint16_t value) +{ + uint8_t data[2]; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "subindex = 0x%02X, value = %u)\n", + __func__, sc, index, subindex, value); + + EC_WRITE_U16(data, value); + return ecrt_slave_config_sdo(sc, index, subindex, data, 2); +} + +/****************************************************************************/ + +int ecrt_slave_config_sdo32(ec_slave_config_t *sc, uint16_t index, + uint8_t subindex, uint32_t value) +{ + uint8_t data[4]; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "subindex = 0x%02X, value = %u)\n", + __func__, sc, index, subindex, value); + + EC_WRITE_U32(data, value); + return ecrt_slave_config_sdo(sc, index, subindex, data, 4); +} + +/****************************************************************************/ + +int ecrt_slave_config_complete_sdo(ec_slave_config_t *sc, uint16_t index, + const uint8_t *data, size_t size) +{ + ec_slave_t *slave = sc->slave; + ec_sdo_request_t *req; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "data = 0x%p, size = %zu)\n", __func__, sc, index, data, size); + + if (slave && !(slave->sii.mailbox_protocols & EC_MBOX_COE)) { + EC_CONFIG_WARN(sc, "Attached slave does not support CoE!\n"); + } + + if (!(req = (ec_sdo_request_t *) + kmalloc(sizeof(ec_sdo_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate memory for" + " SDO configuration!\n"); + return -ENOMEM; + } + + ec_sdo_request_init(req); + ecrt_sdo_request_index(req, index, 0); + req->complete_access = 1; + + ret = ec_sdo_request_copy_data(req, data, size); + if (ret < 0) { + ec_sdo_request_clear(req); + kfree(req); + return ret; + } + + down(&sc->master->master_sem); + list_add_tail(&req->list, &sc->sdo_configs); + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_emerg_size(ec_slave_config_t *sc, size_t elements) +{ + return ec_coe_emerg_ring_size(&sc->emerg_ring, elements); +} + +/****************************************************************************/ + +int ecrt_slave_config_emerg_pop(ec_slave_config_t *sc, uint8_t *target) +{ + return ec_coe_emerg_ring_pop(&sc->emerg_ring, target); +} + +/****************************************************************************/ + +int ecrt_slave_config_emerg_clear(ec_slave_config_t *sc) +{ + return ec_coe_emerg_ring_clear_ring(&sc->emerg_ring); +} + +/****************************************************************************/ + +int ecrt_slave_config_emerg_overruns(const ec_slave_config_t *sc) +{ + return ec_coe_emerg_ring_overruns(&sc->emerg_ring); +} + +/****************************************************************************/ + +/** Same as ecrt_slave_config_create_sdo_request(), but with ERR_PTR() return + * value. + */ +ec_sdo_request_t *ecrt_slave_config_create_sdo_request_err( + ec_slave_config_t *sc, uint16_t index, uint8_t subindex, size_t size) +{ + ec_sdo_request_t *req; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, " + "index = 0x%04X, subindex = 0x%02X, size = %zu)\n", + __func__, sc, index, subindex, size); + + if (!(req = (ec_sdo_request_t *) + kmalloc(sizeof(ec_sdo_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate SDO request memory!\n"); + return ERR_PTR(-ENOMEM); + } + + ec_sdo_request_init(req); + ecrt_sdo_request_index(req, index, subindex); + + ret = ec_sdo_request_alloc(req, size); + if (ret < 0) { + ec_sdo_request_clear(req); + kfree(req); + return ERR_PTR(ret); + } + + // prepare data for optional writing + memset(req->data, 0x00, size); + req->data_size = size; + + down(&sc->master->master_sem); + list_add_tail(&req->list, &sc->sdo_requests); + up(&sc->master->master_sem); + + return req; +} + +/****************************************************************************/ + +ec_sdo_request_t *ecrt_slave_config_create_sdo_request( + ec_slave_config_t *sc, uint16_t index, uint8_t subindex, size_t size) +{ + ec_sdo_request_t *s = ecrt_slave_config_create_sdo_request_err(sc, index, + subindex, size); + return IS_ERR(s) ? NULL : s; +} + +/****************************************************************************/ + +/** Same as ecrt_slave_config_create_soe_request(), but with ERR_PTR() return + * value. + */ +ec_soe_request_t *ecrt_slave_config_create_soe_request_err( + ec_slave_config_t *sc, uint8_t drive_no, uint16_t idn, size_t size) +{ + ec_soe_request_t *req; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, " + "drive_no = 0x%02X, idn = 0x%04X, size = %zu)\n", + __func__, sc, drive_no, idn, size); + + if (!(req = (ec_soe_request_t *) + kmalloc(sizeof(ec_soe_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate IDN request memory!\n"); + return ERR_PTR(-ENOMEM); + } + + ec_soe_request_init(req); + ecrt_soe_request_idn(req, drive_no, idn); + + ret = ec_soe_request_alloc(req, size); + if (ret < 0) { + ec_soe_request_clear(req); + kfree(req); + return ERR_PTR(ret); + } + + // prepare data for optional writing + memset(req->data, 0x00, size); + req->data_size = size; + + down(&sc->master->master_sem); + list_add_tail(&req->list, &sc->soe_requests); + up(&sc->master->master_sem); + + return req; +} + +/****************************************************************************/ + +ec_soe_request_t *ecrt_slave_config_create_soe_request( + ec_slave_config_t *sc, uint8_t drive_no, uint16_t idn, size_t size) +{ + ec_soe_request_t *req = ecrt_slave_config_create_soe_request_err(sc, + drive_no, idn, size); + return IS_ERR(req) ? NULL : req; +} + +/****************************************************************************/ + +/** Same as ecrt_slave_config_create_reg_request(), but with ERR_PTR() return + * value. + */ +ec_reg_request_t *ecrt_slave_config_create_reg_request_err( + ec_slave_config_t *sc, size_t size) +{ + ec_reg_request_t *reg; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, size = %zu)\n", + __func__, sc, size); + + if (!(reg = (ec_reg_request_t *) + kmalloc(sizeof(ec_reg_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate register request memory!\n"); + return ERR_PTR(-ENOMEM); + } + + ret = ec_reg_request_init(reg, size); + if (ret) { + kfree(reg); + return ERR_PTR(ret); + } + + down(&sc->master->master_sem); + list_add_tail(®->list, &sc->reg_requests); + up(&sc->master->master_sem); + + return reg; +} + +/****************************************************************************/ + +ec_reg_request_t *ecrt_slave_config_create_reg_request( + ec_slave_config_t *sc, size_t size) +{ + ec_reg_request_t *reg = + ecrt_slave_config_create_reg_request_err(sc, size); + return IS_ERR(reg) ? NULL : reg; +} + +/****************************************************************************/ + +/** Same as ecrt_slave_config_create_voe_handler(), but with ERR_PTR() return + * value. + */ +ec_voe_handler_t *ecrt_slave_config_create_voe_handler_err( + ec_slave_config_t *sc, size_t size) +{ + ec_voe_handler_t *voe; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, size = %zu)\n", __func__, sc, size); + + if (!(voe = (ec_voe_handler_t *) + kmalloc(sizeof(ec_voe_handler_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate VoE request memory!\n"); + return ERR_PTR(-ENOMEM); + } + + ret = ec_voe_handler_init(voe, sc, size); + if (ret < 0) { + kfree(voe); + return ERR_PTR(ret); + } + + down(&sc->master->master_sem); + list_add_tail(&voe->list, &sc->voe_handlers); + up(&sc->master->master_sem); + + return voe; +} + +/****************************************************************************/ + +ec_voe_handler_t *ecrt_slave_config_create_voe_handler( + ec_slave_config_t *sc, size_t size) +{ + ec_voe_handler_t *voe = ecrt_slave_config_create_voe_handler_err(sc, + size); + return IS_ERR(voe) ? NULL : voe; +} + +/****************************************************************************/ + +int ecrt_slave_config_state(const ec_slave_config_t *sc, + ec_slave_config_state_t *state) +{ + const ec_slave_t *slave = sc->slave; + + state->online = slave ? 1 : 0; + if (state->online) { + state->operational = + slave->current_state == EC_SLAVE_STATE_OP && !slave->force_config; + state->al_state = slave->current_state; + } else { + state->operational = 0; + state->al_state = EC_SLAVE_STATE_UNKNOWN; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_idn(ec_slave_config_t *sc, uint8_t drive_no, + uint16_t idn, ec_al_state_t state, const uint8_t *data, + size_t size) +{ + ec_slave_t *slave = sc->slave; + ec_soe_request_t *req; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, drive_no = %u, idn = 0x%04X, " + "state = %u, data = 0x%p, size = %zu)\n", + __func__, sc, drive_no, idn, state, data, size); + + if (drive_no > 7) { + EC_CONFIG_ERR(sc, "Invalid drive number %u!\n", + (unsigned int) drive_no); + return -EINVAL; + } + + if (state != EC_AL_STATE_PREOP && state != EC_AL_STATE_SAFEOP) { + EC_CONFIG_ERR(sc, "AL state for IDN config" + " must be PREOP or SAFEOP!\n"); + return -EINVAL; + } + + if (slave && !(slave->sii.mailbox_protocols & EC_MBOX_SOE)) { + EC_CONFIG_WARN(sc, "Attached slave does not support SoE!\n"); + } + + if (!(req = (ec_soe_request_t *) + kmalloc(sizeof(ec_soe_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate memory for" + " IDN configuration!\n"); + return -ENOMEM; + } + + ec_soe_request_init(req); + ec_soe_request_set_drive_no(req, drive_no); + ec_soe_request_set_idn(req, idn); + req->al_state = state; + + ret = ec_soe_request_copy_data(req, data, size); + if (ret < 0) { + ec_soe_request_clear(req); + kfree(req); + return ret; + } + + down(&sc->master->master_sem); + list_add_tail(&req->list, &sc->soe_configs); + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_flag(ec_slave_config_t *sc, const char *key, + int32_t value) +{ + ec_flag_t *flag; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, key = %s, value = %i)\n", + __func__, sc, key, value); + + + flag = ec_slave_config_find_flag(sc, key); + if (flag) { + flag->value = value; // overwrite value + } + else { // new flag + int ret; + + if (!(flag = (ec_flag_t *) kmalloc(sizeof(ec_flag_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate memory for flag!\n"); + return -ENOMEM; + } + + ret = ec_flag_init(flag, key, value); + if (ret) { + kfree(flag); + return ret; + } + + down(&sc->master->master_sem); + list_add_tail(&flag->list, &sc->flags); + up(&sc->master->master_sem); + } + return 0; +} + +/****************************************************************************/ + +#ifdef EC_EOE + +int ecrt_slave_config_eoe_mac_address(ec_slave_config_t *sc, + const unsigned char *mac_address) +{ + memcpy(sc->eoe_ip_param_request.mac_address, mac_address, EC_ETH_ALEN); + sc->eoe_ip_param_request.mac_address_included = 1; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_eoe_ip_address(ec_slave_config_t *sc, + struct in_addr ip_address) +{ + sc->eoe_ip_param_request.ip_address = ip_address; + sc->eoe_ip_param_request.ip_address_included = 1; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_eoe_subnet_mask(ec_slave_config_t *sc, + struct in_addr subnet_mask) +{ + sc->eoe_ip_param_request.subnet_mask = subnet_mask; + sc->eoe_ip_param_request.subnet_mask_included = 1; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_eoe_default_gateway(ec_slave_config_t *sc, + struct in_addr gateway_address) +{ + sc->eoe_ip_param_request.gateway = gateway_address; + sc->eoe_ip_param_request.gateway_included = 1; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_eoe_dns_address(ec_slave_config_t *sc, + struct in_addr dns_address) +{ + sc->eoe_ip_param_request.dns = dns_address; + sc->eoe_ip_param_request.dns_included = 1; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_eoe_hostname(ec_slave_config_t *sc, + const char *name) +{ + strscpy(sc->eoe_ip_param_request.name, name, EC_MAX_HOSTNAME_SIZE - 1); + sc->eoe_ip_param_request.name_included = 1; + return 0; +} + +#endif + +/****************************************************************************/ + +int ecrt_slave_config_state_timeout(ec_slave_config_t *sc, + ec_al_state_t from, ec_al_state_t to, unsigned int timeout_ms) +{ + ec_al_timeout_t *timeout; + ec_slave_state_t from_state, to_state; + + if (from != EC_AL_STATE_INIT && from != EC_AL_STATE_PREOP && + from != EC_AL_STATE_SAFEOP && from != EC_AL_STATE_OP) { + EC_CONFIG_ERR(sc, "Invalid from state %i.\n", from); + return -EINVAL; + } + if (to != EC_AL_STATE_INIT && to != EC_AL_STATE_PREOP && + to != EC_AL_STATE_SAFEOP && to != EC_AL_STATE_OP) { + EC_CONFIG_ERR(sc, "Invalid to state %i.\n", to); + return -EINVAL; + } + + from_state = (ec_slave_state_t) from; + to_state = (ec_slave_state_t) to; + + /* try to find an already configured timeout. */ + list_for_each_entry(timeout, &sc->al_timeouts, list) { + if (timeout->from == from_state && timeout->to == to_state) { + if (timeout_ms == 0) { + // delete configured value + list_del(&timeout->list); + kfree(timeout); + return 0; + } + timeout->timeout_ms = timeout_ms; + return 0; + } + } + + if (timeout_ms == 0) { + return 0; + } + + /* no timeout found. create one. */ + if (!(timeout = (ec_al_timeout_t *) + kmalloc(sizeof(ec_al_timeout_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate memory for" + " AL timeout configuration!\n"); + return -ENOMEM; + } + + timeout->from = from_state; + timeout->to = to_state; + timeout->timeout_ms = timeout_ms; + + down(&sc->master->master_sem); + list_add_tail(&timeout->list, &sc->al_timeouts); + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_slave_config_sync_manager); +EXPORT_SYMBOL(ecrt_slave_config_watchdog); +EXPORT_SYMBOL(ecrt_slave_config_pdo_assign_add); +EXPORT_SYMBOL(ecrt_slave_config_pdo_assign_clear); +EXPORT_SYMBOL(ecrt_slave_config_pdo_mapping_add); +EXPORT_SYMBOL(ecrt_slave_config_pdo_mapping_clear); +EXPORT_SYMBOL(ecrt_slave_config_pdos); +EXPORT_SYMBOL(ecrt_slave_config_reg_pdo_entry); +EXPORT_SYMBOL(ecrt_slave_config_reg_pdo_entry_pos); +EXPORT_SYMBOL(ecrt_slave_config_dc); +EXPORT_SYMBOL(ecrt_slave_config_sdo); +EXPORT_SYMBOL(ecrt_slave_config_sdo8); +EXPORT_SYMBOL(ecrt_slave_config_sdo16); +EXPORT_SYMBOL(ecrt_slave_config_sdo32); +EXPORT_SYMBOL(ecrt_slave_config_complete_sdo); +EXPORT_SYMBOL(ecrt_slave_config_emerg_size); +EXPORT_SYMBOL(ecrt_slave_config_emerg_pop); +EXPORT_SYMBOL(ecrt_slave_config_emerg_clear); +EXPORT_SYMBOL(ecrt_slave_config_emerg_overruns); +EXPORT_SYMBOL(ecrt_slave_config_create_sdo_request); +EXPORT_SYMBOL(ecrt_slave_config_create_soe_request); +EXPORT_SYMBOL(ecrt_slave_config_create_voe_handler); +EXPORT_SYMBOL(ecrt_slave_config_create_reg_request); +EXPORT_SYMBOL(ecrt_slave_config_state); +EXPORT_SYMBOL(ecrt_slave_config_idn); +EXPORT_SYMBOL(ecrt_slave_config_flag); +#ifdef EOE +EXPORT_SYMBOL(ecrt_slave_config_eoe_mac_address); +EXPORT_SYMBOL(ecrt_slave_config_eoe_ip_address); +EXPORT_SYMBOL(ecrt_slave_config_eoe_subnet_mask); +EXPORT_SYMBOL(ecrt_slave_config_eoe_default_gateway); +EXPORT_SYMBOL(ecrt_slave_config_eoe_dns_address); +EXPORT_SYMBOL(ecrt_slave_config_eoe_hostname); +#endif +EXPORT_SYMBOL(ecrt_slave_config_state_timeout); + +/** \endcond */ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/slave_config.h b/ubuntu/igh-ecat/master/slave_config.h new file mode 100644 index 00000000000000..124995c28150d9 --- /dev/null +++ b/ubuntu/igh-ecat/master/slave_config.h @@ -0,0 +1,196 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave configuration structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SLAVE_CONFIG_H__ +#define __EC_SLAVE_CONFIG_H__ + +#include + +#include "globals.h" +#include "slave.h" +#include "sync_config.h" +#include "fmmu_config.h" +#include "coe_emerg_ring.h" +#include "flag.h" + +/****************************************************************************/ + +/** Convenience macro for printing configuration-specific information to + * syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT :: ", where INDEX is the master index + * and ALIAS and POSITION identify the configuration. + * + * \param sc EtherCAT slave configuration + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_CONFIG_INFO(sc, fmt, args...) \ + printk(KERN_INFO "EtherCAT %u %u:%u: " fmt, sc->master->index, \ + sc->alias, sc->position, ##args) + +/** Convenience macro for printing configuration-specific errors to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT :: ", where INDEX is the master index + * and ALIAS and POSITION identify the configuration. + * + * \param sc EtherCAT slave configuration + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_CONFIG_ERR(sc, fmt, args...) \ + printk(KERN_ERR "EtherCAT ERROR %u %u:%u: " fmt, sc->master->index, \ + sc->alias, sc->position, ##args) + +/** Convenience macro for printing configuration-specific warnings to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT :: ", where INDEX is the master index + * and ALIAS and POSITION identify the configuration. + * + * \param sc EtherCAT slave configuration + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_CONFIG_WARN(sc, fmt, args...) \ + printk(KERN_WARNING "EtherCAT WARNING %u %u:%u: " fmt, \ + sc->master->index, sc->alias, sc->position, ##args) + +/** Convenience macro for printing configuration-specific debug messages to + * syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT :: ", where INDEX is the master index + * and ALIAS and POSITION identify the configuration. + * + * \param sc EtherCAT slave configuration + * \param level Debug level. Master's debug level must be >= \a level for + * output. + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_CONFIG_DBG(sc, level, fmt, args...) \ + do { \ + if (sc->master->debug_level >= level) { \ + printk(KERN_DEBUG "EtherCAT DEBUG %u %u:%u: " fmt, \ + sc->master->index, sc->alias, sc->position, ##args); \ + } \ + } while (0) + +/****************************************************************************/ + +/** EtherCAT slave configuration. + */ +struct ec_slave_config { + struct list_head list; /**< List item. */ + ec_master_t *master; /**< Master owning the slave configuration. */ + + uint16_t alias; /**< Slave alias. */ + uint16_t position; /**< Index after alias. If alias is zero, this is the + ring position. */ + uint32_t vendor_id; /**< Slave vendor ID. */ + uint32_t product_code; /**< Slave product code. */ + + uint16_t watchdog_divider; /**< Watchdog divider as a number of 40ns + intervals (see spec. reg. 0x0400). */ + uint16_t watchdog_intervals; /**< Process data watchdog intervals (see + spec. reg. 0x0420). */ + + ec_slave_t *slave; /**< Slave pointer. This is \a NULL, if the slave is + offline. */ + + ec_sync_config_t sync_configs[EC_MAX_SYNC_MANAGERS]; /**< Sync manager + configurations. */ + ec_fmmu_config_t fmmu_configs[EC_MAX_FMMUS]; /**< FMMU configurations. */ + uint8_t used_fmmus; /**< Number of FMMUs used. */ + uint16_t dc_assign_activate; /**< Vendor-specific AssignActivate word. */ + ec_sync_signal_t dc_sync[EC_SYNC_SIGNAL_COUNT]; /**< DC sync signals. */ + + struct list_head sdo_configs; /**< List of SDO configurations. */ + struct list_head sdo_requests; /**< List of SDO requests. */ + struct list_head soe_requests; /**< List of SoE requests. */ + struct list_head voe_handlers; /**< List of VoE handlers. */ + struct list_head reg_requests; /**< List of register requests. */ + struct list_head soe_configs; /**< List of SoE configurations. */ + struct list_head flags; /**< List of feature flags. */ + struct list_head al_timeouts; /**< List of specific AL state timeouts. */ + +#ifdef EC_EOE + ec_eoe_request_t eoe_ip_param_request; /**< EoE IP parameters. */ +#endif + + ec_coe_emerg_ring_t emerg_ring; /**< CoE emergency ring buffer. */ +}; + +/****************************************************************************/ + +void ec_slave_config_init(ec_slave_config_t *, ec_master_t *, uint16_t, + uint16_t, uint32_t, uint32_t); +void ec_slave_config_clear(ec_slave_config_t *); + +int ec_slave_config_attach(ec_slave_config_t *); +void ec_slave_config_detach(ec_slave_config_t *); + +void ec_slave_config_load_default_sync_config(ec_slave_config_t *); + +unsigned int ec_slave_config_sdo_count(const ec_slave_config_t *); +const ec_sdo_request_t *ec_slave_config_get_sdo_by_pos_const( + const ec_slave_config_t *, unsigned int); +unsigned int ec_slave_config_idn_count(const ec_slave_config_t *); +const ec_soe_request_t *ec_slave_config_get_idn_by_pos_const( + const ec_slave_config_t *, unsigned int); +unsigned int ec_slave_config_flag_count(const ec_slave_config_t *); +const ec_flag_t *ec_slave_config_get_flag_by_pos_const( + const ec_slave_config_t *, unsigned int); +ec_sdo_request_t *ec_slave_config_find_sdo_request(ec_slave_config_t *, + unsigned int); +ec_soe_request_t *ec_slave_config_find_soe_request(ec_slave_config_t *, + unsigned int); +ec_reg_request_t *ec_slave_config_find_reg_request(ec_slave_config_t *, + unsigned int); +ec_voe_handler_t *ec_slave_config_find_voe_handler(ec_slave_config_t *, + unsigned int); +ec_flag_t *ec_slave_config_find_flag(ec_slave_config_t *, const char *); + +ec_sdo_request_t *ecrt_slave_config_create_sdo_request_err( + ec_slave_config_t *, uint16_t, uint8_t, size_t); +ec_soe_request_t *ecrt_slave_config_create_soe_request_err( + ec_slave_config_t *, uint8_t, uint16_t, size_t); +ec_voe_handler_t *ecrt_slave_config_create_voe_handler_err( + ec_slave_config_t *, size_t); +ec_reg_request_t *ecrt_slave_config_create_reg_request_err( + ec_slave_config_t *, size_t); + +unsigned int ec_slave_config_al_timeout(const ec_slave_config_t *, + ec_slave_state_t, ec_slave_state_t); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/soe_errors.c b/ubuntu/igh-ecat/master/soe_errors.c new file mode 100644 index 00000000000000..937803b2e6ca5e --- /dev/null +++ b/ubuntu/igh-ecat/master/soe_errors.c @@ -0,0 +1,88 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT SoE errors. +*/ + +/****************************************************************************/ + +#include "globals.h" + +/****************************************************************************/ + +/** SoE error codes. + */ +const ec_code_msg_t soe_error_codes[] = { + {0x1001, "No IDN"}, + {0x1009, "Invalid access to element 1"}, + {0x2001, "No name"}, + {0x2002, "Name transmission too short"}, + {0x2003, "Name transmission too long"}, + {0x2004, "Name cannot be changed, read only"}, + {0x2005, "Name is write protected at this time"}, + {0x3002, "Attribute transmission too short"}, + {0x3003, "Attribute transmission too long"}, + {0x3004, "Attribute cannot be changed, read only"}, + {0x3005, "Attribute is write protected at this time"}, + {0x4001, "No unit"}, + {0x4002, "Unit transmission too short"}, + {0x4003, "Unit transmission too long"}, + {0x4004, "Unit cannot be changed, read only"}, + {0x4005, "Unit is write proteced at this time"}, + {0x5001, "No minimum input value"}, + {0x5002, "Minimum input value transmission too short"}, + {0x5003, "Minimum input value transmission too long"}, + {0x5004, "Minimum input value cannot be changed, read only"}, + {0x5005, "Minimum input value is write protected at this time"}, + {0x6001, "No maximum input value"}, + {0x6002, "Maximum input value transmission too short"}, + {0x6003, "Maximum input value transmission too long"}, + {0x6004, "Maximum input value cannot be changed, read only"}, + {0x6005, "Maximum input value is write protected at this time"}, + {0x7002, "Operation data value transmission too short"}, + {0x7003, "Operation data value transmission too long"}, + {0x7004, "Operation data value cannot be changed, read only"}, + {0x7005, "Operation data value is write protected at this time"}, + {0x7006, "Operation data value is smaller than the minimum input value"}, + {0x7007, "Operation data value is greater than the minimum input value"}, + {0x7008, "Invalid operation data"}, + {0x7009, "Operation data is write protected by a password"}, + {0x700A, "Operation data is write protected"}, + {0x700B, "Invalid indirect addressing"}, + {0x700C, "Operation data is write protected due to other settings"}, + {0x700D, "Reserved"}, + {0x7010, "Procedure command already active"}, + {0x7011, "Procedure command not interruptible"}, + {0x7012, "Procedure command is at this time not executable"}, + {0x7013, "Procedure command not executable"}, + {0x7014, "No data state"}, + {0x8001, "No default value"}, + {0x8002, "Default value transmission too long"}, + {0x8004, "Default value cannot be changed, read only"}, + {0x800A, "Invalid drive number"}, + {0x800B, "General error"}, + {0x800C, "No element addressed"}, + {} +}; + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/soe_request.c b/ubuntu/igh-ecat/master/soe_request.c new file mode 100644 index 00000000000000..ef90124ba35a72 --- /dev/null +++ b/ubuntu/igh-ecat/master/soe_request.c @@ -0,0 +1,333 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Sercos-over-EtherCAT request functions. + */ + +/****************************************************************************/ + +#include +#include +#include + +#include "soe_request.h" + +/****************************************************************************/ + +/** Default timeout in ms to wait for SoE responses. + */ +#define EC_SOE_REQUEST_RESPONSE_TIMEOUT 1000 + +/****************************************************************************/ + +void ec_soe_request_clear_data(ec_soe_request_t *); + +/****************************************************************************/ + +/** SoE request constructor. + */ +void ec_soe_request_init( + ec_soe_request_t *req /**< SoE request. */ + ) +{ + INIT_LIST_HEAD(&req->list); + req->drive_no = 0x00; + req->idn = 0x0000; + req->al_state = EC_AL_STATE_INIT; + req->data = NULL; + req->mem_size = 0; + req->data_size = 0; + req->issue_timeout = 0; // no timeout + req->dir = EC_DIR_INVALID; + req->state = EC_INT_REQUEST_INIT; + req->jiffies_start = 0U; + req->jiffies_sent = 0U; + req->error_code = 0x0000; +} + +/****************************************************************************/ + +/** SoE request destructor. + */ +void ec_soe_request_clear( + ec_soe_request_t *req /**< SoE request. */ + ) +{ + ec_soe_request_clear_data(req); +} + +/****************************************************************************/ + +/** Copy another SoE request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_soe_request_copy( + ec_soe_request_t *req, /**< SoE request. */ + const ec_soe_request_t *other /**< Other SoE request to copy from. */ + ) +{ + req->drive_no = other->drive_no; + req->idn = other->idn; + req->al_state = other->al_state; + return ec_soe_request_copy_data(req, other->data, other->data_size); +} + +/****************************************************************************/ + +/** Set drive number. + */ +void ec_soe_request_set_drive_no( + ec_soe_request_t *req, /**< SoE request. */ + uint8_t drive_no /** Drive Number. */ + ) +{ + req->drive_no = drive_no; +} + +/****************************************************************************/ + +/** Set IDN. + */ +void ec_soe_request_set_idn( + ec_soe_request_t *req, /**< SoE request. */ + uint16_t idn /** IDN. */ + ) +{ + req->idn = idn; +} + +/****************************************************************************/ + +/** Free allocated memory. + */ +void ec_soe_request_clear_data( + ec_soe_request_t *req /**< SoE request. */ + ) +{ + if (req->data) { + kfree(req->data); + req->data = NULL; + } + + req->mem_size = 0; + req->data_size = 0; +} + +/****************************************************************************/ + +/** Pre-allocates the data memory. + * + * If the \a mem_size is already bigger than \a size, nothing is done. + * + * \return 0 on success, otherwise -ENOMEM. + */ +int ec_soe_request_alloc( + ec_soe_request_t *req, /**< SoE request. */ + size_t size /**< Data size to allocate. */ + ) +{ + if (size <= req->mem_size) + return 0; + + ec_soe_request_clear_data(req); + + if (!(req->data = (uint8_t *) kmalloc(size, GFP_KERNEL))) { + EC_ERR("Failed to allocate %zu bytes of SoE memory.\n", size); + return -ENOMEM; + } + + req->mem_size = size; + req->data_size = 0; + return 0; +} + +/****************************************************************************/ + +/** Copies SoE data from an external source. + * + * If the \a mem_size is to small, new memory is allocated. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_soe_request_copy_data( + ec_soe_request_t *req, /**< SoE request. */ + const uint8_t *source, /**< Source data. */ + size_t size /**< Number of bytes in \a source. */ + ) +{ + int ret = ec_soe_request_alloc(req, size); + if (ret < 0) + return ret; + + memcpy(req->data, source, size); + req->data_size = size; + return 0; +} + +/****************************************************************************/ + +/** Copies SoE data from an external source. + * + * If the \a mem_size is to small, new memory is allocated. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_soe_request_append_data( + ec_soe_request_t *req, /**< SoE request. */ + const uint8_t *source, /**< Source data. */ + size_t size /**< Number of bytes in \a source. */ + ) +{ + if (req->data_size + size > req->mem_size) { + size_t new_size = req->mem_size ? req->mem_size * 2 : size; + uint8_t *new_data = (uint8_t *) kmalloc(new_size, GFP_KERNEL); + if (!new_data) { + EC_ERR("Failed to allocate %zu bytes of SoE memory.\n", + new_size); + return -ENOMEM; + } + memcpy(new_data, req->data, req->data_size); + kfree(req->data); + req->data = new_data; + req->mem_size = new_size; + } + + memcpy(req->data + req->data_size, source, size); + req->data_size += size; + return 0; +} + +/****************************************************************************/ + +/** Request a read operation. + */ +int ec_soe_request_read( + ec_soe_request_t *req /**< SoE request. */ + ) +{ + req->dir = EC_DIR_INPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->error_code = 0x0000; + req->jiffies_start = jiffies; + return 0; +} + +/****************************************************************************/ + +/** Request a write operation. + */ +int ec_soe_request_write( + ec_soe_request_t *req /**< SoE request. */ + ) +{ + req->dir = EC_DIR_OUTPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->error_code = 0x0000; + req->jiffies_start = jiffies; + return 0; +} + +/****************************************************************************/ + +/** Checks, if the timeout was exceeded. + * + * \return non-zero if the timeout was exceeded, else zero. + */ +int ec_soe_request_timed_out(const ec_soe_request_t *req /**< SDO request. */) +{ + return req->issue_timeout + && jiffies - req->jiffies_start > HZ * req->issue_timeout / 1000; +} + +/***************************************************************************** + * Application interface. + ****************************************************************************/ + +int ecrt_soe_request_idn(ec_soe_request_t *req, uint8_t drive_no, + uint16_t idn) +{ + req->drive_no = drive_no; + req->idn = idn; + return 0; +} + +/****************************************************************************/ + +int ecrt_soe_request_timeout(ec_soe_request_t *req, uint32_t timeout) +{ + req->issue_timeout = timeout; + return 0; +} + +/****************************************************************************/ + +uint8_t *ecrt_soe_request_data(const ec_soe_request_t *req) +{ + return req->data; +} + +/****************************************************************************/ + +size_t ecrt_soe_request_data_size(const ec_soe_request_t *req) +{ + return req->data_size; +} + +/****************************************************************************/ + +ec_request_state_t ecrt_soe_request_state(const ec_soe_request_t *req) +{ + return ec_request_state_translation_table[req->state]; +} + +/****************************************************************************/ + +int ecrt_soe_request_read(ec_soe_request_t *req) +{ + return ec_soe_request_read(req); +} + +/****************************************************************************/ + +int ecrt_soe_request_write(ec_soe_request_t *req) +{ + return ec_soe_request_write(req); +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_soe_request_idn); +EXPORT_SYMBOL(ecrt_soe_request_timeout); +EXPORT_SYMBOL(ecrt_soe_request_data); +EXPORT_SYMBOL(ecrt_soe_request_data_size); +EXPORT_SYMBOL(ecrt_soe_request_state); +EXPORT_SYMBOL(ecrt_soe_request_read); +EXPORT_SYMBOL(ecrt_soe_request_write); + +/** \endcond */ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/soe_request.h b/ubuntu/igh-ecat/master/soe_request.h new file mode 100644 index 00000000000000..ced4c9a196c048 --- /dev/null +++ b/ubuntu/igh-ecat/master/soe_request.h @@ -0,0 +1,76 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT SoE request structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SOE_REQUEST_H__ +#define __EC_SOE_REQUEST_H__ + +#include + +#include "globals.h" + +/****************************************************************************/ + +/** Sercos-over-EtherCAT request. + */ +struct ec_soe_request { + struct list_head list; /**< List item. */ + uint8_t drive_no; /**< Drive number. */ + uint16_t idn; /**< Sercos ID-Number. */ + ec_al_state_t al_state; /**< AL state (only valid for IDN config). */ + uint8_t *data; /**< Pointer to SDO data. */ + size_t mem_size; /**< Size of SDO data memory. */ + size_t data_size; /**< Size of SDO data. */ + uint32_t issue_timeout; /**< Maximum time in ms, the processing of the + request may take. */ + ec_direction_t dir; /**< Direction. EC_DIR_OUTPUT means writing to the + slave, EC_DIR_INPUT means reading from the slave. */ + ec_internal_request_state_t state; /**< Request state. */ + unsigned long jiffies_start; /**< Jiffies, when the request was issued. */ + unsigned long jiffies_sent; /**< Jiffies, when the upload/download + request was sent. */ + uint16_t error_code; /**< SoE error code. */ +}; + +/****************************************************************************/ + +void ec_soe_request_init(ec_soe_request_t *); +void ec_soe_request_clear(ec_soe_request_t *); + +int ec_soe_request_copy(ec_soe_request_t *, const ec_soe_request_t *); +void ec_soe_request_set_drive_no(ec_soe_request_t *, uint8_t); +void ec_soe_request_set_idn(ec_soe_request_t *, uint16_t); +int ec_soe_request_alloc(ec_soe_request_t *, size_t); +int ec_soe_request_copy_data(ec_soe_request_t *, const uint8_t *, size_t); +int ec_soe_request_append_data(ec_soe_request_t *, const uint8_t *, size_t); +int ec_soe_request_read(ec_soe_request_t *); +int ec_soe_request_write(ec_soe_request_t *); +int ec_soe_request_timed_out(const ec_soe_request_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/sync.c b/ubuntu/igh-ecat/master/sync.c new file mode 100644 index 00000000000000..bcfe63fcafe602 --- /dev/null +++ b/ubuntu/igh-ecat/master/sync.c @@ -0,0 +1,170 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT sync manager methods. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "slave.h" +#include "master.h" +#include "pdo.h" +#include "sync.h" + +/****************************************************************************/ + +/** Constructor. + */ +void ec_sync_init( + ec_sync_t *sync, /**< EtherCAT sync manager. */ + ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + sync->slave = slave; + sync->physical_start_address = 0x0000; + sync->default_length = 0x0000; + sync->control_register = 0x00; + sync->enable = 0x00; + ec_pdo_list_init(&sync->pdos); +} + +/****************************************************************************/ + +/** Copy constructor. + */ +void ec_sync_init_copy( + ec_sync_t *sync, /**< EtherCAT sync manager. */ + const ec_sync_t *other /**< Sync manager to copy from. */ + ) +{ + sync->slave = other->slave; + sync->physical_start_address = other->physical_start_address; + sync->default_length = other->default_length; + sync->control_register = other->control_register; + sync->enable = other->enable; + ec_pdo_list_init(&sync->pdos); + ec_pdo_list_copy(&sync->pdos, &other->pdos); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_sync_clear( + ec_sync_t *sync /**< EtherCAT sync manager. */ + ) +{ + ec_pdo_list_clear(&sync->pdos); +} + +/****************************************************************************/ + +/** Initializes a sync manager configuration page. + * + * The referenced memory (\a data) must be at least \a EC_SYNC_SIZE bytes. + */ +void ec_sync_page( + const ec_sync_t *sync, /**< Sync manager. */ + uint8_t sync_index, /**< Index of the sync manager. */ + uint16_t data_size, /**< Data size. */ + const ec_sync_config_t *sync_config, /**< Configuration. */ + uint8_t pdo_xfer, /**< Non-zero, if PDOs will be transferred via this + sync manager. */ + uint8_t *data /**> Configuration memory. */ + ) +{ + // enable only if (SII enable is set or PDO xfer) + // and size is > 0 and SM is not virtual + uint16_t enable = ((sync->enable & 0x01) || pdo_xfer) + && data_size + && ((sync->enable & 0x04) == 0); + uint8_t control = sync->control_register; + + if (sync_config) { + + switch (sync_config->dir) { + case EC_DIR_OUTPUT: + case EC_DIR_INPUT: + EC_WRITE_BIT(&control, 2, + sync_config->dir == EC_DIR_OUTPUT ? 1 : 0); + EC_WRITE_BIT(&control, 3, 0); + break; + default: + break; + } + + switch (sync_config->watchdog_mode) { + case EC_WD_ENABLE: + case EC_WD_DISABLE: + EC_WRITE_BIT(&control, 6, + sync_config->watchdog_mode == EC_WD_ENABLE); + break; + default: + break; + } + } + + EC_SLAVE_DBG(sync->slave, 1, "SM%u: Addr 0x%04X, Size %3u," + " Ctrl 0x%02X, En %u\n", + sync_index, sync->physical_start_address, + data_size, control, enable); + + EC_WRITE_U16(data, sync->physical_start_address); + EC_WRITE_U16(data + 2, data_size); + EC_WRITE_U8 (data + 4, control); + EC_WRITE_U8 (data + 5, 0x00); // status byte (read only) + EC_WRITE_U16(data + 6, enable); +} + +/****************************************************************************/ + +/** Adds a PDO to the list of known mapped PDOs. + * + * \return 0 on success, else < 0 + */ +int ec_sync_add_pdo( + ec_sync_t *sync, /**< EtherCAT sync manager. */ + const ec_pdo_t *pdo /**< PDO to map. */ + ) +{ + return ec_pdo_list_add_pdo_copy(&sync->pdos, pdo); +} + +/****************************************************************************/ + +/** Determines the default direction from the control register. + * + * \return Direction. + */ +ec_direction_t ec_sync_default_direction( + const ec_sync_t *sync /**< EtherCAT sync manager. */ + ) +{ + switch ((sync->control_register & 0x0C) >> 2) { + case 0x0: return EC_DIR_INPUT; + case 0x1: return EC_DIR_OUTPUT; + default: return EC_DIR_INVALID; + } +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/sync.h b/ubuntu/igh-ecat/master/sync.h new file mode 100644 index 00000000000000..9d0ddced610fbb --- /dev/null +++ b/ubuntu/igh-ecat/master/sync.h @@ -0,0 +1,60 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT sync manager. + */ + +/****************************************************************************/ + +#ifndef __EC_SYNC_H__ +#define __EC_SYNC_H__ + +#include "globals.h" +#include "pdo_list.h" +#include "sync_config.h" + +/****************************************************************************/ + +/** Sync manager. + */ +typedef struct { + ec_slave_t *slave; /**< Slave, the sync manager belongs to. */ + uint16_t physical_start_address; /**< Physical start address. */ + uint16_t default_length; /**< Data length in bytes. */ + uint8_t control_register; /**< Control register value. */ + uint8_t enable; /**< Enable bit. */ + ec_pdo_list_t pdos; /**< Current PDO assignment. */ +} ec_sync_t; + +/****************************************************************************/ + +void ec_sync_init(ec_sync_t *, ec_slave_t *); +void ec_sync_init_copy(ec_sync_t *, const ec_sync_t *); +void ec_sync_clear(ec_sync_t *); +void ec_sync_page(const ec_sync_t *, uint8_t, uint16_t, + const ec_sync_config_t *, uint8_t, uint8_t *); +int ec_sync_add_pdo(ec_sync_t *, const ec_pdo_t *); +ec_direction_t ec_sync_default_direction(const ec_sync_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/sync_config.c b/ubuntu/igh-ecat/master/sync_config.c new file mode 100644 index 00000000000000..d2d87a74948d32 --- /dev/null +++ b/ubuntu/igh-ecat/master/sync_config.c @@ -0,0 +1,55 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT sync manager configuration methods. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "sync_config.h" + +/****************************************************************************/ + +/** Constructor. + */ +void ec_sync_config_init( + ec_sync_config_t *sync_config /**< Sync manager configuration. */ + ) +{ + sync_config->dir = EC_DIR_INVALID; + sync_config->watchdog_mode = EC_WD_DEFAULT; + ec_pdo_list_init(&sync_config->pdos); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_sync_config_clear( + ec_sync_config_t *sync_config /**< Sync manager configuration. */ + ) +{ + ec_pdo_list_clear(&sync_config->pdos); +} + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/sync_config.h b/ubuntu/igh-ecat/master/sync_config.h new file mode 100644 index 00000000000000..ca31aa72014165 --- /dev/null +++ b/ubuntu/igh-ecat/master/sync_config.h @@ -0,0 +1,51 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT sync manager. + */ + +/****************************************************************************/ + +#ifndef __EC_SYNC_CONFIG_H__ +#define __EC_SYNC_CONFIG_H__ + +#include "globals.h" +#include "pdo_list.h" + +/****************************************************************************/ + +/** Sync manager configuration. + */ +typedef struct { + ec_direction_t dir; /**< Sync manager direction. */ + ec_watchdog_mode_t watchdog_mode; /**< Watchdog mode. */ + ec_pdo_list_t pdos; /**< Current PDO assignment. */ +} ec_sync_config_t; + +/****************************************************************************/ + +void ec_sync_config_init(ec_sync_config_t *); +void ec_sync_config_clear(ec_sync_config_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/igh-ecat/master/voe_handler.c b/ubuntu/igh-ecat/master/voe_handler.c new file mode 100644 index 00000000000000..fc8cf307b34d83 --- /dev/null +++ b/ubuntu/igh-ecat/master/voe_handler.c @@ -0,0 +1,553 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Vendor specific over EtherCAT protocol handler functions. + */ + +/****************************************************************************/ + +#include + +#include "master.h" +#include "slave_config.h" +#include "mailbox.h" +#include "voe_handler.h" + +/** VoE header size. + */ +#define EC_VOE_HEADER_SIZE 6 + +/** VoE response timeout in [ms]. + */ +#define EC_VOE_RESPONSE_TIMEOUT 500 + +/****************************************************************************/ + +void ec_voe_handler_state_write_start(ec_voe_handler_t *); +void ec_voe_handler_state_write_response(ec_voe_handler_t *); + +void ec_voe_handler_state_read_start(ec_voe_handler_t *); +void ec_voe_handler_state_read_check(ec_voe_handler_t *); +void ec_voe_handler_state_read_response(ec_voe_handler_t *); + +void ec_voe_handler_state_read_nosync_start(ec_voe_handler_t *); +void ec_voe_handler_state_read_nosync_response(ec_voe_handler_t *); + +void ec_voe_handler_state_end(ec_voe_handler_t *); +void ec_voe_handler_state_error(ec_voe_handler_t *); + +/****************************************************************************/ + +/** VoE handler constructor. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_voe_handler_init( + ec_voe_handler_t *voe, /**< VoE handler. */ + ec_slave_config_t *sc, /**< Parent slave configuration. */ + size_t size /**< Size of memory to reserve. */ + ) +{ + voe->config = sc; + voe->vendor_id = 0x00000000; + voe->vendor_type = 0x0000; + voe->data_size = 0; + voe->dir = EC_DIR_INVALID; + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_INIT; + + ec_datagram_init(&voe->datagram); + return ec_datagram_prealloc(&voe->datagram, + size + EC_MBOX_HEADER_SIZE + EC_VOE_HEADER_SIZE); +} + +/****************************************************************************/ + +/** VoE handler destructor. + */ +void ec_voe_handler_clear( + ec_voe_handler_t *voe /**< VoE handler. */ + ) +{ + ec_datagram_clear(&voe->datagram); +} + +/****************************************************************************/ + +/** Get usable memory size. + * + * \return Memory size. + */ +size_t ec_voe_handler_mem_size( + const ec_voe_handler_t *voe /**< VoE handler. */ + ) +{ + if (voe->datagram.mem_size >= EC_MBOX_HEADER_SIZE + EC_VOE_HEADER_SIZE) + return voe->datagram.mem_size - + (EC_MBOX_HEADER_SIZE + EC_VOE_HEADER_SIZE); + else + return 0; +} + +/***************************************************************************** + * Application interface. + ****************************************************************************/ + +int ecrt_voe_handler_send_header(ec_voe_handler_t *voe, uint32_t vendor_id, + uint16_t vendor_type) +{ + voe->vendor_id = vendor_id; + voe->vendor_type = vendor_type; + return 0; +} + +/****************************************************************************/ + +int ecrt_voe_handler_received_header(const ec_voe_handler_t *voe, + uint32_t *vendor_id, uint16_t *vendor_type) +{ + uint8_t *header = voe->datagram.data + EC_MBOX_HEADER_SIZE; + + if (vendor_id) + *vendor_id = EC_READ_U32(header); + if (vendor_type) + *vendor_type = EC_READ_U16(header + 4); + return 0; +} + +/****************************************************************************/ + +uint8_t *ecrt_voe_handler_data(const ec_voe_handler_t *voe) +{ + return voe->datagram.data + EC_MBOX_HEADER_SIZE + EC_VOE_HEADER_SIZE; +} + +/****************************************************************************/ + +size_t ecrt_voe_handler_data_size(const ec_voe_handler_t *voe) +{ + return voe->data_size; +} + +/****************************************************************************/ + +int ecrt_voe_handler_read(ec_voe_handler_t *voe) +{ + voe->dir = EC_DIR_INPUT; + voe->state = ec_voe_handler_state_read_start; + voe->request_state = EC_INT_REQUEST_BUSY; + return 0; +} + +/****************************************************************************/ + +int ecrt_voe_handler_read_nosync(ec_voe_handler_t *voe) +{ + voe->dir = EC_DIR_INPUT; + voe->state = ec_voe_handler_state_read_nosync_start; + voe->request_state = EC_INT_REQUEST_BUSY; + return 0; +} + +/****************************************************************************/ + +int ecrt_voe_handler_write(ec_voe_handler_t *voe, size_t size) +{ + voe->dir = EC_DIR_OUTPUT; + voe->data_size = size; + voe->state = ec_voe_handler_state_write_start; + voe->request_state = EC_INT_REQUEST_BUSY; + return 0; +} + +/****************************************************************************/ + +ec_request_state_t ecrt_voe_handler_execute(ec_voe_handler_t *voe) +{ + if (voe->config->slave) { // FIXME locking? + voe->state(voe); + if (voe->request_state == EC_INT_REQUEST_BUSY) { + ec_master_queue_datagram(voe->config->master, &voe->datagram); + } + } else { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + } + + return ec_request_state_translation_table[voe->request_state]; +} + +/***************************************************************************** + * State functions. + ****************************************************************************/ + +/** Start writing VoE data. + */ +void ec_voe_handler_state_write_start(ec_voe_handler_t *voe) +{ + ec_slave_t *slave = voe->config->slave; + uint8_t *data; + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 0, "Writing %zu bytes of VoE data.\n", + voe->data_size); + ec_print_data(ecrt_voe_handler_data(voe), voe->data_size); + } + + if (!(slave->sii.mailbox_protocols & EC_MBOX_VOE)) { + EC_SLAVE_ERR(slave, "Slave does not support VoE!\n"); + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + data = ec_slave_mbox_prepare_send(slave, &voe->datagram, + EC_MBOX_TYPE_VOE, EC_VOE_HEADER_SIZE + voe->data_size); + if (IS_ERR(data)) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + EC_WRITE_U32(data, voe->vendor_id); + EC_WRITE_U16(data + 4, voe->vendor_type); + /* data already in datagram */ + + voe->retries = EC_FSM_RETRIES; + voe->jiffies_start = jiffies; + voe->state = ec_voe_handler_state_write_response; +} + +/****************************************************************************/ + +/** Wait for the mailbox response. + */ +void ec_voe_handler_state_write_response(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && voe->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Failed to receive VoE write request datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + if (!datagram->working_counter) { + unsigned long diff_ms = + (jiffies - voe->jiffies_start) * 1000 / HZ; + if (diff_ms < EC_VOE_RESPONSE_TIMEOUT) { + EC_SLAVE_DBG(slave, 1, "Slave did not respond to" + " VoE write request. Retrying after %lu ms...\n", + diff_ms); + // no response; send request datagram again + return; + } + } + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Reception of VoE write request failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + EC_CONFIG_DBG(voe->config, 1, "VoE write request successful.\n"); + + voe->request_state = EC_INT_REQUEST_SUCCESS; + voe->state = ec_voe_handler_state_end; +} + +/****************************************************************************/ + +/** Start reading VoE data. + */ +void ec_voe_handler_state_read_start(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + + EC_SLAVE_DBG(slave, 1, "Reading VoE data.\n"); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_VOE)) { + EC_SLAVE_ERR(slave, "Slave does not support VoE!\n"); + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + + voe->jiffies_start = jiffies; + voe->retries = EC_FSM_RETRIES; + voe->state = ec_voe_handler_state_read_check; +} + +/****************************************************************************/ + +/** Check for new data in the mailbox. + */ +void ec_voe_handler_state_read_check(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && voe->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Failed to receive VoE mailbox check datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Reception of VoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + if (!ec_slave_mbox_check(datagram)) { + unsigned long diff_ms = + (datagram->jiffies_received - voe->jiffies_start) * 1000 / HZ; + if (diff_ms >= EC_VOE_RESPONSE_TIMEOUT) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Timeout while waiting for VoE data.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + voe->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + voe->retries = EC_FSM_RETRIES; + voe->state = ec_voe_handler_state_read_response; +} + +/****************************************************************************/ + +/** Read the pending mailbox data. + */ +void ec_voe_handler_state_read_response(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + ec_master_t *master = voe->config->master; + uint8_t *data, mbox_prot; + size_t rec_size; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && voe->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Failed to receive VoE read datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Reception of VoE read response failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_VOE) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_WARN(slave, "Received mailbox protocol 0x%02X" + " as response.\n", mbox_prot); + ec_print_data(data, rec_size); + return; + } + + if (rec_size < EC_VOE_HEADER_SIZE) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Received VoE header is" + " incomplete (%zu bytes)!\n", rec_size); + return; + } + + if (master->debug_level) { + EC_CONFIG_DBG(voe->config, 0, "VoE data:\n"); + ec_print_data(data, rec_size); + } + + voe->data_size = rec_size - EC_VOE_HEADER_SIZE; + voe->request_state = EC_INT_REQUEST_SUCCESS; + voe->state = ec_voe_handler_state_end; // success +} + +/****************************************************************************/ + +/** Start reading VoE data without sending a sync message before. + */ +void ec_voe_handler_state_read_nosync_start(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + + EC_SLAVE_DBG(slave, 1, "Reading VoE data.\n"); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_VOE)) { + EC_SLAVE_ERR(slave, "Slave does not support VoE!\n"); + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + + voe->jiffies_start = jiffies; + voe->retries = EC_FSM_RETRIES; + voe->state = ec_voe_handler_state_read_nosync_response; +} + +/****************************************************************************/ + +/** Read the pending mailbox data without sending a sync message before. This + * might lead to an empty reponse from the client. + */ +void ec_voe_handler_state_read_nosync_response(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + ec_master_t *master = voe->config->master; + uint8_t *data, mbox_prot; + size_t rec_size; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && voe->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Failed to receive VoE read datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter == 0) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_DBG(slave, 1, "Slave did not send VoE data.\n"); + return; + } + + if (datagram->working_counter != 1) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_WARN(slave, "Reception of VoE read response failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + if (!(data = ec_slave_mbox_fetch(slave, datagram, + &mbox_prot, &rec_size))) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_VOE) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_WARN(slave, "Received mailbox protocol 0x%02X" + " as response.\n", mbox_prot); + ec_print_data(data, rec_size); + return; + } + + if (rec_size < EC_VOE_HEADER_SIZE) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Received VoE header is" + " incomplete (%zu bytes)!\n", rec_size); + return; + } + + if (master->debug_level) { + EC_CONFIG_DBG(voe->config, 1, "VoE data:\n"); + ec_print_data(data, rec_size); + } + + voe->data_size = rec_size - EC_VOE_HEADER_SIZE; + voe->request_state = EC_INT_REQUEST_SUCCESS; + voe->state = ec_voe_handler_state_end; // success +} + +/****************************************************************************/ + +/** Successful termination state function. + */ +void ec_voe_handler_state_end(ec_voe_handler_t *voe) +{ +} + +/****************************************************************************/ + +/** Failure termination state function. + */ +void ec_voe_handler_state_error(ec_voe_handler_t *voe) +{ +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_voe_handler_send_header); +EXPORT_SYMBOL(ecrt_voe_handler_received_header); +EXPORT_SYMBOL(ecrt_voe_handler_data); +EXPORT_SYMBOL(ecrt_voe_handler_data_size); +EXPORT_SYMBOL(ecrt_voe_handler_read); +EXPORT_SYMBOL(ecrt_voe_handler_write); +EXPORT_SYMBOL(ecrt_voe_handler_execute); + +/** \endcond */ + +/****************************************************************************/ diff --git a/ubuntu/igh-ecat/master/voe_handler.h b/ubuntu/igh-ecat/master/voe_handler.h new file mode 100644 index 00000000000000..8e85372ccf051d --- /dev/null +++ b/ubuntu/igh-ecat/master/voe_handler.h @@ -0,0 +1,65 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Vendor specific over EtherCAT protocol handler. +*/ + +/****************************************************************************/ + +#ifndef __EC_VOE_HANDLER_H__ +#define __EC_VOE_HANDLER_H__ + +#include + +#include "globals.h" +#include "datagram.h" + +/****************************************************************************/ + +/** Vendor specific over EtherCAT handler. + */ +struct ec_voe_handler { + struct list_head list; /**< List item. */ + ec_slave_config_t *config; /**< Parent slave configuration. */ + ec_datagram_t datagram; /**< State machine datagram. */ + uint32_t vendor_id; /**< Vendor ID for the header. */ + uint16_t vendor_type; /**< Vendor type for the header. */ + size_t data_size; /**< Size of VoE data. */ + ec_direction_t dir; /**< Direction. EC_DIR_OUTPUT means writing to + the slave, EC_DIR_INPUT means reading from the + slave. */ + void (*state)(ec_voe_handler_t *); /**< State function */ + ec_internal_request_state_t request_state; /**< Handler state. */ + unsigned int retries; /**< retries upon datagram timeout */ + unsigned long jiffies_start; /**< Timestamp for timeout calculation. */ +}; + +/****************************************************************************/ + +int ec_voe_handler_init(ec_voe_handler_t *, ec_slave_config_t *, size_t); +void ec_voe_handler_clear(ec_voe_handler_t *); +size_t ec_voe_handler_mem_size(const ec_voe_handler_t *); + +/****************************************************************************/ + +#endif diff --git a/ubuntu/include/Kbuild b/ubuntu/include/Kbuild new file mode 100644 index 00000000000000..139597f9cb07c5 --- /dev/null +++ b/ubuntu/include/Kbuild @@ -0,0 +1,2 @@ + + diff --git a/ubuntu/include/README b/ubuntu/include/README new file mode 100644 index 00000000000000..adc8d33e6d8e8a --- /dev/null +++ b/ubuntu/include/README @@ -0,0 +1,4 @@ +Only use this directory for things which need to share their headers with +other parts of the kernel or other modules in ubuntu/ + +Otherwise, keep them local to the module directory. diff --git a/ubuntu/ubuntu-host/Kconfig b/ubuntu/ubuntu-host/Kconfig new file mode 100644 index 00000000000000..1989da68b62f54 --- /dev/null +++ b/ubuntu/ubuntu-host/Kconfig @@ -0,0 +1,5 @@ +config UBUNTU_HOST + tristate "proc dir for exporting host data to containers" + help + Creates an ubuntu-host directory in proc for providing data from + Ubuntu hosts to containers. diff --git a/ubuntu/ubuntu-host/Makefile b/ubuntu/ubuntu-host/Makefile new file mode 100644 index 00000000000000..fef3c131967606 --- /dev/null +++ b/ubuntu/ubuntu-host/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_UBUNTU_HOST) += ubuntu-host.o diff --git a/ubuntu/ubuntu-host/ubuntu-host.c b/ubuntu/ubuntu-host/ubuntu-host.c new file mode 100644 index 00000000000000..1abd402533b4da --- /dev/null +++ b/ubuntu/ubuntu-host/ubuntu-host.c @@ -0,0 +1,68 @@ +#include +#include +#include +#include +#include + +#define PROC_DIR "ubuntu-host" + +#define ESM_TOKEN_FILE "esm-token" +#define ESM_TOKEN_MAX_SIZE 64 + +static struct proc_dir_entry *proc_dir; +static char esm_token_buffer[ESM_TOKEN_MAX_SIZE]; + +static ssize_t esm_token_read(struct file *f, char __user *buf, size_t len, + loff_t *off) +{ + return simple_read_from_buffer(buf, len, off, esm_token_buffer, + strlen(esm_token_buffer)); +} + +static ssize_t esm_token_write(struct file *f, const char __user *buf, + size_t len, loff_t *off) +{ + ssize_t ret; + + if (len >= ESM_TOKEN_MAX_SIZE - 1) + return -EINVAL; + + ret = simple_write_to_buffer(esm_token_buffer, ESM_TOKEN_MAX_SIZE - 1, + off, buf, len); + if (ret >= 0) + esm_token_buffer[ret] = '\0'; + + return ret; +} + +static const struct proc_ops esm_token_fops = { + .proc_read = esm_token_read, + .proc_write = esm_token_write, +}; + +static void ubuntu_host_cleanup(void) +{ + remove_proc_entry(ESM_TOKEN_FILE, proc_dir); + proc_remove(proc_dir); +} + +static int __init ubuntu_host_init(void) +{ + proc_dir = proc_mkdir(PROC_DIR, NULL); + if (!proc_dir) { + pr_err("Failed to create ubuntu-host dir\n"); + return -ENOMEM; + } + + if (!proc_create_data(ESM_TOKEN_FILE, 0644, proc_dir, &esm_token_fops, NULL)) { + pr_err("Failed to create esm-tokan file\n"); + ubuntu_host_cleanup(); + return -ENOMEM; + } + + return 0; +} + +module_init(ubuntu_host_init); +module_exit(ubuntu_host_cleanup); +MODULE_LICENSE("GPL");