Support bitwise operations for sc_bv data types

[plotnerb]

SystemVerilog synthesis seems to fail when attempting bitwise operations on sc_bv data types. For example, if a SC_MODULE has the following signals declared:

sc_signal<sc_bv<32>> a, b, c;

and attempts to perform the following operation within a SC_METHOD:

c = a.read() & b.read();

the SystemC executable will build successfully, however the SystemVerilog synthesis will fail with the message:

error: Type is not supported : 'sc_dt::sc_bv<32>'

This is unexpected, as the ICSC documentation lists sc_bv as a supported data type. Are there restrictions to what operations are supported on sc_bv types?

[mikhailmoiseev]

Thank you for the issue found. Will check and fix it.
Practically, we are mostly using sc_uint/sc_biguint types in our designs.