feat: restore Lazy FPU stacking without assembly macros

Reintroduce the Lazy FPU stacking optimization while preserving the
reviewer-requested assembly style:

- no tx_port.h include from .S files
- no STORE/LOAD/REGBYTES abstractions
- stack offsets remain hardcoded as in the upstream RISC-V32 GNU port

The optimization records mstatus in the interrupt stack frame and
checks the FS field before saving/restoring floating point state. If
FS is Off, FP register and fcsr save/restore are skipped. If FS is
Initial/Clean/Dirty, the existing FP context path is used.

This touches only tx_thread_context_save.S and
tx_thread_context_restore.S, and credits Wei-Chen Lai in the AUTHOR
blocks for those Lazy FPU changes.

Author: Winstonllllai

ports/risc-v32/gnu/src/tx_thread_context_restore.S

@@ -29,6 +29,7 @@
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Akif Ejaz, 10xEngineers                                             */
+/*    Wei-Chen Lai, National Cheng Kung University                        */
 /*                                                                        */
 /*  DESCRIPTION                                                           */
 /*                                                                        */
@@ -82,7 +83,13 @@ _tx_thread_context_restore:
     /* Just recover the saved registers and return to the point of
        interrupt.  */
 
-    /* Recover floating point registers.  */
+    /* Recover floating point registers only if saved mstatus.FS was not Off.  */
+#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+    lw      t1, 29*4(sp)                                // Pickup saved mstatus
+    srli    t1, t1, 13
+    andi    t1, t1, 0x3
+    beqz    t1, _tx_thread_skip_fp_restore              // Skip if FS was Off
+#endif
 #if defined(__riscv_float_abi_single)
     flw     f0,  31*4(sp)                               // Recover ft0
     flw     f1,  32*4(sp)                               // Recover ft1
@@ -130,6 +137,7 @@ _tx_thread_context_restore:
     lw      t0,  63*4(sp)                               // Recover fcsr
     csrw    fcsr, t0                                    // Restore fcsr
 #endif
+_tx_thread_skip_fp_restore:
 
     /* Recover standard registers.  */
 
@@ -222,7 +230,13 @@ _tx_thread_no_preempt_restore:
 
     lw      sp, 8(t1)                                   // Switch back to thread's stack
 
-    /* Recover floating point registers.  */
+    /* Recover floating point registers only if saved mstatus.FS was not Off.  */
+#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+    lw      t3, 29*4(sp)                                // Pickup saved mstatus
+    srli    t3, t3, 13
+    andi    t3, t3, 0x3
+    beqz    t3, _tx_thread_no_preempt_skip_fp_restore   // Skip if FS was Off
+#endif
 #if defined(__riscv_float_abi_single)
     flw     f0,  31*4(sp)                               // Recover ft0
     flw     f1,  32*4(sp)                               // Recover ft1
@@ -270,6 +284,7 @@ _tx_thread_no_preempt_restore:
     lw      t0,  63*4(sp)                               // Recover fcsr
     csrw    fcsr, t0                                    // Restore fcsr
 #endif
+_tx_thread_no_preempt_skip_fp_restore:
 
     /* Recover the saved context and return to the point of interrupt.  */
 
@@ -331,7 +346,13 @@ _tx_thread_preempt_restore:
     ori     t3, zero, 1                                 // Build interrupt stack type
     sw      t3, 0(t0)                                   // Store stack type
 
-    /* Store floating point preserved registers.  */
+    /* Store floating point preserved registers only if saved mstatus.FS was not Off.  */
+#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+    lw      t3, 29*4(t0)                                // Pickup saved mstatus
+    srli    t3, t3, 13
+    andi    t3, t3, 0x3
+    beqz    t3, _tx_thread_preempt_skip_fp_restore      // Skip if FS was Off
+#endif
 #ifdef __riscv_float_abi_single
     fsw     f8,  39*4(t0)                               // Store fs0
     fsw     f9,  40*4(t0)                               // Store fs1
@@ -359,6 +380,7 @@ _tx_thread_preempt_restore:
     fsd     f26, 57*4(t0)                               // Store fs10
     fsd     f27, 58*4(t0)                               // Store fs11
 #endif
+_tx_thread_preempt_skip_fp_restore:
 
     /* Store standard preserved registers.  */
 

ports/risc-v32/gnu/src/tx_thread_context_save.S

@@ -29,6 +29,7 @@
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Akif Ejaz, 10xEngineers                                             */
+/*    Wei-Chen Lai, National Cheng Kung University                        */
 /*                                                                        */
 /*  DESCRIPTION                                                           */
 /*                                                                        */
@@ -96,6 +97,15 @@ _tx_thread_context_save:
     sw      t5, 14*4(sp)                         // Store t5
     sw      t6, 13*4(sp)                         // Store t6
 
+    /* Save mstatus and skip FP state if FS is Off.  */
+    csrr    t0, mstatus
+    sw      t0, 29*4(sp)
+#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+    srli    t1, t0, 13
+    andi    t1, t1, 0x3
+    beqz    t1, _tx_thread_skip_fpu_save
+#endif
+
     /* Save floating point registers.  */
 #if defined(__riscv_float_abi_single)
     fsw     f0,  31*4(sp)                        // Store ft0
@@ -144,14 +154,11 @@ _tx_thread_context_save:
     csrr    t0, fcsr
     sw      t0, 63*4(sp)                         // Store fcsr
 #endif
+_tx_thread_skip_fpu_save:
 
     csrr    t0, mepc
     sw      t0, 30*4(sp)                         // Save it on the stack
 
-    /* Save mstatus.  */
-    csrr    t0, mstatus
-    sw      t0, 29*4(sp)
-
     la      t1, _tx_thread_current_ptr           // Pickup address of current thread ptr
     lw      t2, 0(t1)                            // Pickup current thread pointer
     beqz    t2, _tx_thread_idle_system_save      // If NULL, idle system was interrupted
@@ -190,6 +197,15 @@ _tx_thread_nested_save:
     sw      t5, 14*4(sp)                         // Store t5
     sw      t6, 13*4(sp)                         // Store t6
 
+    /* Save mstatus and skip FP state if FS is Off.  */
+    csrr    t0, mstatus
+    sw      t0, 29*4(sp)
+#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+    srli    t1, t0, 13
+    andi    t1, t1, 0x3
+    beqz    t1, _tx_thread_skip_nested_fpu_save
+#endif
+
     /* Save floating point registers.  */
 #if defined(__riscv_float_abi_single)
     fsw     f0,  31*4(sp)                        // Store ft0
@@ -238,13 +254,11 @@ _tx_thread_nested_save:
     csrr    t0, fcsr
     sw      t0, 63*4(sp)                         // Store fcsr
 #endif
+_tx_thread_skip_nested_fpu_save:
 
     csrr    t0, mepc
     sw      t0, 30*4(sp)                         // Save it on stack
 
-    csrr    t0, mstatus
-    sw      t0, 29*4(sp)
-
     /* Call the ISR execution exit function if enabled.  */
 #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
     call    _tx_execution_isr_enter              // Call the ISR execution enter function