Add LX8 support for > 32 interrupts

Also fix inconsistent SWPRI define in interrupt handler

Author: ianstcdns

ports/xtensa/xcc/inc/xtensa_context.h

@@ -388,6 +388,10 @@ XSTRUCT_END(XtExcFrame)
 #define XT_USE_INT_WRAPPER    0
 #endif
 
+#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS > 32) && (defined XT_USE_SWPRI)
+#error "Software prioritization of interrupts (XT_USE_SWPRI) not supported for XEA2 with > 32 interrupts."
+#endif
+
 #if XCHAL_HAVE_XEA3
 #ifdef XT_USE_SWPRI
 //#warning "Software prioritization of interrupts (XT_USE_SWPRI) not supported for XEA3."

ports/xtensa/xcc/inc/xtensa_rtos.h

@@ -181,7 +181,11 @@ To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
 #define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
 
 #ifndef __ASSEMBLER__
+#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS > 32)
+typedef uint32_t (*XT_INTEXC_HOOK)(uint32_t cause, uint32_t block);
+#else
 typedef uint32_t (*XT_INTEXC_HOOK)(uint32_t cause);
+#endif
 extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
 #endif
 

ports/xtensa/xcc/inc/xtensa_timer.h

@@ -108,7 +108,19 @@ Otherwise select the first low or medium priority interrupt timer available.
 #define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
 
 #if XCHAL_HAVE_XEA2
-#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
+/*
+ * Xtensa LX8 supports up to 128 interrupts whereas LX7 supports up to 32.
+ *
+ * Redefine the legacy XT_TIMER_INTEN (which limited the interrupt number to
+ * be in the lower 32 or lower 64 bits depending on data type) as two defines
+ * describing the INTEN bit within a 32-bit component and a 4-block component, 
+ * where each block contains a group of 32 interrupt bits.
+ *
+ * Name changes are intentional such that any dependencies are caught at 
+ * compile-time and are found regardless of timer configuration.
+ */
+#define XT_TIMER_INTEN_BIT      (1 << (XT_TIMER_INTNUM & 31U))
+#define XT_TIMER_INTEN_BLK      (XT_TIMER_INTNUM >> 5)
 #endif
 
 #if XT_TIMER_INDEX == 0

ports/xtensa/xcc/readme_threadx.txt

@@ -382,7 +382,8 @@ Application Defines (preprocessor macros definable with the -D option):
                             higher bit numbers over those with lower bit
                             numbers at the same level. This works only for
                             low and medium priority interrupts that can be
-                            dispatched to C handlers.
+                            dispatched to C handlers on either NX cores or 
+                            on LX cores with 32 or fewer interrupts.
 
     TX_SYSTEM_STACK_SIZE=n  Specify the size of the interrupt stack, which
                             is the stack that all interrupt handlers switch

ports/xtensa/xcc/src/tx_clib_lock.c

@@ -66,6 +66,8 @@ TX_MUTEX  clib_lock_mutex;
 void
 __malloc_lock (struct _reent * ptr)
 {
+    (void) ptr;
+
     if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) {
         return;
     }
@@ -80,6 +82,8 @@ __malloc_lock (struct _reent * ptr)
 void
 __malloc_unlock (struct _reent * ptr)
 {
+    (void) ptr;
+
     if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) {
         return;
     }
@@ -99,6 +103,8 @@ __malloc_unlock (struct _reent * ptr)
 void
 __env_lock (struct _reent * ptr)
 {
+    (void) ptr;
+
     if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) {
         return;
     }
@@ -113,6 +119,8 @@ __env_lock (struct _reent * ptr)
 void
 __env_unlock (struct _reent * ptr)
 {
+    (void) ptr;
+
     if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) {
         return;
     }

ports/xtensa/xcc/src/tx_initialize_low_level.c

@@ -80,6 +80,8 @@ VOID   _tx_initialize_low_level(VOID)
 
     /* Disable interrupts - don't want any that interact with ThreadX yet. */
     TX_DISABLE
+    /* Suppress compiler warning about set but not used variable. */
+    (void) interrupt_save;
 
     /*
     Disable stack limit checking if present. Whatever was set up earlier

ports/xtensa/xcc/src/xtensa_context.S

@@ -131,7 +131,7 @@ _xt_context_save:
     s32i    a3,  sp, XT_STK_ATOMCTL
     #endif
 
-    #if XT_USE_SWPRI
+    #ifdef XT_USE_SWPRI
     /* Save virtual priority mask */
     movi    a3,  _xt_vpri_mask
     l32i    a3,  a3, 0
@@ -318,7 +318,7 @@ _xt_context_restore:
 
     ret
 
-#endif /* XCHAL_HAVE_XEA3 */
+#endif /* XCHAL_HAVE_XEA2 */
 
 
 /*******************************************************************************

ports/xtensa/xcc/src/xtensa_intr.c

@@ -1,5 +1,5 @@
 /*******************************************************************************
-Copyright (c) 2006-2019 Cadence Design Systems Inc.
+Copyright (c) 2006-2023 Cadence Design Systems Inc.
 
 Permission is hereby granted, free of charge, to any person obtaining
 a copy of this software and associated documentation files (the
@@ -80,7 +80,7 @@ xt_exc_handler xt_set_exception_handler(uint32_t n, xt_exc_handler f)
 
 #if XCHAL_HAVE_INTERRUPTS
 
-#if XCHAL_HAVE_XEA2
+#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32)
 /* Defined in xtensa_intr_asm.S */
 extern uint32_t _xt_intenable;
 extern uint32_t _xt_vpri_mask;
@@ -157,7 +157,7 @@ xt_handler xt_set_interrupt_handler(uint32_t n, xt_handler f, void * arg)
 */
 void xt_interrupt_enable(uint32_t intnum)
 {
-#if XCHAL_HAVE_XEA2
+#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32)
     uint32_t ps = XT_RSIL(15);
 
     // New INTENABLE = (_xt_intenable | mask) & _xt_vpri_mask.
@@ -177,7 +177,7 @@ void xt_interrupt_enable(uint32_t intnum)
 */
 void xt_interrupt_disable(uint32_t intnum)
 {
-#if XCHAL_HAVE_XEA2
+#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32)
     uint32_t ps = XT_RSIL(15);
 
     // New INTENABLE = (_xt_intenable & ~mask) & _xt_vpri_mask.

ports/xtensa/xcc/src/xtensa_intr_asm.S

@@ -45,7 +45,7 @@
 -------------------------------------------------------------------------------
 */
 
-#if XCHAL_HAVE_XEA2
+#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32)
 
     .data
     .global _xt_intdata