diff --git a/common/inc/lx_api.h b/common/inc/lx_api.h index 4d5cf11..8af0901 100644 --- a/common/inc/lx_api.h +++ b/common/inc/lx_api.h @@ -10,6 +10,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Codex (GPT-5). + /**************************************************************************/ /**************************************************************************/ @@ -537,6 +539,7 @@ typedef struct LX_NOR_FLASH_EXTENDED_CACHE_ENTRY_STRUCT ULONG *lx_nor_flash_extended_cache_entry_sector_address; ULONG *lx_nor_flash_extended_cache_entry_sector_memory; ULONG lx_nor_flash_extended_cache_entry_access_count; + UINT lx_nor_flash_extended_cache_entry_valid; } LX_NOR_FLASH_EXTENDED_CACHE_ENTRY; @@ -814,4 +817,3 @@ VOID _lx_nor_flash_system_error(LX_NOR_FLASH *nor_flash, UINT error_code); #endif #endif - diff --git a/common/src/lx_nor_flash_driver_block_erase.c b/common/src/lx_nor_flash_driver_block_erase.c index d5e4b46..c430129 100644 --- a/common/src/lx_nor_flash_driver_block_erase.c +++ b/common/src/lx_nor_flash_driver_block_erase.c @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Codex (GPT-5). + /**************************************************************************/ /**************************************************************************/ @@ -76,15 +78,19 @@ UINT status; #ifndef LX_NOR_DISABLE_EXTENDED_CACHE UINT i; -ULONG *block_start_address; -ULONG *block_end_address; +ULONG block_start_address; +ULONG block_end_address; ULONG *cache_entry_start; -ULONG *cache_entry_end; +ULONG cache_entry_start_value; +ULONG cache_entry_end_value; - /* Calculate the block starting address. */ - block_start_address = nor_flash -> lx_nor_flash_base_address + (block * nor_flash -> lx_nor_flash_words_per_block); - block_end_address = block_start_address + nor_flash -> lx_nor_flash_words_per_block; + /* Calculate the block starting address. + MISRA C:2012 Rule 11.4 deviation: NOR driver addresses may be logical + address tokens, including zero, so compare address values without + dereferencing them. */ + block_start_address = (ULONG)(nor_flash -> lx_nor_flash_base_address) + (block * nor_flash -> lx_nor_flash_words_per_block * sizeof(ULONG)); + block_end_address = block_start_address + (nor_flash -> lx_nor_flash_words_per_block * sizeof(ULONG)); /* Loop through the cache entries to see if there is a sector in cache. */ for (i = 0; i < nor_flash -> lx_nor_flash_extended_cache_entries; i++) @@ -94,15 +100,21 @@ ULONG *cache_entry_end; /* Determine the cache entry addresses. */ cache_entry_start = nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_address; - cache_entry_end = cache_entry_start + LX_NOR_SECTOR_SIZE; - /* Determine if the flash address in in the cache entry. */ - if ((cache_entry_start) && (block_start_address <= cache_entry_start) && (block_end_address > cache_entry_end)) + /* Determine if the cache entry is in the block being erased. */ + if (nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_valid) { + cache_entry_start_value = (ULONG)cache_entry_start; + cache_entry_end_value = cache_entry_start_value + (LX_NOR_SECTOR_SIZE * sizeof(ULONG)); + + if ((block_start_address <= cache_entry_start_value) && (block_end_address > cache_entry_end_value)) + { - /* Yes, this cache entry is in the block to be erased so invalidate it. */ - nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_address = LX_NULL; - nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_access_count = 0; + /* Yes, this cache entry is in the block to be erased so invalidate it. */ + nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_address = LX_NULL; + nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_access_count = 0; + nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_valid = LX_FALSE; + } } } #endif @@ -117,5 +129,3 @@ ULONG *cache_entry_end; /* Return completion status. */ return(status); } - - diff --git a/common/src/lx_nor_flash_driver_read.c b/common/src/lx_nor_flash_driver_read.c index 5a0e3d9..ce1826b 100644 --- a/common/src/lx_nor_flash_driver_read.c +++ b/common/src/lx_nor_flash_driver_read.c @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Codex (GPT-5). + /**************************************************************************/ /**************************************************************************/ @@ -76,8 +78,11 @@ UINT _lx_nor_flash_driver_read(LX_NOR_FLASH *nor_flash, ULONG *flash_address, U UINT status; UINT i; ULONG *cache_entry_start; -ULONG *cache_entry_end; +ULONG cache_entry_start_value; +ULONG cache_entry_end_value; ULONG cache_offset; +ULONG flash_address_value; +ULONG base_address_value; UINT least_used_cache_entry; @@ -91,6 +96,11 @@ UINT least_used_cache_entry; /* Initialize the least used cache entry. */ least_used_cache_entry = 0; + /* MISRA C:2012 Rule 11.4 deviation: NOR driver addresses may be logical + address tokens, including zero, so compare address values without + dereferencing them. */ + flash_address_value = (ULONG)flash_address; + do { @@ -102,52 +112,55 @@ UINT least_used_cache_entry; /* Determine the cache entry addresses. */ cache_entry_start = nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_address; - cache_entry_end = cache_entry_start + LX_NOR_SECTOR_SIZE; - /* Determine if the flash address in in the cache entry. */ - if ((cache_entry_start) && (flash_address >= cache_entry_start) && (flash_address < cache_entry_end)) + /* Determine if the flash address is in the cache entry. */ + if (nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_valid) { + cache_entry_start_value = (ULONG)cache_entry_start; + cache_entry_end_value = cache_entry_start_value + (LX_NOR_SECTOR_SIZE * sizeof(ULONG)); - /* Yes, we found the entry. */ + if ((flash_address_value >= cache_entry_start_value) && (flash_address_value < cache_entry_end_value)) + { - /* Increment the accessed count. */ - nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_access_count++; + /* Yes, we found the entry. */ - /* Calculate the offset into the cache entry. */ - cache_offset = (ULONG)(flash_address - cache_entry_start); + /* Increment the accessed count. */ + nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_access_count++; - /* Copy the word from the cache. */ - *destination = *(nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_memory + cache_offset); + /* Calculate the offset into the cache entry. */ + cache_offset = (flash_address_value - cache_entry_start_value) / sizeof(ULONG); - /* Increment the number of cache hits. */ - nor_flash -> lx_nor_flash_extended_cache_hits++; + /* Copy the word from the cache. */ + *destination = *(nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_memory + cache_offset); - /* Return success. */ - return(LX_SUCCESS); + /* Increment the number of cache hits. */ + nor_flash -> lx_nor_flash_extended_cache_hits++; + + /* Return success. */ + return(LX_SUCCESS); + } } - else + + /* Determine if we have a new least used sector. */ + if (i != least_used_cache_entry) { - /* Determine if we have a new least used sector. */ - if (i != least_used_cache_entry) + /* Determine if this entry has a smaller accessed count. */ + if (nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_access_count < + nor_flash -> lx_nor_flash_extended_cache[least_used_cache_entry].lx_nor_flash_extended_cache_entry_access_count) { - /* Determine if this entry has a smaller accessed count. */ - if (nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_access_count < - nor_flash -> lx_nor_flash_extended_cache[least_used_cache_entry].lx_nor_flash_extended_cache_entry_access_count) - { - - /* New least used entry. */ - least_used_cache_entry = i; - } + /* New least used entry. */ + least_used_cache_entry = i; } } } /* Now read in the sector into the cache. */ - cache_offset = (ULONG)(flash_address - nor_flash -> lx_nor_flash_base_address); + base_address_value = (ULONG)(nor_flash -> lx_nor_flash_base_address); + cache_offset = (flash_address_value - base_address_value) / sizeof(ULONG); cache_offset = cache_offset & ~((ULONG) (LX_NOR_SECTOR_SIZE-1)); - cache_entry_start = nor_flash -> lx_nor_flash_base_address + cache_offset; + cache_entry_start = (ULONG *)(base_address_value + (cache_offset * sizeof(ULONG))); /* Call the actual driver read function. */ #ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE @@ -171,6 +184,7 @@ UINT least_used_cache_entry; /* Setup the cache entry. */ nor_flash -> lx_nor_flash_extended_cache[least_used_cache_entry].lx_nor_flash_extended_cache_entry_sector_address = cache_entry_start; nor_flash -> lx_nor_flash_extended_cache[least_used_cache_entry].lx_nor_flash_extended_cache_entry_access_count = 0; + nor_flash -> lx_nor_flash_extended_cache[least_used_cache_entry].lx_nor_flash_extended_cache_entry_valid = LX_TRUE; /* Increment the number of cache misses. */ nor_flash -> lx_nor_flash_extended_cache_misses++; @@ -211,5 +225,3 @@ UINT status; return(status); #endif } - - diff --git a/common/src/lx_nor_flash_driver_write.c b/common/src/lx_nor_flash_driver_write.c index ac25d27..ea38c58 100644 --- a/common/src/lx_nor_flash_driver_write.c +++ b/common/src/lx_nor_flash_driver_write.c @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Codex (GPT-5). + /**************************************************************************/ /**************************************************************************/ @@ -77,8 +79,10 @@ UINT _lx_nor_flash_driver_write(LX_NOR_FLASH *nor_flash, ULONG *flash_address, UINT status; UINT i; ULONG *cache_entry_start; -ULONG *cache_entry_end; +ULONG cache_entry_start_value; +ULONG cache_entry_end_value; ULONG cache_offset; +ULONG flash_address_value; /* Is the request a whole sector or a partial sector. */ @@ -87,6 +91,11 @@ ULONG cache_offset; /* One word request, which implies that it is a NOR flash metadata write. */ + /* MISRA C:2012 Rule 11.4 deviation: NOR driver addresses may be logical + address tokens, including zero, so compare address values without + dereferencing them. */ + flash_address_value = (ULONG)flash_address; + /* Loop through the cache entries to see if there is a sector in cache. */ for (i = 0; i < nor_flash -> lx_nor_flash_extended_cache_entries; i++) { @@ -95,22 +104,27 @@ ULONG cache_offset; /* Determine the cache entry addresses. */ cache_entry_start = nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_address; - cache_entry_end = cache_entry_start + LX_NOR_SECTOR_SIZE; - /* Determine if the flash address in in the cache entry. */ - if ((cache_entry_start) && (flash_address >= cache_entry_start) && (flash_address < cache_entry_end)) + /* Determine if the flash address is in the cache entry. */ + if (nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_valid) { + cache_entry_start_value = (ULONG)cache_entry_start; + cache_entry_end_value = cache_entry_start_value + (LX_NOR_SECTOR_SIZE * sizeof(ULONG)); - /* Yes, we found the entry. */ + if ((flash_address_value >= cache_entry_start_value) && (flash_address_value < cache_entry_end_value)) + { - /* Calculate the offset into the cache entry. */ - cache_offset = (ULONG)(flash_address - cache_entry_start); + /* Yes, we found the entry. */ - /* Copy the word into the cache. */ - *(nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_memory + cache_offset) = *source; + /* Calculate the offset into the cache entry. */ + cache_offset = (flash_address_value - cache_entry_start_value) / sizeof(ULONG); - /* Get out of the loop. */ - break; + /* Copy the word into the cache. */ + *(nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_memory + cache_offset) = *source; + + /* Get out of the loop. */ + break; + } } } } @@ -140,4 +154,3 @@ UINT status; return(status); #endif } - diff --git a/common/src/lx_nor_flash_extended_cache_enable.c b/common/src/lx_nor_flash_extended_cache_enable.c index 7bd2863..a1cc5f4 100644 --- a/common/src/lx_nor_flash_extended_cache_enable.c +++ b/common/src/lx_nor_flash_extended_cache_enable.c @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Codex (GPT-5). + /**************************************************************************/ /**************************************************************************/ @@ -276,6 +278,7 @@ ULONG block_word; nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_address = LX_NULL; nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_sector_memory = cache_memory; nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_access_count = 0; + nor_flash -> lx_nor_flash_extended_cache[i].lx_nor_flash_extended_cache_entry_valid = LX_FALSE; /* Move the cache memory forward. */ cache_memory = cache_memory + LX_NOR_SECTOR_SIZE; @@ -318,4 +321,3 @@ ULONG block_word; #endif } - diff --git a/test/regression/levelx_nor_flash_test_cache.c b/test/regression/levelx_nor_flash_test_cache.c index d0b24d0..b39ab41 100644 --- a/test/regression/levelx_nor_flash_test_cache.c +++ b/test/regression/levelx_nor_flash_test_cache.c @@ -9,6 +9,8 @@ /* SPDX-License-Identifier: MIT */ /***************************************************************************/ +// Some portions generated by Codex (GPT-5). + /* Basic NOR flash tests... */ #include @@ -31,11 +33,30 @@ ULONG readbuffer[128]; UCHAR nor_cache_memory[2048+16+8]; UCHAR nor_cache_memory2[8192]; +#ifndef LX_NOR_DISABLE_EXTENDED_CACHE +UCHAR nor_zero_base_cache_memory[512]; +ULONG nor_zero_base_memory[LX_NOR_SECTOR_SIZE * 2]; +ULONG nor_zero_base_driver_read_count; +#endif /* Define LevelX NOR flash simulator prototoypes. */ UINT _lx_nor_flash_simulator_initialize(LX_NOR_FLASH *nor_flash); +#ifndef LX_NOR_DISABLE_EXTENDED_CACHE +#ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE +static UINT zero_base_nor_read(LX_NOR_FLASH *nor_flash, ULONG *flash_address, ULONG *destination, ULONG words); +static UINT zero_base_nor_write(LX_NOR_FLASH *nor_flash, ULONG *flash_address, ULONG *source, ULONG words); +static UINT zero_base_nor_block_erase(LX_NOR_FLASH *nor_flash, ULONG block, ULONG erase_count); +static UINT zero_base_nor_block_erased_verify(LX_NOR_FLASH *nor_flash, ULONG block); +#else +static UINT zero_base_nor_read(ULONG *flash_address, ULONG *destination, ULONG words); +static UINT zero_base_nor_write(ULONG *flash_address, ULONG *source, ULONG words); +static UINT zero_base_nor_block_erase(ULONG block, ULONG erase_count); +static UINT zero_base_nor_block_erased_verify(ULONG block); +#endif +static UINT zero_base_nor_initialize(LX_NOR_FLASH *nor_flash); +#endif @@ -73,12 +94,176 @@ void tx_application_define(void *first_unused_memory) } #endif +#ifndef LX_NOR_DISABLE_EXTENDED_CACHE +static UINT zero_base_nor_initialize(LX_NOR_FLASH *nor_flash) +{ + +UINT status; + + + /* Setup the base address as a logical zero offset. */ + nor_flash -> lx_nor_flash_base_address = LX_NULL; + + /* Setup geometry of the test flash. */ + nor_flash -> lx_nor_flash_total_blocks = 1; + nor_flash -> lx_nor_flash_words_per_block = LX_NOR_SECTOR_SIZE * 2; + + /* Setup function pointers for the NOR flash services. */ + nor_flash -> lx_nor_flash_driver_read = zero_base_nor_read; + nor_flash -> lx_nor_flash_driver_write = zero_base_nor_write; + nor_flash -> lx_nor_flash_driver_block_erase = zero_base_nor_block_erase; + nor_flash -> lx_nor_flash_driver_block_erased_verify = zero_base_nor_block_erased_verify; + + /* Setup local buffer for NOR flash operation. */ + nor_flash -> lx_nor_flash_sector_buffer = buffer; + + /* Erase the test flash. */ +#ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE + status = zero_base_nor_block_erase(nor_flash, 0, 0); +#else + status = zero_base_nor_block_erase(0, 0); +#endif + + /* Return completion status. */ + return(status); +} + +#ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE +static UINT zero_base_nor_read(LX_NOR_FLASH *nor_flash, ULONG *flash_address, ULONG *destination, ULONG words) +#else +static UINT zero_base_nor_read(ULONG *flash_address, ULONG *destination, ULONG words) +#endif +{ + +ULONG offset; + +#ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE + LX_PARAMETER_NOT_USED(nor_flash); +#endif + + /* MISRA C:2012 Rule 11.4 deviation: this test driver intentionally treats + NOR flash addresses as logical offsets, including zero. */ + offset = ((ULONG)flash_address) / sizeof(ULONG); + + if ((offset + words) > (LX_NOR_SECTOR_SIZE * 2)) + { + return(LX_ERROR); + } + + nor_zero_base_driver_read_count++; + + while (words--) + { + *destination++ = nor_zero_base_memory[offset++]; + } + + return(LX_SUCCESS); +} + +#ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE +static UINT zero_base_nor_write(LX_NOR_FLASH *nor_flash, ULONG *flash_address, ULONG *source, ULONG words) +#else +static UINT zero_base_nor_write(ULONG *flash_address, ULONG *source, ULONG words) +#endif +{ + +ULONG offset; + +#ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE + LX_PARAMETER_NOT_USED(nor_flash); +#endif + + /* MISRA C:2012 Rule 11.4 deviation: this test driver intentionally treats + NOR flash addresses as logical offsets, including zero. */ + offset = ((ULONG)flash_address) / sizeof(ULONG); + + if ((offset + words) > (LX_NOR_SECTOR_SIZE * 2)) + { + return(LX_ERROR); + } + + while (words--) + { + nor_zero_base_memory[offset++] = *source++; + } + + return(LX_SUCCESS); +} + +#ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE +static UINT zero_base_nor_block_erase(LX_NOR_FLASH *nor_flash, ULONG block, ULONG erase_count) +#else +static UINT zero_base_nor_block_erase(ULONG block, ULONG erase_count) +#endif +{ + +ULONG offset; +ULONG words; + +#ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE + LX_PARAMETER_NOT_USED(nor_flash); +#endif + LX_PARAMETER_NOT_USED(erase_count); + + if (block != 0) + { + return(LX_ERROR); + } + + offset = 0; + words = LX_NOR_SECTOR_SIZE * 2; + + while (words--) + { + nor_zero_base_memory[offset++] = LX_ALL_ONES; + } + + return(LX_SUCCESS); +} + +#ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE +static UINT zero_base_nor_block_erased_verify(LX_NOR_FLASH *nor_flash, ULONG block) +#else +static UINT zero_base_nor_block_erased_verify(ULONG block) +#endif +{ + +ULONG offset; +ULONG words; + +#ifdef LX_NOR_ENABLE_CONTROL_BLOCK_FOR_DRIVER_INTERFACE + LX_PARAMETER_NOT_USED(nor_flash); +#endif + + if (block != 0) + { + return(LX_ERROR); + } + + offset = 0; + words = LX_NOR_SECTOR_SIZE * 2; + + while (words--) + { + if (nor_zero_base_memory[offset++] != LX_ALL_ONES) + { + return(LX_ERROR); + } + } + + return(LX_SUCCESS); +} +#endif + /* Define the test threads. */ void thread_0_entry(ULONG thread_input) { ULONG i, j, sector; +#ifndef LX_NOR_DISABLE_EXTENDED_CACHE +ULONG read_count; +#endif UINT status; ULONG *word_ptr; @@ -87,6 +272,98 @@ ULONG *word_ptr; /* Initialize LevelX. */ _lx_nor_flash_initialize(); +#ifndef LX_NOR_DISABLE_EXTENDED_CACHE + /* Test 0: Extended cache with a zero NOR flash base address. */ + printf("Test 0: Extended cache with zero base address...."); + + LX_MEMSET(&nor_sim_flash, 0, sizeof(nor_sim_flash)); + status = zero_base_nor_initialize(&nor_sim_flash); + nor_zero_base_memory[0] = 0x12345678; + nor_zero_base_driver_read_count = 0; + + if (status == LX_SUCCESS) + { + status = lx_nor_flash_extended_cache_enable(&nor_sim_flash, nor_zero_base_cache_memory, sizeof(nor_zero_base_cache_memory)); + } + + if (status == LX_SUCCESS) + { + status = _lx_nor_flash_driver_read(&nor_sim_flash, LX_NULL, readbuffer, 1); + } + + if ((status != LX_SUCCESS) || (readbuffer[0] != 0x12345678) || (nor_zero_base_driver_read_count != 1)) + { + printf("FAILED!\n"); +#ifdef BATCH_TEST + exit(1); +#endif + while(1) + { + } + } + + status = _lx_nor_flash_driver_read(&nor_sim_flash, LX_NULL, readbuffer, 1); + + if ((status != LX_SUCCESS) || (readbuffer[0] != 0x12345678) || (nor_zero_base_driver_read_count != 1)) + { + printf("FAILED!\n"); +#ifdef BATCH_TEST + exit(1); +#endif + while(1) + { + } + } + + buffer[0] = 0x87654321; + status = _lx_nor_flash_driver_write(&nor_sim_flash, LX_NULL, buffer, 1); + + if ((status != LX_SUCCESS) || (nor_zero_base_memory[0] != 0x87654321)) + { + printf("FAILED!\n"); +#ifdef BATCH_TEST + exit(1); +#endif + while(1) + { + } + } + + status = _lx_nor_flash_driver_read(&nor_sim_flash, LX_NULL, readbuffer, 1); + + if ((status != LX_SUCCESS) || (readbuffer[0] != 0x87654321) || (nor_zero_base_driver_read_count != 1)) + { + printf("FAILED!\n"); +#ifdef BATCH_TEST + exit(1); +#endif + while(1) + { + } + } + + read_count = nor_zero_base_driver_read_count; + status = _lx_nor_flash_driver_block_erase(&nor_sim_flash, 0, 0); + + if (status == LX_SUCCESS) + { + status = _lx_nor_flash_driver_read(&nor_sim_flash, LX_NULL, readbuffer, 1); + } + + if ((status != LX_SUCCESS) || (readbuffer[0] != LX_ALL_ONES) || (nor_zero_base_driver_read_count != (read_count + 1))) + { + printf("FAILED!\n"); +#ifdef BATCH_TEST + exit(1); +#endif + while(1) + { + } + } + + printf("SUCCESS!\n"); +#endif + /* Test 1: Simple write 100 sectors and read 100 sectors. */ printf("Test 1: Simple write-read 100 sectors..........."); @@ -1668,5 +1945,3 @@ status += lx_nor_flash_extended_cache_enable(&nor_sim_flash, nor_cache_memory2, { } } - -