diff --git a/tests/disas/winch/aarch64/v128_ops/f32x4_eq.wat b/tests/disas/winch/aarch64/v128_ops/f32x4_eq.wat new file mode 100644 index 000000000000..05bc1578cf85 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f32x4_eq.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f32x4.eq + (v128.const f32x4 1.5 nan -0x0p0 100) + (v128.const f32x4 1.5 2 0 -3))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmeq v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0xc0, 0x3f +;; 84: .byte 0x00, 0x00, 0x00, 0x40 +;; 88: udf #0 +;; 8c: mov za0h.h[w12, 0], p0/m, z0.h +;; 90: .byte 0x00, 0x00, 0xc0, 0x3f +;; 94: .byte 0x00, 0x00, 0xc0, 0x7f +;; 98: .byte 0x00, 0x00, 0x00, 0x80 +;; 9c: .byte 0x00, 0x00, 0xc8, 0x42 diff --git a/tests/disas/winch/aarch64/v128_ops/f32x4_ge.wat b/tests/disas/winch/aarch64/v128_ops/f32x4_ge.wat new file mode 100644 index 000000000000..d92a0bbbc2d8 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f32x4_ge.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f32x4.ge + (v128.const f32x4 1.5 nan -0x0p0 100) + (v128.const f32x4 1.5 2 0 -3))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmge v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0xc0, 0x3f +;; 84: .byte 0x00, 0x00, 0x00, 0x40 +;; 88: udf #0 +;; 8c: mov za0h.h[w12, 0], p0/m, z0.h +;; 90: .byte 0x00, 0x00, 0xc0, 0x3f +;; 94: .byte 0x00, 0x00, 0xc0, 0x7f +;; 98: .byte 0x00, 0x00, 0x00, 0x80 +;; 9c: .byte 0x00, 0x00, 0xc8, 0x42 diff --git a/tests/disas/winch/aarch64/v128_ops/f32x4_gt.wat b/tests/disas/winch/aarch64/v128_ops/f32x4_gt.wat new file mode 100644 index 000000000000..d4a3d19d9947 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f32x4_gt.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f32x4.gt + (v128.const f32x4 1.5 nan -0x0p0 100) + (v128.const f32x4 1.5 2 0 -3))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmgt v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0xc0, 0x3f +;; 84: .byte 0x00, 0x00, 0x00, 0x40 +;; 88: udf #0 +;; 8c: mov za0h.h[w12, 0], p0/m, z0.h +;; 90: .byte 0x00, 0x00, 0xc0, 0x3f +;; 94: .byte 0x00, 0x00, 0xc0, 0x7f +;; 98: .byte 0x00, 0x00, 0x00, 0x80 +;; 9c: .byte 0x00, 0x00, 0xc8, 0x42 diff --git a/tests/disas/winch/aarch64/v128_ops/f32x4_le.wat b/tests/disas/winch/aarch64/v128_ops/f32x4_le.wat new file mode 100644 index 000000000000..3c4e0d8d02d5 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f32x4_le.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f32x4.le + (v128.const f32x4 1.5 nan -0x0p0 100) + (v128.const f32x4 1.5 2 0 -3))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmge v1.4s, v0.4s, v1.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0xc0, 0x3f +;; 84: .byte 0x00, 0x00, 0x00, 0x40 +;; 88: udf #0 +;; 8c: mov za0h.h[w12, 0], p0/m, z0.h +;; 90: .byte 0x00, 0x00, 0xc0, 0x3f +;; 94: .byte 0x00, 0x00, 0xc0, 0x7f +;; 98: .byte 0x00, 0x00, 0x00, 0x80 +;; 9c: .byte 0x00, 0x00, 0xc8, 0x42 diff --git a/tests/disas/winch/aarch64/v128_ops/f32x4_lt.wat b/tests/disas/winch/aarch64/v128_ops/f32x4_lt.wat new file mode 100644 index 000000000000..aef9591fc5d6 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f32x4_lt.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f32x4.lt + (v128.const f32x4 1.5 nan -0x0p0 100) + (v128.const f32x4 1.5 2 0 -3))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmgt v1.4s, v0.4s, v1.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0xc0, 0x3f +;; 84: .byte 0x00, 0x00, 0x00, 0x40 +;; 88: udf #0 +;; 8c: mov za0h.h[w12, 0], p0/m, z0.h +;; 90: .byte 0x00, 0x00, 0xc0, 0x3f +;; 94: .byte 0x00, 0x00, 0xc0, 0x7f +;; 98: .byte 0x00, 0x00, 0x00, 0x80 +;; 9c: .byte 0x00, 0x00, 0xc8, 0x42 diff --git a/tests/disas/winch/aarch64/v128_ops/f32x4_ne.wat b/tests/disas/winch/aarch64/v128_ops/f32x4_ne.wat new file mode 100644 index 000000000000..2b3d221fbf85 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f32x4_ne.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f32x4.ne + (v128.const f32x4 1.5 nan -0x0p0 100) + (v128.const f32x4 1.5 2 0 -3))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x78 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmeq v1.4s, v1.4s, v0.4s +;; mvn v1.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 78: udf #0xc11f +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0xc0, 0x3f +;; 84: .byte 0x00, 0x00, 0x00, 0x40 +;; 88: udf #0 +;; 8c: mov za0h.h[w12, 0], p0/m, z0.h +;; 90: .byte 0x00, 0x00, 0xc0, 0x3f +;; 94: .byte 0x00, 0x00, 0xc0, 0x7f +;; 98: .byte 0x00, 0x00, 0x00, 0x80 +;; 9c: .byte 0x00, 0x00, 0xc8, 0x42 diff --git a/tests/disas/winch/aarch64/v128_ops/f64x2_eq.wat b/tests/disas/winch/aarch64/v128_ops/f64x2_eq.wat new file mode 100644 index 000000000000..fb66f63551f8 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f64x2_eq.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f64x2.eq + (v128.const f64x2 nan 2.5) + (v128.const f64x2 1 2.5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmeq v1.2d, v1.2d, v0.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #0 +;; 84: .byte 0x00, 0x00, 0xf0, 0x3f +;; 88: udf #0 +;; 8c: .byte 0x00, 0x00, 0x04, 0x40 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0xf8, 0x7f +;; 98: udf #0 +;; 9c: .byte 0x00, 0x00, 0x04, 0x40 diff --git a/tests/disas/winch/aarch64/v128_ops/f64x2_ge.wat b/tests/disas/winch/aarch64/v128_ops/f64x2_ge.wat new file mode 100644 index 000000000000..36fd342f1b41 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f64x2_ge.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f64x2.ge + (v128.const f64x2 nan 2.5) + (v128.const f64x2 1 2.5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmge v1.2d, v1.2d, v0.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #0 +;; 84: .byte 0x00, 0x00, 0xf0, 0x3f +;; 88: udf #0 +;; 8c: .byte 0x00, 0x00, 0x04, 0x40 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0xf8, 0x7f +;; 98: udf #0 +;; 9c: .byte 0x00, 0x00, 0x04, 0x40 diff --git a/tests/disas/winch/aarch64/v128_ops/f64x2_gt.wat b/tests/disas/winch/aarch64/v128_ops/f64x2_gt.wat new file mode 100644 index 000000000000..1f16afa1da24 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f64x2_gt.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f64x2.gt + (v128.const f64x2 nan 2.5) + (v128.const f64x2 1 2.5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmgt v1.2d, v1.2d, v0.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #0 +;; 84: .byte 0x00, 0x00, 0xf0, 0x3f +;; 88: udf #0 +;; 8c: .byte 0x00, 0x00, 0x04, 0x40 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0xf8, 0x7f +;; 98: udf #0 +;; 9c: .byte 0x00, 0x00, 0x04, 0x40 diff --git a/tests/disas/winch/aarch64/v128_ops/f64x2_le.wat b/tests/disas/winch/aarch64/v128_ops/f64x2_le.wat new file mode 100644 index 000000000000..f9024b52067f --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f64x2_le.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f64x2.le + (v128.const f64x2 nan 2.5) + (v128.const f64x2 1 2.5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmge v1.2d, v0.2d, v1.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #0 +;; 84: .byte 0x00, 0x00, 0xf0, 0x3f +;; 88: udf #0 +;; 8c: .byte 0x00, 0x00, 0x04, 0x40 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0xf8, 0x7f +;; 98: udf #0 +;; 9c: .byte 0x00, 0x00, 0x04, 0x40 diff --git a/tests/disas/winch/aarch64/v128_ops/f64x2_lt.wat b/tests/disas/winch/aarch64/v128_ops/f64x2_lt.wat new file mode 100644 index 000000000000..8fca9d698ab5 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f64x2_lt.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f64x2.lt + (v128.const f64x2 nan 2.5) + (v128.const f64x2 1 2.5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmgt v1.2d, v0.2d, v1.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #0 +;; 84: .byte 0x00, 0x00, 0xf0, 0x3f +;; 88: udf #0 +;; 8c: .byte 0x00, 0x00, 0x04, 0x40 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0xf8, 0x7f +;; 98: udf #0 +;; 9c: .byte 0x00, 0x00, 0x04, 0x40 diff --git a/tests/disas/winch/aarch64/v128_ops/f64x2_ne.wat b/tests/disas/winch/aarch64/v128_ops/f64x2_ne.wat new file mode 100644 index 000000000000..abba0d9a824c --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f64x2_ne.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f64x2.ne + (v128.const f64x2 nan 2.5) + (v128.const f64x2 1 2.5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x78 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fcmeq v1.2d, v1.2d, v0.2d +;; mvn v1.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 78: udf #0xc11f +;; 7c: udf #0 +;; 80: udf #0 +;; 84: .byte 0x00, 0x00, 0xf0, 0x3f +;; 88: udf #0 +;; 8c: .byte 0x00, 0x00, 0x04, 0x40 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0xf8, 0x7f +;; 98: udf #0 +;; 9c: .byte 0x00, 0x00, 0x04, 0x40 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_eq.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_eq.wat new file mode 100644 index 000000000000..4b0f5f9a2778 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_eq.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.eq + (v128.const i16x8 32768 1 65535 5 1000 2000 7 0) + (v128.const i16x8 32767 1 0 9 1000 1999 8 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmeq v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0x7f, 0x01, 0x00 +;; 84: .byte 0x00, 0x00, 0x09, 0x00 +;; 88: .byte 0xe8, 0x03, 0xcf, 0x07 +;; 8c: .byte 0x08, 0x00, 0xff, 0xff +;; 90: .byte 0x00, 0x80, 0x01, 0x00 +;; 94: .byte 0xff, 0xff, 0x05, 0x00 +;; 98: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_ge_s.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_ge_s.wat new file mode 100644 index 000000000000..92da9d797e5b --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_ge_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.ge_s + (v128.const i16x8 32768 1 65535 5 1000 2000 7 0) + (v128.const i16x8 32767 1 0 9 1000 1999 8 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmge v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0x7f, 0x01, 0x00 +;; 84: .byte 0x00, 0x00, 0x09, 0x00 +;; 88: .byte 0xe8, 0x03, 0xcf, 0x07 +;; 8c: .byte 0x08, 0x00, 0xff, 0xff +;; 90: .byte 0x00, 0x80, 0x01, 0x00 +;; 94: .byte 0xff, 0xff, 0x05, 0x00 +;; 98: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_ge_u.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_ge_u.wat new file mode 100644 index 000000000000..b601f321ee0b --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_ge_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.ge_u + (v128.const i16x8 32768 1 65535 5 1000 2000 7 0) + (v128.const i16x8 32767 1 0 9 1000 1999 8 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhs v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0x7f, 0x01, 0x00 +;; 84: .byte 0x00, 0x00, 0x09, 0x00 +;; 88: .byte 0xe8, 0x03, 0xcf, 0x07 +;; 8c: .byte 0x08, 0x00, 0xff, 0xff +;; 90: .byte 0x00, 0x80, 0x01, 0x00 +;; 94: .byte 0xff, 0xff, 0x05, 0x00 +;; 98: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_gt_s.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_gt_s.wat new file mode 100644 index 000000000000..1f2b49ab60d0 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_gt_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.gt_s + (v128.const i16x8 32768 1 65535 5 1000 2000 7 0) + (v128.const i16x8 32767 1 0 9 1000 1999 8 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmgt v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0x7f, 0x01, 0x00 +;; 84: .byte 0x00, 0x00, 0x09, 0x00 +;; 88: .byte 0xe8, 0x03, 0xcf, 0x07 +;; 8c: .byte 0x08, 0x00, 0xff, 0xff +;; 90: .byte 0x00, 0x80, 0x01, 0x00 +;; 94: .byte 0xff, 0xff, 0x05, 0x00 +;; 98: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_gt_u.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_gt_u.wat new file mode 100644 index 000000000000..bf23894a8ebe --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_gt_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.gt_u + (v128.const i16x8 32768 1 65535 5 1000 2000 7 0) + (v128.const i16x8 32767 1 0 9 1000 1999 8 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhi v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0x7f, 0x01, 0x00 +;; 84: .byte 0x00, 0x00, 0x09, 0x00 +;; 88: .byte 0xe8, 0x03, 0xcf, 0x07 +;; 8c: .byte 0x08, 0x00, 0xff, 0xff +;; 90: .byte 0x00, 0x80, 0x01, 0x00 +;; 94: .byte 0xff, 0xff, 0x05, 0x00 +;; 98: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_le_s.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_le_s.wat new file mode 100644 index 000000000000..8059950423fe --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_le_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.le_s + (v128.const i16x8 32768 1 65535 5 1000 2000 7 0) + (v128.const i16x8 32767 1 0 9 1000 1999 8 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmge v1.8h, v0.8h, v1.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0x7f, 0x01, 0x00 +;; 84: .byte 0x00, 0x00, 0x09, 0x00 +;; 88: .byte 0xe8, 0x03, 0xcf, 0x07 +;; 8c: .byte 0x08, 0x00, 0xff, 0xff +;; 90: .byte 0x00, 0x80, 0x01, 0x00 +;; 94: .byte 0xff, 0xff, 0x05, 0x00 +;; 98: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_le_u.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_le_u.wat new file mode 100644 index 000000000000..bc23c1fca66f --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_le_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.le_u + (v128.const i16x8 32768 1 65535 5 1000 2000 7 0) + (v128.const i16x8 32767 1 0 9 1000 1999 8 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhs v1.8h, v0.8h, v1.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0x7f, 0x01, 0x00 +;; 84: .byte 0x00, 0x00, 0x09, 0x00 +;; 88: .byte 0xe8, 0x03, 0xcf, 0x07 +;; 8c: .byte 0x08, 0x00, 0xff, 0xff +;; 90: .byte 0x00, 0x80, 0x01, 0x00 +;; 94: .byte 0xff, 0xff, 0x05, 0x00 +;; 98: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_lt_s.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_lt_s.wat new file mode 100644 index 000000000000..6d7b031aadcc --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_lt_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.lt_s + (v128.const i16x8 32768 1 65535 5 1000 2000 7 0) + (v128.const i16x8 32767 1 0 9 1000 1999 8 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmgt v1.8h, v0.8h, v1.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0x7f, 0x01, 0x00 +;; 84: .byte 0x00, 0x00, 0x09, 0x00 +;; 88: .byte 0xe8, 0x03, 0xcf, 0x07 +;; 8c: .byte 0x08, 0x00, 0xff, 0xff +;; 90: .byte 0x00, 0x80, 0x01, 0x00 +;; 94: .byte 0xff, 0xff, 0x05, 0x00 +;; 98: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_lt_u.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_lt_u.wat new file mode 100644 index 000000000000..9970975de039 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_lt_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.lt_u + (v128.const i16x8 32768 1 65535 5 1000 2000 7 0) + (v128.const i16x8 32767 1 0 9 1000 1999 8 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhi v1.8h, v0.8h, v1.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0x7f, 0x01, 0x00 +;; 84: .byte 0x00, 0x00, 0x09, 0x00 +;; 88: .byte 0xe8, 0x03, 0xcf, 0x07 +;; 8c: .byte 0x08, 0x00, 0xff, 0xff +;; 90: .byte 0x00, 0x80, 0x01, 0x00 +;; 94: .byte 0xff, 0xff, 0x05, 0x00 +;; 98: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_ne.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_ne.wat new file mode 100644 index 000000000000..11508883703b --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_ne.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.ne + (v128.const i16x8 32768 1 65535 5 1000 2000 7 0) + (v128.const i16x8 32767 1 0 9 1000 1999 8 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x78 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmeq v1.8h, v1.8h, v0.8h +;; mvn v1.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 78: udf #0xc11f +;; 7c: udf #0 +;; 80: .byte 0xff, 0x7f, 0x01, 0x00 +;; 84: .byte 0x00, 0x00, 0x09, 0x00 +;; 88: .byte 0xe8, 0x03, 0xcf, 0x07 +;; 8c: .byte 0x08, 0x00, 0xff, 0xff +;; 90: .byte 0x00, 0x80, 0x01, 0x00 +;; 94: .byte 0xff, 0xff, 0x05, 0x00 +;; 98: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_eq.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_eq.wat new file mode 100644 index 000000000000..63e701493c8f --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_eq.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.eq + (v128.const i32x4 0x80000000 1 0xFFFFFFFF 7) + (v128.const i32x4 0x7FFFFFFF 1 0 7))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmeq v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0xff, 0xff, 0x7f +;; 84: udf #1 +;; 88: udf #0 +;; 8c: udf #7 +;; 90: .byte 0x00, 0x00, 0x00, 0x80 +;; 94: udf #1 +;; 98: .byte 0xff, 0xff, 0xff, 0xff +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_ge_s.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_ge_s.wat new file mode 100644 index 000000000000..202324d025f4 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_ge_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.ge_s + (v128.const i32x4 0x80000000 1 0xFFFFFFFF 7) + (v128.const i32x4 0x7FFFFFFF 1 0 7))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmge v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0xff, 0xff, 0x7f +;; 84: udf #1 +;; 88: udf #0 +;; 8c: udf #7 +;; 90: .byte 0x00, 0x00, 0x00, 0x80 +;; 94: udf #1 +;; 98: .byte 0xff, 0xff, 0xff, 0xff +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_ge_u.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_ge_u.wat new file mode 100644 index 000000000000..353656d921ed --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_ge_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.ge_u + (v128.const i32x4 0x80000000 1 0xFFFFFFFF 7) + (v128.const i32x4 0x7FFFFFFF 1 0 7))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhs v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0xff, 0xff, 0x7f +;; 84: udf #1 +;; 88: udf #0 +;; 8c: udf #7 +;; 90: .byte 0x00, 0x00, 0x00, 0x80 +;; 94: udf #1 +;; 98: .byte 0xff, 0xff, 0xff, 0xff +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_gt_s.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_gt_s.wat new file mode 100644 index 000000000000..a302590082ae --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_gt_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.gt_s + (v128.const i32x4 0x80000000 1 0xFFFFFFFF 7) + (v128.const i32x4 0x7FFFFFFF 1 0 7))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmgt v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0xff, 0xff, 0x7f +;; 84: udf #1 +;; 88: udf #0 +;; 8c: udf #7 +;; 90: .byte 0x00, 0x00, 0x00, 0x80 +;; 94: udf #1 +;; 98: .byte 0xff, 0xff, 0xff, 0xff +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_gt_u.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_gt_u.wat new file mode 100644 index 000000000000..a8925cba0d75 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_gt_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.gt_u + (v128.const i32x4 0x80000000 1 0xFFFFFFFF 7) + (v128.const i32x4 0x7FFFFFFF 1 0 7))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhi v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0xff, 0xff, 0x7f +;; 84: udf #1 +;; 88: udf #0 +;; 8c: udf #7 +;; 90: .byte 0x00, 0x00, 0x00, 0x80 +;; 94: udf #1 +;; 98: .byte 0xff, 0xff, 0xff, 0xff +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_le_s.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_le_s.wat new file mode 100644 index 000000000000..0f91a75707a5 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_le_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.le_s + (v128.const i32x4 0x80000000 1 0xFFFFFFFF 7) + (v128.const i32x4 0x7FFFFFFF 1 0 7))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmge v1.4s, v0.4s, v1.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0xff, 0xff, 0x7f +;; 84: udf #1 +;; 88: udf #0 +;; 8c: udf #7 +;; 90: .byte 0x00, 0x00, 0x00, 0x80 +;; 94: udf #1 +;; 98: .byte 0xff, 0xff, 0xff, 0xff +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_le_u.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_le_u.wat new file mode 100644 index 000000000000..02ea873e73b5 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_le_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.le_u + (v128.const i32x4 0x80000000 1 0xFFFFFFFF 7) + (v128.const i32x4 0x7FFFFFFF 1 0 7))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhs v1.4s, v0.4s, v1.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0xff, 0xff, 0x7f +;; 84: udf #1 +;; 88: udf #0 +;; 8c: udf #7 +;; 90: .byte 0x00, 0x00, 0x00, 0x80 +;; 94: udf #1 +;; 98: .byte 0xff, 0xff, 0xff, 0xff +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_lt_s.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_lt_s.wat new file mode 100644 index 000000000000..3a12e43018ea --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_lt_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.lt_s + (v128.const i32x4 0x80000000 1 0xFFFFFFFF 7) + (v128.const i32x4 0x7FFFFFFF 1 0 7))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmgt v1.4s, v0.4s, v1.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0xff, 0xff, 0x7f +;; 84: udf #1 +;; 88: udf #0 +;; 8c: udf #7 +;; 90: .byte 0x00, 0x00, 0x00, 0x80 +;; 94: udf #1 +;; 98: .byte 0xff, 0xff, 0xff, 0xff +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_lt_u.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_lt_u.wat new file mode 100644 index 000000000000..1df397c0cda3 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_lt_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.lt_u + (v128.const i32x4 0x80000000 1 0xFFFFFFFF 7) + (v128.const i32x4 0x7FFFFFFF 1 0 7))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhi v1.4s, v0.4s, v1.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0xff, 0xff, 0xff, 0x7f +;; 84: udf #1 +;; 88: udf #0 +;; 8c: udf #7 +;; 90: .byte 0x00, 0x00, 0x00, 0x80 +;; 94: udf #1 +;; 98: .byte 0xff, 0xff, 0xff, 0xff +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_ne.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_ne.wat new file mode 100644 index 000000000000..e320bf73a8ac --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_ne.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.ne + (v128.const i32x4 0x80000000 1 0xFFFFFFFF 7) + (v128.const i32x4 0x7FFFFFFF 1 0 7))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x78 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmeq v1.4s, v1.4s, v0.4s +;; mvn v1.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 78: udf #0xc11f +;; 7c: udf #0 +;; 80: .byte 0xff, 0xff, 0xff, 0x7f +;; 84: udf #1 +;; 88: udf #0 +;; 8c: udf #7 +;; 90: .byte 0x00, 0x00, 0x00, 0x80 +;; 94: udf #1 +;; 98: .byte 0xff, 0xff, 0xff, 0xff +;; 9c: udf #7 diff --git a/tests/disas/winch/aarch64/v128_ops/i64x2_eq.wat b/tests/disas/winch/aarch64/v128_ops/i64x2_eq.wat new file mode 100644 index 000000000000..8b5ee5916b6a --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i64x2_eq.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i64x2.eq + (v128.const i64x2 0x8000000000000000 5) + (v128.const i64x2 9 5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmeq v1.2d, v1.2d, v0.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #9 +;; 84: udf #0 +;; 88: udf #5 +;; 8c: udf #0 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0x00, 0x80 +;; 98: udf #5 +;; 9c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i64x2_ge_s.wat b/tests/disas/winch/aarch64/v128_ops/i64x2_ge_s.wat new file mode 100644 index 000000000000..bd4756abdfd0 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i64x2_ge_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i64x2.ge_s + (v128.const i64x2 0x8000000000000000 5) + (v128.const i64x2 9 5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmge v1.2d, v1.2d, v0.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #9 +;; 84: udf #0 +;; 88: udf #5 +;; 8c: udf #0 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0x00, 0x80 +;; 98: udf #5 +;; 9c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i64x2_gt_s.wat b/tests/disas/winch/aarch64/v128_ops/i64x2_gt_s.wat new file mode 100644 index 000000000000..0cde09417da0 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i64x2_gt_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i64x2.gt_s + (v128.const i64x2 0x8000000000000000 5) + (v128.const i64x2 9 5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmgt v1.2d, v1.2d, v0.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #9 +;; 84: udf #0 +;; 88: udf #5 +;; 8c: udf #0 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0x00, 0x80 +;; 98: udf #5 +;; 9c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i64x2_le_s.wat b/tests/disas/winch/aarch64/v128_ops/i64x2_le_s.wat new file mode 100644 index 000000000000..daf345e4adf8 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i64x2_le_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i64x2.le_s + (v128.const i64x2 0x8000000000000000 5) + (v128.const i64x2 9 5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmge v1.2d, v0.2d, v1.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #9 +;; 84: udf #0 +;; 88: udf #5 +;; 8c: udf #0 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0x00, 0x80 +;; 98: udf #5 +;; 9c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i64x2_lt_s.wat b/tests/disas/winch/aarch64/v128_ops/i64x2_lt_s.wat new file mode 100644 index 000000000000..9b1223dd66ce --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i64x2_lt_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i64x2.lt_s + (v128.const i64x2 0x8000000000000000 5) + (v128.const i64x2 9 5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmgt v1.2d, v0.2d, v1.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #9 +;; 84: udf #0 +;; 88: udf #5 +;; 8c: udf #0 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0x00, 0x80 +;; 98: udf #5 +;; 9c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i64x2_ne.wat b/tests/disas/winch/aarch64/v128_ops/i64x2_ne.wat new file mode 100644 index 000000000000..2e1c505c950c --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i64x2_ne.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i64x2.ne + (v128.const i64x2 0x8000000000000000 5) + (v128.const i64x2 9 5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x78 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmeq v1.2d, v1.2d, v0.2d +;; mvn v1.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 78: udf #0xc11f +;; 7c: udf #0 +;; 80: udf #9 +;; 84: udf #0 +;; 88: udf #5 +;; 8c: udf #0 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0x00, 0x80 +;; 98: udf #5 +;; 9c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_eq.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_eq.wat new file mode 100644 index 000000000000..320fce810cf3 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_eq.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.eq + (v128.const i8x16 128 1 255 5 100 200 7 0 64 32 16 8 4 2 1 0) + (v128.const i8x16 127 1 0 9 100 100 8 255 64 33 15 8 5 1 2 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmeq v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x7f, 0x01, 0x00, 0x09 +;; 84: .byte 0x64, 0x64, 0x08, 0xff +;; 88: stxrb w15, w0, [x10] +;; 8c: .byte 0x05, 0x01, 0x02, 0x00 +;; 90: .byte 0x80, 0x01, 0xff, 0x05 +;; 94: .byte 0x64, 0xc8, 0x07, 0x00 +;; 98: stxrb w16, w0, [x2] +;; 9c: .byte 0x04, 0x02, 0x01, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_ge_s.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_ge_s.wat new file mode 100644 index 000000000000..adca58cd13df --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_ge_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.ge_s + (v128.const i8x16 128 1 255 5 100 200 7 0 64 32 16 8 4 2 1 0) + (v128.const i8x16 127 1 0 9 100 100 8 255 64 33 15 8 5 1 2 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmge v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x7f, 0x01, 0x00, 0x09 +;; 84: .byte 0x64, 0x64, 0x08, 0xff +;; 88: stxrb w15, w0, [x10] +;; 8c: .byte 0x05, 0x01, 0x02, 0x00 +;; 90: .byte 0x80, 0x01, 0xff, 0x05 +;; 94: .byte 0x64, 0xc8, 0x07, 0x00 +;; 98: stxrb w16, w0, [x2] +;; 9c: .byte 0x04, 0x02, 0x01, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_ge_u.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_ge_u.wat new file mode 100644 index 000000000000..4b24a5bfe9df --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_ge_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.ge_u + (v128.const i8x16 128 1 255 5 100 200 7 0 64 32 16 8 4 2 1 0) + (v128.const i8x16 127 1 0 9 100 100 8 255 64 33 15 8 5 1 2 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhs v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x7f, 0x01, 0x00, 0x09 +;; 84: .byte 0x64, 0x64, 0x08, 0xff +;; 88: stxrb w15, w0, [x10] +;; 8c: .byte 0x05, 0x01, 0x02, 0x00 +;; 90: .byte 0x80, 0x01, 0xff, 0x05 +;; 94: .byte 0x64, 0xc8, 0x07, 0x00 +;; 98: stxrb w16, w0, [x2] +;; 9c: .byte 0x04, 0x02, 0x01, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_gt_s.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_gt_s.wat new file mode 100644 index 000000000000..21c96e533a75 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_gt_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.gt_s + (v128.const i8x16 128 1 255 5 100 200 7 0 64 32 16 8 4 2 1 0) + (v128.const i8x16 127 1 0 9 100 100 8 255 64 33 15 8 5 1 2 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmgt v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x7f, 0x01, 0x00, 0x09 +;; 84: .byte 0x64, 0x64, 0x08, 0xff +;; 88: stxrb w15, w0, [x10] +;; 8c: .byte 0x05, 0x01, 0x02, 0x00 +;; 90: .byte 0x80, 0x01, 0xff, 0x05 +;; 94: .byte 0x64, 0xc8, 0x07, 0x00 +;; 98: stxrb w16, w0, [x2] +;; 9c: .byte 0x04, 0x02, 0x01, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_gt_u.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_gt_u.wat new file mode 100644 index 000000000000..4632e9d10aab --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_gt_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.gt_u + (v128.const i8x16 128 1 255 5 100 200 7 0 64 32 16 8 4 2 1 0) + (v128.const i8x16 127 1 0 9 100 100 8 255 64 33 15 8 5 1 2 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhi v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x7f, 0x01, 0x00, 0x09 +;; 84: .byte 0x64, 0x64, 0x08, 0xff +;; 88: stxrb w15, w0, [x10] +;; 8c: .byte 0x05, 0x01, 0x02, 0x00 +;; 90: .byte 0x80, 0x01, 0xff, 0x05 +;; 94: .byte 0x64, 0xc8, 0x07, 0x00 +;; 98: stxrb w16, w0, [x2] +;; 9c: .byte 0x04, 0x02, 0x01, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_le_s.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_le_s.wat new file mode 100644 index 000000000000..0f2543d54f1e --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_le_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.le_s + (v128.const i8x16 128 1 255 5 100 200 7 0 64 32 16 8 4 2 1 0) + (v128.const i8x16 127 1 0 9 100 100 8 255 64 33 15 8 5 1 2 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmge v1.16b, v0.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x7f, 0x01, 0x00, 0x09 +;; 84: .byte 0x64, 0x64, 0x08, 0xff +;; 88: stxrb w15, w0, [x10] +;; 8c: .byte 0x05, 0x01, 0x02, 0x00 +;; 90: .byte 0x80, 0x01, 0xff, 0x05 +;; 94: .byte 0x64, 0xc8, 0x07, 0x00 +;; 98: stxrb w16, w0, [x2] +;; 9c: .byte 0x04, 0x02, 0x01, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_le_u.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_le_u.wat new file mode 100644 index 000000000000..d6a5126aee86 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_le_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.le_u + (v128.const i8x16 128 1 255 5 100 200 7 0 64 32 16 8 4 2 1 0) + (v128.const i8x16 127 1 0 9 100 100 8 255 64 33 15 8 5 1 2 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhs v1.16b, v0.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x7f, 0x01, 0x00, 0x09 +;; 84: .byte 0x64, 0x64, 0x08, 0xff +;; 88: stxrb w15, w0, [x10] +;; 8c: .byte 0x05, 0x01, 0x02, 0x00 +;; 90: .byte 0x80, 0x01, 0xff, 0x05 +;; 94: .byte 0x64, 0xc8, 0x07, 0x00 +;; 98: stxrb w16, w0, [x2] +;; 9c: .byte 0x04, 0x02, 0x01, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_lt_s.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_lt_s.wat new file mode 100644 index 000000000000..034179ffd8d9 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_lt_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.lt_s + (v128.const i8x16 128 1 255 5 100 200 7 0 64 32 16 8 4 2 1 0) + (v128.const i8x16 127 1 0 9 100 100 8 255 64 33 15 8 5 1 2 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmgt v1.16b, v0.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x7f, 0x01, 0x00, 0x09 +;; 84: .byte 0x64, 0x64, 0x08, 0xff +;; 88: stxrb w15, w0, [x10] +;; 8c: .byte 0x05, 0x01, 0x02, 0x00 +;; 90: .byte 0x80, 0x01, 0xff, 0x05 +;; 94: .byte 0x64, 0xc8, 0x07, 0x00 +;; 98: stxrb w16, w0, [x2] +;; 9c: .byte 0x04, 0x02, 0x01, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_lt_u.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_lt_u.wat new file mode 100644 index 000000000000..b512e6009a87 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_lt_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.lt_u + (v128.const i8x16 128 1 255 5 100 200 7 0 64 32 16 8 4 2 1 0) + (v128.const i8x16 127 1 0 9 100 100 8 255 64 33 15 8 5 1 2 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmhi v1.16b, v0.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x7f, 0x01, 0x00, 0x09 +;; 84: .byte 0x64, 0x64, 0x08, 0xff +;; 88: stxrb w15, w0, [x10] +;; 8c: .byte 0x05, 0x01, 0x02, 0x00 +;; 90: .byte 0x80, 0x01, 0xff, 0x05 +;; 94: .byte 0x64, 0xc8, 0x07, 0x00 +;; 98: stxrb w16, w0, [x2] +;; 9c: .byte 0x04, 0x02, 0x01, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_ne.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_ne.wat new file mode 100644 index 000000000000..1a29577f6ddf --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_ne.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.ne + (v128.const i8x16 128 1 255 5 100 200 7 0 64 32 16 8 4 2 1 0) + (v128.const i8x16 127 1 0 9 100 100 8 255 64 33 15 8 5 1 2 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x78 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; cmeq v1.16b, v1.16b, v0.16b +;; mvn v1.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 78: udf #0xc11f +;; 7c: udf #0 +;; 80: .byte 0x7f, 0x01, 0x00, 0x09 +;; 84: .byte 0x64, 0x64, 0x08, 0xff +;; 88: stxrb w15, w0, [x10] +;; 8c: .byte 0x05, 0x01, 0x02, 0x00 +;; 90: .byte 0x80, 0x01, 0xff, 0x05 +;; 94: .byte 0x64, 0xc8, 0x07, 0x00 +;; 98: stxrb w16, w0, [x2] +;; 9c: .byte 0x04, 0x02, 0x01, 0x00 diff --git a/winch/codegen/src/isa/aarch64/masm.rs b/winch/codegen/src/isa/aarch64/masm.rs index b4e83b385b88..7acf669bc348 100644 --- a/winch/codegen/src/isa/aarch64/masm.rs +++ b/winch/codegen/src/isa/aarch64/masm.rs @@ -1373,62 +1373,176 @@ impl Masm for MacroAssembler { fn v128_eq( &mut self, - _dst: WritableReg, - _lhs: Reg, - _rhs: Reg, - _kind: VectorEqualityKind, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorEqualityKind, ) -> Result<()> { - bail!(CodeGenError::unimplemented_masm_instruction()) + match kind { + VectorEqualityKind::I8x16 => { + self.asm + .vec_rrr(VecALUOp::Cmeq, lhs, rhs, dst, VectorSize::Size8x16); + } + VectorEqualityKind::I16x8 => { + self.asm + .vec_rrr(VecALUOp::Cmeq, lhs, rhs, dst, VectorSize::Size16x8); + } + VectorEqualityKind::I32x4 => { + self.asm + .vec_rrr(VecALUOp::Cmeq, lhs, rhs, dst, VectorSize::Size32x4); + } + VectorEqualityKind::I64x2 => { + self.asm + .vec_rrr(VecALUOp::Cmeq, lhs, rhs, dst, VectorSize::Size64x2); + } + VectorEqualityKind::F32x4 => { + self.asm + .vec_rrr(VecALUOp::Fcmeq, lhs, rhs, dst, VectorSize::Size32x4); + } + VectorEqualityKind::F64x2 => { + self.asm + .vec_rrr(VecALUOp::Fcmeq, lhs, rhs, dst, VectorSize::Size64x2); + } + } + Ok(()) } fn v128_ne( &mut self, - _dst: WritableReg, - _lhs: Reg, - _rhs: Reg, - _kind: VectorEqualityKind, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorEqualityKind, ) -> Result<()> { - bail!(CodeGenError::unimplemented_masm_instruction()) + match kind { + VectorEqualityKind::I8x16 => { + self.asm + .vec_rrr(VecALUOp::Cmeq, lhs, rhs, dst, VectorSize::Size8x16); + self.asm + .vec_misc(VecMisc2::Not, dst.to_reg(), dst, VectorSize::Size8x16); + } + VectorEqualityKind::I16x8 => { + self.asm + .vec_rrr(VecALUOp::Cmeq, lhs, rhs, dst, VectorSize::Size16x8); + self.asm + .vec_misc(VecMisc2::Not, dst.to_reg(), dst, VectorSize::Size16x8); + } + VectorEqualityKind::I32x4 => { + self.asm + .vec_rrr(VecALUOp::Cmeq, lhs, rhs, dst, VectorSize::Size32x4); + self.asm + .vec_misc(VecMisc2::Not, dst.to_reg(), dst, VectorSize::Size32x4); + } + VectorEqualityKind::I64x2 => { + self.asm + .vec_rrr(VecALUOp::Cmeq, lhs, rhs, dst, VectorSize::Size64x2); + self.asm + .vec_misc(VecMisc2::Not, dst.to_reg(), dst, VectorSize::Size64x2); + } + VectorEqualityKind::F32x4 => { + self.asm + .vec_rrr(VecALUOp::Fcmeq, lhs, rhs, dst, VectorSize::Size32x4); + self.asm + .vec_misc(VecMisc2::Not, dst.to_reg(), dst, VectorSize::Size32x4); + } + VectorEqualityKind::F64x2 => { + self.asm + .vec_rrr(VecALUOp::Fcmeq, lhs, rhs, dst, VectorSize::Size64x2); + self.asm + .vec_misc(VecMisc2::Not, dst.to_reg(), dst, VectorSize::Size64x2); + } + } + Ok(()) } fn v128_lt( &mut self, - _dst: WritableReg, - _lhs: Reg, - _rhs: Reg, - _kind: VectorCompareKind, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, ) -> Result<()> { - bail!(CodeGenError::unimplemented_masm_instruction()) + // aarch64 lacks vector less-than; swap operands and use greater-than. + let (op, size) = match kind { + VectorCompareKind::I8x16S => (VecALUOp::Cmgt, VectorSize::Size8x16), + VectorCompareKind::I8x16U => (VecALUOp::Cmhi, VectorSize::Size8x16), + VectorCompareKind::I16x8S => (VecALUOp::Cmgt, VectorSize::Size16x8), + VectorCompareKind::I16x8U => (VecALUOp::Cmhi, VectorSize::Size16x8), + VectorCompareKind::I32x4S => (VecALUOp::Cmgt, VectorSize::Size32x4), + VectorCompareKind::I32x4U => (VecALUOp::Cmhi, VectorSize::Size32x4), + VectorCompareKind::I64x2S => (VecALUOp::Cmgt, VectorSize::Size64x2), + VectorCompareKind::F32x4 => (VecALUOp::Fcmgt, VectorSize::Size32x4), + VectorCompareKind::F64x2 => (VecALUOp::Fcmgt, VectorSize::Size64x2), + }; + self.asm.vec_rrr(op, rhs, lhs, dst, size); + Ok(()) } fn v128_le( &mut self, - _dst: WritableReg, - _lhs: Reg, - _rhs: Reg, - _kind: VectorCompareKind, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, ) -> Result<()> { - bail!(CodeGenError::unimplemented_masm_instruction()) + // aarch64 lacks vector less-than; swap operands and use greater-than. + let (op, size) = match kind { + VectorCompareKind::I8x16S => (VecALUOp::Cmge, VectorSize::Size8x16), + VectorCompareKind::I8x16U => (VecALUOp::Cmhs, VectorSize::Size8x16), + VectorCompareKind::I16x8S => (VecALUOp::Cmge, VectorSize::Size16x8), + VectorCompareKind::I16x8U => (VecALUOp::Cmhs, VectorSize::Size16x8), + VectorCompareKind::I32x4S => (VecALUOp::Cmge, VectorSize::Size32x4), + VectorCompareKind::I32x4U => (VecALUOp::Cmhs, VectorSize::Size32x4), + VectorCompareKind::I64x2S => (VecALUOp::Cmge, VectorSize::Size64x2), + VectorCompareKind::F32x4 => (VecALUOp::Fcmge, VectorSize::Size32x4), + VectorCompareKind::F64x2 => (VecALUOp::Fcmge, VectorSize::Size64x2), + }; + self.asm.vec_rrr(op, rhs, lhs, dst, size); + Ok(()) } fn v128_gt( &mut self, - _dst: WritableReg, - _lhs: Reg, - _rhs: Reg, - _kind: VectorCompareKind, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, ) -> Result<()> { - bail!(CodeGenError::unimplemented_masm_instruction()) + let (op, size) = match kind { + VectorCompareKind::I8x16S => (VecALUOp::Cmgt, VectorSize::Size8x16), + VectorCompareKind::I8x16U => (VecALUOp::Cmhi, VectorSize::Size8x16), + VectorCompareKind::I16x8S => (VecALUOp::Cmgt, VectorSize::Size16x8), + VectorCompareKind::I16x8U => (VecALUOp::Cmhi, VectorSize::Size16x8), + VectorCompareKind::I32x4S => (VecALUOp::Cmgt, VectorSize::Size32x4), + VectorCompareKind::I32x4U => (VecALUOp::Cmhi, VectorSize::Size32x4), + VectorCompareKind::I64x2S => (VecALUOp::Cmgt, VectorSize::Size64x2), + VectorCompareKind::F32x4 => (VecALUOp::Fcmgt, VectorSize::Size32x4), + VectorCompareKind::F64x2 => (VecALUOp::Fcmgt, VectorSize::Size64x2), + }; + self.asm.vec_rrr(op, lhs, rhs, dst, size); + Ok(()) } fn v128_ge( &mut self, - _dst: WritableReg, - _lhs: Reg, - _rhs: Reg, - _kind: VectorCompareKind, + dst: WritableReg, + lhs: Reg, + rhs: Reg, + kind: VectorCompareKind, ) -> Result<()> { - bail!(CodeGenError::unimplemented_masm_instruction()) + let (op, size) = match kind { + VectorCompareKind::I8x16S => (VecALUOp::Cmge, VectorSize::Size8x16), + VectorCompareKind::I8x16U => (VecALUOp::Cmhs, VectorSize::Size8x16), + VectorCompareKind::I16x8S => (VecALUOp::Cmge, VectorSize::Size16x8), + VectorCompareKind::I16x8U => (VecALUOp::Cmhs, VectorSize::Size16x8), + VectorCompareKind::I32x4S => (VecALUOp::Cmge, VectorSize::Size32x4), + VectorCompareKind::I32x4U => (VecALUOp::Cmhs, VectorSize::Size32x4), + VectorCompareKind::I64x2S => (VecALUOp::Cmge, VectorSize::Size64x2), + VectorCompareKind::F32x4 => (VecALUOp::Fcmge, VectorSize::Size32x4), + VectorCompareKind::F64x2 => (VecALUOp::Fcmge, VectorSize::Size64x2), + }; + self.asm.vec_rrr(op, lhs, rhs, dst, size); + Ok(()) } fn v128_not(&mut self, dst: WritableReg) -> Result<()> {