From bb2d83c0f5f1bc86cbbddcc7f4d6245e86ba8efa Mon Sep 17 00:00:00 2001 From: macovedj Date: Tue, 21 Jul 2026 14:43:37 -0500 Subject: [PATCH] winch(aarch64): v128 add and sub ops --- .../winch/aarch64/v128_ops/f32x4_add.wat | 51 +++++++++ .../winch/aarch64/v128_ops/f32x4_sub.wat | 51 +++++++++ .../winch/aarch64/v128_ops/f64x2_add.wat | 51 +++++++++ .../winch/aarch64/v128_ops/f64x2_sub.wat | 51 +++++++++ .../winch/aarch64/v128_ops/i16x8_add.wat | 51 +++++++++ .../aarch64/v128_ops/i16x8_add_sat_s.wat | 51 +++++++++ .../aarch64/v128_ops/i16x8_add_sat_u.wat | 51 +++++++++ .../winch/aarch64/v128_ops/i16x8_sub.wat | 51 +++++++++ .../aarch64/v128_ops/i16x8_sub_sat_s.wat | 51 +++++++++ .../aarch64/v128_ops/i16x8_sub_sat_u.wat | 51 +++++++++ .../winch/aarch64/v128_ops/i32x4_add.wat | 51 +++++++++ .../winch/aarch64/v128_ops/i32x4_sub.wat | 51 +++++++++ .../winch/aarch64/v128_ops/i64x2_add.wat | 51 +++++++++ .../winch/aarch64/v128_ops/i64x2_sub.wat | 51 +++++++++ .../winch/aarch64/v128_ops/i8x16_add.wat | 51 +++++++++ .../aarch64/v128_ops/i8x16_add_sat_s.wat | 51 +++++++++ .../aarch64/v128_ops/i8x16_add_sat_u.wat | 51 +++++++++ .../winch/aarch64/v128_ops/i8x16_sub.wat | 51 +++++++++ .../aarch64/v128_ops/i8x16_sub_sat_s.wat | 51 +++++++++ .../aarch64/v128_ops/i8x16_sub_sat_u.wat | 51 +++++++++ winch/codegen/src/isa/aarch64/masm.rs | 107 +++++++++++++++--- 21 files changed, 1111 insertions(+), 16 deletions(-) create mode 100644 tests/disas/winch/aarch64/v128_ops/f32x4_add.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/f32x4_sub.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/f64x2_add.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/f64x2_sub.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i16x8_add.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i16x8_add_sat_s.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i16x8_add_sat_u.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i16x8_sub.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i16x8_sub_sat_s.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i16x8_sub_sat_u.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i32x4_add.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i32x4_sub.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i64x2_add.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i64x2_sub.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i8x16_add.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i8x16_add_sat_s.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i8x16_add_sat_u.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i8x16_sub.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i8x16_sub_sat_s.wat create mode 100644 tests/disas/winch/aarch64/v128_ops/i8x16_sub_sat_u.wat diff --git a/tests/disas/winch/aarch64/v128_ops/f32x4_add.wat b/tests/disas/winch/aarch64/v128_ops/f32x4_add.wat new file mode 100644 index 000000000000..23a24a9cb3cd --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f32x4_add.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f32x4.add + (v128.const f32x4 1.5 2.5 -3.25 100) + (v128.const f32x4 0.25 -0.5 3.25 0.125))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fadd v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0x80, 0x3e +;; 84: .byte 0x00, 0x00, 0x00, 0xbf +;; 88: .byte 0x00, 0x00, 0x50, 0x40 +;; 8c: .byte 0x00, 0x00, 0x00, 0x3e +;; 90: .byte 0x00, 0x00, 0xc0, 0x3f +;; 94: .byte 0x00, 0x00, 0x20, 0x40 +;; 98: .byte 0x00, 0x00, 0x50, 0xc0 +;; 9c: .byte 0x00, 0x00, 0xc8, 0x42 diff --git a/tests/disas/winch/aarch64/v128_ops/f32x4_sub.wat b/tests/disas/winch/aarch64/v128_ops/f32x4_sub.wat new file mode 100644 index 000000000000..6218af2c4680 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f32x4_sub.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f32x4.sub + (v128.const f32x4 1.5 2.5 -3.25 100) + (v128.const f32x4 0.25 -0.5 3.25 0.125))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fsub v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0x80, 0x3e +;; 84: .byte 0x00, 0x00, 0x00, 0xbf +;; 88: .byte 0x00, 0x00, 0x50, 0x40 +;; 8c: .byte 0x00, 0x00, 0x00, 0x3e +;; 90: .byte 0x00, 0x00, 0xc0, 0x3f +;; 94: .byte 0x00, 0x00, 0x20, 0x40 +;; 98: .byte 0x00, 0x00, 0x50, 0xc0 +;; 9c: .byte 0x00, 0x00, 0xc8, 0x42 diff --git a/tests/disas/winch/aarch64/v128_ops/f64x2_add.wat b/tests/disas/winch/aarch64/v128_ops/f64x2_add.wat new file mode 100644 index 000000000000..21bcd3df7b5c --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f64x2_add.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f64x2.add + (v128.const f64x2 1.5 -2.25) + (v128.const f64x2 0.75 2.5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fadd v1.2d, v1.2d, v0.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #0 +;; 84: .byte 0x00, 0x00, 0xe8, 0x3f +;; 88: udf #0 +;; 8c: .byte 0x00, 0x00, 0x04, 0x40 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0xf8, 0x3f +;; 98: udf #0 +;; 9c: mov z0.b, p0/m, za0h.b[w12, 0] diff --git a/tests/disas/winch/aarch64/v128_ops/f64x2_sub.wat b/tests/disas/winch/aarch64/v128_ops/f64x2_sub.wat new file mode 100644 index 000000000000..da9e79bdeda7 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/f64x2_sub.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (f64x2.sub + (v128.const f64x2 1.5 -2.25) + (v128.const f64x2 0.75 2.5))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; fsub v1.2d, v1.2d, v0.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #0 +;; 84: .byte 0x00, 0x00, 0xe8, 0x3f +;; 88: udf #0 +;; 8c: .byte 0x00, 0x00, 0x04, 0x40 +;; 90: udf #0 +;; 94: .byte 0x00, 0x00, 0xf8, 0x3f +;; 98: udf #0 +;; 9c: mov z0.b, p0/m, za0h.b[w12, 0] diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_add.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_add.wat new file mode 100644 index 000000000000..ec00729d01de --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_add.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.add + (v128.const i16x8 100 200 300 400 500 600 700 800) + (v128.const i16x8 1 2 3 4 5 6 7 8))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; add v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x01, 0x00, 0x02, 0x00 +;; 84: .byte 0x03, 0x00, 0x04, 0x00 +;; 88: .byte 0x05, 0x00, 0x06, 0x00 +;; 8c: .byte 0x07, 0x00, 0x08, 0x00 +;; 90: .byte 0x64, 0x00, 0xc8, 0x00 +;; 94: .byte 0x2c, 0x01, 0x90, 0x01 +;; 98: .byte 0xf4, 0x01, 0x58, 0x02 +;; 9c: .byte 0xbc, 0x02, 0x20, 0x03 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_add_sat_s.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_add_sat_s.wat new file mode 100644 index 000000000000..2fbc0248ecb0 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_add_sat_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.add_sat_s + (v128.const i16x8 32767 -32768 1000 -1000 0 1 32767 -1) + (v128.const i16x8 1 -1 1000 -1000 0 1 -1 32767))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; sqadd v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x01, 0x00, 0xff, 0xff +;; 84: stur d8, [sp, #-0x80] +;; 88: .byte 0x00, 0x00, 0x01, 0x00 +;; 8c: .byte 0xff, 0xff, 0xff, 0x7f +;; 90: .byte 0xff, 0x7f, 0x00, 0x80 +;; 94: stur d8, [sp, #-0x80] +;; 98: .byte 0x00, 0x00, 0x01, 0x00 +;; 9c: .byte 0xff, 0x7f, 0xff, 0xff diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_add_sat_u.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_add_sat_u.wat new file mode 100644 index 000000000000..7b631e637826 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_add_sat_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.add_sat_u + (v128.const i16x8 65535 60000 1000 0 1 32768 65535 2) + (v128.const i16x8 1 10000 1000 0 1 32768 0 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; uqadd v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x01, 0x00, 0x10, 0x27 +;; 84: udf #0x3e8 +;; 88: .byte 0x01, 0x00, 0x00, 0x80 +;; 8c: .byte 0x00, 0x00, 0xff, 0xff +;; 90: bics xzr, xzr, x0, lsr #63 +;; 94: udf #0x3e8 +;; 98: .byte 0x01, 0x00, 0x00, 0x80 +;; 9c: .byte 0xff, 0xff, 0x02, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_sub.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_sub.wat new file mode 100644 index 000000000000..adbb5795fe22 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_sub.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.sub + (v128.const i16x8 1000 2000 3000 4000 5 6 7 8) + (v128.const i16x8 1 2 3 4 500 600 700 800))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; sub v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x01, 0x00, 0x02, 0x00 +;; 84: .byte 0x03, 0x00, 0x04, 0x00 +;; 88: .byte 0xf4, 0x01, 0x58, 0x02 +;; 8c: .byte 0xbc, 0x02, 0x20, 0x03 +;; 90: .byte 0xe8, 0x03, 0xd0, 0x07 +;; 94: fmlal v24.2s, v29.2h, v0.h[6] +;; 98: .byte 0x05, 0x00, 0x06, 0x00 +;; 9c: .byte 0x07, 0x00, 0x08, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_sub_sat_s.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_sub_sat_s.wat new file mode 100644 index 000000000000..9065fffab345 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_sub_sat_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.sub_sat_s + (v128.const i16x8 -32768 32767 1000 -1000 0 1 -32768 32767) + (v128.const i16x8 1 -1 -1000 1000 0 1 32767 -32768))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; sqsub v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x01, 0x00, 0xff, 0xff +;; 84: .byte 0x18, 0xfc, 0xe8, 0x03 +;; 88: .byte 0x00, 0x00, 0x01, 0x00 +;; 8c: .byte 0xff, 0x7f, 0x00, 0x80 +;; 90: .byte 0x00, 0x80, 0xff, 0x7f +;; 94: stur d8, [sp, #-0x80] +;; 98: .byte 0x00, 0x00, 0x01, 0x00 +;; 9c: .byte 0x00, 0x80, 0xff, 0x7f diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_sub_sat_u.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_sub_sat_u.wat new file mode 100644 index 000000000000..3bda2469b2f1 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_sub_sat_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.sub_sat_u + (v128.const i16x8 3 65535 1000 0 1 32768 65535 2) + (v128.const i16x8 10 1 1000 1 1 32769 0 65535))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; uqsub v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x0a, 0x00, 0x01, 0x00 +;; 84: .byte 0xe8, 0x03, 0x01, 0x00 +;; 88: .byte 0x01, 0x00, 0x01, 0x80 +;; 8c: .byte 0x00, 0x00, 0xff, 0xff +;; 90: .byte 0x03, 0x00, 0xff, 0xff +;; 94: udf #0x3e8 +;; 98: .byte 0x01, 0x00, 0x00, 0x80 +;; 9c: .byte 0xff, 0xff, 0x02, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_add.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_add.wat new file mode 100644 index 000000000000..44d7a775cbec --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_add.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.add + (v128.const i32x4 1 2 3 4) + (v128.const i32x4 10 20 30 40))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; add v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #0xa +;; 84: udf #0x14 +;; 88: udf #0x1e +;; 8c: udf #0x28 +;; 90: udf #1 +;; 94: udf #2 +;; 98: udf #3 +;; 9c: udf #4 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_sub.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_sub.wat new file mode 100644 index 000000000000..5e1151c9b943 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_sub.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.sub + (v128.const i32x4 100 200 300 400) + (v128.const i32x4 1 2 3 4))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; sub v1.4s, v1.4s, v0.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #1 +;; 84: udf #2 +;; 88: udf #3 +;; 8c: udf #4 +;; 90: udf #0x64 +;; 94: udf #0xc8 +;; 98: udf #0x12c +;; 9c: udf #0x190 diff --git a/tests/disas/winch/aarch64/v128_ops/i64x2_add.wat b/tests/disas/winch/aarch64/v128_ops/i64x2_add.wat new file mode 100644 index 000000000000..db135a5d6731 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i64x2_add.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i64x2.add + (v128.const i64x2 100 200) + (v128.const i64x2 7 9))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; add v1.2d, v1.2d, v0.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #7 +;; 84: udf #0 +;; 88: udf #9 +;; 8c: udf #0 +;; 90: udf #0x64 +;; 94: udf #0 +;; 98: udf #0xc8 +;; 9c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i64x2_sub.wat b/tests/disas/winch/aarch64/v128_ops/i64x2_sub.wat new file mode 100644 index 000000000000..e597b2e81514 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i64x2_sub.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i64x2.sub + (v128.const i64x2 100 200) + (v128.const i64x2 7 9))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; sub v1.2d, v1.2d, v0.2d +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: udf #7 +;; 84: udf #0 +;; 88: udf #9 +;; 8c: udf #0 +;; 90: udf #0x64 +;; 94: udf #0 +;; 98: udf #0xc8 +;; 9c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_add.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_add.wat new file mode 100644 index 000000000000..55fb7cc96ad0 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_add.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.add + (v128.const i8x16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16) + (v128.const i8x16 10 10 10 10 10 10 10 10 20 20 20 20 20 20 20 20))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; add v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: and w10, w16, w10, lsl #2 +;; 84: and w10, w16, w10, lsl #2 +;; 88: b #0x5050d8 +;; 8c: b #0x5050dc +;; 90: subr z1.b, p0/m, z1.b, z16.b +;; 94: stxrb w7, w5, [x16] +;; 98: .byte 0x09, 0x0a, 0x0b, 0x0c +;; 9c: adr x13, #0x1e25c diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_add_sat_s.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_add_sat_s.wat new file mode 100644 index 000000000000..c23dcec734a7 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_add_sat_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.add_sat_s + (v128.const i8x16 127 -128 100 -100 0 1 -1 50 127 -128 5 -5 64 -64 127 -1) + (v128.const i8x16 1 -1 100 -100 0 1 -1 50 127 -128 5 -5 64 -64 -1 127))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; sqadd v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: ldr q1, #0xca060 +;; 84: .byte 0x00, 0x01, 0xff, 0x32 +;; 88: .byte 0x7f, 0x80, 0x05, 0xfb +;; 8c: .byte 0x40, 0xc0, 0xff, 0x7f +;; 90: ldr q31, #0xc909c +;; 94: .byte 0x00, 0x01, 0xff, 0x32 +;; 98: .byte 0x7f, 0x80, 0x05, 0xfb +;; 9c: .byte 0x40, 0xc0, 0x7f, 0xff diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_add_sat_u.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_add_sat_u.wat new file mode 100644 index 000000000000..e7348d0ed4d3 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_add_sat_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.add_sat_u + (v128.const i8x16 255 200 100 0 1 128 254 255 3 5 250 250 64 64 255 0) + (v128.const i8x16 1 100 100 0 1 128 1 255 3 5 10 6 64 64 0 255))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; uqadd v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x01, 0x64, 0x64, 0x00 +;; 84: .byte 0x01, 0x80, 0x01, 0xff +;; 88: .byte 0x03, 0x05, 0x0a, 0x06 +;; 8c: .byte 0x40, 0x40, 0x00, 0xff +;; 90: .byte 0xff, 0xc8, 0x64, 0x00 +;; 94: .byte 0x01, 0x80, 0xfe, 0xff +;; 98: .byte 0x03, 0x05, 0xfa, 0xfa +;; 9c: .byte 0x40, 0x40, 0xff, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_sub.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_sub.wat new file mode 100644 index 000000000000..19a0445068ef --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_sub.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.sub + (v128.const i8x16 50 60 70 80 90 100 110 120 5 10 15 20 25 30 35 40) + (v128.const i8x16 10 10 10 10 10 10 10 10 10 20 30 40 50 60 70 80))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; sub v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: and w10, w16, w10, lsl #2 +;; 84: and w10, w16, w10, lsl #2 +;; 88: stnp w10, w5, [x0, #0xf0] +;; 8c: adr x18, #0x8c812 +;; 90: adr x18, #0x8c816 +;; 94: .byte 0x5a, 0x64, 0x6e, 0x78 +;; 98: b #0x3c28ac +;; 9c: stnp w25, w7, [x16, #-0xe8] diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_sub_sat_s.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_sub_sat_s.wat new file mode 100644 index 000000000000..9ea51b6454cc --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_sub_sat_s.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.sub_sat_s + (v128.const i8x16 -128 127 -100 100 0 1 -1 50 -128 127 5 -5 -64 64 -128 0) + (v128.const i8x16 1 -1 100 -100 0 1 -1 -50 127 -128 5 -5 64 -64 0 -128))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; sqsub v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: ldr q1, #0xca060 +;; 84: .byte 0x00, 0x01, 0xff, 0xce +;; 88: .byte 0x7f, 0x80, 0x05, 0xfb +;; 8c: .byte 0x40, 0xc0, 0x00, 0x80 +;; 90: fcmla z0.s, p7/m, z28.s, z28.s, #0x10e +;; 94: .byte 0x00, 0x01, 0xff, 0x32 +;; 98: .byte 0x80, 0x7f, 0x05, 0xfb +;; 9c: .byte 0xc0, 0x40, 0x80, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_sub_sat_u.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_sub_sat_u.wat new file mode 100644 index 000000000000..c04504c98823 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_sub_sat_u.wat @@ -0,0 +1,51 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.sub_sat_u + (v128.const i8x16 3 255 100 0 1 128 254 255 3 5 250 6 64 64 255 0) + (v128.const i8x16 10 1 100 1 1 129 255 254 3 5 10 250 65 63 0 255))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x90 +;; uqsub v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x0a, 0x01, 0x64, 0x01 +;; 84: .byte 0x01, 0x81, 0xff, 0xfe +;; 88: .byte 0x03, 0x05, 0x0a, 0xfa +;; 8c: .byte 0x41, 0x3f, 0x00, 0xff +;; 90: .byte 0x03, 0xff, 0x64, 0x00 +;; 94: .byte 0x01, 0x80, 0xfe, 0xff +;; 98: .byte 0x03, 0x05, 0xfa, 0x06 +;; 9c: .byte 0x40, 0x40, 0xff, 0x00 diff --git a/winch/codegen/src/isa/aarch64/masm.rs b/winch/codegen/src/isa/aarch64/masm.rs index b4e83b385b88..83a242014447 100644 --- a/winch/codegen/src/isa/aarch64/masm.rs +++ b/winch/codegen/src/isa/aarch64/masm.rs @@ -774,6 +774,9 @@ impl Masm for MacroAssembler { _reg: WritableReg, _lane_size: OperandSize, ) -> Result<()> { + if !self.shared_flags.enable_nan_canonicalization() { + return Ok(()); + } bail!(CodeGenError::unimplemented_masm_instruction()) } @@ -1518,24 +1521,96 @@ impl Masm for MacroAssembler { bail!(CodeGenError::unimplemented_masm_instruction()) } - fn v128_add( - &mut self, - _lhs: Reg, - _rhs: Reg, - _dst: WritableReg, - _kind: V128AddKind, - ) -> Result<()> { - Err(format_err!(CodeGenError::unimplemented_masm_instruction())) + fn v128_add(&mut self, lhs: Reg, rhs: Reg, dst: WritableReg, kind: V128AddKind) -> Result<()> { + match kind { + V128AddKind::F32x4 => { + self.asm + .vec_rrr(VecALUOp::Fadd, lhs, rhs, dst, VectorSize::Size32x4); + } + V128AddKind::F64x2 => { + self.asm + .vec_rrr(VecALUOp::Fadd, lhs, rhs, dst, VectorSize::Size64x2); + } + V128AddKind::I8x16 => { + self.asm + .vec_rrr(VecALUOp::Add, lhs, rhs, dst, VectorSize::Size8x16); + } + V128AddKind::I8x16SatS => { + self.asm + .vec_rrr(VecALUOp::Sqadd, lhs, rhs, dst, VectorSize::Size8x16); + } + V128AddKind::I8x16SatU => { + self.asm + .vec_rrr(VecALUOp::Uqadd, lhs, rhs, dst, VectorSize::Size8x16); + } + V128AddKind::I16x8 => { + self.asm + .vec_rrr(VecALUOp::Add, lhs, rhs, dst, VectorSize::Size16x8); + } + V128AddKind::I16x8SatS => { + self.asm + .vec_rrr(VecALUOp::Sqadd, lhs, rhs, dst, VectorSize::Size16x8); + } + V128AddKind::I16x8SatU => { + self.asm + .vec_rrr(VecALUOp::Uqadd, lhs, rhs, dst, VectorSize::Size16x8); + } + V128AddKind::I32x4 => { + self.asm + .vec_rrr(VecALUOp::Add, lhs, rhs, dst, VectorSize::Size32x4); + } + V128AddKind::I64x2 => { + self.asm + .vec_rrr(VecALUOp::Add, lhs, rhs, dst, VectorSize::Size64x2); + } + } + Ok(()) } - fn v128_sub( - &mut self, - _lhs: Reg, - _rhs: Reg, - _dst: WritableReg, - _kind: V128SubKind, - ) -> Result<()> { - Err(format_err!(CodeGenError::unimplemented_masm_instruction())) + fn v128_sub(&mut self, lhs: Reg, rhs: Reg, dst: WritableReg, kind: V128SubKind) -> Result<()> { + match kind { + V128SubKind::F32x4 => { + self.asm + .vec_rrr(VecALUOp::Fsub, lhs, rhs, dst, VectorSize::Size32x4); + } + V128SubKind::F64x2 => { + self.asm + .vec_rrr(VecALUOp::Fsub, lhs, rhs, dst, VectorSize::Size64x2); + } + V128SubKind::I8x16 => { + self.asm + .vec_rrr(VecALUOp::Sub, lhs, rhs, dst, VectorSize::Size8x16); + } + V128SubKind::I8x16SatS => { + self.asm + .vec_rrr(VecALUOp::Sqsub, lhs, rhs, dst, VectorSize::Size8x16); + } + V128SubKind::I8x16SatU => { + self.asm + .vec_rrr(VecALUOp::Uqsub, lhs, rhs, dst, VectorSize::Size8x16); + } + V128SubKind::I16x8 => { + self.asm + .vec_rrr(VecALUOp::Sub, lhs, rhs, dst, VectorSize::Size16x8); + } + V128SubKind::I16x8SatS => { + self.asm + .vec_rrr(VecALUOp::Sqsub, lhs, rhs, dst, VectorSize::Size16x8); + } + V128SubKind::I16x8SatU => { + self.asm + .vec_rrr(VecALUOp::Uqsub, lhs, rhs, dst, VectorSize::Size16x8); + } + V128SubKind::I32x4 => { + self.asm + .vec_rrr(VecALUOp::Sub, lhs, rhs, dst, VectorSize::Size32x4); + } + V128SubKind::I64x2 => { + self.asm + .vec_rrr(VecALUOp::Sub, lhs, rhs, dst, VectorSize::Size64x2); + } + } + Ok(()) } fn v128_mul(