From b7205587647371752269525a319ee8ac785f2ad9 Mon Sep 17 00:00:00 2001 From: macovedj Date: Mon, 20 Jul 2026 16:03:54 -0500 Subject: [PATCH 1/4] v128.const support --- .../disas/winch/aarch64/v128_const/const.wat | 40 +++++++++++++++++++ winch/codegen/src/isa/aarch64/asm.rs | 6 ++- winch/codegen/src/isa/aarch64/masm.rs | 8 +--- 3 files changed, 47 insertions(+), 7 deletions(-) create mode 100644 tests/disas/winch/aarch64/v128_const/const.wat diff --git a/tests/disas/winch/aarch64/v128_const/const.wat b/tests/disas/winch/aarch64/v128_const/const.wat new file mode 100644 index 000000000000..e237ed6af118 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_const/const.wat @@ -0,0 +1,40 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) (v128.const i32x4 1 2 3 4)))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x6c +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x70 +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q0, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 6c: udf #0xc11f +;; 70: udf #1 +;; 74: udf #2 +;; 78: udf #3 +;; 7c: udf #4 diff --git a/winch/codegen/src/isa/aarch64/asm.rs b/winch/codegen/src/isa/aarch64/asm.rs index 61ccd6cd2ade..85284ddb26a7 100644 --- a/winch/codegen/src/isa/aarch64/asm.rs +++ b/winch/codegen/src/isa/aarch64/asm.rs @@ -313,7 +313,11 @@ impl Assembler { .for_each(|i| self.emit(i)); } RegClass::Float => { - match ASIMDFPModImm::maybe_from_u64(imm.unwrap_as_u64(), size.into()) { + let modimm = match imm { + Imm::V128(_) => None, + _ => ASIMDFPModImm::maybe_from_u64(imm.unwrap_as_u64(), size.into()), + }; + match modimm { Some(imm) => { self.emit(Inst::FpuMoveFPImm { rd: rd.map(Into::into), diff --git a/winch/codegen/src/isa/aarch64/masm.rs b/winch/codegen/src/isa/aarch64/masm.rs index ac1b6376ee97..e9a7d51d9c35 100644 --- a/winch/codegen/src/isa/aarch64/masm.rs +++ b/winch/codegen/src/isa/aarch64/masm.rs @@ -6,7 +6,7 @@ use super::{ regs::{self, scratch_fpr_bitset, scratch_gpr_bitset}, }; use crate::{ - Context, Result, + Result, abi::{self, align_to, calculate_frame_adjustment, local::LocalSlot, vmctx}, bail, codegen::{CodeGenContext, CodeGenError, Emission, FuncEnv, ptr_type_from_ptr_size}, @@ -517,14 +517,10 @@ impl Masm for MacroAssembler { self.asm.mov_ir(dst, v, v.size()); Ok(()) } - imm @ (I::F32(_) | I::F64(_)) => { + imm @ (I::F32(_) | I::F64(_) | I::V128(_)) => { self.asm.mov_ir(dst, imm, imm.size()); Ok(()) } - I::V128(_) => Err(CodeGenError::unsupported_imm()).context( - "v128 immediates are not supported in winch+aarch64; the SIMD and \ - relaxed-SIMD proposals are unimplemented for this target", - ), }, (RegImm::Reg(rs), rd) => match (rs.class(), rd.to_reg().class()) { (RegClass::Int, RegClass::Int) => Ok(self.asm.mov_rr(rs, rd, size)), From 5d986fd0334de2071bd67a77b6c63293db81ad7a Mon Sep 17 00:00:00 2001 From: macovedj Date: Mon, 20 Jul 2026 17:40:53 -0500 Subject: [PATCH 2/4] remove now-unused UnsupportedImm error variant --- winch/codegen/src/codegen/error.rs | 7 ------- 1 file changed, 7 deletions(-) diff --git a/winch/codegen/src/codegen/error.rs b/winch/codegen/src/codegen/error.rs index 254f5b335407..edeb3c20f03a 100644 --- a/winch/codegen/src/codegen/error.rs +++ b/winch/codegen/src/codegen/error.rs @@ -35,9 +35,6 @@ pub(crate) enum CodeGenError { /// Unsupported eager initialization of tables. #[error("Unsupported eager initialization of tables")] UnsupportedTableEagerInit, - /// Unsupported immediate for instruction. - #[error("Unsupported immediate")] - UnsupportedImm, /// An internal error. /// /// This error means that an internal invariant was not met and usually @@ -179,10 +176,6 @@ impl CodeGenError { Self::Internal(InternalError::InvalidLocalOffset) } - pub(crate) const fn unsupported_imm() -> Self { - Self::UnsupportedImm - } - pub(crate) const fn invalid_two_arg_form() -> Self { Self::Internal(InternalError::InvalidTwoArgumentForm) } From e6bcb4103cfe02f726f03e9a2c4544f9152989bc Mon Sep 17 00:00:00 2001 From: macovedj Date: Tue, 21 Jul 2026 09:46:11 -0500 Subject: [PATCH 3/4] winch: make aarch64 simd test expectations per-file --- crates/test-util/src/wast.rs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/crates/test-util/src/wast.rs b/crates/test-util/src/wast.rs index 864a0c6b2e81..33baecf04954 100644 --- a/crates/test-util/src/wast.rs +++ b/crates/test-util/src/wast.rs @@ -416,7 +416,7 @@ impl Compiler { } if cfg!(target_arch = "aarch64") { - return (config.simd() && !config.spec_test()) || config.threads(); + return config.threads(); } !cfg!(target_arch = "x86_64") @@ -556,16 +556,17 @@ impl WastTest { "misc_testsuite/simd/issue_3327_bnot_lowering.wast", "misc_testsuite/simd/load_splat_out_of_bounds.wast", "misc_testsuite/simd/replace-lane-preserve.wast", + "misc_testsuite/simd/riscv64-replicated-imm5-works.wast", "misc_testsuite/simd/spillslot-size-fuzzbug.wast", "misc_testsuite/simd/sse-cannot-fold-unaligned-loads.wast", "misc_testsuite/simd/unaligned-load.wast", + "misc_testsuite/simd/v128-equal.wast", "misc_testsuite/simd/v128-select.wast", "misc_testsuite/winch/issue-10331.wast", "misc_testsuite/winch/issue-10357.wast", "misc_testsuite/winch/issue-10460.wast", "misc_testsuite/winch/replace_lane.wast", "misc_testsuite/winch/simd_multivalue.wast", - "misc_testsuite/winch/v128_load_lane_invalid_address.wast", "spec_testsuite/proposals/annotations/simd_lane.wast", "spec_testsuite/proposals/multi-memory/simd_memory-multi.wast", "spec_testsuite/simd_address.wast", From 9b9411417f6ff4c83270985c609c01fd7d5dfe6f Mon Sep 17 00:00:00 2001 From: macovedj Date: Tue, 21 Jul 2026 10:41:39 -0500 Subject: [PATCH 4/4] restore simd should-fail check, list wast exceptions --- crates/test-util/src/wast.rs | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/crates/test-util/src/wast.rs b/crates/test-util/src/wast.rs index 33baecf04954..b724334d8de8 100644 --- a/crates/test-util/src/wast.rs +++ b/crates/test-util/src/wast.rs @@ -416,7 +416,7 @@ impl Compiler { } if cfg!(target_arch = "aarch64") { - return config.threads(); + return (config.simd() && !config.spec_test()) || config.threads(); } !cfg!(target_arch = "x86_64") @@ -512,6 +512,13 @@ impl WastTest { } } + if config.compiler == Compiler::Winch && cfg!(target_arch = "aarch64") { + let now_supported = ["misc_testsuite/winch/v128_load_lane_invalid_address.wast"]; + if now_supported.iter().any(|part| self.path.ends_with(part)) { + return false; + } + } + if config.compiler.should_fail(&self.config) { return true; } @@ -556,11 +563,9 @@ impl WastTest { "misc_testsuite/simd/issue_3327_bnot_lowering.wast", "misc_testsuite/simd/load_splat_out_of_bounds.wast", "misc_testsuite/simd/replace-lane-preserve.wast", - "misc_testsuite/simd/riscv64-replicated-imm5-works.wast", "misc_testsuite/simd/spillslot-size-fuzzbug.wast", "misc_testsuite/simd/sse-cannot-fold-unaligned-loads.wast", "misc_testsuite/simd/unaligned-load.wast", - "misc_testsuite/simd/v128-equal.wast", "misc_testsuite/simd/v128-select.wast", "misc_testsuite/winch/issue-10331.wast", "misc_testsuite/winch/issue-10357.wast",