Skip to content

Commit df57990

Browse files
cfallincfallin
authored
Cranelift: upgrade to regalloc2 0.14.0 and use static/constant MachineEnvs. (#12596)
* Update to new regalloc2 with constant MachineEnv. * Re-bless Cranelift filetests. * Re-bless Wasmtime disas tests. * Update to RA2 0.14.0. * Review feedback. * cargo-vet update.
1 parent 313640b commit df57990

704 files changed

Lines changed: 57501 additions & 57484 deletions

File tree

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎Cargo.lock‎

Lines changed: 2 additions & 2 deletions
Some generated files are not rendered by default. Learn more about customizing how changed files appear on GitHub.

‎Cargo.toml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -322,7 +322,7 @@ component-async-tests = { path = "crates/misc/component-async-tests" }
322322

323323
# Bytecode Alliance maintained dependencies:
324324
# ---------------------------
325-
regalloc2 = "0.13.4"
325+
regalloc2 = "0.14.0"
326326
wasip1 = { version = "1.0.0", default-features = false }
327327

328328
# cap-std family:

‎cranelift/codegen/src/isa/aarch64/abi.rs‎

Lines changed: 78 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,6 @@ use alloc::boxed::Box;
1717
use alloc::vec::Vec;
1818
use regalloc2::{MachineEnv, PReg, PRegSet};
1919
use smallvec::{SmallVec, smallvec};
20-
use std::sync::OnceLock;
2120

2221
// We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because
2322
// these ABIs are very similar.
@@ -1089,11 +1088,11 @@ impl ABIMachineSpec for AArch64MachineDeps {
10891088

10901089
fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv {
10911090
if flags.enable_pinned_reg() {
1092-
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();
1093-
MACHINE_ENV.get_or_init(|| create_reg_env(true))
1091+
static MACHINE_ENV: MachineEnv = create_reg_env(true);
1092+
&MACHINE_ENV
10941093
} else {
1095-
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();
1096-
MACHINE_ENV.get_or_init(|| create_reg_env(false))
1094+
static MACHINE_ENV: MachineEnv = create_reg_env(false);
1095+
&MACHINE_ENV
10971096
}
10981097
}
10991098

@@ -1534,100 +1533,96 @@ const WINCH_CLOBBERS: PRegSet = winch_clobbers();
15341533
const ALL_CLOBBERS: PRegSet = all_clobbers();
15351534
const NO_CLOBBERS: PRegSet = PRegSet::empty();
15361535

1537-
fn create_reg_env(enable_pinned_reg: bool) -> MachineEnv {
1538-
fn preg(r: Reg) -> PReg {
1539-
r.to_real_reg().unwrap().into()
1536+
const fn create_reg_env(enable_pinned_reg: bool) -> MachineEnv {
1537+
const fn preg(r: Reg) -> PReg {
1538+
r.to_real_reg().unwrap().preg()
15401539
}
15411540

15421541
let mut env = MachineEnv {
15431542
preferred_regs_by_class: [
1544-
vec![
1545-
preg(xreg(0)),
1546-
preg(xreg(1)),
1547-
preg(xreg(2)),
1548-
preg(xreg(3)),
1549-
preg(xreg(4)),
1550-
preg(xreg(5)),
1551-
preg(xreg(6)),
1552-
preg(xreg(7)),
1553-
preg(xreg(8)),
1554-
preg(xreg(9)),
1555-
preg(xreg(10)),
1556-
preg(xreg(11)),
1557-
preg(xreg(12)),
1558-
preg(xreg(13)),
1559-
preg(xreg(14)),
1560-
preg(xreg(15)),
1561-
// x16 and x17 are spilltmp and tmp2 (see above).
1562-
// x18 could be used by the platform to carry inter-procedural state;
1563-
// conservatively assume so and make it not allocatable.
1564-
// x19-28 are callee-saved and so not preferred.
1565-
// x21 is the pinned register (if enabled) and not allocatable if so.
1566-
// x29 is FP, x30 is LR, x31 is SP/ZR.
1567-
],
1568-
vec![
1569-
preg(vreg(0)),
1570-
preg(vreg(1)),
1571-
preg(vreg(2)),
1572-
preg(vreg(3)),
1573-
preg(vreg(4)),
1574-
preg(vreg(5)),
1575-
preg(vreg(6)),
1576-
preg(vreg(7)),
1543+
PRegSet::empty()
1544+
.with(preg(xreg(0)))
1545+
.with(preg(xreg(1)))
1546+
.with(preg(xreg(2)))
1547+
.with(preg(xreg(3)))
1548+
.with(preg(xreg(4)))
1549+
.with(preg(xreg(5)))
1550+
.with(preg(xreg(6)))
1551+
.with(preg(xreg(7)))
1552+
.with(preg(xreg(8)))
1553+
.with(preg(xreg(9)))
1554+
.with(preg(xreg(10)))
1555+
.with(preg(xreg(11)))
1556+
.with(preg(xreg(12)))
1557+
.with(preg(xreg(13)))
1558+
.with(preg(xreg(14)))
1559+
.with(preg(xreg(15))),
1560+
// x16 and x17 are spilltmp and tmp2 (see above).
1561+
// x18 could be used by the platform to carry inter-procedural state;
1562+
// conservatively assume so and make it not allocatable.
1563+
// x19-28 are callee-saved and so not preferred.
1564+
// x21 is the pinned register (if enabled) and not allocatable if so.
1565+
// x29 is FP, x30 is LR, x31 is SP/ZR.
1566+
PRegSet::empty()
1567+
.with(preg(vreg(0)))
1568+
.with(preg(vreg(1)))
1569+
.with(preg(vreg(2)))
1570+
.with(preg(vreg(3)))
1571+
.with(preg(vreg(4)))
1572+
.with(preg(vreg(5)))
1573+
.with(preg(vreg(6)))
1574+
.with(preg(vreg(7)))
15771575
// v8-15 are callee-saved and so not preferred.
1578-
preg(vreg(16)),
1579-
preg(vreg(17)),
1580-
preg(vreg(18)),
1581-
preg(vreg(19)),
1582-
preg(vreg(20)),
1583-
preg(vreg(21)),
1584-
preg(vreg(22)),
1585-
preg(vreg(23)),
1586-
preg(vreg(24)),
1587-
preg(vreg(25)),
1588-
preg(vreg(26)),
1589-
preg(vreg(27)),
1590-
preg(vreg(28)),
1591-
preg(vreg(29)),
1592-
preg(vreg(30)),
1593-
preg(vreg(31)),
1594-
],
1576+
.with(preg(vreg(16)))
1577+
.with(preg(vreg(17)))
1578+
.with(preg(vreg(18)))
1579+
.with(preg(vreg(19)))
1580+
.with(preg(vreg(20)))
1581+
.with(preg(vreg(21)))
1582+
.with(preg(vreg(22)))
1583+
.with(preg(vreg(23)))
1584+
.with(preg(vreg(24)))
1585+
.with(preg(vreg(25)))
1586+
.with(preg(vreg(26)))
1587+
.with(preg(vreg(27)))
1588+
.with(preg(vreg(28)))
1589+
.with(preg(vreg(29)))
1590+
.with(preg(vreg(30)))
1591+
.with(preg(vreg(31))),
15951592
// Vector Regclass is unused
1596-
vec![],
1593+
PRegSet::empty(),
15971594
],
15981595
non_preferred_regs_by_class: [
1599-
vec![
1600-
preg(xreg(19)),
1601-
preg(xreg(20)),
1596+
PRegSet::empty()
1597+
.with(preg(xreg(19)))
1598+
.with(preg(xreg(20)))
16021599
// x21 is pinned reg if enabled; we add to this list below if not.
1603-
preg(xreg(22)),
1604-
preg(xreg(23)),
1605-
preg(xreg(24)),
1606-
preg(xreg(25)),
1607-
preg(xreg(26)),
1608-
preg(xreg(27)),
1609-
preg(xreg(28)),
1610-
],
1611-
vec![
1612-
preg(vreg(8)),
1613-
preg(vreg(9)),
1614-
preg(vreg(10)),
1615-
preg(vreg(11)),
1616-
preg(vreg(12)),
1617-
preg(vreg(13)),
1618-
preg(vreg(14)),
1619-
preg(vreg(15)),
1620-
],
1600+
.with(preg(xreg(22)))
1601+
.with(preg(xreg(23)))
1602+
.with(preg(xreg(24)))
1603+
.with(preg(xreg(25)))
1604+
.with(preg(xreg(26)))
1605+
.with(preg(xreg(27)))
1606+
.with(preg(xreg(28))),
1607+
PRegSet::empty()
1608+
.with(preg(vreg(8)))
1609+
.with(preg(vreg(9)))
1610+
.with(preg(vreg(10)))
1611+
.with(preg(vreg(11)))
1612+
.with(preg(vreg(12)))
1613+
.with(preg(vreg(13)))
1614+
.with(preg(vreg(14)))
1615+
.with(preg(vreg(15))),
16211616
// Vector Regclass is unused
1622-
vec![],
1617+
PRegSet::empty(),
16231618
],
16241619
fixed_stack_slots: vec![],
16251620
scratch_by_class: [None, None, None],
16261621
};
16271622

16281623
if !enable_pinned_reg {
1629-
debug_assert_eq!(PINNED_REG, 21); // We assumed this above in hardcoded reg list.
1630-
env.non_preferred_regs_by_class[0].push(preg(xreg(PINNED_REG)));
1624+
debug_assert!(PINNED_REG == 21);
1625+
env.non_preferred_regs_by_class[0].add(preg(xreg(PINNED_REG)));
16311626
}
16321627

16331628
env

‎cranelift/codegen/src/isa/aarch64/inst/regs.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,8 @@ pub fn writable_xreg(num: u8) -> Writable<Reg> {
3636
}
3737

3838
/// Get a reference to a V-register (vector/FP register).
39-
pub fn vreg(num: u8) -> Reg {
40-
Reg::from(vreg_preg(num))
39+
pub const fn vreg(num: u8) -> Reg {
40+
Reg::from_real_reg(vreg_preg(num))
4141
}
4242

4343
/// Get the given V-register as a PReg.

‎cranelift/codegen/src/isa/pulley_shared/abi.rs‎

Lines changed: 111 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,8 @@ use alloc::borrow::ToOwned;
1313
use alloc::vec::Vec;
1414
use core::marker::PhantomData;
1515
use cranelift_bitset::ScalarBitSet;
16-
use regalloc2::{MachineEnv, PReg, PRegSet};
16+
use regalloc2::{MachineEnv, PRegSet};
1717
use smallvec::{SmallVec, smallvec};
18-
use std::sync::OnceLock;
1918

2019
/// Support for the Pulley ABI from the callee side (within a function body).
2120
pub(crate) type PulleyCallee<P> = Callee<PulleyMachineDeps<P>>;
@@ -481,8 +480,8 @@ where
481480
}
482481

483482
fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv {
484-
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();
485-
MACHINE_ENV.get_or_init(create_reg_environment)
483+
static MACHINE_ENV: MachineEnv = create_reg_environment();
484+
&MACHINE_ENV
486485
}
487486

488487
fn get_regs_clobbered_by_call(
@@ -972,26 +971,118 @@ const ALL_CLOBBERS: PRegSet = PRegSet::empty()
972971

973972
const NO_CLOBBERS: PRegSet = PRegSet::empty();
974973

975-
fn create_reg_environment() -> MachineEnv {
974+
const fn create_reg_environment() -> MachineEnv {
976975
// Prefer caller-saved registers over callee-saved registers, because that
977976
// way we don't need to emit code to save and restore them if we don't
978977
// mutate them.
979978

980-
let preferred_regs_by_class: [Vec<PReg>; 3] = {
981-
let x_registers: Vec<PReg> = (0..16).map(|x| px_reg(x)).collect();
982-
let f_registers: Vec<PReg> = (0..32).map(|x| pf_reg(x)).collect();
983-
let v_registers: Vec<PReg> = (0..32).map(|x| pv_reg(x)).collect();
984-
[x_registers, f_registers, v_registers]
985-
};
986-
987-
let non_preferred_regs_by_class: [Vec<PReg>; 3] = {
988-
let x_registers: Vec<PReg> = (16..XReg::SPECIAL_START)
989-
.map(|x| px_reg(x.into()))
990-
.collect();
991-
let f_registers: Vec<PReg> = vec![];
992-
let v_registers: Vec<PReg> = vec![];
993-
[x_registers, f_registers, v_registers]
994-
};
979+
let preferred_regs_by_class: [PRegSet; 3] = [
980+
PRegSet::empty()
981+
.with(px_reg(0))
982+
.with(px_reg(1))
983+
.with(px_reg(2))
984+
.with(px_reg(3))
985+
.with(px_reg(4))
986+
.with(px_reg(5))
987+
.with(px_reg(6))
988+
.with(px_reg(7))
989+
.with(px_reg(8))
990+
.with(px_reg(9))
991+
.with(px_reg(10))
992+
.with(px_reg(11))
993+
.with(px_reg(12))
994+
.with(px_reg(13))
995+
.with(px_reg(14))
996+
.with(px_reg(15)),
997+
PRegSet::empty()
998+
.with(pf_reg(0))
999+
.with(pf_reg(1))
1000+
.with(pf_reg(2))
1001+
.with(pf_reg(3))
1002+
.with(pf_reg(4))
1003+
.with(pf_reg(5))
1004+
.with(pf_reg(6))
1005+
.with(pf_reg(7))
1006+
.with(pf_reg(8))
1007+
.with(pf_reg(9))
1008+
.with(pf_reg(10))
1009+
.with(pf_reg(11))
1010+
.with(pf_reg(12))
1011+
.with(pf_reg(13))
1012+
.with(pf_reg(14))
1013+
.with(pf_reg(15))
1014+
.with(pf_reg(16))
1015+
.with(pf_reg(17))
1016+
.with(pf_reg(18))
1017+
.with(pf_reg(19))
1018+
.with(pf_reg(20))
1019+
.with(pf_reg(21))
1020+
.with(pf_reg(22))
1021+
.with(pf_reg(23))
1022+
.with(pf_reg(24))
1023+
.with(pf_reg(25))
1024+
.with(pf_reg(26))
1025+
.with(pf_reg(27))
1026+
.with(pf_reg(28))
1027+
.with(pf_reg(29))
1028+
.with(pf_reg(30))
1029+
.with(pf_reg(31)),
1030+
PRegSet::empty()
1031+
.with(pv_reg(0))
1032+
.with(pv_reg(1))
1033+
.with(pv_reg(2))
1034+
.with(pv_reg(3))
1035+
.with(pv_reg(4))
1036+
.with(pv_reg(5))
1037+
.with(pv_reg(6))
1038+
.with(pv_reg(7))
1039+
.with(pv_reg(8))
1040+
.with(pv_reg(9))
1041+
.with(pv_reg(10))
1042+
.with(pv_reg(11))
1043+
.with(pv_reg(12))
1044+
.with(pv_reg(13))
1045+
.with(pv_reg(14))
1046+
.with(pv_reg(15))
1047+
.with(pv_reg(16))
1048+
.with(pv_reg(17))
1049+
.with(pv_reg(18))
1050+
.with(pv_reg(19))
1051+
.with(pv_reg(20))
1052+
.with(pv_reg(21))
1053+
.with(pv_reg(22))
1054+
.with(pv_reg(23))
1055+
.with(pv_reg(24))
1056+
.with(pv_reg(25))
1057+
.with(pv_reg(26))
1058+
.with(pv_reg(27))
1059+
.with(pv_reg(28))
1060+
.with(pv_reg(29))
1061+
.with(pv_reg(30))
1062+
.with(pv_reg(31)),
1063+
];
1064+
1065+
let non_preferred_regs_by_class: [PRegSet; 3] = [
1066+
PRegSet::empty()
1067+
.with(px_reg(16))
1068+
.with(px_reg(17))
1069+
.with(px_reg(18))
1070+
.with(px_reg(19))
1071+
.with(px_reg(20))
1072+
.with(px_reg(21))
1073+
.with(px_reg(22))
1074+
.with(px_reg(23))
1075+
.with(px_reg(24))
1076+
.with(px_reg(25))
1077+
.with(px_reg(26))
1078+
.with(px_reg(27))
1079+
.with(px_reg(28))
1080+
.with(px_reg(29)),
1081+
PRegSet::empty(),
1082+
PRegSet::empty(),
1083+
];
1084+
1085+
debug_assert!(XReg::SPECIAL_START == 30);
9951086

9961087
MachineEnv {
9971088
preferred_regs_by_class,

0 commit comments

Comments
 (0)