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Update disas test results.
These are all just 8-byte offset increases from the addition of my epoch interrupt page ptr field to `VMStoreContext`. This script helped me show it: ```python """Compare runs of - and + blocks of a diff, and assert that the only differences between them are differences in hex and decimal numbers therein. Further, assert that those differences are a rise of 8, representing the size of the field I added. Output the diff with the proven-correct regions resolved in favor of the + lines. Any remaining diff lines are suspicious and should be manually examined. """ import re from sys import argv def is_diff_line(s, plus_or_minus): return bool(re.match(r"^ +" + "\\" + plus_or_minus, s)) def is_minus_line(s): return is_diff_line(s, "-") def is_plus_line(s): return is_diff_line(s, "+") def check_line_pairs(file_path): with open(file_path, 'r') as file: lines = file.readlines() i = 0 while i < len(lines): if is_minus_line(lines[i]): minus_block = [] while i < len(lines) and is_minus_line(lines[i]): minus_block.append(lines[i]) i += 1 plus_block = [] while i < len(lines) and is_plus_line(lines[i]): plus_block.append(lines[i]) i += 1 if len(minus_block) != len(plus_block): print(" + BLOCK LENGTHS DIFFERED.") print("".join(minus_block)) print("".join(plus_block)) continue # Compare the two blocks line by line for line1, line2 in zip(minus_block, plus_block): # Extract numbers (both decimal and hexadecimal) from both lines numbers1 = [int(num, 16) if num.startswith("0x") else int(num) for num in re.findall(r'0x[0-9a-fA-F]+|\d+', line1)] numbers2 = [int(num, 16) if num.startswith("0x") else int(num) for num in re.findall(r'0x[0-9a-fA-F]+|\d+', line2)] # Check if the numbers differ by 0 or 8 if len(numbers1) == len(numbers2) and all(n2 - n1 in (0, 8) for n1, n2 in zip(numbers1, numbers2)): # It's just an increment (or nothing), so keep the new line: print(re.sub(r"^( +)\+", r"\1 ", line2), end="") else: print(line1, end="") print(line2, end="") else: print(lines[i], end="") i += 1 check_line_pairs(argv[1]) ```
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tests/disas/arith.wat

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;; function u0:0(i64 vmctx, i64) tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; stack_limit = gv2
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;;
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;; block0(v0: i64, v1: i64):

tests/disas/basic-wat-test.wat

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;; function u0:0(i64 vmctx, i64, i32, i32) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; gv3 = vmctx
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;; gv4 = load.i64 notrap aligned gv3+64
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;; gv5 = load.i64 notrap aligned readonly can_move checked gv3+56

tests/disas/br_table.wat

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;; function u0:0(i64 vmctx, i64) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; stack_limit = gv2
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;;
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;; block0(v0: i64, v1: i64):
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;; function u0:1(i64 vmctx, i64) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; stack_limit = gv2
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;;
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;; block0(v0: i64, v1: i64):
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;; function u0:2(i64 vmctx, i64) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; stack_limit = gv2
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;;
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;; block0(v0: i64, v1: i64):
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;; function u0:3(i64 vmctx, i64) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; stack_limit = gv2
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;;
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;; block0(v0: i64, v1: i64):

tests/disas/byteswap.wat

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;; function u0:0(i64 vmctx, i64, i32) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; stack_limit = gv2
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;;
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;; block0(v0: i64, v1: i64, v2: i32):
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;; function u0:1(i64 vmctx, i64, i64) -> i64 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; stack_limit = gv2
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;;
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;; block0(v0: i64, v1: i64, v2: i64):

tests/disas/call-indirect.wat

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;; function u0:0(i64 vmctx, i64, i32, i32) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; gv3 = vmctx
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;; gv4 = load.i64 notrap aligned gv3+48
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;; gv5 = load.i64 notrap aligned gv3+56

tests/disas/call-simd.wat

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;; function u0:0(i64 vmctx, i64) tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; sig0 = (i64 vmctx, i64, i8x16, i8x16) -> i8x16 tail
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;; fn0 = colocated u0:1 sig0
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;; const0 = 0x00000004000000030000000200000001
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;; function u0:1(i64 vmctx, i64, i8x16, i8x16) -> i8x16 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; stack_limit = gv2
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;;
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;; block0(v0: i64, v1: i64, v2: i8x16, v3: i8x16):

tests/disas/call.wat

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;; function u0:0(i64 vmctx, i64) tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; sig0 = (i64 vmctx, i64) -> i32 tail
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;; fn0 = colocated u0:1 sig0
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;; stack_limit = gv2
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;; function u0:1(i64 vmctx, i64) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; stack_limit = gv2
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;;
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;; block0(v0: i64, v1: i64):

tests/disas/component-model/direct-adapter-calls-inlining.wat

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;; function u1:0(i64 vmctx, i64) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; gv3 = vmctx
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;; gv4 = vmctx
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;; gv5 = load.i64 notrap aligned readonly gv4+8
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;; gv6 = load.i64 notrap aligned gv5+16
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;; gv6 = load.i64 notrap aligned gv5+24
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;; gv7 = vmctx
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;; gv8 = load.i64 notrap aligned readonly can_move gv7+96
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;; gv9 = load.i64 notrap aligned readonly can_move gv7+72
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;; gv10 = vmctx
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;; gv11 = load.i64 notrap aligned readonly gv10+8
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;; gv12 = load.i64 notrap aligned gv11+16
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;; gv12 = load.i64 notrap aligned gv11+24
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;; sig0 = (i64 vmctx, i64, i32) -> i32 tail
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;; sig1 = (i64 vmctx, i64, i32) -> i32 tail
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;; fn0 = colocated u2:0 sig0

tests/disas/component-model/direct-adapter-calls-x64.wat

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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r10
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;; movq 0x10(%r10), %r10
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;; movq 0x18(%r10), %r10
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;; addq $0x10, %r10
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;; cmpq %rsp, %r10
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;; ja 0x4f
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r10
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;; movq 0x10(%r10), %r10
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;; movq 0x18(%r10), %r10
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;; addq $0x20, %r10
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;; cmpq %rsp, %r10
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;; ja 0xfe

tests/disas/component-model/direct-adapter-calls.wat

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;; function u0:0(i64 vmctx, i64, i32) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; stack_limit = gv2
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;;
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;; block0(v0: i64, v1: i64, v2: i32):
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;; function u1:0(i64 vmctx, i64) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; gv3 = vmctx
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;; sig0 = (i64 vmctx, i64, i32) -> i32 tail
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;; fn0 = colocated u2:0 sig0
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;; function u2:0(i64 vmctx, i64, i32) -> i32 tail {
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;; gv0 = vmctx
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;; gv1 = load.i64 notrap aligned readonly gv0+8
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;; gv2 = load.i64 notrap aligned gv1+16
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;; gv2 = load.i64 notrap aligned gv1+24
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;; gv3 = vmctx
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;; gv4 = load.i64 notrap aligned readonly can_move gv3+96
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;; gv5 = load.i64 notrap aligned readonly can_move gv3+72

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