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Add test for inc/dec (hl)
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tests/arch/zx48k/optimizer/test_cpustate.py

Lines changed: 44 additions & 0 deletions
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@@ -396,3 +396,47 @@ def test_ix_neg(self):
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"""
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self._eval(code)
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self.assertNotEqual(self.regs['a'], self.mem['ix-1'])
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def test_inc_hl(self):
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code = """
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ld hl, 32
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ld (hl), 1
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inc (hl)
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"""
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self._eval(code)
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self.assertEqual(self.regs['hl'], '32')
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self.assertDictEqual(self.mem, {'32': '2'})
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self.assertEqual(self.cpu_state.Z, 0)
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def test_dec_hl(self):
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code = """
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ld hl, 32
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ld (hl), 1
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dec (hl)
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"""
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self._eval(code)
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self.assertEqual(self.regs['hl'], '32')
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self.assertDictEqual(self.mem, {'32': '0'})
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self.assertEqual(self.cpu_state.Z, 1)
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def test_inc_hl_unknown(self):
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code = """
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ld hl, _a
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ld (hl), 1
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inc (hl)
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"""
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self._eval(code)
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self.assertTrue(helpers.is_unknown16(self.regs['hl']))
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self.assertDictEqual(self.mem, {self.regs['hl']: '2'})
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self.assertEqual(self.cpu_state.Z, 0)
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def test_dec_hl_unknown(self):
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code = """
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ld hl, _a
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ld (hl), 1
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dec (hl)
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"""
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self._eval(code)
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self.assertTrue(helpers.is_unknown16(self.regs['hl']))
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self.assertDictEqual(self.mem, {self.regs['hl']: '0'})
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self.assertEqual(self.cpu_state.Z, 1)

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