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tests/arch/zx48k/optimizer Expand file tree Collapse file tree Original file line number Diff line number Diff line change @@ -396,3 +396,47 @@ def test_ix_neg(self):
396396 """
397397 self ._eval (code )
398398 self .assertNotEqual (self .regs ['a' ], self .mem ['ix-1' ])
399+
400+ def test_inc_hl (self ):
401+ code = """
402+ ld hl, 32
403+ ld (hl), 1
404+ inc (hl)
405+ """
406+ self ._eval (code )
407+ self .assertEqual (self .regs ['hl' ], '32' )
408+ self .assertDictEqual (self .mem , {'32' : '2' })
409+ self .assertEqual (self .cpu_state .Z , 0 )
410+
411+ def test_dec_hl (self ):
412+ code = """
413+ ld hl, 32
414+ ld (hl), 1
415+ dec (hl)
416+ """
417+ self ._eval (code )
418+ self .assertEqual (self .regs ['hl' ], '32' )
419+ self .assertDictEqual (self .mem , {'32' : '0' })
420+ self .assertEqual (self .cpu_state .Z , 1 )
421+
422+ def test_inc_hl_unknown (self ):
423+ code = """
424+ ld hl, _a
425+ ld (hl), 1
426+ inc (hl)
427+ """
428+ self ._eval (code )
429+ self .assertTrue (helpers .is_unknown16 (self .regs ['hl' ]))
430+ self .assertDictEqual (self .mem , {self .regs ['hl' ]: '2' })
431+ self .assertEqual (self .cpu_state .Z , 0 )
432+
433+ def test_dec_hl_unknown (self ):
434+ code = """
435+ ld hl, _a
436+ ld (hl), 1
437+ dec (hl)
438+ """
439+ self ._eval (code )
440+ self .assertTrue (helpers .is_unknown16 (self .regs ['hl' ]))
441+ self .assertDictEqual (self .mem , {self .regs ['hl' ]: '0' })
442+ self .assertEqual (self .cpu_state .Z , 1 )
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