Detect in/out reg dependencies

For in/out the b register is also involved in Z80, as it's
used to address a 16 bit port.

Author: boriel

arch/zx48k/optimizer/memcell.py

@@ -295,12 +295,12 @@ def requires(self):
 
         elif i == 'out':
             result.add(o[1])
-            if o[0] == '(c)':
-                result.add('c')
+            if o[0] == 'c':
+                result.update('b', 'c')
 
         elif i == 'in':
-            if o[1] == '(c)':
-                result.add('c')
+            if o[1] == 'c':
+                result.update('b', 'c')
 
         elif i == 'im':
             result.add('i')

tests/arch/zx48k/backend/test_memcell.py

@@ -129,3 +129,25 @@ def test_requires_xor_a(self):
         c = memcell.MemCell('xor a', 1)
         self.assertSetEqual(c.requires, set())
         self.assertSetEqual(c.destroys, {'a', 'f'})
+
+    def test_require_out(self):
+        """ Test requires for out(c), a instruction
+        """
+        c = memcell.MemCell('out (c), a', 1)
+        self.assertSetEqual(c.requires, {'a', 'b', 'c'})
+        self.assertSetEqual(c.destroys, set())
+
+        c = memcell.MemCell('out (c), d', 1)
+        self.assertSetEqual(c.requires, {'d', 'b', 'c'})
+        self.assertSetEqual(c.destroys, set())
+
+    def test_require_in(self):
+        """ Test requires for out(c), a instruction
+        """
+        c = memcell.MemCell('in a, (c)', 1)
+        self.assertSetEqual(c.requires, {'b', 'c'})
+        self.assertSetEqual(c.destroys, {'a'})
+
+        c = memcell.MemCell('in d, (c)', 1)
+        self.assertSetEqual(c.requires, {'b', 'c'})
+        self.assertSetEqual(c.destroys, {'d'})