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ref: move int16 function into a class (Bits16)
1 parent 91f4636 commit 571d107

2 files changed

Lines changed: 22 additions & 25 deletions

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src/arch/z80/backend/_16bit.py

Lines changed: 18 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -16,19 +16,16 @@
1616
from src.arch.z80.backend.runtime import Labels as RuntimeLabel
1717

1818

19-
# -----------------------------------------------------
20-
# 16 bits operands
21-
# -----------------------------------------------------
22-
def int16(op):
23-
"""Returns a 16 bit operand converted to 16 bits unsigned int.
24-
Negative numbers are returned in 2 complement.
25-
"""
26-
return int(op) & 0xFFFF
27-
28-
2919
class Bits16:
3020
"""Implementation of 16bit operations."""
3121

22+
@classmethod
23+
def int16(cls, op):
24+
"""Returns a 16 bit operand converted to 16 bits unsigned int.
25+
Negative numbers are returned in 2 complement.
26+
"""
27+
return int(op) & 0xFFFF
28+
3229
@classmethod
3330
def get_oper(cls, op1, op2=None, *, reversed: bool = False):
3431
"""Returns pop sequence for 16 bits operands
@@ -63,7 +60,7 @@ def get_oper(cls, op1, op2=None, *, reversed: bool = False):
6360
if indirect:
6461
output.append("ld hl, (%i)" % op)
6562
else:
66-
output.append("ld hl, %i" % int16(op))
63+
output.append("ld hl, %i" % cls.int16(op))
6764
else:
6865
if immediate:
6966
if indirect:
@@ -104,7 +101,7 @@ def get_oper(cls, op1, op2=None, *, reversed: bool = False):
104101
if indirect:
105102
output.append("ld de, (%i)" % op)
106103
else:
107-
output.append("ld de, %i" % int16(op))
104+
output.append("ld de, %i" % cls.int16(op))
108105
else:
109106
if immediate:
110107
output.append("ld de, %s" % op)
@@ -145,7 +142,7 @@ def add16(cls, ins: Quad) -> list[str]:
145142
op1, op2 = tuple(ins[2:])
146143
if _int_ops(op1, op2) is not None:
147144
op1, op2 = _int_ops(op1, op2)
148-
op2 = int16(op2)
145+
op2 = cls.int16(op2)
149146
output = Bits16.get_oper(op1)
150147

151148
if op2 == 0:
@@ -194,7 +191,7 @@ def sub16(cls, ins: Quad) -> list[str]:
194191
op1, op2 = tuple(ins[2:4])
195192

196193
if is_int(op2):
197-
op = int16(op2)
194+
op = cls.int16(op2)
198195
output = Bits16.get_oper(op1)
199196

200197
if op == 0:
@@ -302,7 +299,7 @@ def divu16(cls, ins: Quad) -> list[str]:
302299
return output
303300

304301
if is_int(op2):
305-
op = int16(op2)
302+
op = cls.int16(op2)
306303
output = Bits16.get_oper(op1)
307304

308305
if op2 == 0: # A * 0 = 0 * A = 0
@@ -361,7 +358,7 @@ def divi16(cls, ins: Quad) -> list[str]:
361358
return output
362359

363360
if is_int(op2):
364-
op = int16(op2)
361+
op = cls.int16(op2)
365362
output = Bits16.get_oper(op1)
366363

367364
if op == 1:
@@ -403,7 +400,7 @@ def modu16(cls, ins: Quad) -> list[str]:
403400
op1, op2 = tuple(ins[2:])
404401

405402
if is_int(op2):
406-
op2 = int16(op2)
403+
op2 = cls.int16(op2)
407404
output = Bits16.get_oper(op1)
408405

409406
if op2 == 1:
@@ -448,7 +445,7 @@ def modi16(cls, ins: Quad) -> list[str]:
448445
op1, op2 = tuple(ins[2:])
449446

450447
if is_int(op2):
451-
op2 = int16(op2)
448+
op2 = cls.int16(op2)
452449
output = Bits16.get_oper(op1)
453450

454451
if op2 == 1:
@@ -888,7 +885,7 @@ def shru16(cls, ins: Quad) -> list[str]:
888885
label2 = tmp_label()
889886

890887
if is_int(op2):
891-
op = int16(op2)
888+
op = cls.int16(op2)
892889
if op == 0:
893890
return []
894891

@@ -932,7 +929,7 @@ def shri16(cls, ins: Quad) -> list[str]:
932929
label2 = tmp_label()
933930

934931
if is_int(op2):
935-
op = int16(op2)
932+
op = cls.int16(op2)
936933
if op == 0:
937934
return []
938935

@@ -976,7 +973,7 @@ def shl16(cls, ins: Quad) -> list[str]:
976973
label2 = tmp_label()
977974

978975
if is_int(op2):
979-
op = int16(op2)
976+
op = cls.int16(op2)
980977
if op == 0:
981978
return []
982979

src/arch/z80/backend/_pload.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
# --------------------------------------------------------------
1111
from . import common
1212
from ._8bit import Bits8
13-
from ._16bit import Bits16, int16
13+
from ._16bit import Bits16
1414
from ._32bit import Bits32
1515
from ._f16 import Fixed16
1616
from ._float import Float
@@ -288,7 +288,7 @@ def _pstore16(ins: Quad) -> list[str]:
288288

289289
if indirect:
290290
if is_int(value):
291-
output.append("ld hl, %i" % int16(value))
291+
output.append("ld hl, %i" % Bits16.int16(value))
292292

293293
output.append("ld bc, %i" % i)
294294
output.append(runtime_call(RuntimeLabel.PISTORE16))
@@ -305,7 +305,7 @@ def _pstore16(ins: Quad) -> list[str]:
305305
output.append("add hl, bc")
306306

307307
if is_int(value):
308-
v = int16(value)
308+
v = Bits16.int16(value)
309309
output.append("ld (hl), %i" % (v & 0xFF))
310310
output.append("inc hl")
311311
output.append("ld (hl), %i" % (v >> 8))
@@ -317,7 +317,7 @@ def _pstore16(ins: Quad) -> list[str]:
317317
return output
318318

319319
if is_int(value):
320-
v = int16(value)
320+
v = Bits16.int16(value)
321321
output.append(f"ld ({common.IDX_REG}%+i), %i" % (i, v & 0xFF))
322322
output.append(f"ld ({common.IDX_REG}%+i), %i" % (i + 1, v >> 8))
323323
else:

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