Merge pull request #576 from boriel/bugfix/allow_brackets_for_16bit_regs

boriel · web-flow · commit 1a6aacc12e81 · 2021-10-14T00:01:09.000+02:00
fix: allow ld [NNNN], reg16
diff --git a/src/parsetab/tabs.dbm.bak b/src/parsetab/tabs.dbm.bak
@@ -1,4 +1,4 @@
 'zxbpp', (0, 76970)
-'asmparse', (77312, 268394)
-'zxnext_asmparse', (346112, 298411)
-'zxbparser', (644608, 704752)
+'asmparse', (77312, 268610)
+'zxnext_asmparse', (346112, 298625)
+'zxbparser', (645120, 704752)
diff --git a/src/parsetab/tabs.dbm.dat b/src/parsetab/tabs.dbm.dat
diff --git a/src/parsetab/tabs.dbm.dir b/src/parsetab/tabs.dbm.dir
@@ -1,4 +1,4 @@
 'zxbpp', (0, 76970)
-'asmparse', (77312, 268394)
-'zxnext_asmparse', (346112, 298411)
-'zxbparser', (644608, 704752)
+'asmparse', (77312, 268610)
+'zxnext_asmparse', (346112, 298625)
+'zxbparser', (645120, 704752)
diff --git a/src/zxbasm/asmparse.py b/src/zxbasm/asmparse.py
@@ -552,8 +552,8 @@ def p_LD_addr_reg(p):  # Load address,reg
     | LD pexpr COMMA reg16
     | LD pexpr COMMA SP
     | LD mem_indir COMMA A
-    | LD mem_indir reg16
-    | LD mem_indir SP
+    | LD mem_indir COMMA reg16
+    | LD mem_indir COMMA SP
     """
     p[0] = Asm(p.lineno(1), "LD (NN),%s" % p[4], p[2])
 
diff --git a/tests/functional/ld_hl16_bracket.asm b/tests/functional/ld_hl16_bracket.asm
@@ -0,0 +1,12 @@
+
+ld (0x1234), hl
+ld [0x1234], hl
+
+ld (0x1234), bc
+ld [0x1234], bc
+
+ld [0x1234], de
+ld (0x1234), de
+
+ld (0x1234), sp
+ld [0x1234], sp
diff --git a/tests/functional/ld_hl16_bracket.bin b/tests/functional/ld_hl16_bracket.bin
@@ -0,0 +1 @@
+"4"4�C4�C4�S4�S4�s4�s4
