From f77bb869526298c6c071c2f5eb873198780eb42c Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 26 May 2026 20:05:17 +0530 Subject: [PATCH 1/5] FROMLIST arm64: dts: qcom: kodiak: Add GEM_NOC interconnect for adreno SMMU On Kodiak platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-0-2a6d8ca30d63@oss.qualcomm.com/#t Signed-off-by: Bibek Kumar Patro --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index b2a785662b815..e23bc90d0eae7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3333,6 +3333,8 @@ power-domains = <&gpucc GPU_CC_CX_GDSC>; dma-coherent; + interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; gfx_0_tbu: tbu@3dd9000 { From aadf018b45668d597cfec34eb1f5def37a0fb362 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 26 May 2026 20:05:18 +0530 Subject: [PATCH 2/5] FROMLIST: arm64: dts: qcom: lemans: Add GEM_NOC interconnect for adreno SMMU On Lemans platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-0-2a6d8ca30d63@oss.qualcomm.com/#t Signed-off-by: Bibek Kumar Patro --- arch/arm64/boot/dts/qcom/lemans.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index eb577a92c4985..f661b45d42807 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4427,6 +4427,8 @@ , , ; + interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; serdes0: phy@8901000 { From e385daaaace063db5dbb515f2c6775314b049da1 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 26 May 2026 20:05:19 +0530 Subject: [PATCH 3/5] FROMLIST: arm64: dts: qcom: monaco: Add GEM_NOC interconnect for adreno SMMU On Monaco platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-0-2a6d8ca30d63@oss.qualcomm.com/#t Signed-off-by: Bibek Kumar Patro --- arch/arm64/boot/dts/qcom/monaco.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 6cf6791f1fbc0..4928d6ef969e8 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4977,6 +4977,8 @@ "gpu_cc_hub_aon_clk"; power-domains = <&gpucc GPU_CC_CX_GDSC>; dma-coherent; + interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; pmu@9091000 { From 910e433b2875a1fdc4a147496a502d402dbd94a1 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 26 May 2026 20:05:20 +0530 Subject: [PATCH 4/5] FROMLIST: arm64: dts: qcom: talos: Add GEM_NOC interconnect for adreno SMMU On Talos platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-0-2a6d8ca30d63@oss.qualcomm.com/#t Signed-off-by: Bibek Kumar Patro --- arch/arm64/boot/dts/qcom/talos.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index dcbacbde54a3d..d344b207b4d38 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -2133,6 +2133,8 @@ "iface"; power-domains = <&gpucc CX_GDSC>; dma-coherent; + interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; stm@6002000 { From 2be7e4549878511975dda86590e0577938977e5e Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Sat, 30 May 2026 19:27:06 +0530 Subject: [PATCH 5/5] [DEBUG]: iommu/arm-smmu: Track s2cr values in arm-smmu QCOM implementation Debug patch to trakc the reads and writes from arm-smmu's s2cr implementation. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 156e9d89b885d..65a2b480cc93d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -541,6 +541,15 @@ static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) u32 type = s2cr->type; u32 reg; + dev_info(smmu->dev, + "write_s2cr[%d]: smmu_base=0x%llx orig type=%u cbndx=%u privcfg=%u%s\n", + idx, (u64)smmu->ioaddr, type, cbndx, s2cr->privcfg, + smmu->smrs && smmu->smrs[idx].valid ? + " (SMR valid)" : ""); + if (smmu->smrs && smmu->smrs[idx].valid) + dev_err(smmu->dev, "write_s2cr[%d]: SMR id=0x%x mask=0x%x\n", + idx, smmu->smrs[idx].id, smmu->smrs[idx].mask); + if (qsmmu->bypass_quirk) { if (type == S2CR_TYPE_BYPASS) { /* @@ -551,6 +560,9 @@ static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) */ type = S2CR_TYPE_TRANS; cbndx = qsmmu->bypass_cbndx; + dev_info(smmu->dev, + "write_s2cr[%d]: bypass_quirk: BYPASS->TRANS cbndx=%u\n", + idx, cbndx); } else if (type == S2CR_TYPE_FAULT) { /* * Firmware with quirky S2CR handling will ignore FAULT @@ -559,13 +571,29 @@ static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) */ type = S2CR_TYPE_BYPASS; cbndx = 0xff; + dev_info(smmu->dev, + "write_s2cr[%d]: bypass_quirk: FAULT->BYPASS cbndx=0xff\n", + idx); } } reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) | FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) | FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); + + dev_err(smmu->dev, + "write_s2cr[%d]: off=0x%x phys=0x%llx val=0x%08x (type=%u cbndx=%u privcfg=%u)\n", + idx, ARM_SMMU_GR0_S2CR(idx), + (u64)smmu->ioaddr + ARM_SMMU_GR0_S2CR(idx), + reg, type, cbndx, s2cr->privcfg); + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); + + dev_err(smmu->dev, + "read_s2cr[%d]: off=0x%x phys=0x%llx val=0x%08x (type=%u cbndx=%u privcfg=%u)\n", + idx, ARM_SMMU_GR0_S2CR(idx), + (u64)smmu->ioaddr + ARM_SMMU_GR0_S2CR(idx), + arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_S2CR(idx)), type, cbndx, s2cr->privcfg); } static int qcom_smmu_def_domain_type(struct device *dev)