diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index eb577a92c4985..f661b45d42807 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -4427,6 +4427,8 @@
 				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 		};
 
 		serdes0: phy@8901000 {
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 6cf6791f1fbc0..4928d6ef969e8 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -4977,6 +4977,8 @@
 				      "gpu_cc_hub_aon_clk";
 			power-domains = <&gpucc GPU_CC_CX_GDSC>;
 			dma-coherent;
+			interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 		};
 
 		pmu@9091000 {
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b2a785662b815..e23bc90d0eae7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3333,6 +3333,8 @@
 
 			power-domains = <&gpucc GPU_CC_CX_GDSC>;
 			dma-coherent;
+			interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 		};
 
 		gfx_0_tbu: tbu@3dd9000 {
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index dcbacbde54a3d..d344b207b4d38 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -2133,6 +2133,8 @@
 				      "iface";
 			power-domains = <&gpucc CX_GDSC>;
 			dma-coherent;
+			interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 		};
 
 		stm@6002000 {
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 156e9d89b885d..65a2b480cc93d 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -541,6 +541,15 @@ static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
 	u32 type = s2cr->type;
 	u32 reg;
 
+	dev_info(smmu->dev,
+		 "write_s2cr[%d]: smmu_base=0x%llx orig type=%u cbndx=%u privcfg=%u%s\n",
+		 idx, (u64)smmu->ioaddr, type, cbndx, s2cr->privcfg,
+		 smmu->smrs && smmu->smrs[idx].valid ?
+			" (SMR valid)" : "");
+	if (smmu->smrs && smmu->smrs[idx].valid)
+		dev_err(smmu->dev, "write_s2cr[%d]: SMR id=0x%x mask=0x%x\n",
+			 idx, smmu->smrs[idx].id, smmu->smrs[idx].mask);
+
 	if (qsmmu->bypass_quirk) {
 		if (type == S2CR_TYPE_BYPASS) {
 			/*
@@ -551,6 +560,9 @@ static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
 			 */
 			type = S2CR_TYPE_TRANS;
 			cbndx = qsmmu->bypass_cbndx;
+			dev_info(smmu->dev,
+				 "write_s2cr[%d]: bypass_quirk: BYPASS->TRANS cbndx=%u\n",
+				 idx, cbndx);
 		} else if (type == S2CR_TYPE_FAULT) {
 			/*
 			 * Firmware with quirky S2CR handling will ignore FAULT
@@ -559,13 +571,29 @@ static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
 			 */
 			type = S2CR_TYPE_BYPASS;
 			cbndx = 0xff;
+			dev_info(smmu->dev,
+				 "write_s2cr[%d]: bypass_quirk: FAULT->BYPASS cbndx=0xff\n",
+				 idx);
 		}
 	}
 
 	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
 	      FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
 	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
+
+	dev_err(smmu->dev,
+		 "write_s2cr[%d]: off=0x%x phys=0x%llx val=0x%08x (type=%u cbndx=%u privcfg=%u)\n",
+		 idx, ARM_SMMU_GR0_S2CR(idx),
+		 (u64)smmu->ioaddr + ARM_SMMU_GR0_S2CR(idx),
+		 reg, type, cbndx, s2cr->privcfg);
+
 	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
+
+	dev_err(smmu->dev,
+		 "read_s2cr[%d]: off=0x%x phys=0x%llx val=0x%08x (type=%u cbndx=%u privcfg=%u)\n",
+		 idx, ARM_SMMU_GR0_S2CR(idx),
+		 (u64)smmu->ioaddr + ARM_SMMU_GR0_S2CR(idx),
+		 arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_S2CR(idx)), type, cbndx, s2cr->privcfg);
 }
 
 static int qcom_smmu_def_domain_type(struct device *dev)