From c74fd7ce49e240a7aceb73a134522baef35a24e7 Mon Sep 17 00:00:00 2001
From: Timor Knudsen <timor.knudsen@amd.com>
Date: Sun, 26 Jul 2026 16:44:23 +0200
Subject: [PATCH 1/2] Fix CCM resource count in Yosys by adding resets

---
 rtl/ccm.sv | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/rtl/ccm.sv b/rtl/ccm.sv
index 583a799..46b3d33 100644
--- a/rtl/ccm.sv
+++ b/rtl/ccm.sv
@@ -489,6 +489,19 @@ module ccm
 
     if (rstn == 1'b0) begin
       pipe_2_tvalid   <= '0;
+      // Reset the accumulator registers. Should not be required, but Yosys optimizes away the DSPs without reset.
+      pipe_2_pixel0_r <= '0;
+      pipe_2_pixel0_g <= '0;
+      pipe_2_pixel0_b <= '0;
+      pipe_2_pixel1_r <= '0;
+      pipe_2_pixel1_g <= '0;
+      pipe_2_pixel1_b <= '0;
+      pipe_2_pixel2_r <= '0;
+      pipe_2_pixel2_g <= '0;
+      pipe_2_pixel2_b <= '0;
+      pipe_2_pixel3_r <= '0;
+      pipe_2_pixel3_g <= '0;
+      pipe_2_pixel3_b <= '0;
     end
   end
 

From 0b17c51dac5afc6ae8a109ecbecdb21c1cdff5d0 Mon Sep 17 00:00:00 2001
From: Timor Knudsen <timor.knudsen@amd.com>
Date: Sat, 29 Aug 2026 11:37:33 +0200
Subject: [PATCH 2/2] Build full sim and synth results on main

---
 .github/workflows/cicd.yml |  7 +++++--
 Makefile                   | 10 ++++++++--
 README.md                  |  1 +
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/cicd.yml b/.github/workflows/cicd.yml
index ac34a9a..a59dd3f 100644
--- a/.github/workflows/cicd.yml
+++ b/.github/workflows/cicd.yml
@@ -7,6 +7,9 @@ name: "Lint, simulate, synthesize, test and docs"
 
 on: [push]
 
+env:
+  SPEED: ${{ github.ref == 'refs/heads/main' && 'full' || 'simfast' }}
+
 jobs:
   lint:
     name: "Run pre-commit lint"
@@ -42,7 +45,7 @@ jobs:
       with:
         fetch-depth: 0
     - name: Simulation
-      run: make sim
+      run: make sim SIM_SPEED=${{ env.SPEED }}
     - name: Upload
       uses: actions/upload-artifact@v7
       with:
@@ -68,7 +71,7 @@ jobs:
       with:
         fetch-depth: 0
     - name: Synthesis
-      run: make synth
+      run: make synth SYNTH_SPEED=${{ env.SPEED }}
     - name: Upload
       uses: actions/upload-artifact@v7
       with:
diff --git a/Makefile b/Makefile
index 43ae9a5..c938e6f 100644
--- a/Makefile
+++ b/Makefile
@@ -8,16 +8,22 @@
 BUILD_DIR := build
 CACHE_DIR := .cache
 
+# Can be default, simfast, full, minimal
+SIM_SPEED ?= simfast
+
+# Can be default, simfast, full, minimal
+SYNTH_SPEED ?= simfast
+
 # Default target
 all: lint test synth sim
 
 # Run Verilator RTL test benches
 sim:
-	uv run pytest python/tb -m sim --speed simfast
+	uv run pytest python/tb -m sim --speed $(SIM_SPEED)
 
 # Run Yosys synthesis and generate utilization reports
 synth:
-	uv run pytest python/tb -m synth --speed simfast
+	uv run pytest python/tb -m synth --speed $(SYNTH_SPEED)
 
 # Run Python tests
 test:
diff --git a/README.md b/README.md
index 4a1c9ea..9c7d777 100644
--- a/README.md
+++ b/README.md
@@ -17,6 +17,7 @@ The Mini-ISP philosophy is summarized as follows:
 -	Acceptable image quality: Image quality must be acceptable for most applications and subjectively pleasant to the human eye.
 -	Open-source: All code and test cases are publicly available under a permissive license.
 
+For more information and resource usage statistics, please refer to [the documentation](https://amd.github.io/mini-isp).
 
 ## Table of Contents