@@ -77,8 +77,8 @@ static uint16_t mk_cmd_buf(uint8_t *pdst, uint8_t opcode, uint16_t addr)
7777 pdst [2 ] = ( (opcode >> 3 & 0x01 ) << 4 ) | ( (opcode >> 2 & 0x01 ) << 0 );
7878 pdst [3 ] = ( (opcode >> 1 & 0x01 ) << 4 ) | ( (opcode >> 0 & 0x01 ) << 0 );
7979
80- pdst [4 ] = ((uint8_t )(addr >> 8 ) & 0xFF );
81- pdst [5 ] = ((uint8_t )(addr >> 0 ) & 0xFF );
80+ pdst [4 ] = ((uint8_t )(addr >> 8 ) & 0xFF );
81+ pdst [5 ] = ((uint8_t )(addr >> 0 ) & 0xFF );
8282
8383 pdst [6 ] = 0 ;
8484
@@ -251,7 +251,6 @@ wiznet_pio_spi_handle_t wiznet_pio_spi_open(const wiznet_pio_spi_config_t *wizne
251251 wiznet_pio_spi_close (& state -> funcs );
252252 return NULL ;
253253 }
254-
255254 return & state -> funcs ;
256255}
257256
@@ -320,7 +319,7 @@ static void wiznet_pio_spi_frame_end(void) {
320319
321320#if CIRCUITPY_WIZNET_W6300
322321
323- bool wiznet_pio_spi_read_byte (uint8_t op_code , uint16_t AddrSel , uint8_t * rx , uint16_t rx_length )
322+ bool wiznet_pio_spi_read_byte (uint8_t op_code , uint16_t AddrSel , uint8_t * rx , uint16_t rx_length )
324323{
325324 uint8_t command_buf [8 ] = {0 ,};
326325 uint16_t command_len = mk_cmd_buf (command_buf , op_code , AddrSel );
@@ -342,7 +341,7 @@ bool wiznet_pio_spi_read_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *rx, ui
342341 pio_sm_restart (active_state -> pio , active_state -> pio_sm );
343342 pio_sm_clkdiv_restart (active_state -> pio , active_state -> pio_sm );
344343
345- pio_sm_put (active_state -> pio , active_state -> pio_sm , command_len * loop_cnt - 1 );
344+ pio_sm_put (active_state -> pio , active_state -> pio_sm , command_len * loop_cnt - 1 );
346345 pio_sm_exec (active_state -> pio , active_state -> pio_sm , pio_encode_out (pio_x , 32 ));
347346
348347 pio_sm_put (active_state -> pio , active_state -> pio_sm , rx_length - 1 );
@@ -357,7 +356,7 @@ bool wiznet_pio_spi_read_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *rx, ui
357356 channel_config_set_transfer_data_size (& out_config , DMA_SIZE_8 );
358357 channel_config_set_bswap (& out_config , true);
359358 channel_config_set_dreq (& out_config , pio_get_dreq (active_state -> pio , active_state -> pio_sm , true));
360- dma_channel_configure (active_state -> dma_out , & out_config , & active_state -> pio -> txf [active_state -> pio_sm ], command_buf , command_len , true);
359+ dma_channel_configure (active_state -> dma_out , & out_config , & active_state -> pio -> txf [active_state -> pio_sm ], command_buf , command_len , true);
361360
362361 dma_channel_config in_config = dma_channel_get_default_config (active_state -> dma_in );
363362 channel_config_set_transfer_data_size (& in_config , DMA_SIZE_8 );
@@ -378,30 +377,29 @@ bool wiznet_pio_spi_read_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *rx, ui
378377 __compiler_memory_barrier ();
379378
380379 pio_sm_set_enabled (active_state -> pio , active_state -> pio_sm , false);
381- pio_sm_exec (active_state -> pio , active_state -> pio_sm , pio_encode_mov (pio_pins , pio_null ));
382-
380+ pio_sm_exec (active_state -> pio , active_state -> pio_sm , pio_encode_mov (pio_pins , pio_null ));
383381 #endif
384382
385383 return true;
386384}
387385
388- bool wiznet_pio_spi_write_byte (uint8_t op_code , uint16_t AddrSel , const uint8_t * tx , uint16_t tx_length )
386+ bool wiznet_pio_spi_write_byte (uint8_t op_code , uint16_t AddrSel , const uint8_t * tx , uint16_t tx_length )
389387{
390388 uint8_t command_buf [8 ] = {0 ,};
391389 uint16_t command_len = mk_cmd_buf (command_buf , op_code , AddrSel );
392390 uint32_t loop_cnt = 0 ;
393391 tx_length = tx_length + command_len ;
394-
392+
395393 pio_sm_set_enabled (active_state -> pio , active_state -> pio_sm , false);
396394 pio_sm_set_wrap (active_state -> pio , active_state -> pio_sm , active_state -> pio_offset , active_state -> pio_offset + WIZNET_PIO_SPI_OFFSET_WRITE_BITS_END - 1 );
397395 pio_sm_clear_fifos (active_state -> pio , active_state -> pio_sm );
398-
396+
399397 loop_cnt = 2 ;
400398 pio_sm_set_pindirs_with_mask (active_state -> pio ,
401399 active_state -> pio_sm ,
402400 (1u << active_state -> spi_config -> data_io0_pin ) | (1u << active_state -> spi_config -> data_io1_pin ) | (1u << active_state -> spi_config -> data_io2_pin ) | (1u << active_state -> spi_config -> data_io3_pin ),
403401 (1u << active_state -> spi_config -> data_io0_pin ) | (1u << active_state -> spi_config -> data_io1_pin ) | (1u << active_state -> spi_config -> data_io2_pin ) | (1u << active_state -> spi_config -> data_io3_pin ));
404-
402+
405403
406404
407405 pio_sm_restart (active_state -> pio , active_state -> pio_sm );
@@ -419,14 +417,14 @@ bool wiznet_pio_spi_write_byte(uint8_t op_code, uint16_t AddrSel, const uint8_t
419417 channel_config_set_transfer_data_size (& out_config , DMA_SIZE_8 );
420418 channel_config_set_bswap (& out_config , true);
421419 channel_config_set_dreq (& out_config , pio_get_dreq (active_state -> pio , active_state -> pio_sm , true));
422-
420+
423421 pio_sm_set_enabled (active_state -> pio , active_state -> pio_sm , true);
424-
422+
425423 dma_channel_configure (active_state -> dma_out , & out_config , & active_state -> pio -> txf [active_state -> pio_sm ], command_buf , command_len , true);
426424 dma_channel_wait_for_finish_blocking (active_state -> dma_out );
427425 dma_channel_configure (active_state -> dma_out , & out_config , & active_state -> pio -> txf [active_state -> pio_sm ], tx , tx_length - command_len , true);
428426 dma_channel_wait_for_finish_blocking (active_state -> dma_out );
429-
427+
430428 const uint32_t fdebug_tx_stall = 1u << (PIO_FDEBUG_TXSTALL_LSB + active_state -> pio_sm );
431429 active_state -> pio -> fdebug = fdebug_tx_stall ;
432430 // pio_sm_set_enabled(active_state->pio, active_state->pio_sm, true);
@@ -441,8 +439,7 @@ bool wiznet_pio_spi_write_byte(uint8_t op_code, uint16_t AddrSel, const uint8_t
441439
442440 pio_sm_set_consecutive_pindirs (active_state -> pio , active_state -> pio_sm , active_state -> spi_config -> data_io0_pin , 4 , false);
443441
444-
445- pio_sm_exec (active_state -> pio , active_state -> pio_sm , pio_encode_mov (pio_pins , pio_null ));
442+ pio_sm_exec (active_state -> pio , active_state -> pio_sm , pio_encode_mov (pio_pins , pio_null ));
446443 pio_sm_set_enabled (active_state -> pio , active_state -> pio_sm , false);
447444 #endif
448445
@@ -587,7 +584,6 @@ void wiznet_pio_spi_write_buffer(const uint8_t *pBuf, uint16_t len) {
587584 active_state -> spi_header_count = 0 ;
588585 assert (active_state -> spi_header_count == 0 );
589586 #else
590-
591587 if (!wiznet_pio_spi_transfer (active_state -> spi_header , WIZNET_PIO_SPI_HEADER_LEN , NULL , 0 )) {
592588 panic ("spi failed writing header" );
593589 }
@@ -597,10 +593,10 @@ void wiznet_pio_spi_write_buffer(const uint8_t *pBuf, uint16_t len) {
597593 if (!wiznet_pio_spi_transfer (pBuf , len , NULL , 0 )) {
598594 panic ("spi failed writing buffer" );
599595 }
600- #endif
596+ #endif
601597 }
602598 }
603- }
599+ }
604600
605601
606602static void wiznet_pio_spi_set_active (wiznet_pio_spi_handle_t handle ) {
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